1/*
2 * Copyright (c) 2013 ETH Zurich. All rights reserved.
3 *
4 * This file is distributed under the terms in the attached LICENSE file.
5 * If you do not find this file, copies can be found by writing to:
6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich,
7 * Attn: Systems Group.
8 */
9
10/*
11 * omap44xx_hsi_top.dev
12 *
13 * DESCRIPTION: 
14 *
15 * NOTE: This file has been automatically generated based on the
16 * XML files extracted from the TI RDT v1.0.0.4p Tool.
17 * Download from here: http://www.ti.com/product/omap4460
18 * This means that the file might not be optimal in terms of naming
19 * conventions for constants and registers (duplicated
20 * namespaces in register and device name etc.).
21 * Also, because of the underlying structure from the original XML
22 * it's possible that some constants appear multiple times (if they
23 * have slightly different descriptions for example).
24 *
25 * You want to clean that up before using the files for the first time!
26 */
27 
28device omap44xx_hsi_top msbfirst ( addr base ) "" {
29    
30    
31    register hsi_revision ro addr(base, 0x0) "IP Revision Identifier (X.Y.R)Used by software to track features, bugs, and compatibility" type(uint32);
32    
33    register hsi_hwinfo ro addr(base, 0x4) "Information about the IP module's hardware configuration, i.e. typically the module's HDL generics (if any).Actual field format and encoding is decided by the module's designer." type(uint32);
34
35    constants midlemode_status width(2) "" {
36        MIDLEMODE_0 = 0 "force standby";
37        MIDLEMODE_1 = 1 "no standby";
38        MIDLEMODE_2 = 2 "smart standby";
39        MIDLEMODE_3 = 3 "smart standby wakeup";
40    };
41
42    constants sidlemode_status width(2) "" {
43        SIDLEMODE_0 = 0 "force idle";
44        SIDLEMODE_1 = 1 "no idle";
45        SIDLEMODE_2 = 2 "smart idle";
46        SIDLEMODE_3 = 3 "smart idle wakeup";
47    };
48
49    constants free_emu_status width(1) "" {
50        FREE_EMU_0 = 0 "module is sensitive to emulation suspend";
51        FREE_EMU_1 = 1 "module is not sensitive to emulation suspend";
52    };
53
54    constants softreset_status width(1) "" {
55        SOFTRESET_0 = 0 "no reset applied";
56        SOFTRESET_1 = 1 "Software reset applied";
57    };
58
59    constants autoidle_status width(1) "" {
60        AUTOIDLE_0 = 0 "interface clock is free-running";
61        AUTOIDLE_1 = 1 "automatic interface clock gating strategy, based on interconnect interface activity";
62    };
63    
64    register hsi_sysconfig addr(base, 0x10) "This register allows controlling various parameters of the L4_CFG interface" {
65        _ 18 mbz;
66        midlemode 2 rw type(midlemode_status) "Master interface power management, standby/wait control";
67        _ 7 mbz;
68        sidlemode 2 rw type(sidlemode_status) "Slave interface power management, request/acknowledgement control";
69        free_emu 1 rw type(free_emu_status) "Sensitivity to emulation (debug) suspend input signal";
70        softreset 1 rw type(softreset_status) "Software reset";
71        autoidle 1 rw type(autoidle_status) "Internal interface clock gating strategy";
72    };
73    
74    register hsi_sysstatus ro addr(base, 0x14) "Status on module, (reset done on bit 0, available for more status info)" type(uint32);
75    
76    register hsi_p1_m_irq0u_status addr(base, 0x408) "IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
77        _ 5 mbz;
78        hsr_wake 1 rw "Wake detected on any channel 8..15";
79        hsr_break 1 rw "Break detected on any channel 8..15";
80        hsr_error 1 rw "Error detected on any channel 8..15";
81        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15).";
82        hsr_available_chi 8 rw "Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
83        hst_accepted_chi 8 rw "Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
84    };
85    
86    register hsi_p1_m_irq0u_enable addr(base, 0x40C) "IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" {
87        _ 5 mbz;
88        hsr_wake 1 rw "Wake interrupt enable for all channels 8..15";
89        hsr_break 1 rw "Break interrupt enable for all channels 8..15";
90        hsr_error 1 rw "Error interrupt enable for all channels 8..15";
91        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
92        hsr_available_eni 8 rw "Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
93        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
94    };
95    
96    register hsi_p1_m_irq1u_status addr(base, 0x410) "IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
97        _ 5 mbz;
98        hsr_wake 1 rw "Wake detected on any channel 8..15";
99        hsr_break 1 rw "Break detected on any channel 8..15";
100        hsr_error 1 rw "Error detected on any channel 8..15";
101        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15).";
102        hsr_available_chi 8 rw "Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
103        hst_accepted_chi 8 rw "Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
104    };
105    
106    register hsi_p1_m_irq1u_enable addr(base, 0x414) "IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" {
107        _ 5 mbz;
108        hsr_wake 1 rw "Wake interrupt enable for all channels 8..15";
109        hsr_break 1 rw "Break interrupt enable for all channels 8..15";
110        hsr_error 1 rw "Error interrupt enable for all channels 8..15";
111        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
112        hsr_available_eni 8 rw "Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
113        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
114    };
115    
116    register hsi_p2_m_irq0u_status addr(base, 0x418) "IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
117        _ 5 mbz;
118        hsr_wake 1 rw "Wake detected on any channel 8..15";
119        hsr_break 1 rw "Break detected on any channel 8..15";
120        hsr_error 1 rw "Error detected on any channel 8..15";
121        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15).";
122        hsr_available_chi 8 rw "Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
123        hst_accepted_chi 8 rw "Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
124    };
125    
126    register hsi_p2_m_irq0u_enable addr(base, 0x41C) "IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" {
127        _ 5 mbz;
128        hsr_wake 1 rw "Wake interrupt enable for all channels 8..15";
129        hsr_break 1 rw "Break interrupt enable for all channels 8..15";
130        hsr_error 1 rw "Error interrupt enable for all channels 8..15";
131        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
132        hsr_available_eni 8 rw "Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
133        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
134    };
135    
136    register hsi_p2_m_irq1u_status addr(base, 0x420) "IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
137        _ 5 mbz;
138        hsr_wake 1 rw "Wake detected on any channel 8..15";
139        hsr_break 1 rw "Break detected on any channel 8..15";
140        hsr_error 1 rw "Error detected on any channel 8..15";
141        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15).";
142        hsr_available_chi 8 rw "Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
143        hst_accepted_chi 8 rw "Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
144    };
145    
146    register hsi_p2_m_irq1u_enable addr(base, 0x424) "IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" {
147        _ 5 mbz;
148        hsr_wake 1 rw "Wake interrupt enable for all channels 8..15";
149        hsr_break 1 rw "Break interrupt enable for all channels 8..15";
150        hsr_error 1 rw "Error interrupt enable for all channels 8..15";
151        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
152        hsr_available_eni 8 rw "Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
153        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
154    };
155    
156    register hsi_p1_d_irq0u_status addr(base, 0x430) "IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
157        _ 5 mbz;
158        hsr_wake 1 rw "Wake detected on any channel 8..15";
159        hsr_break 1 rw "Break detected on any channel 8..15";
160        hsr_error 1 rw "Error on any channel 8..15";
161        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
162        hsr_available_chi 8 rw "Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
163        hst_accepted_chi 8 rw "Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
164    };
165    
166    register hsi_p1_d_irq0u_enable addr(base, 0x434) "IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" {
167        _ 5 mbz;
168        hsr_wake 1 rw "Wake interrupt enable for channel 8..15";
169        hsr_break 1 rw "Break interrupt enable for channel 8..15";
170        hsr_error 1 rw "Error interrupt enable for channel 8..15";
171        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 8..15";
172        hsr_available_eni 8 rw "Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
173        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
174    };
175    
176    register hsi_p1_d_irq1u_status addr(base, 0x438) "IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
177        _ 5 mbz;
178        hsr_wake 1 rw "Wake detected on any channel 8..15";
179        hsr_break 1 rw "Break detected on any channel 8..15";
180        hsr_error 1 rw "Error on any channel 8..15";
181        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
182        hsr_available_chi 8 rw "Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
183        hst_accepted_chi 8 rw "Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
184    };
185    
186    register hsi_p1_d_irq1u_enable addr(base, 0x43C) "IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" {
187        _ 5 mbz;
188        hsr_wake 1 rw "Wake interrupt enable for channel 8..15";
189        hsr_break 1 rw "Break interrupt enable for channel 8..15";
190        hsr_error 1 rw "Error interrupt enable for channel 8..15";
191        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 8..15";
192        hsr_available_eni 8 rw "Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
193        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
194    };
195    
196    register hsi_p2_d_irq0u_status addr(base, 0x440) "IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
197        _ 5 mbz;
198        hsr_wake 1 rw "Wake detected on any channel 8..15";
199        hsr_break 1 rw "Break detected on any channel 8..15";
200        hsr_error 1 rw "Error on any channel 8..15";
201        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
202        hsr_available_chi 8 rw "Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
203        hst_accepted_chi 8 rw "Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
204    };
205    
206    register hsi_p2_d_irq0u_enable addr(base, 0x444) "IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" {
207        _ 5 mbz;
208        hsr_wake 1 rw "Wake interrupt enable for channel 8..15";
209        hsr_break 1 rw "Break interrupt enable for channel 8..15";
210        hsr_error 1 rw "Error interrupt enable for channel 8..15";
211        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 8..15";
212        hsr_available_eni 8 rw "Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
213        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
214    };
215    
216    register hsi_p2_d_irq1u_status addr(base, 0x448) "IRQ status register for FIFO (8..15) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
217        _ 5 mbz;
218        hsr_wake 1 rw "Wake detected on any channel 8..15";
219        hsr_break 1 rw "Break detected on any channel 8..15";
220        hsr_error 1 rw "Error on any channel 8..15";
221        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
222        hsr_available_chi 8 rw "Data received on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
223        hst_accepted_chi 8 rw "Data transmitted on channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
224    };
225    
226    register hsi_p2_d_irq1u_enable addr(base, 0x44C) "IRQ enable register for FIFO (8..15) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" {
227        _ 5 mbz;
228        hsr_wake 1 rw "Wake interrupt enable for channel 8..15";
229        hsr_break 1 rw "Break interrupt enable for channel 8..15";
230        hsr_error 1 rw "Error interrupt enable for channel 8..15";
231        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 8..15";
232        hsr_available_eni 8 rw "Data available interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
233        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 8..15 (LSB stands for channel 8 and MSB for channel 15)";
234    };
235    
236    register hsi_dma_m_irqstatus addr(base, 0x800) "This register collects status for all of the DMA events able to generate interrupt to MPU:Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
237        _ 16 mbz;
238        dma_chi 16 rw "Channel i status (LSB stands for channel 0 and MSB for channel 15)";
239    };
240    
241    register hsi_dma_m_irqenable addr(base, 0x804) "This register masks and unmasks DMA sources of interrupt to MPU:Write 0: event is maskedWrite 1: event is enabled" {
242        _ 16 mbz;
243        dma_en_chi 16 rw "Channel i (LSB stands for channel 0 and MSB for channel 15)";
244    };
245    
246    register hsi_p1_m_irq0_status addr(base, 0x808) "IRQ status register for FIFO (0..7) events and for port p break, wake and error events Events will signal interrupt for MPU line r (Mpuirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
247        _ 5 mbz;
248        hsr_wake 1 rw "Wake detected on Port p";
249        hsr_break 1 rw "Break detected on Port p";
250        hsr_error 1 rw "Error on Port p";
251        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
252        hsr_available_chi 8 rw "Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
253        hst_accepted_chi 8 rw "Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
254    };
255    
256    register hsi_p1_m_irq0_enable addr(base, 0x80C) "IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to MPU line r (Mpuirq_r).Write 0: event is maskedWrite 1: event is enabled" {
257        _ 5 mbz;
258        hsr_wake 1 rw "Wake interrupt enable for Port p";
259        hsr_break 1 rw "Break interrupt enable for Port p";
260        hsr_error 1 rw "Error interrupt enable for Port p";
261        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
262        hsr_available_eni 8 rw "Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
263        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
264    };
265    
266    register hsi_p1_m_irq1_status addr(base, 0x810) "IRQ status register for FIFO (0..7) events and for port p break, wake and error events Events will signal interrupt for MPU line r (Mpuirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
267        _ 5 mbz;
268        hsr_wake 1 rw "Wake detected on Port p";
269        hsr_break 1 rw "Break detected on Port p";
270        hsr_error 1 rw "Error on Port p";
271        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
272        hsr_available_chi 8 rw "Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
273        hst_accepted_chi 8 rw "Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
274    };
275    
276    register hsi_p1_m_irq1_enable addr(base, 0x814) "IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to MPU line r (Mpuirq_r).Write 0: event is maskedWrite 1: event is enabled" {
277        _ 5 mbz;
278        hsr_wake 1 rw "Wake interrupt enable for Port p";
279        hsr_break 1 rw "Break interrupt enable for Port p";
280        hsr_error 1 rw "Error interrupt enable for Port p";
281        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
282        hsr_available_eni 8 rw "Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
283        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
284    };
285    
286    register hsi_p2_m_irq0_status addr(base, 0x818) "IRQ status register for FIFO (0..7) events and for port p break, wake and error events Events will signal interrupt for MPU line r (Mpuirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
287        _ 5 mbz;
288        hsr_wake 1 rw "Wake detected on Port p";
289        hsr_break 1 rw "Break detected on Port p";
290        hsr_error 1 rw "Error on Port p";
291        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
292        hsr_available_chi 8 rw "Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
293        hst_accepted_chi 8 rw "Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
294    };
295    
296    register hsi_p2_m_irq0_enable addr(base, 0x81C) "IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to MPU line r (Mpuirq_r).Write 0: event is maskedWrite 1: event is enabled" {
297        _ 5 mbz;
298        hsr_wake 1 rw "Wake interrupt enable for Port p";
299        hsr_break 1 rw "Break interrupt enable for Port p";
300        hsr_error 1 rw "Error interrupt enable for Port p";
301        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
302        hsr_available_eni 8 rw "Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
303        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
304    };
305    
306    register hsi_p2_m_irq1_status addr(base, 0x820) "IRQ status register for FIFO (0..7) events and for port p break, wake and error events Events will signal interrupt for MPU line r (Mpuirq_r)Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
307        _ 5 mbz;
308        hsr_wake 1 rw "Wake detected on Port p";
309        hsr_break 1 rw "Break detected on Port p";
310        hsr_error 1 rw "Error on Port p";
311        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
312        hsr_available_chi 8 rw "Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
313        hst_accepted_chi 8 rw "Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
314    };
315    
316    register hsi_p2_m_irq1_enable addr(base, 0x824) "IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to MPU line r (Mpuirq_r).Write 0: event is maskedWrite 1: event is enabled" {
317        _ 5 mbz;
318        hsr_wake 1 rw "Wake interrupt enable for Port p";
319        hsr_break 1 rw "Break interrupt enable for Port p";
320        hsr_error 1 rw "Error interrupt enable for Port p";
321        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
322        hsr_available_eni 8 rw "Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
323        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
324    };
325    
326    register hsi_dma_d_irqstatus addr(base, 0x828) "IRQ status register for all DMA events. Events will generate interrupt for DSP.Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
327        _ 16 mbz;
328        dma_chi 16 rw "IRQ event happened on DMA channel i (LSB stands for channel 0 and MSB for channel 15)";
329    };
330    
331    register hsi_dma_d_irqenable addr(base, 0x82C) "IRQ enable register for all DMA events signaled to DSP..Write 0: event is maskedWrite 1: event is enabled" {
332        _ 16 mbz;
333        dma_en_chi 16 rw "Channel i (LSB stands for channel 0 and MSB for channel 15)";
334    };
335    
336    register hsi_p1_d_irq0_status addr(base, 0x830) "IRQ status register for FIFO (0..7) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r).Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
337        _ 5 mbz;
338        hsr_wake 1 rw "Wake detected on Port p";
339        hsr_break 1 rw "Break detected on Port p";
340        hsr_error 1 rw "Error on Port p";
341        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
342        hsr_available_chi 8 rw "Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
343        hst_accepted_chi 8 rw "Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
344    };
345    
346    register hsi_p1_d_irq0_enable addr(base, 0x834) "IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" {
347        _ 5 mbz;
348        hsr_wake 1 rw "Wake interrupt enable for Port p";
349        hsr_break 1 rw "Break interrupt enable for Port p";
350        hsr_error 1 rw "Error interrupt enable for Port p";
351        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
352        hsr_available_eni 8 rw "Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
353        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
354    };
355    
356    register hsi_p1_d_irq1_status addr(base, 0x838) "IRQ status register for FIFO (0..7) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r).Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
357        _ 5 mbz;
358        hsr_wake 1 rw "Wake detected on Port p";
359        hsr_break 1 rw "Break detected on Port p";
360        hsr_error 1 rw "Error on Port p";
361        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
362        hsr_available_chi 8 rw "Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
363        hst_accepted_chi 8 rw "Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
364    };
365    
366    register hsi_p1_d_irq1_enable addr(base, 0x83C) "IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" {
367        _ 5 mbz;
368        hsr_wake 1 rw "Wake interrupt enable for Port p";
369        hsr_break 1 rw "Break interrupt enable for Port p";
370        hsr_error 1 rw "Error interrupt enable for Port p";
371        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
372        hsr_available_eni 8 rw "Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
373        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
374    };
375    
376    register hsi_p2_d_irq0_status addr(base, 0x840) "IRQ status register for FIFO (0..7) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r).Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
377        _ 5 mbz;
378        hsr_wake 1 rw "Wake detected on Port p";
379        hsr_break 1 rw "Break detected on Port p";
380        hsr_error 1 rw "Error on Port p";
381        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
382        hsr_available_chi 8 rw "Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
383        hst_accepted_chi 8 rw "Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
384    };
385    
386    register hsi_p2_d_irq0_enable addr(base, 0x844) "IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" {
387        _ 5 mbz;
388        hsr_wake 1 rw "Wake interrupt enable for Port p";
389        hsr_break 1 rw "Break interrupt enable for Port p";
390        hsr_error 1 rw "Error interrupt enable for Port p";
391        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
392        hsr_available_eni 8 rw "Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
393        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
394    };
395    
396    register hsi_p2_d_irq1_status addr(base, 0x848) "IRQ status register for FIFO (0..7) events and for port p break, wake and error events. Events will signal interrupt for DSP line r (Dspirq_r).Read 0: event has not occurredRead 1: event has occurredWrite 0: bit stays unchangedWrite 1: bit gets reset to 0" {
397        _ 5 mbz;
398        hsr_wake 1 rw "Wake detected on Port p";
399        hsr_break 1 rw "Break detected on Port p";
400        hsr_error 1 rw "Error on Port p";
401        hsr_overrun_chi 8 rw "Data overrun in real time mode channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
402        hsr_available_chi 8 rw "Data received on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
403        hst_accepted_chi 8 rw "Data transmitted on channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
404    };
405    
406    register hsi_p2_d_irq1_enable addr(base, 0x84C) "IRQ enable register for FIFO (0..7) events and for port p break, wake and error events signaled to DSP line r (Dspirq_r)Write 0: event is maskedWrite 1: event is enabled" {
407        _ 5 mbz;
408        hsr_wake 1 rw "Wake interrupt enable for Port p";
409        hsr_break 1 rw "Break interrupt enable for Port p";
410        hsr_error 1 rw "Error interrupt enable for Port p";
411        hsr_overrun_eni 8 rw "Overrun interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
412        hsr_available_eni 8 rw "Data available interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
413        hst_accepted_eni 8 rw "Data accepted interrupt enable for channel 0..7 (LSB stands for channel 0 and MSB for channel 7)";
414    };
415    
416    register hsi_p1_wake addr(base, 0xC00) "Programmed wake state for each channel, in port 10x0: no channel wakeup on WAKE line requested0x1: channel wakeup requested" {
417        _ 16 mbz;
418        hsi_wake_chi 16 ro "Channel 0..15 (LSB stands for channel 0 and MSB for channel 15)";
419    };
420    
421    register hsi_p1_clear_wake addr(base, 0xC04) "Clear register for programmed wake state on port 1 HST_WAKE for each channel0x0: no effect0x1: clears bit" {
422        _ 16 mbz;
423        hsi_clear_wake_chi 16 wo "Channel 0..15 (LSB stands for channel 0 and MSB for channel 15)";
424    };
425
426    constants hsi_ready_lvl_status width(1) "" {
427        HSI_READY_LVL_0 = 0 "READY defaults to 0";
428        HSI_READY_LVL_1 = 1 "READY defaults to 1";
429    };
430
431    constants hsi_3_wires_status width(1) "" {
432        HSI_3_WIRES_0 = 0 "sets 4 wires behavior (wakeup with WAKE signal)";
433        HSI_3_WIRES_1 = 1 "sets 3 wire behavior (wakeup on line activity without WAKE signal)";
434    };
435
436    constants hsi_set_wake_chi_status width(16) "" {
437        HSI_SET_WAKE_CHI_0_w = 0 "no effect";
438        HSI_SET_WAKE_CHI_1_w = 1 "sets bit";
439    };
440    
441    register hsi_p1_set_wake addr(base, 0xC08) "Set function for wake state for each channel, in port 10x0: no effect0x1: sets bit" {
442        _ 14 mbz;
443        hsi_ready_lvl 1 rw type(hsi_ready_lvl_status) "READY default level";
444        hsi_3_wires 1 rw type(hsi_3_wires_status) "Sets 3 wires behavior";
445        hsi_set_wake_chi 16 wo type(hsi_set_wake_chi_status) "Sets programmed WAKE state for channel i";
446    };
447    
448    register hsi_p2_wake addr(base, 0xC10) "Programmed wake state for each channel, in port 20x0: no channel wakeup on WAKE line requested0x1: channel wakeup requested" {
449        _ 16 mbz;
450        hsi_wake_chi 16 ro "Channel 0..15 (LSB stands for channel 0 and MSB for channel 15)";
451    };
452    
453    register hsi_p2_clear_wake addr(base, 0xC14) "Clear register for programmed wake state on port 2 HST_WAKE for each channel0x0: no effect0x1: clears bit" {
454        _ 16 mbz;
455        hsi_clear_wake_chi 16 wo "Channel 0..15 (LSB stands for channel 0 and MSB for channel 15)";
456    };
457    
458    register hsi_p2_set_wake addr(base, 0xC18) "Set function for wake state for each channel, in port 20x0: no effect0x1: sets bit" {
459        _ 14 mbz;
460        hsi_ready_lvl 1 rw type(hsi_ready_lvl_status) "READY default level";
461        hsi_3_wires 1 rw type(hsi_3_wires_status) "Sets 3 wires behavior";
462        hsi_set_wake_chi 16 wo type(hsi_set_wake_chi_status) "Sets programmed WAKE state for channel i";
463    };
464
465    constants autogating_status width(1) "" {
466        AUTOGATING_0 = 0 "no DMA clock control";
467        AUTOGATING_1 = 1 "DMA clock control";
468    };
469
470    constants switch_off_status width(1) "" {
471        SWITCH_OFF_0 = 0 "DMA Clock released";
472        SWITCH_OFF_1 = 1 "DMA Clock cutoff";
473    };
474    
475    register dma_gcr addr(base, 0x1100) "Global Control Register: suspend and clock gating" {
476        _ 28 mbz;
477        autogating 1 rw type(autogating_status) "DMA clock autogating enable";
478        _ 2 mbz;
479        switch_off 1 rw type(switch_off_status) "DMA global clock control";
480    };
481
482    constants swreset_status width(1) "" {
483        SWRESET_1 = 1 "writing 1 resets the DMA. It is automatically reset to 0 by hardware once software reset is done";
484    };
485    
486    register dma_grst addr(base, 0x1200) "DMA software reset control register" {
487        _ 31 mbz;
488        swreset 1 rw type(swreset_status) "DMA sw reset control bit";
489    };
490};