1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_dmm.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_dmm msbfirst ( addr base ) "" { 29 30 31 register dmm_revision ro addr(base, 0x0) "DMM Revision Number" type(uint32); 32 33 register dmm_hwinfo addr(base, 0x4) "DMM hardware configuration" { 34 _ 12 mbz; 35 robin_cnt 4 ro "Number of ROBIN in the DMM"; 36 _ 4 mbz; 37 ella_cnt 4 ro "Number of ELLA in the DMM"; 38 _ 4 mbz; 39 tiler_cnt 4 ro "Number of TILER in the DMM"; 40 }; 41 42 register dmm_lisa_hwinfo addr(base, 0x8) "DMM hardware configuration for LISA" { 43 _ 20 mbz; 44 sdrc_cnt 4 ro "Number of attached SDRAM controllers"; 45 _ 3 mbz; 46 section_cnt 5 ro "Number of DMM sections"; 47 }; 48 49 constants idle_mode_status width(2) "" { 50 IDLE_MODE_0 = 0 "Force-idle mode: local target's idle state follows (acknowledges) the system's idle requests unconditionally, that is, regardless of the IP module's internal requirements. Backup mode, for debug only."; 51 IDLE_MODE_1 = 1 "No-idle mode: local target never enters idle state. Backup mode, for debug only"; 52 IDLE_MODE_3 = 3 "Reserved"; 53 IDLE_MODE_2 = 2 "Smart-idle mode: local target's idle state eventually follows (acknowledges) the system's idle requests, depending on the IP module's internal requirements. IP module shall not generate (IRQ- or DMA-request-related) wake-up events."; 54 }; 55 56 register dmm_sysconfig addr(base, 0x10) "DMM clock management configuration" { 57 _ 28 mbz; 58 idle_mode 2 rw type(idle_mode_status) "Configuration of the local target state management mode."; 59 _ 2 mbz; 60 }; 61 62 constants lock_status width(1) "" { 63 LOCK_0_w = 0 "No effect (clear on reset only)"; 64 LOCK_0_r = 0 "unlocked"; 65 LOCK_1_r = 1 "locked"; 66 LOCK_1_w = 1 "Locking registers"; 67 }; 68 69 register dmm_lisa_lock addr(base, 0x1C) "DMM memory mapping lock" { 70 _ 31 mbz; 71 lock 1 rw type(lock_status) "DMM lock map"; 72 }; 73 74 constants sys_size_status width(3) "" { 75 SYS_SIZE_0 = 0 "16-MB section"; 76 SYS_SIZE_1 = 1 "32-MB section"; 77 SYS_SIZE_2 = 2 "64-MB section"; 78 SYS_SIZE_3 = 3 "128-MB section"; 79 SYS_SIZE_4 = 4 "256-MB section"; 80 SYS_SIZE_5 = 5 "512-MB section"; 81 SYS_SIZE_6 = 6 "1-GB section"; 82 SYS_SIZE_7 = 7 "2-GB section"; 83 }; 84 85 register dmm_lisa_map_i_0 addr(base, 0x40) "DMM memory mapping register" { 86 sys_addr 8 rw "DMM system section address MSB for view mapping i"; 87 _ 1 mbz; 88 sys_size 3 rw type(sys_size_status) "DMM system section size for view mapping i"; 89 sdrc_intl 2 rw "SDRAM controller interleaving mode 0x0: No interleaving 0x1: 128-byte interleaving 0x2: 256-byte interleaving 0x3: 512-byte interleaving The 128-/256-/512-byte interleaving applies only to nontiled regions. If accesses are made to tiled regions, interleaving is forced to 1kiB. SDRC_INTL is don't care if SDRC_MAP is not 0x3 (no interleaving)."; 90 sdrc_addrspc 2 rw "SDRAM controller address space for view mapping i"; 91 _ 6 mbz; 92 sdrc_map 2 rw "SDRAM controller mapping for view mapping i 0x0: Unmapped 0x1: Mapped on EMIF1 only (not interleaved) 0x2: Mapped on EMIF2 only (not interleaved) 0x3: Mapped on EMIF1 and EMIF2 (interleaved) To enable interleaving, SDRC_MAP must be 0x3 and SDRC_INTL must be a nonzero value."; 93 sdrc_addr 8 rw "SDRAM controller address MSB for view mapping i"; 94 }; 95 96 register dmm_lisa_map_i_1 addr(base, 0x44) "DMM memory mapping register" { 97 sys_addr 8 rw "DMM system section address MSB for view mapping i"; 98 _ 1 mbz; 99 sys_size 3 rw type(sys_size_status) "DMM system section size for view mapping i"; 100 sdrc_intl 2 rw "SDRAM controller interleaving mode 0x0: No interleaving 0x1: 128-byte interleaving 0x2: 256-byte interleaving 0x3: 512-byte interleaving The 128-/256-/512-byte interleaving applies only to nontiled regions. If accesses are made to tiled regions, interleaving is forced to 1kiB. SDRC_INTL is don't care if SDRC_MAP is not 0x3 (no interleaving)."; 101 sdrc_addrspc 2 rw "SDRAM controller address space for view mapping i"; 102 _ 6 mbz; 103 sdrc_map 2 rw "SDRAM controller mapping for view mapping i 0x0: Unmapped 0x1: Mapped on EMIF1 only (not interleaved) 0x2: Mapped on EMIF2 only (not interleaved) 0x3: Mapped on EMIF1 and EMIF2 (interleaved) To enable interleaving, SDRC_MAP must be 0x3 and SDRC_INTL must be a nonzero value."; 104 sdrc_addr 8 rw "SDRAM controller address MSB for view mapping i"; 105 }; 106 107 register dmm_lisa_map_i_2 addr(base, 0x48) "DMM memory mapping register" { 108 sys_addr 8 rw "DMM system section address MSB for view mapping i"; 109 _ 1 mbz; 110 sys_size 3 rw type(sys_size_status) "DMM system section size for view mapping i"; 111 sdrc_intl 2 rw "SDRAM controller interleaving mode 0x0: No interleaving 0x1: 128-byte interleaving 0x2: 256-byte interleaving 0x3: 512-byte interleaving The 128-/256-/512-byte interleaving applies only to nontiled regions. If accesses are made to tiled regions, interleaving is forced to 1kiB. SDRC_INTL is don't care if SDRC_MAP is not 0x3 (no interleaving)."; 112 sdrc_addrspc 2 rw "SDRAM controller address space for view mapping i"; 113 _ 6 mbz; 114 sdrc_map 2 rw "SDRAM controller mapping for view mapping i 0x0: Unmapped 0x1: Mapped on EMIF1 only (not interleaved) 0x2: Mapped on EMIF2 only (not interleaved) 0x3: Mapped on EMIF1 and EMIF2 (interleaved) To enable interleaving, SDRC_MAP must be 0x3 and SDRC_INTL must be a nonzero value."; 115 sdrc_addr 8 rw "SDRAM controller address MSB for view mapping i"; 116 }; 117 118 register dmm_lisa_map_i_3 addr(base, 0x4C) "DMM memory mapping register" { 119 sys_addr 8 rw "DMM system section address MSB for view mapping i"; 120 _ 1 mbz; 121 sys_size 3 rw type(sys_size_status) "DMM system section size for view mapping i"; 122 sdrc_intl 2 rw "SDRAM controller interleaving mode 0x0: No interleaving 0x1: 128-byte interleaving 0x2: 256-byte interleaving 0x3: 512-byte interleaving The 128-/256-/512-byte interleaving applies only to nontiled regions. If accesses are made to tiled regions, interleaving is forced to 1kiB. SDRC_INTL is don't care if SDRC_MAP is not 0x3 (no interleaving)."; 123 sdrc_addrspc 2 rw "SDRAM controller address space for view mapping i"; 124 _ 6 mbz; 125 sdrc_map 2 rw "SDRAM controller mapping for view mapping i 0x0: Unmapped 0x1: Mapped on EMIF1 only (not interleaved) 0x2: Mapped on EMIF2 only (not interleaved) 0x3: Mapped on EMIF1 and EMIF2 (interleaved) To enable interleaving, SDRC_MAP must be 0x3 and SDRC_INTL must be a nonzero value."; 126 sdrc_addr 8 rw "SDRAM controller address MSB for view mapping i"; 127 }; 128 129 constants or_cnt_status width(5) "" { 130 OR_CNT_1_r = 1 "One orientation entry"; 131 OR_CNT_2_r = 2 "Two orientation entries"; 132 OR_CNT_4_r = 4 "Four orientation entries"; 133 OR_CNT_8_r = 8 "Eight orientation entries"; 134 OR_CNT_16_r = 16 "Sixteen orientation entries"; 135 }; 136 137 register dmm_tiler_hwinfo addr(base, 0x208) "DMM hardware configuration for TILER" { 138 _ 27 mbz; 139 or_cnt 5 ro type(or_cnt_status) "Number of TILER orientation entries"; 140 }; 141 142 constants w7_status width(1) "" { 143 W7_0_w = 0 "OR7 field is unchanged"; 144 W7_1_w = 1 "OR7 field is updated"; 145 }; 146 147 constants w6_status width(1) "" { 148 W6_0_w = 0 "OR6 field is unchanged"; 149 W6_1_w = 1 "OR6 field is updated"; 150 }; 151 152 constants w5_status width(1) "" { 153 W5_0_w = 0 "OR5 field is unchanged"; 154 W5_1_w = 1 "OR5 field is updated"; 155 }; 156 157 constants w4_status width(1) "" { 158 W4_0_w = 0 "OR4 field is unchanged"; 159 W4_1_w = 1 "OR4 field is updated"; 160 }; 161 162 constants w3_status width(1) "" { 163 W3_0_w = 0 "OR3 field is unchanged"; 164 W3_1_w = 1 "OR3 field is updated"; 165 }; 166 167 constants w2_status width(1) "" { 168 W2_0_w = 0 "OR2 field is unchanged"; 169 W2_1_w = 1 "OR2 field is updated"; 170 }; 171 172 constants w1_status width(1) "" { 173 W1_0_w = 0 "OR1 field is unchanged"; 174 W1_1_w = 1 "OR1 field is updated"; 175 }; 176 177 constants w0_status width(1) "" { 178 W0_0_w = 0 "OR0 field is unchanged"; 179 W0_1_w = 1 "OR0 field is updated"; 180 }; 181 182 register dmm_tiler_or0 addr(base, 0x220) "DMM TILER orientation (initiators 0 to 7)" { 183 w7 1 rw type(w7_status) "Write-enable for OR7 bit field"; 184 or7 3 rw "Orientation for initiator 7"; 185 w6 1 rw type(w6_status) "Write-enable for OR6 bit field"; 186 or6 3 rw "Orientation for initiator 6"; 187 w5 1 rw type(w5_status) "Write-enable for OR5 bit field"; 188 or5 3 rw "Orientation for initiator 5"; 189 w4 1 rw type(w4_status) "Write-enable for OR4 bit field"; 190 or4 3 rw "Orientation for initiator 4"; 191 w3 1 rw type(w3_status) "Write-enable for OR3 bit field"; 192 or3 3 rw "Orientation for initiator 3"; 193 w2 1 rw type(w2_status) "Write-enable for OR2 bit field"; 194 or2 3 rw "Orientation for initiator 2"; 195 w1 1 rw type(w1_status) "Write-enable for OR1 bit field"; 196 or1 3 rw "Orientation for initiator 1"; 197 w0 1 rw type(w0_status) "Write-enable for OR0 bit field"; 198 or0 3 rw "Orientation for initiator 0"; 199 }; 200 201 constants w15_status width(1) "" { 202 W15_0_w = 0 "OR15 field is unchanged"; 203 W15_1_w = 1 "OR15 field is updated"; 204 }; 205 206 constants w14_status width(1) "" { 207 W14_0_w = 0 "OR14 field is unchanged"; 208 W14_1_w = 1 "OR14 field is updated"; 209 }; 210 211 constants w13_status width(1) "" { 212 W13_0_w = 0 "OR13 field is unchanged"; 213 W13_1_w = 1 "OR13 field is updated"; 214 }; 215 216 constants w12_status width(1) "" { 217 W12_0_w = 0 "OR12 field is unchanged"; 218 W12_1_w = 1 "OR12 field is updated"; 219 }; 220 221 constants w11_status width(1) "" { 222 W11_0_w = 0 "OR11 field is unchanged"; 223 W11_1_w = 1 "OR11 field is updated"; 224 }; 225 226 constants w10_status width(1) "" { 227 W10_0_w = 0 "OR10 field is unchanged"; 228 W10_1_w = 1 "OR10 field is updated"; 229 }; 230 231 constants w9_status width(1) "" { 232 W9_0_w = 0 "OR9 field is unchanged"; 233 W9_1_w = 1 "OR9 field is updated"; 234 }; 235 236 constants w8_status width(1) "" { 237 W8_0_w = 0 "OR8 field is unchanged"; 238 W8_1_w = 1 "OR8 field is updated"; 239 }; 240 241 register dmm_tiler_or1 addr(base, 0x224) "DMM TILER orientation (initiators 8 to 15)" { 242 w15 1 rw type(w15_status) "Write-enable for OR15 bit field"; 243 or15 3 rw "Orientation for initiator 15"; 244 w14 1 rw type(w14_status) "Write-enable for OR14 bit field"; 245 or14 3 rw "Orientation for initiator 14"; 246 w13 1 rw type(w13_status) "Write-enable for OR13 bit field"; 247 or13 3 rw "Orientation for initiator 13"; 248 w12 1 rw type(w12_status) "Write-enable for OR12 bit field"; 249 or12 3 rw "Orientation for initiator 12"; 250 w11 1 rw type(w11_status) "Write-enable for OR11 bit field"; 251 or11 3 rw "Orientation for initiator 11"; 252 w10 1 rw type(w10_status) "Write-enable for OR10 bit field"; 253 or10 3 rw "Orientation for initiator 10"; 254 w9 1 rw type(w9_status) "Write-enable for OR9 bit field"; 255 or9 3 rw "Orientation for initiator 9"; 256 w8 1 rw type(w8_status) "Write-enable for OR8 bit field"; 257 or8 3 rw "Orientation for initiator 8"; 258 }; 259 260 constants view_map_cnt_status width(4) "" { 261 VIEW_MAP_CNT_1_r = 1 "One view map"; 262 VIEW_MAP_CNT_2_r = 2 "Two view maps"; 263 VIEW_MAP_CNT_4_r = 4 "Four view maps"; 264 VIEW_MAP_CNT_8_r = 8 "Eight view maps"; 265 }; 266 267 constants view_cnt_status width(7) "" { 268 VIEW_CNT_1_r = 1 "One view entry"; 269 VIEW_CNT_2_r = 2 "Two view entries"; 270 VIEW_CNT_4_r = 4 "Four view entries"; 271 VIEW_CNT_8_r = 8 "Eight view entries"; 272 VIEW_CNT_16_r = 16 "Sixteen view entries"; 273 VIEW_CNT_32_r = 32 "Thirty-two view entries"; 274 VIEW_CNT_64_r = 64 "Sixty-four view entries"; 275 }; 276 277 register dmm_pat_hwinfo addr(base, 0x408) "DMM hardware configuration for PAT" { 278 _ 3 mbz; 279 engine_cnt 5 ro "Number of PAT refill engines"; 280 _ 3 mbz; 281 lut_cnt 5 ro "Number of PAT LUT for page-grained physical address translation"; 282 _ 4 mbz; 283 view_map_cnt 4 ro type(view_map_cnt_status) "Number of internal PAT view mappings."; 284 _ 1 mbz; 285 view_cnt 7 ro type(view_cnt_status) "Number of PAT view entries"; 286 }; 287 288 constants cont_hght_status width(3) "" { 289 CONT_HGHT_1_r = 1 "Container height of 32 pages"; 290 CONT_HGHT_2_r = 2 "Container height of 64 pages"; 291 CONT_HGHT_4_r = 4 "Container height of 128 pages"; 292 }; 293 294 constants cont_wdth_status width(4) "" { 295 CONT_WDTH_2_r = 2 "Container width of 64 pages"; 296 CONT_WDTH_4_r = 4 "Container width of 128 pages"; 297 CONT_WDTH_8_r = 8 "Container width of 256 pages"; 298 }; 299 300 constants addr_range_status width(6) "" { 301 ADDR_RANGE_1_r = 1 "128-MB range"; 302 ADDR_RANGE_2_r = 2 "256-MB range"; 303 ADDR_RANGE_4_r = 4 "512-MB range"; 304 ADDR_RANGE_8_r = 8 "1-GB range"; 305 ADDR_RANGE_16_r = 16 "2-GB range"; 306 ADDR_RANGE_32_r = 32 "4-GB range"; 307 }; 308 309 constants page_sz_status width(5) "" { 310 PAGE_SZ_1_r = 1 "4-KB page"; 311 PAGE_SZ_4_r = 4 "16-KB page"; 312 PAGE_SZ_16_r = 16 "64-KB page"; 313 }; 314 315 register dmm_pat_geometry addr(base, 0x40C) "PAT geometry-related settings" { 316 _ 5 mbz; 317 cont_hght 3 ro type(cont_hght_status) "Container height in pages"; 318 _ 4 mbz; 319 cont_wdth 4 ro type(cont_wdth_status) "Container width in pages"; 320 _ 2 mbz; 321 addr_range 6 ro type(addr_range_status) "PAT output physical address range"; 322 _ 3 mbz; 323 page_sz 5 ro type(page_sz_status) "Page size in 4-KB granularity"; 324 }; 325 326 constants mode3_status width(1) "" { 327 MODE3_0 = 0 "Normal mode"; 328 MODE3_1 = 1 "Direct LUT access"; 329 }; 330 331 register dmm_pat_config addr(base, 0x410) "This is the PAT configuration register aimed at defining the major PAT configuration of each refill engine." { 332 _ 28 mbz; 333 mode3 1 rw type(mode3_status) "Mode of refill engine 3"; 334 mode2 1 rw type(mode3_status) "Mode of refill engine 2"; 335 mode1 1 rw type(mode3_status) "Mode of refill engine 1"; 336 mode0 1 rw type(mode3_status) "Mode of refill engine 0"; 337 }; 338 339 constants w7_status1 width(1) "" { 340 W7_0_w_1 = 0 "V7 field is unchanged"; 341 W7_1_w_1 = 1 "V7 field is updated"; 342 }; 343 344 constants w6_status1 width(1) "" { 345 W6_0_w_1 = 0 "V6 field is unchanged"; 346 W6_1_w_1 = 1 "V6 field is updated"; 347 }; 348 349 constants w5_status1 width(1) "" { 350 W5_0_w_1 = 0 "V5 field is unchanged"; 351 W5_1_w_1 = 1 "V5 field is updated"; 352 }; 353 354 constants w4_status1 width(1) "" { 355 W4_0_w_1 = 0 "V4 field is unchanged"; 356 W4_1_w_1 = 1 "V4 field is updated"; 357 }; 358 359 constants w3_status1 width(1) "" { 360 W3_0_w_1 = 0 "V3 field is unchanged"; 361 W3_1_w_1 = 1 "V3 field is updated"; 362 }; 363 364 constants w2_status1 width(1) "" { 365 W2_0_w_1 = 0 "V2 field is unchanged"; 366 W2_1_w_1 = 1 "V2 field is updated"; 367 }; 368 369 constants w1_status1 width(1) "" { 370 W1_0_w_1 = 0 "V1 field is unchanged"; 371 W1_1_w_1 = 1 "V1 field is updated"; 372 }; 373 374 constants w0_status1 width(1) "" { 375 W0_0_w_1 = 0 "V0 field is unchanged"; 376 W0_1_w_1 = 1 "V0 field is updated"; 377 }; 378 379 register dmm_pat_view0 addr(base, 0x420) "DMM PAT View register (initiators 0 to 7)" { 380 w7 1 rw type(w7_status1) "Write-enable for V7 bit field"; 381 _ 1 mbz; 382 v7 2 rw "PAT view for initiator 7"; 383 w6 1 rw type(w6_status1) "Write-enable for V6 bit field"; 384 _ 1 mbz; 385 v6 2 rw "PAT view for initiator 6"; 386 w5 1 rw type(w5_status1) "Write-enable for V5 bit field"; 387 _ 1 mbz; 388 v5 2 rw "PAT view for initiator 5"; 389 w4 1 rw type(w4_status1) "Write-enable for V4 bit field"; 390 _ 1 mbz; 391 v4 2 rw "PAT view for initiator 4"; 392 w3 1 rw type(w3_status1) "Write-enable for V3 bit field"; 393 _ 1 mbz; 394 v3 2 rw "PAT view for initiator 3"; 395 w2 1 rw type(w2_status1) "Write-enable for V2 bit field"; 396 _ 1 mbz; 397 v2 2 rw "PAT view for initiator 2"; 398 w1 1 rw type(w1_status1) "Write-enable for V1 bit field"; 399 _ 1 mbz; 400 v1 2 rw "PAT view for initiator 1"; 401 w0 1 rw type(w0_status1) "Write-enable for V0 bit field"; 402 _ 1 mbz; 403 v0 2 rw "PAT view for initiator 0"; 404 }; 405 406 constants w15_status1 width(1) "" { 407 W15_0_w_1 = 0 "V15 field is unchanged"; 408 W15_1_w_1 = 1 "V15 field is updated"; 409 }; 410 411 constants w14_status1 width(1) "" { 412 W14_0_w_1 = 0 "V14 field is unchanged"; 413 W14_1_w_1 = 1 "V14 field is updated"; 414 }; 415 416 constants w13_status1 width(1) "" { 417 W13_0_w_1 = 0 "V13 field is unchanged"; 418 W13_1_w_1 = 1 "V13 field is updated"; 419 }; 420 421 constants w12_status1 width(1) "" { 422 W12_0_w_1 = 0 "V12 field is unchanged"; 423 W12_1_w_1 = 1 "V12 field is updated"; 424 }; 425 426 constants w11_status1 width(1) "" { 427 W11_0_w_1 = 0 "V11 field is unchanged"; 428 W11_1_w_1 = 1 "V11 field is updated"; 429 }; 430 431 constants w10_status1 width(1) "" { 432 W10_0_w_1 = 0 "V10 field is unchanged"; 433 W10_1_w_1 = 1 "V10 field is updated"; 434 }; 435 436 constants w9_status1 width(1) "" { 437 W9_0_w_1 = 0 "V9 field is unchanged"; 438 W9_1_w_1 = 1 "V9 field is updated"; 439 }; 440 441 constants w8_status1 width(1) "" { 442 W8_0_w_1 = 0 "V8 field is unchanged"; 443 W8_1_w_1 = 1 "V8 field is updated"; 444 }; 445 446 register dmm_pat_view1 addr(base, 0x424) "DMM PAT view register (initiators 8 to 15)" { 447 w15 1 rw type(w15_status1) "Write-enable for V15 bit field"; 448 _ 1 mbz; 449 v15 2 rw "PAT view for initiator 15"; 450 w14 1 rw type(w14_status1) "Write-enable for V14 bit field"; 451 _ 1 mbz; 452 v14 2 rw "PAT view for initiator 14"; 453 w13 1 rw type(w13_status1) "Write-enable for V13 bit field"; 454 _ 1 mbz; 455 v13 2 rw "PAT view for initiator 13"; 456 w12 1 rw type(w12_status1) "Write-enable for V12 bit field"; 457 _ 1 mbz; 458 v12 2 rw "PAT view for initiator 12"; 459 w11 1 rw type(w11_status1) "Write-enable for V11 bit field"; 460 _ 1 mbz; 461 v11 2 rw "PAT view for initiator 11"; 462 w10 1 rw type(w10_status1) "Write-enable for V10 bit field"; 463 _ 1 mbz; 464 v10 2 rw "PAT view for initiator 10"; 465 w9 1 rw type(w9_status1) "Write-enable for V9 bit field"; 466 _ 1 mbz; 467 v9 2 rw "PAT view for initiator 9"; 468 w8 1 rw type(w8_status1) "Write-enable for V8 bit field"; 469 _ 1 mbz; 470 v8 2 rw "PAT view for initiator 8"; 471 }; 472 473 constants access_page_status width(1) "" { 474 ACCESS_PAGE_0 = 0 "Direct access, container base address given in CONT_PAGE"; 475 ACCESS_PAGE_1 = 1 "Indirect access through the LUT indexed by CONT_PAGE"; 476 }; 477 478 constants access_32_status width(1) "" { 479 ACCESS_32_0 = 0 "Direct access, container base address given in CONT_32"; 480 ACCESS_32_1 = 1 "Indirect access through the LUT indexed by CONT_32"; 481 }; 482 483 constants access_16_status width(1) "" { 484 ACCESS_16_0 = 0 "Direct access, container base address given in CONT_16"; 485 ACCESS_16_1 = 1 "Indirect access through the LUT indexed by CONT_16"; 486 }; 487 488 constants access_8_status width(1) "" { 489 ACCESS_8_0 = 0 "Direct access, container base address given in CONT_8"; 490 ACCESS_8_1 = 1 "Indirect access through the LUT indexed by CONT_8"; 491 }; 492 493 register dmm_pat_view_map_i_0 addr(base, 0x440) "PAT view mapping register" { 494 access_page 1 rw type(access_page_status) "Kind of access for this page mode container in view mapping i"; 495 _ 3 mbz; 496 cont_page 4 rw "Container for page mode in view mapping i"; 497 access_32 1 rw type(access_32_status) "Kind of access for this 32-bit mode container in view mapping i"; 498 _ 3 mbz; 499 cont_32 4 rw "Container for 32-bit mode in view mapping i"; 500 access_16 1 rw type(access_16_status) "Kind of access for this 16-bit mode container in view mapping i"; 501 _ 3 mbz; 502 cont_16 4 rw "Container for 16-bit mode in view mapping i"; 503 access_8 1 rw type(access_8_status) "Kind of access for this 8-bit mode container in view mapping i"; 504 _ 3 mbz; 505 cont_8 4 rw "Container for 8-bit mode in view mapping i"; 506 }; 507 508 register dmm_pat_view_map_i_1 addr(base, 0x444) "PAT view mapping register" { 509 access_page 1 rw type(access_page_status) "Kind of access for this page mode container in view mapping i"; 510 _ 3 mbz; 511 cont_page 4 rw "Container for page mode in view mapping i"; 512 access_32 1 rw type(access_32_status) "Kind of access for this 32-bit mode container in view mapping i"; 513 _ 3 mbz; 514 cont_32 4 rw "Container for 32-bit mode in view mapping i"; 515 access_16 1 rw type(access_16_status) "Kind of access for this 16-bit mode container in view mapping i"; 516 _ 3 mbz; 517 cont_16 4 rw "Container for 16-bit mode in view mapping i"; 518 access_8 1 rw type(access_8_status) "Kind of access for this 8-bit mode container in view mapping i"; 519 _ 3 mbz; 520 cont_8 4 rw "Container for 8-bit mode in view mapping i"; 521 }; 522 523 register dmm_pat_view_map_i_2 addr(base, 0x448) "PAT view mapping register" { 524 access_page 1 rw type(access_page_status) "Kind of access for this page mode container in view mapping i"; 525 _ 3 mbz; 526 cont_page 4 rw "Container for page mode in view mapping i"; 527 access_32 1 rw type(access_32_status) "Kind of access for this 32-bit mode container in view mapping i"; 528 _ 3 mbz; 529 cont_32 4 rw "Container for 32-bit mode in view mapping i"; 530 access_16 1 rw type(access_16_status) "Kind of access for this 16-bit mode container in view mapping i"; 531 _ 3 mbz; 532 cont_16 4 rw "Container for 16-bit mode in view mapping i"; 533 access_8 1 rw type(access_8_status) "Kind of access for this 8-bit mode container in view mapping i"; 534 _ 3 mbz; 535 cont_8 4 rw "Container for 8-bit mode in view mapping i"; 536 }; 537 538 register dmm_pat_view_map_i_3 addr(base, 0x44C) "PAT view mapping register" { 539 access_page 1 rw type(access_page_status) "Kind of access for this page mode container in view mapping i"; 540 _ 3 mbz; 541 cont_page 4 rw "Container for page mode in view mapping i"; 542 access_32 1 rw type(access_32_status) "Kind of access for this 32-bit mode container in view mapping i"; 543 _ 3 mbz; 544 cont_32 4 rw "Container for 32-bit mode in view mapping i"; 545 access_16 1 rw type(access_16_status) "Kind of access for this 16-bit mode container in view mapping i"; 546 _ 3 mbz; 547 cont_16 4 rw "Container for 16-bit mode in view mapping i"; 548 access_8 1 rw type(access_8_status) "Kind of access for this 8-bit mode container in view mapping i"; 549 _ 3 mbz; 550 cont_8 4 rw "Container for 8-bit mode in view mapping i"; 551 }; 552 553 register dmm_pat_view_map_base addr(base, 0x460) "Base address of all view mappings" { 554 base_addr 1 rw "MSB of the PAT view mapping base address"; 555 _ 31 mbz; 556 }; 557 558 constants err_lut_miss1_status width(1) "" { 559 ERR_LUT_MISS1_0_w = 0 "Keep current error event"; 560 ERR_LUT_MISS1_0_r = 0 "No such error event"; 561 ERR_LUT_MISS1_1_r = 1 "Error event happened"; 562 ERR_LUT_MISS1_1_w = 1 "Set error event"; 563 }; 564 565 constants fill_lst1_status width(1) "" { 566 FILL_LST1_0_w = 0 "Keep area 1 refill done event"; 567 FILL_LST1_0_r = 0 "Area 1 is yet-to-be refilled"; 568 FILL_LST1_1_r = 1 "Area 1 is refilled"; 569 FILL_LST1_1_w = 1 "Set area 1 refill done event"; 570 }; 571 572 constants fill_lst0_status width(1) "" { 573 FILL_LST0_0_w = 0 "Keep area 0 refill done event"; 574 FILL_LST0_0_r = 0 "Area 0 is yet-to-be refilled"; 575 FILL_LST0_1_r = 1 "Area 0 is refilled"; 576 FILL_LST0_1_w = 1 "Set area 0 refill done event"; 577 }; 578 579 register dmm_pat_irqstatus_raw addr(base, 0x480) "Per-event raw interrupt status vector. Raw status is set even if the related event is not enabled. Write 1 to set the (raw) status, mostly for debug. n = 0 for the first interrupt status raw register, n = 1 for the second interrupt status raw register." { 580 _ 16 mbz; 581 err_lut_miss1 1 rw type(err_lut_miss1_status) "Access to a yet-to-be-refilled area event in area 4.n+1"; 582 err_upd_data1 1 rw type(err_lut_miss1_status) "Data register update while refilling error event in area 4.n+1"; 583 err_upd_ctrl1 1 rw type(err_lut_miss1_status) "Control register update while refilling error event in area 4.n+1"; 584 err_upd_area1 1 rw type(err_lut_miss1_status) "Area register update while refilling error event in area 4.n+1"; 585 err_inv_data1 1 rw type(err_lut_miss1_status) "Invalid entry-table pointer error event in area 4.n+1"; 586 err_inv_dsc1 1 rw type(err_lut_miss1_status) "Invalid descriptor pointer error event in area 4.n+1"; 587 fill_lst1 1 rw type(fill_lst1_status) "End of refill event for the last descriptor in area 4.n+1"; 588 fill_dsc1 1 rw type(fill_lst1_status) "End of refill event for any descriptor in area 4.n+1"; 589 err_lut_miss0 1 rw type(err_lut_miss1_status) "Access to a yet-to-be-refilled area event in area 4.n"; 590 err_upd_data0 1 rw type(err_lut_miss1_status) "Data register update while refilling error event in area 4.n"; 591 err_upd_ctrl0 1 rw type(err_lut_miss1_status) "Control register update while refilling error event in area 4.n"; 592 err_upd_area0 1 rw type(err_lut_miss1_status) "Area register update while refilling error event in area 4.n"; 593 err_inv_data0 1 rw type(err_lut_miss1_status) "Invalid entry-table pointer error event in area 4.n"; 594 err_inv_dsc0 1 rw type(err_lut_miss1_status) "Invalid descriptor pointer error event in area 4.n"; 595 fill_lst0 1 rw type(fill_lst0_status) "End of refill event for the last descriptor in area 4.n"; 596 fill_dsc0 1 rw type(fill_lst0_status) "End of refill event for any descriptor in area 4.n"; 597 }; 598 599 constants err_lut_miss1_status1 width(1) "" { 600 ERR_LUT_MISS1_0_w_1 = 0 "Keep current maskable error event"; 601 ERR_LUT_MISS1_0_r_1 = 0 "No such error event or this event is masked"; 602 ERR_LUT_MISS1_1_r_1 = 1 "Error event happened"; 603 ERR_LUT_MISS1_1_w_1 = 1 "Clear this maskable error event"; 604 }; 605 606 constants fill_lst1_status1 width(1) "" { 607 FILL_LST1_0_w_1 = 0 "Keep current area refill done maskable event"; 608 FILL_LST1_0_r_1 = 0 "Current area is yet-to-be refilled or this event is masked"; 609 FILL_LST1_1_r_1 = 1 "Current area is refilled"; 610 FILL_LST1_1_w_1 = 1 "Clear current area refill done maskable event"; 611 }; 612 613 register dmm_pat_irqstatus addr(base, 0x490) "Per-event 'enabled' interrupt status vector. Enabled status is not set unless the event is enabled. Write 1 to clear the status after interrupt has been serviced (raw status gets cleared, that is, even if not enabled). n = 0 for the first interrupt status register, n = 1 for the second interrupt status register." { 614 _ 16 mbz; 615 err_lut_miss1 1 rw1c type(err_lut_miss1_status1) "Access to a yet-to-be-refilled area event in area 4.n+1"; 616 err_upd_data1 1 rw1c type(err_lut_miss1_status1) "Data register update while refilling error event in area 4.n+1"; 617 err_upd_ctrl1 1 rw1c type(err_lut_miss1_status1) "Control register update while refilling error event in area 4.n+1"; 618 err_upd_area1 1 rw1c type(err_lut_miss1_status1) "Area register update while refilling error event in area 4.n+1"; 619 err_inv_data1 1 rw1c type(err_lut_miss1_status1) "Invalid entry-table pointer error event in area 4.n+1"; 620 err_inv_dsc1 1 rw1c type(err_lut_miss1_status1) "Invalid descriptor pointer error event in area 4.n+1"; 621 fill_lst1 1 rw1c type(fill_lst1_status1) "End of refill event for the last descriptor in area 4.n+1"; 622 fill_dsc1 1 rw1c type(fill_lst1_status1) "End of refill event for any descriptor in area 4.n+1"; 623 err_lut_miss0 1 rw1c type(err_lut_miss1_status1) "Access to a yet-to-be-refilled area event in area 4.n"; 624 err_upd_data0 1 rw1c type(err_lut_miss1_status1) "Data register update while refilling error event in area 4.n"; 625 err_upd_ctrl0 1 rw1c type(err_lut_miss1_status1) "Control register update while refilling error event in area 4.n"; 626 err_upd_area0 1 rw1c type(err_lut_miss1_status1) "Area register update while refilling error event in area 4.n"; 627 err_inv_data0 1 rw1c type(err_lut_miss1_status1) "Invalid entry-table pointer error event in area 4.n"; 628 err_inv_dsc0 1 rw1c type(err_lut_miss1_status1) "Invalid descriptor pointer error event in area 4.n"; 629 fill_lst0 1 rw1c type(fill_lst1_status1) "End of refill event for the last descriptor in area 4.n"; 630 fill_dsc0 1 rw1c type(fill_lst1_status1) "End of refill event for any descriptor in area 4.n"; 631 }; 632 633 constants err_lut_miss1_status2 width(1) "" { 634 ERR_LUT_MISS1_0_w_2 = 0 "Keep current mask of this interrupt source"; 635 ERR_LUT_MISS1_0_r_2 = 0 "This interrupt source is disabled (masked)"; 636 ERR_LUT_MISS1_1_r_2 = 1 "This interrupt source is enabled (unmasked)"; 637 ERR_LUT_MISS1_1_w_2 = 1 "Enable (unmask) this interrupt source"; 638 }; 639 640 register dmm_pat_irqenable_set addr(base, 0x4A0) "Per-event interrupt enable bit vector. Write 1 to set (enable interrupt). Readout equal to corresponding _CLR register. n = 0 for the first interrupt enable set register, n = 1 for the second interrupt enable set register." { 641 _ 16 mbz; 642 err_lut_miss1 1 rw type(err_lut_miss1_status2) "Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n+1"; 643 err_upd_data1 1 rw type(err_lut_miss1_status2) "Unexpected data register update while refilling interrupt source mask for area 4.n+1"; 644 err_upd_ctrl1 1 rw type(err_lut_miss1_status2) "Unexpected control register update while refilling interrupt source mask for area 4.n+1"; 645 err_upd_area1 1 rw type(err_lut_miss1_status2) "Unexpected area register update while refilling interrupt source mask for area 4.n+1"; 646 err_inv_data1 1 rw type(err_lut_miss1_status2) "Invalid entry-table pointer interrupt source mask for area 4.n+1"; 647 err_inv_dsc1 1 rw type(err_lut_miss1_status2) "Invalid descriptor pointer interrupt source mask for area 4.n+1"; 648 fill_lst1 1 rw type(err_lut_miss1_status2) "End of refill interrupt source mask for the last descriptor in area 4.n+1"; 649 fill_dsc1 1 rw type(err_lut_miss1_status2) "End of refill interrupt source mask for any descriptor in area 4.n+1"; 650 err_lut_miss0 1 rw type(err_lut_miss1_status2) "Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n"; 651 err_upd_data0 1 rw type(err_lut_miss1_status2) "Unexpected data register update while refilling interrupt source mask for area 4.n"; 652 err_upd_ctrl0 1 rw type(err_lut_miss1_status2) "Unexpected control register update while refilling interrupt source mask for area 4.n"; 653 err_upd_area0 1 rw type(err_lut_miss1_status2) "Unexpected area register update while refilling interrupt source mask for area 4.n"; 654 err_inv_data0 1 rw type(err_lut_miss1_status2) "Invalid entry-table pointer interrupt source mask for area 4.n"; 655 err_inv_dsc0 1 rw type(err_lut_miss1_status2) "Invalid descriptor pointer interrupt source mask for area 4.n"; 656 fill_lst0 1 rw type(err_lut_miss1_status2) "End of refill interrupt source mask for the last descriptor in area 4.n"; 657 fill_dsc0 1 rw type(err_lut_miss1_status2) "End of refill interrupt source mask for any descriptor in area 4.n"; 658 }; 659 660 constants err_lut_miss1_status3 width(1) "" { 661 ERR_LUT_MISS1_0_w_3 = 0 "Keep current mask of this interrupt source"; 662 ERR_LUT_MISS1_0_r_3 = 0 "This interrupt source is disabled (masked)"; 663 ERR_LUT_MISS1_1_r_3 = 1 "This interrupt source is enabled (unmasked)"; 664 ERR_LUT_MISS1_1_w_3 = 1 "Disable (mask) this interrupt source"; 665 }; 666 667 register dmm_pat_irqenable_clr addr(base, 0x4B0) "Per-event interrupt enable bit vector. Write 1 to clear (disable interrupt). Readout equal to corresponding _SET register. n = 0 for the first interrupt enable clear register, n = 1 for the second interrupt enable clear register." { 668 _ 16 mbz; 669 err_lut_miss1 1 rw1c type(err_lut_miss1_status3) "Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n+1"; 670 err_upd_data1 1 rw1c type(err_lut_miss1_status3) "Unexpected data register update while refilling interrupt source mask for area 4.n+1"; 671 err_upd_ctrl1 1 rw1c type(err_lut_miss1_status3) "Unexpected control register update while refilling interrupt source mask for area 4.n+1"; 672 err_upd_area1 1 rw1c type(err_lut_miss1_status3) "Unexpected area register update while refilling interrupt source mask for area 4.n+1"; 673 err_inv_data1 1 rw1c type(err_lut_miss1_status3) "Invalid entry-table pointer interrupt source mask for area 4.n+1"; 674 err_inv_dsc1 1 rw1c type(err_lut_miss1_status3) "Invalid descriptor pointer interrupt source mask for area 4.n+1"; 675 fill_lst1 1 rw1c type(err_lut_miss1_status3) "End of refill interrupt source mask for the last descriptor in area 4.n+1"; 676 fill_dsc1 1 rw1c type(err_lut_miss1_status3) "End of refill interrupt source mask for any descriptor in area 4.n+1"; 677 err_lut_miss0 1 rw1c type(err_lut_miss1_status3) "Unexpected access to a yet-to-be-refilled area interrupt source mask for area 4.n"; 678 err_upd_data0 1 rw1c type(err_lut_miss1_status3) "Unexpected data register update while refilling interrupt source mask for area 4.n"; 679 err_upd_ctrl0 1 rw1c type(err_lut_miss1_status3) "Unexpected control register update while refilling interrupt source mask for area 4.n"; 680 err_upd_area0 1 rw1c type(err_lut_miss1_status3) "Unexpected area register update while refilling interrupt source mask for area 4.n"; 681 err_inv_data0 1 rw1c type(err_lut_miss1_status3) "Invalid entry-table pointer interrupt source mask for area 4.n"; 682 err_inv_dsc0 1 rw1c type(err_lut_miss1_status3) "Invalid descriptor pointer interrupt source mask for area 4.n"; 683 fill_lst0 1 rw1c type(err_lut_miss1_status3) "End of refill interrupt source mask for the last descriptor in area 4.n"; 684 fill_dsc0 1 rw1c type(err_lut_miss1_status3) "End of refill interrupt source mask for any descriptor in area 4.n"; 685 }; 686 687 constants error_status width(6) "" { 688 ERROR_0_r = 0 "No error"; 689 ERROR_1_r = 1 "Invalid descriptor provided"; 690 ERROR_2_r = 2 "Invalid data pointer provided"; 691 ERROR_4_r = 4 "Unexpected area register update while refilling"; 692 ERROR_8_r = 8 "Unexpected control register update while refilling"; 693 ERROR_16_r = 16 "Unexpected data register update while refilling"; 694 ERROR_32_r = 32 "Unexpected access to a yet-to-be-refilled location"; 695 }; 696 697 register dmm_pat_status_i_0 addr(base, 0x4C0) "Status register for each refill engine n = 0 for the first engine status register, n = 1 for the second engine status register." { 698 _ 7 mbz; 699 cnt 9 ro "Counter of remaining lines to reload for engine n"; 700 error 6 ro type(error_status) "Error happened in engine n"; 701 _ 2 mbz; 702 bypassed 1 ro "Engine n is bypassed. Direct access to the LUT is provided."; 703 _ 2 mbz; 704 linked 1 ro "Area reconfiguration link asserted for engine n"; 705 done 1 ro "Area reloading finished for engine n"; 706 run 1 ro "Area currently reloading for engine n"; 707 valid 1 ro "Valid area description for engine n"; 708 ready 1 ro "Area registers ready for engine n"; 709 }; 710 711 register dmm_pat_status_i_1 addr(base, 0x4C4) "Status register for each refill engine n = 0 for the first engine status register, n = 1 for the second engine status register." { 712 _ 7 mbz; 713 cnt 9 ro "Counter of remaining lines to reload for engine n"; 714 error 6 ro type(error_status) "Error happened in engine n"; 715 _ 2 mbz; 716 bypassed 1 ro "Engine n is bypassed. Direct access to the LUT is provided."; 717 _ 2 mbz; 718 linked 1 ro "Area reconfiguration link asserted for engine n"; 719 done 1 ro "Area reloading finished for engine n"; 720 run 1 ro "Area currently reloading for engine n"; 721 valid 1 ro "Valid area description for engine n"; 722 ready 1 ro "Area registers ready for engine n"; 723 }; 724 725 register dmm_pat_status_i_2 addr(base, 0x4C8) "Status register for each refill engine n = 0 for the first engine status register, n = 1 for the second engine status register." { 726 _ 7 mbz; 727 cnt 9 ro "Counter of remaining lines to reload for engine n"; 728 error 6 ro type(error_status) "Error happened in engine n"; 729 _ 2 mbz; 730 bypassed 1 ro "Engine n is bypassed. Direct access to the LUT is provided."; 731 _ 2 mbz; 732 linked 1 ro "Area reconfiguration link asserted for engine n"; 733 done 1 ro "Area reloading finished for engine n"; 734 run 1 ro "Area currently reloading for engine n"; 735 valid 1 ro "Valid area description for engine n"; 736 ready 1 ro "Area registers ready for engine n"; 737 }; 738 739 register dmm_pat_status_i_3 addr(base, 0x4CC) "Status register for each refill engine n = 0 for the first engine status register, n = 1 for the second engine status register." { 740 _ 7 mbz; 741 cnt 9 ro "Counter of remaining lines to reload for engine n"; 742 error 6 ro type(error_status) "Error happened in engine n"; 743 _ 2 mbz; 744 bypassed 1 ro "Engine n is bypassed. Direct access to the LUT is provided."; 745 _ 2 mbz; 746 linked 1 ro "Area reconfiguration link asserted for engine n"; 747 done 1 ro "Area reloading finished for engine n"; 748 run 1 ro "Area currently reloading for engine n"; 749 valid 1 ro "Valid area description for engine n"; 750 ready 1 ro "Area registers ready for engine n"; 751 }; 752 753 register dmm_pat_descr_i_0 addr(base, 0x500) "Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine, n = 1 for the descriptor register of the second engine. Writing to this register aborts the current ongoing area reload and resets the corresponding DMM_PAT_AREA__x, DMM_PAT_CTRL__x and DMM_PAT_DATA__x registers." { 754 addr 28 rw "Physical address of the next table refill descriptor of engine n"; 755 _ 4 mbz; 756 }; 757 758 register dmm_pat_descr_i_1 addr(base, 0x510) "Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine, n = 1 for the descriptor register of the second engine. Writing to this register aborts the current ongoing area reload and resets the corresponding DMM_PAT_AREA__x, DMM_PAT_CTRL__x and DMM_PAT_DATA__x registers." { 759 addr 28 rw "Physical address of the next table refill descriptor of engine n"; 760 _ 4 mbz; 761 }; 762 763 register dmm_pat_descr_i_2 addr(base, 0x520) "Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine, n = 1 for the descriptor register of the second engine. Writing to this register aborts the current ongoing area reload and resets the corresponding DMM_PAT_AREA__x, DMM_PAT_CTRL__x and DMM_PAT_DATA__x registers." { 764 addr 28 rw "Physical address of the next table refill descriptor of engine n"; 765 _ 4 mbz; 766 }; 767 768 register dmm_pat_descr_i_3 addr(base, 0x530) "Physical address of the next table refill descriptor n = 0 for the descriptor register of the first engine, n = 1 for the descriptor register of the second engine. Writing to this register aborts the current ongoing area reload and resets the corresponding DMM_PAT_AREA__x, DMM_PAT_CTRL__x and DMM_PAT_DATA__x registers." { 769 addr 28 rw "Physical address of the next table refill descriptor of engine n"; 770 _ 4 mbz; 771 }; 772 773 register dmm_pat_area_i_0 addr(base, 0x504) "Area definition for DMM physical address translator n = 0 for the area register of the first engine, n = 1 for the area register of the second engine." { 774 _ 1 mbz; 775 y1 7 rw "Y-coordinate of the bottom-right corner of the PAT area for engine n"; 776 x1 8 rw "X-coordinate of the bottom-right corner of the PAT area for engine n"; 777 _ 1 mbz; 778 y0 7 rw "Y-coordinate of the top-left corner of the PAT area for engine n"; 779 x0 8 rw "X-coordinate of the top-left corner of the PAT area for engine n"; 780 }; 781 782 register dmm_pat_area_i_1 addr(base, 0x514) "Area definition for DMM physical address translator n = 0 for the area register of the first engine, n = 1 for the area register of the second engine." { 783 _ 1 mbz; 784 y1 7 rw "Y-coordinate of the bottom-right corner of the PAT area for engine n"; 785 x1 8 rw "X-coordinate of the bottom-right corner of the PAT area for engine n"; 786 _ 1 mbz; 787 y0 7 rw "Y-coordinate of the top-left corner of the PAT area for engine n"; 788 x0 8 rw "X-coordinate of the top-left corner of the PAT area for engine n"; 789 }; 790 791 register dmm_pat_area_i_2 addr(base, 0x524) "Area definition for DMM physical address translator n = 0 for the area register of the first engine, n = 1 for the area register of the second engine." { 792 _ 1 mbz; 793 y1 7 rw "Y-coordinate of the bottom-right corner of the PAT area for engine n"; 794 x1 8 rw "X-coordinate of the bottom-right corner of the PAT area for engine n"; 795 _ 1 mbz; 796 y0 7 rw "Y-coordinate of the top-left corner of the PAT area for engine n"; 797 x0 8 rw "X-coordinate of the top-left corner of the PAT area for engine n"; 798 }; 799 800 register dmm_pat_area_i_3 addr(base, 0x534) "Area definition for DMM physical address translator n = 0 for the area register of the first engine, n = 1 for the area register of the second engine." { 801 _ 1 mbz; 802 y1 7 rw "Y-coordinate of the bottom-right corner of the PAT area for engine n"; 803 x1 8 rw "X-coordinate of the bottom-right corner of the PAT area for engine n"; 804 _ 1 mbz; 805 y0 7 rw "Y-coordinate of the top-left corner of the PAT area for engine n"; 806 x0 8 rw "X-coordinate of the top-left corner of the PAT area for engine n"; 807 }; 808 809 constants sync_status width(1) "" { 810 SYNC_0 = 0 "Not synchronized"; 811 SYNC_1 = 1 "Synchronized"; 812 }; 813 814 register dmm_pat_ctrl_i_0 addr(base, 0x508) "DMM physical address translator control register n = 0 for the control register of the first engine, n = 1 for the control register of the second engine." { 815 initiator 4 rw "DMM PAT initiator for synchronization in engine n"; 816 _ 11 mbz; 817 sync 1 rw type(sync_status) "DMM PAT table reload synchronization for engine n"; 818 _ 9 mbz; 819 direction 3 rw "Direction of this PAT table refill for engine n"; 820 _ 3 mbz; 821 start 1 rw "Starting a PAT table refill with engine n"; 822 }; 823 824 register dmm_pat_ctrl_i_1 addr(base, 0x518) "DMM physical address translator control register n = 0 for the control register of the first engine, n = 1 for the control register of the second engine." { 825 initiator 4 rw "DMM PAT initiator for synchronization in engine n"; 826 _ 11 mbz; 827 sync 1 rw type(sync_status) "DMM PAT table reload synchronization for engine n"; 828 _ 9 mbz; 829 direction 3 rw "Direction of this PAT table refill for engine n"; 830 _ 3 mbz; 831 start 1 rw "Starting a PAT table refill with engine n"; 832 }; 833 834 register dmm_pat_ctrl_i_2 addr(base, 0x528) "DMM physical address translator control register n = 0 for the control register of the first engine, n = 1 for the control register of the second engine." { 835 initiator 4 rw "DMM PAT initiator for synchronization in engine n"; 836 _ 11 mbz; 837 sync 1 rw type(sync_status) "DMM PAT table reload synchronization for engine n"; 838 _ 9 mbz; 839 direction 3 rw "Direction of this PAT table refill for engine n"; 840 _ 3 mbz; 841 start 1 rw "Starting a PAT table refill with engine n"; 842 }; 843 844 register dmm_pat_ctrl_i_3 addr(base, 0x538) "DMM physical address translator control register n = 0 for the control register of the first engine, n = 1 for the control register of the second engine." { 845 initiator 4 rw "DMM PAT initiator for synchronization in engine n"; 846 _ 11 mbz; 847 sync 1 rw type(sync_status) "DMM PAT table reload synchronization for engine n"; 848 _ 9 mbz; 849 direction 3 rw "Direction of this PAT table refill for engine n"; 850 _ 3 mbz; 851 start 1 rw "Starting a PAT table refill with engine n"; 852 }; 853 854 register dmm_pat_data_i_0 addr(base, 0x50C) "Physical address of the current table refill entry data n = 0 for the data register of the first engine, n = 1 for the data register of the second engine." { 855 addr 28 rw "Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n"; 856 _ 4 mbz; 857 }; 858 859 register dmm_pat_data_i_1 addr(base, 0x51C) "Physical address of the current table refill entry data n = 0 for the data register of the first engine, n = 1 for the data register of the second engine." { 860 addr 28 rw "Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n"; 861 _ 4 mbz; 862 }; 863 864 register dmm_pat_data_i_2 addr(base, 0x52C) "Physical address of the current table refill entry data n = 0 for the data register of the first engine, n = 1 for the data register of the second engine." { 865 addr 28 rw "Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n"; 866 _ 4 mbz; 867 }; 868 869 register dmm_pat_data_i_3 addr(base, 0x53C) "Physical address of the current table refill entry data n = 0 for the data register of the first engine, n = 1 for the data register of the second engine." { 870 addr 28 rw "Physical address of the current table refill entry data or single actual entry data when in manual mode for engine n"; 871 _ 4 mbz; 872 }; 873 874 constants prio_cnt_status width(7) "" { 875 PRIO_CNT_1_r = 1 "One priority entry"; 876 PRIO_CNT_2_r = 2 "Two priority entries"; 877 PRIO_CNT_4_r = 4 "Four priority entries"; 878 PRIO_CNT_8_r = 8 "Eight priority entries"; 879 PRIO_CNT_16_r = 16 "Sixteen priority entries"; 880 PRIO_CNT_32_r = 32 "Thirty-two priority entries"; 881 PRIO_CNT_64_r = 64 "Sixty-four priority entries"; 882 }; 883 884 register dmm_peg_hwinfo addr(base, 0x608) "DMM hardware configuration for PEG" { 885 _ 25 mbz; 886 prio_cnt 7 ro type(prio_cnt_status) "Number of PEG priority entries"; 887 }; 888 889 constants w7_status2 width(1) "" { 890 W7_0_w_2 = 0 "P7 field is unchanged"; 891 W7_1_w_2 = 1 "P7 field is updated"; 892 }; 893 894 constants w6_status2 width(1) "" { 895 W6_0_w_2 = 0 "P6 field is unchanged"; 896 W6_1_w_2 = 1 "P6 field is updated"; 897 }; 898 899 constants w5_status2 width(1) "" { 900 W5_0_w_2 = 0 "P5 field is unchanged"; 901 W5_1_w_2 = 1 "P5 field is updated"; 902 }; 903 904 constants w4_status2 width(1) "" { 905 W4_0_w_2 = 0 "P4 field is unchanged"; 906 W4_1_w_2 = 1 "P4 field is updated"; 907 }; 908 909 constants w3_status2 width(1) "" { 910 W3_0_w_2 = 0 "P3 field is unchanged"; 911 W3_1_w_2 = 1 "P3 field is updated"; 912 }; 913 914 constants w2_status2 width(1) "" { 915 W2_0_w_2 = 0 "P2 field is unchanged"; 916 W2_1_w_2 = 1 "P2 field is updated"; 917 }; 918 919 constants w1_status2 width(1) "" { 920 W1_0_w_2 = 0 "P1 field is unchanged"; 921 W1_1_w_2 = 1 "P1 field is updated"; 922 }; 923 924 constants w0_status2 width(1) "" { 925 W0_0_w_2 = 0 "P0 field is unchanged"; 926 W0_1_w_2 = 1 "P0 field is updated"; 927 }; 928 929 register dmm_peg_prio_k_0 addr(base, 0x620) "DMM PEG Priority register" { 930 w7 1 rw type(w7_status2) "Write-enable for P7 bit field"; 931 p7 3 rw "Priority for initiator 8.k+7"; 932 w6 1 rw type(w6_status2) "Write-enable for P6 bit field"; 933 p6 3 rw "Priority for initiator 8.k+6"; 934 w5 1 rw type(w5_status2) "Write-enable for P5 bit field"; 935 p5 3 rw "Priority for initiator 8.k+5"; 936 w4 1 rw type(w4_status2) "Write-enable for P4 bit field"; 937 p4 3 rw "Priority for initiator 8.k+4"; 938 w3 1 rw type(w3_status2) "Write-enable for P3 bit field"; 939 p3 3 rw "Priority for initiator 8.k+3"; 940 w2 1 rw type(w2_status2) "Write-enable for P2 bit field"; 941 p2 3 rw "Priority for initiator 8.k+2"; 942 w1 1 rw type(w1_status2) "Write-enable for P1 bit field"; 943 p1 3 rw "Priority for initiator 8.k+1"; 944 w0 1 rw type(w0_status2) "Write-enable for P0 bit field"; 945 p0 3 rw "Priority for initiator 8.k"; 946 }; 947 948 register dmm_peg_prio_k_1 addr(base, 0x624) "DMM PEG Priority register" { 949 w7 1 rw type(w7_status2) "Write-enable for P7 bit field"; 950 p7 3 rw "Priority for initiator 8.k+7"; 951 w6 1 rw type(w6_status2) "Write-enable for P6 bit field"; 952 p6 3 rw "Priority for initiator 8.k+6"; 953 w5 1 rw type(w5_status2) "Write-enable for P5 bit field"; 954 p5 3 rw "Priority for initiator 8.k+5"; 955 w4 1 rw type(w4_status2) "Write-enable for P4 bit field"; 956 p4 3 rw "Priority for initiator 8.k+4"; 957 w3 1 rw type(w3_status2) "Write-enable for P3 bit field"; 958 p3 3 rw "Priority for initiator 8.k+3"; 959 w2 1 rw type(w2_status2) "Write-enable for P2 bit field"; 960 p2 3 rw "Priority for initiator 8.k+2"; 961 w1 1 rw type(w1_status2) "Write-enable for P1 bit field"; 962 p1 3 rw "Priority for initiator 8.k+1"; 963 w0 1 rw type(w0_status2) "Write-enable for P0 bit field"; 964 p0 3 rw "Priority for initiator 8.k"; 965 }; 966 967 register dmm_peg_prio_k_2 addr(base, 0x628) "DMM PEG Priority register" { 968 w7 1 rw type(w7_status2) "Write-enable for P7 bit field"; 969 p7 3 rw "Priority for initiator 8.k+7"; 970 w6 1 rw type(w6_status2) "Write-enable for P6 bit field"; 971 p6 3 rw "Priority for initiator 8.k+6"; 972 w5 1 rw type(w5_status2) "Write-enable for P5 bit field"; 973 p5 3 rw "Priority for initiator 8.k+5"; 974 w4 1 rw type(w4_status2) "Write-enable for P4 bit field"; 975 p4 3 rw "Priority for initiator 8.k+4"; 976 w3 1 rw type(w3_status2) "Write-enable for P3 bit field"; 977 p3 3 rw "Priority for initiator 8.k+3"; 978 w2 1 rw type(w2_status2) "Write-enable for P2 bit field"; 979 p2 3 rw "Priority for initiator 8.k+2"; 980 w1 1 rw type(w1_status2) "Write-enable for P1 bit field"; 981 p1 3 rw "Priority for initiator 8.k+1"; 982 w0 1 rw type(w0_status2) "Write-enable for P0 bit field"; 983 p0 3 rw "Priority for initiator 8.k"; 984 }; 985 986 register dmm_peg_prio_k_3 addr(base, 0x62C) "DMM PEG Priority register" { 987 w7 1 rw type(w7_status2) "Write-enable for P7 bit field"; 988 p7 3 rw "Priority for initiator 8.k+7"; 989 w6 1 rw type(w6_status2) "Write-enable for P6 bit field"; 990 p6 3 rw "Priority for initiator 8.k+6"; 991 w5 1 rw type(w5_status2) "Write-enable for P5 bit field"; 992 p5 3 rw "Priority for initiator 8.k+5"; 993 w4 1 rw type(w4_status2) "Write-enable for P4 bit field"; 994 p4 3 rw "Priority for initiator 8.k+4"; 995 w3 1 rw type(w3_status2) "Write-enable for P3 bit field"; 996 p3 3 rw "Priority for initiator 8.k+3"; 997 w2 1 rw type(w2_status2) "Write-enable for P2 bit field"; 998 p2 3 rw "Priority for initiator 8.k+2"; 999 w1 1 rw type(w1_status2) "Write-enable for P1 bit field"; 1000 p1 3 rw "Priority for initiator 8.k+1"; 1001 w0 1 rw type(w0_status2) "Write-enable for P0 bit field"; 1002 p0 3 rw "Priority for initiator 8.k"; 1003 }; 1004 1005 register dmm_peg_prio_k_4 addr(base, 0x630) "DMM PEG Priority register" { 1006 w7 1 rw type(w7_status2) "Write-enable for P7 bit field"; 1007 p7 3 rw "Priority for initiator 8.k+7"; 1008 w6 1 rw type(w6_status2) "Write-enable for P6 bit field"; 1009 p6 3 rw "Priority for initiator 8.k+6"; 1010 w5 1 rw type(w5_status2) "Write-enable for P5 bit field"; 1011 p5 3 rw "Priority for initiator 8.k+5"; 1012 w4 1 rw type(w4_status2) "Write-enable for P4 bit field"; 1013 p4 3 rw "Priority for initiator 8.k+4"; 1014 w3 1 rw type(w3_status2) "Write-enable for P3 bit field"; 1015 p3 3 rw "Priority for initiator 8.k+3"; 1016 w2 1 rw type(w2_status2) "Write-enable for P2 bit field"; 1017 p2 3 rw "Priority for initiator 8.k+2"; 1018 w1 1 rw type(w1_status2) "Write-enable for P1 bit field"; 1019 p1 3 rw "Priority for initiator 8.k+1"; 1020 w0 1 rw type(w0_status2) "Write-enable for P0 bit field"; 1021 p0 3 rw "Priority for initiator 8.k"; 1022 }; 1023 1024 register dmm_peg_prio_k_5 addr(base, 0x634) "DMM PEG Priority register" { 1025 w7 1 rw type(w7_status2) "Write-enable for P7 bit field"; 1026 p7 3 rw "Priority for initiator 8.k+7"; 1027 w6 1 rw type(w6_status2) "Write-enable for P6 bit field"; 1028 p6 3 rw "Priority for initiator 8.k+6"; 1029 w5 1 rw type(w5_status2) "Write-enable for P5 bit field"; 1030 p5 3 rw "Priority for initiator 8.k+5"; 1031 w4 1 rw type(w4_status2) "Write-enable for P4 bit field"; 1032 p4 3 rw "Priority for initiator 8.k+4"; 1033 w3 1 rw type(w3_status2) "Write-enable for P3 bit field"; 1034 p3 3 rw "Priority for initiator 8.k+3"; 1035 w2 1 rw type(w2_status2) "Write-enable for P2 bit field"; 1036 p2 3 rw "Priority for initiator 8.k+2"; 1037 w1 1 rw type(w1_status2) "Write-enable for P1 bit field"; 1038 p1 3 rw "Priority for initiator 8.k+1"; 1039 w0 1 rw type(w0_status2) "Write-enable for P0 bit field"; 1040 p0 3 rw "Priority for initiator 8.k"; 1041 }; 1042 1043 register dmm_peg_prio_k_6 addr(base, 0x638) "DMM PEG Priority register" { 1044 w7 1 rw type(w7_status2) "Write-enable for P7 bit field"; 1045 p7 3 rw "Priority for initiator 8.k+7"; 1046 w6 1 rw type(w6_status2) "Write-enable for P6 bit field"; 1047 p6 3 rw "Priority for initiator 8.k+6"; 1048 w5 1 rw type(w5_status2) "Write-enable for P5 bit field"; 1049 p5 3 rw "Priority for initiator 8.k+5"; 1050 w4 1 rw type(w4_status2) "Write-enable for P4 bit field"; 1051 p4 3 rw "Priority for initiator 8.k+4"; 1052 w3 1 rw type(w3_status2) "Write-enable for P3 bit field"; 1053 p3 3 rw "Priority for initiator 8.k+3"; 1054 w2 1 rw type(w2_status2) "Write-enable for P2 bit field"; 1055 p2 3 rw "Priority for initiator 8.k+2"; 1056 w1 1 rw type(w1_status2) "Write-enable for P1 bit field"; 1057 p1 3 rw "Priority for initiator 8.k+1"; 1058 w0 1 rw type(w0_status2) "Write-enable for P0 bit field"; 1059 p0 3 rw "Priority for initiator 8.k"; 1060 }; 1061 1062 register dmm_peg_prio_k_7 addr(base, 0x63C) "DMM PEG Priority register" { 1063 w7 1 rw type(w7_status2) "Write-enable for P7 bit field"; 1064 p7 3 rw "Priority for initiator 8.k+7"; 1065 w6 1 rw type(w6_status2) "Write-enable for P6 bit field"; 1066 p6 3 rw "Priority for initiator 8.k+6"; 1067 w5 1 rw type(w5_status2) "Write-enable for P5 bit field"; 1068 p5 3 rw "Priority for initiator 8.k+5"; 1069 w4 1 rw type(w4_status2) "Write-enable for P4 bit field"; 1070 p4 3 rw "Priority for initiator 8.k+4"; 1071 w3 1 rw type(w3_status2) "Write-enable for P3 bit field"; 1072 p3 3 rw "Priority for initiator 8.k+3"; 1073 w2 1 rw type(w2_status2) "Write-enable for P2 bit field"; 1074 p2 3 rw "Priority for initiator 8.k+2"; 1075 w1 1 rw type(w1_status2) "Write-enable for P1 bit field"; 1076 p1 3 rw "Priority for initiator 8.k+1"; 1077 w0 1 rw type(w0_status2) "Write-enable for P0 bit field"; 1078 p0 3 rw "Priority for initiator 8.k"; 1079 }; 1080 1081 constants w_pat_status width(1) "" { 1082 W_PAT_0_w = 0 "P_PAT field is updated"; 1083 W_PAT_1_w = 1 "P_PAT field is unchanged"; 1084 }; 1085 1086 register dmm_peg_prio_pat addr(base, 0x640) "DMM PEG priority register for the internal PAT engine." { 1087 _ 28 mbz; 1088 w_pat 1 rw type(w_pat_status) "Write-enable for P_PAT bit field"; 1089 p_pat 3 rw "Priority for PAT engine"; 1090 }; 1091};