1/* 2 * Copyright (c) 2013 ETH Zurich. All rights reserved. 3 * 4 * This file is distributed under the terms in the attached LICENSE file. 5 * If you do not find this file, copies can be found by writing to: 6 * ETH Zurich D-INFK, CAB F.78, Universitaetstr. 6, CH-8092 Zurich, 7 * Attn: Systems Group. 8 */ 9 10/* 11 * omap44xx_ckgen_cm2.dev 12 * 13 * DESCRIPTION: 14 * 15 * NOTE: This file has been automatically generated based on the 16 * XML files extracted from the TI RDT v1.0.0.4p Tool. 17 * Download from here: http://www.ti.com/product/omap4460 18 * This means that the file might not be optimal in terms of naming 19 * conventions for constants and registers (duplicated 20 * namespaces in register and device name etc.). 21 * Also, because of the underlying structure from the original XML 22 * it's possible that some constants appear multiple times (if they 23 * have slightly different descriptions for example). 24 * 25 * You want to clean that up before using the files for the first time! 26 */ 27 28device omap44xx_ckgen_cm2 msbfirst ( addr base ) "" { 29 30 31 constants clksel_status width(1) "" { 32 CLKSEL_0 = 0 "Root clock is sourced from CORE_CLK"; 33 CLKSEL_1 = 1 "Functional clock is sourced from DPLL_PER"; 34 }; 35 36 register cm_clksel_mpu_m3_iss_root addr(base, 0x0) "MPU_A3/ISS root clock selection (MPU_A3_ISS_CLK)." { 37 _ 31 mbz; 38 clksel 1 rw type(clksel_status) "Select the source for the root clock of MPU_A3/ISS"; 39 }; 40 41 constants clksel_status1 width(1) "" { 42 CLKSEL_0_1 = 0 "Set the divider in bypass mode to support bypass clock from DPLL_USB to pass through without division."; 43 CLKSEL_1_1 = 1 "Set the divider to divide the DPLL o/p (480 MHz typical) by 8 to generate 60-MHz clock, to be used for OPP100 and OPP50."; 44 }; 45 46 register cm_clksel_usb_60mhz addr(base, 0x4) "Selects the configuration of the divider generating 60MHz clock for USB from the DPLL_USB o/p." { 47 _ 31 mbz; 48 clksel 1 rw type(clksel_status1) "Select the configuration of the divider"; 49 }; 50 51 constants scale_fclk_status width(1) "" { 52 SCALE_FCLK_0 = 0 "The functional clocks run at their default frequencies"; 53 SCALE_FCLK_1 = 1 "The functional clocks run at half their typical frequencies"; 54 }; 55 56 register cm_scale_fclk addr(base, 0x8) "This register can be used to scale PER_ABE_NC_FCLK, 96M_FCLK, 48M_FCLK, and 64M_FCLK to half their respective typical frequencies." { 57 _ 31 mbz; 58 scale_fclk 1 rw type(scale_fclk_status) "Enable or disable the functional clock scaling."; 59 }; 60 61 register cm_core_dvfs_perf1 addr(base, 0x10) "This register allows to system master #1 to specify which level of performance is required from CORE domain (mainly external memory throughput?)" { 62 _ 24 mbz; 63 perf_req 8 rw "Current performance request. Unit to be defined by user."; 64 }; 65 66 register cm_core_dvfs_perf2 addr(base, 0x14) "This register allows to system master #2 to specify which level of performance is require from CORE domain (mainly external memory throughput?)" { 67 _ 24 mbz; 68 perf_req 8 rw "Current performance request. Unit to be defined by user."; 69 }; 70 71 register cm_core_dvfs_perf3 addr(base, 0x18) "This register allows to system master #3 to specify which level of performance is require from CORE domain (mainly external memory throughput?)" { 72 _ 24 mbz; 73 perf_req 8 rw "Current performance request. Unit to be defined by user."; 74 }; 75 76 register cm_core_dvfs_perf4 addr(base, 0x1C) "This register allows to system master #4 to specify which level of performance is require from CORE domain (mainly external memory throughput?)" { 77 _ 24 mbz; 78 perf_req 8 rw "Current performance request. Unit to be defined by user."; 79 }; 80 81 register cm_core_dvfs_current addr(base, 0x24) "This register hold the current level of performance achievable by the CORE domain, according to the current OPP setting" { 82 _ 24 mbz; 83 perf_current 8 rw "Current achievable performance level. Unit to be defined by user."; 84 }; 85 86 register cm_iva_dvfs_perf_dsp addr(base, 0x28) "This register allows to specify which level of performance is required from IVA domain for DSP to operate." { 87 _ 24 mbz; 88 perf_req 8 rw "Current performance request. Unit to be defined by user."; 89 }; 90 91 register cm_iva_dvfs_perf_ivahd addr(base, 0x2C) "This register allows to specify which level of performance is required from IVA domain for IVAHD to operate." { 92 _ 24 mbz; 93 perf_req 8 rw "Current performance request. Unit to be defined by user."; 94 }; 95 96 register cm_iva_dvfs_perf_abe addr(base, 0x30) "This register allows to specify which level of performance is required from IVA domain for ABE to operate." { 97 _ 24 mbz; 98 perf_req 8 rw "Current performance request. Unit to be defined by user."; 99 }; 100 101 register cm_iva_dvfs_current addr(base, 0x38) "This register hold the current level of performance achievable by the IVA domain, according to the current OPP setting" { 102 _ 24 mbz; 103 perf_current 8 rw "Current achievable performance level. Unit to be defined by user."; 104 }; 105 106 constants dpll_ssc_downspread_status width(1) "" { 107 DPLL_SSC_DOWNSPREAD_0 = 0 "When SSC is enabled, clock frequency is spread on both sides of the programmed frequency"; 108 DPLL_SSC_DOWNSPREAD_1 = 1 "When SSC is enabled, clock frequency is spread only on the lower side of the programmed frequency"; 109 }; 110 111 constants dpll_ssc_ack_status width(1) "" { 112 DPLL_SSC_ACK_0_r = 0 "SSC has been turned off on PLL o/ps"; 113 DPLL_SSC_ACK_1_r = 1 "SSC has been turned on on PLL o/ps"; 114 }; 115 116 constants dpll_ssc_en_status width(1) "" { 117 DPLL_SSC_EN_0 = 0 "SSC disabled"; 118 DPLL_SSC_EN_1 = 1 "SSC enabled"; 119 }; 120 121 constants dpll_regm4xen_status width(1) "" { 122 DPLL_REGM4XEN_0_r = 0 "REGM4XEN mode of the DPLL is disabled"; 123 }; 124 125 constants dpll_lpmode_en_status width(1) "" { 126 DPLL_LPMODE_EN_0 = 0 "Low-power mode of the DPLL is disabled"; 127 DPLL_LPMODE_EN_1 = 1 "Low-power mode of the DPLL is enabled"; 128 }; 129 130 constants dpll_driftguard_en_status width(1) "" { 131 DPLL_DRIFTGUARD_EN_0 = 0 "DRIFTGUARD feature is disabled"; 132 DPLL_DRIFTGUARD_EN_1 = 1 "DRIFTGUARD feature is enabled"; 133 }; 134 135 constants dpll_en_status width(3) "" { 136 DPLL_EN_0 = 0 "Reserved"; 137 DPLL_EN_1 = 1 "Reserved"; 138 DPLL_EN_2 = 2 "Reserved"; 139 DPLL_EN_3 = 3 "Reserved"; 140 DPLL_EN_4 = 4 "Put the DPLL in MN bypass mode. The DPLL_MULT register bits are reset to 0 automatically by putting the DPLL in this mode."; 141 DPLL_EN_5 = 5 "Put the DPLL in idle bypass low-power mode."; 142 DPLL_EN_6 = 6 "Put the DPLL in idle bypass fast-relock mode."; 143 DPLL_EN_7 = 7 "Enables the DPLL in lock mode"; 144 }; 145 146 register cm_clkmode_dpll_per addr(base, 0x40) "This register allows controlling the DPLL modes." { 147 _ 17 mbz; 148 dpll_ssc_downspread 1 rw type(dpll_ssc_downspread_status) "Control if only low frequency spread is required"; 149 dpll_ssc_ack 1 ro type(dpll_ssc_ack_status) "Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature"; 150 dpll_ssc_en 1 rw type(dpll_ssc_en_status) "Enable or disable Spread Spectrum Clocking"; 151 dpll_regm4xen 1 ro type(dpll_regm4xen_status) "Enable the REGM4XEN mode of the DPLL. Please check the DPLL documentation to check when this mode can be enabled."; 152 dpll_lpmode_en 1 rw type(dpll_lpmode_en_status) "Set the DPLL in low-power mode. Check the DPLL documentation to see when this can be enabled."; 153 _ 1 mbz; 154 dpll_driftguard_en 1 rw type(dpll_driftguard_en_status) "This bit allows to enable or disable the automatic recalibration feature of the DPLL. The DPLL will automatically start a recalibration process upon assertion of the DPLL's RECAL flag if this bit is set."; 155 _ 5 mbz; 156 dpll_en 3 rw type(dpll_en_status) "DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect MN bypass mode."; 157 }; 158 159 constants st_mn_bypass_status width(1) "" { 160 ST_MN_BYPASS_1_r = 1 "DPLL is in MN_Bypass"; 161 ST_MN_BYPASS_0_r = 0 "DPLL is not in MN_Bypass"; 162 }; 163 164 constants st_dpll_clk_status width(1) "" { 165 ST_DPLL_CLK_1_r = 1 "DPLL is LOCKED"; 166 ST_DPLL_CLK_0_r = 0 "DPLL is either in bypass mode or in stop mode."; 167 }; 168 169 register cm_idlest_dpll_per addr(base, 0x44) "This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" { 170 _ 23 mbz; 171 st_mn_bypass 1 ro type(st_mn_bypass_status) "DPLL MN_BYPASS status"; 172 _ 7 mbz; 173 st_dpll_clk 1 ro type(st_dpll_clk_status) "DPLL lock status"; 174 }; 175 176 constants auto_dpll_mode_status width(3) "" { 177 AUTO_DPLL_MODE_0 = 0 "DPLL auto control disabled"; 178 AUTO_DPLL_MODE_1 = 1 "The DPLL is automatically put in low-power stop mode when its DPLL generated clocks are not required anymore. It is also restarted automatically."; 179 AUTO_DPLL_MODE_2 = 2 "The DPLL is automatically put in fast-relock stop mode when its DPLL generated clocks are not required anymore. It is also restarted automatically."; 180 AUTO_DPLL_MODE_3 = 3 "Reserved"; 181 AUTO_DPLL_MODE_4 = 4 "Reserved"; 182 AUTO_DPLL_MODE_5 = 5 "The DPLL is automatically put in idle bypass low-power mode when its DPLL generated clocks are not required anymore. It is also restarted automatically."; 183 AUTO_DPLL_MODE_6 = 6 "The DPLL is automatically put in idle bypass fast-relock mode when its DPLL generated clocks are not required anymore. It is also restarted automatically."; 184 AUTO_DPLL_MODE_7 = 7 "Reserved"; 185 }; 186 187 register cm_autoidle_dpll_per addr(base, 0x48) "This register provides automatic control over the DPLL activity." { 188 _ 29 mbz; 189 auto_dpll_mode 3 rw type(auto_dpll_mode_status) "DPLL automatic control;"; 190 }; 191 192 register cm_clksel_dpll_per addr(base, 0x4C) "This register provides controls over the DPLL." { 193 _ 8 mbz; 194 dpll_byp_clksel 1 rw "Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL Locked mode, 0 - No impact 1 - No impact In DPLL Bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT/CLKOUTX2 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT/CLKOUTX2"; 195 _ 4 mbz; 196 dpll_mult 11 rw type(dpll_en_status) "DPLL multiplier factor (2 to 2047). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 2047 = DPLL multiplies by M)."; 197 _ 1 mbz; 198 dpll_div 7 rw "DPLL divider factor (0 to 127) (equal to input N of DPLL; actual division factor is N+1)."; 199 }; 200 201 constants st_dpll_clkoutx2_status width(1) "" { 202 ST_DPLL_CLKOUTX2_0_r = 0 "The clock output is gated"; 203 ST_DPLL_CLKOUTX2_1_r = 1 "The clock output is enabled"; 204 }; 205 206 constants dpll_clkout_div_status width(5) "" { 207 DPLL_CLKOUT_DIV_0 = 0 "Reserved"; 208 DPLL_CLKOUT_DIV_4 = 4 "4, to be used for OPP100 and OPP50 (when DPLL_PER is locked at 768 MHz)"; 209 DPLL_CLKOUT_DIV_8 = 8 "8, to be used for OPP100 and OPP50 (when DPLL_PER is locked at 1536 MHz)"; 210 }; 211 212 register cm_div_m2_dpll_per addr(base, 0x50) "This register provides controls over the M2 divider of the DPLL." { 213 _ 20 mbz; 214 st_dpll_clkoutx2 1 ro type(st_dpll_clkoutx2_status) "DPLL CLKOUTX2 status"; 215 dpll_clkoutx2_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of DPLL CLKOUTX2"; 216 st_dpll_clkout 1 ro type(st_dpll_clkoutx2_status) "DPLL CLKOUT status"; 217 dpll_clkout_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of DPLL CLKOUT"; 218 _ 2 mbz; 219 dpll_clkout_divchack 1 ro "Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect."; 220 dpll_clkout_div 5 rw type(dpll_clkout_div_status) "DPLL post-divider factor, M2, for internal clock generation (1 to 31)"; 221 }; 222 223 constants st_dpll_clkouthif_status width(1) "" { 224 ST_DPLL_CLKOUTHIF_0_r = 0 "The clock output is gated."; 225 ST_DPLL_CLKOUTHIF_1_r = 1 "The clock output is enabled."; 226 }; 227 228 constants dpll_clkouthif_div_status width(5) "" { 229 DPLL_CLKOUTHIF_DIV_0 = 0 "Reserved"; 230 DPLL_CLKOUTHIF_DIV_3 = 3 "3, to be used for OPP100 (when DPLL_PER is locked at 768 MHz)"; 231 DPLL_CLKOUTHIF_DIV_4 = 4 "4, to be used for OPP50 (when DPLL_PER is locked at 768 MHz)"; 232 DPLL_CLKOUTHIF_DIV_6 = 6 "6, to be used for OPP100 (when DPLL_PER is locked at 1536 MHz)"; 233 DPLL_CLKOUTHIF_DIV_8 = 8 "8, to be used for OPP50 (when DPLL_PER is locked at 1536 MHz)"; 234 }; 235 236 register cm_div_m3_dpll_per addr(base, 0x54) "This register provides controls over the M3 divider of the DPLL." { 237 _ 22 mbz; 238 st_dpll_clkouthif 1 ro type(st_dpll_clkouthif_status) "DPLL CLKOUTHIF status"; 239 dpll_clkouthif_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of DPLL CLKOUTHIF"; 240 _ 2 mbz; 241 dpll_clkouthif_divchack 1 ro "Toggle on this status bit after changing DPLL_CLKOUTHIF_DIV indicates that the change in divider value has taken effect."; 242 dpll_clkouthif_div 5 rw type(dpll_clkouthif_div_status) "DPLL post-divider factor, M3, for internal clock generation (1 to 31). The values listed below (3, 4, 6 and 8) are used for maximum supported frequency at each OPP. Higher dividers (max 31), thus lower frequencies, are also supported."; 243 }; 244 245 constants hsdivider_clkout1_pwdn_status width(1) "" { 246 HSDIVIDER_CLKOUT1_PWDN_0 = 0 "Divider is powered up"; 247 HSDIVIDER_CLKOUT1_PWDN_1 = 1 "Divider is powered down"; 248 }; 249 250 constants hsdivider_clkout1_div_status width(5) "" { 251 HSDIVIDER_CLKOUT1_DIV_0 = 0 "Reserved"; 252 HSDIVIDER_CLKOUT1_DIV_6 = 6 "6, to be used for OPP100 and OPP50 (when DPLL_PER is locked at 768 MHz)"; 253 HSDIVIDER_CLKOUT1_DIV_12 = 12 "12, to be used for OPP100 and OPP50 (when DPLL_PER is locked at 1536 MHz)"; 254 }; 255 256 register cm_div_m4_dpll_per addr(base, 0x58) "This register provides controls over the CLKOUT1 o/p of the HSDIVIDER." { 257 _ 19 mbz; 258 hsdivider_clkout1_pwdn 1 rw type(hsdivider_clkout1_pwdn_status) "Direct power down control for HSDIVIDER M4 divider and CLKOUT1 output. Power down should be enabled only when clock is first gated."; 259 _ 2 mbz; 260 st_hsdivider_clkout1 1 ro type(st_dpll_clkouthif_status) "HSDIVIDER CLKOUT1 status"; 261 hsdivider_clkout1_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of HSDIVIDER CLKOUT1"; 262 _ 2 mbz; 263 hsdivider_clkout1_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT1_DIV indicates that the change in divider value has taken effect."; 264 hsdivider_clkout1_div 5 rw type(hsdivider_clkout1_div_status) "DPLL M4 post-divider factor (1 to 31)"; 265 }; 266 267 constants hsdivider_clkout2_pwdn_status width(1) "" { 268 HSDIVIDER_CLKOUT2_PWDN_0 = 0 "Divider is powered up."; 269 HSDIVIDER_CLKOUT2_PWDN_1 = 1 "Divider is powered down."; 270 }; 271 272 constants hsdivider_clkout2_div_status width(5) "" { 273 HSDIVIDER_CLKOUT2_DIV_0 = 0 "Reserved"; 274 HSDIVIDER_CLKOUT2_DIV_5 = 5 "5, to be used for OPP100 and OPP50 (when DPLL_PER is locked at 768 MHz)"; 275 HSDIVIDER_CLKOUT2_DIV_9 = 9 "9, to be used for OPP100 and OPP50 (when DPLL_PER is locked at 1536 MHz)"; 276 }; 277 278 register cm_div_m5_dpll_per addr(base, 0x5C) "This register provides controls over the CLKOUT2 o/p of the HSDIVIDER." { 279 _ 19 mbz; 280 hsdivider_clkout2_pwdn 1 rw type(hsdivider_clkout2_pwdn_status) "Direct power down control for HSDIVIDER M5 divider and CLKOUT2 output. Power down should be enabled only when clock is first gated."; 281 _ 2 mbz; 282 st_hsdivider_clkout2 1 ro type(st_dpll_clkouthif_status) "HSDIVIDER CLKOUT2 status"; 283 hsdivider_clkout2_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of HSDIVIDER CLKOUT2"; 284 _ 2 mbz; 285 hsdivider_clkout2_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT2_DIV indicates that the change in divider value has taken effect."; 286 hsdivider_clkout2_div 5 rw type(hsdivider_clkout2_div_status) "DPLL M5 post-divider factor (1 to 31)"; 287 }; 288 289 constants hsdivider_clkout3_div_status width(5) "" { 290 HSDIVIDER_CLKOUT3_DIV_0 = 0 "Reserved"; 291 HSDIVIDER_CLKOUT3_DIV_2 = 2 "2, to be used for OPP100 (when DPLL_PER is locked at 768 MHz)"; 292 HSDIVIDER_CLKOUT3_DIV_4 = 4 "4, to be used for OPP100 (when DPLL_PER is locked at 1536 MHz) and for OPP50 (when DPLL_PER is locked at 768 MHz)"; 293 HSDIVIDER_CLKOUT3_DIV_8 = 8 "8, to be used for OPP50 (when DPLL_PER is locked at 1536 MHz)"; 294 }; 295 296 register cm_div_m6_dpll_per addr(base, 0x60) "This register provides controls over the CLKOUT3 o/p of the HSDIVIDER." { 297 _ 19 mbz; 298 hsdivider_clkout3_pwdn 1 rw type(hsdivider_clkout2_pwdn_status) "Direct power down control for HSDIVIDER M6 divider and CLKOUT3 output. Power down should be enabled only when clock is first gated."; 299 _ 2 mbz; 300 st_hsdivider_clkout3 1 ro type(st_dpll_clkouthif_status) "HSDIVIDER CLKOUT3 status"; 301 hsdivider_clkout3_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of HSDIVIDER CLKOUT3"; 302 _ 2 mbz; 303 hsdivider_clkout3_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT3_DIV indicates that the change in divider value has taken effect."; 304 hsdivider_clkout3_div 5 rw type(hsdivider_clkout3_div_status) "DPLL M6 post-divider factor (1 to 31)"; 305 }; 306 307 constants hsdivider_clkout4_div_status width(5) "" { 308 HSDIVIDER_CLKOUT4_DIV_0 = 0 "Reserved"; 309 HSDIVIDER_CLKOUT4_DIV_3 = 3 "3, to be used for OPP100 (when DPLL_PER is locked at 768 MHz)"; 310 HSDIVIDER_CLKOUT4_DIV_5 = 5 "5, to be used for OPP100 (when DPLL_PER is locked at 1536 MHz)"; 311 HSDIVIDER_CLKOUT4_DIV_6 = 6 "6, to be used for OPP50 (when DPLL_PER is locked at 768 MHz)"; 312 HSDIVIDER_CLKOUT4_DIV_10 = 10 "10, to be used for OPP50 (when DPLL_PER is locked at 1536 MHz)"; 313 }; 314 315 register cm_div_m7_dpll_per addr(base, 0x64) "This register provides controls over the CLKOUT4 o/p of the HSDIVIDER." { 316 _ 19 mbz; 317 hsdivider_clkout4_pwdn 1 rw type(hsdivider_clkout2_pwdn_status) "Direct power down control for HSDIVIDER M7 divider and CLKOUT4 output. Power down should be enabled only when clock is first gated."; 318 _ 2 mbz; 319 st_hsdivider_clkout4 1 ro type(st_dpll_clkouthif_status) "HSDIVIDER CLKOUT4 status"; 320 hsdivider_clkout4_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of HSDIVIDER CLKOUT4"; 321 _ 2 mbz; 322 hsdivider_clkout4_divchack 1 ro "Toggle on this status bit after changing HSDIVIDER_CLKOUT4_DIV indicates that the change in divider value has taken effect."; 323 hsdivider_clkout4_div 5 rw type(hsdivider_clkout4_div_status) "DPLL M7 post-divider factor (1 to 31)"; 324 }; 325 326 register cm_ssc_deltamstep_dpll_per addr(base, 0x68) "Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" { 327 _ 12 mbz; 328 deltamstep 20 rw "DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [19:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part"; 329 }; 330 331 register cm_ssc_modfreqdiv_dpll_per addr(base, 0x6C) "Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" { 332 _ 21 mbz; 333 modfreqdiv_exponent 3 rw "Set the Exponent component of MODFREQDIV factor"; 334 _ 1 mbz; 335 modfreqdiv_mantissa 7 rw "Set the Mantissa component of MODFREQDIV factor"; 336 }; 337 338 constants dpll_en_status1 width(3) "" { 339 DPLL_EN_0_1 = 0 "Reserved"; 340 DPLL_EN_1_1 = 1 "Put the DPLL in low-power stop mode"; 341 DPLL_EN_2_1 = 2 "Reserved2"; 342 DPLL_EN_3_1 = 3 "Reserved"; 343 DPLL_EN_4_1 = 4 "Put the DPLL in MN bypass mode. The DPLL_MULT register bits are reset to 0 automatically by putting the DPLL in this mode."; 344 DPLL_EN_5_1 = 5 "Put the DPLL in idle bypass low-power mode."; 345 DPLL_EN_6_1 = 6 "Reserved"; 346 DPLL_EN_7_1 = 7 "Enables the DPLL in lock mode"; 347 }; 348 349 register cm_clkmode_dpll_usb addr(base, 0x80) "This register allows controlling the DPLL modes." { 350 _ 17 mbz; 351 dpll_ssc_downspread 1 rw type(dpll_ssc_downspread_status) "Control if only low frequency spread is required"; 352 dpll_ssc_ack 1 ro type(dpll_ssc_ack_status) "Acknowledgement from the DPLL regarding start and stop of Spread Spectrum Clocking feature"; 353 dpll_ssc_en 1 rw type(dpll_ssc_en_status) "Enable or disable Spread Spectrum Clocking"; 354 _ 9 mbz; 355 dpll_en 3 rw type(dpll_en_status1) "DPLL control. Upon Warm Reset, the PRCM DPLL control state machine updates this register to reflect DPLL low-power stop mode."; 356 }; 357 358 register cm_idlest_dpll_usb addr(base, 0x84) "This register allows monitoring DPLL activity. This register is read only and automatically updated. [warm reset insensitive]" { 359 _ 23 mbz; 360 st_mn_bypass 1 ro type(st_mn_bypass_status) "DPLL MN_BYPASS status"; 361 _ 7 mbz; 362 st_dpll_clk 1 ro type(st_dpll_clk_status) "DPLL lock status"; 363 }; 364 365 constants auto_dpll_mode_status1 width(3) "" { 366 AUTO_DPLL_MODE_0_1 = 0 "DPLL auto control disabled"; 367 AUTO_DPLL_MODE_1_1 = 1 "The DPLL is automatically put in low-power stop mode when its DPLL generated clocks are not required anymore. It is also restarted automatically."; 368 AUTO_DPLL_MODE_2_1 = 2 "Reserved"; 369 AUTO_DPLL_MODE_3_1 = 3 "Reserved"; 370 AUTO_DPLL_MODE_4_1 = 4 "Reserved"; 371 AUTO_DPLL_MODE_5_1 = 5 "The DPLL is automatically put in idle bypass low-power mode when its DPLL generated clocks are not required anymore. It is also restarted automatically."; 372 AUTO_DPLL_MODE_6_1 = 6 "Reserved"; 373 AUTO_DPLL_MODE_7_1 = 7 "Reserved"; 374 }; 375 376 register cm_autoidle_dpll_usb addr(base, 0x88) "This register provides automatic control over the DPLL activity." { 377 _ 29 mbz; 378 auto_dpll_mode 3 rw type(auto_dpll_mode_status1) "DPLL automatic control;"; 379 }; 380 381 register cm_clksel_dpll_usb addr(base, 0x8C) "This register provides controls over the DPLL." { 382 dpll_sd_div 8 rw type(dpll_en_status) "Sigma-Delta divider select (2-255). This factor must be set by s/w to ensure optimum jitter performance. DPLL_SD_DIV = CEILING ([DPLL_MULT/(DPLL_DIV+1)] * CLKINP / 250), where CLKINP is the input clock of the DPLL in MHz). Must be set with M and N factors, and must not be changed once DPLL is locked."; 383 dpll_byp_clksel 1 rw "Allows control of the BYPASS clock of the PLL and the associated HSDIVIDER. Same as ULOWCLKEN on DPLL. In DPLL locked mode, 0 - No impact 1 - No impact In DPLL bypass mode, 0 - CLKINP is selected as the BYPASS clock for CLKOUT 1 - CLKINPULOW is selected as the BYPASS clock for CLKOUT"; 384 _ 3 mbz; 385 dpll_mult 12 rw type(dpll_en_status) "DPLL multiplier factor (2 to 4095). This register is automatically cleared to 0 when the DPLL_EN field in the *CLKMODE_DPLL* register is set to select MN bypass mode. (equal to input M of DPLL; M=2 to 4095 = DPLL multiplies by M)."; 386 dpll_div 8 rw "DPLL divider factor (0 to 255) (equal to input N of DPLL; actual division factor is N+1)."; 387 }; 388 389 constants dpll_clkout_div_status1 width(7) "" { 390 DPLL_CLKOUT_DIV_0_1 = 0 "Reserved"; 391 DPLL_CLKOUT_DIV_2 = 2 "2, to be used for OPP100 and OPP50"; 392 }; 393 394 register cm_div_m2_dpll_usb addr(base, 0x90) "This register provides controls over the M2 divider of the DPLL." { 395 _ 22 mbz; 396 st_dpll_clkout 1 ro type(st_dpll_clkouthif_status) "DPLL CLKOUT status"; 397 dpll_clkout_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of DPLL CLKOUT"; 398 dpll_clkout_divchack 1 ro "Toggle on this status bit after changing DPLL_CLKOUT_DIV indicates that the change in divider value has taken effect."; 399 dpll_clkout_div 7 rw type(dpll_clkout_div_status1) "DPLL post-divider factor, M2, for internal clock generation (1 to 127)"; 400 }; 401 402 register cm_ssc_deltamstep_dpll_usb addr(base, 0xA8) "Control the DeltaMStep parameter for Spread Spectrum Clocking. [warm reset insensitive]" { 403 _ 11 mbz; 404 deltamstep 21 rw "DeltaMStep is split into fractional and integer part. For Triangular Spread Spectrum: [20:18] for integer part, [17:0] for fractional part For Square Wave Spread Spectrum [19:14] for integer part, [13:0] for fractional part"; 405 }; 406 407 register cm_ssc_modfreqdiv_dpll_usb addr(base, 0xAC) "Control the Modulation Frequency (Fm) for Spread Spectrum. [warm reset insensitive]" { 408 _ 21 mbz; 409 modfreqdiv_exponent 3 rw "Set the Exponent component of MODFREQDIV factor"; 410 _ 1 mbz; 411 modfreqdiv_mantissa 7 rw "Set the Mantissa component of MODFREQDIV factor"; 412 }; 413 414 register cm_clkdcoldo_dpll_usb addr(base, 0xB4) "This register provides controls over the CLKDCOLDO output of the DPLL." { 415 _ 22 mbz; 416 st_dpll_clkdcoldo 1 ro type(st_dpll_clkoutx2_status) "DPLL CLKDCOLDO status"; 417 dpll_clkdcoldo_gate_ctrl 1 rw type(scale_fclk_status) "Control gating of DPLL CLKDCOLDO"; 418 _ 8 mbz; 419 }; 420};