1# frv testcase for cfcmps $FRi,$FRj,$FCCi,$CCi,$cond_2
2# mach: fr500 fr550 frv
3
4	.include "testutils.inc"
5
6	float_constants
7	start
8	load_float_constants
9
10	.global cfcmps
11cfcmps:
12	set_spr_immed	0x1b1b,cccr
13
14	set_fcc         0x7,0		; Set mask opposite of expected
15	cfcmps      	fr0,fr0,fcc0,cc0,1
16	test_fcc	0x8,0
17	set_fcc         0xb,0		; Set mask opposite of expected
18	cfcmps      	fr0,fr4,fcc0,cc0,1
19	test_fcc	0x4,0
20	set_fcc         0xb,0		; Set mask opposite of expected
21	cfcmps      	fr0,fr8,fcc0,cc0,1
22	test_fcc	0x4,0
23	set_fcc         0xb,0		; Set mask opposite of expected
24	cfcmps      	fr0,fr12,fcc0,cc0,1
25	test_fcc	0x4,0
26	set_fcc         0xb,0		; Set mask opposite of expected
27	cfcmps      	fr0,fr16,fcc0,cc0,1
28	test_fcc	0x4,0
29	set_fcc         0xb,0		; Set mask opposite of expected
30	cfcmps      	fr0,fr20,fcc0,cc0,1
31	test_fcc	0x4,0
32	set_fcc         0xb,0		; Set mask opposite of expected
33	cfcmps      	fr0,fr24,fcc0,cc0,1
34	test_fcc	0x4,0
35	set_fcc         0xb,0		; Set mask opposite of expected
36	cfcmps      	fr0,fr28,fcc0,cc0,1
37	test_fcc	0x4,0
38	set_fcc         0xb,0		; Set mask opposite of expected
39	cfcmps      	fr0,fr32,fcc0,cc0,1
40	test_fcc	0x4,0
41	set_fcc         0xb,0		; Set mask opposite of expected
42	cfcmps      	fr0,fr36,fcc0,cc0,1
43	test_fcc	0x4,0
44	set_fcc         0xb,0		; Set mask opposite of expected
45	cfcmps      	fr0,fr40,fcc0,cc0,1
46	test_fcc	0x4,0
47	set_fcc         0xb,0		; Set mask opposite of expected
48	cfcmps      	fr0,fr44,fcc0,cc0,1
49	test_fcc	0x4,0
50	set_fcc         0xb,0		; Set mask opposite of expected
51	cfcmps      	fr0,fr48,fcc0,cc0,1
52	test_fcc	0x4,0
53	set_fcc         0xb,0		; Set mask opposite of expected
54	cfcmps      	fr0,fr52,fcc0,cc0,1
55	test_fcc	0x4,0
56	set_fcc         0xe,0		; Set mask opposite of expected
57	cfcmps      	fr0,fr56,fcc0,cc0,1
58	test_fcc	0x1,0
59	set_fcc         0xe,0		; Set mask opposite of expected
60	cfcmps      	fr0,fr60,fcc0,cc0,1
61	test_fcc	0x1,0
62
63	set_fcc         0xd,0		; Set mask opposite of expected
64	cfcmps      	fr4,fr0,fcc0,cc0,1
65	test_fcc	0x2,0
66	set_fcc         0x7,0		; Set mask opposite of expected
67	cfcmps      	fr4,fr4,fcc0,cc0,1
68	test_fcc	0x8,0
69	set_fcc         0xb,0		; Set mask opposite of expected
70	cfcmps      	fr4,fr8,fcc0,cc0,1
71	test_fcc	0x4,0
72	set_fcc         0xb,0		; Set mask opposite of expected
73	cfcmps      	fr4,fr12,fcc0,cc0,1
74	test_fcc	0x4,0
75	set_fcc         0xb,0		; Set mask opposite of expected
76	cfcmps      	fr4,fr16,fcc0,cc0,1
77	test_fcc	0x4,0
78	set_fcc         0xb,0		; Set mask opposite of expected
79	cfcmps      	fr4,fr20,fcc0,cc0,1
80	test_fcc	0x4,0
81	set_fcc         0xb,0		; Set mask opposite of expected
82	cfcmps      	fr4,fr24,fcc0,cc0,1
83	test_fcc	0x4,0
84	set_fcc         0xb,0		; Set mask opposite of expected
85	cfcmps      	fr4,fr28,fcc0,cc0,1
86	test_fcc	0x4,0
87	set_fcc         0xb,0		; Set mask opposite of expected
88	cfcmps      	fr4,fr32,fcc0,cc0,1
89	test_fcc	0x4,0
90	set_fcc         0xb,0		; Set mask opposite of expected
91	cfcmps      	fr4,fr36,fcc0,cc0,1
92	test_fcc	0x4,0
93	set_fcc         0xb,0		; Set mask opposite of expected
94	cfcmps      	fr4,fr40,fcc0,cc0,1
95	test_fcc	0x4,0
96	set_fcc         0xb,0		; Set mask opposite of expected
97	cfcmps      	fr4,fr44,fcc0,cc0,1
98	test_fcc	0x4,0
99	set_fcc         0xb,0		; Set mask opposite of expected
100	cfcmps      	fr4,fr48,fcc0,cc0,1
101	test_fcc	0x4,0
102	set_fcc         0xb,0		; Set mask opposite of expected
103	cfcmps      	fr4,fr52,fcc0,cc0,1
104	test_fcc	0x4,0
105	set_fcc         0xe,0		; Set mask opposite of expected
106	cfcmps      	fr4,fr56,fcc0,cc0,1
107	test_fcc	0x1,0
108	set_fcc         0xe,0		; Set mask opposite of expected
109	cfcmps      	fr4,fr60,fcc0,cc0,1
110	test_fcc	0x1,0
111
112	set_fcc         0xd,0		; Set mask opposite of expected
113	cfcmps      	fr8,fr0,fcc0,cc0,1
114	test_fcc	0x2,0
115	set_fcc         0xd,0		; Set mask opposite of expected
116	cfcmps      	fr8,fr4,fcc0,cc0,1
117	test_fcc	0x2,0
118	set_fcc         0x7,0		; Set mask opposite of expected
119	cfcmps      	fr8,fr8,fcc0,cc0,1
120	test_fcc	0x8,0
121	set_fcc         0xb,0		; Set mask opposite of expected
122	cfcmps      	fr8,fr12,fcc0,cc0,1
123	test_fcc	0x4,0
124	set_fcc         0xb,0		; Set mask opposite of expected
125	cfcmps      	fr8,fr16,fcc0,cc0,1
126	test_fcc	0x4,0
127	set_fcc         0xb,0		; Set mask opposite of expected
128	cfcmps      	fr8,fr20,fcc0,cc0,1
129	test_fcc	0x4,0
130	set_fcc         0xb,0		; Set mask opposite of expected
131	cfcmps      	fr8,fr24,fcc0,cc0,1
132	test_fcc	0x4,0
133	set_fcc         0xb,0		; Set mask opposite of expected
134	cfcmps      	fr8,fr28,fcc0,cc0,1
135	test_fcc	0x4,0
136	set_fcc         0xb,0		; Set mask opposite of expected
137	cfcmps      	fr8,fr32,fcc0,cc0,1
138	test_fcc	0x4,0
139	set_fcc         0xb,0		; Set mask opposite of expected
140	cfcmps      	fr8,fr36,fcc0,cc0,1
141	test_fcc	0x4,0
142	set_fcc         0xb,0		; Set mask opposite of expected
143	cfcmps      	fr8,fr40,fcc0,cc0,1
144	test_fcc	0x4,0
145	set_fcc         0xb,0		; Set mask opposite of expected
146	cfcmps      	fr8,fr44,fcc0,cc0,1
147	test_fcc	0x4,0
148	set_fcc         0xb,0		; Set mask opposite of expected
149	cfcmps      	fr8,fr48,fcc0,cc0,1
150	test_fcc	0x4,0
151	set_fcc         0xb,0		; Set mask opposite of expected
152	cfcmps      	fr8,fr52,fcc0,cc0,1
153	test_fcc	0x4,0
154	set_fcc         0xe,0		; Set mask opposite of expected
155	cfcmps      	fr8,fr56,fcc0,cc0,1
156	test_fcc	0x1,0
157	set_fcc         0xe,0		; Set mask opposite of expected
158	cfcmps      	fr8,fr60,fcc0,cc0,1
159	test_fcc	0x1,0
160
161	set_fcc         0xd,0		; Set mask opposite of expected
162	cfcmps      	fr12,fr0,fcc0,cc0,1
163	test_fcc	0x2,0
164	set_fcc         0xd,0		; Set mask opposite of expected
165	cfcmps      	fr12,fr4,fcc0,cc0,1
166	test_fcc	0x2,0
167	set_fcc         0xd,0		; Set mask opposite of expected
168	cfcmps      	fr12,fr8,fcc0,cc0,1
169	test_fcc	0x2,0
170	set_fcc         0x7,0		; Set mask opposite of expected
171	cfcmps      	fr12,fr12,fcc0,cc0,1
172	test_fcc	0x8,0
173	set_fcc         0xb,0		; Set mask opposite of expected
174	cfcmps      	fr12,fr16,fcc0,cc0,1
175	test_fcc	0x4,0
176	set_fcc         0xb,0		; Set mask opposite of expected
177	cfcmps      	fr12,fr20,fcc0,cc0,1
178	test_fcc	0x4,0
179	set_fcc         0xb,0		; Set mask opposite of expected
180	cfcmps      	fr12,fr24,fcc0,cc0,1
181	test_fcc	0x4,0
182	set_fcc         0xb,0		; Set mask opposite of expected
183	cfcmps      	fr12,fr28,fcc0,cc0,1
184	test_fcc	0x4,0
185	set_fcc         0xb,0		; Set mask opposite of expected
186	cfcmps      	fr12,fr32,fcc0,cc0,1
187	test_fcc	0x4,0
188	set_fcc         0xb,0		; Set mask opposite of expected
189	cfcmps      	fr12,fr36,fcc0,cc0,1
190	test_fcc	0x4,0
191	set_fcc         0xb,0		; Set mask opposite of expected
192	cfcmps      	fr12,fr40,fcc0,cc0,1
193	test_fcc	0x4,0
194	set_fcc         0xb,0		; Set mask opposite of expected
195	cfcmps      	fr12,fr44,fcc0,cc0,1
196	test_fcc	0x4,0
197	set_fcc         0xb,0		; Set mask opposite of expected
198	cfcmps      	fr12,fr48,fcc0,cc0,1
199	test_fcc	0x4,0
200	set_fcc         0xb,0		; Set mask opposite of expected
201	cfcmps      	fr12,fr52,fcc0,cc0,1
202	test_fcc	0x4,0
203	set_fcc         0xe,0		; Set mask opposite of expected
204	cfcmps      	fr12,fr56,fcc0,cc0,1
205	test_fcc	0x1,0
206	set_fcc         0xe,0		; Set mask opposite of expected
207	cfcmps      	fr12,fr60,fcc0,cc0,1
208	test_fcc	0x1,0
209
210	set_fcc         0xd,0		; Set mask opposite of expected
211	cfcmps      	fr16,fr0,fcc0,cc0,1
212	test_fcc	0x2,0
213	set_fcc         0xd,0		; Set mask opposite of expected
214	cfcmps      	fr16,fr4,fcc0,cc0,1
215	test_fcc	0x2,0
216	set_fcc         0xd,0		; Set mask opposite of expected
217	cfcmps      	fr16,fr8,fcc0,cc0,1
218	test_fcc	0x2,0
219	set_fcc         0xd,0		; Set mask opposite of expected
220	cfcmps      	fr16,fr12,fcc0,cc0,1
221	test_fcc	0x2,0
222	set_fcc         0x7,0		; Set mask opposite of expected
223	cfcmps      	fr16,fr16,fcc0,cc0,1
224	test_fcc	0x8,0
225	set_fcc         0x7,0		; Set mask opposite of expected
226	cfcmps      	fr16,fr20,fcc0,cc0,1
227	test_fcc	0x8,0
228	set_fcc         0xb,0		; Set mask opposite of expected
229	cfcmps      	fr16,fr24,fcc0,cc0,1
230	test_fcc	0x4,0
231	set_fcc         0xb,0		; Set mask opposite of expected
232	cfcmps      	fr16,fr28,fcc0,cc0,1
233	test_fcc	0x4,0
234	set_fcc         0xb,0		; Set mask opposite of expected
235	cfcmps      	fr16,fr32,fcc0,cc0,1
236	test_fcc	0x4,0
237	set_fcc         0xb,0		; Set mask opposite of expected
238	cfcmps      	fr16,fr36,fcc0,cc0,1
239	test_fcc	0x4,0
240	set_fcc         0xb,0		; Set mask opposite of expected
241	cfcmps      	fr16,fr40,fcc0,cc0,1
242	test_fcc	0x4,0
243	set_fcc         0xb,0		; Set mask opposite of expected
244	cfcmps      	fr16,fr44,fcc0,cc0,1
245	test_fcc	0x4,0
246	set_fcc         0xb,0		; Set mask opposite of expected
247	cfcmps      	fr16,fr48,fcc0,cc0,1
248	test_fcc	0x4,0
249	set_fcc         0xb,0		; Set mask opposite of expected
250	cfcmps      	fr16,fr52,fcc0,cc0,1
251	test_fcc	0x4,0
252	set_fcc         0xe,0		; Set mask opposite of expected
253	cfcmps      	fr16,fr56,fcc0,cc0,1
254	test_fcc	0x1,0
255	set_fcc         0xe,0		; Set mask opposite of expected
256	cfcmps      	fr16,fr60,fcc0,cc0,1
257	test_fcc	0x1,0
258
259	set_fcc         0xd,0		; Set mask opposite of expected
260	cfcmps      	fr20,fr0,fcc0,cc0,1
261	test_fcc	0x2,0
262	set_fcc         0xd,0		; Set mask opposite of expected
263	cfcmps      	fr20,fr4,fcc0,cc0,1
264	test_fcc	0x2,0
265	set_fcc         0xd,0		; Set mask opposite of expected
266	cfcmps      	fr20,fr8,fcc0,cc0,1
267	test_fcc	0x2,0
268	set_fcc         0xd,0		; Set mask opposite of expected
269	cfcmps      	fr20,fr12,fcc0,cc0,1
270	test_fcc	0x2,0
271	set_fcc         0x7,0		; Set mask opposite of expected
272	cfcmps      	fr20,fr16,fcc0,cc0,1
273	test_fcc	0x8,0
274	set_fcc         0x7,0		; Set mask opposite of expected
275	cfcmps      	fr20,fr20,fcc0,cc0,1
276	test_fcc	0x8,0
277	set_fcc         0xb,0		; Set mask opposite of expected
278	cfcmps      	fr20,fr24,fcc0,cc0,1
279	test_fcc	0x4,0
280	set_fcc         0xb,0		; Set mask opposite of expected
281	cfcmps      	fr20,fr28,fcc0,cc0,1
282	test_fcc	0x4,0
283	set_fcc         0xb,0		; Set mask opposite of expected
284	cfcmps      	fr20,fr32,fcc0,cc0,1
285	test_fcc	0x4,0
286	set_fcc         0xb,0		; Set mask opposite of expected
287	cfcmps      	fr20,fr36,fcc0,cc0,1
288	test_fcc	0x4,0
289	set_fcc         0xb,0		; Set mask opposite of expected
290	cfcmps      	fr20,fr40,fcc0,cc0,1
291	test_fcc	0x4,0
292	set_fcc         0xb,0		; Set mask opposite of expected
293	cfcmps      	fr20,fr44,fcc0,cc0,1
294	test_fcc	0x4,0
295	set_fcc         0xb,0		; Set mask opposite of expected
296	cfcmps      	fr20,fr48,fcc0,cc0,1
297	test_fcc	0x4,0
298	set_fcc         0xb,0		; Set mask opposite of expected
299	cfcmps      	fr20,fr52,fcc0,cc0,1
300	test_fcc	0x4,0
301	set_fcc         0xe,0		; Set mask opposite of expected
302	cfcmps      	fr20,fr56,fcc0,cc0,1
303	test_fcc	0x1,0
304	set_fcc         0xe,0		; Set mask opposite of expected
305	cfcmps      	fr20,fr60,fcc0,cc0,1
306	test_fcc	0x1,0
307
308	set_fcc         0xd,0		; Set mask opposite of expected
309	cfcmps      	fr24,fr0,fcc0,cc4,1
310	test_fcc	0x2,0
311	set_fcc         0xd,0		; Set mask opposite of expected
312	cfcmps      	fr24,fr4,fcc0,cc4,1
313	test_fcc	0x2,0
314	set_fcc         0xd,0		; Set mask opposite of expected
315	cfcmps      	fr24,fr8,fcc0,cc4,1
316	test_fcc	0x2,0
317	set_fcc         0xd,0		; Set mask opposite of expected
318	cfcmps      	fr24,fr12,fcc0,cc4,1
319	test_fcc	0x2,0
320	set_fcc         0xd,0		; Set mask opposite of expected
321	cfcmps      	fr24,fr16,fcc0,cc4,1
322	test_fcc	0x2,0
323	set_fcc         0xd,0		; Set mask opposite of expected
324	cfcmps      	fr24,fr20,fcc0,cc4,1
325	test_fcc	0x2,0
326	set_fcc         0x7,0		; Set mask opposite of expected
327	cfcmps      	fr24,fr24,fcc0,cc4,1
328	test_fcc	0x8,0
329	set_fcc         0xb,0		; Set mask opposite of expected
330	cfcmps      	fr24,fr28,fcc0,cc4,1
331	test_fcc	0x4,0
332	set_fcc         0xb,0		; Set mask opposite of expected
333	cfcmps      	fr24,fr32,fcc0,cc4,1
334	test_fcc	0x4,0
335	set_fcc         0xb,0		; Set mask opposite of expected
336	cfcmps      	fr24,fr36,fcc0,cc4,1
337	test_fcc	0x4,0
338	set_fcc         0xb,0		; Set mask opposite of expected
339	cfcmps      	fr24,fr40,fcc0,cc4,1
340	test_fcc	0x4,0
341	set_fcc         0xb,0		; Set mask opposite of expected
342	cfcmps      	fr24,fr44,fcc0,cc4,1
343	test_fcc	0x4,0
344	set_fcc         0xb,0		; Set mask opposite of expected
345	cfcmps      	fr24,fr48,fcc0,cc4,1
346	test_fcc	0x4,0
347	set_fcc         0xb,0		; Set mask opposite of expected
348	cfcmps      	fr24,fr52,fcc0,cc4,1
349	test_fcc	0x4,0
350	set_fcc         0xe,0		; Set mask opposite of expected
351	cfcmps      	fr24,fr56,fcc0,cc4,1
352	test_fcc	0x1,0
353	set_fcc         0xe,0		; Set mask opposite of expected
354	cfcmps      	fr24,fr60,fcc0,cc4,1
355	test_fcc	0x1,0
356
357	set_fcc         0xd,0		; Set mask opposite of expected
358	cfcmps      	fr28,fr0,fcc0,cc4,1
359	test_fcc	0x2,0
360	set_fcc         0xd,0		; Set mask opposite of expected
361	cfcmps      	fr28,fr4,fcc0,cc4,1
362	test_fcc	0x2,0
363	set_fcc         0xd,0		; Set mask opposite of expected
364	cfcmps      	fr28,fr8,fcc0,cc4,1
365	test_fcc	0x2,0
366	set_fcc         0xd,0		; Set mask opposite of expected
367	cfcmps      	fr28,fr12,fcc0,cc4,1
368	test_fcc	0x2,0
369	set_fcc         0xd,0		; Set mask opposite of expected
370	cfcmps      	fr28,fr16,fcc0,cc4,1
371	test_fcc	0x2,0
372	set_fcc         0xd,0		; Set mask opposite of expected
373	cfcmps      	fr28,fr20,fcc0,cc4,1
374	test_fcc	0x2,0
375	set_fcc         0xd,0		; Set mask opposite of expected
376	cfcmps      	fr28,fr24,fcc0,cc4,1
377	test_fcc	0x2,0
378	set_fcc         0x7,0		; Set mask opposite of expected
379	cfcmps      	fr28,fr28,fcc0,cc4,1
380	test_fcc	0x8,0
381	set_fcc         0xb,0		; Set mask opposite of expected
382	cfcmps      	fr28,fr32,fcc0,cc4,1
383	test_fcc	0x4,0
384	set_fcc         0xb,0		; Set mask opposite of expected
385	cfcmps      	fr28,fr36,fcc0,cc4,1
386	test_fcc	0x4,0
387	set_fcc         0xb,0		; Set mask opposite of expected
388	cfcmps      	fr28,fr40,fcc0,cc4,1
389	test_fcc	0x4,0
390	set_fcc         0xb,0		; Set mask opposite of expected
391	cfcmps      	fr28,fr44,fcc0,cc4,1
392	test_fcc	0x4,0
393	set_fcc         0xb,0		; Set mask opposite of expected
394	cfcmps      	fr28,fr48,fcc0,cc4,1
395	test_fcc	0x4,0
396	set_fcc         0xb,0		; Set mask opposite of expected
397	cfcmps      	fr28,fr52,fcc0,cc4,1
398	test_fcc	0x4,0
399	set_fcc         0xe,0		; Set mask opposite of expected
400	cfcmps      	fr28,fr56,fcc0,cc4,1
401	test_fcc	0x1,0
402	set_fcc         0xe,0		; Set mask opposite of expected
403	cfcmps      	fr28,fr60,fcc0,cc4,1
404	test_fcc	0x1,0
405
406	set_fcc         0xd,0		; Set mask opposite of expected
407	cfcmps      	fr48,fr0,fcc0,cc4,1
408	test_fcc	0x2,0
409	set_fcc         0xd,0		; Set mask opposite of expected
410	cfcmps      	fr48,fr4,fcc0,cc4,1
411	test_fcc	0x2,0
412	set_fcc         0xd,0		; Set mask opposite of expected
413	cfcmps      	fr48,fr8,fcc0,cc4,1
414	test_fcc	0x2,0
415	set_fcc         0xd,0		; Set mask opposite of expected
416	cfcmps      	fr48,fr12,fcc0,cc4,1
417	test_fcc	0x2,0
418	set_fcc         0xd,0		; Set mask opposite of expected
419	cfcmps      	fr48,fr16,fcc0,cc4,1
420	test_fcc	0x2,0
421	set_fcc         0xd,0		; Set mask opposite of expected
422	cfcmps      	fr48,fr20,fcc0,cc4,1
423	test_fcc	0x2,0
424	set_fcc         0xd,0		; Set mask opposite of expected
425	cfcmps      	fr48,fr24,fcc0,cc4,1
426	test_fcc	0x2,0
427	set_fcc         0xd,0		; Set mask opposite of expected
428	cfcmps      	fr48,fr28,fcc0,cc4,1
429	test_fcc	0x2,0
430	set_fcc         0xd,0		; Set mask opposite of expected
431	cfcmps      	fr48,fr32,fcc0,cc4,1
432	test_fcc	0x2,0
433	set_fcc         0xd,0		; Set mask opposite of expected
434	cfcmps      	fr48,fr36,fcc0,cc4,1
435	test_fcc	0x2,0
436	set_fcc         0xd,0		; Set mask opposite of expected
437	cfcmps      	fr48,fr40,fcc0,cc4,1
438	test_fcc	0x2,0
439	set_fcc         0xd,0		; Set mask opposite of expected
440	cfcmps      	fr48,fr44,fcc0,cc4,1
441	test_fcc	0x2,0
442	set_fcc         0x7,0		; Set mask opposite of expected
443	cfcmps      	fr48,fr48,fcc0,cc4,1
444	test_fcc	0x8,0
445	set_fcc         0xb,0		; Set mask opposite of expected
446	cfcmps      	fr48,fr52,fcc0,cc4,1
447	test_fcc	0x4,0
448	set_fcc         0xe,0		; Set mask opposite of expected
449	cfcmps      	fr48,fr56,fcc0,cc4,1
450	test_fcc	0x1,0
451	set_fcc         0xe,0		; Set mask opposite of expected
452	cfcmps      	fr48,fr60,fcc0,cc4,1
453	test_fcc	0x1,0
454
455	set_fcc         0xd,0		; Set mask opposite of expected
456	cfcmps      	fr52,fr0,fcc0,cc4,1
457	test_fcc	0x2,0
458	set_fcc         0xd,0		; Set mask opposite of expected
459	cfcmps      	fr52,fr4,fcc0,cc4,1
460	test_fcc	0x2,0
461	set_fcc         0xd,0		; Set mask opposite of expected
462	cfcmps      	fr52,fr8,fcc0,cc4,1
463	test_fcc	0x2,0
464	set_fcc         0xd,0		; Set mask opposite of expected
465	cfcmps      	fr52,fr12,fcc0,cc4,1
466	test_fcc	0x2,0
467	set_fcc         0xd,0		; Set mask opposite of expected
468	cfcmps      	fr52,fr16,fcc0,cc4,1
469	test_fcc	0x2,0
470	set_fcc         0xd,0		; Set mask opposite of expected
471	cfcmps      	fr52,fr20,fcc0,cc4,1
472	test_fcc	0x2,0
473	set_fcc         0xd,0		; Set mask opposite of expected
474	cfcmps      	fr52,fr24,fcc0,cc4,1
475	test_fcc	0x2,0
476	set_fcc         0xd,0		; Set mask opposite of expected
477	cfcmps      	fr52,fr28,fcc0,cc4,1
478	test_fcc	0x2,0
479	set_fcc         0xd,0		; Set mask opposite of expected
480	cfcmps      	fr52,fr32,fcc0,cc4,1
481	test_fcc	0x2,0
482	set_fcc         0xd,0		; Set mask opposite of expected
483	cfcmps      	fr52,fr36,fcc0,cc4,1
484	test_fcc	0x2,0
485	set_fcc         0xd,0		; Set mask opposite of expected
486	cfcmps      	fr52,fr40,fcc0,cc4,1
487	test_fcc	0x2,0
488	set_fcc         0xd,0		; Set mask opposite of expected
489	cfcmps      	fr52,fr44,fcc0,cc4,1
490	test_fcc	0x2,0
491	set_fcc         0xd,0		; Set mask opposite of expected
492	cfcmps      	fr52,fr48,fcc0,cc4,1
493	test_fcc	0x2,0
494	set_fcc         0x7,0		; Set mask opposite of expected
495	cfcmps      	fr52,fr52,fcc0,cc4,1
496	test_fcc	0x8,0
497	set_fcc         0xe,0		; Set mask opposite of expected
498	cfcmps      	fr52,fr56,fcc0,cc4,1
499	test_fcc	0x1,0
500	set_fcc         0xe,0		; Set mask opposite of expected
501	cfcmps      	fr52,fr60,fcc0,cc4,1
502	test_fcc	0x1,0
503
504	set_fcc         0xe,0		; Set mask opposite of expected
505	cfcmps      	fr56,fr0,fcc0,cc4,1
506	test_fcc	0x1,0
507	set_fcc         0xe,0		; Set mask opposite of expected
508	cfcmps      	fr56,fr4,fcc0,cc4,1
509	test_fcc	0x1,0
510	set_fcc         0xe,0		; Set mask opposite of expected
511	cfcmps      	fr56,fr8,fcc0,cc4,1
512	test_fcc	0x1,0
513	set_fcc         0xe,0		; Set mask opposite of expected
514	cfcmps      	fr56,fr12,fcc0,cc4,1
515	test_fcc	0x1,0
516	set_fcc         0xe,0		; Set mask opposite of expected
517	cfcmps      	fr56,fr16,fcc0,cc4,1
518	test_fcc	0x1,0
519	set_fcc         0xe,0		; Set mask opposite of expected
520	cfcmps      	fr56,fr20,fcc0,cc4,1
521	test_fcc	0x1,0
522	set_fcc         0xe,0		; Set mask opposite of expected
523	cfcmps      	fr56,fr24,fcc0,cc4,1
524	test_fcc	0x1,0
525	set_fcc         0xe,0		; Set mask opposite of expected
526	cfcmps      	fr56,fr28,fcc0,cc4,1
527	test_fcc	0x1,0
528	set_fcc         0xe,0		; Set mask opposite of expected
529	cfcmps      	fr56,fr32,fcc0,cc4,1
530	test_fcc	0x1,0
531	set_fcc         0xe,0		; Set mask opposite of expected
532	cfcmps      	fr56,fr36,fcc0,cc4,1
533	test_fcc	0x1,0
534	set_fcc         0xe,0		; Set mask opposite of expected
535	cfcmps      	fr56,fr40,fcc0,cc4,1
536	test_fcc	0x1,0
537	set_fcc         0xe,0		; Set mask opposite of expected
538	cfcmps      	fr56,fr44,fcc0,cc4,1
539	test_fcc	0x1,0
540	set_fcc         0xe,0		; Set mask opposite of expected
541	cfcmps      	fr56,fr48,fcc0,cc4,1
542	test_fcc	0x1,0
543	set_fcc         0xe,0		; Set mask opposite of expected
544	cfcmps      	fr56,fr52,fcc0,cc4,1
545	test_fcc	0x1,0
546	set_fcc         0xe,0		; Set mask opposite of expected
547	cfcmps      	fr56,fr56,fcc0,cc4,1
548	test_fcc	0x1,0
549	set_fcc         0xe,0		; Set mask opposite of expected
550	cfcmps      	fr56,fr60,fcc0,cc4,1
551	test_fcc	0x1,0
552
553	set_fcc         0xe,0		; Set mask opposite of expected
554	cfcmps      	fr60,fr0,fcc0,cc4,1
555	test_fcc	0x1,0
556	set_fcc         0xe,0		; Set mask opposite of expected
557	cfcmps      	fr60,fr4,fcc0,cc4,1
558	test_fcc	0x1,0
559	set_fcc         0xe,0		; Set mask opposite of expected
560	cfcmps      	fr60,fr8,fcc0,cc4,1
561	test_fcc	0x1,0
562	set_fcc         0xe,0		; Set mask opposite of expected
563	cfcmps      	fr60,fr12,fcc0,cc4,1
564	test_fcc	0x1,0
565	set_fcc         0xe,0		; Set mask opposite of expected
566	cfcmps      	fr60,fr16,fcc0,cc4,1
567	test_fcc	0x1,0
568	set_fcc         0xe,0		; Set mask opposite of expected
569	cfcmps      	fr60,fr20,fcc0,cc4,1
570	test_fcc	0x1,0
571	set_fcc         0xe,0		; Set mask opposite of expected
572	cfcmps      	fr60,fr24,fcc0,cc4,1
573	test_fcc	0x1,0
574	set_fcc         0xe,0		; Set mask opposite of expected
575	cfcmps      	fr60,fr28,fcc0,cc4,1
576	test_fcc	0x1,0
577	set_fcc         0xe,0		; Set mask opposite of expected
578	cfcmps      	fr60,fr32,fcc0,cc4,1
579	test_fcc	0x1,0
580	set_fcc         0xe,0		; Set mask opposite of expected
581	cfcmps      	fr60,fr36,fcc0,cc4,1
582	test_fcc	0x1,0
583	set_fcc         0xe,0		; Set mask opposite of expected
584	cfcmps      	fr60,fr40,fcc0,cc4,1
585	test_fcc	0x1,0
586	set_fcc         0xe,0		; Set mask opposite of expected
587	cfcmps      	fr60,fr44,fcc0,cc4,1
588	test_fcc	0x1,0
589	set_fcc         0xe,0		; Set mask opposite of expected
590	cfcmps      	fr60,fr48,fcc0,cc4,1
591	test_fcc	0x1,0
592	set_fcc         0xe,0		; Set mask opposite of expected
593	cfcmps      	fr60,fr52,fcc0,cc4,1
594	test_fcc	0x1,0
595	set_fcc         0xe,0		; Set mask opposite of expected
596	cfcmps      	fr60,fr56,fcc0,cc4,1
597	test_fcc	0x1,0
598	set_fcc         0xe,0		; Set mask opposite of expected
599	cfcmps      	fr60,fr60,fcc0,cc4,1
600	test_fcc	0x1,0
601;
602	set_fcc         0x7,0		; Set mask opposite of expected
603	cfcmps      	fr0,fr0,fcc0,cc1,0
604	test_fcc	0x8,0
605	set_fcc         0xb,0		; Set mask opposite of expected
606	cfcmps      	fr0,fr4,fcc0,cc1,0
607	test_fcc	0x4,0
608	set_fcc         0xb,0		; Set mask opposite of expected
609	cfcmps      	fr0,fr8,fcc0,cc1,0
610	test_fcc	0x4,0
611	set_fcc         0xb,0		; Set mask opposite of expected
612	cfcmps      	fr0,fr12,fcc0,cc1,0
613	test_fcc	0x4,0
614	set_fcc         0xb,0		; Set mask opposite of expected
615	cfcmps      	fr0,fr16,fcc0,cc1,0
616	test_fcc	0x4,0
617	set_fcc         0xb,0		; Set mask opposite of expected
618	cfcmps      	fr0,fr20,fcc0,cc1,0
619	test_fcc	0x4,0
620	set_fcc         0xb,0		; Set mask opposite of expected
621	cfcmps      	fr0,fr24,fcc0,cc1,0
622	test_fcc	0x4,0
623	set_fcc         0xb,0		; Set mask opposite of expected
624	cfcmps      	fr0,fr28,fcc0,cc1,0
625	test_fcc	0x4,0
626	set_fcc         0xb,0		; Set mask opposite of expected
627	cfcmps      	fr0,fr32,fcc0,cc1,0
628	test_fcc	0x4,0
629	set_fcc         0xb,0		; Set mask opposite of expected
630	cfcmps      	fr0,fr36,fcc0,cc1,0
631	test_fcc	0x4,0
632	set_fcc         0xb,0		; Set mask opposite of expected
633	cfcmps      	fr0,fr40,fcc0,cc1,0
634	test_fcc	0x4,0
635	set_fcc         0xb,0		; Set mask opposite of expected
636	cfcmps      	fr0,fr44,fcc0,cc1,0
637	test_fcc	0x4,0
638	set_fcc         0xb,0		; Set mask opposite of expected
639	cfcmps      	fr0,fr48,fcc0,cc1,0
640	test_fcc	0x4,0
641	set_fcc         0xb,0		; Set mask opposite of expected
642	cfcmps      	fr0,fr52,fcc0,cc1,0
643	test_fcc	0x4,0
644	set_fcc         0xe,0		; Set mask opposite of expected
645	cfcmps      	fr0,fr56,fcc0,cc1,0
646	test_fcc	0x1,0
647	set_fcc         0xe,0		; Set mask opposite of expected
648	cfcmps      	fr0,fr60,fcc0,cc1,0
649	test_fcc	0x1,0
650
651	set_fcc         0xd,0		; Set mask opposite of expected
652	cfcmps      	fr4,fr0,fcc0,cc1,0
653	test_fcc	0x2,0
654	set_fcc         0x7,0		; Set mask opposite of expected
655	cfcmps      	fr4,fr4,fcc0,cc1,0
656	test_fcc	0x8,0
657	set_fcc         0xb,0		; Set mask opposite of expected
658	cfcmps      	fr4,fr8,fcc0,cc1,0
659	test_fcc	0x4,0
660	set_fcc         0xb,0		; Set mask opposite of expected
661	cfcmps      	fr4,fr12,fcc0,cc1,0
662	test_fcc	0x4,0
663	set_fcc         0xb,0		; Set mask opposite of expected
664	cfcmps      	fr4,fr16,fcc0,cc1,0
665	test_fcc	0x4,0
666	set_fcc         0xb,0		; Set mask opposite of expected
667	cfcmps      	fr4,fr20,fcc0,cc1,0
668	test_fcc	0x4,0
669	set_fcc         0xb,0		; Set mask opposite of expected
670	cfcmps      	fr4,fr24,fcc0,cc1,0
671	test_fcc	0x4,0
672	set_fcc         0xb,0		; Set mask opposite of expected
673	cfcmps      	fr4,fr28,fcc0,cc1,0
674	test_fcc	0x4,0
675	set_fcc         0xb,0		; Set mask opposite of expected
676	cfcmps      	fr4,fr32,fcc0,cc1,0
677	test_fcc	0x4,0
678	set_fcc         0xb,0		; Set mask opposite of expected
679	cfcmps      	fr4,fr36,fcc0,cc1,0
680	test_fcc	0x4,0
681	set_fcc         0xb,0		; Set mask opposite of expected
682	cfcmps      	fr4,fr40,fcc0,cc1,0
683	test_fcc	0x4,0
684	set_fcc         0xb,0		; Set mask opposite of expected
685	cfcmps      	fr4,fr44,fcc0,cc1,0
686	test_fcc	0x4,0
687	set_fcc         0xb,0		; Set mask opposite of expected
688	cfcmps      	fr4,fr48,fcc0,cc1,0
689	test_fcc	0x4,0
690	set_fcc         0xb,0		; Set mask opposite of expected
691	cfcmps      	fr4,fr52,fcc0,cc1,0
692	test_fcc	0x4,0
693	set_fcc         0xe,0		; Set mask opposite of expected
694	cfcmps      	fr4,fr56,fcc0,cc1,0
695	test_fcc	0x1,0
696	set_fcc         0xe,0		; Set mask opposite of expected
697	cfcmps      	fr4,fr60,fcc0,cc1,0
698	test_fcc	0x1,0
699
700	set_fcc         0xd,0		; Set mask opposite of expected
701	cfcmps      	fr8,fr0,fcc0,cc1,0
702	test_fcc	0x2,0
703	set_fcc         0xd,0		; Set mask opposite of expected
704	cfcmps      	fr8,fr4,fcc0,cc1,0
705	test_fcc	0x2,0
706	set_fcc         0x7,0		; Set mask opposite of expected
707	cfcmps      	fr8,fr8,fcc0,cc1,0
708	test_fcc	0x8,0
709	set_fcc         0xb,0		; Set mask opposite of expected
710	cfcmps      	fr8,fr12,fcc0,cc1,0
711	test_fcc	0x4,0
712	set_fcc         0xb,0		; Set mask opposite of expected
713	cfcmps      	fr8,fr16,fcc0,cc1,0
714	test_fcc	0x4,0
715	set_fcc         0xb,0		; Set mask opposite of expected
716	cfcmps      	fr8,fr20,fcc0,cc1,0
717	test_fcc	0x4,0
718	set_fcc         0xb,0		; Set mask opposite of expected
719	cfcmps      	fr8,fr24,fcc0,cc1,0
720	test_fcc	0x4,0
721	set_fcc         0xb,0		; Set mask opposite of expected
722	cfcmps      	fr8,fr28,fcc0,cc1,0
723	test_fcc	0x4,0
724	set_fcc         0xb,0		; Set mask opposite of expected
725	cfcmps      	fr8,fr32,fcc0,cc1,0
726	test_fcc	0x4,0
727	set_fcc         0xb,0		; Set mask opposite of expected
728	cfcmps      	fr8,fr36,fcc0,cc1,0
729	test_fcc	0x4,0
730	set_fcc         0xb,0		; Set mask opposite of expected
731	cfcmps      	fr8,fr40,fcc0,cc1,0
732	test_fcc	0x4,0
733	set_fcc         0xb,0		; Set mask opposite of expected
734	cfcmps      	fr8,fr44,fcc0,cc1,0
735	test_fcc	0x4,0
736	set_fcc         0xb,0		; Set mask opposite of expected
737	cfcmps      	fr8,fr48,fcc0,cc1,0
738	test_fcc	0x4,0
739	set_fcc         0xb,0		; Set mask opposite of expected
740	cfcmps      	fr8,fr52,fcc0,cc1,0
741	test_fcc	0x4,0
742	set_fcc         0xe,0		; Set mask opposite of expected
743	cfcmps      	fr8,fr56,fcc0,cc1,0
744	test_fcc	0x1,0
745	set_fcc         0xe,0		; Set mask opposite of expected
746	cfcmps      	fr8,fr60,fcc0,cc1,0
747	test_fcc	0x1,0
748
749	set_fcc         0xd,0		; Set mask opposite of expected
750	cfcmps      	fr12,fr0,fcc0,cc1,0
751	test_fcc	0x2,0
752	set_fcc         0xd,0		; Set mask opposite of expected
753	cfcmps      	fr12,fr4,fcc0,cc1,0
754	test_fcc	0x2,0
755	set_fcc         0xd,0		; Set mask opposite of expected
756	cfcmps      	fr12,fr8,fcc0,cc1,0
757	test_fcc	0x2,0
758	set_fcc         0x7,0		; Set mask opposite of expected
759	cfcmps      	fr12,fr12,fcc0,cc1,0
760	test_fcc	0x8,0
761	set_fcc         0xb,0		; Set mask opposite of expected
762	cfcmps      	fr12,fr16,fcc0,cc1,0
763	test_fcc	0x4,0
764	set_fcc         0xb,0		; Set mask opposite of expected
765	cfcmps      	fr12,fr20,fcc0,cc1,0
766	test_fcc	0x4,0
767	set_fcc         0xb,0		; Set mask opposite of expected
768	cfcmps      	fr12,fr24,fcc0,cc1,0
769	test_fcc	0x4,0
770	set_fcc         0xb,0		; Set mask opposite of expected
771	cfcmps      	fr12,fr28,fcc0,cc1,0
772	test_fcc	0x4,0
773	set_fcc         0xb,0		; Set mask opposite of expected
774	cfcmps      	fr12,fr32,fcc0,cc1,0
775	test_fcc	0x4,0
776	set_fcc         0xb,0		; Set mask opposite of expected
777	cfcmps      	fr12,fr36,fcc0,cc1,0
778	test_fcc	0x4,0
779	set_fcc         0xb,0		; Set mask opposite of expected
780	cfcmps      	fr12,fr40,fcc0,cc1,0
781	test_fcc	0x4,0
782	set_fcc         0xb,0		; Set mask opposite of expected
783	cfcmps      	fr12,fr44,fcc0,cc1,0
784	test_fcc	0x4,0
785	set_fcc         0xb,0		; Set mask opposite of expected
786	cfcmps      	fr12,fr48,fcc0,cc1,0
787	test_fcc	0x4,0
788	set_fcc         0xb,0		; Set mask opposite of expected
789	cfcmps      	fr12,fr52,fcc0,cc1,0
790	test_fcc	0x4,0
791	set_fcc         0xe,0		; Set mask opposite of expected
792	cfcmps      	fr12,fr56,fcc0,cc1,0
793	test_fcc	0x1,0
794	set_fcc         0xe,0		; Set mask opposite of expected
795	cfcmps      	fr12,fr60,fcc0,cc1,0
796	test_fcc	0x1,0
797
798	set_fcc         0xd,0		; Set mask opposite of expected
799	cfcmps      	fr16,fr0,fcc0,cc1,0
800	test_fcc	0x2,0
801	set_fcc         0xd,0		; Set mask opposite of expected
802	cfcmps      	fr16,fr4,fcc0,cc1,0
803	test_fcc	0x2,0
804	set_fcc         0xd,0		; Set mask opposite of expected
805	cfcmps      	fr16,fr8,fcc0,cc1,0
806	test_fcc	0x2,0
807	set_fcc         0xd,0		; Set mask opposite of expected
808	cfcmps      	fr16,fr12,fcc0,cc1,0
809	test_fcc	0x2,0
810	set_fcc         0x7,0		; Set mask opposite of expected
811	cfcmps      	fr16,fr16,fcc0,cc1,0
812	test_fcc	0x8,0
813	set_fcc         0x7,0		; Set mask opposite of expected
814	cfcmps      	fr16,fr20,fcc0,cc1,0
815	test_fcc	0x8,0
816	set_fcc         0xb,0		; Set mask opposite of expected
817	cfcmps      	fr16,fr24,fcc0,cc1,0
818	test_fcc	0x4,0
819	set_fcc         0xb,0		; Set mask opposite of expected
820	cfcmps      	fr16,fr28,fcc0,cc1,0
821	test_fcc	0x4,0
822	set_fcc         0xb,0		; Set mask opposite of expected
823	cfcmps      	fr16,fr32,fcc0,cc1,0
824	test_fcc	0x4,0
825	set_fcc         0xb,0		; Set mask opposite of expected
826	cfcmps      	fr16,fr36,fcc0,cc1,0
827	test_fcc	0x4,0
828	set_fcc         0xb,0		; Set mask opposite of expected
829	cfcmps      	fr16,fr40,fcc0,cc1,0
830	test_fcc	0x4,0
831	set_fcc         0xb,0		; Set mask opposite of expected
832	cfcmps      	fr16,fr44,fcc0,cc1,0
833	test_fcc	0x4,0
834	set_fcc         0xb,0		; Set mask opposite of expected
835	cfcmps      	fr16,fr48,fcc0,cc1,0
836	test_fcc	0x4,0
837	set_fcc         0xb,0		; Set mask opposite of expected
838	cfcmps      	fr16,fr52,fcc0,cc1,0
839	test_fcc	0x4,0
840	set_fcc         0xe,0		; Set mask opposite of expected
841	cfcmps      	fr16,fr56,fcc0,cc1,0
842	test_fcc	0x1,0
843	set_fcc         0xe,0		; Set mask opposite of expected
844	cfcmps      	fr16,fr60,fcc0,cc1,0
845	test_fcc	0x1,0
846
847	set_fcc         0xd,0		; Set mask opposite of expected
848	cfcmps      	fr20,fr0,fcc0,cc1,0
849	test_fcc	0x2,0
850	set_fcc         0xd,0		; Set mask opposite of expected
851	cfcmps      	fr20,fr4,fcc0,cc1,0
852	test_fcc	0x2,0
853	set_fcc         0xd,0		; Set mask opposite of expected
854	cfcmps      	fr20,fr8,fcc0,cc1,0
855	test_fcc	0x2,0
856	set_fcc         0xd,0		; Set mask opposite of expected
857	cfcmps      	fr20,fr12,fcc0,cc1,0
858	test_fcc	0x2,0
859	set_fcc         0x7,0		; Set mask opposite of expected
860	cfcmps      	fr20,fr16,fcc0,cc1,0
861	test_fcc	0x8,0
862	set_fcc         0x7,0		; Set mask opposite of expected
863	cfcmps      	fr20,fr20,fcc0,cc1,0
864	test_fcc	0x8,0
865	set_fcc         0xb,0		; Set mask opposite of expected
866	cfcmps      	fr20,fr24,fcc0,cc1,0
867	test_fcc	0x4,0
868	set_fcc         0xb,0		; Set mask opposite of expected
869	cfcmps      	fr20,fr28,fcc0,cc1,0
870	test_fcc	0x4,0
871	set_fcc         0xb,0		; Set mask opposite of expected
872	cfcmps      	fr20,fr32,fcc0,cc1,0
873	test_fcc	0x4,0
874	set_fcc         0xb,0		; Set mask opposite of expected
875	cfcmps      	fr20,fr36,fcc0,cc1,0
876	test_fcc	0x4,0
877	set_fcc         0xb,0		; Set mask opposite of expected
878	cfcmps      	fr20,fr40,fcc0,cc1,0
879	test_fcc	0x4,0
880	set_fcc         0xb,0		; Set mask opposite of expected
881	cfcmps      	fr20,fr44,fcc0,cc1,0
882	test_fcc	0x4,0
883	set_fcc         0xb,0		; Set mask opposite of expected
884	cfcmps      	fr20,fr48,fcc0,cc1,0
885	test_fcc	0x4,0
886	set_fcc         0xb,0		; Set mask opposite of expected
887	cfcmps      	fr20,fr52,fcc0,cc1,0
888	test_fcc	0x4,0
889	set_fcc         0xe,0		; Set mask opposite of expected
890	cfcmps      	fr20,fr56,fcc0,cc1,0
891	test_fcc	0x1,0
892	set_fcc         0xe,0		; Set mask opposite of expected
893	cfcmps      	fr20,fr60,fcc0,cc1,0
894	test_fcc	0x1,0
895
896	set_fcc         0xd,0		; Set mask opposite of expected
897	cfcmps      	fr24,fr0,fcc0,cc5,0
898	test_fcc	0x2,0
899	set_fcc         0xd,0		; Set mask opposite of expected
900	cfcmps      	fr24,fr4,fcc0,cc5,0
901	test_fcc	0x2,0
902	set_fcc         0xd,0		; Set mask opposite of expected
903	cfcmps      	fr24,fr8,fcc0,cc5,0
904	test_fcc	0x2,0
905	set_fcc         0xd,0		; Set mask opposite of expected
906	cfcmps      	fr24,fr12,fcc0,cc5,0
907	test_fcc	0x2,0
908	set_fcc         0xd,0		; Set mask opposite of expected
909	cfcmps      	fr24,fr16,fcc0,cc5,0
910	test_fcc	0x2,0
911	set_fcc         0xd,0		; Set mask opposite of expected
912	cfcmps      	fr24,fr20,fcc0,cc5,0
913	test_fcc	0x2,0
914	set_fcc         0x7,0		; Set mask opposite of expected
915	cfcmps      	fr24,fr24,fcc0,cc5,0
916	test_fcc	0x8,0
917	set_fcc         0xb,0		; Set mask opposite of expected
918	cfcmps      	fr24,fr28,fcc0,cc5,0
919	test_fcc	0x4,0
920	set_fcc         0xb,0		; Set mask opposite of expected
921	cfcmps      	fr24,fr32,fcc0,cc5,0
922	test_fcc	0x4,0
923	set_fcc         0xb,0		; Set mask opposite of expected
924	cfcmps      	fr24,fr36,fcc0,cc5,0
925	test_fcc	0x4,0
926	set_fcc         0xb,0		; Set mask opposite of expected
927	cfcmps      	fr24,fr40,fcc0,cc5,0
928	test_fcc	0x4,0
929	set_fcc         0xb,0		; Set mask opposite of expected
930	cfcmps      	fr24,fr44,fcc0,cc5,0
931	test_fcc	0x4,0
932	set_fcc         0xb,0		; Set mask opposite of expected
933	cfcmps      	fr24,fr48,fcc0,cc5,0
934	test_fcc	0x4,0
935	set_fcc         0xb,0		; Set mask opposite of expected
936	cfcmps      	fr24,fr52,fcc0,cc5,0
937	test_fcc	0x4,0
938	set_fcc         0xe,0		; Set mask opposite of expected
939	cfcmps      	fr24,fr56,fcc0,cc5,0
940	test_fcc	0x1,0
941	set_fcc         0xe,0		; Set mask opposite of expected
942	cfcmps      	fr24,fr60,fcc0,cc5,0
943	test_fcc	0x1,0
944
945	set_fcc         0xd,0		; Set mask opposite of expected
946	cfcmps      	fr28,fr0,fcc0,cc5,0
947	test_fcc	0x2,0
948	set_fcc         0xd,0		; Set mask opposite of expected
949	cfcmps      	fr28,fr4,fcc0,cc5,0
950	test_fcc	0x2,0
951	set_fcc         0xd,0		; Set mask opposite of expected
952	cfcmps      	fr28,fr8,fcc0,cc5,0
953	test_fcc	0x2,0
954	set_fcc         0xd,0		; Set mask opposite of expected
955	cfcmps      	fr28,fr12,fcc0,cc5,0
956	test_fcc	0x2,0
957	set_fcc         0xd,0		; Set mask opposite of expected
958	cfcmps      	fr28,fr16,fcc0,cc5,0
959	test_fcc	0x2,0
960	set_fcc         0xd,0		; Set mask opposite of expected
961	cfcmps      	fr28,fr20,fcc0,cc5,0
962	test_fcc	0x2,0
963	set_fcc         0xd,0		; Set mask opposite of expected
964	cfcmps      	fr28,fr24,fcc0,cc5,0
965	test_fcc	0x2,0
966	set_fcc         0x7,0		; Set mask opposite of expected
967	cfcmps      	fr28,fr28,fcc0,cc5,0
968	test_fcc	0x8,0
969	set_fcc         0xb,0		; Set mask opposite of expected
970	cfcmps      	fr28,fr32,fcc0,cc5,0
971	test_fcc	0x4,0
972	set_fcc         0xb,0		; Set mask opposite of expected
973	cfcmps      	fr28,fr36,fcc0,cc5,0
974	test_fcc	0x4,0
975	set_fcc         0xb,0		; Set mask opposite of expected
976	cfcmps      	fr28,fr40,fcc0,cc5,0
977	test_fcc	0x4,0
978	set_fcc         0xb,0		; Set mask opposite of expected
979	cfcmps      	fr28,fr44,fcc0,cc5,0
980	test_fcc	0x4,0
981	set_fcc         0xb,0		; Set mask opposite of expected
982	cfcmps      	fr28,fr48,fcc0,cc5,0
983	test_fcc	0x4,0
984	set_fcc         0xb,0		; Set mask opposite of expected
985	cfcmps      	fr28,fr52,fcc0,cc5,0
986	test_fcc	0x4,0
987	set_fcc         0xe,0		; Set mask opposite of expected
988	cfcmps      	fr28,fr56,fcc0,cc5,0
989	test_fcc	0x1,0
990	set_fcc         0xe,0		; Set mask opposite of expected
991	cfcmps      	fr28,fr60,fcc0,cc5,0
992	test_fcc	0x1,0
993
994	set_fcc         0xd,0		; Set mask opposite of expected
995	cfcmps      	fr48,fr0,fcc0,cc5,0
996	test_fcc	0x2,0
997	set_fcc         0xd,0		; Set mask opposite of expected
998	cfcmps      	fr48,fr4,fcc0,cc5,0
999	test_fcc	0x2,0
1000	set_fcc         0xd,0		; Set mask opposite of expected
1001	cfcmps      	fr48,fr8,fcc0,cc5,0
1002	test_fcc	0x2,0
1003	set_fcc         0xd,0		; Set mask opposite of expected
1004	cfcmps      	fr48,fr12,fcc0,cc5,0
1005	test_fcc	0x2,0
1006	set_fcc         0xd,0		; Set mask opposite of expected
1007	cfcmps      	fr48,fr16,fcc0,cc5,0
1008	test_fcc	0x2,0
1009	set_fcc         0xd,0		; Set mask opposite of expected
1010	cfcmps      	fr48,fr20,fcc0,cc5,0
1011	test_fcc	0x2,0
1012	set_fcc         0xd,0		; Set mask opposite of expected
1013	cfcmps      	fr48,fr24,fcc0,cc5,0
1014	test_fcc	0x2,0
1015	set_fcc         0xd,0		; Set mask opposite of expected
1016	cfcmps      	fr48,fr28,fcc0,cc5,0
1017	test_fcc	0x2,0
1018	set_fcc         0xd,0		; Set mask opposite of expected
1019	cfcmps      	fr48,fr32,fcc0,cc5,0
1020	test_fcc	0x2,0
1021	set_fcc         0xd,0		; Set mask opposite of expected
1022	cfcmps      	fr48,fr36,fcc0,cc5,0
1023	test_fcc	0x2,0
1024	set_fcc         0xd,0		; Set mask opposite of expected
1025	cfcmps      	fr48,fr40,fcc0,cc5,0
1026	test_fcc	0x2,0
1027	set_fcc         0xd,0		; Set mask opposite of expected
1028	cfcmps      	fr48,fr44,fcc0,cc5,0
1029	test_fcc	0x2,0
1030	set_fcc         0x7,0		; Set mask opposite of expected
1031	cfcmps      	fr48,fr48,fcc0,cc5,0
1032	test_fcc	0x8,0
1033	set_fcc         0xb,0		; Set mask opposite of expected
1034	cfcmps      	fr48,fr52,fcc0,cc5,0
1035	test_fcc	0x4,0
1036	set_fcc         0xe,0		; Set mask opposite of expected
1037	cfcmps      	fr48,fr56,fcc0,cc5,0
1038	test_fcc	0x1,0
1039	set_fcc         0xe,0		; Set mask opposite of expected
1040	cfcmps      	fr48,fr60,fcc0,cc5,0
1041	test_fcc	0x1,0
1042
1043	set_fcc         0xd,0		; Set mask opposite of expected
1044	cfcmps      	fr52,fr0,fcc0,cc5,0
1045	test_fcc	0x2,0
1046	set_fcc         0xd,0		; Set mask opposite of expected
1047	cfcmps      	fr52,fr4,fcc0,cc5,0
1048	test_fcc	0x2,0
1049	set_fcc         0xd,0		; Set mask opposite of expected
1050	cfcmps      	fr52,fr8,fcc0,cc5,0
1051	test_fcc	0x2,0
1052	set_fcc         0xd,0		; Set mask opposite of expected
1053	cfcmps      	fr52,fr12,fcc0,cc5,0
1054	test_fcc	0x2,0
1055	set_fcc         0xd,0		; Set mask opposite of expected
1056	cfcmps      	fr52,fr16,fcc0,cc5,0
1057	test_fcc	0x2,0
1058	set_fcc         0xd,0		; Set mask opposite of expected
1059	cfcmps      	fr52,fr20,fcc0,cc5,0
1060	test_fcc	0x2,0
1061	set_fcc         0xd,0		; Set mask opposite of expected
1062	cfcmps      	fr52,fr24,fcc0,cc5,0
1063	test_fcc	0x2,0
1064	set_fcc         0xd,0		; Set mask opposite of expected
1065	cfcmps      	fr52,fr28,fcc0,cc5,0
1066	test_fcc	0x2,0
1067	set_fcc         0xd,0		; Set mask opposite of expected
1068	cfcmps      	fr52,fr32,fcc0,cc5,0
1069	test_fcc	0x2,0
1070	set_fcc         0xd,0		; Set mask opposite of expected
1071	cfcmps      	fr52,fr36,fcc0,cc5,0
1072	test_fcc	0x2,0
1073	set_fcc         0xd,0		; Set mask opposite of expected
1074	cfcmps      	fr52,fr40,fcc0,cc5,0
1075	test_fcc	0x2,0
1076	set_fcc         0xd,0		; Set mask opposite of expected
1077	cfcmps      	fr52,fr44,fcc0,cc5,0
1078	test_fcc	0x2,0
1079	set_fcc         0xd,0		; Set mask opposite of expected
1080	cfcmps      	fr52,fr48,fcc0,cc5,0
1081	test_fcc	0x2,0
1082	set_fcc         0x7,0		; Set mask opposite of expected
1083	cfcmps      	fr52,fr52,fcc0,cc5,0
1084	test_fcc	0x8,0
1085	set_fcc         0xe,0		; Set mask opposite of expected
1086	cfcmps      	fr52,fr56,fcc0,cc5,0
1087	test_fcc	0x1,0
1088	set_fcc         0xe,0		; Set mask opposite of expected
1089	cfcmps      	fr52,fr60,fcc0,cc5,0
1090	test_fcc	0x1,0
1091
1092	set_fcc         0xe,0		; Set mask opposite of expected
1093	cfcmps      	fr56,fr0,fcc0,cc5,0
1094	test_fcc	0x1,0
1095	set_fcc         0xe,0		; Set mask opposite of expected
1096	cfcmps      	fr56,fr4,fcc0,cc5,0
1097	test_fcc	0x1,0
1098	set_fcc         0xe,0		; Set mask opposite of expected
1099	cfcmps      	fr56,fr8,fcc0,cc5,0
1100	test_fcc	0x1,0
1101	set_fcc         0xe,0		; Set mask opposite of expected
1102	cfcmps      	fr56,fr12,fcc0,cc5,0
1103	test_fcc	0x1,0
1104	set_fcc         0xe,0		; Set mask opposite of expected
1105	cfcmps      	fr56,fr16,fcc0,cc5,0
1106	test_fcc	0x1,0
1107	set_fcc         0xe,0		; Set mask opposite of expected
1108	cfcmps      	fr56,fr20,fcc0,cc5,0
1109	test_fcc	0x1,0
1110	set_fcc         0xe,0		; Set mask opposite of expected
1111	cfcmps      	fr56,fr24,fcc0,cc5,0
1112	test_fcc	0x1,0
1113	set_fcc         0xe,0		; Set mask opposite of expected
1114	cfcmps      	fr56,fr28,fcc0,cc5,0
1115	test_fcc	0x1,0
1116	set_fcc         0xe,0		; Set mask opposite of expected
1117	cfcmps      	fr56,fr32,fcc0,cc5,0
1118	test_fcc	0x1,0
1119	set_fcc         0xe,0		; Set mask opposite of expected
1120	cfcmps      	fr56,fr36,fcc0,cc5,0
1121	test_fcc	0x1,0
1122	set_fcc         0xe,0		; Set mask opposite of expected
1123	cfcmps      	fr56,fr40,fcc0,cc5,0
1124	test_fcc	0x1,0
1125	set_fcc         0xe,0		; Set mask opposite of expected
1126	cfcmps      	fr56,fr44,fcc0,cc5,0
1127	test_fcc	0x1,0
1128	set_fcc         0xe,0		; Set mask opposite of expected
1129	cfcmps      	fr56,fr48,fcc0,cc5,0
1130	test_fcc	0x1,0
1131	set_fcc         0xe,0		; Set mask opposite of expected
1132	cfcmps      	fr56,fr52,fcc0,cc5,0
1133	test_fcc	0x1,0
1134	set_fcc         0xe,0		; Set mask opposite of expected
1135	cfcmps      	fr56,fr56,fcc0,cc5,0
1136	test_fcc	0x1,0
1137	set_fcc         0xe,0		; Set mask opposite of expected
1138	cfcmps      	fr56,fr60,fcc0,cc5,0
1139	test_fcc	0x1,0
1140
1141	set_fcc         0xe,0		; Set mask opposite of expected
1142	cfcmps      	fr60,fr0,fcc0,cc5,0
1143	test_fcc	0x1,0
1144	set_fcc         0xe,0		; Set mask opposite of expected
1145	cfcmps      	fr60,fr4,fcc0,cc5,0
1146	test_fcc	0x1,0
1147	set_fcc         0xe,0		; Set mask opposite of expected
1148	cfcmps      	fr60,fr8,fcc0,cc5,0
1149	test_fcc	0x1,0
1150	set_fcc         0xe,0		; Set mask opposite of expected
1151	cfcmps      	fr60,fr12,fcc0,cc5,0
1152	test_fcc	0x1,0
1153	set_fcc         0xe,0		; Set mask opposite of expected
1154	cfcmps      	fr60,fr16,fcc0,cc5,0
1155	test_fcc	0x1,0
1156	set_fcc         0xe,0		; Set mask opposite of expected
1157	cfcmps      	fr60,fr20,fcc0,cc5,0
1158	test_fcc	0x1,0
1159	set_fcc         0xe,0		; Set mask opposite of expected
1160	cfcmps      	fr60,fr24,fcc0,cc5,0
1161	test_fcc	0x1,0
1162	set_fcc         0xe,0		; Set mask opposite of expected
1163	cfcmps      	fr60,fr28,fcc0,cc5,0
1164	test_fcc	0x1,0
1165	set_fcc         0xe,0		; Set mask opposite of expected
1166	cfcmps      	fr60,fr32,fcc0,cc5,0
1167	test_fcc	0x1,0
1168	set_fcc         0xe,0		; Set mask opposite of expected
1169	cfcmps      	fr60,fr36,fcc0,cc5,0
1170	test_fcc	0x1,0
1171	set_fcc         0xe,0		; Set mask opposite of expected
1172	cfcmps      	fr60,fr40,fcc0,cc5,0
1173	test_fcc	0x1,0
1174	set_fcc         0xe,0		; Set mask opposite of expected
1175	cfcmps      	fr60,fr44,fcc0,cc5,0
1176	test_fcc	0x1,0
1177	set_fcc         0xe,0		; Set mask opposite of expected
1178	cfcmps      	fr60,fr48,fcc0,cc5,0
1179	test_fcc	0x1,0
1180	set_fcc         0xe,0		; Set mask opposite of expected
1181	cfcmps      	fr60,fr52,fcc0,cc5,0
1182	test_fcc	0x1,0
1183	set_fcc         0xe,0		; Set mask opposite of expected
1184	cfcmps      	fr60,fr56,fcc0,cc5,0
1185	test_fcc	0x1,0
1186	set_fcc         0xe,0		; Set mask opposite of expected
1187	cfcmps      	fr60,fr60,fcc0,cc5,0
1188	test_fcc	0x1,0
1189;
1190	set_fcc         0x7,0		; Set mask opposite of expected
1191	cfcmps      	fr0,fr0,fcc0,cc0,0
1192	test_fcc	0x7,0
1193	set_fcc         0xb,0		; Set mask opposite of expected
1194	cfcmps      	fr0,fr4,fcc0,cc0,0
1195	test_fcc	0xb,0
1196	set_fcc         0xb,0		; Set mask opposite of expected
1197	cfcmps      	fr0,fr8,fcc0,cc0,0
1198	test_fcc	0xb,0
1199	set_fcc         0xb,0		; Set mask opposite of expected
1200	cfcmps      	fr0,fr12,fcc0,cc0,0
1201	test_fcc	0xb,0
1202	set_fcc         0xb,0		; Set mask opposite of expected
1203	cfcmps      	fr0,fr16,fcc0,cc0,0
1204	test_fcc	0xb,0
1205	set_fcc         0xb,0		; Set mask opposite of expected
1206	cfcmps      	fr0,fr20,fcc0,cc0,0
1207	test_fcc	0xb,0
1208	set_fcc         0xb,0		; Set mask opposite of expected
1209	cfcmps      	fr0,fr24,fcc0,cc0,0
1210	test_fcc	0xb,0
1211	set_fcc         0xb,0		; Set mask opposite of expected
1212	cfcmps      	fr0,fr28,fcc0,cc0,0
1213	test_fcc	0xb,0
1214	set_fcc         0xb,0		; Set mask opposite of expected
1215	cfcmps      	fr0,fr32,fcc0,cc0,0
1216	test_fcc	0xb,0
1217	set_fcc         0xb,0		; Set mask opposite of expected
1218	cfcmps      	fr0,fr36,fcc0,cc0,0
1219	test_fcc	0xb,0
1220	set_fcc         0xb,0		; Set mask opposite of expected
1221	cfcmps      	fr0,fr40,fcc0,cc0,0
1222	test_fcc	0xb,0
1223	set_fcc         0xb,0		; Set mask opposite of expected
1224	cfcmps      	fr0,fr44,fcc0,cc0,0
1225	test_fcc	0xb,0
1226	set_fcc         0xb,0		; Set mask opposite of expected
1227	cfcmps      	fr0,fr48,fcc0,cc0,0
1228	test_fcc	0xb,0
1229	set_fcc         0xb,0		; Set mask opposite of expected
1230	cfcmps      	fr0,fr52,fcc0,cc0,0
1231	test_fcc	0xb,0
1232	set_fcc         0xe,0		; Set mask opposite of expected
1233	cfcmps      	fr0,fr56,fcc0,cc0,0
1234	test_fcc	0xe,0
1235	set_fcc         0xe,0		; Set mask opposite of expected
1236	cfcmps      	fr0,fr60,fcc0,cc0,0
1237	test_fcc	0xe,0
1238
1239	set_fcc         0xd,0		; Set mask opposite of expected
1240	cfcmps      	fr4,fr0,fcc0,cc0,0
1241	test_fcc	0xd,0
1242	set_fcc         0x7,0		; Set mask opposite of expected
1243	cfcmps      	fr4,fr4,fcc0,cc0,0
1244	test_fcc	0x7,0
1245	set_fcc         0xb,0		; Set mask opposite of expected
1246	cfcmps      	fr4,fr8,fcc0,cc0,0
1247	test_fcc	0xb,0
1248	set_fcc         0xb,0		; Set mask opposite of expected
1249	cfcmps      	fr4,fr12,fcc0,cc0,0
1250	test_fcc	0xb,0
1251	set_fcc         0xb,0		; Set mask opposite of expected
1252	cfcmps      	fr4,fr16,fcc0,cc0,0
1253	test_fcc	0xb,0
1254	set_fcc         0xb,0		; Set mask opposite of expected
1255	cfcmps      	fr4,fr20,fcc0,cc0,0
1256	test_fcc	0xb,0
1257	set_fcc         0xb,0		; Set mask opposite of expected
1258	cfcmps      	fr4,fr24,fcc0,cc0,0
1259	test_fcc	0xb,0
1260	set_fcc         0xb,0		; Set mask opposite of expected
1261	cfcmps      	fr4,fr28,fcc0,cc0,0
1262	test_fcc	0xb,0
1263	set_fcc         0xb,0		; Set mask opposite of expected
1264	cfcmps      	fr4,fr32,fcc0,cc0,0
1265	test_fcc	0xb,0
1266	set_fcc         0xb,0		; Set mask opposite of expected
1267	cfcmps      	fr4,fr36,fcc0,cc0,0
1268	test_fcc	0xb,0
1269	set_fcc         0xb,0		; Set mask opposite of expected
1270	cfcmps      	fr4,fr40,fcc0,cc0,0
1271	test_fcc	0xb,0
1272	set_fcc         0xb,0		; Set mask opposite of expected
1273	cfcmps      	fr4,fr44,fcc0,cc0,0
1274	test_fcc	0xb,0
1275	set_fcc         0xb,0		; Set mask opposite of expected
1276	cfcmps      	fr4,fr48,fcc0,cc0,0
1277	test_fcc	0xb,0
1278	set_fcc         0xb,0		; Set mask opposite of expected
1279	cfcmps      	fr4,fr52,fcc0,cc0,0
1280	test_fcc	0xb,0
1281	set_fcc         0xe,0		; Set mask opposite of expected
1282	cfcmps      	fr4,fr56,fcc0,cc0,0
1283	test_fcc	0xe,0
1284	set_fcc         0xe,0		; Set mask opposite of expected
1285	cfcmps      	fr4,fr60,fcc0,cc0,0
1286	test_fcc	0xe,0
1287
1288	set_fcc         0xd,0		; Set mask opposite of expected
1289	cfcmps      	fr8,fr0,fcc0,cc0,0
1290	test_fcc	0xd,0
1291	set_fcc         0xd,0		; Set mask opposite of expected
1292	cfcmps      	fr8,fr4,fcc0,cc0,0
1293	test_fcc	0xd,0
1294	set_fcc         0x7,0		; Set mask opposite of expected
1295	cfcmps      	fr8,fr8,fcc0,cc0,0
1296	test_fcc	0x7,0
1297	set_fcc         0xb,0		; Set mask opposite of expected
1298	cfcmps      	fr8,fr12,fcc0,cc0,0
1299	test_fcc	0xb,0
1300	set_fcc         0xb,0		; Set mask opposite of expected
1301	cfcmps      	fr8,fr16,fcc0,cc0,0
1302	test_fcc	0xb,0
1303	set_fcc         0xb,0		; Set mask opposite of expected
1304	cfcmps      	fr8,fr20,fcc0,cc0,0
1305	test_fcc	0xb,0
1306	set_fcc         0xb,0		; Set mask opposite of expected
1307	cfcmps      	fr8,fr24,fcc0,cc0,0
1308	test_fcc	0xb,0
1309	set_fcc         0xb,0		; Set mask opposite of expected
1310	cfcmps      	fr8,fr28,fcc0,cc0,0
1311	test_fcc	0xb,0
1312	set_fcc         0xb,0		; Set mask opposite of expected
1313	cfcmps      	fr8,fr32,fcc0,cc0,0
1314	test_fcc	0xb,0
1315	set_fcc         0xb,0		; Set mask opposite of expected
1316	cfcmps      	fr8,fr36,fcc0,cc0,0
1317	test_fcc	0xb,0
1318	set_fcc         0xb,0		; Set mask opposite of expected
1319	cfcmps      	fr8,fr40,fcc0,cc0,0
1320	test_fcc	0xb,0
1321	set_fcc         0xb,0		; Set mask opposite of expected
1322	cfcmps      	fr8,fr44,fcc0,cc0,0
1323	test_fcc	0xb,0
1324	set_fcc         0xb,0		; Set mask opposite of expected
1325	cfcmps      	fr8,fr48,fcc0,cc0,0
1326	test_fcc	0xb,0
1327	set_fcc         0xb,0		; Set mask opposite of expected
1328	cfcmps      	fr8,fr52,fcc0,cc0,0
1329	test_fcc	0xb,0
1330	set_fcc         0xe,0		; Set mask opposite of expected
1331	cfcmps      	fr8,fr56,fcc0,cc0,0
1332	test_fcc	0xe,0
1333	set_fcc         0xe,0		; Set mask opposite of expected
1334	cfcmps      	fr8,fr60,fcc0,cc0,0
1335	test_fcc	0xe,0
1336
1337	set_fcc         0xd,0		; Set mask opposite of expected
1338	cfcmps      	fr12,fr0,fcc0,cc0,0
1339	test_fcc	0xd,0
1340	set_fcc         0xd,0		; Set mask opposite of expected
1341	cfcmps      	fr12,fr4,fcc0,cc0,0
1342	test_fcc	0xd,0
1343	set_fcc         0xd,0		; Set mask opposite of expected
1344	cfcmps      	fr12,fr8,fcc0,cc0,0
1345	test_fcc	0xd,0
1346	set_fcc         0x7,0		; Set mask opposite of expected
1347	cfcmps      	fr12,fr12,fcc0,cc0,0
1348	test_fcc	0x7,0
1349	set_fcc         0xb,0		; Set mask opposite of expected
1350	cfcmps      	fr12,fr16,fcc0,cc0,0
1351	test_fcc	0xb,0
1352	set_fcc         0xb,0		; Set mask opposite of expected
1353	cfcmps      	fr12,fr20,fcc0,cc0,0
1354	test_fcc	0xb,0
1355	set_fcc         0xb,0		; Set mask opposite of expected
1356	cfcmps      	fr12,fr24,fcc0,cc0,0
1357	test_fcc	0xb,0
1358	set_fcc         0xb,0		; Set mask opposite of expected
1359	cfcmps      	fr12,fr28,fcc0,cc0,0
1360	test_fcc	0xb,0
1361	set_fcc         0xb,0		; Set mask opposite of expected
1362	cfcmps      	fr12,fr32,fcc0,cc0,0
1363	test_fcc	0xb,0
1364	set_fcc         0xb,0		; Set mask opposite of expected
1365	cfcmps      	fr12,fr36,fcc0,cc0,0
1366	test_fcc	0xb,0
1367	set_fcc         0xb,0		; Set mask opposite of expected
1368	cfcmps      	fr12,fr40,fcc0,cc0,0
1369	test_fcc	0xb,0
1370	set_fcc         0xb,0		; Set mask opposite of expected
1371	cfcmps      	fr12,fr44,fcc0,cc0,0
1372	test_fcc	0xb,0
1373	set_fcc         0xb,0		; Set mask opposite of expected
1374	cfcmps      	fr12,fr48,fcc0,cc0,0
1375	test_fcc	0xb,0
1376	set_fcc         0xb,0		; Set mask opposite of expected
1377	cfcmps      	fr12,fr52,fcc0,cc0,0
1378	test_fcc	0xb,0
1379	set_fcc         0xe,0		; Set mask opposite of expected
1380	cfcmps      	fr12,fr56,fcc0,cc0,0
1381	test_fcc	0xe,0
1382	set_fcc         0xe,0		; Set mask opposite of expected
1383	cfcmps      	fr12,fr60,fcc0,cc0,0
1384	test_fcc	0xe,0
1385
1386	set_fcc         0xd,0		; Set mask opposite of expected
1387	cfcmps      	fr16,fr0,fcc0,cc0,0
1388	test_fcc	0xd,0
1389	set_fcc         0xd,0		; Set mask opposite of expected
1390	cfcmps      	fr16,fr4,fcc0,cc0,0
1391	test_fcc	0xd,0
1392	set_fcc         0xd,0		; Set mask opposite of expected
1393	cfcmps      	fr16,fr8,fcc0,cc0,0
1394	test_fcc	0xd,0
1395	set_fcc         0xd,0		; Set mask opposite of expected
1396	cfcmps      	fr16,fr12,fcc0,cc0,0
1397	test_fcc	0xd,0
1398	set_fcc         0x7,0		; Set mask opposite of expected
1399	cfcmps      	fr16,fr16,fcc0,cc0,0
1400	test_fcc	0x7,0
1401	set_fcc         0x7,0		; Set mask opposite of expected
1402	cfcmps      	fr16,fr20,fcc0,cc0,0
1403	test_fcc	0x7,0
1404	set_fcc         0xb,0		; Set mask opposite of expected
1405	cfcmps      	fr16,fr24,fcc0,cc0,0
1406	test_fcc	0xb,0
1407	set_fcc         0xb,0		; Set mask opposite of expected
1408	cfcmps      	fr16,fr28,fcc0,cc0,0
1409	test_fcc	0xb,0
1410	set_fcc         0xb,0		; Set mask opposite of expected
1411	cfcmps      	fr16,fr32,fcc0,cc0,0
1412	test_fcc	0xb,0
1413	set_fcc         0xb,0		; Set mask opposite of expected
1414	cfcmps      	fr16,fr36,fcc0,cc0,0
1415	test_fcc	0xb,0
1416	set_fcc         0xb,0		; Set mask opposite of expected
1417	cfcmps      	fr16,fr40,fcc0,cc0,0
1418	test_fcc	0xb,0
1419	set_fcc         0xb,0		; Set mask opposite of expected
1420	cfcmps      	fr16,fr44,fcc0,cc0,0
1421	test_fcc	0xb,0
1422	set_fcc         0xb,0		; Set mask opposite of expected
1423	cfcmps      	fr16,fr48,fcc0,cc0,0
1424	test_fcc	0xb,0
1425	set_fcc         0xb,0		; Set mask opposite of expected
1426	cfcmps      	fr16,fr52,fcc0,cc0,0
1427	test_fcc	0xb,0
1428	set_fcc         0xe,0		; Set mask opposite of expected
1429	cfcmps      	fr16,fr56,fcc0,cc0,0
1430	test_fcc	0xe,0
1431	set_fcc         0xe,0		; Set mask opposite of expected
1432	cfcmps      	fr16,fr60,fcc0,cc0,0
1433	test_fcc	0xe,0
1434
1435	set_fcc         0xd,0		; Set mask opposite of expected
1436	cfcmps      	fr20,fr0,fcc0,cc0,0
1437	test_fcc	0xd,0
1438	set_fcc         0xd,0		; Set mask opposite of expected
1439	cfcmps      	fr20,fr4,fcc0,cc0,0
1440	test_fcc	0xd,0
1441	set_fcc         0xd,0		; Set mask opposite of expected
1442	cfcmps      	fr20,fr8,fcc0,cc0,0
1443	test_fcc	0xd,0
1444	set_fcc         0xd,0		; Set mask opposite of expected
1445	cfcmps      	fr20,fr12,fcc0,cc0,0
1446	test_fcc	0xd,0
1447	set_fcc         0x7,0		; Set mask opposite of expected
1448	cfcmps      	fr20,fr16,fcc0,cc0,0
1449	test_fcc	0x7,0
1450	set_fcc         0x7,0		; Set mask opposite of expected
1451	cfcmps      	fr20,fr20,fcc0,cc0,0
1452	test_fcc	0x7,0
1453	set_fcc         0xb,0		; Set mask opposite of expected
1454	cfcmps      	fr20,fr24,fcc0,cc0,0
1455	test_fcc	0xb,0
1456	set_fcc         0xb,0		; Set mask opposite of expected
1457	cfcmps      	fr20,fr28,fcc0,cc0,0
1458	test_fcc	0xb,0
1459	set_fcc         0xb,0		; Set mask opposite of expected
1460	cfcmps      	fr20,fr32,fcc0,cc0,0
1461	test_fcc	0xb,0
1462	set_fcc         0xb,0		; Set mask opposite of expected
1463	cfcmps      	fr20,fr36,fcc0,cc0,0
1464	test_fcc	0xb,0
1465	set_fcc         0xb,0		; Set mask opposite of expected
1466	cfcmps      	fr20,fr40,fcc0,cc0,0
1467	test_fcc	0xb,0
1468	set_fcc         0xb,0		; Set mask opposite of expected
1469	cfcmps      	fr20,fr44,fcc0,cc0,0
1470	test_fcc	0xb,0
1471	set_fcc         0xb,0		; Set mask opposite of expected
1472	cfcmps      	fr20,fr48,fcc0,cc0,0
1473	test_fcc	0xb,0
1474	set_fcc         0xb,0		; Set mask opposite of expected
1475	cfcmps      	fr20,fr52,fcc0,cc0,0
1476	test_fcc	0xb,0
1477	set_fcc         0xe,0		; Set mask opposite of expected
1478	cfcmps      	fr20,fr56,fcc0,cc0,0
1479	test_fcc	0xe,0
1480	set_fcc         0xe,0		; Set mask opposite of expected
1481	cfcmps      	fr20,fr60,fcc0,cc0,0
1482	test_fcc	0xe,0
1483
1484	set_fcc         0xd,0		; Set mask opposite of expected
1485	cfcmps      	fr24,fr0,fcc0,cc4,0
1486	test_fcc	0xd,0
1487	set_fcc         0xd,0		; Set mask opposite of expected
1488	cfcmps      	fr24,fr4,fcc0,cc4,0
1489	test_fcc	0xd,0
1490	set_fcc         0xd,0		; Set mask opposite of expected
1491	cfcmps      	fr24,fr8,fcc0,cc4,0
1492	test_fcc	0xd,0
1493	set_fcc         0xd,0		; Set mask opposite of expected
1494	cfcmps      	fr24,fr12,fcc0,cc4,0
1495	test_fcc	0xd,0
1496	set_fcc         0xd,0		; Set mask opposite of expected
1497	cfcmps      	fr24,fr16,fcc0,cc4,0
1498	test_fcc	0xd,0
1499	set_fcc         0xd,0		; Set mask opposite of expected
1500	cfcmps      	fr24,fr20,fcc0,cc4,0
1501	test_fcc	0xd,0
1502	set_fcc         0x7,0		; Set mask opposite of expected
1503	cfcmps      	fr24,fr24,fcc0,cc4,0
1504	test_fcc	0x7,0
1505	set_fcc         0xb,0		; Set mask opposite of expected
1506	cfcmps      	fr24,fr28,fcc0,cc4,0
1507	test_fcc	0xb,0
1508	set_fcc         0xb,0		; Set mask opposite of expected
1509	cfcmps      	fr24,fr32,fcc0,cc4,0
1510	test_fcc	0xb,0
1511	set_fcc         0xb,0		; Set mask opposite of expected
1512	cfcmps      	fr24,fr36,fcc0,cc4,0
1513	test_fcc	0xb,0
1514	set_fcc         0xb,0		; Set mask opposite of expected
1515	cfcmps      	fr24,fr40,fcc0,cc4,0
1516	test_fcc	0xb,0
1517	set_fcc         0xb,0		; Set mask opposite of expected
1518	cfcmps      	fr24,fr44,fcc0,cc4,0
1519	test_fcc	0xb,0
1520	set_fcc         0xb,0		; Set mask opposite of expected
1521	cfcmps      	fr24,fr48,fcc0,cc4,0
1522	test_fcc	0xb,0
1523	set_fcc         0xb,0		; Set mask opposite of expected
1524	cfcmps      	fr24,fr52,fcc0,cc4,0
1525	test_fcc	0xb,0
1526	set_fcc         0xe,0		; Set mask opposite of expected
1527	cfcmps      	fr24,fr56,fcc0,cc4,0
1528	test_fcc	0xe,0
1529	set_fcc         0xe,0		; Set mask opposite of expected
1530	cfcmps      	fr24,fr60,fcc0,cc4,0
1531	test_fcc	0xe,0
1532
1533	set_fcc         0xd,0		; Set mask opposite of expected
1534	cfcmps      	fr28,fr0,fcc0,cc4,0
1535	test_fcc	0xd,0
1536	set_fcc         0xd,0		; Set mask opposite of expected
1537	cfcmps      	fr28,fr4,fcc0,cc4,0
1538	test_fcc	0xd,0
1539	set_fcc         0xd,0		; Set mask opposite of expected
1540	cfcmps      	fr28,fr8,fcc0,cc4,0
1541	test_fcc	0xd,0
1542	set_fcc         0xd,0		; Set mask opposite of expected
1543	cfcmps      	fr28,fr12,fcc0,cc4,0
1544	test_fcc	0xd,0
1545	set_fcc         0xd,0		; Set mask opposite of expected
1546	cfcmps      	fr28,fr16,fcc0,cc4,0
1547	test_fcc	0xd,0
1548	set_fcc         0xd,0		; Set mask opposite of expected
1549	cfcmps      	fr28,fr20,fcc0,cc4,0
1550	test_fcc	0xd,0
1551	set_fcc         0xd,0		; Set mask opposite of expected
1552	cfcmps      	fr28,fr24,fcc0,cc4,0
1553	test_fcc	0xd,0
1554	set_fcc         0x7,0		; Set mask opposite of expected
1555	cfcmps      	fr28,fr28,fcc0,cc4,0
1556	test_fcc	0x7,0
1557	set_fcc         0xb,0		; Set mask opposite of expected
1558	cfcmps      	fr28,fr32,fcc0,cc4,0
1559	test_fcc	0xb,0
1560	set_fcc         0xb,0		; Set mask opposite of expected
1561	cfcmps      	fr28,fr36,fcc0,cc4,0
1562	test_fcc	0xb,0
1563	set_fcc         0xb,0		; Set mask opposite of expected
1564	cfcmps      	fr28,fr40,fcc0,cc4,0
1565	test_fcc	0xb,0
1566	set_fcc         0xb,0		; Set mask opposite of expected
1567	cfcmps      	fr28,fr44,fcc0,cc4,0
1568	test_fcc	0xb,0
1569	set_fcc         0xb,0		; Set mask opposite of expected
1570	cfcmps      	fr28,fr48,fcc0,cc4,0
1571	test_fcc	0xb,0
1572	set_fcc         0xb,0		; Set mask opposite of expected
1573	cfcmps      	fr28,fr52,fcc0,cc4,0
1574	test_fcc	0xb,0
1575	set_fcc         0xe,0		; Set mask opposite of expected
1576	cfcmps      	fr28,fr56,fcc0,cc4,0
1577	test_fcc	0xe,0
1578	set_fcc         0xe,0		; Set mask opposite of expected
1579	cfcmps      	fr28,fr60,fcc0,cc4,0
1580	test_fcc	0xe,0
1581
1582	set_fcc         0xd,0		; Set mask opposite of expected
1583	cfcmps      	fr48,fr0,fcc0,cc4,0
1584	test_fcc	0xd,0
1585	set_fcc         0xd,0		; Set mask opposite of expected
1586	cfcmps      	fr48,fr4,fcc0,cc4,0
1587	test_fcc	0xd,0
1588	set_fcc         0xd,0		; Set mask opposite of expected
1589	cfcmps      	fr48,fr8,fcc0,cc4,0
1590	test_fcc	0xd,0
1591	set_fcc         0xd,0		; Set mask opposite of expected
1592	cfcmps      	fr48,fr12,fcc0,cc4,0
1593	test_fcc	0xd,0
1594	set_fcc         0xd,0		; Set mask opposite of expected
1595	cfcmps      	fr48,fr16,fcc0,cc4,0
1596	test_fcc	0xd,0
1597	set_fcc         0xd,0		; Set mask opposite of expected
1598	cfcmps      	fr48,fr20,fcc0,cc4,0
1599	test_fcc	0xd,0
1600	set_fcc         0xd,0		; Set mask opposite of expected
1601	cfcmps      	fr48,fr24,fcc0,cc4,0
1602	test_fcc	0xd,0
1603	set_fcc         0xd,0		; Set mask opposite of expected
1604	cfcmps      	fr48,fr28,fcc0,cc4,0
1605	test_fcc	0xd,0
1606	set_fcc         0xd,0		; Set mask opposite of expected
1607	cfcmps      	fr48,fr32,fcc0,cc4,0
1608	test_fcc	0xd,0
1609	set_fcc         0xd,0		; Set mask opposite of expected
1610	cfcmps      	fr48,fr36,fcc0,cc4,0
1611	test_fcc	0xd,0
1612	set_fcc         0xd,0		; Set mask opposite of expected
1613	cfcmps      	fr48,fr40,fcc0,cc4,0
1614	test_fcc	0xd,0
1615	set_fcc         0xd,0		; Set mask opposite of expected
1616	cfcmps      	fr48,fr44,fcc0,cc4,0
1617	test_fcc	0xd,0
1618	set_fcc         0x7,0		; Set mask opposite of expected
1619	cfcmps      	fr48,fr48,fcc0,cc4,0
1620	test_fcc	0x7,0
1621	set_fcc         0xb,0		; Set mask opposite of expected
1622	cfcmps      	fr48,fr52,fcc0,cc4,0
1623	test_fcc	0xb,0
1624	set_fcc         0xe,0		; Set mask opposite of expected
1625	cfcmps      	fr48,fr56,fcc0,cc4,0
1626	test_fcc	0xe,0
1627	set_fcc         0xe,0		; Set mask opposite of expected
1628	cfcmps      	fr48,fr60,fcc0,cc4,0
1629	test_fcc	0xe,0
1630
1631	set_fcc         0xd,0		; Set mask opposite of expected
1632	cfcmps      	fr52,fr0,fcc0,cc4,0
1633	test_fcc	0xd,0
1634	set_fcc         0xd,0		; Set mask opposite of expected
1635	cfcmps      	fr52,fr4,fcc0,cc4,0
1636	test_fcc	0xd,0
1637	set_fcc         0xd,0		; Set mask opposite of expected
1638	cfcmps      	fr52,fr8,fcc0,cc4,0
1639	test_fcc	0xd,0
1640	set_fcc         0xd,0		; Set mask opposite of expected
1641	cfcmps      	fr52,fr12,fcc0,cc4,0
1642	test_fcc	0xd,0
1643	set_fcc         0xd,0		; Set mask opposite of expected
1644	cfcmps      	fr52,fr16,fcc0,cc4,0
1645	test_fcc	0xd,0
1646	set_fcc         0xd,0		; Set mask opposite of expected
1647	cfcmps      	fr52,fr20,fcc0,cc4,0
1648	test_fcc	0xd,0
1649	set_fcc         0xd,0		; Set mask opposite of expected
1650	cfcmps      	fr52,fr24,fcc0,cc4,0
1651	test_fcc	0xd,0
1652	set_fcc         0xd,0		; Set mask opposite of expected
1653	cfcmps      	fr52,fr28,fcc0,cc4,0
1654	test_fcc	0xd,0
1655	set_fcc         0xd,0		; Set mask opposite of expected
1656	cfcmps      	fr52,fr32,fcc0,cc4,0
1657	test_fcc	0xd,0
1658	set_fcc         0xd,0		; Set mask opposite of expected
1659	cfcmps      	fr52,fr36,fcc0,cc4,0
1660	test_fcc	0xd,0
1661	set_fcc         0xd,0		; Set mask opposite of expected
1662	cfcmps      	fr52,fr40,fcc0,cc4,0
1663	test_fcc	0xd,0
1664	set_fcc         0xd,0		; Set mask opposite of expected
1665	cfcmps      	fr52,fr44,fcc0,cc4,0
1666	test_fcc	0xd,0
1667	set_fcc         0xd,0		; Set mask opposite of expected
1668	cfcmps      	fr52,fr48,fcc0,cc4,0
1669	test_fcc	0xd,0
1670	set_fcc         0x7,0		; Set mask opposite of expected
1671	cfcmps      	fr52,fr52,fcc0,cc4,0
1672	test_fcc	0x7,0
1673	set_fcc         0xe,0		; Set mask opposite of expected
1674	cfcmps      	fr52,fr56,fcc0,cc4,0
1675	test_fcc	0xe,0
1676	set_fcc         0xe,0		; Set mask opposite of expected
1677	cfcmps      	fr52,fr60,fcc0,cc4,0
1678	test_fcc	0xe,0
1679
1680	set_fcc         0xe,0		; Set mask opposite of expected
1681	cfcmps      	fr56,fr0,fcc0,cc4,0
1682	test_fcc	0xe,0
1683	set_fcc         0xe,0		; Set mask opposite of expected
1684	cfcmps      	fr56,fr4,fcc0,cc4,0
1685	test_fcc	0xe,0
1686	set_fcc         0xe,0		; Set mask opposite of expected
1687	cfcmps      	fr56,fr8,fcc0,cc4,0
1688	test_fcc	0xe,0
1689	set_fcc         0xe,0		; Set mask opposite of expected
1690	cfcmps      	fr56,fr12,fcc0,cc4,0
1691	test_fcc	0xe,0
1692	set_fcc         0xe,0		; Set mask opposite of expected
1693	cfcmps      	fr56,fr16,fcc0,cc4,0
1694	test_fcc	0xe,0
1695	set_fcc         0xe,0		; Set mask opposite of expected
1696	cfcmps      	fr56,fr20,fcc0,cc4,0
1697	test_fcc	0xe,0
1698	set_fcc         0xe,0		; Set mask opposite of expected
1699	cfcmps      	fr56,fr24,fcc0,cc4,0
1700	test_fcc	0xe,0
1701	set_fcc         0xe,0		; Set mask opposite of expected
1702	cfcmps      	fr56,fr28,fcc0,cc4,0
1703	test_fcc	0xe,0
1704	set_fcc         0xe,0		; Set mask opposite of expected
1705	cfcmps      	fr56,fr32,fcc0,cc4,0
1706	test_fcc	0xe,0
1707	set_fcc         0xe,0		; Set mask opposite of expected
1708	cfcmps      	fr56,fr36,fcc0,cc4,0
1709	test_fcc	0xe,0
1710	set_fcc         0xe,0		; Set mask opposite of expected
1711	cfcmps      	fr56,fr40,fcc0,cc4,0
1712	test_fcc	0xe,0
1713	set_fcc         0xe,0		; Set mask opposite of expected
1714	cfcmps      	fr56,fr44,fcc0,cc4,0
1715	test_fcc	0xe,0
1716	set_fcc         0xe,0		; Set mask opposite of expected
1717	cfcmps      	fr56,fr48,fcc0,cc4,0
1718	test_fcc	0xe,0
1719	set_fcc         0xe,0		; Set mask opposite of expected
1720	cfcmps      	fr56,fr52,fcc0,cc4,0
1721	test_fcc	0xe,0
1722	set_fcc         0xe,0		; Set mask opposite of expected
1723	cfcmps      	fr56,fr56,fcc0,cc4,0
1724	test_fcc	0xe,0
1725	set_fcc         0xe,0		; Set mask opposite of expected
1726	cfcmps      	fr56,fr60,fcc0,cc4,0
1727	test_fcc	0xe,0
1728
1729	set_fcc         0xe,0		; Set mask opposite of expected
1730	cfcmps      	fr60,fr0,fcc0,cc4,0
1731	test_fcc	0xe,0
1732	set_fcc         0xe,0		; Set mask opposite of expected
1733	cfcmps      	fr60,fr4,fcc0,cc4,0
1734	test_fcc	0xe,0
1735	set_fcc         0xe,0		; Set mask opposite of expected
1736	cfcmps      	fr60,fr8,fcc0,cc4,0
1737	test_fcc	0xe,0
1738	set_fcc         0xe,0		; Set mask opposite of expected
1739	cfcmps      	fr60,fr12,fcc0,cc4,0
1740	test_fcc	0xe,0
1741	set_fcc         0xe,0		; Set mask opposite of expected
1742	cfcmps      	fr60,fr16,fcc0,cc4,0
1743	test_fcc	0xe,0
1744	set_fcc         0xe,0		; Set mask opposite of expected
1745	cfcmps      	fr60,fr20,fcc0,cc4,0
1746	test_fcc	0xe,0
1747	set_fcc         0xe,0		; Set mask opposite of expected
1748	cfcmps      	fr60,fr24,fcc0,cc4,0
1749	test_fcc	0xe,0
1750	set_fcc         0xe,0		; Set mask opposite of expected
1751	cfcmps      	fr60,fr28,fcc0,cc4,0
1752	test_fcc	0xe,0
1753	set_fcc         0xe,0		; Set mask opposite of expected
1754	cfcmps      	fr60,fr32,fcc0,cc4,0
1755	test_fcc	0xe,0
1756	set_fcc         0xe,0		; Set mask opposite of expected
1757	cfcmps      	fr60,fr36,fcc0,cc4,0
1758	test_fcc	0xe,0
1759	set_fcc         0xe,0		; Set mask opposite of expected
1760	cfcmps      	fr60,fr40,fcc0,cc4,0
1761	test_fcc	0xe,0
1762	set_fcc         0xe,0		; Set mask opposite of expected
1763	cfcmps      	fr60,fr44,fcc0,cc4,0
1764	test_fcc	0xe,0
1765	set_fcc         0xe,0		; Set mask opposite of expected
1766	cfcmps      	fr60,fr48,fcc0,cc4,0
1767	test_fcc	0xe,0
1768	set_fcc         0xe,0		; Set mask opposite of expected
1769	cfcmps      	fr60,fr52,fcc0,cc4,0
1770	test_fcc	0xe,0
1771	set_fcc         0xe,0		; Set mask opposite of expected
1772	cfcmps      	fr60,fr56,fcc0,cc4,0
1773	test_fcc	0xe,0
1774	set_fcc         0xe,0		; Set mask opposite of expected
1775	cfcmps      	fr60,fr60,fcc0,cc4,0
1776	test_fcc	0xe,0
1777;
1778	set_fcc         0x7,0		; Set mask opposite of expected
1779	cfcmps      	fr0,fr0,fcc0,cc1,1
1780	test_fcc	0x7,0
1781	set_fcc         0xb,0		; Set mask opposite of expected
1782	cfcmps      	fr0,fr4,fcc0,cc1,1
1783	test_fcc	0xb,0
1784	set_fcc         0xb,0		; Set mask opposite of expected
1785	cfcmps      	fr0,fr8,fcc0,cc1,1
1786	test_fcc	0xb,0
1787	set_fcc         0xb,0		; Set mask opposite of expected
1788	cfcmps      	fr0,fr12,fcc0,cc1,1
1789	test_fcc	0xb,0
1790	set_fcc         0xb,0		; Set mask opposite of expected
1791	cfcmps      	fr0,fr16,fcc0,cc1,1
1792	test_fcc	0xb,0
1793	set_fcc         0xb,0		; Set mask opposite of expected
1794	cfcmps      	fr0,fr20,fcc0,cc1,1
1795	test_fcc	0xb,0
1796	set_fcc         0xb,0		; Set mask opposite of expected
1797	cfcmps      	fr0,fr24,fcc0,cc1,1
1798	test_fcc	0xb,0
1799	set_fcc         0xb,0		; Set mask opposite of expected
1800	cfcmps      	fr0,fr28,fcc0,cc1,1
1801	test_fcc	0xb,0
1802	set_fcc         0xb,0		; Set mask opposite of expected
1803	cfcmps      	fr0,fr32,fcc0,cc1,1
1804	test_fcc	0xb,0
1805	set_fcc         0xb,0		; Set mask opposite of expected
1806	cfcmps      	fr0,fr36,fcc0,cc1,1
1807	test_fcc	0xb,0
1808	set_fcc         0xb,0		; Set mask opposite of expected
1809	cfcmps      	fr0,fr40,fcc0,cc1,1
1810	test_fcc	0xb,0
1811	set_fcc         0xb,0		; Set mask opposite of expected
1812	cfcmps      	fr0,fr44,fcc0,cc1,1
1813	test_fcc	0xb,0
1814	set_fcc         0xb,0		; Set mask opposite of expected
1815	cfcmps      	fr0,fr48,fcc0,cc1,1
1816	test_fcc	0xb,0
1817	set_fcc         0xb,0		; Set mask opposite of expected
1818	cfcmps      	fr0,fr52,fcc0,cc1,1
1819	test_fcc	0xb,0
1820	set_fcc         0xe,0		; Set mask opposite of expected
1821	cfcmps      	fr0,fr56,fcc0,cc1,1
1822	test_fcc	0xe,0
1823	set_fcc         0xe,0		; Set mask opposite of expected
1824	cfcmps      	fr0,fr60,fcc0,cc1,1
1825	test_fcc	0xe,0
1826
1827	set_fcc         0xd,0		; Set mask opposite of expected
1828	cfcmps      	fr4,fr0,fcc0,cc1,1
1829	test_fcc	0xd,0
1830	set_fcc         0x7,0		; Set mask opposite of expected
1831	cfcmps      	fr4,fr4,fcc0,cc1,1
1832	test_fcc	0x7,0
1833	set_fcc         0xb,0		; Set mask opposite of expected
1834	cfcmps      	fr4,fr8,fcc0,cc1,1
1835	test_fcc	0xb,0
1836	set_fcc         0xb,0		; Set mask opposite of expected
1837	cfcmps      	fr4,fr12,fcc0,cc1,1
1838	test_fcc	0xb,0
1839	set_fcc         0xb,0		; Set mask opposite of expected
1840	cfcmps      	fr4,fr16,fcc0,cc1,1
1841	test_fcc	0xb,0
1842	set_fcc         0xb,0		; Set mask opposite of expected
1843	cfcmps      	fr4,fr20,fcc0,cc1,1
1844	test_fcc	0xb,0
1845	set_fcc         0xb,0		; Set mask opposite of expected
1846	cfcmps      	fr4,fr24,fcc0,cc1,1
1847	test_fcc	0xb,0
1848	set_fcc         0xb,0		; Set mask opposite of expected
1849	cfcmps      	fr4,fr28,fcc0,cc1,1
1850	test_fcc	0xb,0
1851	set_fcc         0xb,0		; Set mask opposite of expected
1852	cfcmps      	fr4,fr32,fcc0,cc1,1
1853	test_fcc	0xb,0
1854	set_fcc         0xb,0		; Set mask opposite of expected
1855	cfcmps      	fr4,fr36,fcc0,cc1,1
1856	test_fcc	0xb,0
1857	set_fcc         0xb,0		; Set mask opposite of expected
1858	cfcmps      	fr4,fr40,fcc0,cc1,1
1859	test_fcc	0xb,0
1860	set_fcc         0xb,0		; Set mask opposite of expected
1861	cfcmps      	fr4,fr44,fcc0,cc1,1
1862	test_fcc	0xb,0
1863	set_fcc         0xb,0		; Set mask opposite of expected
1864	cfcmps      	fr4,fr48,fcc0,cc1,1
1865	test_fcc	0xb,0
1866	set_fcc         0xb,0		; Set mask opposite of expected
1867	cfcmps      	fr4,fr52,fcc0,cc1,1
1868	test_fcc	0xb,0
1869	set_fcc         0xe,0		; Set mask opposite of expected
1870	cfcmps      	fr4,fr56,fcc0,cc1,1
1871	test_fcc	0xe,0
1872	set_fcc         0xe,0		; Set mask opposite of expected
1873	cfcmps      	fr4,fr60,fcc0,cc1,1
1874	test_fcc	0xe,0
1875
1876	set_fcc         0xd,0		; Set mask opposite of expected
1877	cfcmps      	fr8,fr0,fcc0,cc1,1
1878	test_fcc	0xd,0
1879	set_fcc         0xd,0		; Set mask opposite of expected
1880	cfcmps      	fr8,fr4,fcc0,cc1,1
1881	test_fcc	0xd,0
1882	set_fcc         0x7,0		; Set mask opposite of expected
1883	cfcmps      	fr8,fr8,fcc0,cc1,1
1884	test_fcc	0x7,0
1885	set_fcc         0xb,0		; Set mask opposite of expected
1886	cfcmps      	fr8,fr12,fcc0,cc1,1
1887	test_fcc	0xb,0
1888	set_fcc         0xb,0		; Set mask opposite of expected
1889	cfcmps      	fr8,fr16,fcc0,cc1,1
1890	test_fcc	0xb,0
1891	set_fcc         0xb,0		; Set mask opposite of expected
1892	cfcmps      	fr8,fr20,fcc0,cc1,1
1893	test_fcc	0xb,0
1894	set_fcc         0xb,0		; Set mask opposite of expected
1895	cfcmps      	fr8,fr24,fcc0,cc1,1
1896	test_fcc	0xb,0
1897	set_fcc         0xb,0		; Set mask opposite of expected
1898	cfcmps      	fr8,fr28,fcc0,cc1,1
1899	test_fcc	0xb,0
1900	set_fcc         0xb,0		; Set mask opposite of expected
1901	cfcmps      	fr8,fr32,fcc0,cc1,1
1902	test_fcc	0xb,0
1903	set_fcc         0xb,0		; Set mask opposite of expected
1904	cfcmps      	fr8,fr36,fcc0,cc1,1
1905	test_fcc	0xb,0
1906	set_fcc         0xb,0		; Set mask opposite of expected
1907	cfcmps      	fr8,fr40,fcc0,cc1,1
1908	test_fcc	0xb,0
1909	set_fcc         0xb,0		; Set mask opposite of expected
1910	cfcmps      	fr8,fr44,fcc0,cc1,1
1911	test_fcc	0xb,0
1912	set_fcc         0xb,0		; Set mask opposite of expected
1913	cfcmps      	fr8,fr48,fcc0,cc1,1
1914	test_fcc	0xb,0
1915	set_fcc         0xb,0		; Set mask opposite of expected
1916	cfcmps      	fr8,fr52,fcc0,cc1,1
1917	test_fcc	0xb,0
1918	set_fcc         0xe,0		; Set mask opposite of expected
1919	cfcmps      	fr8,fr56,fcc0,cc1,1
1920	test_fcc	0xe,0
1921	set_fcc         0xe,0		; Set mask opposite of expected
1922	cfcmps      	fr8,fr60,fcc0,cc1,1
1923	test_fcc	0xe,0
1924
1925	set_fcc         0xd,0		; Set mask opposite of expected
1926	cfcmps      	fr12,fr0,fcc0,cc1,1
1927	test_fcc	0xd,0
1928	set_fcc         0xd,0		; Set mask opposite of expected
1929	cfcmps      	fr12,fr4,fcc0,cc1,1
1930	test_fcc	0xd,0
1931	set_fcc         0xd,0		; Set mask opposite of expected
1932	cfcmps      	fr12,fr8,fcc0,cc1,1
1933	test_fcc	0xd,0
1934	set_fcc         0x7,0		; Set mask opposite of expected
1935	cfcmps      	fr12,fr12,fcc0,cc1,1
1936	test_fcc	0x7,0
1937	set_fcc         0xb,0		; Set mask opposite of expected
1938	cfcmps      	fr12,fr16,fcc0,cc1,1
1939	test_fcc	0xb,0
1940	set_fcc         0xb,0		; Set mask opposite of expected
1941	cfcmps      	fr12,fr20,fcc0,cc1,1
1942	test_fcc	0xb,0
1943	set_fcc         0xb,0		; Set mask opposite of expected
1944	cfcmps      	fr12,fr24,fcc0,cc1,1
1945	test_fcc	0xb,0
1946	set_fcc         0xb,0		; Set mask opposite of expected
1947	cfcmps      	fr12,fr28,fcc0,cc1,1
1948	test_fcc	0xb,0
1949	set_fcc         0xb,0		; Set mask opposite of expected
1950	cfcmps      	fr12,fr32,fcc0,cc1,1
1951	test_fcc	0xb,0
1952	set_fcc         0xb,0		; Set mask opposite of expected
1953	cfcmps      	fr12,fr36,fcc0,cc1,1
1954	test_fcc	0xb,0
1955	set_fcc         0xb,0		; Set mask opposite of expected
1956	cfcmps      	fr12,fr40,fcc0,cc1,1
1957	test_fcc	0xb,0
1958	set_fcc         0xb,0		; Set mask opposite of expected
1959	cfcmps      	fr12,fr44,fcc0,cc1,1
1960	test_fcc	0xb,0
1961	set_fcc         0xb,0		; Set mask opposite of expected
1962	cfcmps      	fr12,fr48,fcc0,cc1,1
1963	test_fcc	0xb,0
1964	set_fcc         0xb,0		; Set mask opposite of expected
1965	cfcmps      	fr12,fr52,fcc0,cc1,1
1966	test_fcc	0xb,0
1967	set_fcc         0xe,0		; Set mask opposite of expected
1968	cfcmps      	fr12,fr56,fcc0,cc1,1
1969	test_fcc	0xe,0
1970	set_fcc         0xe,0		; Set mask opposite of expected
1971	cfcmps      	fr12,fr60,fcc0,cc1,1
1972	test_fcc	0xe,0
1973
1974	set_fcc         0xd,0		; Set mask opposite of expected
1975	cfcmps      	fr16,fr0,fcc0,cc1,1
1976	test_fcc	0xd,0
1977	set_fcc         0xd,0		; Set mask opposite of expected
1978	cfcmps      	fr16,fr4,fcc0,cc1,1
1979	test_fcc	0xd,0
1980	set_fcc         0xd,0		; Set mask opposite of expected
1981	cfcmps      	fr16,fr8,fcc0,cc1,1
1982	test_fcc	0xd,0
1983	set_fcc         0xd,0		; Set mask opposite of expected
1984	cfcmps      	fr16,fr12,fcc0,cc1,1
1985	test_fcc	0xd,0
1986	set_fcc         0x7,0		; Set mask opposite of expected
1987	cfcmps      	fr16,fr16,fcc0,cc1,1
1988	test_fcc	0x7,0
1989	set_fcc         0x7,0		; Set mask opposite of expected
1990	cfcmps      	fr16,fr20,fcc0,cc1,1
1991	test_fcc	0x7,0
1992	set_fcc         0xb,0		; Set mask opposite of expected
1993	cfcmps      	fr16,fr24,fcc0,cc1,1
1994	test_fcc	0xb,0
1995	set_fcc         0xb,0		; Set mask opposite of expected
1996	cfcmps      	fr16,fr28,fcc0,cc1,1
1997	test_fcc	0xb,0
1998	set_fcc         0xb,0		; Set mask opposite of expected
1999	cfcmps      	fr16,fr32,fcc0,cc1,1
2000	test_fcc	0xb,0
2001	set_fcc         0xb,0		; Set mask opposite of expected
2002	cfcmps      	fr16,fr36,fcc0,cc1,1
2003	test_fcc	0xb,0
2004	set_fcc         0xb,0		; Set mask opposite of expected
2005	cfcmps      	fr16,fr40,fcc0,cc1,1
2006	test_fcc	0xb,0
2007	set_fcc         0xb,0		; Set mask opposite of expected
2008	cfcmps      	fr16,fr44,fcc0,cc1,1
2009	test_fcc	0xb,0
2010	set_fcc         0xb,0		; Set mask opposite of expected
2011	cfcmps      	fr16,fr48,fcc0,cc1,1
2012	test_fcc	0xb,0
2013	set_fcc         0xb,0		; Set mask opposite of expected
2014	cfcmps      	fr16,fr52,fcc0,cc1,1
2015	test_fcc	0xb,0
2016	set_fcc         0xe,0		; Set mask opposite of expected
2017	cfcmps      	fr16,fr56,fcc0,cc1,1
2018	test_fcc	0xe,0
2019	set_fcc         0xe,0		; Set mask opposite of expected
2020	cfcmps      	fr16,fr60,fcc0,cc1,1
2021	test_fcc	0xe,0
2022
2023	set_fcc         0xd,0		; Set mask opposite of expected
2024	cfcmps      	fr20,fr0,fcc0,cc1,1
2025	test_fcc	0xd,0
2026	set_fcc         0xd,0		; Set mask opposite of expected
2027	cfcmps      	fr20,fr4,fcc0,cc1,1
2028	test_fcc	0xd,0
2029	set_fcc         0xd,0		; Set mask opposite of expected
2030	cfcmps      	fr20,fr8,fcc0,cc1,1
2031	test_fcc	0xd,0
2032	set_fcc         0xd,0		; Set mask opposite of expected
2033	cfcmps      	fr20,fr12,fcc0,cc1,1
2034	test_fcc	0xd,0
2035	set_fcc         0x7,0		; Set mask opposite of expected
2036	cfcmps      	fr20,fr16,fcc0,cc1,1
2037	test_fcc	0x7,0
2038	set_fcc         0x7,0		; Set mask opposite of expected
2039	cfcmps      	fr20,fr20,fcc0,cc1,1
2040	test_fcc	0x7,0
2041	set_fcc         0xb,0		; Set mask opposite of expected
2042	cfcmps      	fr20,fr24,fcc0,cc1,1
2043	test_fcc	0xb,0
2044	set_fcc         0xb,0		; Set mask opposite of expected
2045	cfcmps      	fr20,fr28,fcc0,cc1,1
2046	test_fcc	0xb,0
2047	set_fcc         0xb,0		; Set mask opposite of expected
2048	cfcmps      	fr20,fr32,fcc0,cc1,1
2049	test_fcc	0xb,0
2050	set_fcc         0xb,0		; Set mask opposite of expected
2051	cfcmps      	fr20,fr36,fcc0,cc1,1
2052	test_fcc	0xb,0
2053	set_fcc         0xb,0		; Set mask opposite of expected
2054	cfcmps      	fr20,fr40,fcc0,cc1,1
2055	test_fcc	0xb,0
2056	set_fcc         0xb,0		; Set mask opposite of expected
2057	cfcmps      	fr20,fr44,fcc0,cc1,1
2058	test_fcc	0xb,0
2059	set_fcc         0xb,0		; Set mask opposite of expected
2060	cfcmps      	fr20,fr48,fcc0,cc1,1
2061	test_fcc	0xb,0
2062	set_fcc         0xb,0		; Set mask opposite of expected
2063	cfcmps      	fr20,fr52,fcc0,cc1,1
2064	test_fcc	0xb,0
2065	set_fcc         0xe,0		; Set mask opposite of expected
2066	cfcmps      	fr20,fr56,fcc0,cc1,1
2067	test_fcc	0xe,0
2068	set_fcc         0xe,0		; Set mask opposite of expected
2069	cfcmps      	fr20,fr60,fcc0,cc1,1
2070	test_fcc	0xe,0
2071
2072	set_fcc         0xd,0		; Set mask opposite of expected
2073	cfcmps      	fr24,fr0,fcc0,cc5,1
2074	test_fcc	0xd,0
2075	set_fcc         0xd,0		; Set mask opposite of expected
2076	cfcmps      	fr24,fr4,fcc0,cc5,1
2077	test_fcc	0xd,0
2078	set_fcc         0xd,0		; Set mask opposite of expected
2079	cfcmps      	fr24,fr8,fcc0,cc5,1
2080	test_fcc	0xd,0
2081	set_fcc         0xd,0		; Set mask opposite of expected
2082	cfcmps      	fr24,fr12,fcc0,cc5,1
2083	test_fcc	0xd,0
2084	set_fcc         0xd,0		; Set mask opposite of expected
2085	cfcmps      	fr24,fr16,fcc0,cc5,1
2086	test_fcc	0xd,0
2087	set_fcc         0xd,0		; Set mask opposite of expected
2088	cfcmps      	fr24,fr20,fcc0,cc5,1
2089	test_fcc	0xd,0
2090	set_fcc         0x7,0		; Set mask opposite of expected
2091	cfcmps      	fr24,fr24,fcc0,cc5,1
2092	test_fcc	0x7,0
2093	set_fcc         0xb,0		; Set mask opposite of expected
2094	cfcmps      	fr24,fr28,fcc0,cc5,1
2095	test_fcc	0xb,0
2096	set_fcc         0xb,0		; Set mask opposite of expected
2097	cfcmps      	fr24,fr32,fcc0,cc5,1
2098	test_fcc	0xb,0
2099	set_fcc         0xb,0		; Set mask opposite of expected
2100	cfcmps      	fr24,fr36,fcc0,cc5,1
2101	test_fcc	0xb,0
2102	set_fcc         0xb,0		; Set mask opposite of expected
2103	cfcmps      	fr24,fr40,fcc0,cc5,1
2104	test_fcc	0xb,0
2105	set_fcc         0xb,0		; Set mask opposite of expected
2106	cfcmps      	fr24,fr44,fcc0,cc5,1
2107	test_fcc	0xb,0
2108	set_fcc         0xb,0		; Set mask opposite of expected
2109	cfcmps      	fr24,fr48,fcc0,cc5,1
2110	test_fcc	0xb,0
2111	set_fcc         0xb,0		; Set mask opposite of expected
2112	cfcmps      	fr24,fr52,fcc0,cc5,1
2113	test_fcc	0xb,0
2114	set_fcc         0xe,0		; Set mask opposite of expected
2115	cfcmps      	fr24,fr56,fcc0,cc5,1
2116	test_fcc	0xe,0
2117	set_fcc         0xe,0		; Set mask opposite of expected
2118	cfcmps      	fr24,fr60,fcc0,cc5,1
2119	test_fcc	0xe,0
2120
2121	set_fcc         0xd,0		; Set mask opposite of expected
2122	cfcmps      	fr28,fr0,fcc0,cc5,1
2123	test_fcc	0xd,0
2124	set_fcc         0xd,0		; Set mask opposite of expected
2125	cfcmps      	fr28,fr4,fcc0,cc5,1
2126	test_fcc	0xd,0
2127	set_fcc         0xd,0		; Set mask opposite of expected
2128	cfcmps      	fr28,fr8,fcc0,cc5,1
2129	test_fcc	0xd,0
2130	set_fcc         0xd,0		; Set mask opposite of expected
2131	cfcmps      	fr28,fr12,fcc0,cc5,1
2132	test_fcc	0xd,0
2133	set_fcc         0xd,0		; Set mask opposite of expected
2134	cfcmps      	fr28,fr16,fcc0,cc5,1
2135	test_fcc	0xd,0
2136	set_fcc         0xd,0		; Set mask opposite of expected
2137	cfcmps      	fr28,fr20,fcc0,cc5,1
2138	test_fcc	0xd,0
2139	set_fcc         0xd,0		; Set mask opposite of expected
2140	cfcmps      	fr28,fr24,fcc0,cc5,1
2141	test_fcc	0xd,0
2142	set_fcc         0x7,0		; Set mask opposite of expected
2143	cfcmps      	fr28,fr28,fcc0,cc5,1
2144	test_fcc	0x7,0
2145	set_fcc         0xb,0		; Set mask opposite of expected
2146	cfcmps      	fr28,fr32,fcc0,cc5,1
2147	test_fcc	0xb,0
2148	set_fcc         0xb,0		; Set mask opposite of expected
2149	cfcmps      	fr28,fr36,fcc0,cc5,1
2150	test_fcc	0xb,0
2151	set_fcc         0xb,0		; Set mask opposite of expected
2152	cfcmps      	fr28,fr40,fcc0,cc5,1
2153	test_fcc	0xb,0
2154	set_fcc         0xb,0		; Set mask opposite of expected
2155	cfcmps      	fr28,fr44,fcc0,cc5,1
2156	test_fcc	0xb,0
2157	set_fcc         0xb,0		; Set mask opposite of expected
2158	cfcmps      	fr28,fr48,fcc0,cc5,1
2159	test_fcc	0xb,0
2160	set_fcc         0xb,0		; Set mask opposite of expected
2161	cfcmps      	fr28,fr52,fcc0,cc5,1
2162	test_fcc	0xb,0
2163	set_fcc         0xe,0		; Set mask opposite of expected
2164	cfcmps      	fr28,fr56,fcc0,cc5,1
2165	test_fcc	0xe,0
2166	set_fcc         0xe,0		; Set mask opposite of expected
2167	cfcmps      	fr28,fr60,fcc0,cc5,1
2168	test_fcc	0xe,0
2169
2170	set_fcc         0xd,0		; Set mask opposite of expected
2171	cfcmps      	fr48,fr0,fcc0,cc5,1
2172	test_fcc	0xd,0
2173	set_fcc         0xd,0		; Set mask opposite of expected
2174	cfcmps      	fr48,fr4,fcc0,cc5,1
2175	test_fcc	0xd,0
2176	set_fcc         0xd,0		; Set mask opposite of expected
2177	cfcmps      	fr48,fr8,fcc0,cc5,1
2178	test_fcc	0xd,0
2179	set_fcc         0xd,0		; Set mask opposite of expected
2180	cfcmps      	fr48,fr12,fcc0,cc5,1
2181	test_fcc	0xd,0
2182	set_fcc         0xd,0		; Set mask opposite of expected
2183	cfcmps      	fr48,fr16,fcc0,cc5,1
2184	test_fcc	0xd,0
2185	set_fcc         0xd,0		; Set mask opposite of expected
2186	cfcmps      	fr48,fr20,fcc0,cc5,1
2187	test_fcc	0xd,0
2188	set_fcc         0xd,0		; Set mask opposite of expected
2189	cfcmps      	fr48,fr24,fcc0,cc5,1
2190	test_fcc	0xd,0
2191	set_fcc         0xd,0		; Set mask opposite of expected
2192	cfcmps      	fr48,fr28,fcc0,cc5,1
2193	test_fcc	0xd,0
2194	set_fcc         0xd,0		; Set mask opposite of expected
2195	cfcmps      	fr48,fr32,fcc0,cc5,1
2196	test_fcc	0xd,0
2197	set_fcc         0xd,0		; Set mask opposite of expected
2198	cfcmps      	fr48,fr36,fcc0,cc5,1
2199	test_fcc	0xd,0
2200	set_fcc         0xd,0		; Set mask opposite of expected
2201	cfcmps      	fr48,fr40,fcc0,cc5,1
2202	test_fcc	0xd,0
2203	set_fcc         0xd,0		; Set mask opposite of expected
2204	cfcmps      	fr48,fr44,fcc0,cc5,1
2205	test_fcc	0xd,0
2206	set_fcc         0x7,0		; Set mask opposite of expected
2207	cfcmps      	fr48,fr48,fcc0,cc5,1
2208	test_fcc	0x7,0
2209	set_fcc         0xb,0		; Set mask opposite of expected
2210	cfcmps      	fr48,fr52,fcc0,cc5,1
2211	test_fcc	0xb,0
2212	set_fcc         0xe,0		; Set mask opposite of expected
2213	cfcmps      	fr48,fr56,fcc0,cc5,1
2214	test_fcc	0xe,0
2215	set_fcc         0xe,0		; Set mask opposite of expected
2216	cfcmps      	fr48,fr60,fcc0,cc5,1
2217	test_fcc	0xe,0
2218
2219	set_fcc         0xd,0		; Set mask opposite of expected
2220	cfcmps      	fr52,fr0,fcc0,cc5,1
2221	test_fcc	0xd,0
2222	set_fcc         0xd,0		; Set mask opposite of expected
2223	cfcmps      	fr52,fr4,fcc0,cc5,1
2224	test_fcc	0xd,0
2225	set_fcc         0xd,0		; Set mask opposite of expected
2226	cfcmps      	fr52,fr8,fcc0,cc5,1
2227	test_fcc	0xd,0
2228	set_fcc         0xd,0		; Set mask opposite of expected
2229	cfcmps      	fr52,fr12,fcc0,cc5,1
2230	test_fcc	0xd,0
2231	set_fcc         0xd,0		; Set mask opposite of expected
2232	cfcmps      	fr52,fr16,fcc0,cc5,1
2233	test_fcc	0xd,0
2234	set_fcc         0xd,0		; Set mask opposite of expected
2235	cfcmps      	fr52,fr20,fcc0,cc5,1
2236	test_fcc	0xd,0
2237	set_fcc         0xd,0		; Set mask opposite of expected
2238	cfcmps      	fr52,fr24,fcc0,cc5,1
2239	test_fcc	0xd,0
2240	set_fcc         0xd,0		; Set mask opposite of expected
2241	cfcmps      	fr52,fr28,fcc0,cc5,1
2242	test_fcc	0xd,0
2243	set_fcc         0xd,0		; Set mask opposite of expected
2244	cfcmps      	fr52,fr32,fcc0,cc5,1
2245	test_fcc	0xd,0
2246	set_fcc         0xd,0		; Set mask opposite of expected
2247	cfcmps      	fr52,fr36,fcc0,cc5,1
2248	test_fcc	0xd,0
2249	set_fcc         0xd,0		; Set mask opposite of expected
2250	cfcmps      	fr52,fr40,fcc0,cc5,1
2251	test_fcc	0xd,0
2252	set_fcc         0xd,0		; Set mask opposite of expected
2253	cfcmps      	fr52,fr44,fcc0,cc5,1
2254	test_fcc	0xd,0
2255	set_fcc         0xd,0		; Set mask opposite of expected
2256	cfcmps      	fr52,fr48,fcc0,cc5,1
2257	test_fcc	0xd,0
2258	set_fcc         0x7,0		; Set mask opposite of expected
2259	cfcmps      	fr52,fr52,fcc0,cc5,1
2260	test_fcc	0x7,0
2261	set_fcc         0xe,0		; Set mask opposite of expected
2262	cfcmps      	fr52,fr56,fcc0,cc5,1
2263	test_fcc	0xe,0
2264	set_fcc         0xe,0		; Set mask opposite of expected
2265	cfcmps      	fr52,fr60,fcc0,cc5,1
2266	test_fcc	0xe,0
2267
2268	set_fcc         0xe,0		; Set mask opposite of expected
2269	cfcmps      	fr56,fr0,fcc0,cc5,1
2270	test_fcc	0xe,0
2271	set_fcc         0xe,0		; Set mask opposite of expected
2272	cfcmps      	fr56,fr4,fcc0,cc5,1
2273	test_fcc	0xe,0
2274	set_fcc         0xe,0		; Set mask opposite of expected
2275	cfcmps      	fr56,fr8,fcc0,cc5,1
2276	test_fcc	0xe,0
2277	set_fcc         0xe,0		; Set mask opposite of expected
2278	cfcmps      	fr56,fr12,fcc0,cc5,1
2279	test_fcc	0xe,0
2280	set_fcc         0xe,0		; Set mask opposite of expected
2281	cfcmps      	fr56,fr16,fcc0,cc5,1
2282	test_fcc	0xe,0
2283	set_fcc         0xe,0		; Set mask opposite of expected
2284	cfcmps      	fr56,fr20,fcc0,cc5,1
2285	test_fcc	0xe,0
2286	set_fcc         0xe,0		; Set mask opposite of expected
2287	cfcmps      	fr56,fr24,fcc0,cc5,1
2288	test_fcc	0xe,0
2289	set_fcc         0xe,0		; Set mask opposite of expected
2290	cfcmps      	fr56,fr28,fcc0,cc5,1
2291	test_fcc	0xe,0
2292	set_fcc         0xe,0		; Set mask opposite of expected
2293	cfcmps      	fr56,fr32,fcc0,cc5,1
2294	test_fcc	0xe,0
2295	set_fcc         0xe,0		; Set mask opposite of expected
2296	cfcmps      	fr56,fr36,fcc0,cc5,1
2297	test_fcc	0xe,0
2298	set_fcc         0xe,0		; Set mask opposite of expected
2299	cfcmps      	fr56,fr40,fcc0,cc5,1
2300	test_fcc	0xe,0
2301	set_fcc         0xe,0		; Set mask opposite of expected
2302	cfcmps      	fr56,fr44,fcc0,cc5,1
2303	test_fcc	0xe,0
2304	set_fcc         0xe,0		; Set mask opposite of expected
2305	cfcmps      	fr56,fr48,fcc0,cc5,1
2306	test_fcc	0xe,0
2307	set_fcc         0xe,0		; Set mask opposite of expected
2308	cfcmps      	fr56,fr52,fcc0,cc5,1
2309	test_fcc	0xe,0
2310	set_fcc         0xe,0		; Set mask opposite of expected
2311	cfcmps      	fr56,fr56,fcc0,cc5,1
2312	test_fcc	0xe,0
2313	set_fcc         0xe,0		; Set mask opposite of expected
2314	cfcmps      	fr56,fr60,fcc0,cc5,1
2315	test_fcc	0xe,0
2316
2317	set_fcc         0xe,0		; Set mask opposite of expected
2318	cfcmps      	fr60,fr0,fcc0,cc5,1
2319	test_fcc	0xe,0
2320	set_fcc         0xe,0		; Set mask opposite of expected
2321	cfcmps      	fr60,fr4,fcc0,cc5,1
2322	test_fcc	0xe,0
2323	set_fcc         0xe,0		; Set mask opposite of expected
2324	cfcmps      	fr60,fr8,fcc0,cc5,1
2325	test_fcc	0xe,0
2326	set_fcc         0xe,0		; Set mask opposite of expected
2327	cfcmps      	fr60,fr12,fcc0,cc5,1
2328	test_fcc	0xe,0
2329	set_fcc         0xe,0		; Set mask opposite of expected
2330	cfcmps      	fr60,fr16,fcc0,cc5,1
2331	test_fcc	0xe,0
2332	set_fcc         0xe,0		; Set mask opposite of expected
2333	cfcmps      	fr60,fr20,fcc0,cc5,1
2334	test_fcc	0xe,0
2335	set_fcc         0xe,0		; Set mask opposite of expected
2336	cfcmps      	fr60,fr24,fcc0,cc5,1
2337	test_fcc	0xe,0
2338	set_fcc         0xe,0		; Set mask opposite of expected
2339	cfcmps      	fr60,fr28,fcc0,cc5,1
2340	test_fcc	0xe,0
2341	set_fcc         0xe,0		; Set mask opposite of expected
2342	cfcmps      	fr60,fr32,fcc0,cc5,1
2343	test_fcc	0xe,0
2344	set_fcc         0xe,0		; Set mask opposite of expected
2345	cfcmps      	fr60,fr36,fcc0,cc5,1
2346	test_fcc	0xe,0
2347	set_fcc         0xe,0		; Set mask opposite of expected
2348	cfcmps      	fr60,fr40,fcc0,cc5,1
2349	test_fcc	0xe,0
2350	set_fcc         0xe,0		; Set mask opposite of expected
2351	cfcmps      	fr60,fr44,fcc0,cc5,1
2352	test_fcc	0xe,0
2353	set_fcc         0xe,0		; Set mask opposite of expected
2354	cfcmps      	fr60,fr48,fcc0,cc5,1
2355	test_fcc	0xe,0
2356	set_fcc         0xe,0		; Set mask opposite of expected
2357	cfcmps      	fr60,fr52,fcc0,cc5,1
2358	test_fcc	0xe,0
2359	set_fcc         0xe,0		; Set mask opposite of expected
2360	cfcmps      	fr60,fr56,fcc0,cc5,1
2361	test_fcc	0xe,0
2362	set_fcc         0xe,0		; Set mask opposite of expected
2363	cfcmps      	fr60,fr60,fcc0,cc5,1
2364	test_fcc	0xe,0
2365;
2366	set_fcc         0x7,0		; Set mask opposite of expected
2367	cfcmps      	fr0,fr0,fcc0,cc2,1
2368	test_fcc	0x7,0
2369	set_fcc         0xb,0		; Set mask opposite of expected
2370	cfcmps      	fr0,fr4,fcc0,cc2,0
2371	test_fcc	0xb,0
2372	set_fcc         0xb,0		; Set mask opposite of expected
2373	cfcmps      	fr0,fr8,fcc0,cc2,1
2374	test_fcc	0xb,0
2375	set_fcc         0xb,0		; Set mask opposite of expected
2376	cfcmps      	fr0,fr12,fcc0,cc2,0
2377	test_fcc	0xb,0
2378	set_fcc         0xb,0		; Set mask opposite of expected
2379	cfcmps      	fr0,fr16,fcc0,cc2,1
2380	test_fcc	0xb,0
2381	set_fcc         0xb,0		; Set mask opposite of expected
2382	cfcmps      	fr0,fr20,fcc0,cc2,0
2383	test_fcc	0xb,0
2384	set_fcc         0xb,0		; Set mask opposite of expected
2385	cfcmps      	fr0,fr24,fcc0,cc2,1
2386	test_fcc	0xb,0
2387	set_fcc         0xb,0		; Set mask opposite of expected
2388	cfcmps      	fr0,fr28,fcc0,cc2,0
2389	test_fcc	0xb,0
2390	set_fcc         0xb,0		; Set mask opposite of expected
2391	cfcmps      	fr0,fr32,fcc0,cc2,1
2392	test_fcc	0xb,0
2393	set_fcc         0xb,0		; Set mask opposite of expected
2394	cfcmps      	fr0,fr36,fcc0,cc2,0
2395	test_fcc	0xb,0
2396	set_fcc         0xb,0		; Set mask opposite of expected
2397	cfcmps      	fr0,fr40,fcc0,cc2,1
2398	test_fcc	0xb,0
2399	set_fcc         0xb,0		; Set mask opposite of expected
2400	cfcmps      	fr0,fr44,fcc0,cc2,0
2401	test_fcc	0xb,0
2402	set_fcc         0xb,0		; Set mask opposite of expected
2403	cfcmps      	fr0,fr48,fcc0,cc2,1
2404	test_fcc	0xb,0
2405	set_fcc         0xb,0		; Set mask opposite of expected
2406	cfcmps      	fr0,fr52,fcc0,cc2,0
2407	test_fcc	0xb,0
2408	set_fcc         0xe,0		; Set mask opposite of expected
2409	cfcmps      	fr0,fr56,fcc0,cc2,1
2410	test_fcc	0xe,0
2411	set_fcc         0xe,0		; Set mask opposite of expected
2412	cfcmps      	fr0,fr60,fcc0,cc2,0
2413	test_fcc	0xe,0
2414
2415	set_fcc         0xd,0		; Set mask opposite of expected
2416	cfcmps      	fr4,fr0,fcc0,cc2,1
2417	test_fcc	0xd,0
2418	set_fcc         0x7,0		; Set mask opposite of expected
2419	cfcmps      	fr4,fr4,fcc0,cc2,0
2420	test_fcc	0x7,0
2421	set_fcc         0xb,0		; Set mask opposite of expected
2422	cfcmps      	fr4,fr8,fcc0,cc2,1
2423	test_fcc	0xb,0
2424	set_fcc         0xb,0		; Set mask opposite of expected
2425	cfcmps      	fr4,fr12,fcc0,cc2,0
2426	test_fcc	0xb,0
2427	set_fcc         0xb,0		; Set mask opposite of expected
2428	cfcmps      	fr4,fr16,fcc0,cc2,1
2429	test_fcc	0xb,0
2430	set_fcc         0xb,0		; Set mask opposite of expected
2431	cfcmps      	fr4,fr20,fcc0,cc2,0
2432	test_fcc	0xb,0
2433	set_fcc         0xb,0		; Set mask opposite of expected
2434	cfcmps      	fr4,fr24,fcc0,cc2,1
2435	test_fcc	0xb,0
2436	set_fcc         0xb,0		; Set mask opposite of expected
2437	cfcmps      	fr4,fr28,fcc0,cc2,0
2438	test_fcc	0xb,0
2439	set_fcc         0xb,0		; Set mask opposite of expected
2440	cfcmps      	fr4,fr32,fcc0,cc2,1
2441	test_fcc	0xb,0
2442	set_fcc         0xb,0		; Set mask opposite of expected
2443	cfcmps      	fr4,fr36,fcc0,cc2,0
2444	test_fcc	0xb,0
2445	set_fcc         0xb,0		; Set mask opposite of expected
2446	cfcmps      	fr4,fr40,fcc0,cc2,1
2447	test_fcc	0xb,0
2448	set_fcc         0xb,0		; Set mask opposite of expected
2449	cfcmps      	fr4,fr44,fcc0,cc2,0
2450	test_fcc	0xb,0
2451	set_fcc         0xb,0		; Set mask opposite of expected
2452	cfcmps      	fr4,fr48,fcc0,cc2,1
2453	test_fcc	0xb,0
2454	set_fcc         0xb,0		; Set mask opposite of expected
2455	cfcmps      	fr4,fr52,fcc0,cc2,0
2456	test_fcc	0xb,0
2457	set_fcc         0xe,0		; Set mask opposite of expected
2458	cfcmps      	fr4,fr56,fcc0,cc2,1
2459	test_fcc	0xe,0
2460	set_fcc         0xe,0		; Set mask opposite of expected
2461	cfcmps      	fr4,fr60,fcc0,cc2,0
2462	test_fcc	0xe,0
2463
2464	set_fcc         0xd,0		; Set mask opposite of expected
2465	cfcmps      	fr8,fr0,fcc0,cc2,1
2466	test_fcc	0xd,0
2467	set_fcc         0xd,0		; Set mask opposite of expected
2468	cfcmps      	fr8,fr4,fcc0,cc2,0
2469	test_fcc	0xd,0
2470	set_fcc         0x7,0		; Set mask opposite of expected
2471	cfcmps      	fr8,fr8,fcc0,cc2,1
2472	test_fcc	0x7,0
2473	set_fcc         0xb,0		; Set mask opposite of expected
2474	cfcmps      	fr8,fr12,fcc0,cc2,0
2475	test_fcc	0xb,0
2476	set_fcc         0xb,0		; Set mask opposite of expected
2477	cfcmps      	fr8,fr16,fcc0,cc2,1
2478	test_fcc	0xb,0
2479	set_fcc         0xb,0		; Set mask opposite of expected
2480	cfcmps      	fr8,fr20,fcc0,cc2,0
2481	test_fcc	0xb,0
2482	set_fcc         0xb,0		; Set mask opposite of expected
2483	cfcmps      	fr8,fr24,fcc0,cc2,1
2484	test_fcc	0xb,0
2485	set_fcc         0xb,0		; Set mask opposite of expected
2486	cfcmps      	fr8,fr28,fcc0,cc2,0
2487	test_fcc	0xb,0
2488	set_fcc         0xb,0		; Set mask opposite of expected
2489	cfcmps      	fr8,fr32,fcc0,cc2,1
2490	test_fcc	0xb,0
2491	set_fcc         0xb,0		; Set mask opposite of expected
2492	cfcmps      	fr8,fr36,fcc0,cc2,0
2493	test_fcc	0xb,0
2494	set_fcc         0xb,0		; Set mask opposite of expected
2495	cfcmps      	fr8,fr40,fcc0,cc2,1
2496	test_fcc	0xb,0
2497	set_fcc         0xb,0		; Set mask opposite of expected
2498	cfcmps      	fr8,fr44,fcc0,cc2,0
2499	test_fcc	0xb,0
2500	set_fcc         0xb,0		; Set mask opposite of expected
2501	cfcmps      	fr8,fr48,fcc0,cc2,1
2502	test_fcc	0xb,0
2503	set_fcc         0xb,0		; Set mask opposite of expected
2504	cfcmps      	fr8,fr52,fcc0,cc2,0
2505	test_fcc	0xb,0
2506	set_fcc         0xe,0		; Set mask opposite of expected
2507	cfcmps      	fr8,fr56,fcc0,cc2,1
2508	test_fcc	0xe,0
2509	set_fcc         0xe,0		; Set mask opposite of expected
2510	cfcmps      	fr8,fr60,fcc0,cc2,0
2511	test_fcc	0xe,0
2512
2513	set_fcc         0xd,0		; Set mask opposite of expected
2514	cfcmps      	fr12,fr0,fcc0,cc2,1
2515	test_fcc	0xd,0
2516	set_fcc         0xd,0		; Set mask opposite of expected
2517	cfcmps      	fr12,fr4,fcc0,cc2,0
2518	test_fcc	0xd,0
2519	set_fcc         0xd,0		; Set mask opposite of expected
2520	cfcmps      	fr12,fr8,fcc0,cc2,1
2521	test_fcc	0xd,0
2522	set_fcc         0x7,0		; Set mask opposite of expected
2523	cfcmps      	fr12,fr12,fcc0,cc2,0
2524	test_fcc	0x7,0
2525	set_fcc         0xb,0		; Set mask opposite of expected
2526	cfcmps      	fr12,fr16,fcc0,cc2,1
2527	test_fcc	0xb,0
2528	set_fcc         0xb,0		; Set mask opposite of expected
2529	cfcmps      	fr12,fr20,fcc0,cc2,0
2530	test_fcc	0xb,0
2531	set_fcc         0xb,0		; Set mask opposite of expected
2532	cfcmps      	fr12,fr24,fcc0,cc2,1
2533	test_fcc	0xb,0
2534	set_fcc         0xb,0		; Set mask opposite of expected
2535	cfcmps      	fr12,fr28,fcc0,cc2,0
2536	test_fcc	0xb,0
2537	set_fcc         0xb,0		; Set mask opposite of expected
2538	cfcmps      	fr12,fr32,fcc0,cc2,1
2539	test_fcc	0xb,0
2540	set_fcc         0xb,0		; Set mask opposite of expected
2541	cfcmps      	fr12,fr36,fcc0,cc2,0
2542	test_fcc	0xb,0
2543	set_fcc         0xb,0		; Set mask opposite of expected
2544	cfcmps      	fr12,fr40,fcc0,cc2,1
2545	test_fcc	0xb,0
2546	set_fcc         0xb,0		; Set mask opposite of expected
2547	cfcmps      	fr12,fr44,fcc0,cc2,0
2548	test_fcc	0xb,0
2549	set_fcc         0xb,0		; Set mask opposite of expected
2550	cfcmps      	fr12,fr48,fcc0,cc2,1
2551	test_fcc	0xb,0
2552	set_fcc         0xb,0		; Set mask opposite of expected
2553	cfcmps      	fr12,fr52,fcc0,cc2,0
2554	test_fcc	0xb,0
2555	set_fcc         0xe,0		; Set mask opposite of expected
2556	cfcmps      	fr12,fr56,fcc0,cc2,1
2557	test_fcc	0xe,0
2558	set_fcc         0xe,0		; Set mask opposite of expected
2559	cfcmps      	fr12,fr60,fcc0,cc2,0
2560	test_fcc	0xe,0
2561
2562	set_fcc         0xd,0		; Set mask opposite of expected
2563	cfcmps      	fr16,fr0,fcc0,cc2,1
2564	test_fcc	0xd,0
2565	set_fcc         0xd,0		; Set mask opposite of expected
2566	cfcmps      	fr16,fr4,fcc0,cc2,0
2567	test_fcc	0xd,0
2568	set_fcc         0xd,0		; Set mask opposite of expected
2569	cfcmps      	fr16,fr8,fcc0,cc2,1
2570	test_fcc	0xd,0
2571	set_fcc         0xd,0		; Set mask opposite of expected
2572	cfcmps      	fr16,fr12,fcc0,cc2,0
2573	test_fcc	0xd,0
2574	set_fcc         0x7,0		; Set mask opposite of expected
2575	cfcmps      	fr16,fr16,fcc0,cc2,1
2576	test_fcc	0x7,0
2577	set_fcc         0x7,0		; Set mask opposite of expected
2578	cfcmps      	fr16,fr20,fcc0,cc2,0
2579	test_fcc	0x7,0
2580	set_fcc         0xb,0		; Set mask opposite of expected
2581	cfcmps      	fr16,fr24,fcc0,cc2,1
2582	test_fcc	0xb,0
2583	set_fcc         0xb,0		; Set mask opposite of expected
2584	cfcmps      	fr16,fr28,fcc0,cc2,0
2585	test_fcc	0xb,0
2586	set_fcc         0xb,0		; Set mask opposite of expected
2587	cfcmps      	fr16,fr32,fcc0,cc2,1
2588	test_fcc	0xb,0
2589	set_fcc         0xb,0		; Set mask opposite of expected
2590	cfcmps      	fr16,fr36,fcc0,cc2,0
2591	test_fcc	0xb,0
2592	set_fcc         0xb,0		; Set mask opposite of expected
2593	cfcmps      	fr16,fr40,fcc0,cc2,1
2594	test_fcc	0xb,0
2595	set_fcc         0xb,0		; Set mask opposite of expected
2596	cfcmps      	fr16,fr44,fcc0,cc2,0
2597	test_fcc	0xb,0
2598	set_fcc         0xb,0		; Set mask opposite of expected
2599	cfcmps      	fr16,fr48,fcc0,cc2,1
2600	test_fcc	0xb,0
2601	set_fcc         0xb,0		; Set mask opposite of expected
2602	cfcmps      	fr16,fr52,fcc0,cc2,0
2603	test_fcc	0xb,0
2604	set_fcc         0xe,0		; Set mask opposite of expected
2605	cfcmps      	fr16,fr56,fcc0,cc2,1
2606	test_fcc	0xe,0
2607	set_fcc         0xe,0		; Set mask opposite of expected
2608	cfcmps      	fr16,fr60,fcc0,cc2,0
2609	test_fcc	0xe,0
2610
2611	set_fcc         0xd,0		; Set mask opposite of expected
2612	cfcmps      	fr20,fr0,fcc0,cc2,1
2613	test_fcc	0xd,0
2614	set_fcc         0xd,0		; Set mask opposite of expected
2615	cfcmps      	fr20,fr4,fcc0,cc2,0
2616	test_fcc	0xd,0
2617	set_fcc         0xd,0		; Set mask opposite of expected
2618	cfcmps      	fr20,fr8,fcc0,cc2,1
2619	test_fcc	0xd,0
2620	set_fcc         0xd,0		; Set mask opposite of expected
2621	cfcmps      	fr20,fr12,fcc0,cc2,0
2622	test_fcc	0xd,0
2623	set_fcc         0x7,0		; Set mask opposite of expected
2624	cfcmps      	fr20,fr16,fcc0,cc2,1
2625	test_fcc	0x7,0
2626	set_fcc         0x7,0		; Set mask opposite of expected
2627	cfcmps      	fr20,fr20,fcc0,cc2,0
2628	test_fcc	0x7,0
2629	set_fcc         0xb,0		; Set mask opposite of expected
2630	cfcmps      	fr20,fr24,fcc0,cc2,1
2631	test_fcc	0xb,0
2632	set_fcc         0xb,0		; Set mask opposite of expected
2633	cfcmps      	fr20,fr28,fcc0,cc2,0
2634	test_fcc	0xb,0
2635	set_fcc         0xb,0		; Set mask opposite of expected
2636	cfcmps      	fr20,fr32,fcc0,cc2,1
2637	test_fcc	0xb,0
2638	set_fcc         0xb,0		; Set mask opposite of expected
2639	cfcmps      	fr20,fr36,fcc0,cc2,0
2640	test_fcc	0xb,0
2641	set_fcc         0xb,0		; Set mask opposite of expected
2642	cfcmps      	fr20,fr40,fcc0,cc2,1
2643	test_fcc	0xb,0
2644	set_fcc         0xb,0		; Set mask opposite of expected
2645	cfcmps      	fr20,fr44,fcc0,cc2,0
2646	test_fcc	0xb,0
2647	set_fcc         0xb,0		; Set mask opposite of expected
2648	cfcmps      	fr20,fr48,fcc0,cc2,1
2649	test_fcc	0xb,0
2650	set_fcc         0xb,0		; Set mask opposite of expected
2651	cfcmps      	fr20,fr52,fcc0,cc2,0
2652	test_fcc	0xb,0
2653	set_fcc         0xe,0		; Set mask opposite of expected
2654	cfcmps      	fr20,fr56,fcc0,cc2,1
2655	test_fcc	0xe,0
2656	set_fcc         0xe,0		; Set mask opposite of expected
2657	cfcmps      	fr20,fr60,fcc0,cc2,0
2658	test_fcc	0xe,0
2659
2660	set_fcc         0xd,0		; Set mask opposite of expected
2661	cfcmps      	fr24,fr0,fcc0,cc6,1
2662	test_fcc	0xd,0
2663	set_fcc         0xd,0		; Set mask opposite of expected
2664	cfcmps      	fr24,fr4,fcc0,cc6,0
2665	test_fcc	0xd,0
2666	set_fcc         0xd,0		; Set mask opposite of expected
2667	cfcmps      	fr24,fr8,fcc0,cc6,1
2668	test_fcc	0xd,0
2669	set_fcc         0xd,0		; Set mask opposite of expected
2670	cfcmps      	fr24,fr12,fcc0,cc6,0
2671	test_fcc	0xd,0
2672	set_fcc         0xd,0		; Set mask opposite of expected
2673	cfcmps      	fr24,fr16,fcc0,cc6,1
2674	test_fcc	0xd,0
2675	set_fcc         0xd,0		; Set mask opposite of expected
2676	cfcmps      	fr24,fr20,fcc0,cc6,0
2677	test_fcc	0xd,0
2678	set_fcc         0x7,0		; Set mask opposite of expected
2679	cfcmps      	fr24,fr24,fcc0,cc6,1
2680	test_fcc	0x7,0
2681	set_fcc         0xb,0		; Set mask opposite of expected
2682	cfcmps      	fr24,fr28,fcc0,cc6,0
2683	test_fcc	0xb,0
2684	set_fcc         0xb,0		; Set mask opposite of expected
2685	cfcmps      	fr24,fr32,fcc0,cc6,1
2686	test_fcc	0xb,0
2687	set_fcc         0xb,0		; Set mask opposite of expected
2688	cfcmps      	fr24,fr36,fcc0,cc6,0
2689	test_fcc	0xb,0
2690	set_fcc         0xb,0		; Set mask opposite of expected
2691	cfcmps      	fr24,fr40,fcc0,cc6,1
2692	test_fcc	0xb,0
2693	set_fcc         0xb,0		; Set mask opposite of expected
2694	cfcmps      	fr24,fr44,fcc0,cc6,0
2695	test_fcc	0xb,0
2696	set_fcc         0xb,0		; Set mask opposite of expected
2697	cfcmps      	fr24,fr48,fcc0,cc6,1
2698	test_fcc	0xb,0
2699	set_fcc         0xb,0		; Set mask opposite of expected
2700	cfcmps      	fr24,fr52,fcc0,cc6,0
2701	test_fcc	0xb,0
2702	set_fcc         0xe,0		; Set mask opposite of expected
2703	cfcmps      	fr24,fr56,fcc0,cc6,1
2704	test_fcc	0xe,0
2705	set_fcc         0xe,0		; Set mask opposite of expected
2706	cfcmps      	fr24,fr60,fcc0,cc6,0
2707	test_fcc	0xe,0
2708
2709	set_fcc         0xd,0		; Set mask opposite of expected
2710	cfcmps      	fr28,fr0,fcc0,cc6,1
2711	test_fcc	0xd,0
2712	set_fcc         0xd,0		; Set mask opposite of expected
2713	cfcmps      	fr28,fr4,fcc0,cc6,0
2714	test_fcc	0xd,0
2715	set_fcc         0xd,0		; Set mask opposite of expected
2716	cfcmps      	fr28,fr8,fcc0,cc6,1
2717	test_fcc	0xd,0
2718	set_fcc         0xd,0		; Set mask opposite of expected
2719	cfcmps      	fr28,fr12,fcc0,cc6,0
2720	test_fcc	0xd,0
2721	set_fcc         0xd,0		; Set mask opposite of expected
2722	cfcmps      	fr28,fr16,fcc0,cc6,1
2723	test_fcc	0xd,0
2724	set_fcc         0xd,0		; Set mask opposite of expected
2725	cfcmps      	fr28,fr20,fcc0,cc6,0
2726	test_fcc	0xd,0
2727	set_fcc         0xd,0		; Set mask opposite of expected
2728	cfcmps      	fr28,fr24,fcc0,cc6,1
2729	test_fcc	0xd,0
2730	set_fcc         0x7,0		; Set mask opposite of expected
2731	cfcmps      	fr28,fr28,fcc0,cc6,0
2732	test_fcc	0x7,0
2733	set_fcc         0xb,0		; Set mask opposite of expected
2734	cfcmps      	fr28,fr32,fcc0,cc6,1
2735	test_fcc	0xb,0
2736	set_fcc         0xb,0		; Set mask opposite of expected
2737	cfcmps      	fr28,fr36,fcc0,cc6,0
2738	test_fcc	0xb,0
2739	set_fcc         0xb,0		; Set mask opposite of expected
2740	cfcmps      	fr28,fr40,fcc0,cc6,1
2741	test_fcc	0xb,0
2742	set_fcc         0xb,0		; Set mask opposite of expected
2743	cfcmps      	fr28,fr44,fcc0,cc6,0
2744	test_fcc	0xb,0
2745	set_fcc         0xb,0		; Set mask opposite of expected
2746	cfcmps      	fr28,fr48,fcc0,cc6,1
2747	test_fcc	0xb,0
2748	set_fcc         0xb,0		; Set mask opposite of expected
2749	cfcmps      	fr28,fr52,fcc0,cc6,0
2750	test_fcc	0xb,0
2751	set_fcc         0xe,0		; Set mask opposite of expected
2752	cfcmps      	fr28,fr56,fcc0,cc6,1
2753	test_fcc	0xe,0
2754	set_fcc         0xe,0		; Set mask opposite of expected
2755	cfcmps      	fr28,fr60,fcc0,cc6,0
2756	test_fcc	0xe,0
2757
2758	set_fcc         0xd,0		; Set mask opposite of expected
2759	cfcmps      	fr48,fr0,fcc0,cc6,1
2760	test_fcc	0xd,0
2761	set_fcc         0xd,0		; Set mask opposite of expected
2762	cfcmps      	fr48,fr4,fcc0,cc6,0
2763	test_fcc	0xd,0
2764	set_fcc         0xd,0		; Set mask opposite of expected
2765	cfcmps      	fr48,fr8,fcc0,cc6,1
2766	test_fcc	0xd,0
2767	set_fcc         0xd,0		; Set mask opposite of expected
2768	cfcmps      	fr48,fr12,fcc0,cc6,0
2769	test_fcc	0xd,0
2770	set_fcc         0xd,0		; Set mask opposite of expected
2771	cfcmps      	fr48,fr16,fcc0,cc6,1
2772	test_fcc	0xd,0
2773	set_fcc         0xd,0		; Set mask opposite of expected
2774	cfcmps      	fr48,fr20,fcc0,cc6,0
2775	test_fcc	0xd,0
2776	set_fcc         0xd,0		; Set mask opposite of expected
2777	cfcmps      	fr48,fr24,fcc0,cc6,1
2778	test_fcc	0xd,0
2779	set_fcc         0xd,0		; Set mask opposite of expected
2780	cfcmps      	fr48,fr28,fcc0,cc6,0
2781	test_fcc	0xd,0
2782	set_fcc         0xd,0		; Set mask opposite of expected
2783	cfcmps      	fr48,fr32,fcc0,cc6,1
2784	test_fcc	0xd,0
2785	set_fcc         0xd,0		; Set mask opposite of expected
2786	cfcmps      	fr48,fr36,fcc0,cc6,0
2787	test_fcc	0xd,0
2788	set_fcc         0xd,0		; Set mask opposite of expected
2789	cfcmps      	fr48,fr40,fcc0,cc6,1
2790	test_fcc	0xd,0
2791	set_fcc         0xd,0		; Set mask opposite of expected
2792	cfcmps      	fr48,fr44,fcc0,cc6,0
2793	test_fcc	0xd,0
2794	set_fcc         0x7,0		; Set mask opposite of expected
2795	cfcmps      	fr48,fr48,fcc0,cc6,1
2796	test_fcc	0x7,0
2797	set_fcc         0xb,0		; Set mask opposite of expected
2798	cfcmps      	fr48,fr52,fcc0,cc6,0
2799	test_fcc	0xb,0
2800	set_fcc         0xe,0		; Set mask opposite of expected
2801	cfcmps      	fr48,fr56,fcc0,cc6,1
2802	test_fcc	0xe,0
2803	set_fcc         0xe,0		; Set mask opposite of expected
2804	cfcmps      	fr48,fr60,fcc0,cc6,0
2805	test_fcc	0xe,0
2806
2807	set_fcc         0xd,0		; Set mask opposite of expected
2808	cfcmps      	fr52,fr0,fcc0,cc6,1
2809	test_fcc	0xd,0
2810	set_fcc         0xd,0		; Set mask opposite of expected
2811	cfcmps      	fr52,fr4,fcc0,cc6,0
2812	test_fcc	0xd,0
2813	set_fcc         0xd,0		; Set mask opposite of expected
2814	cfcmps      	fr52,fr8,fcc0,cc6,1
2815	test_fcc	0xd,0
2816	set_fcc         0xd,0		; Set mask opposite of expected
2817	cfcmps      	fr52,fr12,fcc0,cc6,0
2818	test_fcc	0xd,0
2819	set_fcc         0xd,0		; Set mask opposite of expected
2820	cfcmps      	fr52,fr16,fcc0,cc6,1
2821	test_fcc	0xd,0
2822	set_fcc         0xd,0		; Set mask opposite of expected
2823	cfcmps      	fr52,fr20,fcc0,cc6,0
2824	test_fcc	0xd,0
2825	set_fcc         0xd,0		; Set mask opposite of expected
2826	cfcmps      	fr52,fr24,fcc0,cc6,1
2827	test_fcc	0xd,0
2828	set_fcc         0xd,0		; Set mask opposite of expected
2829	cfcmps      	fr52,fr28,fcc0,cc6,0
2830	test_fcc	0xd,0
2831	set_fcc         0xd,0		; Set mask opposite of expected
2832	cfcmps      	fr52,fr32,fcc0,cc6,1
2833	test_fcc	0xd,0
2834	set_fcc         0xd,0		; Set mask opposite of expected
2835	cfcmps      	fr52,fr36,fcc0,cc6,0
2836	test_fcc	0xd,0
2837	set_fcc         0xd,0		; Set mask opposite of expected
2838	cfcmps      	fr52,fr40,fcc0,cc6,1
2839	test_fcc	0xd,0
2840	set_fcc         0xd,0		; Set mask opposite of expected
2841	cfcmps      	fr52,fr44,fcc0,cc6,0
2842	test_fcc	0xd,0
2843	set_fcc         0xd,0		; Set mask opposite of expected
2844	cfcmps      	fr52,fr48,fcc0,cc6,1
2845	test_fcc	0xd,0
2846	set_fcc         0x7,0		; Set mask opposite of expected
2847	cfcmps      	fr52,fr52,fcc0,cc6,0
2848	test_fcc	0x7,0
2849	set_fcc         0xe,0		; Set mask opposite of expected
2850	cfcmps      	fr52,fr56,fcc0,cc6,1
2851	test_fcc	0xe,0
2852	set_fcc         0xe,0		; Set mask opposite of expected
2853	cfcmps      	fr52,fr60,fcc0,cc6,0
2854	test_fcc	0xe,0
2855
2856	set_fcc         0xe,0		; Set mask opposite of expected
2857	cfcmps      	fr56,fr0,fcc0,cc6,1
2858	test_fcc	0xe,0
2859	set_fcc         0xe,0		; Set mask opposite of expected
2860	cfcmps      	fr56,fr4,fcc0,cc6,0
2861	test_fcc	0xe,0
2862	set_fcc         0xe,0		; Set mask opposite of expected
2863	cfcmps      	fr56,fr8,fcc0,cc6,1
2864	test_fcc	0xe,0
2865	set_fcc         0xe,0		; Set mask opposite of expected
2866	cfcmps      	fr56,fr12,fcc0,cc6,0
2867	test_fcc	0xe,0
2868	set_fcc         0xe,0		; Set mask opposite of expected
2869	cfcmps      	fr56,fr16,fcc0,cc6,1
2870	test_fcc	0xe,0
2871	set_fcc         0xe,0		; Set mask opposite of expected
2872	cfcmps      	fr56,fr20,fcc0,cc6,0
2873	test_fcc	0xe,0
2874	set_fcc         0xe,0		; Set mask opposite of expected
2875	cfcmps      	fr56,fr24,fcc0,cc6,1
2876	test_fcc	0xe,0
2877	set_fcc         0xe,0		; Set mask opposite of expected
2878	cfcmps      	fr56,fr28,fcc0,cc6,0
2879	test_fcc	0xe,0
2880	set_fcc         0xe,0		; Set mask opposite of expected
2881	cfcmps      	fr56,fr32,fcc0,cc6,1
2882	test_fcc	0xe,0
2883	set_fcc         0xe,0		; Set mask opposite of expected
2884	cfcmps      	fr56,fr36,fcc0,cc6,0
2885	test_fcc	0xe,0
2886	set_fcc         0xe,0		; Set mask opposite of expected
2887	cfcmps      	fr56,fr40,fcc0,cc6,1
2888	test_fcc	0xe,0
2889	set_fcc         0xe,0		; Set mask opposite of expected
2890	cfcmps      	fr56,fr44,fcc0,cc6,0
2891	test_fcc	0xe,0
2892	set_fcc         0xe,0		; Set mask opposite of expected
2893	cfcmps      	fr56,fr48,fcc0,cc6,1
2894	test_fcc	0xe,0
2895	set_fcc         0xe,0		; Set mask opposite of expected
2896	cfcmps      	fr56,fr52,fcc0,cc6,0
2897	test_fcc	0xe,0
2898	set_fcc         0xe,0		; Set mask opposite of expected
2899	cfcmps      	fr56,fr56,fcc0,cc6,1
2900	test_fcc	0xe,0
2901	set_fcc         0xe,0		; Set mask opposite of expected
2902	cfcmps      	fr56,fr60,fcc0,cc6,0
2903	test_fcc	0xe,0
2904
2905	set_fcc         0xe,0		; Set mask opposite of expected
2906	cfcmps      	fr60,fr0,fcc0,cc6,1
2907	test_fcc	0xe,0
2908	set_fcc         0xe,0		; Set mask opposite of expected
2909	cfcmps      	fr60,fr4,fcc0,cc6,0
2910	test_fcc	0xe,0
2911	set_fcc         0xe,0		; Set mask opposite of expected
2912	cfcmps      	fr60,fr8,fcc0,cc6,1
2913	test_fcc	0xe,0
2914	set_fcc         0xe,0		; Set mask opposite of expected
2915	cfcmps      	fr60,fr12,fcc0,cc6,1
2916	test_fcc	0xe,0
2917	set_fcc         0xe,0		; Set mask opposite of expected
2918	cfcmps      	fr60,fr16,fcc0,cc6,0
2919	test_fcc	0xe,0
2920	set_fcc         0xe,0		; Set mask opposite of expected
2921	cfcmps      	fr60,fr20,fcc0,cc6,1
2922	test_fcc	0xe,0
2923	set_fcc         0xe,0		; Set mask opposite of expected
2924	cfcmps      	fr60,fr24,fcc0,cc6,0
2925	test_fcc	0xe,0
2926	set_fcc         0xe,0		; Set mask opposite of expected
2927	cfcmps      	fr60,fr28,fcc0,cc6,1
2928	test_fcc	0xe,0
2929	set_fcc         0xe,0		; Set mask opposite of expected
2930	cfcmps      	fr60,fr32,fcc0,cc6,0
2931	test_fcc	0xe,0
2932	set_fcc         0xe,0		; Set mask opposite of expected
2933	cfcmps      	fr60,fr36,fcc0,cc6,1
2934	test_fcc	0xe,0
2935	set_fcc         0xe,0		; Set mask opposite of expected
2936	cfcmps      	fr60,fr40,fcc0,cc6,0
2937	test_fcc	0xe,0
2938	set_fcc         0xe,0		; Set mask opposite of expected
2939	cfcmps      	fr60,fr44,fcc0,cc6,1
2940	test_fcc	0xe,0
2941	set_fcc         0xe,0		; Set mask opposite of expected
2942	cfcmps      	fr60,fr48,fcc0,cc6,0
2943	test_fcc	0xe,0
2944	set_fcc         0xe,0		; Set mask opposite of expected
2945	cfcmps      	fr60,fr52,fcc0,cc6,1
2946	test_fcc	0xe,0
2947	set_fcc         0xe,0		; Set mask opposite of expected
2948	cfcmps      	fr60,fr56,fcc0,cc6,0
2949	test_fcc	0xe,0
2950	set_fcc         0xe,0		; Set mask opposite of expected
2951	cfcmps      	fr60,fr60,fcc0,cc6,1
2952	test_fcc	0xe,0
2953
2954	set_fcc         0x7,0		; Set mask opposite of expected
2955	cfcmps      	fr0,fr0,fcc0,cc3,1
2956	test_fcc	0x7,0
2957	set_fcc         0xb,0		; Set mask opposite of expected
2958	cfcmps      	fr0,fr4,fcc0,cc3,0
2959	test_fcc	0xb,0
2960	set_fcc         0xb,0		; Set mask opposite of expected
2961	cfcmps      	fr0,fr8,fcc0,cc3,1
2962	test_fcc	0xb,0
2963	set_fcc         0xb,0		; Set mask opposite of expected
2964	cfcmps      	fr0,fr12,fcc0,cc3,0
2965	test_fcc	0xb,0
2966	set_fcc         0xb,0		; Set mask opposite of expected
2967	cfcmps      	fr0,fr16,fcc0,cc3,1
2968	test_fcc	0xb,0
2969	set_fcc         0xb,0		; Set mask opposite of expected
2970	cfcmps      	fr0,fr20,fcc0,cc3,0
2971	test_fcc	0xb,0
2972	set_fcc         0xb,0		; Set mask opposite of expected
2973	cfcmps      	fr0,fr24,fcc0,cc3,1
2974	test_fcc	0xb,0
2975	set_fcc         0xb,0		; Set mask opposite of expected
2976	cfcmps      	fr0,fr28,fcc0,cc3,0
2977	test_fcc	0xb,0
2978	set_fcc         0xb,0		; Set mask opposite of expected
2979	cfcmps      	fr0,fr32,fcc0,cc3,1
2980	test_fcc	0xb,0
2981	set_fcc         0xb,0		; Set mask opposite of expected
2982	cfcmps      	fr0,fr36,fcc0,cc3,0
2983	test_fcc	0xb,0
2984	set_fcc         0xb,0		; Set mask opposite of expected
2985	cfcmps      	fr0,fr40,fcc0,cc3,1
2986	test_fcc	0xb,0
2987	set_fcc         0xb,0		; Set mask opposite of expected
2988	cfcmps      	fr0,fr44,fcc0,cc3,0
2989	test_fcc	0xb,0
2990	set_fcc         0xb,0		; Set mask opposite of expected
2991	cfcmps      	fr0,fr48,fcc0,cc3,1
2992	test_fcc	0xb,0
2993	set_fcc         0xb,0		; Set mask opposite of expected
2994	cfcmps      	fr0,fr52,fcc0,cc3,0
2995	test_fcc	0xb,0
2996	set_fcc         0xe,0		; Set mask opposite of expected
2997	cfcmps      	fr0,fr56,fcc0,cc3,1
2998	test_fcc	0xe,0
2999	set_fcc         0xe,0		; Set mask opposite of expected
3000	cfcmps      	fr0,fr60,fcc0,cc3,0
3001	test_fcc	0xe,0
3002
3003	set_fcc         0xd,0		; Set mask opposite of expected
3004	cfcmps      	fr4,fr0,fcc0,cc3,1
3005	test_fcc	0xd,0
3006	set_fcc         0x7,0		; Set mask opposite of expected
3007	cfcmps      	fr4,fr4,fcc0,cc3,0
3008	test_fcc	0x7,0
3009	set_fcc         0xb,0		; Set mask opposite of expected
3010	cfcmps      	fr4,fr8,fcc0,cc3,1
3011	test_fcc	0xb,0
3012	set_fcc         0xb,0		; Set mask opposite of expected
3013	cfcmps      	fr4,fr12,fcc0,cc3,0
3014	test_fcc	0xb,0
3015	set_fcc         0xb,0		; Set mask opposite of expected
3016	cfcmps      	fr4,fr16,fcc0,cc3,1
3017	test_fcc	0xb,0
3018	set_fcc         0xb,0		; Set mask opposite of expected
3019	cfcmps      	fr4,fr20,fcc0,cc3,0
3020	test_fcc	0xb,0
3021	set_fcc         0xb,0		; Set mask opposite of expected
3022	cfcmps      	fr4,fr24,fcc0,cc3,1
3023	test_fcc	0xb,0
3024	set_fcc         0xb,0		; Set mask opposite of expected
3025	cfcmps      	fr4,fr28,fcc0,cc3,0
3026	test_fcc	0xb,0
3027	set_fcc         0xb,0		; Set mask opposite of expected
3028	cfcmps      	fr4,fr32,fcc0,cc3,1
3029	test_fcc	0xb,0
3030	set_fcc         0xb,0		; Set mask opposite of expected
3031	cfcmps      	fr4,fr36,fcc0,cc3,0
3032	test_fcc	0xb,0
3033	set_fcc         0xb,0		; Set mask opposite of expected
3034	cfcmps      	fr4,fr40,fcc0,cc3,1
3035	test_fcc	0xb,0
3036	set_fcc         0xb,0		; Set mask opposite of expected
3037	cfcmps      	fr4,fr44,fcc0,cc3,0
3038	test_fcc	0xb,0
3039	set_fcc         0xb,0		; Set mask opposite of expected
3040	cfcmps      	fr4,fr48,fcc0,cc3,1
3041	test_fcc	0xb,0
3042	set_fcc         0xb,0		; Set mask opposite of expected
3043	cfcmps      	fr4,fr52,fcc0,cc3,0
3044	test_fcc	0xb,0
3045	set_fcc         0xe,0		; Set mask opposite of expected
3046	cfcmps      	fr4,fr56,fcc0,cc3,1
3047	test_fcc	0xe,0
3048	set_fcc         0xe,0		; Set mask opposite of expected
3049	cfcmps      	fr4,fr60,fcc0,cc3,0
3050	test_fcc	0xe,0
3051
3052	set_fcc         0xd,0		; Set mask opposite of expected
3053	cfcmps      	fr8,fr0,fcc0,cc3,1
3054	test_fcc	0xd,0
3055	set_fcc         0xd,0		; Set mask opposite of expected
3056	cfcmps      	fr8,fr4,fcc0,cc3,0
3057	test_fcc	0xd,0
3058	set_fcc         0x7,0		; Set mask opposite of expected
3059	cfcmps      	fr8,fr8,fcc0,cc3,1
3060	test_fcc	0x7,0
3061	set_fcc         0xb,0		; Set mask opposite of expected
3062	cfcmps      	fr8,fr12,fcc0,cc3,0
3063	test_fcc	0xb,0
3064	set_fcc         0xb,0		; Set mask opposite of expected
3065	cfcmps      	fr8,fr16,fcc0,cc3,1
3066	test_fcc	0xb,0
3067	set_fcc         0xb,0		; Set mask opposite of expected
3068	cfcmps      	fr8,fr20,fcc0,cc3,0
3069	test_fcc	0xb,0
3070	set_fcc         0xb,0		; Set mask opposite of expected
3071	cfcmps      	fr8,fr24,fcc0,cc3,1
3072	test_fcc	0xb,0
3073	set_fcc         0xb,0		; Set mask opposite of expected
3074	cfcmps      	fr8,fr28,fcc0,cc3,0
3075	test_fcc	0xb,0
3076	set_fcc         0xb,0		; Set mask opposite of expected
3077	cfcmps      	fr8,fr32,fcc0,cc3,1
3078	test_fcc	0xb,0
3079	set_fcc         0xb,0		; Set mask opposite of expected
3080	cfcmps      	fr8,fr36,fcc0,cc3,0
3081	test_fcc	0xb,0
3082	set_fcc         0xb,0		; Set mask opposite of expected
3083	cfcmps      	fr8,fr40,fcc0,cc3,1
3084	test_fcc	0xb,0
3085	set_fcc         0xb,0		; Set mask opposite of expected
3086	cfcmps      	fr8,fr44,fcc0,cc3,0
3087	test_fcc	0xb,0
3088	set_fcc         0xb,0		; Set mask opposite of expected
3089	cfcmps      	fr8,fr48,fcc0,cc3,1
3090	test_fcc	0xb,0
3091	set_fcc         0xb,0		; Set mask opposite of expected
3092	cfcmps      	fr8,fr52,fcc0,cc3,0
3093	test_fcc	0xb,0
3094	set_fcc         0xe,0		; Set mask opposite of expected
3095	cfcmps      	fr8,fr56,fcc0,cc3,1
3096	test_fcc	0xe,0
3097	set_fcc         0xe,0		; Set mask opposite of expected
3098	cfcmps      	fr8,fr60,fcc0,cc3,0
3099	test_fcc	0xe,0
3100
3101	set_fcc         0xd,0		; Set mask opposite of expected
3102	cfcmps      	fr12,fr0,fcc0,cc3,1
3103	test_fcc	0xd,0
3104	set_fcc         0xd,0		; Set mask opposite of expected
3105	cfcmps      	fr12,fr4,fcc0,cc3,0
3106	test_fcc	0xd,0
3107	set_fcc         0xd,0		; Set mask opposite of expected
3108	cfcmps      	fr12,fr8,fcc0,cc3,1
3109	test_fcc	0xd,0
3110	set_fcc         0x7,0		; Set mask opposite of expected
3111	cfcmps      	fr12,fr12,fcc0,cc3,0
3112	test_fcc	0x7,0
3113	set_fcc         0xb,0		; Set mask opposite of expected
3114	cfcmps      	fr12,fr16,fcc0,cc3,1
3115	test_fcc	0xb,0
3116	set_fcc         0xb,0		; Set mask opposite of expected
3117	cfcmps      	fr12,fr20,fcc0,cc3,0
3118	test_fcc	0xb,0
3119	set_fcc         0xb,0		; Set mask opposite of expected
3120	cfcmps      	fr12,fr24,fcc0,cc3,1
3121	test_fcc	0xb,0
3122	set_fcc         0xb,0		; Set mask opposite of expected
3123	cfcmps      	fr12,fr28,fcc0,cc3,0
3124	test_fcc	0xb,0
3125	set_fcc         0xb,0		; Set mask opposite of expected
3126	cfcmps      	fr12,fr32,fcc0,cc3,1
3127	test_fcc	0xb,0
3128	set_fcc         0xb,0		; Set mask opposite of expected
3129	cfcmps      	fr12,fr36,fcc0,cc3,0
3130	test_fcc	0xb,0
3131	set_fcc         0xb,0		; Set mask opposite of expected
3132	cfcmps      	fr12,fr40,fcc0,cc3,1
3133	test_fcc	0xb,0
3134	set_fcc         0xb,0		; Set mask opposite of expected
3135	cfcmps      	fr12,fr44,fcc0,cc3,0
3136	test_fcc	0xb,0
3137	set_fcc         0xb,0		; Set mask opposite of expected
3138	cfcmps      	fr12,fr48,fcc0,cc3,1
3139	test_fcc	0xb,0
3140	set_fcc         0xb,0		; Set mask opposite of expected
3141	cfcmps      	fr12,fr52,fcc0,cc3,0
3142	test_fcc	0xb,0
3143	set_fcc         0xe,0		; Set mask opposite of expected
3144	cfcmps      	fr12,fr56,fcc0,cc3,1
3145	test_fcc	0xe,0
3146	set_fcc         0xe,0		; Set mask opposite of expected
3147	cfcmps      	fr12,fr60,fcc0,cc3,0
3148	test_fcc	0xe,0
3149
3150	set_fcc         0xd,0		; Set mask opposite of expected
3151	cfcmps      	fr16,fr0,fcc0,cc3,1
3152	test_fcc	0xd,0
3153	set_fcc         0xd,0		; Set mask opposite of expected
3154	cfcmps      	fr16,fr4,fcc0,cc3,0
3155	test_fcc	0xd,0
3156	set_fcc         0xd,0		; Set mask opposite of expected
3157	cfcmps      	fr16,fr8,fcc0,cc3,1
3158	test_fcc	0xd,0
3159	set_fcc         0xd,0		; Set mask opposite of expected
3160	cfcmps      	fr16,fr12,fcc0,cc3,0
3161	test_fcc	0xd,0
3162	set_fcc         0x7,0		; Set mask opposite of expected
3163	cfcmps      	fr16,fr16,fcc0,cc3,1
3164	test_fcc	0x7,0
3165	set_fcc         0x7,0		; Set mask opposite of expected
3166	cfcmps      	fr16,fr20,fcc0,cc3,0
3167	test_fcc	0x7,0
3168	set_fcc         0xb,0		; Set mask opposite of expected
3169	cfcmps      	fr16,fr24,fcc0,cc3,1
3170	test_fcc	0xb,0
3171	set_fcc         0xb,0		; Set mask opposite of expected
3172	cfcmps      	fr16,fr28,fcc0,cc3,0
3173	test_fcc	0xb,0
3174	set_fcc         0xb,0		; Set mask opposite of expected
3175	cfcmps      	fr16,fr32,fcc0,cc3,1
3176	test_fcc	0xb,0
3177	set_fcc         0xb,0		; Set mask opposite of expected
3178	cfcmps      	fr16,fr36,fcc0,cc3,0
3179	test_fcc	0xb,0
3180	set_fcc         0xb,0		; Set mask opposite of expected
3181	cfcmps      	fr16,fr40,fcc0,cc3,1
3182	test_fcc	0xb,0
3183	set_fcc         0xb,0		; Set mask opposite of expected
3184	cfcmps      	fr16,fr44,fcc0,cc3,0
3185	test_fcc	0xb,0
3186	set_fcc         0xb,0		; Set mask opposite of expected
3187	cfcmps      	fr16,fr48,fcc0,cc3,1
3188	test_fcc	0xb,0
3189	set_fcc         0xb,0		; Set mask opposite of expected
3190	cfcmps      	fr16,fr52,fcc0,cc3,0
3191	test_fcc	0xb,0
3192	set_fcc         0xe,0		; Set mask opposite of expected
3193	cfcmps      	fr16,fr56,fcc0,cc3,1
3194	test_fcc	0xe,0
3195	set_fcc         0xe,0		; Set mask opposite of expected
3196	cfcmps      	fr16,fr60,fcc0,cc3,0
3197	test_fcc	0xe,0
3198
3199	set_fcc         0xd,0		; Set mask opposite of expected
3200	cfcmps      	fr20,fr0,fcc0,cc3,1
3201	test_fcc	0xd,0
3202	set_fcc         0xd,0		; Set mask opposite of expected
3203	cfcmps      	fr20,fr4,fcc0,cc3,0
3204	test_fcc	0xd,0
3205	set_fcc         0xd,0		; Set mask opposite of expected
3206	cfcmps      	fr20,fr8,fcc0,cc3,1
3207	test_fcc	0xd,0
3208	set_fcc         0xd,0		; Set mask opposite of expected
3209	cfcmps      	fr20,fr12,fcc0,cc3,0
3210	test_fcc	0xd,0
3211	set_fcc         0x7,0		; Set mask opposite of expected
3212	cfcmps      	fr20,fr16,fcc0,cc3,1
3213	test_fcc	0x7,0
3214	set_fcc         0x7,0		; Set mask opposite of expected
3215	cfcmps      	fr20,fr20,fcc0,cc3,0
3216	test_fcc	0x7,0
3217	set_fcc         0xb,0		; Set mask opposite of expected
3218	cfcmps      	fr20,fr24,fcc0,cc3,1
3219	test_fcc	0xb,0
3220	set_fcc         0xb,0		; Set mask opposite of expected
3221	cfcmps      	fr20,fr28,fcc0,cc3,0
3222	test_fcc	0xb,0
3223	set_fcc         0xb,0		; Set mask opposite of expected
3224	cfcmps      	fr20,fr32,fcc0,cc3,1
3225	test_fcc	0xb,0
3226	set_fcc         0xb,0		; Set mask opposite of expected
3227	cfcmps      	fr20,fr36,fcc0,cc3,0
3228	test_fcc	0xb,0
3229	set_fcc         0xb,0		; Set mask opposite of expected
3230	cfcmps      	fr20,fr40,fcc0,cc3,1
3231	test_fcc	0xb,0
3232	set_fcc         0xb,0		; Set mask opposite of expected
3233	cfcmps      	fr20,fr44,fcc0,cc3,0
3234	test_fcc	0xb,0
3235	set_fcc         0xb,0		; Set mask opposite of expected
3236	cfcmps      	fr20,fr48,fcc0,cc3,1
3237	test_fcc	0xb,0
3238	set_fcc         0xb,0		; Set mask opposite of expected
3239	cfcmps      	fr20,fr52,fcc0,cc3,0
3240	test_fcc	0xb,0
3241	set_fcc         0xe,0		; Set mask opposite of expected
3242	cfcmps      	fr20,fr56,fcc0,cc3,1
3243	test_fcc	0xe,0
3244	set_fcc         0xe,0		; Set mask opposite of expected
3245	cfcmps      	fr20,fr60,fcc0,cc3,0
3246	test_fcc	0xe,0
3247
3248	set_fcc         0xd,0		; Set mask opposite of expected
3249	cfcmps      	fr24,fr0,fcc0,cc7,1
3250	test_fcc	0xd,0
3251	set_fcc         0xd,0		; Set mask opposite of expected
3252	cfcmps      	fr24,fr4,fcc0,cc7,0
3253	test_fcc	0xd,0
3254	set_fcc         0xd,0		; Set mask opposite of expected
3255	cfcmps      	fr24,fr8,fcc0,cc7,1
3256	test_fcc	0xd,0
3257	set_fcc         0xd,0		; Set mask opposite of expected
3258	cfcmps      	fr24,fr12,fcc0,cc7,0
3259	test_fcc	0xd,0
3260	set_fcc         0xd,0		; Set mask opposite of expected
3261	cfcmps      	fr24,fr16,fcc0,cc7,1
3262	test_fcc	0xd,0
3263	set_fcc         0xd,0		; Set mask opposite of expected
3264	cfcmps      	fr24,fr20,fcc0,cc7,0
3265	test_fcc	0xd,0
3266	set_fcc         0x7,0		; Set mask opposite of expected
3267	cfcmps      	fr24,fr24,fcc0,cc7,1
3268	test_fcc	0x7,0
3269	set_fcc         0xb,0		; Set mask opposite of expected
3270	cfcmps      	fr24,fr28,fcc0,cc7,0
3271	test_fcc	0xb,0
3272	set_fcc         0xb,0		; Set mask opposite of expected
3273	cfcmps      	fr24,fr32,fcc0,cc7,1
3274	test_fcc	0xb,0
3275	set_fcc         0xb,0		; Set mask opposite of expected
3276	cfcmps      	fr24,fr36,fcc0,cc7,0
3277	test_fcc	0xb,0
3278	set_fcc         0xb,0		; Set mask opposite of expected
3279	cfcmps      	fr24,fr40,fcc0,cc7,1
3280	test_fcc	0xb,0
3281	set_fcc         0xb,0		; Set mask opposite of expected
3282	cfcmps      	fr24,fr44,fcc0,cc7,0
3283	test_fcc	0xb,0
3284	set_fcc         0xb,0		; Set mask opposite of expected
3285	cfcmps      	fr24,fr48,fcc0,cc7,1
3286	test_fcc	0xb,0
3287	set_fcc         0xb,0		; Set mask opposite of expected
3288	cfcmps      	fr24,fr52,fcc0,cc7,0
3289	test_fcc	0xb,0
3290	set_fcc         0xe,0		; Set mask opposite of expected
3291	cfcmps      	fr24,fr56,fcc0,cc7,1
3292	test_fcc	0xe,0
3293	set_fcc         0xe,0		; Set mask opposite of expected
3294	cfcmps      	fr24,fr60,fcc0,cc7,0
3295	test_fcc	0xe,0
3296
3297	set_fcc         0xd,0		; Set mask opposite of expected
3298	cfcmps      	fr28,fr0,fcc0,cc7,1
3299	test_fcc	0xd,0
3300	set_fcc         0xd,0		; Set mask opposite of expected
3301	cfcmps      	fr28,fr4,fcc0,cc7,0
3302	test_fcc	0xd,0
3303	set_fcc         0xd,0		; Set mask opposite of expected
3304	cfcmps      	fr28,fr8,fcc0,cc7,1
3305	test_fcc	0xd,0
3306	set_fcc         0xd,0		; Set mask opposite of expected
3307	cfcmps      	fr28,fr12,fcc0,cc7,0
3308	test_fcc	0xd,0
3309	set_fcc         0xd,0		; Set mask opposite of expected
3310	cfcmps      	fr28,fr16,fcc0,cc7,1
3311	test_fcc	0xd,0
3312	set_fcc         0xd,0		; Set mask opposite of expected
3313	cfcmps      	fr28,fr20,fcc0,cc7,0
3314	test_fcc	0xd,0
3315	set_fcc         0xd,0		; Set mask opposite of expected
3316	cfcmps      	fr28,fr24,fcc0,cc7,1
3317	test_fcc	0xd,0
3318	set_fcc         0x7,0		; Set mask opposite of expected
3319	cfcmps      	fr28,fr28,fcc0,cc7,0
3320	test_fcc	0x7,0
3321	set_fcc         0xb,0		; Set mask opposite of expected
3322	cfcmps      	fr28,fr32,fcc0,cc7,1
3323	test_fcc	0xb,0
3324	set_fcc         0xb,0		; Set mask opposite of expected
3325	cfcmps      	fr28,fr36,fcc0,cc7,0
3326	test_fcc	0xb,0
3327	set_fcc         0xb,0		; Set mask opposite of expected
3328	cfcmps      	fr28,fr40,fcc0,cc7,1
3329	test_fcc	0xb,0
3330	set_fcc         0xb,0		; Set mask opposite of expected
3331	cfcmps      	fr28,fr44,fcc0,cc7,0
3332	test_fcc	0xb,0
3333	set_fcc         0xb,0		; Set mask opposite of expected
3334	cfcmps      	fr28,fr48,fcc0,cc7,1
3335	test_fcc	0xb,0
3336	set_fcc         0xb,0		; Set mask opposite of expected
3337	cfcmps      	fr28,fr52,fcc0,cc7,0
3338	test_fcc	0xb,0
3339	set_fcc         0xe,0		; Set mask opposite of expected
3340	cfcmps      	fr28,fr56,fcc0,cc7,1
3341	test_fcc	0xe,0
3342	set_fcc         0xe,0		; Set mask opposite of expected
3343	cfcmps      	fr28,fr60,fcc0,cc7,0
3344	test_fcc	0xe,0
3345
3346	set_fcc         0xd,0		; Set mask opposite of expected
3347	cfcmps      	fr48,fr0,fcc0,cc7,1
3348	test_fcc	0xd,0
3349	set_fcc         0xd,0		; Set mask opposite of expected
3350	cfcmps      	fr48,fr4,fcc0,cc7,0
3351	test_fcc	0xd,0
3352	set_fcc         0xd,0		; Set mask opposite of expected
3353	cfcmps      	fr48,fr8,fcc0,cc7,1
3354	test_fcc	0xd,0
3355	set_fcc         0xd,0		; Set mask opposite of expected
3356	cfcmps      	fr48,fr12,fcc0,cc7,0
3357	test_fcc	0xd,0
3358	set_fcc         0xd,0		; Set mask opposite of expected
3359	cfcmps      	fr48,fr16,fcc0,cc7,1
3360	test_fcc	0xd,0
3361	set_fcc         0xd,0		; Set mask opposite of expected
3362	cfcmps      	fr48,fr20,fcc0,cc7,0
3363	test_fcc	0xd,0
3364	set_fcc         0xd,0		; Set mask opposite of expected
3365	cfcmps      	fr48,fr24,fcc0,cc7,1
3366	test_fcc	0xd,0
3367	set_fcc         0xd,0		; Set mask opposite of expected
3368	cfcmps      	fr48,fr28,fcc0,cc7,0
3369	test_fcc	0xd,0
3370	set_fcc         0xd,0		; Set mask opposite of expected
3371	cfcmps      	fr48,fr32,fcc0,cc7,1
3372	test_fcc	0xd,0
3373	set_fcc         0xd,0		; Set mask opposite of expected
3374	cfcmps      	fr48,fr36,fcc0,cc7,0
3375	test_fcc	0xd,0
3376	set_fcc         0xd,0		; Set mask opposite of expected
3377	cfcmps      	fr48,fr40,fcc0,cc7,1
3378	test_fcc	0xd,0
3379	set_fcc         0xd,0		; Set mask opposite of expected
3380	cfcmps      	fr48,fr44,fcc0,cc7,0
3381	test_fcc	0xd,0
3382	set_fcc         0x7,0		; Set mask opposite of expected
3383	cfcmps      	fr48,fr48,fcc0,cc7,1
3384	test_fcc	0x7,0
3385	set_fcc         0xb,0		; Set mask opposite of expected
3386	cfcmps      	fr48,fr52,fcc0,cc7,0
3387	test_fcc	0xb,0
3388	set_fcc         0xe,0		; Set mask opposite of expected
3389	cfcmps      	fr48,fr56,fcc0,cc7,1
3390	test_fcc	0xe,0
3391	set_fcc         0xe,0		; Set mask opposite of expected
3392	cfcmps      	fr48,fr60,fcc0,cc7,0
3393	test_fcc	0xe,0
3394
3395	set_fcc         0xd,0		; Set mask opposite of expected
3396	cfcmps      	fr52,fr0,fcc0,cc7,1
3397	test_fcc	0xd,0
3398	set_fcc         0xd,0		; Set mask opposite of expected
3399	cfcmps      	fr52,fr4,fcc0,cc7,0
3400	test_fcc	0xd,0
3401	set_fcc         0xd,0		; Set mask opposite of expected
3402	cfcmps      	fr52,fr8,fcc0,cc7,1
3403	test_fcc	0xd,0
3404	set_fcc         0xd,0		; Set mask opposite of expected
3405	cfcmps      	fr52,fr12,fcc0,cc7,0
3406	test_fcc	0xd,0
3407	set_fcc         0xd,0		; Set mask opposite of expected
3408	cfcmps      	fr52,fr16,fcc0,cc7,1
3409	test_fcc	0xd,0
3410	set_fcc         0xd,0		; Set mask opposite of expected
3411	cfcmps      	fr52,fr20,fcc0,cc7,0
3412	test_fcc	0xd,0
3413	set_fcc         0xd,0		; Set mask opposite of expected
3414	cfcmps      	fr52,fr24,fcc0,cc7,1
3415	test_fcc	0xd,0
3416	set_fcc         0xd,0		; Set mask opposite of expected
3417	cfcmps      	fr52,fr28,fcc0,cc7,0
3418	test_fcc	0xd,0
3419	set_fcc         0xd,0		; Set mask opposite of expected
3420	cfcmps      	fr52,fr32,fcc0,cc7,1
3421	test_fcc	0xd,0
3422	set_fcc         0xd,0		; Set mask opposite of expected
3423	cfcmps      	fr52,fr36,fcc0,cc7,0
3424	test_fcc	0xd,0
3425	set_fcc         0xd,0		; Set mask opposite of expected
3426	cfcmps      	fr52,fr40,fcc0,cc7,1
3427	test_fcc	0xd,0
3428	set_fcc         0xd,0		; Set mask opposite of expected
3429	cfcmps      	fr52,fr44,fcc0,cc7,0
3430	test_fcc	0xd,0
3431	set_fcc         0xd,0		; Set mask opposite of expected
3432	cfcmps      	fr52,fr48,fcc0,cc7,1
3433	test_fcc	0xd,0
3434	set_fcc         0x7,0		; Set mask opposite of expected
3435	cfcmps      	fr52,fr52,fcc0,cc7,0
3436	test_fcc	0x7,0
3437	set_fcc         0xe,0		; Set mask opposite of expected
3438	cfcmps      	fr52,fr56,fcc0,cc7,1
3439	test_fcc	0xe,0
3440	set_fcc         0xe,0		; Set mask opposite of expected
3441	cfcmps      	fr52,fr60,fcc0,cc7,0
3442	test_fcc	0xe,0
3443
3444	set_fcc         0xe,0		; Set mask opposite of expected
3445	cfcmps      	fr56,fr0,fcc0,cc7,1
3446	test_fcc	0xe,0
3447	set_fcc         0xe,0		; Set mask opposite of expected
3448	cfcmps      	fr56,fr4,fcc0,cc7,0
3449	test_fcc	0xe,0
3450	set_fcc         0xe,0		; Set mask opposite of expected
3451	cfcmps      	fr56,fr8,fcc0,cc7,1
3452	test_fcc	0xe,0
3453	set_fcc         0xe,0		; Set mask opposite of expected
3454	cfcmps      	fr56,fr12,fcc0,cc7,0
3455	test_fcc	0xe,0
3456	set_fcc         0xe,0		; Set mask opposite of expected
3457	cfcmps      	fr56,fr16,fcc0,cc7,1
3458	test_fcc	0xe,0
3459	set_fcc         0xe,0		; Set mask opposite of expected
3460	cfcmps      	fr56,fr20,fcc0,cc7,0
3461	test_fcc	0xe,0
3462	set_fcc         0xe,0		; Set mask opposite of expected
3463	cfcmps      	fr56,fr24,fcc0,cc7,1
3464	test_fcc	0xe,0
3465	set_fcc         0xe,0		; Set mask opposite of expected
3466	cfcmps      	fr56,fr28,fcc0,cc7,0
3467	test_fcc	0xe,0
3468	set_fcc         0xe,0		; Set mask opposite of expected
3469	cfcmps      	fr56,fr32,fcc0,cc7,1
3470	test_fcc	0xe,0
3471	set_fcc         0xe,0		; Set mask opposite of expected
3472	cfcmps      	fr56,fr36,fcc0,cc7,0
3473	test_fcc	0xe,0
3474	set_fcc         0xe,0		; Set mask opposite of expected
3475	cfcmps      	fr56,fr40,fcc0,cc7,1
3476	test_fcc	0xe,0
3477	set_fcc         0xe,0		; Set mask opposite of expected
3478	cfcmps      	fr56,fr44,fcc0,cc7,0
3479	test_fcc	0xe,0
3480	set_fcc         0xe,0		; Set mask opposite of expected
3481	cfcmps      	fr56,fr48,fcc0,cc7,1
3482	test_fcc	0xe,0
3483	set_fcc         0xe,0		; Set mask opposite of expected
3484	cfcmps      	fr56,fr52,fcc0,cc7,0
3485	test_fcc	0xe,0
3486	set_fcc         0xe,0		; Set mask opposite of expected
3487	cfcmps      	fr56,fr56,fcc0,cc7,1
3488	test_fcc	0xe,0
3489	set_fcc         0xe,0		; Set mask opposite of expected
3490	cfcmps      	fr56,fr60,fcc0,cc7,0
3491	test_fcc	0xe,0
3492
3493	set_fcc         0xe,0		; Set mask opposite of expected
3494	cfcmps      	fr60,fr0,fcc0,cc7,1
3495	test_fcc	0xe,0
3496	set_fcc         0xe,0		; Set mask opposite of expected
3497	cfcmps      	fr60,fr4,fcc0,cc7,0
3498	test_fcc	0xe,0
3499	set_fcc         0xe,0		; Set mask opposite of expected
3500	cfcmps      	fr60,fr8,fcc0,cc7,1
3501	test_fcc	0xe,0
3502	set_fcc         0xe,0		; Set mask opposite of expected
3503	cfcmps      	fr60,fr12,fcc0,cc7,1
3504	test_fcc	0xe,0
3505	set_fcc         0xe,0		; Set mask opposite of expected
3506	cfcmps      	fr60,fr16,fcc0,cc7,0
3507	test_fcc	0xe,0
3508	set_fcc         0xe,0		; Set mask opposite of expected
3509	cfcmps      	fr60,fr20,fcc0,cc7,1
3510	test_fcc	0xe,0
3511	set_fcc         0xe,0		; Set mask opposite of expected
3512	cfcmps      	fr60,fr24,fcc0,cc7,0
3513	test_fcc	0xe,0
3514	set_fcc         0xe,0		; Set mask opposite of expected
3515	cfcmps      	fr60,fr28,fcc0,cc7,1
3516	test_fcc	0xe,0
3517	set_fcc         0xe,0		; Set mask opposite of expected
3518	cfcmps      	fr60,fr32,fcc0,cc7,0
3519	test_fcc	0xe,0
3520	set_fcc         0xe,0		; Set mask opposite of expected
3521	cfcmps      	fr60,fr36,fcc0,cc7,1
3522	test_fcc	0xe,0
3523	set_fcc         0xe,0		; Set mask opposite of expected
3524	cfcmps      	fr60,fr40,fcc0,cc7,0
3525	test_fcc	0xe,0
3526	set_fcc         0xe,0		; Set mask opposite of expected
3527	cfcmps      	fr60,fr44,fcc0,cc7,1
3528	test_fcc	0xe,0
3529	set_fcc         0xe,0		; Set mask opposite of expected
3530	cfcmps      	fr60,fr48,fcc0,cc7,0
3531	test_fcc	0xe,0
3532	set_fcc         0xe,0		; Set mask opposite of expected
3533	cfcmps      	fr60,fr52,fcc0,cc7,1
3534	test_fcc	0xe,0
3535	set_fcc         0xe,0		; Set mask opposite of expected
3536	cfcmps      	fr60,fr56,fcc0,cc7,0
3537	test_fcc	0xe,0
3538	set_fcc         0xe,0		; Set mask opposite of expected
3539	cfcmps      	fr60,fr60,fcc0,cc7,1
3540	test_fcc	0xe,0
3541
3542	pass
3543