1/* Main simulator entry points specific to the SH5. 2 Copyright (C) 2000 Free Software Foundation, Inc. 3 Contributed by Cygnus Solutions. 4 5This file is part of the GNU simulators. 6 7This program is free software; you can redistribute it and/or modify 8it under the terms of the GNU General Public License as published by 9the Free Software Foundation; either version 3 of the License, or 10(at your option) any later version. 11 12This program is distributed in the hope that it will be useful, 13but WITHOUT ANY WARRANTY; without even the implied warranty of 14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15GNU General Public License for more details. 16 17You should have received a copy of the GNU General Public License 18along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20#include "libiberty.h" 21#include "bfd.h" 22#include "sim-main.h" 23#ifdef HAVE_STDLIB_H 24#include <stdlib.h> 25#endif 26#include "sim-options.h" 27#include "dis-asm.h" 28 29static void free_state (SIM_DESC); 30 31/* Since we don't build the cgen-opcode table, we use a wrapper around 32 the existing disassembler from libopcodes. */ 33static CGEN_DISASSEMBLER sh64_disassemble_insn; 34 35/* Records simulator descriptor so utilities like sh5_dump_regs can be 36 called from gdb. */ 37SIM_DESC current_state; 38 39/* Cover function of sim_state_free to free the cpu buffers as well. */ 40 41static void 42free_state (SIM_DESC sd) 43{ 44 if (STATE_MODULES (sd) != NULL) 45 sim_module_uninstall (sd); 46 sim_cpu_free_all (sd); 47 sim_state_free (sd); 48} 49 50/* Create an instance of the simulator. */ 51 52SIM_DESC 53sim_open (kind, callback, abfd, argv) 54 SIM_OPEN_KIND kind; 55 host_callback *callback; 56 struct bfd *abfd; 57 char **argv; 58{ 59 char c; 60 int i; 61 SIM_DESC sd = sim_state_alloc (kind, callback); 62 63 /* The cpu data is kept in a separately allocated chunk of memory. */ 64 if (sim_cpu_alloc_all (sd, 1, cgen_cpu_max_extra_bytes ()) != SIM_RC_OK) 65 { 66 free_state (sd); 67 return 0; 68 } 69 70#if 0 /* FIXME: pc is in mach-specific struct */ 71 /* FIXME: watchpoints code shouldn't need this */ 72 { 73 SIM_CPU *current_cpu = STATE_CPU (sd, 0); 74 STATE_WATCHPOINTS (sd)->pc = &(PC); 75 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC); 76 } 77#endif 78 79 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK) 80 { 81 free_state (sd); 82 return 0; 83 } 84 85#if 0 /* FIXME: 'twould be nice if we could do this */ 86 /* These options override any module options. 87 Obviously ambiguity should be avoided, however the caller may wish to 88 augment the meaning of an option. */ 89 if (extra_options != NULL) 90 sim_add_option_table (sd, extra_options); 91#endif 92 93 /* getopt will print the error message so we just have to exit if this fails. 94 FIXME: Hmmm... in the case of gdb we need getopt to call 95 print_filtered. */ 96 if (sim_parse_args (sd, argv) != SIM_RC_OK) 97 { 98 free_state (sd); 99 return 0; 100 } 101 102 /* Allocate core managed memory if none specified by user. 103 Use address 4 here in case the user wanted address 0 unmapped. */ 104 if (sim_core_read_buffer (sd, NULL, read_map, &c, 4, 1) == 0) 105 sim_do_commandf (sd, "memory region 0,0x%x", SH64_DEFAULT_MEM_SIZE); 106 107 /* Add a small memory region way up in the address space to handle 108 writes to invalidate an instruction cache line. This is used for 109 trampolines. Since we don't simulate the cache, this memory just 110 avoids bus errors. 64K ought to do. */ 111 sim_do_command (sd," memory region 0xf0000000,0x10000"); 112 113 /* check for/establish the reference program image */ 114 if (sim_analyze_program (sd, 115 (STATE_PROG_ARGV (sd) != NULL 116 ? *STATE_PROG_ARGV (sd) 117 : NULL), 118 abfd) != SIM_RC_OK) 119 { 120 free_state (sd); 121 return 0; 122 } 123 124 /* Establish any remaining configuration options. */ 125 if (sim_config (sd) != SIM_RC_OK) 126 { 127 free_state (sd); 128 return 0; 129 } 130 131 if (sim_post_argv_init (sd) != SIM_RC_OK) 132 { 133 free_state (sd); 134 return 0; 135 } 136 137 /* Open a copy of the cpu descriptor table. */ 138 { 139 CGEN_CPU_DESC cd = sh_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name, 140 CGEN_ENDIAN_BIG); 141 142 for (i = 0; i < MAX_NR_PROCESSORS; ++i) 143 { 144 SIM_CPU *cpu = STATE_CPU (sd, i); 145 CPU_CPU_DESC (cpu) = cd; 146 CPU_DISASSEMBLER (cpu) = sh64_disassemble_insn; 147 } 148 } 149 150 /* Clear idesc table pointers for good measure. */ 151 sh64_idesc_media = sh64_idesc_compact = NULL; 152 153 /* Initialize various cgen things not done by common framework. 154 Must be done after sh_cgen_cpu_open. */ 155 cgen_init (sd); 156 157 /* Store in a global so things like sparc32_dump_regs can be invoked 158 from the gdb command line. */ 159 current_state = sd; 160 161 return sd; 162} 163 164void 165sim_close (sd, quitting) 166 SIM_DESC sd; 167 int quitting; 168{ 169 sh_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0))); 170 sim_module_uninstall (sd); 171} 172 173SIM_RC 174sim_create_inferior (sd, abfd, argv, envp) 175 SIM_DESC sd; 176 struct bfd *abfd; 177 char **argv; 178 char **envp; 179{ 180 SIM_CPU *current_cpu = STATE_CPU (sd, 0); 181 SIM_ADDR addr; 182 183 if (abfd != NULL) 184 addr = bfd_get_start_address (abfd); 185 else 186 addr = 0; 187 sim_pc_set (current_cpu, addr); 188 189#if 0 190 STATE_ARGV (sd) = sim_copy_argv (argv); 191 STATE_ENVP (sd) = sim_copy_argv (envp); 192#endif 193 194 return SIM_RC_OK; 195} 196 197void 198sim_do_command (sd, cmd) 199 SIM_DESC sd; 200 char *cmd; 201{ 202 if (sim_args_command (sd, cmd) != SIM_RC_OK) 203 sim_io_eprintf (sd, "Unknown command `%s'\n", cmd); 204} 205 206 207/* Disassemble an instruction. */ 208 209static void 210sh64_disassemble_insn (SIM_CPU *cpu, const CGEN_INSN *insn, 211 const ARGBUF *abuf, IADDR pc, char *buf) 212{ 213 struct disassemble_info disasm_info; 214 SFILE sfile; 215 SIM_DESC sd = CPU_STATE (cpu); 216 217 sfile.buffer = sfile.current = buf; 218 INIT_DISASSEMBLE_INFO (disasm_info, (FILE *) &sfile, 219 (fprintf_ftype) sim_disasm_sprintf); 220 221 disasm_info.arch = bfd_get_arch (STATE_PROG_BFD (sd)); 222 disasm_info.mach = bfd_get_mach (STATE_PROG_BFD (sd)); 223 disasm_info.endian = 224 (bfd_big_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_BIG 225 : bfd_little_endian (STATE_PROG_BFD (sd)) ? BFD_ENDIAN_LITTLE 226 : BFD_ENDIAN_UNKNOWN); 227 disasm_info.read_memory_func = sim_disasm_read_memory; 228 disasm_info.memory_error_func = sim_disasm_perror_memory; 229 disasm_info.application_data = (PTR) cpu; 230 231 if (sh64_h_ism_get (cpu) == ISM_MEDIA) 232 print_insn_sh64x_media (pc, &disasm_info); 233 else 234 print_insn_sh (pc, &disasm_info); 235} 236