12007-09-04 Nick Clifton <nickc@redhat.com> 2 3 * interp.c (options enum): Add OPTION_INFO_MEMORY. 4 (display_mem_info): New static variable. 5 (mips_option_handler): Handle OPTION_INFO_MEMORY. 6 (mips_options): Add info-memory and memory-info. 7 (sim_open): After processing the command line and board 8 specification, check display_mem_info. If it is set then 9 call the real handler for the --memory-info command line 10 switch. 11 122007-08-24 Joel Brobecker <brobecker@adacore.com> 13 14 * configure.ac: Change license of multi-run.c to GPL version 3. 15 * configure: Regenerate. 16 172007-06-28 Richard Sandiford <richard@codesourcery.com> 18 19 * configure.ac, configure: Revert last patch. 20 212007-06-26 Richard Sandiford <richard@codesourcery.com> 22 23 * configure.ac (sim_mipsisa3264_configs): New variable. 24 (mipsis32*-*-, mipsisa32r2*-*-*, mips64*-*-*, mips64r2*-*-*): Make 25 every configuration support all four targets, using the triplet to 26 determine the default. 27 * configure: Regenerate. 28 292007-06-25 Richard Sandiford <richard@codesourcery.com> 30 31 * Makefile.in (m16run.o): New rule. 32 332007-05-15 Thiemo Seufer <ths@mips.com> 34 35 * mips3264r2.igen (DSHD): Fix compile warning. 36 372007-05-14 Thiemo Seufer <ths@mips.com> 38 39 * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL, 40 CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt, 41 NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS, 42 RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support 43 for mips32r2. 44 452007-03-01 Thiemo Seufer <ths@mips.com> 46 47 * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32 48 and mips64. 49 502007-02-20 Thiemo Seufer <ths@mips.com> 51 52 * dsp.igen: Update copyright notice. 53 * dsp2.igen: Fix copyright notice. 54 552007-02-20 Thiemo Seufer <ths@mips.com> 56 Chao-Ying Fu <fu@mips.com> 57 58 * Makefile.in (IGEN_INCLUDE): Add dsp2.igen. 59 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): 60 Add dsp2 to sim_igen_machine. 61 * configure: Regenerate. 62 * dsp.igen (do_ph_op): Add MUL support when op = 2. 63 (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph. 64 (mulq_rs.ph): Use do_ph_mulq. 65 (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen. 66 * mips.igen: Add dsp2 model and include dsp2.igen. 67 (MFHI, MFLO, MTHI, MTLO): Extend these instructions for 68 for *mips32r2, *mips64r2, *dsp. 69 (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions 70 for *mips32r2, *mips64r2, *dsp2. 71 * dsp2.igen: New file for MIPS DSP REV 2 ASE. 72 732007-02-19 Thiemo Seufer <ths@mips.com> 74 Nigel Stephens <nigel@mips.com> 75 76 * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2 77 jumps with hazard barrier. 78 792007-02-19 Thiemo Seufer <ths@mips.com> 80 Nigel Stephens <nigel@mips.com> 81 82 * interp.c (sim_monitor): Flush stdout and stderr file descriptors 83 after each call to sim_io_write. 84 852007-02-19 Thiemo Seufer <ths@mips.com> 86 Nigel Stephens <nigel@mips.com> 87 88 * interp.c (ColdReset): Set CP0 Config0 to reflect the address size 89 supported by this simulator. 90 (decode_coproc): Recognise additional CP0 Config registers 91 correctly. 92 932007-02-19 Thiemo Seufer <ths@mips.com> 94 Nigel Stephens <nigel@mips.com> 95 David Ung <davidu@mips.com> 96 97 * cp1.c (value_fpr): Don't inherit existing FPR_STATE for 98 uninterpreted formats. If fmt is one of the uninterpreted types 99 don't update the FPR_STATE. Handle fmt_uninterpreted_32 like 100 fmt_word, and fmt_uninterpreted_64 like fmt_long. 101 (store_fpr): When writing an invalid odd register, set the 102 matching even register to fmt_unknown, not the following register. 103 * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to 104 the the memory window at offset 0 set by --memory-size command 105 line option. 106 (sim_store_register): Handle storing 4 bytes to an 8 byte floating 107 point register. 108 (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte 109 register. 110 (sim_monitor): When returning the memory size to the MIPS 111 application, use the value in STATE_MEM_SIZE, not an arbitrary 112 hardcoded value. 113 (cop_lw): Don' mess around with FPR_STATE, just pass 114 fmt_uninterpreted_32 to StoreFPR. 115 (cop_sw): Similarly. 116 (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted. 117 (cop_sd): Similarly. 118 * mips.igen (not_word_value): Single version for mips32, mips64 119 and mips16. 120 1212007-02-19 Thiemo Seufer <ths@mips.com> 122 Nigel Stephens <nigel@mips.com> 123 124 * interp.c (MEM_SIZE): Increase default memory size from 2 to 8 125 MBytes. 126 1272007-02-17 Thiemo Seufer <ths@mips.com> 128 129 * configure.ac (mips*-sde-elf*): Move in front of generic machine 130 configuration. 131 * configure: Regenerate. 132 1332007-02-17 Thiemo Seufer <ths@mips.com> 134 135 * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*): 136 Add mdmx to sim_igen_machine. 137 (mipsisa64*-*-*): Likewise. Remove dsp. 138 (mipsisa32*-*-*): Remove dsp. 139 * configure: Regenerate. 140 1412007-02-13 Thiemo Seufer <ths@mips.com> 142 143 * configure.ac: Add mips*-sde-elf* target. 144 * configure: Regenerate. 145 1462006-12-21 Hans-Peter Nilsson <hp@axis.com> 147 148 * acconfig.h: Remove. 149 * config.in, configure: Regenerate. 150 1512006-11-07 Thiemo Seufer <ths@mips.com> 152 153 * dsp.igen (do_w_op): Fix compiler warning. 154 1552006-08-29 Thiemo Seufer <ths@mips.com> 156 David Ung <davidu@mips.com> 157 158 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to 159 sim_igen_machine. 160 * configure: Regenerate. 161 * mips.igen (model): Add smartmips. 162 (MADDU): Increment ACX if carry. 163 (do_mult): Clear ACX. 164 (ROR,RORV): Add smartmips. 165 (include): Include smartmips.igen. 166 * sim-main.h (ACX): Set to REGISTERS[89]. 167 * smartmips.igen: New file. 168 1692006-08-29 Thiemo Seufer <ths@mips.com> 170 David Ung <davidu@mips.com> 171 172 * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and 173 mips3264r2.igen. Add missing dependency rules. 174 * m16e.igen: Support for mips16e save/restore instructions. 175 1762006-06-13 Richard Earnshaw <rearnsha@arm.com> 177 178 * configure: Regenerated. 179 1802006-06-05 Daniel Jacobowitz <dan@codesourcery.com> 181 182 * configure: Regenerated. 183 1842006-05-31 Daniel Jacobowitz <dan@codesourcery.com> 185 186 * configure: Regenerated. 187 1882006-05-15 Chao-ying Fu <fu@mips.com> 189 190 * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions. 191 1922006-04-18 Nick Clifton <nickc@redhat.com> 193 194 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break 195 statement. 196 1972006-03-29 Hans-Peter Nilsson <hp@axis.com> 198 199 * configure: Regenerate. 200 2012005-12-14 Chao-ying Fu <fu@mips.com> 202 203 * Makefile.in (SIM_OBJS): Add dsp.o. 204 (dsp.o): New dependency. 205 (IGEN_INCLUDE): Add dsp.igen. 206 * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*, 207 mipsisa64*-*-*): Add dsp to sim_igen_machine. 208 * configure: Regenerate. 209 * mips.igen: Add dsp model and include dsp.igen. 210 (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2, 211 because these instructions are extended in DSP ASE. 212 * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of 213 adding 6 DSP accumulator registers and 1 DSP control register. 214 (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX, 215 AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT, 216 DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK, 217 DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK, 218 DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK, 219 DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK, 220 DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6, 221 DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK, 222 DSPCR_CCOND_SMASK): New define. 223 (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators. 224 * dsp.c, dsp.igen: New files for MIPS DSP ASE. 225 2262005-07-08 Ian Lance Taylor <ian@airs.com> 227 228 * tconfig.in (SIM_QUIET_NAN_NEGATED): Define. 229 2302005-06-16 David Ung <davidu@mips.com> 231 Nigel Stephens <nigel@mips.com> 232 233 * mips.igen: New mips16e model and include m16e.igen. 234 (check_u64): Add mips16e tag. 235 * m16e.igen: New file for MIPS16e instructions. 236 * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*, 237 mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e 238 models. 239 * configure: Regenerate. 240 2412005-05-26 David Ung <davidu@mips.com> 242 243 * mips.igen (mips32r2, mips64r2): New ISA models. Add new model 244 tags to all instructions which are applicable to the new ISAs. 245 (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from 246 vr.igen. 247 * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific 248 instructions. 249 * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move 250 to mips.igen. 251 * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets. 252 * configure: Regenerate. 253 2542005-03-23 Mark Kettenis <kettenis@gnu.org> 255 256 * configure: Regenerate. 257 2582005-01-14 Andrew Cagney <cagney@gnu.org> 259 260 * configure.ac: Sinclude aclocal.m4 before common.m4. Add 261 explicit call to AC_CONFIG_HEADER. 262 * configure: Regenerate. 263 2642005-01-12 Andrew Cagney <cagney@gnu.org> 265 266 * configure.ac: Update to use ../common/common.m4. 267 * configure: Re-generate. 268 2692005-01-11 Andrew Cagney <cagney@localhost.localdomain> 270 271 * configure: Regenerated to track ../common/aclocal.m4 changes. 272 2732005-01-07 Andrew Cagney <cagney@gnu.org> 274 275 * configure.ac: Rename configure.in, require autoconf 2.59. 276 * configure: Re-generate. 277 2782004-12-08 Hans-Peter Nilsson <hp@axis.com> 279 280 * configure: Regenerate for ../common/aclocal.m4 update. 281 2822004-09-24 Monika Chaddha <monika@acmet.com> 283 284 Committed by Andrew Cagney. 285 * m16.igen (CMP, CMPI): Fix assembler. 286 2872004-08-18 Chris Demetriou <cgd@broadcom.com> 288 289 * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine. 290 * configure: Regenerate. 291 2922004-06-25 Chris Demetriou <cgd@broadcom.com> 293 294 * configure.in (sim_m16_machine): Include mipsIII. 295 * configure: Regenerate. 296 2972004-05-11 Maciej W. Rozycki <macro@ds2.pg.gda.pl> 298 299 * mips/interp.c (decode_coproc): Sign-extend the address retrieved 300 from COP0_BADVADDR. 301 * mips/sim-main.h (COP0_BADVADDR): Remove a cast. 302 3032004-04-10 Chris Demetriou <cgd@broadcom.com> 304 305 * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New. 306 3072004-04-09 Chris Demetriou <cgd@broadcom.com> 308 309 * mips.igen (check_fmt): Remove. 310 (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W) 311 (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt) 312 (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt) 313 (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt) 314 (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt) 315 (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats. 316 (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt) 317 (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt) 318 (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt. 319 (C.cnd.fmta): Remove incorrect call to check_fmt_p. 320 3212004-04-09 Chris Demetriou <cgd@broadcom.com> 322 323 * sb1.igen (check_sbx): New function. 324 (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx. 325 3262004-03-29 Chris Demetriou <cgd@broadcom.com> 327 Richard Sandiford <rsandifo@redhat.com> 328 329 * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD) 330 (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New. 331 * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide 332 separate implementations for mipsIV and mipsV. Use new macros to 333 determine whether the restrictions apply. 334 3352004-01-19 Chris Demetriou <cgd@broadcom.com> 336 337 * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo) 338 (check_mult_hilo): Improve comments. 339 (check_div_hilo): Likewise. Also, fork off a new version 340 to handle mips32/mips64 (since there are no hazards to check 341 in MIPS32/MIPS64). 342 3432003-06-17 Richard Sandiford <rsandifo@redhat.com> 344 345 * mips.igen (do_dmultx): Fix check for negative operands. 346 3472003-05-16 Ian Lance Taylor <ian@airs.com> 348 349 * Makefile.in (SHELL): Make sure this is defined. 350 (various): Use $(SHELL) whenever we invoke move-if-change. 351 3522003-05-03 Chris Demetriou <cgd@broadcom.com> 353 354 * cp1.c: Tweak attribution slightly. 355 * cp1.h: Likewise. 356 * mdmx.c: Likewise. 357 * mdmx.igen: Likewise. 358 * mips3d.igen: Likewise. 359 * sb1.igen: Likewise. 360 3612003-04-15 Richard Sandiford <rsandifo@redhat.com> 362 363 * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of 364 unsigned operands. 365 3662003-02-27 Andrew Cagney <cagney@redhat.com> 367 368 * interp.c (sim_open): Rename _bfd to bfd. 369 (sim_create_inferior): Ditto. 370 3712003-01-14 Chris Demetriou <cgd@broadcom.com> 372 373 * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64. 374 3752003-01-14 Chris Demetriou <cgd@broadcom.com> 376 377 * mips.igen (EI, DI): Remove. 378 3792003-01-05 Richard Sandiford <rsandifo@redhat.com> 380 381 * Makefile.in (tmp-run-multi): Fix mips16 filter. 382 3832003-01-04 Richard Sandiford <rsandifo@redhat.com> 384 Andrew Cagney <ac131313@redhat.com> 385 Gavin Romig-Koch <gavin@redhat.com> 386 Graydon Hoare <graydon@redhat.com> 387 Aldy Hernandez <aldyh@redhat.com> 388 Dave Brolley <brolley@redhat.com> 389 Chris Demetriou <cgd@broadcom.com> 390 391 * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1. 392 (sim_mach_default): New variable. 393 (mips64vr-*-*, mips64vrel-*-*): New configurations. 394 Add a new simulator generator, MULTI. 395 * configure: Regenerate. 396 * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables. 397 (multi-run.o): New dependency. 398 (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables. 399 (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules. 400 (tmp-multi): Combine them. 401 (BUILT_SRC_FROM_MULTI): New variable. Depend on tmp-multi. 402 (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI. 403 (distclean-extra): New rule. 404 * sim-main.h: Include bfd.h. 405 (MIPS_MACH): New macro. 406 * mips.igen (vr4120, vr5400, vr5500): New models. 407 (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500. 408 * vr.igen: Replace with new version. 409 4102003-01-04 Chris Demetriou <cgd@broadcom.com> 411 412 * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1). 413 * configure: Regenerate. 414 4152002-12-31 Chris Demetriou <cgd@broadcom.com> 416 417 * sim-main.h (check_branch_bug, mark_branch_bug): Remove. 418 * mips.igen: Remove all invocations of check_branch_bug and 419 mark_branch_bug. 420 4212002-12-16 Chris Demetriou <cgd@broadcom.com> 422 423 * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h". 424 4252002-07-30 Chris Demetriou <cgd@broadcom.com> 426 427 * mips.igen (do_load_double, do_store_double): New functions. 428 (LDC1, SDC1): Rename to... 429 (LDC1b, SDC1b): respectively. 430 (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support. 431 4322002-07-29 Michael Snyder <msnyder@redhat.com> 433 434 * cp1.c (fp_recip2): Modify initialization expression so that 435 GCC will recognize it as constant. 436 4372002-06-18 Chris Demetriou <cgd@broadcom.com> 438 439 * mdmx.c (SD_): Delete. 440 (Unpredictable): Re-define, for now, to directly invoke 441 unpredictable_action(). 442 (mdmx_acc_op): Fix error in .ob immediate handling. 443 4442002-06-18 Andrew Cagney <cagney@redhat.com> 445 446 * interp.c (sim_firmware_command): Initialize `address'. 447 4482002-06-16 Andrew Cagney <ac131313@redhat.com> 449 450 * configure: Regenerated to track ../common/aclocal.m4 changes. 451 4522002-06-14 Chris Demetriou <cgd@broadcom.com> 453 Ed Satterthwaite <ehs@broadcom.com> 454 455 * mips3d.igen: New file which contains MIPS-3D ASE instructions. 456 * Makefile.in (IGEN_INCLUDE): Add mips3d.igen. 457 * mips.igen: Include mips3d.igen. 458 (mips3d): New model name for MIPS-3D ASE instructions. 459 (CVT.W.fmt): Don't use this instruction for word (source) format 460 instructions. 461 * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32) 462 (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32) 463 (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions. 464 (NR_FRAC_GUARD, IMPLICIT_1): New macros. 465 * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2) 466 (RSquareRoot1, RSquareRoot2): New macros. 467 (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1) 468 (fp_rsqrt2): New functions. 469 * configure.in: Add MIPS-3D support to mipsisa64 simulator. 470 * configure: Regenerate. 471 4722002-06-13 Chris Demetriou <cgd@broadcom.com> 473 Ed Satterthwaite <ehs@broadcom.com> 474 475 * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros. 476 (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac) 477 (fp_inv_sqrt, fpu_format_name): Add paired-single support. 478 (convert): Note that this function is not used for paired-single 479 format conversions. 480 (ps_lower, ps_upper, pack_ps, convert_ps): New functions. 481 * mips.igen (FMT, MOVtf.fmt): Add paired-single support. 482 (check_fmt_p): Enable paired-single support. 483 (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS) 484 (PUU.PS): New instructions. 485 (CVT.S.fmt): Don't use this instruction for paired-single format 486 destinations. 487 * sim-main.h (FP_formats): New value 'fmt_ps.' 488 (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes. 489 (PSLower, PSUpper, PackPS, ConvertPS): New macros. 490 4912002-06-12 Chris Demetriou <cgd@broadcom.com> 492 493 * mips.igen: Fix formatting of function calls in 494 many FP operations. 495 4962002-06-12 Chris Demetriou <cgd@broadcom.com> 497 498 * mips.igen (MOVN, MOVZ): Trace result. 499 (TNEI): Print "tnei" as the opcode name in traces. 500 (CEIL.W): Add disassembly string for traces. 501 (RSQRT.fmt): Make location of disassembly string consistent 502 with other instructions. 503 5042002-06-12 Chris Demetriou <cgd@broadcom.com> 505 506 * mips.igen (X): Delete unused function. 507 5082002-06-08 Andrew Cagney <cagney@redhat.com> 509 510 * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h". 511 5122002-06-07 Chris Demetriou <cgd@broadcom.com> 513 Ed Satterthwaite <ehs@broadcom.com> 514 515 * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt) 516 (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions. 517 * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd) 518 (fp_nmsub): New prototypes. 519 (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd) 520 (NegMultiplySub): New defines. 521 * mips.igen (RSQRT.fmt): Use RSquareRoot(). 522 (MADD.D, MADD.S): Replace with... 523 (MADD.fmt): New instruction. 524 (MSUB.D, MSUB.S): Replace with... 525 (MSUB.fmt): New instruction. 526 (NMADD.D, NMADD.S): Replace with... 527 (NMADD.fmt): New instruction. 528 (NMSUB.D, MSUB.S): Replace with... 529 (NMSUB.fmt): New instruction. 530 5312002-06-07 Chris Demetriou <cgd@broadcom.com> 532 Ed Satterthwaite <ehs@broadcom.com> 533 534 * cp1.c: Fix more comment spelling and formatting. 535 (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value. 536 (denorm_mode): New function. 537 (fpu_unary, fpu_binary): Round results after operation, collect 538 status from rounding operations, and update the FCSR. 539 (convert): Collect status from integer conversions and rounding 540 operations, and update the FCSR. Adjust NaN values that result 541 from conversions. Convert to use sim_io_eprintf rather than 542 fprintf, and remove some debugging code. 543 * cp1.h (fenr_FS): New define. 544 5452002-06-07 Chris Demetriou <cgd@broadcom.com> 546 547 * cp1.c (convert): Remove unusable debugging code, and move MIPS 548 rounding mode to sim FP rounding mode flag conversion code into... 549 (rounding_mode): New function. 550 5512002-06-07 Chris Demetriou <cgd@broadcom.com> 552 553 * cp1.c: Clean up formatting of a few comments. 554 (value_fpr): Reformat switch statement. 555 5562002-06-06 Chris Demetriou <cgd@broadcom.com> 557 Ed Satterthwaite <ehs@broadcom.com> 558 559 * cp1.h: New file. 560 * sim-main.h: Include cp1.h. 561 (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE) 562 (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF) 563 (FP_RM_TOMINF, GETRM): Remove. Moved to cp1.h. 564 (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove. 565 (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes. 566 (ValueFCR, StoreFCR, TestFCSR, Compare): New macros. 567 * cp1.c: Don't include sim-fpu.h; already included by 568 sim-main.h. Clean up formatting of some comments. 569 (NaN, Equal, Less): Remove. 570 (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test) 571 (fp_cmp): New functions. 572 * mips.igen (do_c_cond_fmt): Remove. 573 (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with 574 Compare. Add result tracing. 575 (CxC1): Remove, replace with... 576 (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions. 577 (DMxC1): Remove, replace with... 578 (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions. 579 (MxC1): Remove, replace with... 580 (MFC1a, MFC1b, MTC1a, MTC1b): New instructions. 581 5822002-06-04 Chris Demetriou <cgd@broadcom.com> 583 584 * sim-main.h (FGRIDX): Remove, replace all uses with... 585 (FGR_BASE): New macro. 586 (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros. 587 (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member. 588 (NR_FGR, FGR): Likewise. 589 * interp.c: Replace all uses of FGRIDX with FGR_BASE. 590 * mips.igen: Likewise. 591 5922002-06-04 Chris Demetriou <cgd@broadcom.com> 593 594 * cp1.c: Add an FSF Copyright notice to this file. 595 5962002-06-04 Chris Demetriou <cgd@broadcom.com> 597 Ed Satterthwaite <ehs@broadcom.com> 598 599 * cp1.c (Infinity): Remove. 600 * sim-main.h (Infinity): Likewise. 601 602 * cp1.c (fp_unary, fp_binary): New functions. 603 (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip) 604 (fp_sqrt): New functions, implemented in terms of the above. 605 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) 606 (Recip, SquareRoot): Remove (replaced by functions above). 607 * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div) 608 (fp_recip, fp_sqrt): New prototypes. 609 (AbsoluteValue, Negate, Add, Sub, Multiply, Divide) 610 (Recip, SquareRoot): Replace prototypes with #defines which 611 invoke the functions above. 612 6132002-06-03 Chris Demetriou <cgd@broadcom.com> 614 615 * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate) 616 (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in 617 file, remove PARAMS from prototypes. 618 (value_fpr, store_fpr, convert): Likewise. Use SIM_STATE to provide 619 simulator state arguments. 620 (ValueFPR, StoreFPR, Convert): Move lower in file. Use SIM_ARGS to 621 pass simulator state arguments. 622 * cp1.c (SD): Redefine as CPU_STATE(cpu). 623 (store_fpr, convert): Remove 'sd' argument. 624 (value_fpr): Likewise. Convert to use 'SD' instead. 625 6262002-06-03 Chris Demetriou <cgd@broadcom.com> 627 628 * cp1.c (Min, Max): Remove #if 0'd functions. 629 * sim-main.h (Min, Max): Remove. 630 6312002-06-03 Chris Demetriou <cgd@broadcom.com> 632 633 * cp1.c: fix formatting of switch case and default labels. 634 * interp.c: Likewise. 635 * sim-main.c: Likewise. 636 6372002-06-03 Chris Demetriou <cgd@broadcom.com> 638 639 * cp1.c: Clean up comments which describe FP formats. 640 (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64. 641 6422002-06-03 Chris Demetriou <cgd@broadcom.com> 643 Ed Satterthwaite <ehs@broadcom.com> 644 645 * configure.in (mipsisa64sb1*-*-*): New target for supporting 646 Broadcom SiByte SB-1 processor configurations. 647 * configure: Regenerate. 648 * sb1.igen: New file. 649 * mips.igen: Include sb1.igen. 650 (sb1): New model. 651 * Makefile.in (IGEN_INCLUDE): Add sb1.igen. 652 * mdmx.igen: Add "sb1" model to all appropriate functions and 653 instructions. 654 * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions. 655 (ob_func, ob_acc): Reference the above. 656 (qh_acc): Adjust to keep the same size as ob_acc. 657 * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff) 658 (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros. 659 6602002-06-03 Chris Demetriou <cgd@broadcom.com> 661 662 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen. 663 6642002-06-02 Chris Demetriou <cgd@broadcom.com> 665 Ed Satterthwaite <ehs@broadcom.com> 666 667 * mips.igen (mdmx): New (pseudo-)model. 668 * mdmx.c, mdmx.igen: New files. 669 * Makefile.in (SIM_OBJS): Add mdmx.o. 670 * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48): 671 New typedefs. 672 (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp) 673 (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA) 674 (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC) 675 (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS) 676 (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES) 677 (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical) 678 (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL) 679 (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND) 680 (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA) 681 (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR) 682 (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB) 683 (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor) 684 (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel) 685 (qh_fmtsel): New macros. 686 (_sim_cpu): New member "acc". 687 (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op) 688 (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions. 689 6902002-05-01 Chris Demetriou <cgd@broadcom.com> 691 692 * interp.c: Use 'deprecated' rather than 'depreciated.' 693 * sim-main.h: Likewise. 694 6952002-05-01 Chris Demetriou <cgd@broadcom.com> 696 697 * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult 698 which wouldn't compile anyway. 699 * sim-main.h (unpredictable_action): New function prototype. 700 (Unpredictable): Define to call igen function unpredictable(). 701 (NotWordValue): New macro to call igen function not_word_value(). 702 (UndefinedResult): Remove. 703 * interp.c (undefined_result): Remove. 704 (unpredictable_action): New function. 705 * mips.igen (not_word_value, unpredictable): New functions. 706 (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL) 707 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu) 708 (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke 709 NotWordValue() to check for unpredictable inputs, then 710 Unpredictable() to handle them. 711 7122002-02-24 Chris Demetriou <cgd@broadcom.com> 713 714 * mips.igen: Fix formatting of calls to Unpredictable(). 715 7162002-04-20 Andrew Cagney <ac131313@redhat.com> 717 718 * interp.c (sim_open): Revert previous change. 719 7202002-04-18 Alexandre Oliva <aoliva@redhat.com> 721 722 * interp.c (sim_open): Disable chunk of code that wrote code in 723 vector table entries. 724 7252002-03-19 Chris Demetriou <cgd@broadcom.com> 726 727 * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f) 728 (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove 729 unused definitions. 730 7312002-03-19 Chris Demetriou <cgd@broadcom.com> 732 733 * cp1.c: Fix many formatting issues. 734 7352002-03-19 Chris G. Demetriou <cgd@broadcom.com> 736 737 * cp1.c (fpu_format_name): New function to replace... 738 (DOFMT): This. Delete, and update all callers. 739 (fpu_rounding_mode_name): New function to replace... 740 (RMMODE): This. Delete, and update all callers. 741 7422002-03-19 Chris G. Demetriou <cgd@broadcom.com> 743 744 * interp.c: Move FPU support routines from here to... 745 * cp1.c: Here. New file. 746 * Makefile.in (SIM_OBJS): Add cp1.o to object list. 747 (cp1.o): New target. 748 7492002-03-12 Chris Demetriou <cgd@broadcom.com> 750 751 * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets. 752 * mips.igen (mips32, mips64): New models, add to all instructions 753 and functions as appropriate. 754 (loadstore_ea, check_u64): New variant for model mips64. 755 (check_fmt_p): New variant for models mipsV and mips64, remove 756 mipsV model marking fro other variant. 757 (SLL) Rename to... 758 (SLLa) this. 759 (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions 760 for mips32 and mips64. 761 (DCLO, DCLZ): New instructions for mips64. 762 7632002-03-07 Chris Demetriou <cgd@broadcom.com> 764 765 * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print 766 immediate or code as a hex value with the "%#lx" format. 767 (ANDI): Likewise, and fix printed instruction name. 768 7692002-03-05 Chris Demetriou <cgd@broadcom.com> 770 771 * sim-main.h (UndefinedResult, Unpredictable): New macros 772 which currently do nothing. 773 7742002-03-05 Chris Demetriou <cgd@broadcom.com> 775 776 * sim-main.h (status_UX, status_SX, status_KX, status_TS) 777 (status_PX, status_MX, status_CU0, status_CU1, status_CU2) 778 (status_CU3): New definitions. 779 780 * sim-main.h (ExceptionCause): Add new values for MIPS32 781 and MIPS64: MDMX, MCheck, CacheErr. Update comments 782 for DebugBreakPoint and NMIReset to note their status in 783 MIPS32 and MIPS64. 784 (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck) 785 (SignalExceptionCacheErr): New exception macros. 786 7872002-03-05 Chris Demetriou <cgd@broadcom.com> 788 789 * mips.igen (check_fpu): Enable check for coprocessor 1 usability. 790 * sim-main.h (COP_Usable): Define, but for now coprocessor 1 791 is always enabled. 792 (SignalExceptionCoProcessorUnusable): Take as argument the 793 unusable coprocessor number. 794 7952002-03-05 Chris Demetriou <cgd@broadcom.com> 796 797 * mips.igen: Fix formatting of all SignalException calls. 798 7992002-03-05 Chris Demetriou <cgd@broadcom.com> 800 801 * sim-main.h (SIGNEXTEND): Remove. 802 8032002-03-04 Chris Demetriou <cgd@broadcom.com> 804 805 * mips.igen: Remove gencode comment from top of file, fix 806 spelling in another comment. 807 8082002-03-04 Chris Demetriou <cgd@broadcom.com> 809 810 * mips.igen (check_fmt, check_fmt_p): New functions to check 811 whether specific floating point formats are usable. 812 (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt) 813 (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt) 814 (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W): 815 Use the new functions. 816 (do_c_cond_fmt): Remove format checks... 817 (C.cond.fmta, C.cond.fmtb): And move them into all callers. 818 8192002-03-03 Chris Demetriou <cgd@broadcom.com> 820 821 * mips.igen: Fix formatting of check_fpu calls. 822 8232002-03-03 Chris Demetriou <cgd@broadcom.com> 824 825 * mips.igen (FLOOR.L.fmt): Store correct destination register. 826 8272002-03-03 Chris Demetriou <cgd@broadcom.com> 828 829 * mips.igen: Remove whitespace at end of lines. 830 8312002-03-02 Chris Demetriou <cgd@broadcom.com> 832 833 * mips.igen (loadstore_ea): New function to do effective 834 address calculations. 835 (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store, 836 do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1, 837 CACHE): Use loadstore_ea to do effective address computations. 838 8392002-03-02 Chris Demetriou <cgd@broadcom.com> 840 841 * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND. 842 * mips.igen (LL, CxC1, MxC1): Likewise. 843 8442002-03-02 Chris Demetriou <cgd@broadcom.com> 845 846 * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt, 847 CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, 848 FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt, 849 MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D, 850 NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, 851 SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE): 852 Don't split opcode fields by hand, use the opcode field values 853 provided by igen. 854 8552002-03-01 Chris Demetriou <cgd@broadcom.com> 856 857 * mips.igen (do_divu): Fix spacing. 858 859 * mips.igen (do_dsllv): Move to be right before DSLLV, 860 to match the rest of the do_<shift> functions. 861 8622002-03-01 Chris Demetriou <cgd@broadcom.com> 863 864 * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl, 865 DSRL32, do_dsrlv): Trace inputs and results. 866 8672002-03-01 Chris Demetriou <cgd@broadcom.com> 868 869 * mips.igen (CACHE): Provide instruction-printing string. 870 871 * interp.c (signal_exception): Comment tokens after #endif. 872 8732002-02-28 Chris Demetriou <cgd@broadcom.com> 874 875 * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32". 876 (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt, 877 NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt, 878 ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt, 879 CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta, 880 C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1, 881 SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D, 882 LWC1, SWC1): Add "f" to filter, since these are FP instructions. 883 8842002-02-28 Chris Demetriou <cgd@broadcom.com> 885 886 * mips.igen (DSRA32, DSRAV): Fix order of arguments in 887 instruction-printing string. 888 (LWU): Use '64' as the filter flag. 889 8902002-02-28 Chris Demetriou <cgd@broadcom.com> 891 892 * mips.igen (SDXC1): Fix instruction-printing string. 893 8942002-02-28 Chris Demetriou <cgd@broadcom.com> 895 896 * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with 897 filter flags "32,f". 898 8992002-02-27 Chris Demetriou <cgd@broadcom.com> 900 901 * mips.igen (PREFX): This is a 64-bit instruction, use '64' 902 as the filter flag. 903 9042002-02-27 Chris Demetriou <cgd@broadcom.com> 905 906 * mips.igen (PREFX): Tweak instruction opcode fields (i.e., 907 add a comma) so that it more closely match the MIPS ISA 908 documentation opcode partitioning. 909 (PREF): Put useful names on opcode fields, and include 910 instruction-printing string. 911 9122002-02-27 Chris Demetriou <cgd@broadcom.com> 913 914 * mips.igen (check_u64): New function which in the future will 915 check whether 64-bit instructions are usable and signal an 916 exception if not. Currently a no-op. 917 (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL, 918 DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, 919 DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1, 920 LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64. 921 922 * mips.igen (check_fpu): New function which in the future will 923 check whether FPU instructions are usable and signal an exception 924 if not. Currently a no-op. 925 (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb, 926 CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, 927 CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1, 928 LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf, 929 MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, 930 NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt, 931 ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1, 932 SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu. 933 9342002-02-27 Chris Demetriou <cgd@broadcom.com> 935 936 * mips.igen (do_load_left, do_load_right): Move to be immediately 937 following do_load. 938 (do_store_left, do_store_right): Move to be immediately following 939 do_store. 940 9412002-02-27 Chris Demetriou <cgd@broadcom.com> 942 943 * mips.igen (mipsV): New model name. Also, add it to 944 all instructions and functions where it is appropriate. 945 9462002-02-18 Chris Demetriou <cgd@broadcom.com> 947 948 * mips.igen: For all functions and instructions, list model 949 names that support that instruction one per line. 950 9512002-02-11 Chris Demetriou <cgd@broadcom.com> 952 953 * mips.igen: Add some additional comments about supported 954 models, and about which instructions go where. 955 (BC1b, MFC0, MTC0, RFE): Sort supported models in the same 956 order as is used in the rest of the file. 957 9582002-02-11 Chris Demetriou <cgd@broadcom.com> 959 960 * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment 961 indicating that ALU32_END or ALU64_END are there to check 962 for overflow. 963 (DADD): Likewise, but also remove previous comment about 964 overflow checking. 965 9662002-02-10 Chris Demetriou <cgd@broadcom.com> 967 968 * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32, 969 DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU, 970 JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU, 971 SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI, 972 ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode 973 fields (i.e., add and move commas) so that they more closely 974 match the MIPS ISA documentation opcode partitioning. 975 9762002-02-10 Chris Demetriou <cgd@broadcom.com> 977 978 * mips.igen (ADDI): Print immediate value. 979 (BREAK): Print code. 980 (DADDIU, DSRAV, DSRLV): Print correct instruction name. 981 (SLL): Print "nop" specially, and don't run the code 982 that does the shift for the "nop" case. 983 9842001-11-17 Fred Fish <fnf@redhat.com> 985 986 * sim-main.h (float_operation): Move enum declaration outside 987 of _sim_cpu struct declaration. 988 9892001-04-12 Jim Blandy <jimb@redhat.com> 990 991 * mips.igen (CFC1, CTC1): Pass the correct register numbers to 992 PENDING_FILL. Use PENDING_SCHED directly to handle the pending 993 set of the FCSR. 994 * sim-main.h (COCIDX): Remove definition; this isn't supported by 995 PENDING_FILL, and you can get the intended effect gracefully by 996 calling PENDING_SCHED directly. 997 9982001-02-23 Ben Elliston <bje@redhat.com> 999 1000 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not 1001 already defined elsewhere. 1002 10032001-02-19 Ben Elliston <bje@redhat.com> 1004 1005 * sim-main.h (sim_monitor): Return an int. 1006 * interp.c (sim_monitor): Add return values. 1007 (signal_exception): Handle error conditions from sim_monitor. 1008 10092001-02-08 Ben Elliston <bje@redhat.com> 1010 1011 * sim-main.c (load_memory): Pass cia to sim_core_read* functions. 1012 (store_memory): Likewise, pass cia to sim_core_write*. 1013 10142000-10-19 Frank Ch. Eigler <fche@redhat.com> 1015 1016 On advice from Chris G. Demetriou <cgd@sibyte.com>: 1017 * sim-main.h (GPR_CLEAR): Remove unused alternative macro. 1018 1019Thu Jul 27 22:02:05 2000 Andrew Cagney <cagney@b1.cygnus.com> 1020 1021 From Maciej W. Rozycki <macro@ds2.pg.gda.pl>: 1022 * Makefile.in: Don't delete *.igen when cleaning directory. 1023 1024Wed Jul 19 18:50:51 2000 Andrew Cagney <cagney@b1.cygnus.com> 1025 1026 * m16.igen (break): Call SignalException not sim_engine_halt. 1027 1028Mon Jul 3 11:13:20 2000 Andrew Cagney <cagney@b1.cygnus.com> 1029 1030 From Jason Eckhardt: 1031 * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT]. 1032 1033Tue Jun 13 20:52:07 2000 Andrew Cagney <cagney@b1.cygnus.com> 1034 1035 * mips.igen (MxC1, DMxC1): Fix printf formatting. 1036 10372000-05-24 Michael Hayes <mhayes@cygnus.com> 1038 1039 * mips.igen (do_dmultx): Fix typo. 1040 1041Tue May 23 21:39:23 2000 Andrew Cagney <cagney@b1.cygnus.com> 1042 1043 * configure: Regenerated to track ../common/aclocal.m4 changes. 1044 1045Fri Apr 28 20:48:36 2000 Andrew Cagney <cagney@b1.cygnus.com> 1046 1047 * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call. 1048 10492000-04-12 Frank Ch. Eigler <fche@redhat.com> 1050 1051 * sim-main.h (GPR_CLEAR): Define macro. 1052 1053Mon Apr 10 00:07:09 2000 Andrew Cagney <cagney@b1.cygnus.com> 1054 1055 * interp.c (decode_coproc): Output long using %lx and not %s. 1056 10572000-03-21 Frank Ch. Eigler <fche@redhat.com> 1058 1059 * interp.c (sim_open): Sort & extend dummy memory regions for 1060 --board=jmr3904 for eCos. 1061 10622000-03-02 Frank Ch. Eigler <fche@redhat.com> 1063 1064 * configure: Regenerated. 1065 1066Tue Feb 8 18:35:01 2000 Donald Lindsay <dlindsay@hound.cygnus.com> 1067 1068 * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf 1069 calls, conditional on the simulator being in verbose mode. 1070 1071Fri Feb 4 09:45:15 2000 Donald Lindsay <dlindsay@cygnus.com> 1072 1073 * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary 1074 cache don't get ReservedInstruction traps. 1075 10761999-11-29 Mark Salter <msalter@cygnus.com> 1077 1078 * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask 1079 to clear status bits in sdisr register. This is how the hardware works. 1080 1081 * interp.c (sim_open): Added more memory aliases for jmr3904 hardware 1082 being used by cygmon. 1083 10841999-11-11 Andrew Haley <aph@cygnus.com> 1085 1086 * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0 1087 instructions. 1088 1089Thu Sep 9 15:12:08 1999 Geoffrey Keating <geoffk@cygnus.com> 1090 1091 * mips.igen (MULT): Correct previous mis-applied patch. 1092 1093Tue Sep 7 13:34:54 1999 Geoffrey Keating <geoffk@cygnus.com> 1094 1095 * mips.igen (delayslot32): Handle sequence like 1096 mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12 1097 correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue. 1098 (MULT): Actually pass the third register... 1099 11001999-09-03 Mark Salter <msalter@cygnus.com> 1101 1102 * interp.c (sim_open): Added more memory aliases for additional 1103 hardware being touched by cygmon on jmr3904 board. 1104 1105Thu Sep 2 18:15:53 1999 Andrew Cagney <cagney@b1.cygnus.com> 1106 1107 * configure: Regenerated to track ../common/aclocal.m4 changes. 1108 1109Tue Jul 27 16:36:51 1999 Andrew Cagney <cagney@amy.cygnus.com> 1110 1111 * interp.c (sim_store_register): Handle case where client - GDB - 1112 specifies that a 4 byte register is 8 bytes in size. 1113 (sim_fetch_register): Ditto. 1114 11151999-07-14 Frank Ch. Eigler <fche@cygnus.com> 1116 1117 Implement "sim firmware" option, inspired by jimb's version of 1998-01. 1118 * interp.c (firmware_option_p): New global flag: "sim firmware" given. 1119 (idt_monitor_base): Base address for IDT monitor traps. 1120 (pmon_monitor_base): Ditto for PMON. 1121 (lsipmon_monitor_base): Ditto for LSI PMON. 1122 (MONITOR_BASE, MONITOR_SIZE): Removed macros. 1123 (mips_option): Add "firmware" option with new OPTION_FIRMWARE key. 1124 (sim_firmware_command): New function. 1125 (mips_option_handler): Call it for OPTION_FIRMWARE. 1126 (sim_open): Allocate memory for idt_monitor region. If "--board" 1127 option was given, add no monitor by default. Add BREAK hooks only if 1128 monitors are also there. 1129 1130Mon Jul 12 00:02:27 1999 Andrew Cagney <cagney@amy.cygnus.com> 1131 1132 * interp.c (sim_monitor): Flush output before reading input. 1133 1134Sun Jul 11 19:28:11 1999 Andrew Cagney <cagney@b1.cygnus.com> 1135 1136 * tconfig.in (SIM_HANDLES_LMA): Always define. 1137 1138Thu Jul 8 16:06:59 1999 Andrew Cagney <cagney@b1.cygnus.com> 1139 1140 From Mark Salter <msalter@cygnus.com>: 1141 * interp.c (BOARD_BSP): Define. Add to list of possible boards. 1142 (sim_open): Add setup for BSP board. 1143 1144Wed Jul 7 12:45:58 1999 Andrew Cagney <cagney@b1.cygnus.com> 1145 1146 * mips.igen (MULT, MULTU): Add syntax for two operand version. 1147 (DMFC0, DMTC0): Recognize. Call DecodeCoproc which will report 1148 them as unimplemented. 1149 11501999-05-08 Felix Lee <flee@cygnus.com> 1151 1152 * configure: Regenerated to track ../common/aclocal.m4 changes. 1153 11541999-04-21 Frank Ch. Eigler <fche@cygnus.com> 1155 1156 * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub. 1157 1158Thu Apr 15 14:15:17 1999 Andrew Cagney <cagney@amy.cygnus.com> 1159 1160 * configure.in: Any mips64vr5*-*-* target should have 1161 -DTARGET_ENABLE_FR=1. 1162 (default_endian): Any mips64vr*el-*-* target should default to 1163 LITTLE_ENDIAN. 1164 * configure: Re-generate. 1165 11661999-02-19 Gavin Romig-Koch <gavin@cygnus.com> 1167 1168 * mips.igen (ldl): Extend from _16_, not 32. 1169 1170Wed Jan 27 18:51:38 1999 Andrew Cagney <cagney@chook.cygnus.com> 1171 1172 * interp.c (sim_store_register): Force registers written to by GDB 1173 into an un-interpreted state. 1174 11751999-02-05 Frank Ch. Eigler <fche@cygnus.com> 1176 1177 * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the 1178 CPU, start periodic background I/O polls. 1179 (tx3904sio_poll): New function: periodic I/O poller. 1180 11811998-12-30 Frank Ch. Eigler <fche@cygnus.com> 1182 1183 * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt. 1184 1185Tue Dec 29 16:03:53 1998 Rainer Orth <ro@TechFak.Uni-Bielefeld.DE> 1186 1187 * configure.in, configure (mips64vr5*-*-*): Added missing ;; in 1188 case statement. 1189 11901998-12-29 Frank Ch. Eigler <fche@cygnus.com> 1191 1192 * interp.c (sim_open): Allocate jm3904 memory in smaller chunks. 1193 (load_word): Call SIM_CORE_SIGNAL hook on error. 1194 (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before 1195 starting. For exception dispatching, pass PC instead of NULL_CIA. 1196 (decode_coproc): Use COP0_BADVADDR to store faulting address. 1197 * sim-main.h (COP0_BADVADDR): Define. 1198 (SIM_CORE_SIGNAL): Define hook to call mips_core_signal. 1199 (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*(). 1200 (_sim_cpu): Add exc_* fields to store register value snapshots. 1201 * mips.igen (*): Replace memory-related SignalException* calls 1202 with references to SIM_CORE_SIGNAL hook. 1203 1204 * dv-tx3904irc.c (tx3904irc_port_event): printf format warning 1205 fix. 1206 * sim-main.c (*): Minor warning cleanups. 1207 12081998-12-24 Gavin Romig-Koch <gavin@cygnus.com> 1209 1210 * m16.igen (DADDIU5): Correct type-o. 1211 1212Mon Dec 21 10:34:48 1998 Andrew Cagney <cagney@chook> 1213 1214 * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp 1215 variables. 1216 1217Wed Dec 16 18:20:28 1998 Andrew Cagney <cagney@chook> 1218 1219 * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib 1220 to include path. 1221 (interp.o): Add dependency on itable.h 1222 (oengine.c, gencode): Delete remaining references. 1223 (BUILT_SRC_FROM_GEN): Clean up. 1224 12251998-12-16 Gavin Romig-Koch <gavin@cygnus.com> 1226 1227 * vr4run.c: New. 1228 * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a, 1229 tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack, 1230 tmp-run-hack) : New. 1231 * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU, 1232 DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX): 1233 Drop the "64" qualifier to get the HACK generator working. 1234 Use IMMEDIATE rather than IMMED. Use SHAMT rather than SHIFT. 1235 * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only 1236 qualifier to get the hack generator working. 1237 (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New. 1238 (DSLL): Use do_dsll. 1239 (DSLLV): Use do_dsllv. 1240 (DSRA): Use do_dsra. 1241 (DSRL): Use do_dsrl. 1242 (DSRLV): Use do_dsrlv. 1243 (BC1): Move *vr4100 to get the HACK generator working. 1244 (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to 1245 get the HACK generator working. 1246 (MACC) Rename to get the HACK generator working. 1247 (DMACC,MACCS,DMACCS): Add the 64. 1248 12491998-12-12 Gavin Romig-Koch <gavin@cygnus.com> 1250 1251 * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts. 1252 * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR. 1253 12541998-12-11 Gavin Romig-Koch <gavin@cygnus.com> 1255 1256 * mips/interp.c (DEBUG): Cleanups. 1257 12581998-12-10 Frank Ch. Eigler <fche@cygnus.com> 1259 1260 * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes. 1261 (tx3904sio_tickle): fflush after a stdout character output. 1262 12631998-12-03 Frank Ch. Eigler <fche@cygnus.com> 1264 1265 * interp.c (sim_close): Uninstall modules. 1266 1267Wed Nov 25 13:41:03 1998 Andrew Cagney <cagney@b1.cygnus.com> 1268 1269 * sim-main.h, interp.c (sim_monitor): Change to global 1270 function. 1271 1272Wed Nov 25 17:33:24 1998 Andrew Cagney <cagney@b1.cygnus.com> 1273 1274 * configure.in (vr4100): Only include vr4100 instructions in 1275 simulator. 1276 * configure: Re-generate. 1277 * m16.igen (*): Tag all mips16 instructions as also being vr4100. 1278 1279Mon Nov 23 18:20:36 1998 Andrew Cagney <cagney@b1.cygnus.com> 1280 1281 * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN. 1282 * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping 1283 true alternative. 1284 1285 * configure.in (sim_default_gen, sim_use_gen): Replace with 1286 sim_gen. 1287 (--enable-sim-igen): Delete config option. Always using IGEN. 1288 * configure: Re-generate. 1289 1290 * Makefile.in (gencode): Kill, kill, kill. 1291 * gencode.c: Ditto. 1292 1293Mon Nov 23 18:07:36 1998 Andrew Cagney <cagney@b1.cygnus.com> 1294 1295 * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64 1296 bit mips16 igen simulator. 1297 * configure: Re-generate. 1298 1299 * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark 1300 as part of vr4100 ISA. 1301 * vr.igen: Mark all instructions as 64 bit only. 1302 1303Mon Nov 23 17:07:37 1998 Andrew Cagney <cagney@b1.cygnus.com> 1304 1305 * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent): 1306 Pacify GCC. 1307 1308Mon Nov 23 13:23:40 1998 Andrew Cagney <cagney@b1.cygnus.com> 1309 1310 * configure.in: Configure mips-lsi-elf nee mips*lsi* as a 1311 mipsIII/mips16 igen simulator. Fix sim_gen VS sim_igen typos. 1312 * configure: Re-generate. 1313 1314 * m16.igen (BREAK): Define breakpoint instruction. 1315 (JALX32): Mark instruction as mips16 and not r3900. 1316 * mips.igen (C.cond.fmt): Fix typo in instruction format. 1317 1318 * sim-main.h (PENDING_FILL): Wrap C statements in do/while. 1319 1320Sat Nov 7 09:54:38 1998 Andrew Cagney <cagney@b1.cygnus.com> 1321 1322 * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK 1323 insn as a debug breakpoint. 1324 1325 * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as 1326 pending.slot_size. 1327 (PENDING_SCHED): Clean up trace statement. 1328 (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL. 1329 (PENDING_FILL): Delay write by only one cycle. 1330 (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE. 1331 1332 * sim-main.c (pending_tick): Clean up trace statements. Add trace 1333 of pending writes. 1334 (pending_tick): Fix sizes in switch statements, 4 & 8 instead of 1335 32 & 64. 1336 (pending_tick): Move incrementing of index to FOR statement. 1337 (pending_tick): Only update PENDING_OUT after a write has occured. 1338 1339 * configure.in: Add explicit mips-lsi-* target. Use gencode to 1340 build simulator. 1341 * configure: Re-generate. 1342 1343 * interp.c (sim_engine_run OLD): Delete explicit call to 1344 PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK. 1345 1346Sat Oct 30 09:49:10 1998 Frank Ch. Eigler <fche@cygnus.com> 1347 1348 * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy 1349 interrupt level number to match changed SignalExceptionInterrupt 1350 macro. 1351 1352Fri Oct 9 18:02:25 1998 Doug Evans <devans@canuck.cygnus.com> 1353 1354 * interp.c: #include "itable.h" if WITH_IGEN. 1355 (get_insn_name): New function. 1356 (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS. 1357 * sim-main.h (MAX_INSNS,INSN_NAME): Delete. 1358 1359Mon Sep 14 12:36:44 1998 Frank Ch. Eigler <fche@cygnus.com> 1360 1361 * configure: Rebuilt to inhale new common/aclocal.m4. 1362 1363Tue Sep 1 15:39:18 1998 Frank Ch. Eigler <fche@cygnus.com> 1364 1365 * dv-tx3904sio.c: Include sim-assert.h. 1366 1367Tue Aug 25 12:49:46 1998 Frank Ch. Eigler <fche@cygnus.com> 1368 1369 * dv-tx3904sio.c: New file: tx3904 serial I/O module. 1370 * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target. 1371 Reorganize target-specific sim-hardware checks. 1372 * configure: rebuilt. 1373 * interp.c (sim_open): For tx39 target boards, set 1374 OPERATING_ENVIRONMENT, add tx3904sio devices. 1375 * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading 1376 ROM executables. Install dv-sockser into sim-modules list. 1377 1378 * dv-tx3904irc.c: Compiler warning clean-up. 1379 * dv-tx3904tmr.c: Compiler warning clean-up. Remove particularly 1380 frequent hw-trace messages. 1381 1382Fri Jul 31 18:14:16 1998 Andrew Cagney <cagney@b1.cygnus.com> 1383 1384 * vr.igen (MulAcc): Identify as a vr4100 specific function. 1385 1386Sat Jul 25 16:03:14 1998 Andrew Cagney <cagney@b1.cygnus.com> 1387 1388 * Makefile.in (IGEN_INCLUDE): Add vr.igen. 1389 1390 * vr.igen: New file. 1391 (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c. 1392 * mips.igen: Define vr4100 model. Include vr.igen. 1393Mon Jun 29 09:21:07 1998 Gavin Koch <gavin@cygnus.com> 1394 1395 * mips.igen (check_mf_hilo): Correct check. 1396 1397Wed Jun 17 12:20:49 1998 Andrew Cagney <cagney@b1.cygnus.com> 1398 1399 * sim-main.h (interrupt_event): Add prototype. 1400 1401 * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused 1402 register_ptr, register_value. 1403 (deliver_tx3904tmr_tick): Fix types passed to printf fmt. 1404 1405 * sim-main.h (tracefh): Make extern. 1406 1407Tue Jun 16 14:39:00 1998 Frank Ch. Eigler <fche@cygnus.com> 1408 1409 * dv-tx3904tmr.c: Deschedule timer event after dispatching. 1410 Reduce unnecessarily high timer event frequency. 1411 * dv-tx3904cpu.c: Ditto for interrupt event. 1412 1413Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com> 1414 1415 * interp.c (decode_coproc): For TX39, add stub COP0 register #7, 1416 to allay warnings. 1417 (interrupt_event): Made non-static. 1418 1419 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental 1420 interchange of configuration values for external vs. internal 1421 clock dividers. 1422 1423Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com> 1424 1425 * mips.igen (BREAK): Moved code to here for 1426 simulator-reserved break instructions. 1427 * gencode.c (build_instruction): Ditto. 1428 * interp.c (signal_exception): Code moved from here. Non- 1429 reserved instructions now use exception vector, rather 1430 than halting sim. 1431 * sim-main.h: Moved magic constants to here. 1432 1433Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com> 1434 1435 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE 1436 register upon non-zero interrupt event level, clear upon zero 1437 event value. 1438 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal 1439 by passing zero event value. 1440 (*_io_{read,write}_buffer): Endianness fixes. 1441 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes. 1442 (deliver_*_tick): Reduce sim event interval to 75% of count interval. 1443 1444 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based 1445 serial I/O and timer module at base address 0xFFFF0000. 1446 1447Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com> 1448 1449 * mips.igen (SWC1) : Correct the handling of ReverseEndian 1450 and BigEndianCPU. 1451 1452Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com> 1453 1454 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips 1455 parts. 1456 * configure: Update. 1457 1458Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com> 1459 1460 * dv-tx3904tmr.c: New file - implements tx3904 timer. 1461 * dv-tx3904{irc,cpu}.c: Mild reformatting. 1462 * configure.in: Include tx3904tmr in hw_device list. 1463 * configure: Rebuilt. 1464 * interp.c (sim_open): Instantiate three timer instances. 1465 Fix address typo of tx3904irc instance. 1466 1467Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com> 1468 1469 * interp.c (signal_exception): SystemCall exception now uses 1470 the exception vector. 1471 1472Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com> 1473 1474 * interp.c (decode_coproc): For TX39, add stub COP0 register #3, 1475 to allay warnings. 1476 1477Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com> 1478 1479 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39. 1480 1481Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com> 1482 1483 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method. 1484 1485 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and 1486 sim-main.h. Declare a struct hw_descriptor instead of struct 1487 hw_device_descriptor. 1488 1489Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com> 1490 1491 * mips.igen (do_store_left, do_load_left): Compute nr of left and 1492 right bits and then re-align left hand bytes to correct byte 1493 lanes. Fix incorrect computation in do_store_left when loading 1494 bytes from second word. 1495 1496Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com> 1497 1498 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904. 1499 * interp.c (sim_open): Only create a device tree when HW is 1500 enabled. 1501 1502 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC. 1503 * interp.c (signal_exception): Ditto. 1504 1505Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com> 1506 1507 * gencode.c: Mark BEGEZALL as LIKELY. 1508 1509Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com> 1510 1511 * sim-main.h (ALU32_END): Sign extend 32 bit results. 1512 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace. 1513 1514Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com> 1515 1516 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware 1517 modules. Recognize TX39 target with "mips*tx39" pattern. 1518 * configure: Rebuilt. 1519 * sim-main.h (*): Added many macros defining bits in 1520 TX39 control registers. 1521 (SignalInterrupt): Send actual PC instead of NULL. 1522 (SignalNMIReset): New exception type. 1523 * interp.c (board): New variable for future use to identify 1524 a particular board being simulated. 1525 (mips_option_handler,mips_options): Added "--board" option. 1526 (interrupt_event): Send actual PC. 1527 (sim_open): Make memory layout conditional on board setting. 1528 (signal_exception): Initial implementation of hardware interrupt 1529 handling. Accept another break instruction variant for simulator 1530 exit. 1531 (decode_coproc): Implement RFE instruction for TX39. 1532 (mips.igen): Decode RFE instruction as such. 1533 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904. 1534 * interp.c: Define "jmr3904" and "jmr3904debug" board types and 1535 bbegin to implement memory map. 1536 * dv-tx3904cpu.c: New file. 1537 * dv-tx3904irc.c: New file. 1538 1539Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com> 1540 1541 * mips.igen (check_mt_hilo): Create a separate r3900 version. 1542 1543Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com> 1544 1545 * tx.igen (madd,maddu): Replace calls to check_op_hilo 1546 with calls to check_div_hilo. 1547 1548Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com> 1549 1550 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo): 1551 Replace check_op_hilo with check_mult_hilo and check_div_hilo. 1552 Add special r3900 version of do_mult_hilo. 1553 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo 1554 with calls to check_mult_hilo. 1555 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo 1556 with calls to check_div_hilo. 1557 1558Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com> 1559 1560 * configure.in (SUBTARGET_R3900): Define for mipstx39 target. 1561 Document a replacement. 1562 1563Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com> 1564 1565 * interp.c (sim_monitor): Make mon_printf work. 1566 1567Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com> 1568 1569 * sim-main.h (INSN_NAME): New arg `cpu'. 1570 1571Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com> 1572 1573 * configure: Regenerated to track ../common/aclocal.m4 changes. 1574 1575Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche> 1576 1577 * configure: Regenerated to track ../common/aclocal.m4 changes. 1578 * config.in: Ditto. 1579 1580Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com> 1581 1582 * acconfig.h: New file. 1583 * configure.in: Reverted change of Apr 24; use sinclude again. 1584 1585Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche> 1586 1587 * configure: Regenerated to track ../common/aclocal.m4 changes. 1588 * config.in: Ditto. 1589 1590Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com> 1591 1592 * configure.in: Don't call sinclude. 1593 1594Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com> 1595 1596 * mips.igen (do_store_left): Pass 0 not NULL to store_memory. 1597 1598Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com> 1599 1600 * mips.igen (ERET): Implement. 1601 1602 * interp.c (decode_coproc): Return sign-extended EPC. 1603 1604 * mips.igen (ANDI, LUI, MFC0): Add tracing code. 1605 1606 * interp.c (signal_exception): Do not ignore Trap. 1607 (signal_exception): On TRAP, restart at exception address. 1608 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define. 1609 (signal_exception): Update. 1610 (sim_open): Patch V_COMMON interrupt vector with an abort sequence 1611 so that TRAP instructions are caught. 1612 1613Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com> 1614 1615 * sim-main.h (struct hilo_access, struct hilo_history): Define, 1616 contains HI/LO access history. 1617 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access. 1618 (HIACCESS, LOACCESS): Delete, replace with 1619 (HIHISTORY, LOHISTORY): New macros. 1620 (CHECKHILO): Delete all, moved to mips.igen 1621 1622 * gencode.c (build_instruction): Do not generate checks for 1623 correct HI/LO register usage. 1624 1625 * interp.c (old_engine_run): Delete checks for correct HI/LO 1626 register usage. 1627 1628 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo, 1629 check_mf_cycles): New functions. 1630 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div, 1631 do_divu, domultx, do_mult, do_multu): Use. 1632 1633 * tx.igen ("madd", "maddu"): Use. 1634 1635Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com> 1636 1637 * mips.igen (DSRAV): Use function do_dsrav. 1638 (SRAV): Use new function do_srav. 1639 1640 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX]. 1641 (B): Sign extend 11 bit immediate. 1642 (EXT-B*): Shift 16 bit immediate left by 1. 1643 (ADDIU*): Don't sign extend immediate value. 1644 1645Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com> 1646 1647 * m16run.c (sim_engine_run): Restore CIA after handling an event. 1648 1649 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use 1650 functions. 1651 1652 * mips.igen (delayslot32, nullify_next_insn): New functions. 1653 (m16.igen): Always include. 1654 (do_*): Add more tracing. 1655 1656 * m16.igen (delayslot16): Add NIA argument, could be called by a 1657 32 bit MIPS16 instruction. 1658 1659 * interp.c (ifetch16): Move function from here. 1660 * sim-main.c (ifetch16): To here. 1661 1662 * sim-main.c (ifetch16, ifetch32): Update to match current 1663 implementations of LH, LW. 1664 (signal_exception): Don't print out incorrect hex value of illegal 1665 instruction. 1666 1667Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com> 1668 1669 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an 1670 instruction. 1671 1672 * m16.igen: Implement MIPS16 instructions. 1673 1674 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu, 1675 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav, 1676 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or, 1677 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra, 1678 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move 1679 bodies of corresponding code from 32 bit insn to these. Also used 1680 by MIPS16 versions of functions. 1681 1682 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define. 1683 (IMEM16): Drop NR argument from macro. 1684 1685Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com> 1686 1687 * Makefile.in (SIM_OBJS): Add sim-main.o. 1688 1689 * sim-main.h (address_translation, load_memory, store_memory, 1690 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark 1691 as INLINE_SIM_MAIN. 1692 (pr_addr, pr_uword64): Declare. 1693 (sim-main.c): Include when H_REVEALS_MODULE_P. 1694 1695 * interp.c (address_translation, load_memory, store_memory, 1696 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move 1697 from here. 1698 * sim-main.c: To here. Fix compilation problems. 1699 1700 * configure.in: Enable inlining. 1701 * configure: Re-config. 1702 1703Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com> 1704 1705 * configure: Regenerated to track ../common/aclocal.m4 changes. 1706 1707Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com> 1708 1709 * mips.igen: Include tx.igen. 1710 * Makefile.in (IGEN_INCLUDE): Add tx.igen. 1711 * tx.igen: New file, contains MADD and MADDU. 1712 1713 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not 1714 the hardwired constant `7'. 1715 (store_memory): Ditto. 1716 (LOADDRMASK): Move definition to sim-main.h. 1717 1718 mips.igen (MTC0): Enable for r3900. 1719 (ADDU): Add trace. 1720 1721 mips.igen (do_load_byte): Delete. 1722 (do_load, do_store, do_load_left, do_load_write, do_store_left, 1723 do_store_right): New functions. 1724 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use. 1725 1726 configure.in: Let the tx39 use igen again. 1727 configure: Update. 1728 1729Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com> 1730 1731 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity, 1732 not an address sized quantity. Return zero for cache sizes. 1733 1734Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com> 1735 1736 * mips.igen (r3900): r3900 does not support 64 bit integer 1737 operations. 1738 1739Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com> 1740 1741 * configure.in (mipstx39*-*-*): Use gencode simulator rather 1742 than igen one. 1743 * configure : Rebuild. 1744 1745Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com> 1746 1747 * configure: Regenerated to track ../common/aclocal.m4 changes. 1748 1749Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com> 1750 1751 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS. 1752 1753Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com> 1754 1755 * configure: Regenerated to track ../common/aclocal.m4 changes. 1756 * config.in: Regenerated to track ../common/aclocal.m4 changes. 1757 1758Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com> 1759 1760 * configure: Regenerated to track ../common/aclocal.m4 changes. 1761 1762Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com> 1763 1764 * interp.c (Max, Min): Comment out functions. Not yet used. 1765 1766Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com> 1767 1768 * configure: Regenerated to track ../common/aclocal.m4 changes. 1769 1770Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com> 1771 1772 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added 1773 configurable settings for stand-alone simulator. 1774 1775 * configure.in: Added X11 search, just in case. 1776 1777 * configure: Regenerated. 1778 1779Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com> 1780 1781 * interp.c (sim_write, sim_read, load_memory, store_memory): 1782 Replace sim_core_*_map with read_map, write_map, exec_map resp. 1783 1784Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com> 1785 1786 * sim-main.h (GETFCC): Return an unsigned value. 1787 1788Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com> 1789 1790 * mips.igen (DIV): Fix check for -1 / MIN_INT. 1791 (DADD): Result destination is RD not RT. 1792 1793Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com> 1794 1795 * sim-main.h (HIACCESS, LOACCESS): Always define. 1796 1797 * mdmx.igen (Maxi, Mini): Rename Max, Min. 1798 1799 * interp.c (sim_info): Delete. 1800 1801Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com> 1802 1803 * interp.c (DECLARE_OPTION_HANDLER): Use it. 1804 (mips_option_handler): New argument `cpu'. 1805 (sim_open): Update call to sim_add_option_table. 1806 1807Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com> 1808 1809 * mips.igen (CxC1): Add tracing. 1810 1811Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com> 1812 1813 * sim-main.h (Max, Min): Declare. 1814 1815 * interp.c (Max, Min): New functions. 1816 1817 * mips.igen (BC1): Add tracing. 1818 1819Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com> 1820 1821 * interp.c Added memory map for stack in vr4100 1822 1823Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com> 1824 1825 * interp.c (load_memory): Add missing "break"'s. 1826 1827Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com> 1828 1829 * interp.c (sim_store_register, sim_fetch_register): Pass in 1830 length parameter. Return -1. 1831 1832Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com> 1833 1834 * interp.c: Added hardware init hook, fixed warnings. 1835 1836Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com> 1837 1838 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL. 1839 1840Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com> 1841 1842 * interp.c (ifetch16): New function. 1843 1844 * sim-main.h (IMEM32): Rename IMEM. 1845 (IMEM16_IMMED): Define. 1846 (IMEM16): Define. 1847 (DELAY_SLOT): Update. 1848 1849 * m16run.c (sim_engine_run): New file. 1850 1851 * m16.igen: All instructions except LB. 1852 (LB): Call do_load_byte. 1853 * mips.igen (do_load_byte): New function. 1854 (LB): Call do_load_byte. 1855 1856 * mips.igen: Move spec for insn bit size and high bit from here. 1857 * Makefile.in (tmp-igen, tmp-m16): To here. 1858 1859 * m16.dc: New file, decode mips16 instructions. 1860 1861 * Makefile.in (SIM_NO_ALL): Define. 1862 (tmp-m16): Generate both 16 bit and 32 bit simulator engines. 1863 1864Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com> 1865 1866 * configure.in (mips_fpu_bitsize): For tx39, restrict floating 1867 point unit to 32 bit registers. 1868 * configure: Re-generate. 1869 1870Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com> 1871 1872 * configure.in (sim_use_gen): Make IGEN the default simulator 1873 generator for generic 32 and 64 bit mips targets. 1874 * configure: Re-generate. 1875 1876Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com> 1877 1878 * sim-main.h (SizeFGR): Determine from floating-point and not gpr 1879 bitsize. 1880 1881 * interp.c (sim_fetch_register, sim_store_register): Read/write 1882 FGR from correct location. 1883 (sim_open): Set size of FGR's according to 1884 WITH_TARGET_FLOATING_POINT_BITSIZE. 1885 1886 * sim-main.h (FGR): Store floating point registers in a separate 1887 array. 1888 1889Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com> 1890 1891 * configure: Regenerated to track ../common/aclocal.m4 changes. 1892 1893Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com> 1894 1895 * interp.c (ColdReset): Call PENDING_INVALIDATE. 1896 1897 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK. 1898 1899 * interp.c (pending_tick): New function. Deliver pending writes. 1900 1901 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED, 1902 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that 1903 it can handle mixed sized quantites and single bits. 1904 1905Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com> 1906 1907 * interp.c (oengine.h): Do not include when building with IGEN. 1908 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE. 1909 (sim_info): Ditto for PROCESSOR_64BIT. 1910 (sim_monitor): Replace ut_reg with unsigned_word. 1911 (*): Ditto for t_reg. 1912 (LOADDRMASK): Define. 1913 (sim_open): Remove defunct check that host FP is IEEE compliant, 1914 using software to emulate floating point. 1915 (value_fpr, ...): Always compile, was conditional on HASFPU. 1916 1917Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com> 1918 1919 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in 1920 size. 1921 1922 * interp.c (SD, CPU): Define. 1923 (mips_option_handler): Set flags in each CPU. 1924 (interrupt_event): Assume CPU 0 is the one being iterrupted. 1925 (sim_close): Do not clear STATE, deleted anyway. 1926 (sim_write, sim_read): Assume CPU zero's vm should be used for 1927 data transfers. 1928 (sim_create_inferior): Set the PC for all processors. 1929 (sim_monitor, store_word, load_word, mips16_entry): Add cpu 1930 argument. 1931 (mips16_entry): Pass correct nr of args to store_word, load_word. 1932 (ColdReset): Cold reset all cpu's. 1933 (signal_exception): Pass cpu to sim_monitor & mips16_entry. 1934 (sim_monitor, load_memory, store_memory, signal_exception): Use 1935 `CPU' instead of STATE_CPU. 1936 1937 1938 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with 1939 SD or CPU_. 1940 1941 * sim-main.h (signal_exception): Add sim_cpu arg. 1942 (SignalException*): Pass both SD and CPU to signal_exception. 1943 * interp.c (signal_exception): Update. 1944 1945 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c: 1946 Ditto 1947 (sync_operation, prefetch, cache_op, store_memory, load_memory, 1948 address_translation): Ditto 1949 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto. 1950 1951Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com> 1952 1953 * configure: Regenerated to track ../common/aclocal.m4 changes. 1954 1955Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com> 1956 1957 * interp.c (sim_engine_run): Add `nr_cpus' argument. 1958 1959 * mips.igen (model): Map processor names onto BFD name. 1960 1961 * sim-main.h (CPU_CIA): Delete. 1962 (SET_CIA, GET_CIA): Define 1963 1964Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com> 1965 1966 * sim-main.h (GPR_SET): Define, used by igen when zeroing a 1967 regiser. 1968 1969 * configure.in (default_endian): Configure a big-endian simulator 1970 by default. 1971 * configure: Re-generate. 1972 1973Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba> 1974 1975 * configure: Regenerated to track ../common/aclocal.m4 changes. 1976 1977Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com> 1978 1979 * interp.c (sim_monitor): Handle Densan monitor outbyte 1980 and inbyte functions. 1981 19821997-12-29 Felix Lee <flee@cygnus.com> 1983 1984 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c). 1985 1986Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com) 1987 1988 * Makefile.in (tmp-igen): Arrange for $zero to always be 1989 reset to zero after every instruction. 1990 1991Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com> 1992 1993 * configure: Regenerated to track ../common/aclocal.m4 changes. 1994 * config.in: Ditto. 1995 1996Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com) 1997 1998 * mips.igen (MSUB): Fix to work like MADD. 1999 * gencode.c (MSUB): Similarly. 2000 2001Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com> 2002 2003 * configure: Regenerated to track ../common/aclocal.m4 changes. 2004 2005Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com> 2006 2007 * mips.igen (LWC1): Correct assembler - lwc1 not swc1. 2008 2009Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com> 2010 2011 * sim-main.h (sim-fpu.h): Include. 2012 2013 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub, 2014 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite 2015 using host independant sim_fpu module. 2016 2017Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com> 2018 2019 * interp.c (signal_exception): Report internal errors with SIGABRT 2020 not SIGQUIT. 2021 2022 * sim-main.h (C0_CONFIG): New register. 2023 (signal.h): No longer include. 2024 2025 * interp.c (decode_coproc): Allow access C0_CONFIG to register. 2026 2027Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com> 2028 2029 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS). 2030 2031Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com> 2032 2033 * mips.igen: Tag vr5000 instructions. 2034 (ANDI): Was missing mipsIV model, fix assembler syntax. 2035 (do_c_cond_fmt): New function. 2036 (C.cond.fmt): Handle mips I-III which do not support CC field 2037 separatly. 2038 (bc1): Handle mips IV which do not have a delaed FCC separatly. 2039 (SDR): Mask paddr when BigEndianMem, not the converse as specified 2040 in IV3.2 spec. 2041 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle 2042 vr5000 which saves LO in a GPR separatly. 2043 2044 * configure.in (enable-sim-igen): For vr5000, select vr5000 2045 specific instructions. 2046 * configure: Re-generate. 2047 2048Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com> 2049 2050 * Makefile.in (SIM_OBJS): Add sim-fpu module. 2051 2052 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and 2053 fmt_uninterpreted_64 bit cases to switch. Convert to 2054 fmt_formatted, 2055 2056 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define, 2057 2058 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse 2059 as specified in IV3.2 spec. 2060 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR. 2061 2062Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com> 2063 2064 * mips.igen: Delay slot branches add OFFSET to NIA not CIA. 2065 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement. 2066 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non 2067 PENDING_FILL versions of instructions. Simplify. 2068 (X): New function. 2069 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of 2070 instructions. 2071 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to 2072 a signed value. 2073 (MTHI, MFHI): Disable code checking HI-LO. 2074 2075 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh 2076 global. 2077 (NULLIFY_NEXT_INSTRUCTION): Call dotrace. 2078 2079Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com> 2080 2081 * gencode.c (build_mips16_operands): Replace IPC with cia. 2082 2083 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr, 2084 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace 2085 IPC to `cia'. 2086 (UndefinedResult): Replace function with macro/function 2087 combination. 2088 (sim_engine_run): Don't save PC in IPC. 2089 2090 * sim-main.h (IPC): Delete. 2091 2092 2093 * interp.c (signal_exception, store_word, load_word, 2094 address_translation, load_memory, store_memory, cache_op, 2095 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert, 2096 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add 2097 current instruction address - cia - argument. 2098 (sim_read, sim_write): Call address_translation directly. 2099 (sim_engine_run): Rename variable vaddr to cia. 2100 (signal_exception): Pass cia to sim_monitor 2101 2102 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp, 2103 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW, 2104 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update. 2105 2106 * sim-main.h (SignalExceptionSimulatorFault): Delete definition. 2107 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with 2108 SIM_ASSERT. 2109 2110 * interp.c (signal_exception): Pass restart address to 2111 sim_engine_restart. 2112 2113 * Makefile.in (semantics.o, engine.o, support.o, itable.o, 2114 idecode.o): Add dependency. 2115 2116 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK): 2117 Delete definitions 2118 (DELAY_SLOT): Update NIA not PC with branch address. 2119 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next. 2120 2121 * mips.igen: Use CIA not PC in branch calculations. 2122 (illegal): Call SignalException. 2123 (BEQ, ADDIU): Fix assembler. 2124 2125Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com> 2126 2127 * m16.igen (JALX): Was missing. 2128 2129 * configure.in (enable-sim-igen): New configuration option. 2130 * configure: Re-generate. 2131 2132 * sim-main.h (MAX_INSNS, INSN_NAME): Define. 2133 2134 * interp.c (load_memory, store_memory): Delete parameter RAW. 2135 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly 2136 bypassing {load,store}_memory. 2137 2138 * sim-main.h (ByteSwapMem): Delete definition. 2139 2140 * Makefile.in (SIM_OBJS): Add sim-memopt module. 2141 2142 * interp.c (sim_do_command, sim_commands): Delete mips specific 2143 commands. Handled by module sim-options. 2144 2145 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module. 2146 (WITH_MODULO_MEMORY): Define. 2147 2148 * interp.c (sim_info): Delete code printing memory size. 2149 2150 * interp.c (mips_size): Nee sim_size, delete function. 2151 (power2): Delete. 2152 (monitor, monitor_base, monitor_size): Delete global variables. 2153 (sim_open, sim_close): Delete code creating monitor and other 2154 memory regions. Use sim-memopts module, via sim_do_commandf, to 2155 manage memory regions. 2156 (load_memory, store_memory): Use sim-core for memory model. 2157 2158 * interp.c (address_translation): Delete all memory map code 2159 except line forcing 32 bit addresses. 2160 2161Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com> 2162 2163 * sim-main.h (WITH_TRACE): Delete definition. Enables common 2164 trace options. 2165 2166 * interp.c (logfh, logfile): Delete globals. 2167 (sim_open, sim_close): Delete code opening & closing log file. 2168 (mips_option_handler): Delete -l and -n options. 2169 (OPTION mips_options): Ditto. 2170 2171 * interp.c (OPTION mips_options): Rename option trace to dinero. 2172 (mips_option_handler): Update. 2173 2174Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com> 2175 2176 * interp.c (fetch_str): New function. 2177 (sim_monitor): Rewrite using sim_read & sim_write. 2178 (sim_open): Check magic number. 2179 (sim_open): Write monitor vectors into memory using sim_write. 2180 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define. 2181 (sim_read, sim_write): Simplify - transfer data one byte at a 2182 time. 2183 (load_memory, store_memory): Clarify meaning of parameter RAW. 2184 2185 * sim-main.h (isHOST): Defete definition. 2186 (isTARGET): Mark as depreciated. 2187 (address_translation): Delete parameter HOST. 2188 2189 * interp.c (address_translation): Delete parameter HOST. 2190 2191Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com> 2192 2193 * mips.igen: 2194 2195 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen. 2196 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE. 2197 2198Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com> 2199 2200 * mips.igen: Add model filter field to records. 2201 2202Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> 2203 2204 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0. 2205 2206 interp.c (sim_engine_run): Do not compile function sim_engine_run 2207 when WITH_IGEN == 1. 2208 2209 * configure.in (sim_igen_flags, sim_m16_flags): Set according to 2210 target architecture. 2211 2212 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to 2213 igen. Replace with configuration variables sim_igen_flags / 2214 sim_m16_flags. 2215 2216 * m16.igen: New file. Copy mips16 insns here. 2217 * mips.igen: From here. 2218 2219Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com> 2220 2221 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ 2222 to top. 2223 (tmp-igen, tmp-m16): Pass -I srcdir to igen. 2224 2225Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com> 2226 2227 * gencode.c (build_instruction): Follow sim_write's lead in using 2228 BigEndianMem instead of !ByteSwapMem. 2229 2230Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com> 2231 2232 * configure.in (sim_gen): Dependent on target, select type of 2233 generator. Always select old style generator. 2234 2235 configure: Re-generate. 2236 2237 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New 2238 targets. 2239 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16, 2240 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN, 2241 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define 2242 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member 2243 SIM_@sim_gen@_*, set by autoconf. 2244 2245Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com> 2246 2247 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define. 2248 2249 * interp.c (ColdReset): Remove #ifdef HASFPU, check 2250 CURRENT_FLOATING_POINT instead. 2251 2252 * interp.c (ifetch32): New function. Fetch 32 bit instruction. 2253 (address_translation): Raise exception InstructionFetch when 2254 translation fails and isINSTRUCTION. 2255 2256 * interp.c (sim_open, sim_write, sim_monitor, store_word, 2257 sim_engine_run): Change type of of vaddr and paddr to 2258 address_word. 2259 (address_translation, prefetch, load_memory, store_memory, 2260 cache_op): Change type of vAddr and pAddr to address_word. 2261 2262 * gencode.c (build_instruction): Change type of vaddr and paddr to 2263 address_word. 2264 2265Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com> 2266 2267 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT 2268 macro to obtain result of ALU op. 2269 2270Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com> 2271 2272 * interp.c (sim_info): Call profile_print. 2273 2274Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> 2275 2276 * Makefile.in (SIM_OBJS): Add sim-profile.o module. 2277 2278 * sim-main.h (WITH_PROFILE): Do not define, defined in 2279 common/sim-config.h. Use sim-profile module. 2280 (simPROFILE): Delete defintion. 2281 2282 * interp.c (PROFILE): Delete definition. 2283 (mips_option_handler): Delete 'p', 'y' and 'x' profile options. 2284 (sim_close): Delete code writing profile histogram. 2285 (mips_set_profile, mips_set_profile_size, writeout16, writeout32): 2286 Delete. 2287 (sim_engine_run): Delete code profiling the PC. 2288 2289Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com> 2290 2291 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word. 2292 2293 * interp.c (sim_monitor): Make register pointers of type 2294 unsigned_word*. 2295 2296 * sim-main.h: Make registers of type unsigned_word not 2297 signed_word. 2298 2299Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> 2300 2301 * interp.c (sync_operation): Rename from SyncOperation, make 2302 global, add SD argument. 2303 (prefetch): Rename from Prefetch, make global, add SD argument. 2304 (decode_coproc): Make global. 2305 2306 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define. 2307 2308 * gencode.c (build_instruction): Generate DecodeCoproc not 2309 decode_coproc calls. 2310 2311 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h 2312 (SizeFGR): Move to sim-main.h 2313 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT, 2314 simSIGINT, simJALDELAYSLOT): Move to sim-main.h 2315 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to 2316 sim-main.h. 2317 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF, 2318 FP_RM_TOMINF, GETRM): Move to sim-main.h. 2319 (Uncached, CachedNoncoherent, CachedCoherent, Cached, 2320 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h. 2321 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian, 2322 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h 2323 2324 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise 2325 exception. 2326 (sim-alu.h): Include. 2327 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define. 2328 (sim_cia): Typedef to instruction_address. 2329 2330Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com> 2331 2332 * Makefile.in (interp.o): Rename generated file engine.c to 2333 oengine.c. 2334 2335 * interp.c: Update. 2336 2337Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com> 2338 2339 * gencode.c (build_instruction): Use FPR_STATE not fpr_state. 2340 2341Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com> 2342 2343 * gencode.c (build_instruction): For "FPSQRT", output correct 2344 number of arguments to Recip. 2345 2346Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com> 2347 2348 * Makefile.in (interp.o): Depends on sim-main.h 2349 2350 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers. 2351 2352 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state, 2353 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields. 2354 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*, 2355 STATE, DSSTATE): Define 2356 (GPR, FGRIDX, ..): Define. 2357 2358 * interp.c (registers, register_widths, fpr_state, ipc, dspc, 2359 pending_*, hiaccess, loaccess, state, dsstate): Delete globals. 2360 (GPR, FGRIDX, ...): Delete macros. 2361 2362 * interp.c: Update names to match defines from sim-main.h 2363 2364Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com> 2365 2366 * interp.c (sim_monitor): Add SD argument. 2367 (sim_warning): Delete. Replace calls with calls to 2368 sim_io_eprintf. 2369 (sim_error): Delete. Replace calls with sim_io_error. 2370 (open_trace, writeout32, writeout16, getnum): Add SD argument. 2371 (mips_set_profile): Rename from sim_set_profile. Add SD argument. 2372 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD 2373 argument. 2374 (mips_size): Rename from sim_size. Add SD argument. 2375 2376 * interp.c (simulator): Delete global variable. 2377 (callback): Delete global variable. 2378 (mips_option_handler, sim_open, sim_write, sim_read, 2379 sim_store_register, sim_fetch_register, sim_info, sim_do_command, 2380 sim_size,sim_monitor): Use sim_io_* not callback->*. 2381 (sim_open): ZALLOC simulator struct. 2382 (PROFILE): Do not define. 2383 2384Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> 2385 2386 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in 2387 support.h with corresponding code. 2388 2389 * sim-main.h (word64, uword64), support.h: Move definition to 2390 sim-main.h. 2391 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto. 2392 2393 * support.h: Delete 2394 * Makefile.in: Update dependencies 2395 * interp.c: Do not include. 2396 2397Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com> 2398 2399 * interp.c (address_translation, load_memory, store_memory, 2400 cache_op): Rename to from AddressTranslation et.al., make global, 2401 add SD argument 2402 2403 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory, 2404 CacheOp): Define. 2405 2406 * interp.c (SignalException): Rename to signal_exception, make 2407 global. 2408 2409 * interp.c (Interrupt, ...): Move definitions to sim-main.h. 2410 2411 * sim-main.h (SignalException, SignalExceptionInterrupt, 2412 SignalExceptionInstructionFetch, SignalExceptionAddressStore, 2413 SignalExceptionAddressLoad, SignalExceptionSimulatorFault, 2414 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable): 2415 Define. 2416 2417 * interp.c, support.h: Use. 2418 2419Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com> 2420 2421 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename 2422 to value_fpr / store_fpr. Add SD argument. 2423 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub, 2424 Multiply, Divide, Recip, SquareRoot, Convert): Make global. 2425 2426 * sim-main.h (ValueFPR, StoreFPR): Define. 2427 2428Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com> 2429 2430 * interp.c (sim_engine_run): Check consistency between configure 2431 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN 2432 and HASFPU. 2433 2434 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE. 2435 (mips_fpu): Configure WITH_FLOATING_POINT. 2436 (mips_endian): Configure WITH_TARGET_ENDIAN. 2437 * configure: Update. 2438 2439Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com> 2440 2441 * configure: Regenerated to track ../common/aclocal.m4 changes. 2442 2443Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com> 2444 2445 * configure: Regenerated. 2446 2447Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com> 2448 2449 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB. 2450 2451Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com> 2452 2453 * gencode.c (print_igen_insn_models): Assume certain architectures 2454 include all mips* instructions. 2455 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16 2456 instruction. 2457 2458 * Makefile.in (tmp.igen): Add target. Generate igen input from 2459 gencode file. 2460 2461 * gencode.c (FEATURE_IGEN): Define. 2462 (main): Add --igen option. Generate output in igen format. 2463 (process_instructions): Format output according to igen option. 2464 (print_igen_insn_format): New function. 2465 (print_igen_insn_models): New function. 2466 (process_instructions): Only issue warnings and ignore 2467 instructions when no FEATURE_IGEN. 2468 2469Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com> 2470 2471 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some 2472 MIPS targets. 2473 2474Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com> 2475 2476 * configure: Regenerated to track ../common/aclocal.m4 changes. 2477 2478Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com> 2479 2480 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN, 2481 SIM_RESERVED_BITS): Delete, moved to common. 2482 (SIM_EXTRA_CFLAGS): Update. 2483 2484Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com> 2485 2486 * configure.in: Configure non-strict memory alignment. 2487 * configure: Regenerated to track ../common/aclocal.m4 changes. 2488 2489Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com> 2490 2491 * configure: Regenerated to track ../common/aclocal.m4 changes. 2492 2493Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com> 2494 2495 * gencode.c (SDBBP,DERET): Added (3900) insns. 2496 (RFE): Turn on for 3900. 2497 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added. 2498 (dsstate): Made global. 2499 (SUBTARGET_R3900): Added. 2500 (CANCELDELAYSLOT): New. 2501 (SignalException): Ignore SystemCall rather than ignore and 2502 terminate. Add DebugBreakPoint handling. 2503 (decode_coproc): New insns RFE, DERET; and new registers Debug 2504 and DEPC protected by SUBTARGET_R3900. 2505 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing 2506 bits explicitly. 2507 * Makefile.in,configure.in: Add mips subtarget option. 2508 * configure: Update. 2509 2510Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com> 2511 2512 * gencode.c: Add r3900 (tx39). 2513 2514 2515Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com> 2516 2517 * gencode.c (build_instruction): Don't need to subtract 4 for 2518 JALR, just 2. 2519 2520Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com> 2521 2522 * interp.c: Correct some HASFPU problems. 2523 2524Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com> 2525 2526 * configure: Regenerated to track ../common/aclocal.m4 changes. 2527 2528Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com> 2529 2530 * interp.c (mips_options): Fix samples option short form, should 2531 be `x'. 2532 2533Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com> 2534 2535 * interp.c (sim_info): Enable info code. Was just returning. 2536 2537Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com> 2538 2539 * interp.c (decode_coproc): Clarify warning about unsuported MTC0, 2540 MFC0. 2541 2542Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com> 2543 2544 * gencode.c (build_instruction): Use SIGNED64 for 64 bit 2545 constants. 2546 (build_instruction): Ditto for LL. 2547 2548Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba> 2549 2550 * configure: Regenerated to track ../common/aclocal.m4 changes. 2551 2552Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com> 2553 2554 * configure: Regenerated to track ../common/aclocal.m4 changes. 2555 * config.in: Ditto. 2556 2557Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com> 2558 2559 * interp.c (sim_open): Add call to sim_analyze_program, update 2560 call to sim_config. 2561 2562Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com> 2563 2564 * interp.c (sim_kill): Delete. 2565 (sim_create_inferior): Add ABFD argument. Set PC from same. 2566 (sim_load): Move code initializing trap handlers from here. 2567 (sim_open): To here. 2568 (sim_load): Delete, use sim-hload.c. 2569 2570 * Makefile.in (SIM_OBJS): Add sim-hload.o module. 2571 2572Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com> 2573 2574 * configure: Regenerated to track ../common/aclocal.m4 changes. 2575 * config.in: Ditto. 2576 2577Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com> 2578 2579 * interp.c (sim_open): Add ABFD argument. 2580 (sim_load): Move call to sim_config from here. 2581 (sim_open): To here. Check return status. 2582 2583Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com> 2584 2585 * gencode.c (build_instruction): Two arg MADD should 2586 not assign result to $0. 2587 2588Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com) 2589 2590 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian) 2591 * sim/mips/configure.in: Regenerate. 2592 2593Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com> 2594 2595 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit 2596 signed8, unsigned8 et.al. types. 2597 2598 * interp.c (SUB_REG_FETCH): Handle both little and big endian 2599 hosts when selecting subreg. 2600 2601Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com) 2602 2603 * interp.c (sim_engine_run): Reset the ZERO register to zero 2604 regardless of FEATURE_WARN_ZERO. 2605 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO. 2606 2607Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com> 2608 2609 * interp.c (decode_coproc): Implement MTC0 N, CAUSE. 2610 (SignalException): For BreakPoints ignore any mode bits and just 2611 save the PC. 2612 (SignalException): Always set the CAUSE register. 2613 2614Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com> 2615 2616 * interp.c (SignalException): Clear the simDELAYSLOT flag when an 2617 exception has been taken. 2618 2619 * interp.c: Implement the ERET and mt/f sr instructions. 2620 2621Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com> 2622 2623 * interp.c (SignalException): Don't bother restarting an 2624 interrupt. 2625 2626Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com> 2627 2628 * interp.c (SignalException): Really take an interrupt. 2629 (interrupt_event): Only deliver interrupts when enabled. 2630 2631Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com> 2632 2633 * interp.c (sim_info): Only print info when verbose. 2634 (sim_info) Use sim_io_printf for output. 2635 2636Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> 2637 2638 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all 2639 mips architectures. 2640 2641Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com> 2642 2643 * interp.c (sim_do_command): Check for common commands if a 2644 simulator specific command fails. 2645 2646Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com> 2647 2648 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP 2649 and simBE when DEBUG is defined. 2650 2651Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com> 2652 2653 * interp.c (interrupt_event): New function. Pass exception event 2654 onto exception handler. 2655 2656 * configure.in: Check for stdlib.h. 2657 * configure: Regenerate. 2658 2659 * gencode.c (build_instruction): Add UNUSED attribute to tempS 2660 variable declaration. 2661 (build_instruction): Initialize memval1. 2662 (build_instruction): Add UNUSED attribute to byte, bigend, 2663 reverse. 2664 (build_operands): Ditto. 2665 2666 * interp.c: Fix GCC warnings. 2667 (sim_get_quit_code): Delete. 2668 2669 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS. 2670 * Makefile.in: Ditto. 2671 * configure: Re-generate. 2672 2673 * Makefile.in (SIM_OBJS): Add sim-watch.o module. 2674 2675Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com> 2676 2677 * interp.c (mips_option_handler): New function parse argumes using 2678 sim-options. 2679 (myname): Replace with STATE_MY_NAME. 2680 (sim_open): Delete check for host endianness - performed by 2681 sim_config. 2682 (simHOSTBE, simBE): Delete, replaced by sim-endian flags. 2683 (sim_open): Move much of the initialization from here. 2684 (sim_load): To here. After the image has been loaded and 2685 endianness set. 2686 (sim_open): Move ColdReset from here. 2687 (sim_create_inferior): To here. 2688 (sim_open): Make FP check less dependant on host endianness. 2689 2690 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or 2691 run. 2692 * interp.c (sim_set_callbacks): Delete. 2693 2694 * interp.c (membank, membank_base, membank_size): Replace with 2695 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE. 2696 (sim_open): Remove call to callback->init. gdb/run do this. 2697 2698 * interp.c: Update 2699 2700 * sim-main.h (SIM_HAVE_FLATMEM): Define. 2701 2702 * interp.c (big_endian_p): Delete, replaced by 2703 current_target_byte_order. 2704 2705Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com> 2706 2707 * interp.c (host_read_long, host_read_word, host_swap_word, 2708 host_swap_long): Delete. Using common sim-endian. 2709 (sim_fetch_register, sim_store_register): Use H2T. 2710 (pipeline_ticks): Delete. Handled by sim-events. 2711 (sim_info): Update. 2712 (sim_engine_run): Update. 2713 2714Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com> 2715 2716 * interp.c (sim_stop_reason): Move code determining simEXCEPTION 2717 reason from here. 2718 (SignalException): To here. Signal using sim_engine_halt. 2719 (sim_stop_reason): Delete, moved to common. 2720 2721Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com> 2722 2723 * interp.c (sim_open): Add callback argument. 2724 (sim_set_callbacks): Delete SIM_DESC argument. 2725 (sim_size): Ditto. 2726 2727Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com> 2728 2729 * Makefile.in (SIM_OBJS): Add common modules. 2730 2731 * interp.c (sim_set_callbacks): Also set SD callback. 2732 (set_endianness, xfer_*, swap_*): Delete. 2733 (host_read_word, host_read_long, host_swap_word, host_swap_long): 2734 Change to functions using sim-endian macros. 2735 (control_c, sim_stop): Delete, use common version. 2736 (simulate): Convert into. 2737 (sim_engine_run): This function. 2738 (sim_resume): Delete. 2739 2740 * interp.c (simulation): New variable - the simulator object. 2741 (sim_kind): Delete global - merged into simulation. 2742 (sim_load): Cleanup. Move PC assignment from here. 2743 (sim_create_inferior): To here. 2744 2745 * sim-main.h: New file. 2746 * interp.c (sim-main.h): Include. 2747 2748Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com> 2749 2750 * configure: Regenerated to track ../common/aclocal.m4 changes. 2751 2752Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com> 2753 2754 * tconfig.in (SIM_HAVE_BIENDIAN): Define. 2755 2756Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com> 2757 2758 * gencode.c (build_instruction): DIV instructions: check 2759 for division by zero and integer overflow before using 2760 host's division operation. 2761 2762Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com> 2763 2764 * Makefile.in (SIM_OBJS): Add sim-load.o. 2765 * interp.c: #include bfd.h. 2766 (target_byte_order): Delete. 2767 (sim_kind, myname, big_endian_p): New static locals. 2768 (sim_open): Set sim_kind, myname. Move call to set_endianness to 2769 after argument parsing. Recognize -E arg, set endianness accordingly. 2770 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to 2771 load file into simulator. Set PC from bfd. 2772 (sim_create_inferior): Return SIM_RC. Delete arg start_address. 2773 (set_endianness): Use big_endian_p instead of target_byte_order. 2774 2775Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com> 2776 2777 * interp.c (sim_size): Delete prototype - conflicts with 2778 definition in remote-sim.h. Correct definition. 2779 2780Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com> 2781 2782 * configure: Regenerated to track ../common/aclocal.m4 changes. 2783 * config.in: Ditto. 2784 2785Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com> 2786 2787 * interp.c (sim_open): New arg `kind'. 2788 2789 * configure: Regenerated to track ../common/aclocal.m4 changes. 2790 2791Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com> 2792 2793 * configure: Regenerated to track ../common/aclocal.m4 changes. 2794 2795Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com> 2796 2797 * interp.c (sim_open): Set optind to 0 before calling getopt. 2798 2799Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com> 2800 2801 * configure: Regenerated to track ../common/aclocal.m4 changes. 2802 2803Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com> 2804 2805 * interp.c : Replace uses of pr_addr with pr_uword64 2806 where the bit length is always 64 independent of SIM_ADDR. 2807 (pr_uword64) : added. 2808 2809Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com> 2810 2811 * configure: Re-generate. 2812 2813Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com> 2814 2815 * configure: Regenerate to track ../common/aclocal.m4 changes. 2816 2817Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com> 2818 2819 * interp.c (sim_open): New SIM_DESC result. Argument is now 2820 in argv form. 2821 (other sim_*): New SIM_DESC argument. 2822 2823Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com> 2824 2825 * interp.c: Fix printing of addresses for non-64-bit targets. 2826 (pr_addr): Add function to print address based on size. 2827 2828Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com> 2829 2830 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors. 2831 2832Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com> 2833 2834 * gencode.c (build_mips16_operands): Correct computation of base 2835 address for extended PC relative instruction. 2836 2837Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com> 2838 2839 * interp.c (mips16_entry): Add support for floating point cases. 2840 (SignalException): Pass floating point cases to mips16_entry. 2841 (ValueFPR): Don't restrict fmt_single and fmt_word to even 2842 registers. 2843 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single 2844 or fmt_word. 2845 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR, 2846 and then set the state to fmt_uninterpreted. 2847 (COP_SW): Temporarily set the state to fmt_word while calling 2848 ValueFPR. 2849 2850Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com> 2851 2852 * gencode.c (build_instruction): The high order may be set in the 2853 comparison flags at any ISA level, not just ISA 4. 2854 2855Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com> 2856 2857 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use 2858 COMMON_{PRE,POST}_CONFIG_FRAG instead. 2859 * configure.in: sinclude ../common/aclocal.m4. 2860 * configure: Regenerated. 2861 2862Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com> 2863 2864 * configure: Rebuild after change to aclocal.m4. 2865 2866Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com) 2867 2868 * configure configure.in Makefile.in: Update to new configure 2869 scheme which is more compatible with WinGDB builds. 2870 * configure.in: Improve comment on how to run autoconf. 2871 * configure: Re-run autoconf to get new ../common/aclocal.m4. 2872 * Makefile.in: Use autoconf substitution to install common 2873 makefile fragment. 2874 2875Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com> 2876 2877 * gencode.c (build_instruction): Use BigEndianCPU instead of 2878 ByteSwapMem. 2879 2880Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com> 2881 2882 * interp.c (sim_monitor): Make output to stdout visible in 2883 wingdb's I/O log window. 2884 2885Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com> 2886 2887 * support.h: Undo previous change to SIGTRAP 2888 and SIGQUIT values. 2889 2890Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com> 2891 2892 * interp.c (store_word, load_word): New static functions. 2893 (mips16_entry): New static function. 2894 (SignalException): Look for mips16 entry and exit instructions. 2895 (simulate): Use the correct index when setting fpr_state after 2896 doing a pending move. 2897 2898Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com> 2899 2900 * interp.c: Fix byte-swapping code throughout to work on 2901 both little- and big-endian hosts. 2902 2903Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com> 2904 2905 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent 2906 with gdb/config/i386/xm-windows.h. 2907 2908Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com> 2909 2910 * gencode.c (build_instruction): Work around MSVC++ code gen bug 2911 that messes up arithmetic shifts. 2912 2913Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com) 2914 2915 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for 2916 SIGTRAP and SIGQUIT for _WIN32. 2917 2918Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com> 2919 2920 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to 2921 force a 64 bit multiplication. 2922 (build_instruction) [OR]: In mips16 mode, don't do anything if the 2923 destination register is 0, since that is the default mips16 nop 2924 instruction. 2925 2926Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com> 2927 2928 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI. 2929 (build_endian_shift): Don't check proc64. 2930 (build_instruction): Always set memval to uword64. Cast op2 to 2931 uword64 when shifting it left in memory instructions. Always use 2932 the same code for stores--don't special case proc64. 2933 2934 * gencode.c (build_mips16_operands): Fix base PC value for PC 2935 relative operands. 2936 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a 2937 jal instruction. 2938 * interp.c (simJALDELAYSLOT): Define. 2939 (JALDELAYSLOT): Define. 2940 (INDELAYSLOT, INJALDELAYSLOT): Define. 2941 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared. 2942 2943Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com) 2944 2945 * interp.c (sim_open): add flush_cache as a PMON routine 2946 (sim_monitor): handle flush_cache by ignoring it 2947 2948Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com> 2949 2950 * gencode.c (build_instruction): Use !ByteSwapMem instead of 2951 BigEndianMem. 2952 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete. 2953 (BigEndianMem): Rename to ByteSwapMem and change sense. 2954 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change 2955 BigEndianMem references to !ByteSwapMem. 2956 (set_endianness): New function, with prototype. 2957 (sim_open): Call set_endianness. 2958 (sim_info): Use simBE instead of BigEndianMem. 2959 (xfer_direct_word, xfer_direct_long, swap_direct_word, 2960 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word, 2961 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER 2962 ifdefs, keeping the prototype declaration. 2963 (swap_word): Rewrite correctly. 2964 (ColdReset): Delete references to CONFIG. Delete endianness related 2965 code; moved to set_endianness. 2966 2967Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com> 2968 2969 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits. 2970 * interp.c (CHECKHILO): Define away. 2971 (simSIGINT): New macro. 2972 (membank_size): Increase from 1MB to 2MB. 2973 (control_c): New function. 2974 (sim_resume): Rename parameter signal to signal_number. Add local 2975 variable prev. Call signal before and after simulate. 2976 (sim_stop_reason): Add simSIGINT support. 2977 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg 2978 functions always. 2979 (sim_warning): Delete call to SignalException. Do call printf_filtered 2980 if logfh is NULL. 2981 (AddressTranslation): Add #ifdef DEBUG around debugging message and 2982 a call to sim_warning. 2983 2984Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com> 2985 2986 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD 2987 16 bit instructions. 2988 2989Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com> 2990 2991 Add support for mips16 (16 bit MIPS implementation): 2992 * gencode.c (inst_type): Add mips16 instruction encoding types. 2993 (GETDATASIZEINSN): Define. 2994 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add 2995 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and 2996 mtlo. 2997 (MIPS16_DECODE): New table, for mips16 instructions. 2998 (bitmap_val): New static function. 2999 (struct mips16_op): Define. 3000 (mips16_op_table): New table, for mips16 operands. 3001 (build_mips16_operands): New static function. 3002 (process_instructions): If PC is odd, decode a mips16 3003 instruction. Break out instruction handling into new 3004 build_instruction function. 3005 (build_instruction): New static function, broken out of 3006 process_instructions. Check modifiers rather than flags for SHIFT 3007 bit count and m[ft]{hi,lo} direction. 3008 (usage): Pass program name to fprintf. 3009 (main): Remove unused variable this_option_optind. Change 3010 ``*loptarg++'' to ``loptarg++''. 3011 (my_strtoul): Parenthesize && within ||. 3012 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd. 3013 (simulate): If PC is odd, fetch a 16 bit instruction, and 3014 increment PC by 2 rather than 4. 3015 * configure.in: Add case for mips16*-*-*. 3016 * configure: Rebuild. 3017 3018Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com> 3019 3020 * interp.c: Allow -t to enable tracing in standalone simulator. 3021 Fix garbage output in trace file and error messages. 3022 3023Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com> 3024 3025 * Makefile.in: Delete stuff moved to ../common/Make-common.in. 3026 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define. 3027 * configure.in: Simplify using macros in ../common/aclocal.m4. 3028 * configure: Regenerated. 3029 * tconfig.in: New file. 3030 3031Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com> 3032 3033 * interp.c: Fix bugs in 64-bit port. 3034 Use ansi function declarations for msvc compiler. 3035 Initialize and test file pointer in trace code. 3036 Prevent duplicate definition of LAST_EMED_REGNUM. 3037 3038Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com> 3039 3040 * interp.c (xfer_big_long): Prevent unwanted sign extension. 3041 3042Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk> 3043 3044 * interp.c (SignalException): Check for explicit terminating 3045 breakpoint value. 3046 * gencode.c: Pass instruction value through SignalException() 3047 calls for Trap, Breakpoint and Syscall. 3048 3049Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk> 3050 3051 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is 3052 only used on those hosts that provide it. 3053 * configure.in: Add sqrt() to list of functions to be checked for. 3054 * config.in: Re-generated. 3055 * configure: Re-generated. 3056 3057Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com> 3058 3059 * gencode.c (process_instructions): Call build_endian_shift when 3060 expanding STORE RIGHT, to fix swr. 3061 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly 3062 clear the high bits. 3063 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate. 3064 Fix float to int conversions to produce signed values. 3065 3066Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com> 3067 3068 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction. 3069 (process_instructions): Correct handling of nor instruction. 3070 Correct shift count for 32 bit shift instructions. Correct sign 3071 extension for arithmetic shifts to not shift the number of bits in 3072 the type. Fix 64 bit multiply high word calculation. Fix 32 bit 3073 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1. 3074 Fix madd. 3075 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC. 3076 It's OK to have a mult follow a mult. What's not OK is to have a 3077 mult follow an mfhi. 3078 (Convert): Comment out incorrect rounding code. 3079 3080Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk> 3081 3082 * interp.c (sim_monitor): Improved monitor printf 3083 simulation. Tidied up simulator warnings, and added "--log" option 3084 for directing warning message output. 3085 * gencode.c: Use sim_warning() rather than WARNING macro. 3086 3087Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com> 3088 3089 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and 3090 getopt1.o, rather than on gencode.c. Link objects together. 3091 Don't link against -liberty. 3092 (gencode.o, getopt.o, getopt1.o): New targets. 3093 * gencode.c: Include <ctype.h> and "ansidecl.h". 3094 (AND): Undefine after including "ansidecl.h". 3095 (ULONG_MAX): Define if not defined. 3096 (OP_*): Don't define macros; now defined in opcode/mips.h. 3097 (main): Call my_strtoul rather than strtoul. 3098 (my_strtoul): New static function. 3099 3100Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com) 3101 3102 * gencode.c (process_instructions): Generate word64 and uword64 3103 instead of `long long' and `unsigned long long' data types. 3104 * interp.c: #include sysdep.h to get signals, and define default 3105 for SIGBUS. 3106 * (Convert): Work around for Visual-C++ compiler bug with type 3107 conversion. 3108 * support.h: Make things compile under Visual-C++ by using 3109 __int64 instead of `long long'. Change many refs to long long 3110 into word64/uword64 typedefs. 3111 3112Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp) 3113 3114 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir, 3115 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values. 3116 (docdir): Removed. 3117 * configure.in (AC_PREREQ): autoconf 2.5 or higher. 3118 (AC_PROG_INSTALL): Added. 3119 (AC_PROG_CC): Moved to before configure.host call. 3120 * configure: Rebuilt. 3121 3122Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk> 3123 3124 * configure.in: Define @SIMCONF@ depending on mips target. 3125 * configure: Rebuild. 3126 * Makefile.in (run): Add @SIMCONF@ to control simulator 3127 construction. 3128 * gencode.c: Change LOADDRMASK to 64bit memory model only. 3129 * interp.c: Remove some debugging, provide more detailed error 3130 messages, update memory accesses to use LOADDRMASK. 3131 3132Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com> 3133 3134 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS, 3135 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set 3136 stamp-h. 3137 * configure: Rebuild. 3138 * config.in: New file, generated by autoheader. 3139 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>, 3140 and <strings.h> if they exist. Replace #ifdef sun with #ifdef 3141 HAVE_ANINT and HAVE_AINT, as appropriate. 3142 * Makefile.in (run): Use @LIBS@ rather than -lm. 3143 (interp.o): Depend upon config.h. 3144 (Makefile): Just rebuild Makefile. 3145 (clean): Remove stamp-h. 3146 (mostlyclean): Make the same as clean, not as distclean. 3147 (config.h, stamp-h): New targets. 3148 3149Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk> 3150 3151 * interp.c (ColdReset): Fix boolean test. Make all simulator 3152 globals static. 3153 3154Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk> 3155 3156 * interp.c (xfer_direct_word, xfer_direct_long, 3157 swap_direct_word, swap_direct_long, xfer_big_word, 3158 xfer_big_long, xfer_little_word, xfer_little_long, 3159 swap_word,swap_long): Added. 3160 * interp.c (ColdReset): Provide function indirection to 3161 host<->simulated_target transfer routines. 3162 * interp.c (sim_store_register, sim_fetch_register): Updated to 3163 make use of indirected transfer routines. 3164 3165Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk> 3166 3167 * gencode.c (process_instructions): Ensure FP ABS instruction 3168 recognised. 3169 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON 3170 system call support. 3171 3172Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk> 3173 3174 * interp.c (sim_do_command): Complain if callback structure not 3175 initialised. 3176 3177Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk> 3178 3179 * interp.c (Convert): Provide round-to-nearest and round-to-zero 3180 support for Sun hosts. 3181 * Makefile.in (gencode): Ensure the host compiler and libraries 3182 used for cross-hosted build. 3183 3184Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk> 3185 3186 * interp.c, gencode.c: Some more (TODO) tidying. 3187 3188Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk> 3189 3190 * gencode.c, interp.c: Replaced explicit long long references with 3191 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls. 3192 * support.h (SET64LO, SET64HI): Macros added. 3193 3194Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com> 3195 3196 * configure: Regenerate with autoconf 2.7. 3197 3198Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com> 3199 3200 * interp.c (LoadMemory): Enclose text following #endif in /* */. 3201 * support.h: Remove superfluous "1" from #if. 3202 * support.h (CHECKSIM): Remove stray 'a' at end of line. 3203 3204Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com> 3205 3206 * interp.c (StoreFPR): Control UndefinedResult() call on 3207 WARN_RESULT manifest. 3208 3209Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk> 3210 3211 * gencode.c: Tidied instruction decoding, and added FP instruction 3212 support. 3213 3214 * interp.c: Added dineroIII, and BSD profiling support. Also 3215 run-time FP handling. 3216 3217Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk> 3218 3219 * Changelog, Makefile.in, README.Cygnus, configure, configure.in, 3220 gencode.c, interp.c, support.h: created. 3221