1/* frv simulator support code
2   Copyright (C) 1998, 2000, 2001, 2007 Free Software Foundation, Inc.
3   Contributed by Red Hat.
4
5This file is part of the GNU simulators.
6
7This program is free software; you can redistribute it and/or modify
8it under the terms of the GNU General Public License as published by
9the Free Software Foundation; either version 3 of the License, or
10(at your option) any later version.
11
12This program is distributed in the hope that it will be useful,
13but WITHOUT ANY WARRANTY; without even the implied warranty of
14MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15GNU General Public License for more details.
16
17You should have received a copy of the GNU General Public License
18along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
19
20/* Main header for the frv.  */
21
22#define USING_SIM_BASE_H /* FIXME: quick hack */
23
24struct _sim_cpu; /* FIXME: should be in sim-basics.h */
25typedef struct _sim_cpu SIM_CPU;
26
27/* Set the mask of unsupported traces.  */
28#define WITH_TRACE \
29  (~(TRACE_alu | TRACE_decode | TRACE_memory | TRACE_model | TRACE_fpu \
30     | TRACE_branch | TRACE_debug))
31
32/* sim-basics.h includes config.h but cgen-types.h must be included before
33   sim-basics.h and cgen-types.h needs config.h.  */
34#include "config.h"
35
36#include "symcat.h"
37#include "sim-basics.h"
38#include "cgen-types.h"
39#include "frv-desc.h"
40#include "frv-opc.h"
41#include "arch.h"
42
43/* These must be defined before sim-base.h.  */
44typedef USI sim_cia;
45
46#define CIA_GET(cpu)     CPU_PC_GET (cpu)
47#define CIA_SET(cpu,val) CPU_PC_SET ((cpu), (val))
48
49void frv_sim_engine_halt_hook (SIM_DESC, SIM_CPU *, sim_cia);
50#define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) \
51  frv_sim_engine_halt_hook ((SD), (LAST_CPU), (CIA))
52
53#define SIM_ENGINE_RESTART_HOOK(SD, LAST_CPU, CIA) 0
54
55#include "sim-base.h"
56#include "cgen-sim.h"
57#include "frv-sim.h"
58#include "cache.h"
59#include "registers.h"
60#include "profile.h"
61
62/* The _sim_cpu struct.  */
63
64struct _sim_cpu {
65  /* sim/common cpu base.  */
66  sim_cpu_base base;
67
68  /* Static parts of cgen.  */
69  CGEN_CPU cgen_cpu;
70
71  /* CPU specific parts go here.
72     Note that in files that don't need to access these pieces WANT_CPU_FOO
73     won't be defined and thus these parts won't appear.  This is ok in the
74     sense that things work.  It is a source of bugs though.
75     One has to of course be careful to not take the size of this
76     struct and no structure members accessed in non-cpu specific files can
77     go after here.  Oh for a better language.  */
78#if defined (WANT_CPU_FRVBF)
79  FRVBF_CPU_DATA cpu_data;
80
81  /* Control information for registers */
82  FRV_REGISTER_CONTROL register_control;
83#define CPU_REGISTER_CONTROL(cpu) (& (cpu)->register_control)
84
85  FRV_VLIW vliw;
86#define CPU_VLIW(cpu) (& (cpu)->vliw)
87
88  FRV_CACHE insn_cache;
89#define CPU_INSN_CACHE(cpu) (& (cpu)->insn_cache)
90
91  FRV_CACHE data_cache;
92#define CPU_DATA_CACHE(cpu) (& (cpu)->data_cache)
93
94  FRV_PROFILE_STATE profile_state;
95#define CPU_PROFILE_STATE(cpu) (& (cpu)->profile_state)
96
97  int debug_state;
98#define CPU_DEBUG_STATE(cpu) ((cpu)->debug_state)
99
100  SI load_address;
101#define CPU_LOAD_ADDRESS(cpu) ((cpu)->load_address)
102
103  SI load_length;
104#define CPU_LOAD_LENGTH(cpu) ((cpu)->load_length)
105
106  SI load_flag;
107#define CPU_LOAD_SIGNED(cpu) ((cpu)->load_flag)
108#define CPU_LOAD_LOCK(cpu) ((cpu)->load_flag)
109
110  SI store_flag;
111#define CPU_RSTR_INVALIDATE(cpu) ((cpu)->store_flag)
112
113  unsigned long elf_flags;
114#define CPU_ELF_FLAGS(cpu) ((cpu)->elf_flags)
115#endif /* defined (WANT_CPU_FRVBF) */
116};
117
118/* The sim_state struct.  */
119
120struct sim_state {
121  sim_cpu *cpu;
122#define STATE_CPU(sd, n) (/*&*/ (sd)->cpu)
123
124  CGEN_STATE cgen_state;
125
126  sim_state_base base;
127};
128
129/* Misc.  */
130
131/* Catch address exceptions.  */
132extern SIM_CORE_SIGNAL_FN frv_core_signal;
133#define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
134frv_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), \
135		  (TRANSFER), (ERROR))
136
137/* Default memory size.  */
138#define FRV_DEFAULT_MEM_SIZE 0x800000 /* 8M */
139