1/* arminit.c -- ARMulator initialization: ARM6 Instruction Emulator. 2 Copyright (C) 1994 Advanced RISC Machines Ltd. 3 4 This program is free software; you can redistribute it and/or modify 5 it under the terms of the GNU General Public License as published by 6 the Free Software Foundation; either version 2 of the License, or 7 (at your option) any later version. 8 9 This program is distributed in the hope that it will be useful, 10 but WITHOUT ANY WARRANTY; without even the implied warranty of 11 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 GNU General Public License for more details. 13 14 You should have received a copy of the GNU General Public License 15 along with this program; if not, write to the Free Software 16 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 17 18#include "armdefs.h" 19#include "armemu.h" 20#include "dbg_rdi.h" 21 22/***************************************************************************\ 23* Definitions for the emulator architecture * 24\***************************************************************************/ 25 26void ARMul_EmulateInit (void); 27ARMul_State *ARMul_NewState (void); 28void ARMul_Reset (ARMul_State * state); 29ARMword ARMul_DoCycle (ARMul_State * state); 30unsigned ARMul_DoCoPro (ARMul_State * state); 31ARMword ARMul_DoProg (ARMul_State * state); 32ARMword ARMul_DoInstr (ARMul_State * state); 33void ARMul_Abort (ARMul_State * state, ARMword address); 34 35unsigned ARMul_MultTable[32] = 36 { 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 37 10, 10, 11, 11, 12, 12, 13, 13, 14, 14, 15, 15, 16, 16, 16 38}; 39ARMword ARMul_ImmedTable[4096]; /* immediate DP LHS values */ 40char ARMul_BitList[256]; /* number of bits in a byte table */ 41 42/***************************************************************************\ 43* Call this routine once to set up the emulator's tables. * 44\***************************************************************************/ 45 46void 47ARMul_EmulateInit (void) 48{ 49 unsigned long i, j; 50 51 for (i = 0; i < 4096; i++) 52 { /* the values of 12 bit dp rhs's */ 53 ARMul_ImmedTable[i] = ROTATER (i & 0xffL, (i >> 7L) & 0x1eL); 54 } 55 56 for (i = 0; i < 256; ARMul_BitList[i++] = 0); /* how many bits in LSM */ 57 for (j = 1; j < 256; j <<= 1) 58 for (i = 0; i < 256; i++) 59 if ((i & j) > 0) 60 ARMul_BitList[i]++; 61 62 for (i = 0; i < 256; i++) 63 ARMul_BitList[i] *= 4; /* you always need 4 times these values */ 64 65} 66 67/***************************************************************************\ 68* Returns a new instantiation of the ARMulator's state * 69\***************************************************************************/ 70 71ARMul_State * 72ARMul_NewState (void) 73{ 74 ARMul_State *state; 75 unsigned i, j; 76 77 state = (ARMul_State *) malloc (sizeof (ARMul_State)); 78 memset (state, 0, sizeof (ARMul_State)); 79 80 state->Emulate = RUN; 81 for (i = 0; i < 16; i++) 82 { 83 state->Reg[i] = 0; 84 for (j = 0; j < 7; j++) 85 state->RegBank[j][i] = 0; 86 } 87 for (i = 0; i < 7; i++) 88 state->Spsr[i] = 0; 89 90 /* state->Mode = USER26MODE; */ 91 state->Mode = USER32MODE; 92 93 state->CallDebug = FALSE; 94 state->Debug = FALSE; 95 state->VectorCatch = 0; 96 state->Aborted = FALSE; 97 state->Reseted = FALSE; 98 state->Inted = 3; 99 state->LastInted = 3; 100 101 state->MemDataPtr = NULL; 102 state->MemInPtr = NULL; 103 state->MemOutPtr = NULL; 104 state->MemSparePtr = NULL; 105 state->MemSize = 0; 106 107 state->OSptr = NULL; 108 state->CommandLine = NULL; 109 110 state->CP14R0_CCD = -1; 111 state->LastTime = 0; 112 113 state->EventSet = 0; 114 state->Now = 0; 115 state->EventPtr = (struct EventNode **) malloc ((unsigned) EVENTLISTSIZE * 116 sizeof (struct EventNode 117 *)); 118 for (i = 0; i < EVENTLISTSIZE; i++) 119 *(state->EventPtr + i) = NULL; 120 121 state->prog32Sig = HIGH; 122 state->data32Sig = HIGH; 123 124 state->lateabtSig = LOW; 125 state->bigendSig = LOW; 126 127 state->is_v4 = LOW; 128 state->is_v5 = LOW; 129 state->is_v5e = LOW; 130 state->is_XScale = LOW; 131 state->is_iWMMXt = LOW; 132 state->is_v6 = LOW; 133 134 ARMul_Reset (state); 135 136 return state; 137} 138 139/***************************************************************************\ 140 Call this routine to set ARMulator to model certain processor properities 141\***************************************************************************/ 142 143void 144ARMul_SelectProcessor (ARMul_State * state, unsigned properties) 145{ 146 if (properties & ARM_Fix26_Prop) 147 { 148 state->prog32Sig = LOW; 149 state->data32Sig = LOW; 150 } 151 else 152 { 153 state->prog32Sig = HIGH; 154 state->data32Sig = HIGH; 155 } 156 157 state->lateabtSig = LOW; 158 159 state->is_v4 = (properties & (ARM_v4_Prop | ARM_v5_Prop)) ? HIGH : LOW; 160 state->is_v5 = (properties & ARM_v5_Prop) ? HIGH : LOW; 161 state->is_v5e = (properties & ARM_v5e_Prop) ? HIGH : LOW; 162 state->is_XScale = (properties & ARM_XScale_Prop) ? HIGH : LOW; 163 state->is_iWMMXt = (properties & ARM_iWMMXt_Prop) ? HIGH : LOW; 164 state->is_ep9312 = (properties & ARM_ep9312_Prop) ? HIGH : LOW; 165 state->is_v6 = (properties & ARM_v6_Prop) ? HIGH : LOW; 166 167 /* Only initialse the coprocessor support once we 168 know what kind of chip we are dealing with. */ 169 ARMul_CoProInit (state); 170} 171 172/***************************************************************************\ 173* Call this routine to set up the initial machine state (or perform a RESET * 174\***************************************************************************/ 175 176void 177ARMul_Reset (ARMul_State * state) 178{ 179 state->NextInstr = 0; 180 181 if (state->prog32Sig) 182 { 183 state->Reg[15] = 0; 184 state->Cpsr = INTBITS | SVC32MODE; 185 state->Mode = SVC32MODE; 186 } 187 else 188 { 189 state->Reg[15] = R15INTBITS | SVC26MODE; 190 state->Cpsr = INTBITS | SVC26MODE; 191 state->Mode = SVC26MODE; 192 } 193 194 ARMul_CPSRAltered (state); 195 state->Bank = SVCBANK; 196 197 FLUSHPIPE; 198 199 state->EndCondition = 0; 200 state->ErrorCode = 0; 201 202 state->Exception = FALSE; 203 state->NresetSig = HIGH; 204 state->NfiqSig = HIGH; 205 state->NirqSig = HIGH; 206 state->NtransSig = (state->Mode & 3) ? HIGH : LOW; 207 state->abortSig = LOW; 208 state->AbortAddr = 1; 209 210 state->NumInstrs = 0; 211 state->NumNcycles = 0; 212 state->NumScycles = 0; 213 state->NumIcycles = 0; 214 state->NumCcycles = 0; 215 state->NumFcycles = 0; 216#ifdef ASIM 217 (void) ARMul_MemoryInit (); 218 ARMul_OSInit (state); 219#endif 220} 221 222 223/***************************************************************************\ 224* Emulate the execution of an entire program. Start the correct emulator * 225* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * 226* address of the last instruction that is executed. * 227\***************************************************************************/ 228 229ARMword 230ARMul_DoProg (ARMul_State * state) 231{ 232 ARMword pc = 0; 233 234 state->Emulate = RUN; 235 while (state->Emulate != STOP) 236 { 237 state->Emulate = RUN; 238 if (state->prog32Sig && ARMul_MODE32BIT) 239 pc = ARMul_Emulate32 (state); 240 else 241 pc = ARMul_Emulate26 (state); 242 } 243 return (pc); 244} 245 246/***************************************************************************\ 247* Emulate the execution of one instruction. Start the correct emulator * 248* (Emulate26 for a 26 bit ARM and Emulate32 for a 32 bit ARM), return the * 249* address of the instruction that is executed. * 250\***************************************************************************/ 251 252ARMword 253ARMul_DoInstr (ARMul_State * state) 254{ 255 ARMword pc = 0; 256 257 state->Emulate = ONCE; 258 if (state->prog32Sig && ARMul_MODE32BIT) 259 pc = ARMul_Emulate32 (state); 260 else 261 pc = ARMul_Emulate26 (state); 262 263 return (pc); 264} 265 266/***************************************************************************\ 267* This routine causes an Abort to occur, including selecting the correct * 268* mode, register bank, and the saving of registers. Call with the * 269* appropriate vector's memory address (0,4,8 ....) * 270\***************************************************************************/ 271 272void 273ARMul_Abort (ARMul_State * state, ARMword vector) 274{ 275 ARMword temp; 276 int isize = INSN_SIZE; 277 int esize = (TFLAG ? 0 : 4); 278 int e2size = (TFLAG ? -4 : 0); 279 280 state->Aborted = FALSE; 281 282 if (ARMul_OSException (state, vector, ARMul_GetPC (state))) 283 return; 284 285 if (state->prog32Sig) 286 if (ARMul_MODE26BIT) 287 temp = R15PC; 288 else 289 temp = state->Reg[15]; 290 else 291 temp = R15PC | ECC | ER15INT | EMODE; 292 293 switch (vector) 294 { 295 case ARMul_ResetV: /* RESET */ 296 SETABORT (INTBITS, state->prog32Sig ? SVC32MODE : SVC26MODE, 0); 297 break; 298 case ARMul_UndefinedInstrV: /* Undefined Instruction */ 299 SETABORT (IBIT, state->prog32Sig ? UNDEF32MODE : SVC26MODE, isize); 300 break; 301 case ARMul_SWIV: /* Software Interrupt */ 302 SETABORT (IBIT, state->prog32Sig ? SVC32MODE : SVC26MODE, isize); 303 break; 304 case ARMul_PrefetchAbortV: /* Prefetch Abort */ 305 state->AbortAddr = 1; 306 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, esize); 307 break; 308 case ARMul_DataAbortV: /* Data Abort */ 309 SETABORT (IBIT, state->prog32Sig ? ABORT32MODE : SVC26MODE, e2size); 310 break; 311 case ARMul_AddrExceptnV: /* Address Exception */ 312 SETABORT (IBIT, SVC26MODE, isize); 313 break; 314 case ARMul_IRQV: /* IRQ */ 315 if ( ! state->is_XScale 316 || ! state->CPRead[13] (state, 0, & temp) 317 || (temp & ARMul_CP13_R0_IRQ)) 318 SETABORT (IBIT, state->prog32Sig ? IRQ32MODE : IRQ26MODE, esize); 319 break; 320 case ARMul_FIQV: /* FIQ */ 321 if ( ! state->is_XScale 322 || ! state->CPRead[13] (state, 0, & temp) 323 || (temp & ARMul_CP13_R0_FIQ)) 324 SETABORT (INTBITS, state->prog32Sig ? FIQ32MODE : FIQ26MODE, esize); 325 break; 326 } 327 if (ARMul_MODE32BIT) 328 ARMul_SetR15 (state, vector); 329 else 330 ARMul_SetR15 (state, R15CCINTMODE | vector); 331 332 if (ARMul_ReadWord (state, ARMul_GetPC (state)) == 0) 333 { 334 /* No vector has been installed. Rather than simulating whatever 335 random bits might happen to be at address 0x20 onwards we elect 336 to stop. */ 337 switch (vector) 338 { 339 case ARMul_ResetV: state->EndCondition = RDIError_Reset; break; 340 case ARMul_UndefinedInstrV: state->EndCondition = RDIError_UndefinedInstruction; break; 341 case ARMul_SWIV: state->EndCondition = RDIError_SoftwareInterrupt; break; 342 case ARMul_PrefetchAbortV: state->EndCondition = RDIError_PrefetchAbort; break; 343 case ARMul_DataAbortV: state->EndCondition = RDIError_DataAbort; break; 344 case ARMul_AddrExceptnV: state->EndCondition = RDIError_AddressException; break; 345 case ARMul_IRQV: state->EndCondition = RDIError_IRQ; break; 346 case ARMul_FIQV: state->EndCondition = RDIError_FIQ; break; 347 default: break; 348 } 349 state->Emulate = FALSE; 350 } 351} 352