1/* Target-dependent code for the Xtensa port of GDB, the GNU debugger. 2 3 Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20 21/* XTENSA_TDEP_VERSION can/should be changed along with XTENSA_CONFIG_VERSION 22 whenever the "tdep" structure changes in an incompatible way. */ 23 24#define XTENSA_TDEP_VERSION 0x60 25 26/* Xtensa register type. */ 27 28typedef enum 29{ 30 xtRegisterTypeArRegfile = 1, /* Register File ar0..arXX. */ 31 xtRegisterTypeSpecialReg, /* CPU states, such as PS, Booleans, (rsr). */ 32 xtRegisterTypeUserReg, /* User defined registers (rur). */ 33 xtRegisterTypeTieRegfile, /* User define register files. */ 34 xtRegisterTypeTieState, /* TIE States (mapped on user regs). */ 35 xtRegisterTypeMapped, /* Mapped on Special Registers. */ 36 xtRegisterTypeUnmapped, /* Special case of masked registers. */ 37 xtRegisterTypeWindow, /* Live window registers (a0..a15). */ 38 xtRegisterTypeVirtual, /* PC, FP. */ 39 xtRegisterTypeUnknown 40} xtensa_register_type_t; 41 42 43/* Xtensa register group. */ 44 45#define XTENSA_MAX_COPROCESSOR 0x08 /* Number of Xtensa coprocessors. */ 46 47typedef enum 48{ 49 xtRegisterGroupUnknown = 0, 50 xtRegisterGroupRegFile = 0x0001, /* Register files without ARx. */ 51 xtRegisterGroupAddrReg = 0x0002, /* ARx. */ 52 xtRegisterGroupSpecialReg = 0x0004, /* SRxx. */ 53 xtRegisterGroupUserReg = 0x0008, /* URxx. */ 54 xtRegisterGroupState = 0x0010, /* States. */ 55 56 xtRegisterGroupGeneral = 0x0100, /* General registers, Ax, SR. */ 57 xtRegisterGroupUser = 0x0200, /* User registers. */ 58 xtRegisterGroupFloat = 0x0400, /* Floating Point. */ 59 xtRegisterGroupVectra = 0x0800, /* Vectra. */ 60 xtRegisterGroupSystem = 0x1000, /* System. */ 61 62 xtRegisterGroupCP0 = 0x01000000, /* CP0. */ 63 xtRegisterGroupCP1 = 0x02000000, /* CP1. */ 64 xtRegisterGroupCP2 = 0x04000000, /* CP2. */ 65 xtRegisterGroupCP3 = 0x08000000, /* CP3. */ 66 xtRegisterGroupCP4 = 0x10000000, /* CP4. */ 67 xtRegisterGroupCP5 = 0x20000000, /* CP5. */ 68 xtRegisterGroupCP6 = 0x40000000, /* CP6. */ 69 xtRegisterGroupCP7 = 0x80000000, /* CP7. */ 70 71} xtensa_register_group_t; 72 73 74/* Xtensa target flags. */ 75 76typedef enum 77{ 78 xtTargetFlagsNonVisibleRegs = 0x0001, 79 xtTargetFlagsUseFetchStore = 0x0002, 80} xtensa_target_flags_t; 81 82 83/* Xtensa ELF core file register set representation ('.reg' section). 84 Copied from target-side ELF header <xtensa/elf.h>. */ 85 86typedef unsigned long xtensa_elf_greg_t; 87 88typedef struct 89{ 90 xtensa_elf_greg_t xchal_config_id0; 91 xtensa_elf_greg_t xchal_config_id1; 92 xtensa_elf_greg_t cpux; 93 xtensa_elf_greg_t cpuy; 94 xtensa_elf_greg_t pc; 95 xtensa_elf_greg_t ps; 96 xtensa_elf_greg_t exccause; 97 xtensa_elf_greg_t excvaddr; 98 xtensa_elf_greg_t windowbase; 99 xtensa_elf_greg_t windowstart; 100 xtensa_elf_greg_t lbeg; 101 xtensa_elf_greg_t lend; 102 xtensa_elf_greg_t lcount; 103 xtensa_elf_greg_t sar; 104 xtensa_elf_greg_t syscall; 105 xtensa_elf_greg_t ar[0]; /* variable size (per config). */ 106} xtensa_elf_gregset_t; 107 108#define SIZEOF_GREGSET (sizeof (xtensa_elf_gregset_t) + NUM_AREGS * 4) 109#define XTENSA_ELF_NGREG (SIZEOF_GREGSET / sizeof(xtensa_elf_greg_t)) 110 111 112/* Mask. */ 113 114typedef struct 115{ 116 int reg_num; 117 int bit_start; 118 int bit_size; 119} xtensa_reg_mask_t; 120 121typedef struct 122{ 123 int count; 124 xtensa_reg_mask_t *mask; 125} xtensa_mask_t; 126 127 128/* Xtensa register representation. */ 129 130typedef struct 131{ 132 char* name; /* Register name. */ 133 int offset; /* Offset. */ 134 xtensa_register_type_t type; /* Register type. */ 135 xtensa_register_group_t group;/* Register group. */ 136 struct type* ctype; /* C-type. */ 137 int bit_size; /* The actual bit size in the target. */ 138 int byte_size; /* Actual space allocated in registers[]. */ 139 int align; /* Alignment for this register. */ 140 141 unsigned int target_number; /* Register target number. */ 142 143 int flags; /* Flags. */ 144 145 const xtensa_mask_t *mask; /* Register is a compilation of other regs. */ 146 const char *fetch; /* Instruction sequence to fetch register. */ 147 const char *store; /* Instruction sequence to store register. */ 148} xtensa_register_t; 149 150 151#define XTENSA_REGISTER_FLAGS_PRIVILEDGED 0x0001 152#define XTENSA_REGISTER_FLAGS_READABLE 0x0002 153#define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004 154#define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008 155 156 157/* Call-ABI for stack frame. */ 158 159typedef enum 160{ 161 CallAbiDefault = 0, /* Any 'callX' instructions; default stack. */ 162 CallAbiCall0Only, /* Only 'call0' instructions; flat stack. */ 163} call_abi_t; 164 165 166/* Xtensa-specific target dependencies. */ 167 168struct gdbarch_tdep 169{ 170 unsigned int target_flags; 171 172 /* Spill location for TIE register files under ocd. */ 173 174 unsigned int spill_location; 175 unsigned int spill_size; 176 177 char *unused; /* Placeholder for compatibility. */ 178 call_abi_t call_abi; /* Calling convention. */ 179 180 /* CPU configuration. */ 181 182 unsigned int debug_interrupt_level; 183 184 unsigned int icache_line_bytes; 185 unsigned int dcache_line_bytes; 186 unsigned int dcache_writeback; 187 188 unsigned int isa_use_windowed_registers; 189 unsigned int isa_use_density_instructions; 190 unsigned int isa_use_exceptions; 191 unsigned int isa_use_ext_l32r; 192 unsigned int isa_max_insn_size; /* Maximum instruction length. */ 193 unsigned int debug_num_ibreaks; /* Number of IBREAKs. */ 194 unsigned int debug_num_dbreaks; 195 196 /* Register map. */ 197 198 xtensa_register_t* regmap; 199 200 unsigned int num_regs; /* Number of registers in regmap. */ 201 unsigned int num_pseudo_regs; /* Number of pseudo registers. */ 202 unsigned int num_aregs; /* Size of register file. */ 203 unsigned int num_contexts; 204 205 int ar_base; /* Register number for AR0. */ 206 int a0_base; /* Register number for A0 (pseudo). */ 207 int wb_regnum; /* Register number for WB. */ 208 int ws_regnum; /* Register number for WS. */ 209 int pc_regnum; /* Register number for PC. */ 210 int ps_regnum; /* Register number for PS. */ 211 int lbeg_regnum; /* Register numbers for count regs. */ 212 int lend_regnum; 213 int lcount_regnum; 214 int sar_regnum; /* Register number of SAR. */ 215 int litbase_regnum; /* Register number of LITBASE. */ 216 217 int interrupt_regnum; /* Register number for interrupt. */ 218 int interrupt2_regnum; /* Register number for interrupt2. */ 219 int cpenable_regnum; /* Register number for cpenable. */ 220 int debugcause_regnum; /* Register number for debugcause. */ 221 int exccause_regnum; /* Register number for exccause. */ 222 int excvaddr_regnum; /* Register number for excvaddr. */ 223 224 int max_register_raw_size; 225 int max_register_virtual_size; 226 unsigned long *fp_layout; /* Layout of custom/TIE regs in 'FP' area. */ 227 unsigned int fp_layout_bytes; /* Size of layout information (in bytes). */ 228 unsigned long *gregmap; 229}; 230 231 232/* Define macros to access some of the gdbarch entries. */ 233#define XTENSA_TARGET_FLAGS \ 234 (gdbarch_tdep (current_gdbarch)->target_flags) 235#define SPILL_LOCATION \ 236 (gdbarch_tdep (current_gdbarch)->spill_location) 237#define SPILL_SIZE \ 238 (gdbarch_tdep (current_gdbarch)->spill_size) 239#define CALL_ABI \ 240 (gdbarch_tdep (current_gdbarch)->call_abi) 241#define ISA_USE_WINDOWED_REGISTERS \ 242 (gdbarch_tdep (current_gdbarch)->isa_use_windowed_registers) 243#define ISA_USE_DENSITY_INSTRUCTIONS \ 244 (gdbarch_tdep (current_gdbarch)->isa_use_density_instructions) 245#define ISA_USE_EXCEPTIONS \ 246 (gdbarch_tdep (current_gdbarch)->isa_use_exceptions) 247#define ISA_USE_EXT_L32R \ 248 (gdbarch_tdep (current_gdbarch)->isa_use_ext_l32r) 249#define DEBUG_DATA_VADDR_TRAP_COUNT \ 250 (gdbarch_tdep (current_gdbarch)->debug_data_vaddr_trap_count) 251#define DEBUG_INST_VADDR_TRAP_COUNT \ 252 (gdbarch_tdep (current_gdbarch)->debug_inst_vaddr_trap_count) 253#define ISA_MAX_INSN_SIZE \ 254 (gdbarch_tdep (current_gdbarch)->isa_max_insn_size) 255#define DEBUG_NUM_IBREAKS \ 256 (gdbarch_tdep (current_gdbarch)->debug_num_ibreaks) 257#define DEBUG_NUM_DBREAKS \ 258 (gdbarch_tdep (current_gdbarch)->debug_num_dbreaks) 259 260#define NUM_AREGS (gdbarch_tdep (current_gdbarch)->num_aregs) 261#define WB_REGNUM (gdbarch_tdep (current_gdbarch)->wb_regnum) 262#define WS_REGNUM (gdbarch_tdep (current_gdbarch)->ws_regnum) 263#define LBEG_REGNUM (gdbarch_tdep (current_gdbarch)->lbeg_regnum) 264#define LEND_REGNUM (gdbarch_tdep (current_gdbarch)->lend_regnum) 265#define LCOUNT_REGNUM (gdbarch_tdep (current_gdbarch)->lcount_regnum) 266#define SAR_REGNUM (gdbarch_tdep (current_gdbarch)->sar_regnum) 267#define REGMAP (gdbarch_tdep (current_gdbarch)->regmap) 268 269#define LITBASE_REGNUM (gdbarch_tdep (current_gdbarch)->litbase_regnum) 270#define DEBUGCAUSE_REGNUM (gdbarch_tdep (current_gdbarch)->debugcause_regnum) 271#define EXCCAUSE_REGNUM (gdbarch_tdep (current_gdbarch)->exccause_regnum) 272#define EXCVADDR_REGNUM (gdbarch_tdep (current_gdbarch)->excvaddr_regnum) 273#define NUM_IBREAKS (gdbarch_tdep (current_gdbarch)->num_ibreaks) 274#define REGMAP_BYTES (gdbarch_tdep (current_gdbarch)->regmap_bytes) 275#define A0_BASE (gdbarch_tdep (current_gdbarch)->a0_base) 276#define AR_BASE (gdbarch_tdep (current_gdbarch)->ar_base) 277#define FP_ALIAS \ 278 (gdbarch_num_regs (current_gdbarch) \ 279 + gdbarch_num_pseudo_regs (current_gdbarch)) 280#define CALL_ABI (gdbarch_tdep (current_gdbarch)->call_abi) 281#define NUM_CONTEXTS (gdbarch_tdep (current_gdbarch)->num_contexts) 282 283#define FP_LAYOUT (gdbarch_tdep (current_gdbarch)->fp_layout) 284#define FP_LAYOUT_BYTES (gdbarch_tdep (current_gdbarch)->fp_layout_bytes) 285#define GREGMAP (gdbarch_tdep (current_gdbarch)->gregmap) 286 287#define AREGS_MASK (NUM_AREGS - 1) 288#define WB_MASK (AREGS_MASK >> 2) 289#define WB_SHIFT 2 290 291/* We assign fixed numbers to the registers of the "current" window 292 (i.e., relative to WB). The registers get remapped via the reg_map 293 data structure to their corresponding register in the AR register 294 file (see xtensa-tdep.c). */ 295 296#define A0_REGNUM (A0_BASE + 0) 297#define A1_REGNUM (A0_BASE + 1) 298#define A2_REGNUM (A0_BASE + 2) 299#define A3_REGNUM (A0_BASE + 3) 300#define A4_REGNUM (A0_BASE + 4) 301#define A5_REGNUM (A0_BASE + 5) 302#define A6_REGNUM (A0_BASE + 6) 303#define A7_REGNUM (A0_BASE + 7) 304#define A8_REGNUM (A0_BASE + 8) 305#define A9_REGNUM (A0_BASE + 9) 306#define A10_REGNUM (A0_BASE + 10) 307#define A11_REGNUM (A0_BASE + 11) 308#define A12_REGNUM (A0_BASE + 12) 309#define A13_REGNUM (A0_BASE + 13) 310#define A14_REGNUM (A0_BASE + 14) 311#define A15_REGNUM (A0_BASE + 15) 312 313