1This is as.info, produced by makeinfo version 4.13 from 2/scratch/astubbs/arm-eabi-lite/obj/binutils-src-2013.11-24-arm-none-eabi-i686-pc-linux-gnu/gas/doc/as.texinfo. 3 4INFO-DIR-SECTION Software development 5START-INFO-DIR-ENTRY 6* As: (as). The GNU assembler. 7* Gas: (as). The GNU assembler. 8END-INFO-DIR-ENTRY 9 10 This file documents the GNU Assembler "as". 11 12 Copyright (C) 1991-2013 Free Software Foundation, Inc. 13 14 Permission is granted to copy, distribute and/or modify this document 15under the terms of the GNU Free Documentation License, Version 1.3 or 16any later version published by the Free Software Foundation; with no 17Invariant Sections, with no Front-Cover Texts, and with no Back-Cover 18Texts. A copy of the license is included in the section entitled "GNU 19Free Documentation License". 20 21 22File: as.info, Node: Top, Next: Overview, Up: (dir) 23 24Using as 25******** 26 27This file is a user guide to the GNU assembler `as' (Sourcery CodeBench 28Lite 2013.11-24) version 2.23.52. 29 30 This document is distributed under the terms of the GNU Free 31Documentation License. A copy of the license is included in the 32section entitled "GNU Free Documentation License". 33 34* Menu: 35 36* Overview:: Overview 37* Invoking:: Command-Line Options 38* Syntax:: Syntax 39* Sections:: Sections and Relocation 40* Symbols:: Symbols 41* Expressions:: Expressions 42* Pseudo Ops:: Assembler Directives 43 44* Object Attributes:: Object Attributes 45* Machine Dependencies:: Machine Dependent Features 46* Reporting Bugs:: Reporting Bugs 47* Acknowledgements:: Who Did What 48* GNU Free Documentation License:: GNU Free Documentation License 49* AS Index:: AS Index 50 51 52File: as.info, Node: Overview, Next: Invoking, Prev: Top, Up: Top 53 541 Overview 55********** 56 57Here is a brief summary of how to invoke `as'. For details, see *note 58Command-Line Options: Invoking. 59 60 as [-a[cdghlns][=FILE]] [-alternate] [-D] 61 [-compress-debug-sections] [-nocompress-debug-sections] 62 [-debug-prefix-map OLD=NEW] 63 [-defsym SYM=VAL] [-f] [-g] [-gstabs] 64 [-gstabs+] [-gdwarf-2] [-gdwarf-sections] 65 [-help] [-I DIR] [-J] 66 [-K] [-L] [-listing-lhs-width=NUM] 67 [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM] 68 [-listing-cont-lines=NUM] [-keep-locals] [-o 69 OBJFILE] [-R] [-reduce-memory-overheads] [-statistics] 70 [-v] [-version] [-version] [-W] [-warn] 71 [-fatal-warnings] [-w] [-x] [-Z] [@FILE] 72 [-size-check=[error|warning]] 73 [-target-help] [TARGET-OPTIONS] 74 [-|FILES ...] 75 76 _Target AArch64 options:_ 77 [-EB|-EL] 78 [-mabi=ABI] 79 80 _Target Alpha options:_ 81 [-mCPU] 82 [-mdebug | -no-mdebug] 83 [-replace | -noreplace] 84 [-relax] [-g] [-GSIZE] 85 [-F] [-32addr] 86 87 _Target ARC options:_ 88 [-marc[5|6|7|8]] 89 [-EB|-EL] 90 91 _Target ARM options:_ 92 [-mcpu=PROCESSOR[+EXTENSION...]] 93 [-march=ARCHITECTURE[+EXTENSION...]] 94 [-mfpu=FLOATING-POINT-FORMAT] 95 [-mfloat-abi=ABI] 96 [-meabi=VER] 97 [-mthumb] 98 [-EB|-EL] 99 [-mapcs-32|-mapcs-26|-mapcs-float| 100 -mapcs-reentrant] 101 [-mthumb-interwork] [-k] 102 103 _Target Blackfin options:_ 104 [-mcpu=PROCESSOR[-SIREVISION]] 105 [-mfdpic] 106 [-mno-fdpic] 107 [-mnopic] 108 109 _Target CRIS options:_ 110 [-underscore | -no-underscore] 111 [-pic] [-N] 112 [-emulation=criself | -emulation=crisaout] 113 [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32] 114 115 _Target D10V options:_ 116 [-O] 117 118 _Target D30V options:_ 119 [-O|-n|-N] 120 121 _Target EPIPHANY options:_ 122 [-mepiphany|-mepiphany16] 123 124 _Target H8/300 options:_ 125 [-h-tick-hex] 126 127 _Target i386 options:_ 128 [-32|-x32|-64] [-n] 129 [-march=CPU[+EXTENSION...]] [-mtune=CPU] 130 131 _Target i960 options:_ 132 [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB| 133 -AKC|-AMC] 134 [-b] [-no-relax] 135 136 _Target IA-64 options:_ 137 [-mconstant-gp|-mauto-pic] 138 [-milp32|-milp64|-mlp64|-mp64] 139 [-mle|mbe] 140 [-mtune=itanium1|-mtune=itanium2] 141 [-munwind-check=warning|-munwind-check=error] 142 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error] 143 [-x|-xexplicit] [-xauto] [-xdebug] 144 145 _Target IP2K options:_ 146 [-mip2022|-mip2022ext] 147 148 _Target M32C options:_ 149 [-m32c|-m16c] [-relax] [-h-tick-hex] 150 151 _Target M32R options:_ 152 [-m32rx|-[no-]warn-explicit-parallel-conflicts| 153 -W[n]p] 154 155 _Target M680X0 options:_ 156 [-l] [-m68000|-m68010|-m68020|...] 157 158 _Target M68HC11 options:_ 159 [-m68hc11|-m68hc12|-m68hcs12|-mm9s12x|-mm9s12xg] 160 [-mshort|-mlong] 161 [-mshort-double|-mlong-double] 162 [-force-long-branches] [-short-branches] 163 [-strict-direct-mode] [-print-insn-syntax] 164 [-print-opcodes] [-generate-example] 165 166 _Target MCORE options:_ 167 [-jsri2bsr] [-sifilter] [-relax] 168 [-mcpu=[210|340]] 169 170 _Target Meta options:_ 171 [-mcpu=CPU] [-mfpu=CPU] [-mdsp=CPU] 172 _Target MICROBLAZE options:_ 173 174 _Target MIPS options:_ 175 [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]] 176 [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared] 177 [-non_shared] [-xgot [-mvxworks-pic] 178 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32] 179 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2] 180 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2] 181 [-mips64] [-mips64r2] 182 [-construct-floats] [-no-construct-floats] 183 [-mnan=ENCODING] 184 [-trap] [-no-break] [-break] [-no-trap] 185 [-mips16] [-no-mips16] 186 [-mmicromips] [-mno-micromips] 187 [-msmartmips] [-mno-smartmips] 188 [-mips3d] [-no-mips3d] 189 [-mdmx] [-no-mdmx] 190 [-mdsp] [-mno-dsp] 191 [-mdspr2] [-mno-dspr2] 192 [-mmt] [-mno-mt] 193 [-mmcu] [-mno-mcu] 194 [-minsn32] [-mno-insn32] 195 [-mfix7000] [-mno-fix7000] 196 [-mfix-rm7000] [-mno-fix-rm7000] 197 [-mfix-vr4120] [-mno-fix-vr4120] 198 [-mfix-vr4130] [-mno-fix-vr4130] 199 [-mdebug] [-no-mdebug] 200 [-mpdr] [-mno-pdr] 201 202 _Target MMIX options:_ 203 [-fixed-special-register-names] [-globalize-symbols] 204 [-gnu-syntax] [-relax] [-no-predefined-symbols] 205 [-no-expand] [-no-merge-gregs] [-x] 206 [-linker-allocated-gregs] 207 208 _Target Nios II options:_ 209 [-relax-all] [-relax-section] [-no-relax] 210 [-EB] [-EL] 211 212 _Target PDP11 options:_ 213 [-mpic|-mno-pic] [-mall] [-mno-extensions] 214 [-mEXTENSION|-mno-EXTENSION] 215 [-mCPU] [-mMACHINE] 216 217 _Target picoJava options:_ 218 [-mb|-me] 219 220 _Target PowerPC options:_ 221 [-a32|-a64] 222 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405| 223 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64| 224 -m620|-me500|-e500x2|-me500mc|-me500mc64|-me5500|-me6500|-mppc64bridge| 225 -mbooke|-mpower4|-mpwr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6| 226 -mpower7|-mpwr7|-mpower8|-mpwr8|-ma2|-mcell|-mspe|-mtitan|-me300|-mcom] 227 [-many] [-maltivec|-mvsx|-mhtm|-mvle] 228 [-mregnames|-mno-regnames] 229 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb] 230 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be] 231 [-msolaris|-mno-solaris] 232 [-nops=COUNT] 233 234 _Target RX options:_ 235 [-mlittle-endian|-mbig-endian] 236 [-m32bit-doubles|-m64bit-doubles] 237 [-muse-conventional-section-names] 238 [-msmall-data-limit] 239 [-mpid] 240 [-mrelax] 241 [-mint-register=NUMBER] 242 [-mgcc-abi|-mrx-abi] 243 244 _Target s390 options:_ 245 [-m31|-m64] [-mesa|-mzarch] [-march=CPU] 246 [-mregnames|-mno-regnames] 247 [-mwarn-areg-zero] 248 249 _Target SCORE options:_ 250 [-EB][-EL][-FIXDD][-NWARN] 251 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3] 252 [-march=score7][-march=score3] 253 [-USE_R1][-KPIC][-O0][-G NUM][-V] 254 255 _Target SPARC options:_ 256 [-Av6|-Av7|-Av8|-Asparclet|-Asparclite 257 -Av8plus|-Av8plusa|-Av9|-Av9a] 258 [-xarch=v8plus|-xarch=v8plusa] [-bump] 259 [-32|-64] 260 261 _Target TIC54X options:_ 262 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf] 263 [-merrors-to-file <FILENAME>|-me <FILENAME>] 264 265 266 _Target TIC6X options:_ 267 [-march=ARCH] [-mbig-endian|-mlittle-endian] 268 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far] 269 [-mpic|-mno-pic] 270 271 _Target TILE-Gx options:_ 272 [-m32|-m64][-EB][-EL] 273 274 275 _Target Xtensa options:_ 276 [-[no-]text-section-literals] [-[no-]absolute-literals] 277 [-[no-]target-align] [-[no-]longcalls] 278 [-[no-]transform] 279 [-rename-section OLDNAME=NEWNAME] 280 281 282 _Target Z80 options:_ 283 [-z80] [-r800] 284 [ -ignore-undocumented-instructions] [-Wnud] 285 [ -ignore-unportable-instructions] [-Wnup] 286 [ -warn-undocumented-instructions] [-Wud] 287 [ -warn-unportable-instructions] [-Wup] 288 [ -forbid-undocumented-instructions] [-Fud] 289 [ -forbid-unportable-instructions] [-Fup] 290 291`@FILE' 292 Read command-line options from FILE. The options read are 293 inserted in place of the original @FILE option. If FILE does not 294 exist, or cannot be read, then the option will be treated 295 literally, and not removed. 296 297 Options in FILE are separated by whitespace. A whitespace 298 character may be included in an option by surrounding the entire 299 option in either single or double quotes. Any character 300 (including a backslash) may be included by prefixing the character 301 to be included with a backslash. The FILE may itself contain 302 additional @FILE options; any such options will be processed 303 recursively. 304 305`-a[cdghlmns]' 306 Turn on listings, in any of a variety of ways: 307 308 `-ac' 309 omit false conditionals 310 311 `-ad' 312 omit debugging directives 313 314 `-ag' 315 include general information, like as version and options 316 passed 317 318 `-ah' 319 include high-level source 320 321 `-al' 322 include assembly 323 324 `-am' 325 include macro expansions 326 327 `-an' 328 omit forms processing 329 330 `-as' 331 include symbols 332 333 `=file' 334 set the name of the listing file 335 336 You may combine these options; for example, use `-aln' for assembly 337 listing without forms processing. The `=file' option, if used, 338 must be the last one. By itself, `-a' defaults to `-ahls'. 339 340`--alternate' 341 Begin in alternate macro mode. *Note `.altmacro': Altmacro. 342 343`--compress-debug-sections' 344 Compress DWARF debug sections using zlib. The debug sections are 345 renamed to begin with `.zdebug', and the resulting object file may 346 not be compatible with older linkers and object file utilities. 347 348`--nocompress-debug-sections' 349 Do not compress DWARF debug sections. This is the default. 350 351`-D' 352 Ignored. This option is accepted for script compatibility with 353 calls to other assemblers. 354 355`--debug-prefix-map OLD=NEW' 356 When assembling files in directory `OLD', record debugging 357 information describing them as in `NEW' instead. 358 359`--defsym SYM=VALUE' 360 Define the symbol SYM to be VALUE before assembling the input file. 361 VALUE must be an integer constant. As in C, a leading `0x' 362 indicates a hexadecimal value, and a leading `0' indicates an octal 363 value. The value of the symbol can be overridden inside a source 364 file via the use of a `.set' pseudo-op. 365 366`-f' 367 "fast"--skip whitespace and comment preprocessing (assume source is 368 compiler output). 369 370`-g' 371`--gen-debug' 372 Generate debugging information for each assembler source line 373 using whichever debug format is preferred by the target. This 374 currently means either STABS, ECOFF or DWARF2. 375 376`--gstabs' 377 Generate stabs debugging information for each assembler line. This 378 may help debugging assembler code, if the debugger can handle it. 379 380`--gstabs+' 381 Generate stabs debugging information for each assembler line, with 382 GNU extensions that probably only gdb can handle, and that could 383 make other debuggers crash or refuse to read your program. This 384 may help debugging assembler code. Currently the only GNU 385 extension is the location of the current working directory at 386 assembling time. 387 388`--gdwarf-2' 389 Generate DWARF2 debugging information for each assembler line. 390 This may help debugging assembler code, if the debugger can handle 391 it. Note--this option is only supported by some targets, not all 392 of them. 393 394`--gdwarf-sections' 395 Instead of creating a .debug_line section, create a series of 396 .debug_line.FOO sections where FOO is the name of the 397 corresponding code section. For example a code section called 398 .TEXT.FUNC will have its dwarf line number information placed into 399 a section called .DEBUG_LINE.TEXT.FUNC. If the code section is 400 just called .TEXT then debug line section will still be called 401 just .DEBUG_LINE without any suffix. 402 403`--size-check=error' 404`--size-check=warning' 405 Issue an error or warning for invalid ELF .size directive. 406 407`--help' 408 Print a summary of the command line options and exit. 409 410`--target-help' 411 Print a summary of all target specific options and exit. 412 413`-I DIR' 414 Add directory DIR to the search list for `.include' directives. 415 416`-J' 417 Don't warn about signed overflow. 418 419`-K' 420 Issue warnings when difference tables altered for long 421 displacements. 422 423`-L' 424`--keep-locals' 425 Keep (in the symbol table) local symbols. These symbols start with 426 system-specific local label prefixes, typically `.L' for ELF 427 systems or `L' for traditional a.out systems. *Note Symbol 428 Names::. 429 430`--listing-lhs-width=NUMBER' 431 Set the maximum width, in words, of the output data column for an 432 assembler listing to NUMBER. 433 434`--listing-lhs-width2=NUMBER' 435 Set the maximum width, in words, of the output data column for 436 continuation lines in an assembler listing to NUMBER. 437 438`--listing-rhs-width=NUMBER' 439 Set the maximum width of an input source line, as displayed in a 440 listing, to NUMBER bytes. 441 442`--listing-cont-lines=NUMBER' 443 Set the maximum number of lines printed in a listing for a single 444 line of input to NUMBER + 1. 445 446`-o OBJFILE' 447 Name the object-file output from `as' OBJFILE. 448 449`-R' 450 Fold the data section into the text section. 451 452 Set the default size of GAS's hash tables to a prime number close 453 to NUMBER. Increasing this value can reduce the length of time it 454 takes the assembler to perform its tasks, at the expense of 455 increasing the assembler's memory requirements. Similarly 456 reducing this value can reduce the memory requirements at the 457 expense of speed. 458 459`--reduce-memory-overheads' 460 This option reduces GAS's memory requirements, at the expense of 461 making the assembly processes slower. Currently this switch is a 462 synonym for `--hash-size=4051', but in the future it may have 463 other effects as well. 464 465`--statistics' 466 Print the maximum space (in bytes) and total time (in seconds) 467 used by assembly. 468 469`--strip-local-absolute' 470 Remove local absolute symbols from the outgoing symbol table. 471 472`-v' 473`-version' 474 Print the `as' version. 475 476`--version' 477 Print the `as' version and exit. 478 479`-W' 480`--no-warn' 481 Suppress warning messages. 482 483`--fatal-warnings' 484 Treat warnings as errors. 485 486`--warn' 487 Don't suppress warning messages or treat them as errors. 488 489`-w' 490 Ignored. 491 492`-x' 493 Ignored. 494 495`-Z' 496 Generate an object file even after errors. 497 498`-- | FILES ...' 499 Standard input, or source files to assemble. 500 501 502 *Note AArch64 Options::, for the options available when as is 503configured for the 64-bit mode of the ARM Architecture (AArch64). 504 505 *Note Alpha Options::, for the options available when as is 506configured for an Alpha processor. 507 508 The following options are available when as is configured for an ARC 509processor. 510 511`-marc[5|6|7|8]' 512 This option selects the core processor variant. 513 514`-EB | -EL' 515 Select either big-endian (-EB) or little-endian (-EL) output. 516 517 The following options are available when as is configured for the ARM 518processor family. 519 520`-mcpu=PROCESSOR[+EXTENSION...]' 521 Specify which ARM processor variant is the target. 522 523`-march=ARCHITECTURE[+EXTENSION...]' 524 Specify which ARM architecture variant is used by the target. 525 526`-mfpu=FLOATING-POINT-FORMAT' 527 Select which Floating Point architecture is the target. 528 529`-mfloat-abi=ABI' 530 Select which floating point ABI is in use. 531 532`-mthumb' 533 Enable Thumb only instruction decoding. 534 535`-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant' 536 Select which procedure calling convention is in use. 537 538`-EB | -EL' 539 Select either big-endian (-EB) or little-endian (-EL) output. 540 541`-mthumb-interwork' 542 Specify that the code has been generated with interworking between 543 Thumb and ARM code in mind. 544 545`-k' 546 Specify that PIC code has been generated. 547 548 *Note Blackfin Options::, for the options available when as is 549configured for the Blackfin processor family. 550 551 See the info pages for documentation of the CRIS-specific options. 552 553 The following options are available when as is configured for a D10V 554processor. 555`-O' 556 Optimize output by parallelizing instructions. 557 558 The following options are available when as is configured for a D30V 559processor. 560`-O' 561 Optimize output by parallelizing instructions. 562 563`-n' 564 Warn when nops are generated. 565 566`-N' 567 Warn when a nop after a 32-bit multiply instruction is generated. 568 569 The following options are available when as is configured for the 570Adapteva EPIPHANY series. 571 572 *Note Epiphany Options::, for the options available when as is 573configured for an Epiphany processor. 574 575 *Note i386-Options::, for the options available when as is 576configured for an i386 processor. 577 578 The following options are available when as is configured for the 579Intel 80960 processor. 580 581`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' 582 Specify which variant of the 960 architecture is the target. 583 584`-b' 585 Add code to collect statistics about branches taken. 586 587`-no-relax' 588 Do not alter compare-and-branch instructions for long 589 displacements; error if necessary. 590 591 592 The following options are available when as is configured for the 593Ubicom IP2K series. 594 595`-mip2022ext' 596 Specifies that the extended IP2022 instructions are allowed. 597 598`-mip2022' 599 Restores the default behaviour, which restricts the permitted 600 instructions to just the basic IP2022 ones. 601 602 603 The following options are available when as is configured for the 604Renesas M32C and M16C processors. 605 606`-m32c' 607 Assemble M32C instructions. 608 609`-m16c' 610 Assemble M16C instructions (the default). 611 612`-relax' 613 Enable support for link-time relaxations. 614 615`-h-tick-hex' 616 Support H'00 style hex constants in addition to 0x00 style. 617 618 619 The following options are available when as is configured for the 620Renesas M32R (formerly Mitsubishi M32R) series. 621 622`--m32rx' 623 Specify which processor in the M32R family is the target. The 624 default is normally the M32R, but this option changes it to the 625 M32RX. 626 627`--warn-explicit-parallel-conflicts or --Wp' 628 Produce warning messages when questionable parallel constructs are 629 encountered. 630 631`--no-warn-explicit-parallel-conflicts or --Wnp' 632 Do not produce warning messages when questionable parallel 633 constructs are encountered. 634 635 636 The following options are available when as is configured for the 637Motorola 68000 series. 638 639`-l' 640 Shorten references to undefined symbols, to one word instead of 641 two. 642 643`-m68000 | -m68008 | -m68010 | -m68020 | -m68030' 644`| -m68040 | -m68060 | -m68302 | -m68331 | -m68332' 645`| -m68333 | -m68340 | -mcpu32 | -m5200' 646 Specify what processor in the 68000 family is the target. The 647 default is normally the 68020, but this can be changed at 648 configuration time. 649 650`-m68881 | -m68882 | -mno-68881 | -mno-68882' 651 The target machine does (or does not) have a floating-point 652 coprocessor. The default is to assume a coprocessor for 68020, 653 68030, and cpu32. Although the basic 68000 is not compatible with 654 the 68881, a combination of the two can be specified, since it's 655 possible to do emulation of the coprocessor instructions with the 656 main processor. 657 658`-m68851 | -mno-68851' 659 The target machine does (or does not) have a memory-management 660 unit coprocessor. The default is to assume an MMU for 68020 and 661 up. 662 663 664 *Note Nios II Options::, for the options available when as is 665configured for an Altera Nios II processor. 666 667 For details about the PDP-11 machine dependent features options, see 668*note PDP-11-Options::. 669 670`-mpic | -mno-pic' 671 Generate position-independent (or position-dependent) code. The 672 default is `-mpic'. 673 674`-mall' 675`-mall-extensions' 676 Enable all instruction set extensions. This is the default. 677 678`-mno-extensions' 679 Disable all instruction set extensions. 680 681`-mEXTENSION | -mno-EXTENSION' 682 Enable (or disable) a particular instruction set extension. 683 684`-mCPU' 685 Enable the instruction set extensions supported by a particular 686 CPU, and disable all other extensions. 687 688`-mMACHINE' 689 Enable the instruction set extensions supported by a particular 690 machine model, and disable all other extensions. 691 692 The following options are available when as is configured for a 693picoJava processor. 694 695`-mb' 696 Generate "big endian" format output. 697 698`-ml' 699 Generate "little endian" format output. 700 701 702 The following options are available when as is configured for the 703Motorola 68HC11 or 68HC12 series. 704 705`-m68hc11 | -m68hc12 | -m68hcs12 | -mm9s12x | -mm9s12xg' 706 Specify what processor is the target. The default is defined by 707 the configuration option when building the assembler. 708 709`--xgate-ramoffset' 710 Instruct the linker to offset RAM addresses from S12X address 711 space into XGATE address space. 712 713`-mshort' 714 Specify to use the 16-bit integer ABI. 715 716`-mlong' 717 Specify to use the 32-bit integer ABI. 718 719`-mshort-double' 720 Specify to use the 32-bit double ABI. 721 722`-mlong-double' 723 Specify to use the 64-bit double ABI. 724 725`--force-long-branches' 726 Relative branches are turned into absolute ones. This concerns 727 conditional branches, unconditional branches and branches to a sub 728 routine. 729 730`-S | --short-branches' 731 Do not turn relative branches into absolute ones when the offset 732 is out of range. 733 734`--strict-direct-mode' 735 Do not turn the direct addressing mode into extended addressing 736 mode when the instruction does not support direct addressing mode. 737 738`--print-insn-syntax' 739 Print the syntax of instruction in case of error. 740 741`--print-opcodes' 742 Print the list of instructions with syntax and then exit. 743 744`--generate-example' 745 Print an example of instruction for each possible instruction and 746 then exit. This option is only useful for testing `as'. 747 748 749 The following options are available when `as' is configured for the 750SPARC architecture: 751 752`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' 753`-Av8plus | -Av8plusa | -Av9 | -Av9a' 754 Explicitly select a variant of the SPARC architecture. 755 756 `-Av8plus' and `-Av8plusa' select a 32 bit environment. `-Av9' 757 and `-Av9a' select a 64 bit environment. 758 759 `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with 760 UltraSPARC extensions. 761 762`-xarch=v8plus | -xarch=v8plusa' 763 For compatibility with the Solaris v9 assembler. These options are 764 equivalent to -Av8plus and -Av8plusa, respectively. 765 766`-bump' 767 Warn when the assembler switches to another architecture. 768 769 The following options are available when as is configured for the 770'c54x architecture. 771 772`-mfar-mode' 773 Enable extended addressing mode. All addresses and relocations 774 will assume extended addressing (usually 23 bits). 775 776`-mcpu=CPU_VERSION' 777 Sets the CPU version being compiled for. 778 779`-merrors-to-file FILENAME' 780 Redirect error output to a file, for broken systems which don't 781 support such behaviour in the shell. 782 783 The following options are available when as is configured for a MIPS 784processor. 785 786`-G NUM' 787 This option sets the largest size of an object that can be 788 referenced implicitly with the `gp' register. It is only accepted 789 for targets that use ECOFF format, such as a DECstation running 790 Ultrix. The default value is 8. 791 792`-EB' 793 Generate "big endian" format output. 794 795`-EL' 796 Generate "little endian" format output. 797 798`-mips1' 799`-mips2' 800`-mips3' 801`-mips4' 802`-mips5' 803`-mips32' 804`-mips32r2' 805`-mips64' 806`-mips64r2' 807 Generate code for a particular MIPS Instruction Set Architecture 808 level. `-mips1' is an alias for `-march=r3000', `-mips2' is an 809 alias for `-march=r6000', `-mips3' is an alias for `-march=r4000' 810 and `-mips4' is an alias for `-march=r8000'. `-mips5', `-mips32', 811 `-mips32r2', `-mips64', and `-mips64r2' correspond to generic MIPS 812 V, MIPS32, MIPS32 Release 2, MIPS64, and MIPS64 Release 2 ISA 813 processors, respectively. 814 815`-march=CPU' 816 Generate code for a particular MIPS CPU. 817 818`-mtune=CPU' 819 Schedule and tune for a particular MIPS CPU. 820 821`-mfix7000' 822`-mno-fix7000' 823 Cause nops to be inserted if the read of the destination register 824 of an mfhi or mflo instruction occurs in the following two 825 instructions. 826 827`-mfix-rm7000' 828`-mno-fix-rm7000' 829 Cause nops to be inserted if a dmult or dmultu instruction is 830 followed by a load instruction. 831 832`-mdebug' 833`-no-mdebug' 834 Cause stabs-style debugging output to go into an ECOFF-style 835 .mdebug section instead of the standard ELF .stabs sections. 836 837`-mpdr' 838`-mno-pdr' 839 Control generation of `.pdr' sections. 840 841`-mgp32' 842`-mfp32' 843 The register sizes are normally inferred from the ISA and ABI, but 844 these flags force a certain group of registers to be treated as 32 845 bits wide at all times. `-mgp32' controls the size of 846 general-purpose registers and `-mfp32' controls the size of 847 floating-point registers. 848 849`-mips16' 850`-no-mips16' 851 Generate code for the MIPS 16 processor. This is equivalent to 852 putting `.set mips16' at the start of the assembly file. 853 `-no-mips16' turns off this option. 854 855`-mmicromips' 856`-mno-micromips' 857 Generate code for the microMIPS processor. This is equivalent to 858 putting `.set micromips' at the start of the assembly file. 859 `-mno-micromips' turns off this option. This is equivalent to 860 putting `.set nomicromips' at the start of the assembly file. 861 862`-msmartmips' 863`-mno-smartmips' 864 Enables the SmartMIPS extension to the MIPS32 instruction set. 865 This is equivalent to putting `.set smartmips' at the start of the 866 assembly file. `-mno-smartmips' turns off this option. 867 868`-mips3d' 869`-no-mips3d' 870 Generate code for the MIPS-3D Application Specific Extension. 871 This tells the assembler to accept MIPS-3D instructions. 872 `-no-mips3d' turns off this option. 873 874`-mdmx' 875`-no-mdmx' 876 Generate code for the MDMX Application Specific Extension. This 877 tells the assembler to accept MDMX instructions. `-no-mdmx' turns 878 off this option. 879 880`-mdsp' 881`-mno-dsp' 882 Generate code for the DSP Release 1 Application Specific Extension. 883 This tells the assembler to accept DSP Release 1 instructions. 884 `-mno-dsp' turns off this option. 885 886`-mdspr2' 887`-mno-dspr2' 888 Generate code for the DSP Release 2 Application Specific Extension. 889 This option implies -mdsp. This tells the assembler to accept DSP 890 Release 2 instructions. `-mno-dspr2' turns off this option. 891 892`-mmt' 893`-mno-mt' 894 Generate code for the MT Application Specific Extension. This 895 tells the assembler to accept MT instructions. `-mno-mt' turns 896 off this option. 897 898`-mmcu' 899`-mno-mcu' 900 Generate code for the MCU Application Specific Extension. This 901 tells the assembler to accept MCU instructions. `-mno-mcu' turns 902 off this option. 903 904`-minsn32' 905`-mno-insn32' 906 Only use 32-bit instruction encodings when generating code for the 907 microMIPS processor. This option inhibits the use of any 16-bit 908 instructions. This is equivalent to putting `.set insn32' at the 909 start of the assembly file. `-mno-insn32' turns off this option. 910 This is equivalent to putting `.set noinsn32' at the start of the 911 assembly file. By default `-mno-insn32' is selected, allowing all 912 instructions to be used. 913 914`--construct-floats' 915`--no-construct-floats' 916 The `--no-construct-floats' option disables the construction of 917 double width floating point constants by loading the two halves of 918 the value into the two single width floating point registers that 919 make up the double width register. By default 920 `--construct-floats' is selected, allowing construction of these 921 floating point constants. 922 923`--relax-branch' 924`--no-relax-branch' 925 The `--relax-branch' option enables the relaxation of out-of-range 926 branches. By default `--no-relax-branch' is selected, causing any 927 out-of-range branches to produce an error. 928 929`-mnan=ENCODING' 930 Select between the IEEE 754-2008 (`-mnan=2008') or the legacy 931 (`-mnan=legacy') NaN encoding format. The latter is the default. 932 933`--emulation=NAME' 934 This option was formerly used to switch between ELF and ECOFF 935 output on targets like IRIX 5 that supported both. MIPS ECOFF 936 support was removed in GAS 2.24, so the option now serves little 937 purpose. It is retained for backwards compatibility. 938 939 The available configuration names are: `mipself', `mipslelf' and 940 `mipsbelf'. Choosing `mipself' now has no effect, since the output 941 is always ELF. `mipslelf' and `mipsbelf' select little- and 942 big-endian output respectively, but `-EL' and `-EB' are now the 943 preferred options instead. 944 945`-nocpp' 946 `as' ignores this option. It is accepted for compatibility with 947 the native tools. 948 949`--trap' 950`--no-trap' 951`--break' 952`--no-break' 953 Control how to deal with multiplication overflow and division by 954 zero. `--trap' or `--no-break' (which are synonyms) take a trap 955 exception (and only work for Instruction Set Architecture level 2 956 and higher); `--break' or `--no-trap' (also synonyms, and the 957 default) take a break exception. 958 959`-n' 960 When this option is used, `as' will issue a warning every time it 961 generates a nop instruction from a macro. 962 963 The following options are available when as is configured for an 964MCore processor. 965 966`-jsri2bsr' 967`-nojsri2bsr' 968 Enable or disable the JSRI to BSR transformation. By default this 969 is enabled. The command line option `-nojsri2bsr' can be used to 970 disable it. 971 972`-sifilter' 973`-nosifilter' 974 Enable or disable the silicon filter behaviour. By default this 975 is disabled. The default can be overridden by the `-sifilter' 976 command line option. 977 978`-relax' 979 Alter jump instructions for long displacements. 980 981`-mcpu=[210|340]' 982 Select the cpu type on the target hardware. This controls which 983 instructions can be assembled. 984 985`-EB' 986 Assemble for a big endian target. 987 988`-EL' 989 Assemble for a little endian target. 990 991 992 *Note Meta Options::, for the options available when as is configured 993for a Meta processor. 994 995 See the info pages for documentation of the MMIX-specific options. 996 997 *Note PowerPC-Opts::, for the options available when as is configured 998for a PowerPC processor. 999 1000 See the info pages for documentation of the RX-specific options. 1001 1002 The following options are available when as is configured for the 1003s390 processor family. 1004 1005`-m31' 1006`-m64' 1007 Select the word size, either 31/32 bits or 64 bits. 1008 1009`-mesa' 1010 1011`-mzarch' 1012 Select the architecture mode, either the Enterprise System 1013 Architecture (esa) or the z/Architecture mode (zarch). 1014 1015`-march=PROCESSOR' 1016 Specify which s390 processor variant is the target, `g6', `g6', 1017 `z900', `z990', `z9-109', `z9-ec', `z10', `z196', or `zEC12'. 1018 1019`-mregnames' 1020`-mno-regnames' 1021 Allow or disallow symbolic names for registers. 1022 1023`-mwarn-areg-zero' 1024 Warn whenever the operand for a base or index register has been 1025 specified but evaluates to zero. 1026 1027 *Note TIC6X Options::, for the options available when as is 1028configured for a TMS320C6000 processor. 1029 1030 *Note TILE-Gx Options::, for the options available when as is 1031configured for a TILE-Gx processor. 1032 1033 *Note Xtensa Options::, for the options available when as is 1034configured for an Xtensa processor. 1035 1036 The following options are available when as is configured for a Z80 1037family processor. 1038`-z80' 1039 Assemble for Z80 processor. 1040 1041`-r800' 1042 Assemble for R800 processor. 1043 1044`-ignore-undocumented-instructions' 1045`-Wnud' 1046 Assemble undocumented Z80 instructions that also work on R800 1047 without warning. 1048 1049`-ignore-unportable-instructions' 1050`-Wnup' 1051 Assemble all undocumented Z80 instructions without warning. 1052 1053`-warn-undocumented-instructions' 1054`-Wud' 1055 Issue a warning for undocumented Z80 instructions that also work 1056 on R800. 1057 1058`-warn-unportable-instructions' 1059`-Wup' 1060 Issue a warning for undocumented Z80 instructions that do not work 1061 on R800. 1062 1063`-forbid-undocumented-instructions' 1064`-Fud' 1065 Treat all undocumented instructions as errors. 1066 1067`-forbid-unportable-instructions' 1068`-Fup' 1069 Treat undocumented Z80 instructions that do not work on R800 as 1070 errors. 1071 1072* Menu: 1073 1074* Manual:: Structure of this Manual 1075* GNU Assembler:: The GNU Assembler 1076* Object Formats:: Object File Formats 1077* Command Line:: Command Line 1078* Input Files:: Input Files 1079* Object:: Output (Object) File 1080* Errors:: Error and Warning Messages 1081 1082 1083File: as.info, Node: Manual, Next: GNU Assembler, Up: Overview 1084 10851.1 Structure of this Manual 1086============================ 1087 1088This manual is intended to describe what you need to know to use GNU 1089`as'. We cover the syntax expected in source files, including notation 1090for symbols, constants, and expressions; the directives that `as' 1091understands; and of course how to invoke `as'. 1092 1093 This manual also describes some of the machine-dependent features of 1094various flavors of the assembler. 1095 1096 On the other hand, this manual is _not_ intended as an introduction 1097to programming in assembly language--let alone programming in general! 1098In a similar vein, we make no attempt to introduce the machine 1099architecture; we do _not_ describe the instruction set, standard 1100mnemonics, registers or addressing modes that are standard to a 1101particular architecture. You may want to consult the manufacturer's 1102machine architecture manual for this information. 1103 1104 1105File: as.info, Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: Overview 1106 11071.2 The GNU Assembler 1108===================== 1109 1110GNU `as' is really a family of assemblers. If you use (or have used) 1111the GNU assembler on one architecture, you should find a fairly similar 1112environment when you use it on another architecture. Each version has 1113much in common with the others, including object file formats, most 1114assembler directives (often called "pseudo-ops") and assembler syntax. 1115 1116 `as' is primarily intended to assemble the output of the GNU C 1117compiler `gcc' for use by the linker `ld'. Nevertheless, we've tried 1118to make `as' assemble correctly everything that other assemblers for 1119the same machine would assemble. Any exceptions are documented 1120explicitly (*note Machine Dependencies::). This doesn't mean `as' 1121always uses the same syntax as another assembler for the same 1122architecture; for example, we know of several incompatible versions of 1123680x0 assembly language syntax. 1124 1125 Unlike older assemblers, `as' is designed to assemble a source 1126program in one pass of the source file. This has a subtle impact on the 1127`.org' directive (*note `.org': Org.). 1128 1129 1130File: as.info, Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview 1131 11321.3 Object File Formats 1133======================= 1134 1135The GNU assembler can be configured to produce several alternative 1136object file formats. For the most part, this does not affect how you 1137write assembly language programs; but directives for debugging symbols 1138are typically different in different file formats. *Note Symbol 1139Attributes: Symbol Attributes. 1140 1141 1142File: as.info, Node: Command Line, Next: Input Files, Prev: Object Formats, Up: Overview 1143 11441.4 Command Line 1145================ 1146 1147After the program name `as', the command line may contain options and 1148file names. Options may appear in any order, and may be before, after, 1149or between file names. The order of file names is significant. 1150 1151 `--' (two hyphens) by itself names the standard input file 1152explicitly, as one of the files for `as' to assemble. 1153 1154 Except for `--' any command line argument that begins with a hyphen 1155(`-') is an option. Each option changes the behavior of `as'. No 1156option changes the way another option works. An option is a `-' 1157followed by one or more letters; the case of the letter is important. 1158All options are optional. 1159 1160 Some options expect exactly one file name to follow them. The file 1161name may either immediately follow the option's letter (compatible with 1162older assemblers) or it may be the next command argument (GNU 1163standard). These two command lines are equivalent: 1164 1165 as -o my-object-file.o mumble.s 1166 as -omy-object-file.o mumble.s 1167 1168 1169File: as.info, Node: Input Files, Next: Object, Prev: Command Line, Up: Overview 1170 11711.5 Input Files 1172=============== 1173 1174We use the phrase "source program", abbreviated "source", to describe 1175the program input to one run of `as'. The program may be in one or 1176more files; how the source is partitioned into files doesn't change the 1177meaning of the source. 1178 1179 The source program is a concatenation of the text in all the files, 1180in the order specified. 1181 1182 Each time you run `as' it assembles exactly one source program. The 1183source program is made up of one or more files. (The standard input is 1184also a file.) 1185 1186 You give `as' a command line that has zero or more input file names. 1187The input files are read (from left file name to right). A command 1188line argument (in any position) that has no special meaning is taken to 1189be an input file name. 1190 1191 If you give `as' no file names it attempts to read one input file 1192from the `as' standard input, which is normally your terminal. You may 1193have to type <ctl-D> to tell `as' there is no more program to assemble. 1194 1195 Use `--' if you need to explicitly name the standard input file in 1196your command line. 1197 1198 If the source is empty, `as' produces a small, empty object file. 1199 1200Filenames and Line-numbers 1201-------------------------- 1202 1203There are two ways of locating a line in the input file (or files) and 1204either may be used in reporting error messages. One way refers to a 1205line number in a physical file; the other refers to a line number in a 1206"logical" file. *Note Error and Warning Messages: Errors. 1207 1208 "Physical files" are those files named in the command line given to 1209`as'. 1210 1211 "Logical files" are simply names declared explicitly by assembler 1212directives; they bear no relation to physical files. Logical file 1213names help error messages reflect the original source file, when `as' 1214source is itself synthesized from other files. `as' understands the 1215`#' directives emitted by the `gcc' preprocessor. See also *note 1216`.file': File. 1217 1218 1219File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview 1220 12211.6 Output (Object) File 1222======================== 1223 1224Every time you run `as' it produces an output file, which is your 1225assembly language program translated into numbers. This file is the 1226object file. Its default name is `a.out'. You can give it another 1227name by using the `-o' option. Conventionally, object file names end 1228with `.o'. The default name is used for historical reasons: older 1229assemblers were capable of assembling self-contained programs directly 1230into a runnable program. (For some formats, this isn't currently 1231possible, but it can be done for the `a.out' format.) 1232 1233 The object file is meant for input to the linker `ld'. It contains 1234assembled program code, information to help `ld' integrate the 1235assembled program into a runnable file, and (optionally) symbolic 1236information for the debugger. 1237 1238 1239File: as.info, Node: Errors, Prev: Object, Up: Overview 1240 12411.7 Error and Warning Messages 1242============================== 1243 1244`as' may write warnings and error messages to the standard error file 1245(usually your terminal). This should not happen when a compiler runs 1246`as' automatically. Warnings report an assumption made so that `as' 1247could keep assembling a flawed program; errors report a grave problem 1248that stops the assembly. 1249 1250 Warning messages have the format 1251 1252 file_name:NNN:Warning Message Text 1253 1254(where NNN is a line number). If a logical file name has been given 1255(*note `.file': File.) it is used for the filename, otherwise the name 1256of the current input file is used. If a logical line number was given 1257(*note `.line': Line.) then it is used to calculate the number printed, 1258otherwise the actual line in the current source file is printed. The 1259message text is intended to be self explanatory (in the grand Unix 1260tradition). 1261 1262 Error messages have the format 1263 file_name:NNN:FATAL:Error Message Text 1264 The file name and line number are derived as for warning messages. 1265The actual message text may be rather less explanatory because many of 1266them aren't supposed to happen. 1267 1268 1269File: as.info, Node: Invoking, Next: Syntax, Prev: Overview, Up: Top 1270 12712 Command-Line Options 1272********************** 1273 1274This chapter describes command-line options available in _all_ versions 1275of the GNU assembler; see *note Machine Dependencies::, for options 1276specific to particular machine architectures. 1277 1278 If you are invoking `as' via the GNU C compiler, you can use the 1279`-Wa' option to pass arguments through to the assembler. The assembler 1280arguments must be separated from each other (and the `-Wa') by commas. 1281For example: 1282 1283 gcc -c -g -O -Wa,-alh,-L file.c 1284 1285This passes two options to the assembler: `-alh' (emit a listing to 1286standard output with high-level and assembly source) and `-L' (retain 1287local symbols in the symbol table). 1288 1289 Usually you do not need to use this `-Wa' mechanism, since many 1290compiler command-line options are automatically passed to the assembler 1291by the compiler. (You can call the GNU compiler driver with the `-v' 1292option to see precisely what options it passes to each compilation 1293pass, including the assembler.) 1294 1295* Menu: 1296 1297* a:: -a[cdghlns] enable listings 1298* alternate:: --alternate enable alternate macro syntax 1299* D:: -D for compatibility 1300* f:: -f to work faster 1301* I:: -I for .include search path 1302 1303* K:: -K for difference tables 1304 1305* L:: -L to retain local symbols 1306* listing:: --listing-XXX to configure listing output 1307* M:: -M or --mri to assemble in MRI compatibility mode 1308* MD:: --MD for dependency tracking 1309* o:: -o to name the object file 1310* R:: -R to join data and text sections 1311* statistics:: --statistics to see statistics about assembly 1312* traditional-format:: --traditional-format for compatible output 1313* v:: -v to announce version 1314* W:: -W, --no-warn, --warn, --fatal-warnings to control warnings 1315* Z:: -Z to make object file even after errors 1316 1317 1318File: as.info, Node: a, Next: alternate, Up: Invoking 1319 13202.1 Enable Listings: `-a[cdghlns]' 1321================================== 1322 1323These options enable listing output from the assembler. By itself, 1324`-a' requests high-level, assembly, and symbols listing. You can use 1325other letters to select specific options for the list: `-ah' requests a 1326high-level language listing, `-al' requests an output-program assembly 1327listing, and `-as' requests a symbol table listing. High-level 1328listings require that a compiler debugging option like `-g' be used, 1329and that assembly listings (`-al') be requested also. 1330 1331 Use the `-ag' option to print a first section with general assembly 1332information, like as version, switches passed, or time stamp. 1333 1334 Use the `-ac' option to omit false conditionals from a listing. Any 1335lines which are not assembled because of a false `.if' (or `.ifdef', or 1336any other conditional), or a true `.if' followed by an `.else', will be 1337omitted from the listing. 1338 1339 Use the `-ad' option to omit debugging directives from the listing. 1340 1341 Once you have specified one of these options, you can further control 1342listing output and its appearance using the directives `.list', 1343`.nolist', `.psize', `.eject', `.title', and `.sbttl'. The `-an' 1344option turns off all forms processing. If you do not request listing 1345output with one of the `-a' options, the listing-control directives 1346have no effect. 1347 1348 The letters after `-a' may be combined into one option, _e.g._, 1349`-aln'. 1350 1351 Note if the assembler source is coming from the standard input (e.g., 1352because it is being created by `gcc' and the `-pipe' command line switch 1353is being used) then the listing will not contain any comments or 1354preprocessor directives. This is because the listing code buffers 1355input source lines from stdin only after they have been preprocessed by 1356the assembler. This reduces memory usage and makes the code more 1357efficient. 1358 1359 1360File: as.info, Node: alternate, Next: D, Prev: a, Up: Invoking 1361 13622.2 `--alternate' 1363================= 1364 1365Begin in alternate macro mode, see *note `.altmacro': Altmacro. 1366 1367 1368File: as.info, Node: D, Next: f, Prev: alternate, Up: Invoking 1369 13702.3 `-D' 1371======== 1372 1373This option has no effect whatsoever, but it is accepted to make it more 1374likely that scripts written for other assemblers also work with `as'. 1375 1376 1377File: as.info, Node: f, Next: I, Prev: D, Up: Invoking 1378 13792.4 Work Faster: `-f' 1380===================== 1381 1382`-f' should only be used when assembling programs written by a 1383(trusted) compiler. `-f' stops the assembler from doing whitespace and 1384comment preprocessing on the input file(s) before assembling them. 1385*Note Preprocessing: Preprocessing. 1386 1387 _Warning:_ if you use `-f' when the files actually need to be 1388 preprocessed (if they contain comments, for example), `as' does 1389 not work correctly. 1390 1391 1392File: as.info, Node: I, Next: K, Prev: f, Up: Invoking 1393 13942.5 `.include' Search Path: `-I' PATH 1395===================================== 1396 1397Use this option to add a PATH to the list of directories `as' searches 1398for files specified in `.include' directives (*note `.include': 1399Include.). You may use `-I' as many times as necessary to include a 1400variety of paths. The current working directory is always searched 1401first; after that, `as' searches any `-I' directories in the same order 1402as they were specified (left to right) on the command line. 1403 1404 1405File: as.info, Node: K, Next: L, Prev: I, Up: Invoking 1406 14072.6 Difference Tables: `-K' 1408=========================== 1409 1410`as' sometimes alters the code emitted for directives of the form 1411`.word SYM1-SYM2'. *Note `.word': Word. You can use the `-K' option 1412if you want a warning issued when this is done. 1413 1414 1415File: as.info, Node: L, Next: listing, Prev: K, Up: Invoking 1416 14172.7 Include Local Symbols: `-L' 1418=============================== 1419 1420Symbols beginning with system-specific local label prefixes, typically 1421`.L' for ELF systems or `L' for traditional a.out systems, are called 1422"local symbols". *Note Symbol Names::. Normally you do not see such 1423symbols when debugging, because they are intended for the use of 1424programs (like compilers) that compose assembler programs, not for your 1425notice. Normally both `as' and `ld' discard such symbols, so you do 1426not normally debug with them. 1427 1428 This option tells `as' to retain those local symbols in the object 1429file. Usually if you do this you also tell the linker `ld' to preserve 1430those symbols. 1431 1432 1433File: as.info, Node: listing, Next: M, Prev: L, Up: Invoking 1434 14352.8 Configuring listing output: `--listing' 1436=========================================== 1437 1438The listing feature of the assembler can be enabled via the command 1439line switch `-a' (*note a::). This feature combines the input source 1440file(s) with a hex dump of the corresponding locations in the output 1441object file, and displays them as a listing file. The format of this 1442listing can be controlled by directives inside the assembler source 1443(i.e., `.list' (*note List::), `.title' (*note Title::), `.sbttl' 1444(*note Sbttl::), `.psize' (*note Psize::), and `.eject' (*note Eject::) 1445and also by the following switches: 1446 1447`--listing-lhs-width=`number'' 1448 Sets the maximum width, in words, of the first line of the hex 1449 byte dump. This dump appears on the left hand side of the listing 1450 output. 1451 1452`--listing-lhs-width2=`number'' 1453 Sets the maximum width, in words, of any further lines of the hex 1454 byte dump for a given input source line. If this value is not 1455 specified, it defaults to being the same as the value specified 1456 for `--listing-lhs-width'. If neither switch is used the default 1457 is to one. 1458 1459`--listing-rhs-width=`number'' 1460 Sets the maximum width, in characters, of the source line that is 1461 displayed alongside the hex dump. The default value for this 1462 parameter is 100. The source line is displayed on the right hand 1463 side of the listing output. 1464 1465`--listing-cont-lines=`number'' 1466 Sets the maximum number of continuation lines of hex dump that 1467 will be displayed for a given single line of source input. The 1468 default value is 4. 1469 1470 1471File: as.info, Node: M, Next: MD, Prev: listing, Up: Invoking 1472 14732.9 Assemble in MRI Compatibility Mode: `-M' 1474============================================ 1475 1476The `-M' or `--mri' option selects MRI compatibility mode. This 1477changes the syntax and pseudo-op handling of `as' to make it compatible 1478with the `ASM68K' or the `ASM960' (depending upon the configured 1479target) assembler from Microtec Research. The exact nature of the MRI 1480syntax will not be documented here; see the MRI manuals for more 1481information. Note in particular that the handling of macros and macro 1482arguments is somewhat different. The purpose of this option is to 1483permit assembling existing MRI assembler code using `as'. 1484 1485 The MRI compatibility is not complete. Certain operations of the 1486MRI assembler depend upon its object file format, and can not be 1487supported using other object file formats. Supporting these would 1488require enhancing each object file format individually. These are: 1489 1490 * global symbols in common section 1491 1492 The m68k MRI assembler supports common sections which are merged 1493 by the linker. Other object file formats do not support this. 1494 `as' handles common sections by treating them as a single common 1495 symbol. It permits local symbols to be defined within a common 1496 section, but it can not support global symbols, since it has no 1497 way to describe them. 1498 1499 * complex relocations 1500 1501 The MRI assemblers support relocations against a negated section 1502 address, and relocations which combine the start addresses of two 1503 or more sections. These are not support by other object file 1504 formats. 1505 1506 * `END' pseudo-op specifying start address 1507 1508 The MRI `END' pseudo-op permits the specification of a start 1509 address. This is not supported by other object file formats. The 1510 start address may instead be specified using the `-e' option to 1511 the linker, or in a linker script. 1512 1513 * `IDNT', `.ident' and `NAME' pseudo-ops 1514 1515 The MRI `IDNT', `.ident' and `NAME' pseudo-ops assign a module 1516 name to the output file. This is not supported by other object 1517 file formats. 1518 1519 * `ORG' pseudo-op 1520 1521 The m68k MRI `ORG' pseudo-op begins an absolute section at a given 1522 address. This differs from the usual `as' `.org' pseudo-op, which 1523 changes the location within the current section. Absolute 1524 sections are not supported by other object file formats. The 1525 address of a section may be assigned within a linker script. 1526 1527 There are some other features of the MRI assembler which are not 1528supported by `as', typically either because they are difficult or 1529because they seem of little consequence. Some of these may be 1530supported in future releases. 1531 1532 * EBCDIC strings 1533 1534 EBCDIC strings are not supported. 1535 1536 * packed binary coded decimal 1537 1538 Packed binary coded decimal is not supported. This means that the 1539 `DC.P' and `DCB.P' pseudo-ops are not supported. 1540 1541 * `FEQU' pseudo-op 1542 1543 The m68k `FEQU' pseudo-op is not supported. 1544 1545 * `NOOBJ' pseudo-op 1546 1547 The m68k `NOOBJ' pseudo-op is not supported. 1548 1549 * `OPT' branch control options 1550 1551 The m68k `OPT' branch control options--`B', `BRS', `BRB', `BRL', 1552 and `BRW'--are ignored. `as' automatically relaxes all branches, 1553 whether forward or backward, to an appropriate size, so these 1554 options serve no purpose. 1555 1556 * `OPT' list control options 1557 1558 The following m68k `OPT' list control options are ignored: `C', 1559 `CEX', `CL', `CRE', `E', `G', `I', `M', `MEX', `MC', `MD', `X'. 1560 1561 * other `OPT' options 1562 1563 The following m68k `OPT' options are ignored: `NEST', `O', `OLD', 1564 `OP', `P', `PCO', `PCR', `PCS', `R'. 1565 1566 * `OPT' `D' option is default 1567 1568 The m68k `OPT' `D' option is the default, unlike the MRI assembler. 1569 `OPT NOD' may be used to turn it off. 1570 1571 * `XREF' pseudo-op. 1572 1573 The m68k `XREF' pseudo-op is ignored. 1574 1575 * `.debug' pseudo-op 1576 1577 The i960 `.debug' pseudo-op is not supported. 1578 1579 * `.extended' pseudo-op 1580 1581 The i960 `.extended' pseudo-op is not supported. 1582 1583 * `.list' pseudo-op. 1584 1585 The various options of the i960 `.list' pseudo-op are not 1586 supported. 1587 1588 * `.optimize' pseudo-op 1589 1590 The i960 `.optimize' pseudo-op is not supported. 1591 1592 * `.output' pseudo-op 1593 1594 The i960 `.output' pseudo-op is not supported. 1595 1596 * `.setreal' pseudo-op 1597 1598 The i960 `.setreal' pseudo-op is not supported. 1599 1600 1601 1602File: as.info, Node: MD, Next: o, Prev: M, Up: Invoking 1603 16042.10 Dependency Tracking: `--MD' 1605================================ 1606 1607`as' can generate a dependency file for the file it creates. This file 1608consists of a single rule suitable for `make' describing the 1609dependencies of the main source file. 1610 1611 The rule is written to the file named in its argument. 1612 1613 This feature is used in the automatic updating of makefiles. 1614 1615 1616File: as.info, Node: o, Next: R, Prev: MD, Up: Invoking 1617 16182.11 Name the Object File: `-o' 1619=============================== 1620 1621There is always one object file output when you run `as'. By default 1622it has the name `a.out' (or `b.out', for Intel 960 targets only). You 1623use this option (which takes exactly one filename) to give the object 1624file a different name. 1625 1626 Whatever the object file is called, `as' overwrites any existing 1627file of the same name. 1628 1629 1630File: as.info, Node: R, Next: statistics, Prev: o, Up: Invoking 1631 16322.12 Join Data and Text Sections: `-R' 1633====================================== 1634 1635`-R' tells `as' to write the object file as if all data-section data 1636lives in the text section. This is only done at the very last moment: 1637your binary data are the same, but data section parts are relocated 1638differently. The data section part of your object file is zero bytes 1639long because all its bytes are appended to the text section. (*Note 1640Sections and Relocation: Sections.) 1641 1642 When you specify `-R' it would be possible to generate shorter 1643address displacements (because we do not have to cross between text and 1644data section). We refrain from doing this simply for compatibility with 1645older versions of `as'. In future, `-R' may work this way. 1646 1647 When `as' is configured for COFF or ELF output, this option is only 1648useful if you use sections named `.text' and `.data'. 1649 1650 `-R' is not supported for any of the HPPA targets. Using `-R' 1651generates a warning from `as'. 1652 1653 1654File: as.info, Node: statistics, Next: traditional-format, Prev: R, Up: Invoking 1655 16562.13 Display Assembly Statistics: `--statistics' 1657================================================ 1658 1659Use `--statistics' to display two statistics about the resources used by 1660`as': the maximum amount of space allocated during the assembly (in 1661bytes), and the total execution time taken for the assembly (in CPU 1662seconds). 1663 1664 1665File: as.info, Node: traditional-format, Next: v, Prev: statistics, Up: Invoking 1666 16672.14 Compatible Output: `--traditional-format' 1668============================================== 1669 1670For some targets, the output of `as' is different in some ways from the 1671output of some existing assembler. This switch requests `as' to use 1672the traditional format instead. 1673 1674 For example, it disables the exception frame optimizations which 1675`as' normally does by default on `gcc' output. 1676 1677 1678File: as.info, Node: v, Next: W, Prev: traditional-format, Up: Invoking 1679 16802.15 Announce Version: `-v' 1681=========================== 1682 1683You can find out what version of as is running by including the option 1684`-v' (which you can also spell as `-version') on the command line. 1685 1686 1687File: as.info, Node: W, Next: Z, Prev: v, Up: Invoking 1688 16892.16 Control Warnings: `-W', `--warn', `--no-warn', `--fatal-warnings' 1690====================================================================== 1691 1692`as' should never give a warning or error message when assembling 1693compiler output. But programs written by people often cause `as' to 1694give a warning that a particular assumption was made. All such 1695warnings are directed to the standard error file. 1696 1697 If you use the `-W' and `--no-warn' options, no warnings are issued. 1698This only affects the warning messages: it does not change any 1699particular of how `as' assembles your file. Errors, which stop the 1700assembly, are still reported. 1701 1702 If you use the `--fatal-warnings' option, `as' considers files that 1703generate warnings to be in error. 1704 1705 You can switch these options off again by specifying `--warn', which 1706causes warnings to be output as usual. 1707 1708 1709File: as.info, Node: Z, Prev: W, Up: Invoking 1710 17112.17 Generate Object File in Spite of Errors: `-Z' 1712================================================== 1713 1714After an error message, `as' normally produces no output. If for some 1715reason you are interested in object file output even after `as' gives 1716an error message on your program, use the `-Z' option. If there are 1717any errors, `as' continues anyways, and writes an object file after a 1718final warning message of the form `N errors, M warnings, generating bad 1719object file.' 1720 1721 1722File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top 1723 17243 Syntax 1725******** 1726 1727This chapter describes the machine-independent syntax allowed in a 1728source file. `as' syntax is similar to what many other assemblers use; 1729it is inspired by the BSD 4.2 assembler, except that `as' does not 1730assemble Vax bit-fields. 1731 1732* Menu: 1733 1734* Preprocessing:: Preprocessing 1735* Whitespace:: Whitespace 1736* Comments:: Comments 1737* Symbol Intro:: Symbols 1738* Statements:: Statements 1739* Constants:: Constants 1740 1741 1742File: as.info, Node: Preprocessing, Next: Whitespace, Up: Syntax 1743 17443.1 Preprocessing 1745================= 1746 1747The `as' internal preprocessor: 1748 * adjusts and removes extra whitespace. It leaves one space or tab 1749 before the keywords on a line, and turns any other whitespace on 1750 the line into a single space. 1751 1752 * removes all comments, replacing them with a single space, or an 1753 appropriate number of newlines. 1754 1755 * converts character constants into the appropriate numeric values. 1756 1757 It does not do macro processing, include file handling, or anything 1758else you may get from your C compiler's preprocessor. You can do 1759include file processing with the `.include' directive (*note 1760`.include': Include.). You can use the GNU C compiler driver to get 1761other "CPP" style preprocessing by giving the input file a `.S' suffix. 1762*Note Options Controlling the Kind of Output: (gcc.info)Overall Options. 1763 1764 Excess whitespace, comments, and character constants cannot be used 1765in the portions of the input text that are not preprocessed. 1766 1767 If the first line of an input file is `#NO_APP' or if you use the 1768`-f' option, whitespace and comments are not removed from the input 1769file. Within an input file, you can ask for whitespace and comment 1770removal in specific portions of the by putting a line that says `#APP' 1771before the text that may contain whitespace or comments, and putting a 1772line that says `#NO_APP' after this text. This feature is mainly 1773intend to support `asm' statements in compilers whose output is 1774otherwise free of comments and whitespace. 1775 1776 1777File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax 1778 17793.2 Whitespace 1780============== 1781 1782"Whitespace" is one or more blanks or tabs, in any order. Whitespace 1783is used to separate symbols, and to make programs neater for people to 1784read. Unless within character constants (*note Character Constants: 1785Characters.), any whitespace means the same as exactly one space. 1786 1787 1788File: as.info, Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syntax 1789 17903.3 Comments 1791============ 1792 1793There are two ways of rendering comments to `as'. In both cases the 1794comment is equivalent to one space. 1795 1796 Anything from `/*' through the next `*/' is a comment. This means 1797you may not nest these comments. 1798 1799 /* 1800 The only way to include a newline ('\n') in a comment 1801 is to use this sort of comment. 1802 */ 1803 1804 /* This sort of comment does not nest. */ 1805 1806 Anything from a "line comment" character up to the next newline is 1807considered a comment and is ignored. The line comment character is 1808target specific, and some targets multiple comment characters. Some 1809targets also have line comment characters that only work if they are 1810the first character on a line. Some targets use a sequence of two 1811characters to introduce a line comment. Some targets can also change 1812their line comment characters depending upon command line options that 1813have been used. For more details see the _Syntax_ section in the 1814documentation for individual targets. 1815 1816 If the line comment character is the hash sign (`#') then it still 1817has the special ability to enable and disable preprocessing (*note 1818Preprocessing::) and to specify logical line numbers: 1819 1820 To be compatible with past assemblers, lines that begin with `#' 1821have a special interpretation. Following the `#' should be an absolute 1822expression (*note Expressions::): the logical line number of the _next_ 1823line. Then a string (*note Strings: Strings.) is allowed: if present 1824it is a new logical file name. The rest of the line, if any, should be 1825whitespace. 1826 1827 If the first non-whitespace characters on the line are not numeric, 1828the line is ignored. (Just like a comment.) 1829 1830 # This is an ordinary comment. 1831 # 42-6 "new_file_name" # New logical file name 1832 # This is logical line # 36. 1833 This feature is deprecated, and may disappear from future versions 1834of `as'. 1835 1836 1837File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax 1838 18393.4 Symbols 1840=========== 1841 1842A "symbol" is one or more characters chosen from the set of all letters 1843(both upper and lower case), digits and the three characters `_.$'. On 1844most machines, you can also use `$' in symbol names; exceptions are 1845noted in *note Machine Dependencies::. No symbol may begin with a 1846digit. Case is significant. There is no length limit: all characters 1847are significant. Multibyte characters are supported. Symbols are 1848delimited by characters not in that set, or by the beginning of a file 1849(since the source program must end with a newline, the end of a file is 1850not a possible symbol delimiter). *Note Symbols::. 1851 1852 1853File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax 1854 18553.5 Statements 1856============== 1857 1858A "statement" ends at a newline character (`\n') or a "line separator 1859character". The line separator character is target specific and 1860described in the _Syntax_ section of each target's documentation. Not 1861all targets support a line separator character. The newline or line 1862separator character is considered to be part of the preceding 1863statement. Newlines and separators within character constants are an 1864exception: they do not end statements. 1865 1866 It is an error to end any statement with end-of-file: the last 1867character of any input file should be a newline. 1868 1869 An empty statement is allowed, and may include whitespace. It is 1870ignored. 1871 1872 A statement begins with zero or more labels, optionally followed by a 1873key symbol which determines what kind of statement it is. The key 1874symbol determines the syntax of the rest of the statement. If the 1875symbol begins with a dot `.' then the statement is an assembler 1876directive: typically valid for any computer. If the symbol begins with 1877a letter the statement is an assembly language "instruction": it 1878assembles into a machine language instruction. Different versions of 1879`as' for different computers recognize different instructions. In 1880fact, the same symbol may represent a different instruction in a 1881different computer's assembly language. 1882 1883 A label is a symbol immediately followed by a colon (`:'). 1884Whitespace before a label or after a colon is permitted, but you may not 1885have whitespace between a label's symbol and its colon. *Note Labels::. 1886 1887 For HPPA targets, labels need not be immediately followed by a 1888colon, but the definition of a label must begin in column zero. This 1889also implies that only one label may be defined on each line. 1890 1891 label: .directive followed by something 1892 another_label: # This is an empty statement. 1893 instruction operand_1, operand_2, ... 1894 1895 1896File: as.info, Node: Constants, Prev: Statements, Up: Syntax 1897 18983.6 Constants 1899============= 1900 1901A constant is a number, written so that its value is known by 1902inspection, without knowing any context. Like this: 1903 .byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value. 1904 .ascii "Ring the bell\7" # A string constant. 1905 .octa 0x123456789abcdef0123456789ABCDEF0 # A bignum. 1906 .float 0f-314159265358979323846264338327\ 1907 95028841971.693993751E-40 # - pi, a flonum. 1908 1909* Menu: 1910 1911* Characters:: Character Constants 1912* Numbers:: Number Constants 1913 1914 1915File: as.info, Node: Characters, Next: Numbers, Up: Constants 1916 19173.6.1 Character Constants 1918------------------------- 1919 1920There are two kinds of character constants. A "character" stands for 1921one character in one byte and its value may be used in numeric 1922expressions. String constants (properly called string _literals_) are 1923potentially many bytes and their values may not be used in arithmetic 1924expressions. 1925 1926* Menu: 1927 1928* Strings:: Strings 1929* Chars:: Characters 1930 1931 1932File: as.info, Node: Strings, Next: Chars, Up: Characters 1933 19343.6.1.1 Strings 1935............... 1936 1937A "string" is written between double-quotes. It may contain 1938double-quotes or null characters. The way to get special characters 1939into a string is to "escape" these characters: precede them with a 1940backslash `\' character. For example `\\' represents one backslash: 1941the first `\' is an escape which tells `as' to interpret the second 1942character literally as a backslash (which prevents `as' from 1943recognizing the second `\' as an escape character). The complete list 1944of escapes follows. 1945 1946`\b' 1947 Mnemonic for backspace; for ASCII this is octal code 010. 1948 1949`\f' 1950 Mnemonic for FormFeed; for ASCII this is octal code 014. 1951 1952`\n' 1953 Mnemonic for newline; for ASCII this is octal code 012. 1954 1955`\r' 1956 Mnemonic for carriage-Return; for ASCII this is octal code 015. 1957 1958`\t' 1959 Mnemonic for horizontal Tab; for ASCII this is octal code 011. 1960 1961`\ DIGIT DIGIT DIGIT' 1962 An octal character code. The numeric code is 3 octal digits. For 1963 compatibility with other Unix systems, 8 and 9 are accepted as 1964 digits: for example, `\008' has the value 010, and `\009' the 1965 value 011. 1966 1967`\`x' HEX-DIGITS...' 1968 A hex character code. All trailing hex digits are combined. 1969 Either upper or lower case `x' works. 1970 1971`\\' 1972 Represents one `\' character. 1973 1974`\"' 1975 Represents one `"' character. Needed in strings to represent this 1976 character, because an unescaped `"' would end the string. 1977 1978`\ ANYTHING-ELSE' 1979 Any other character when escaped by `\' gives a warning, but 1980 assembles as if the `\' was not present. The idea is that if you 1981 used an escape sequence you clearly didn't want the literal 1982 interpretation of the following character. However `as' has no 1983 other interpretation, so `as' knows it is giving you the wrong 1984 code and warns you of the fact. 1985 1986 Which characters are escapable, and what those escapes represent, 1987varies widely among assemblers. The current set is what we think the 1988BSD 4.2 assembler recognizes, and is a subset of what most C compilers 1989recognize. If you are in doubt, do not use an escape sequence. 1990 1991 1992File: as.info, Node: Chars, Prev: Strings, Up: Characters 1993 19943.6.1.2 Characters 1995.................. 1996 1997A single character may be written as a single quote immediately 1998followed by that character. The same escapes apply to characters as to 1999strings. So if you want to write the character backslash, you must 2000write `'\\' where the first `\' escapes the second `\'. As you can 2001see, the quote is an acute accent, not a grave accent. A newline 2002immediately following an acute accent is taken as a literal character 2003and does not count as the end of a statement. The value of a character 2004constant in a numeric expression is the machine's byte-wide code for 2005that character. `as' assumes your character code is ASCII: `'A' means 200665, `'B' means 66, and so on. 2007 2008 2009File: as.info, Node: Numbers, Prev: Characters, Up: Constants 2010 20113.6.2 Number Constants 2012---------------------- 2013 2014`as' distinguishes three kinds of numbers according to how they are 2015stored in the target machine. _Integers_ are numbers that would fit 2016into an `int' in the C language. _Bignums_ are integers, but they are 2017stored in more than 32 bits. _Flonums_ are floating point numbers, 2018described below. 2019 2020* Menu: 2021 2022* Integers:: Integers 2023* Bignums:: Bignums 2024* Flonums:: Flonums 2025 2026 2027File: as.info, Node: Integers, Next: Bignums, Up: Numbers 2028 20293.6.2.1 Integers 2030................ 2031 2032A binary integer is `0b' or `0B' followed by zero or more of the binary 2033digits `01'. 2034 2035 An octal integer is `0' followed by zero or more of the octal digits 2036(`01234567'). 2037 2038 A decimal integer starts with a non-zero digit followed by zero or 2039more digits (`0123456789'). 2040 2041 A hexadecimal integer is `0x' or `0X' followed by one or more 2042hexadecimal digits chosen from `0123456789abcdefABCDEF'. 2043 2044 Integers have the usual values. To denote a negative integer, use 2045the prefix operator `-' discussed under expressions (*note Prefix 2046Operators: Prefix Ops.). 2047 2048 2049File: as.info, Node: Bignums, Next: Flonums, Prev: Integers, Up: Numbers 2050 20513.6.2.2 Bignums 2052............... 2053 2054A "bignum" has the same syntax and semantics as an integer except that 2055the number (or its negative) takes more than 32 bits to represent in 2056binary. The distinction is made because in some places integers are 2057permitted while bignums are not. 2058 2059 2060File: as.info, Node: Flonums, Prev: Bignums, Up: Numbers 2061 20623.6.2.3 Flonums 2063............... 2064 2065A "flonum" represents a floating point number. The translation is 2066indirect: a decimal floating point number from the text is converted by 2067`as' to a generic binary floating point number of more than sufficient 2068precision. This generic floating point number is converted to a 2069particular computer's floating point format (or formats) by a portion 2070of `as' specialized to that computer. 2071 2072 A flonum is written by writing (in order) 2073 * The digit `0'. (`0' is optional on the HPPA.) 2074 2075 * A letter, to tell `as' the rest of the number is a flonum. `e' is 2076 recommended. Case is not important. 2077 2078 On the H8/300, Renesas / SuperH SH, and AMD 29K architectures, the 2079 letter must be one of the letters `DFPRSX' (in upper or lower 2080 case). 2081 2082 On the ARC, the letter must be one of the letters `DFRS' (in upper 2083 or lower case). 2084 2085 On the Intel 960 architecture, the letter must be one of the 2086 letters `DFT' (in upper or lower case). 2087 2088 On the HPPA architecture, the letter must be `E' (upper case only). 2089 2090 * An optional sign: either `+' or `-'. 2091 2092 * An optional "integer part": zero or more decimal digits. 2093 2094 * An optional "fractional part": `.' followed by zero or more 2095 decimal digits. 2096 2097 * An optional exponent, consisting of: 2098 2099 * An `E' or `e'. 2100 2101 * Optional sign: either `+' or `-'. 2102 2103 * One or more decimal digits. 2104 2105 2106 At least one of the integer part or the fractional part must be 2107present. The floating point number has the usual base-10 value. 2108 2109 `as' does all processing using integers. Flonums are computed 2110independently of any floating point hardware in the computer running 2111`as'. 2112 2113 2114File: as.info, Node: Sections, Next: Symbols, Prev: Syntax, Up: Top 2115 21164 Sections and Relocation 2117************************* 2118 2119* Menu: 2120 2121* Secs Background:: Background 2122* Ld Sections:: Linker Sections 2123* As Sections:: Assembler Internal Sections 2124* Sub-Sections:: Sub-Sections 2125* bss:: bss Section 2126 2127 2128File: as.info, Node: Secs Background, Next: Ld Sections, Up: Sections 2129 21304.1 Background 2131============== 2132 2133Roughly, a section is a range of addresses, with no gaps; all data "in" 2134those addresses is treated the same for some particular purpose. For 2135example there may be a "read only" section. 2136 2137 The linker `ld' reads many object files (partial programs) and 2138combines their contents to form a runnable program. When `as' emits an 2139object file, the partial program is assumed to start at address 0. 2140`ld' assigns the final addresses for the partial program, so that 2141different partial programs do not overlap. This is actually an 2142oversimplification, but it suffices to explain how `as' uses sections. 2143 2144 `ld' moves blocks of bytes of your program to their run-time 2145addresses. These blocks slide to their run-time addresses as rigid 2146units; their length does not change and neither does the order of bytes 2147within them. Such a rigid unit is called a _section_. Assigning 2148run-time addresses to sections is called "relocation". It includes the 2149task of adjusting mentions of object-file addresses so they refer to 2150the proper run-time addresses. For the H8/300, and for the Renesas / 2151SuperH SH, `as' pads sections if needed to ensure they end on a word 2152(sixteen bit) boundary. 2153 2154 An object file written by `as' has at least three sections, any of 2155which may be empty. These are named "text", "data" and "bss" sections. 2156 2157 When it generates COFF or ELF output, `as' can also generate 2158whatever other named sections you specify using the `.section' 2159directive (*note `.section': Section.). If you do not use any 2160directives that place output in the `.text' or `.data' sections, these 2161sections still exist, but are empty. 2162 2163 When `as' generates SOM or ELF output for the HPPA, `as' can also 2164generate whatever other named sections you specify using the `.space' 2165and `.subspace' directives. See `HP9000 Series 800 Assembly Language 2166Reference Manual' (HP 92432-90001) for details on the `.space' and 2167`.subspace' assembler directives. 2168 2169 Additionally, `as' uses different names for the standard text, data, 2170and bss sections when generating SOM output. Program text is placed 2171into the `$CODE$' section, data into `$DATA$', and BSS into `$BSS$'. 2172 2173 Within the object file, the text section starts at address `0', the 2174data section follows, and the bss section follows the data section. 2175 2176 When generating either SOM or ELF output files on the HPPA, the text 2177section starts at address `0', the data section at address `0x4000000', 2178and the bss section follows the data section. 2179 2180 To let `ld' know which data changes when the sections are relocated, 2181and how to change that data, `as' also writes to the object file 2182details of the relocation needed. To perform relocation `ld' must 2183know, each time an address in the object file is mentioned: 2184 * Where in the object file is the beginning of this reference to an 2185 address? 2186 2187 * How long (in bytes) is this reference? 2188 2189 * Which section does the address refer to? What is the numeric 2190 value of 2191 (ADDRESS) - (START-ADDRESS OF SECTION)? 2192 2193 * Is the reference to an address "Program-Counter relative"? 2194 2195 In fact, every address `as' ever uses is expressed as 2196 (SECTION) + (OFFSET INTO SECTION) 2197 Further, most expressions `as' computes have this section-relative 2198nature. (For some object formats, such as SOM for the HPPA, some 2199expressions are symbol-relative instead.) 2200 2201 In this manual we use the notation {SECNAME N} to mean "offset N 2202into section SECNAME." 2203 2204 Apart from text, data and bss sections you need to know about the 2205"absolute" section. When `ld' mixes partial programs, addresses in the 2206absolute section remain unchanged. For example, address `{absolute 0}' 2207is "relocated" to run-time address 0 by `ld'. Although the linker 2208never arranges two partial programs' data sections with overlapping 2209addresses after linking, _by definition_ their absolute sections must 2210overlap. Address `{absolute 239}' in one part of a program is always 2211the same address when the program is running as address `{absolute 2212239}' in any other part of the program. 2213 2214 The idea of sections is extended to the "undefined" section. Any 2215address whose section is unknown at assembly time is by definition 2216rendered {undefined U}--where U is filled in later. Since numbers are 2217always defined, the only way to generate an undefined address is to 2218mention an undefined symbol. A reference to a named common block would 2219be such a symbol: its value is unknown at assembly time so it has 2220section _undefined_. 2221 2222 By analogy the word _section_ is used to describe groups of sections 2223in the linked program. `ld' puts all partial programs' text sections 2224in contiguous addresses in the linked program. It is customary to 2225refer to the _text section_ of a program, meaning all the addresses of 2226all partial programs' text sections. Likewise for data and bss 2227sections. 2228 2229 Some sections are manipulated by `ld'; others are invented for use 2230of `as' and have no meaning except during assembly. 2231 2232 2233File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections 2234 22354.2 Linker Sections 2236=================== 2237 2238`ld' deals with just four kinds of sections, summarized below. 2239 2240*named sections* 2241*text section* 2242*data section* 2243 These sections hold your program. `as' and `ld' treat them as 2244 separate but equal sections. Anything you can say of one section 2245 is true of another. When the program is running, however, it is 2246 customary for the text section to be unalterable. The text 2247 section is often shared among processes: it contains instructions, 2248 constants and the like. The data section of a running program is 2249 usually alterable: for example, C variables would be stored in the 2250 data section. 2251 2252*bss section* 2253 This section contains zeroed bytes when your program begins 2254 running. It is used to hold uninitialized variables or common 2255 storage. The length of each partial program's bss section is 2256 important, but because it starts out containing zeroed bytes there 2257 is no need to store explicit zero bytes in the object file. The 2258 bss section was invented to eliminate those explicit zeros from 2259 object files. 2260 2261*absolute section* 2262 Address 0 of this section is always "relocated" to runtime address 2263 0. This is useful if you want to refer to an address that `ld' 2264 must not change when relocating. In this sense we speak of 2265 absolute addresses being "unrelocatable": they do not change 2266 during relocation. 2267 2268*undefined section* 2269 This "section" is a catch-all for address references to objects 2270 not in the preceding sections. 2271 2272 An idealized example of three relocatable sections follows. The 2273example uses the traditional section names `.text' and `.data'. Memory 2274addresses are on the horizontal axis. 2275 2276 +-----+----+--+ 2277 partial program # 1: |ttttt|dddd|00| 2278 +-----+----+--+ 2279 2280 text data bss 2281 seg. seg. seg. 2282 2283 +---+---+---+ 2284 partial program # 2: |TTT|DDD|000| 2285 +---+---+---+ 2286 2287 +--+---+-----+--+----+---+-----+~~ 2288 linked program: | |TTT|ttttt| |dddd|DDD|00000| 2289 +--+---+-----+--+----+---+-----+~~ 2290 2291 addresses: 0 ... 2292 2293 2294File: as.info, Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: Sections 2295 22964.3 Assembler Internal Sections 2297=============================== 2298 2299These sections are meant only for the internal use of `as'. They have 2300no meaning at run-time. You do not really need to know about these 2301sections for most purposes; but they can be mentioned in `as' warning 2302messages, so it might be helpful to have an idea of their meanings to 2303`as'. These sections are used to permit the value of every expression 2304in your assembly language program to be a section-relative address. 2305 2306ASSEMBLER-INTERNAL-LOGIC-ERROR! 2307 An internal assembler logic error has been found. This means 2308 there is a bug in the assembler. 2309 2310expr section 2311 The assembler stores complex expression internally as combinations 2312 of symbols. When it needs to represent an expression as a symbol, 2313 it puts it in the expr section. 2314 2315 2316File: as.info, Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Sections 2317 23184.4 Sub-Sections 2319================ 2320 2321Assembled bytes conventionally fall into two sections: text and data. 2322You may have separate groups of data in named sections that you want to 2323end up near to each other in the object file, even though they are not 2324contiguous in the assembler source. `as' allows you to use 2325"subsections" for this purpose. Within each section, there can be 2326numbered subsections with values from 0 to 8192. Objects assembled 2327into the same subsection go into the object file together with other 2328objects in the same subsection. For example, a compiler might want to 2329store constants in the text section, but might not want to have them 2330interspersed with the program being assembled. In this case, the 2331compiler could issue a `.text 0' before each section of code being 2332output, and a `.text 1' before each group of constants being output. 2333 2334Subsections are optional. If you do not use subsections, everything 2335goes in subsection number zero. 2336 2337 Each subsection is zero-padded up to a multiple of four bytes. 2338(Subsections may be padded a different amount on different flavors of 2339`as'.) 2340 2341 Subsections appear in your object file in numeric order, lowest 2342numbered to highest. (All this to be compatible with other people's 2343assemblers.) The object file contains no representation of 2344subsections; `ld' and other programs that manipulate object files see 2345no trace of them. They just see all your text subsections as a text 2346section, and all your data subsections as a data section. 2347 2348 To specify which subsection you want subsequent statements assembled 2349into, use a numeric argument to specify it, in a `.text EXPRESSION' or 2350a `.data EXPRESSION' statement. When generating COFF output, you can 2351also use an extra subsection argument with arbitrary named sections: 2352`.section NAME, EXPRESSION'. When generating ELF output, you can also 2353use the `.subsection' directive (*note SubSection::) to specify a 2354subsection: `.subsection EXPRESSION'. EXPRESSION should be an absolute 2355expression (*note Expressions::). If you just say `.text' then `.text 23560' is assumed. Likewise `.data' means `.data 0'. Assembly begins in 2357`text 0'. For instance: 2358 .text 0 # The default subsection is text 0 anyway. 2359 .ascii "This lives in the first text subsection. *" 2360 .text 1 2361 .ascii "But this lives in the second text subsection." 2362 .data 0 2363 .ascii "This lives in the data section," 2364 .ascii "in the first data subsection." 2365 .text 0 2366 .ascii "This lives in the first text section," 2367 .ascii "immediately following the asterisk (*)." 2368 2369 Each section has a "location counter" incremented by one for every 2370byte assembled into that section. Because subsections are merely a 2371convenience restricted to `as' there is no concept of a subsection 2372location counter. There is no way to directly manipulate a location 2373counter--but the `.align' directive changes it, and any label 2374definition captures its current value. The location counter of the 2375section where statements are being assembled is said to be the "active" 2376location counter. 2377 2378 2379File: as.info, Node: bss, Prev: Sub-Sections, Up: Sections 2380 23814.5 bss Section 2382=============== 2383 2384The bss section is used for local common variable storage. You may 2385allocate address space in the bss section, but you may not dictate data 2386to load into it before your program executes. When your program starts 2387running, all the contents of the bss section are zeroed bytes. 2388 2389 The `.lcomm' pseudo-op defines a symbol in the bss section; see 2390*note `.lcomm': Lcomm. 2391 2392 The `.comm' pseudo-op may be used to declare a common symbol, which 2393is another form of uninitialized symbol; see *note `.comm': Comm. 2394 2395 When assembling for a target which supports multiple sections, such 2396as ELF or COFF, you may switch into the `.bss' section and define 2397symbols as usual; see *note `.section': Section. You may only assemble 2398zero values into the section. Typically the section will only contain 2399symbol definitions and `.skip' directives (*note `.skip': Skip.). 2400 2401 2402File: as.info, Node: Symbols, Next: Expressions, Prev: Sections, Up: Top 2403 24045 Symbols 2405********* 2406 2407Symbols are a central concept: the programmer uses symbols to name 2408things, the linker uses symbols to link, and the debugger uses symbols 2409to debug. 2410 2411 _Warning:_ `as' does not place symbols in the object file in the 2412 same order they were declared. This may break some debuggers. 2413 2414* Menu: 2415 2416* Labels:: Labels 2417* Setting Symbols:: Giving Symbols Other Values 2418* Symbol Names:: Symbol Names 2419* Dot:: The Special Dot Symbol 2420* Symbol Attributes:: Symbol Attributes 2421 2422 2423File: as.info, Node: Labels, Next: Setting Symbols, Up: Symbols 2424 24255.1 Labels 2426========== 2427 2428A "label" is written as a symbol immediately followed by a colon `:'. 2429The symbol then represents the current value of the active location 2430counter, and is, for example, a suitable instruction operand. You are 2431warned if you use the same symbol to represent two different locations: 2432the first definition overrides any other definitions. 2433 2434 On the HPPA, the usual form for a label need not be immediately 2435followed by a colon, but instead must start in column zero. Only one 2436label may be defined on a single line. To work around this, the HPPA 2437version of `as' also provides a special directive `.label' for defining 2438labels more flexibly. 2439 2440 2441File: as.info, Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: Symbols 2442 24435.2 Giving Symbols Other Values 2444=============================== 2445 2446A symbol can be given an arbitrary value by writing a symbol, followed 2447by an equals sign `=', followed by an expression (*note Expressions::). 2448This is equivalent to using the `.set' directive. *Note `.set': Set. 2449In the same way, using a double equals sign `='`=' here represents an 2450equivalent of the `.eqv' directive. *Note `.eqv': Eqv. 2451 2452 Blackfin does not support symbol assignment with `='. 2453 2454 2455File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols 2456 24575.3 Symbol Names 2458================ 2459 2460Symbol names begin with a letter or with one of `._'. On most 2461machines, you can also use `$' in symbol names; exceptions are noted in 2462*note Machine Dependencies::. That character may be followed by any 2463string of digits, letters, dollar signs (unless otherwise noted for a 2464particular target machine), and underscores. 2465 2466Case of letters is significant: `foo' is a different symbol name than 2467`Foo'. 2468 2469 Multibyte characters are supported. To generate a symbol name 2470containing multibyte characters enclose it within double quotes and use 2471escape codes. cf *Note Strings::. Generating a multibyte symbol name 2472from a label is not currently supported. 2473 2474 Each symbol has exactly one name. Each name in an assembly language 2475program refers to exactly one symbol. You may use that symbol name any 2476number of times in a program. 2477 2478Local Symbol Names 2479------------------ 2480 2481A local symbol is any symbol beginning with certain local label 2482prefixes. By default, the local label prefix is `.L' for ELF systems or 2483`L' for traditional a.out systems, but each target may have its own set 2484of local label prefixes. On the HPPA local symbols begin with `L$'. 2485 2486 Local symbols are defined and used within the assembler, but they are 2487normally not saved in object files. Thus, they are not visible when 2488debugging. You may use the `-L' option (*note Include Local Symbols: 2489`-L': L.) to retain the local symbols in the object files. 2490 2491Local Labels 2492------------ 2493 2494Local labels help compilers and programmers use names temporarily. 2495They create symbols which are guaranteed to be unique over the entire 2496scope of the input source code and which can be referred to by a simple 2497notation. To define a local label, write a label of the form `N:' 2498(where N represents any positive integer). To refer to the most recent 2499previous definition of that label write `Nb', using the same number as 2500when you defined the label. To refer to the next definition of a local 2501label, write `Nf'--the `b' stands for "backwards" and the `f' stands 2502for "forwards". 2503 2504 There is no restriction on how you can use these labels, and you can 2505reuse them too. So that it is possible to repeatedly define the same 2506local label (using the same number `N'), although you can only refer to 2507the most recently defined local label of that number (for a backwards 2508reference) or the next definition of a specific local label for a 2509forward reference. It is also worth noting that the first 10 local 2510labels (`0:'...`9:') are implemented in a slightly more efficient 2511manner than the others. 2512 2513 Here is an example: 2514 2515 1: branch 1f 2516 2: branch 1b 2517 1: branch 2f 2518 2: branch 1b 2519 2520 Which is the equivalent of: 2521 2522 label_1: branch label_3 2523 label_2: branch label_1 2524 label_3: branch label_4 2525 label_4: branch label_3 2526 2527 Local label names are only a notational device. They are immediately 2528transformed into more conventional symbol names before the assembler 2529uses them. The symbol names are stored in the symbol table, appear in 2530error messages, and are optionally emitted to the object file. The 2531names are constructed using these parts: 2532 2533`_local label prefix_' 2534 All local symbols begin with the system-specific local label 2535 prefix. Normally both `as' and `ld' forget symbols that start 2536 with the local label prefix. These labels are used for symbols 2537 you are never intended to see. If you use the `-L' option then 2538 `as' retains these symbols in the object file. If you also 2539 instruct `ld' to retain these symbols, you may use them in 2540 debugging. 2541 2542`NUMBER' 2543 This is the number that was used in the local label definition. 2544 So if the label is written `55:' then the number is `55'. 2545 2546`C-B' 2547 This unusual character is included so you do not accidentally 2548 invent a symbol of the same name. The character has ASCII value 2549 of `\002' (control-B). 2550 2551`_ordinal number_' 2552 This is a serial number to keep the labels distinct. The first 2553 definition of `0:' gets the number `1'. The 15th definition of 2554 `0:' gets the number `15', and so on. Likewise the first 2555 definition of `1:' gets the number `1' and its 15th definition 2556 gets `15' as well. 2557 2558 So for example, the first `1:' may be named `.L1C-B1', and the 44th 2559`3:' may be named `.L3C-B44'. 2560 2561Dollar Local Labels 2562------------------- 2563 2564`as' also supports an even more local form of local labels called 2565dollar labels. These labels go out of scope (i.e., they become 2566undefined) as soon as a non-local label is defined. Thus they remain 2567valid for only a small region of the input source code. Normal local 2568labels, by contrast, remain in scope for the entire file, or until they 2569are redefined by another occurrence of the same local label. 2570 2571 Dollar labels are defined in exactly the same way as ordinary local 2572labels, except that they have a dollar sign suffix to their numeric 2573value, e.g., `55$:'. 2574 2575 They can also be distinguished from ordinary local labels by their 2576transformed names which use ASCII character `\001' (control-A) as the 2577magic character to distinguish them from ordinary labels. For example, 2578the fifth definition of `6$' may be named `.L6C-A5'. 2579 2580 2581File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols 2582 25835.4 The Special Dot Symbol 2584========================== 2585 2586The special symbol `.' refers to the current address that `as' is 2587assembling into. Thus, the expression `melvin: .long .' defines 2588`melvin' to contain its own address. Assigning a value to `.' is 2589treated the same as a `.org' directive. Thus, the expression `.=.+4' 2590is the same as saying `.space 4'. 2591 2592 2593File: as.info, Node: Symbol Attributes, Prev: Dot, Up: Symbols 2594 25955.5 Symbol Attributes 2596===================== 2597 2598Every symbol has, as well as its name, the attributes "Value" and 2599"Type". Depending on output format, symbols can also have auxiliary 2600attributes. 2601 2602 If you use a symbol without defining it, `as' assumes zero for all 2603these attributes, and probably won't warn you. This makes the symbol 2604an externally defined symbol, which is generally what you would want. 2605 2606* Menu: 2607 2608* Symbol Value:: Value 2609* Symbol Type:: Type 2610 2611 2612* a.out Symbols:: Symbol Attributes: `a.out' 2613 2614* COFF Symbols:: Symbol Attributes for COFF 2615 2616* SOM Symbols:: Symbol Attributes for SOM 2617 2618 2619File: as.info, Node: Symbol Value, Next: Symbol Type, Up: Symbol Attributes 2620 26215.5.1 Value 2622----------- 2623 2624The value of a symbol is (usually) 32 bits. For a symbol which labels a 2625location in the text, data, bss or absolute sections the value is the 2626number of addresses from the start of that section to the label. 2627Naturally for text, data and bss sections the value of a symbol changes 2628as `ld' changes section base addresses during linking. Absolute 2629symbols' values do not change during linking: that is why they are 2630called absolute. 2631 2632 The value of an undefined symbol is treated in a special way. If it 2633is 0 then the symbol is not defined in this assembler source file, and 2634`ld' tries to determine its value from other files linked into the same 2635program. You make this kind of symbol simply by mentioning a symbol 2636name without defining it. A non-zero value represents a `.comm' common 2637declaration. The value is how much common storage to reserve, in bytes 2638(addresses). The symbol refers to the first address of the allocated 2639storage. 2640 2641 2642File: as.info, Node: Symbol Type, Next: a.out Symbols, Prev: Symbol Value, Up: Symbol Attributes 2643 26445.5.2 Type 2645---------- 2646 2647The type attribute of a symbol contains relocation (section) 2648information, any flag settings indicating that a symbol is external, and 2649(optionally), other information for linkers and debuggers. The exact 2650format depends on the object-code output format in use. 2651 2652 2653File: as.info, Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes 2654 26555.5.3 Symbol Attributes: `a.out' 2656-------------------------------- 2657 2658* Menu: 2659 2660* Symbol Desc:: Descriptor 2661* Symbol Other:: Other 2662 2663 2664File: as.info, Node: Symbol Desc, Next: Symbol Other, Up: a.out Symbols 2665 26665.5.3.1 Descriptor 2667.................. 2668 2669This is an arbitrary 16-bit value. You may establish a symbol's 2670descriptor value by using a `.desc' statement (*note `.desc': Desc.). 2671A descriptor value means nothing to `as'. 2672 2673 2674File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols 2675 26765.5.3.2 Other 2677............. 2678 2679This is an arbitrary 8-bit value. It means nothing to `as'. 2680 2681 2682File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes 2683 26845.5.4 Symbol Attributes for COFF 2685-------------------------------- 2686 2687The COFF format supports a multitude of auxiliary symbol attributes; 2688like the primary symbol attributes, they are set between `.def' and 2689`.endef' directives. 2690 26915.5.4.1 Primary Attributes 2692.......................... 2693 2694The symbol name is set with `.def'; the value and type, respectively, 2695with `.val' and `.type'. 2696 26975.5.4.2 Auxiliary Attributes 2698............................ 2699 2700The `as' directives `.dim', `.line', `.scl', `.size', `.tag', and 2701`.weak' can generate auxiliary symbol table information for COFF. 2702 2703 2704File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes 2705 27065.5.5 Symbol Attributes for SOM 2707------------------------------- 2708 2709The SOM format for the HPPA supports a multitude of symbol attributes 2710set with the `.EXPORT' and `.IMPORT' directives. 2711 2712 The attributes are described in `HP9000 Series 800 Assembly Language 2713Reference Manual' (HP 92432-90001) under the `IMPORT' and `EXPORT' 2714assembler directive documentation. 2715 2716 2717File: as.info, Node: Expressions, Next: Pseudo Ops, Prev: Symbols, Up: Top 2718 27196 Expressions 2720************* 2721 2722An "expression" specifies an address or numeric value. Whitespace may 2723precede and/or follow an expression. 2724 2725 The result of an expression must be an absolute number, or else an 2726offset into a particular section. If an expression is not absolute, 2727and there is not enough information when `as' sees the expression to 2728know its section, a second pass over the source program might be 2729necessary to interpret the expression--but the second pass is currently 2730not implemented. `as' aborts with an error message in this situation. 2731 2732* Menu: 2733 2734* Empty Exprs:: Empty Expressions 2735* Integer Exprs:: Integer Expressions 2736 2737 2738File: as.info, Node: Empty Exprs, Next: Integer Exprs, Up: Expressions 2739 27406.1 Empty Expressions 2741===================== 2742 2743An empty expression has no value: it is just whitespace or null. 2744Wherever an absolute expression is required, you may omit the 2745expression, and `as' assumes a value of (absolute) 0. This is 2746compatible with other assemblers. 2747 2748 2749File: as.info, Node: Integer Exprs, Prev: Empty Exprs, Up: Expressions 2750 27516.2 Integer Expressions 2752======================= 2753 2754An "integer expression" is one or more _arguments_ delimited by 2755_operators_. 2756 2757* Menu: 2758 2759* Arguments:: Arguments 2760* Operators:: Operators 2761* Prefix Ops:: Prefix Operators 2762* Infix Ops:: Infix Operators 2763 2764 2765File: as.info, Node: Arguments, Next: Operators, Up: Integer Exprs 2766 27676.2.1 Arguments 2768--------------- 2769 2770"Arguments" are symbols, numbers or subexpressions. In other contexts 2771arguments are sometimes called "arithmetic operands". In this manual, 2772to avoid confusing them with the "instruction operands" of the machine 2773language, we use the term "argument" to refer to parts of expressions 2774only, reserving the word "operand" to refer only to machine instruction 2775operands. 2776 2777 Symbols are evaluated to yield {SECTION NNN} where SECTION is one of 2778text, data, bss, absolute, or undefined. NNN is a signed, 2's 2779complement 32 bit integer. 2780 2781 Numbers are usually integers. 2782 2783 A number can be a flonum or bignum. In this case, you are warned 2784that only the low order 32 bits are used, and `as' pretends these 32 2785bits are an integer. You may write integer-manipulating instructions 2786that act on exotic constants, compatible with other assemblers. 2787 2788 Subexpressions are a left parenthesis `(' followed by an integer 2789expression, followed by a right parenthesis `)'; or a prefix operator 2790followed by an argument. 2791 2792 2793File: as.info, Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integer Exprs 2794 27956.2.2 Operators 2796--------------- 2797 2798"Operators" are arithmetic functions, like `+' or `%'. Prefix 2799operators are followed by an argument. Infix operators appear between 2800their arguments. Operators may be preceded and/or followed by 2801whitespace. 2802 2803 2804File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs 2805 28066.2.3 Prefix Operator 2807--------------------- 2808 2809`as' has the following "prefix operators". They each take one 2810argument, which must be absolute. 2811 2812`-' 2813 "Negation". Two's complement negation. 2814 2815`~' 2816 "Complementation". Bitwise not. 2817 2818 2819File: as.info, Node: Infix Ops, Prev: Prefix Ops, Up: Integer Exprs 2820 28216.2.4 Infix Operators 2822--------------------- 2823 2824"Infix operators" take two arguments, one on either side. Operators 2825have precedence, but operations with equal precedence are performed left 2826to right. Apart from `+' or `-', both arguments must be absolute, and 2827the result is absolute. 2828 2829 1. Highest Precedence 2830 2831 `*' 2832 "Multiplication". 2833 2834 `/' 2835 "Division". Truncation is the same as the C operator `/' 2836 2837 `%' 2838 "Remainder". 2839 2840 `<<' 2841 "Shift Left". Same as the C operator `<<'. 2842 2843 `>>' 2844 "Shift Right". Same as the C operator `>>'. 2845 2846 2. Intermediate precedence 2847 2848 `|' 2849 "Bitwise Inclusive Or". 2850 2851 `&' 2852 "Bitwise And". 2853 2854 `^' 2855 "Bitwise Exclusive Or". 2856 2857 `!' 2858 "Bitwise Or Not". 2859 2860 3. Low Precedence 2861 2862 `+' 2863 "Addition". If either argument is absolute, the result has 2864 the section of the other argument. You may not add together 2865 arguments from different sections. 2866 2867 `-' 2868 "Subtraction". If the right argument is absolute, the result 2869 has the section of the left argument. If both arguments are 2870 in the same section, the result is absolute. You may not 2871 subtract arguments from different sections. 2872 2873 `==' 2874 "Is Equal To" 2875 2876 `<>' 2877 `!=' 2878 "Is Not Equal To" 2879 2880 `<' 2881 "Is Less Than" 2882 2883 `>' 2884 "Is Greater Than" 2885 2886 `>=' 2887 "Is Greater Than Or Equal To" 2888 2889 `<=' 2890 "Is Less Than Or Equal To" 2891 2892 The comparison operators can be used as infix operators. A 2893 true results has a value of -1 whereas a false result has a 2894 value of 0. Note, these operators perform signed 2895 comparisons. 2896 2897 4. Lowest Precedence 2898 2899 `&&' 2900 "Logical And". 2901 2902 `||' 2903 "Logical Or". 2904 2905 These two logical operations can be used to combine the 2906 results of sub expressions. Note, unlike the comparison 2907 operators a true result returns a value of 1 but a false 2908 results does still return 0. Also note that the logical or 2909 operator has a slightly lower precedence than logical and. 2910 2911 2912 In short, it's only meaningful to add or subtract the _offsets_ in an 2913address; you can only have a defined section in one of the two 2914arguments. 2915 2916 2917File: as.info, Node: Pseudo Ops, Next: Object Attributes, Prev: Expressions, Up: Top 2918 29197 Assembler Directives 2920********************** 2921 2922All assembler directives have names that begin with a period (`.'). 2923The rest of the name is letters, usually in lower case. 2924 2925 This chapter discusses directives that are available regardless of 2926the target machine configuration for the GNU assembler. Some machine 2927configurations provide additional directives. *Note Machine 2928Dependencies::. 2929 2930* Menu: 2931 2932* Abort:: `.abort' 2933 2934* ABORT (COFF):: `.ABORT' 2935 2936* Align:: `.align ABS-EXPR , ABS-EXPR' 2937* Altmacro:: `.altmacro' 2938* Ascii:: `.ascii "STRING"'... 2939* Asciz:: `.asciz "STRING"'... 2940* Balign:: `.balign ABS-EXPR , ABS-EXPR' 2941* Bundle directives:: `.bundle_align_mode ABS-EXPR', `.bundle_lock', `.bundle_unlock' 2942* Byte:: `.byte EXPRESSIONS' 2943* CFI directives:: `.cfi_startproc [simple]', `.cfi_endproc', etc. 2944* Comm:: `.comm SYMBOL , LENGTH ' 2945* Data:: `.data SUBSECTION' 2946 2947* Def:: `.def NAME' 2948 2949* Desc:: `.desc SYMBOL, ABS-EXPRESSION' 2950 2951* Dim:: `.dim' 2952 2953* Double:: `.double FLONUMS' 2954* Eject:: `.eject' 2955* Else:: `.else' 2956* Elseif:: `.elseif' 2957* End:: `.end' 2958 2959* Endef:: `.endef' 2960 2961* Endfunc:: `.endfunc' 2962* Endif:: `.endif' 2963* Equ:: `.equ SYMBOL, EXPRESSION' 2964* Equiv:: `.equiv SYMBOL, EXPRESSION' 2965* Eqv:: `.eqv SYMBOL, EXPRESSION' 2966* Err:: `.err' 2967* Error:: `.error STRING' 2968* Exitm:: `.exitm' 2969* Extern:: `.extern' 2970* Fail:: `.fail' 2971* File:: `.file' 2972* Fill:: `.fill REPEAT , SIZE , VALUE' 2973* Float:: `.float FLONUMS' 2974* Func:: `.func' 2975* Global:: `.global SYMBOL', `.globl SYMBOL' 2976 2977* Gnu_attribute:: `.gnu_attribute TAG,VALUE' 2978* Hidden:: `.hidden NAMES' 2979 2980* hword:: `.hword EXPRESSIONS' 2981* Ident:: `.ident' 2982* If:: `.if ABSOLUTE EXPRESSION' 2983* Incbin:: `.incbin "FILE"[,SKIP[,COUNT]]' 2984* Include:: `.include "FILE"' 2985* Int:: `.int EXPRESSIONS' 2986 2987* Internal:: `.internal NAMES' 2988 2989* Irp:: `.irp SYMBOL,VALUES'... 2990* Irpc:: `.irpc SYMBOL,VALUES'... 2991* Lcomm:: `.lcomm SYMBOL , LENGTH' 2992* Lflags:: `.lflags' 2993 2994* Line:: `.line LINE-NUMBER' 2995 2996* Linkonce:: `.linkonce [TYPE]' 2997* List:: `.list' 2998* Ln:: `.ln LINE-NUMBER' 2999* Loc:: `.loc FILENO LINENO' 3000* Loc_mark_labels:: `.loc_mark_labels ENABLE' 3001 3002* Local:: `.local NAMES' 3003 3004* Long:: `.long EXPRESSIONS' 3005 3006* Macro:: `.macro NAME ARGS'... 3007* MRI:: `.mri VAL' 3008* Noaltmacro:: `.noaltmacro' 3009* Nolist:: `.nolist' 3010* Octa:: `.octa BIGNUMS' 3011* Offset:: `.offset LOC' 3012* Org:: `.org NEW-LC, FILL' 3013* P2align:: `.p2align ABS-EXPR, ABS-EXPR, ABS-EXPR' 3014 3015* PopSection:: `.popsection' 3016* Previous:: `.previous' 3017 3018* Print:: `.print STRING' 3019 3020* Protected:: `.protected NAMES' 3021 3022* Psize:: `.psize LINES, COLUMNS' 3023* Purgem:: `.purgem NAME' 3024 3025* PushSection:: `.pushsection NAME' 3026 3027* Quad:: `.quad BIGNUMS' 3028* Reloc:: `.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 3029* Rept:: `.rept COUNT' 3030* Sbttl:: `.sbttl "SUBHEADING"' 3031 3032* Scl:: `.scl CLASS' 3033 3034* Section:: `.section NAME[, FLAGS]' 3035 3036* Set:: `.set SYMBOL, EXPRESSION' 3037* Short:: `.short EXPRESSIONS' 3038* Single:: `.single FLONUMS' 3039 3040* Size:: `.size [NAME , EXPRESSION]' 3041 3042* Skip:: `.skip SIZE , FILL' 3043 3044* Sleb128:: `.sleb128 EXPRESSIONS' 3045 3046* Space:: `.space SIZE , FILL' 3047 3048* Stab:: `.stabd, .stabn, .stabs' 3049 3050* String:: `.string "STR"', `.string8 "STR"', `.string16 "STR"', `.string32 "STR"', `.string64 "STR"' 3051* Struct:: `.struct EXPRESSION' 3052 3053* SubSection:: `.subsection' 3054* Symver:: `.symver NAME,NAME2@NODENAME' 3055 3056 3057* Tag:: `.tag STRUCTNAME' 3058 3059* Text:: `.text SUBSECTION' 3060* Title:: `.title "HEADING"' 3061 3062* Type:: `.type <INT | NAME , TYPE DESCRIPTION>' 3063 3064* Uleb128:: `.uleb128 EXPRESSIONS' 3065 3066* Val:: `.val ADDR' 3067 3068 3069* Version:: `.version "STRING"' 3070* VTableEntry:: `.vtable_entry TABLE, OFFSET' 3071* VTableInherit:: `.vtable_inherit CHILD, PARENT' 3072 3073* Warning:: `.warning STRING' 3074* Weak:: `.weak NAMES' 3075* Weakref:: `.weakref ALIAS, SYMBOL' 3076* Word:: `.word EXPRESSIONS' 3077* Deprecated:: Deprecated Directives 3078 3079 3080File: as.info, Node: Abort, Next: ABORT (COFF), Up: Pseudo Ops 3081 30827.1 `.abort' 3083============ 3084 3085This directive stops the assembly immediately. It is for compatibility 3086with other assemblers. The original idea was that the assembly 3087language source would be piped into the assembler. If the sender of 3088the source quit, it could use this directive tells `as' to quit also. 3089One day `.abort' will not be supported. 3090 3091 3092File: as.info, Node: ABORT (COFF), Next: Align, Prev: Abort, Up: Pseudo Ops 3093 30947.2 `.ABORT' (COFF) 3095=================== 3096 3097When producing COFF output, `as' accepts this directive as a synonym 3098for `.abort'. 3099 3100 3101File: as.info, Node: Align, Next: Altmacro, Prev: ABORT (COFF), Up: Pseudo Ops 3102 31037.3 `.align ABS-EXPR, ABS-EXPR, ABS-EXPR' 3104========================================= 3105 3106Pad the location counter (in the current subsection) to a particular 3107storage boundary. The first expression (which must be absolute) is the 3108alignment required, as described below. 3109 3110 The second expression (also absolute) gives the fill value to be 3111stored in the padding bytes. It (and the comma) may be omitted. If it 3112is omitted, the padding bytes are normally zero. However, on some 3113systems, if the section is marked as containing code and the fill value 3114is omitted, the space is filled with no-op instructions. 3115 3116 The third expression is also absolute, and is also optional. If it 3117is present, it is the maximum number of bytes that should be skipped by 3118this alignment directive. If doing the alignment would require 3119skipping more bytes than the specified maximum, then the alignment is 3120not done at all. You can omit the fill value (the second argument) 3121entirely by simply using two commas after the required alignment; this 3122can be useful if you want the alignment to be filled with no-op 3123instructions when appropriate. 3124 3125 The way the required alignment is specified varies from system to 3126system. For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32, 3127s390, sparc, tic4x, tic80 and xtensa, the first expression is the 3128alignment request in bytes. For example `.align 8' advances the 3129location counter until it is a multiple of 8. If the location counter 3130is already a multiple of 8, no change is needed. For the tic54x, the 3131first expression is the alignment request in words. 3132 3133 For other systems, including ppc, i386 using a.out format, arm and 3134strongarm, it is the number of low-order zero bits the location counter 3135must have after advancement. For example `.align 3' advances the 3136location counter until it a multiple of 8. If the location counter is 3137already a multiple of 8, no change is needed. 3138 3139 This inconsistency is due to the different behaviors of the various 3140native assemblers for these systems which GAS must emulate. GAS also 3141provides `.balign' and `.p2align' directives, described later, which 3142have a consistent behavior across all architectures (but are specific 3143to GAS). 3144 3145 3146File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops 3147 31487.4 `.altmacro' 3149=============== 3150 3151Enable alternate macro mode, enabling: 3152 3153`LOCAL NAME [ , ... ]' 3154 One additional directive, `LOCAL', is available. It is used to 3155 generate a string replacement for each of the NAME arguments, and 3156 replace any instances of NAME in each macro expansion. The 3157 replacement string is unique in the assembly, and different for 3158 each separate macro expansion. `LOCAL' allows you to write macros 3159 that define symbols, without fear of conflict between separate 3160 macro expansions. 3161 3162`String delimiters' 3163 You can write strings delimited in these other ways besides 3164 `"STRING"': 3165 3166 `'STRING'' 3167 You can delimit strings with single-quote characters. 3168 3169 `<STRING>' 3170 You can delimit strings with matching angle brackets. 3171 3172`single-character string escape' 3173 To include any single character literally in a string (even if the 3174 character would otherwise have some special meaning), you can 3175 prefix the character with `!' (an exclamation mark). For example, 3176 you can write `<4.3 !> 5.4!!>' to get the literal text `4.3 > 3177 5.4!'. 3178 3179`Expression results as strings' 3180 You can write `%EXPR' to evaluate the expression EXPR and use the 3181 result as a string. 3182 3183 3184File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops 3185 31867.5 `.ascii "STRING"'... 3187======================== 3188 3189`.ascii' expects zero or more string literals (*note Strings::) 3190separated by commas. It assembles each string (with no automatic 3191trailing zero byte) into consecutive addresses. 3192 3193 3194File: as.info, Node: Asciz, Next: Balign, Prev: Ascii, Up: Pseudo Ops 3195 31967.6 `.asciz "STRING"'... 3197======================== 3198 3199`.asciz' is just like `.ascii', but each string is followed by a zero 3200byte. The "z" in `.asciz' stands for "zero". 3201 3202 3203File: as.info, Node: Balign, Next: Bundle directives, Prev: Asciz, Up: Pseudo Ops 3204 32057.7 `.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' 3206============================================== 3207 3208Pad the location counter (in the current subsection) to a particular 3209storage boundary. The first expression (which must be absolute) is the 3210alignment request in bytes. For example `.balign 8' advances the 3211location counter until it is a multiple of 8. If the location counter 3212is already a multiple of 8, no change is needed. 3213 3214 The second expression (also absolute) gives the fill value to be 3215stored in the padding bytes. It (and the comma) may be omitted. If it 3216is omitted, the padding bytes are normally zero. However, on some 3217systems, if the section is marked as containing code and the fill value 3218is omitted, the space is filled with no-op instructions. 3219 3220 The third expression is also absolute, and is also optional. If it 3221is present, it is the maximum number of bytes that should be skipped by 3222this alignment directive. If doing the alignment would require 3223skipping more bytes than the specified maximum, then the alignment is 3224not done at all. You can omit the fill value (the second argument) 3225entirely by simply using two commas after the required alignment; this 3226can be useful if you want the alignment to be filled with no-op 3227instructions when appropriate. 3228 3229 The `.balignw' and `.balignl' directives are variants of the 3230`.balign' directive. The `.balignw' directive treats the fill pattern 3231as a two byte word value. The `.balignl' directives treats the fill 3232pattern as a four byte longword value. For example, `.balignw 32334,0x368d' will align to a multiple of 4. If it skips two bytes, they 3234will be filled in with the value 0x368d (the exact placement of the 3235bytes depends upon the endianness of the processor). If it skips 1 or 32363 bytes, the fill value is undefined. 3237 3238 3239File: as.info, Node: Bundle directives, Next: Byte, Prev: Balign, Up: Pseudo Ops 3240 32417.8 `.bundle_align_mode ABS-EXPR' 3242================================= 3243 3244`.bundle_align_mode' enables or disables "aligned instruction bundle" 3245mode. In this mode, sequences of adjacent instructions are grouped 3246into fixed-sized "bundles". If the argument is zero, this mode is 3247disabled (which is the default state). If the argument it not zero, it 3248gives the size of an instruction bundle as a power of two (as for the 3249`.p2align' directive, *note P2align::). 3250 3251 For some targets, it's an ABI requirement that no instruction may 3252span a certain aligned boundary. A "bundle" is simply a sequence of 3253instructions that starts on an aligned boundary. For example, if 3254ABS-EXPR is `5' then the bundle size is 32, so each aligned chunk of 32 3255bytes is a bundle. When aligned instruction bundle mode is in effect, 3256no single instruction may span a boundary between bundles. If an 3257instruction would start too close to the end of a bundle for the length 3258of that particular instruction to fit within the bundle, then the space 3259at the end of that bundle is filled with no-op instructions so the 3260instruction starts in the next bundle. As a corollary, it's an error 3261if any single instruction's encoding is longer than the bundle size. 3262 32637.9 `.bundle_lock' and `.bundle_unlock' 3264======================================= 3265 3266The `.bundle_lock' and directive `.bundle_unlock' directives allow 3267explicit control over instruction bundle padding. These directives are 3268only valid when `.bundle_align_mode' has been used to enable aligned 3269instruction bundle mode. It's an error if they appear when 3270`.bundle_align_mode' has not been used at all, or when the last 3271directive was `.bundle_align_mode 0'. 3272 3273 For some targets, it's an ABI requirement that certain instructions 3274may appear only as part of specified permissible sequences of multiple 3275instructions, all within the same bundle. A pair of `.bundle_lock' and 3276`.bundle_unlock' directives define a "bundle-locked" instruction 3277sequence. For purposes of aligned instruction bundle mode, a sequence 3278starting with `.bundle_lock' and ending with `.bundle_unlock' is 3279treated as a single instruction. That is, the entire sequence must fit 3280into a single bundle and may not span a bundle boundary. If necessary, 3281no-op instructions will be inserted before the first instruction of the 3282sequence so that the whole sequence starts on an aligned bundle 3283boundary. It's an error if the sequence is longer than the bundle size. 3284 3285 For convenience when using `.bundle_lock' and `.bundle_unlock' 3286inside assembler macros (*note Macro::), bundle-locked sequences may be 3287nested. That is, a second `.bundle_lock' directive before the next 3288`.bundle_unlock' directive has no effect except that it must be matched 3289by another closing `.bundle_unlock' so that there is the same number of 3290`.bundle_lock' and `.bundle_unlock' directives. 3291 3292 3293File: as.info, Node: Byte, Next: CFI directives, Prev: Bundle directives, Up: Pseudo Ops 3294 32957.10 `.byte EXPRESSIONS' 3296======================== 3297 3298`.byte' expects zero or more expressions, separated by commas. Each 3299expression is assembled into the next byte. 3300 3301 3302File: as.info, Node: CFI directives, Next: Comm, Prev: Byte, Up: Pseudo Ops 3303 33047.11 `.cfi_sections SECTION_LIST' 3305================================= 3306 3307`.cfi_sections' may be used to specify whether CFI directives should 3308emit `.eh_frame' section and/or `.debug_frame' section. If 3309SECTION_LIST is `.eh_frame', `.eh_frame' is emitted, if SECTION_LIST is 3310`.debug_frame', `.debug_frame' is emitted. To emit both use 3311`.eh_frame, .debug_frame'. The default if this directive is not used 3312is `.cfi_sections .eh_frame'. 3313 3314 On targets that support compact unwinding tables these can be 3315generated by specifying `.eh_frame_header' instead of `.eh_frame'. 3316 33177.12 `.cfi_startproc [simple]' 3318============================== 3319 3320`.cfi_startproc' is used at the beginning of each function that should 3321have an entry in `.eh_frame'. It initializes some internal data 3322structures. Don't forget to close the function by `.cfi_endproc'. 3323 3324 Unless `.cfi_startproc' is used along with parameter `simple' it 3325also emits some architecture dependent initial CFI instructions. 3326 33277.13 `.cfi_endproc' 3328=================== 3329 3330`.cfi_endproc' is used at the end of a function where it closes its 3331unwind entry previously opened by `.cfi_startproc', and emits it to 3332`.eh_frame'. 3333 33347.14 `.cfi_personality ENCODING [, EXP]' 3335======================================== 3336 3337`.cfi_personality' defines personality routine and its encoding. 3338ENCODING must be a constant determining how the personality should be 3339encoded. If it is 255 (`DW_EH_PE_omit'), second argument is not 3340present, otherwise second argument should be a constant or a symbol 3341name. When using indirect encodings, the symbol provided should be the 3342location where personality can be loaded from, not the personality 3343routine itself. The default after `.cfi_startproc' is 3344`.cfi_personality 0xff', no personality routine. 3345 33467.15 `.cfi_lsda ENCODING [, EXP]' 3347================================= 3348 3349`.cfi_lsda' defines LSDA and its encoding. ENCODING must be a constant 3350determining how the LSDA should be encoded. If it is 255 3351(`DW_EH_PE_omit'), second argument is not present, otherwise second 3352argument should be a constant or a symbol name. The default after 3353`.cfi_startproc' is `.cfi_lsda 0xff', no LSDA. 3354 33557.16 `.cfi_inline_lsda' [ALIGN] 3356=============================== 3357 3358`.cfi_inline_lsda' marks the start of a LSDA data section and switches 3359to the corresponding `.gnu.extab' section. Must be preceded by a CFI 3360block containing a `.cfi_lsda' directive. Only valid when generating 3361compact EH frames (i.e. with `.cfi_sections eh_frame_entry'. 3362 3363 If a compact encoding is being used then the table header and 3364unwinding opcodes will be generated at this point, so that they are 3365immediately followed by the LSDA data. The symbol referenced by the 3366`.cfi_lsda' directive should still be defined in case a fallback FDE 3367based encoding is used. 3368 3369 The optional ALIGN argument specifies the alignment required. The 3370alinment is specified as a power of two, as with the `.p2align' 3371directive. 3372 33737.17 `.cfi_def_cfa REGISTER, OFFSET' 3374==================================== 3375 3376`.cfi_def_cfa' defines a rule for computing CFA as: take address from 3377REGISTER and add OFFSET to it. 3378 33797.18 `.cfi_def_cfa_register REGISTER' 3380===================================== 3381 3382`.cfi_def_cfa_register' modifies a rule for computing CFA. From now on 3383REGISTER will be used instead of the old one. Offset remains the same. 3384 33857.19 `.cfi_def_cfa_offset OFFSET' 3386================================= 3387 3388`.cfi_def_cfa_offset' modifies a rule for computing CFA. Register 3389remains the same, but OFFSET is new. Note that it is the absolute 3390offset that will be added to a defined register to compute CFA address. 3391 33927.20 `.cfi_adjust_cfa_offset OFFSET' 3393==================================== 3394 3395Same as `.cfi_def_cfa_offset' but OFFSET is a relative value that is 3396added/substracted from the previous offset. 3397 33987.21 `.cfi_offset REGISTER, OFFSET' 3399=================================== 3400 3401Previous value of REGISTER is saved at offset OFFSET from CFA. 3402 34037.22 `.cfi_rel_offset REGISTER, OFFSET' 3404======================================= 3405 3406Previous value of REGISTER is saved at offset OFFSET from the current 3407CFA register. This is transformed to `.cfi_offset' using the known 3408displacement of the CFA register from the CFA. This is often easier to 3409use, because the number will match the code it's annotating. 3410 34117.23 `.cfi_register REGISTER1, REGISTER2' 3412========================================= 3413 3414Previous value of REGISTER1 is saved in register REGISTER2. 3415 34167.24 `.cfi_restore REGISTER' 3417============================ 3418 3419`.cfi_restore' says that the rule for REGISTER is now the same as it 3420was at the beginning of the function, after all initial instruction 3421added by `.cfi_startproc' were executed. 3422 34237.25 `.cfi_undefined REGISTER' 3424============================== 3425 3426From now on the previous value of REGISTER can't be restored anymore. 3427 34287.26 `.cfi_same_value REGISTER' 3429=============================== 3430 3431Current value of REGISTER is the same like in the previous frame, i.e. 3432no restoration needed. 3433 34347.27 `.cfi_remember_state', 3435=========================== 3436 3437First save all current rules for all registers by `.cfi_remember_state', 3438then totally screw them up by subsequent `.cfi_*' directives and when 3439everything is hopelessly bad, use `.cfi_restore_state' to restore the 3440previous saved state. 3441 34427.28 `.cfi_return_column REGISTER' 3443================================== 3444 3445Change return column REGISTER, i.e. the return address is either 3446directly in REGISTER or can be accessed by rules for REGISTER. 3447 34487.29 `.cfi_signal_frame' 3449======================== 3450 3451Mark current function as signal trampoline. 3452 34537.30 `.cfi_window_save' 3454======================= 3455 3456SPARC register window has been saved. 3457 34587.31 `.cfi_escape' EXPRESSION[, ...] 3459==================================== 3460 3461Allows the user to add arbitrary bytes to the unwind info. One might 3462use this to add OS-specific CFI opcodes, or generic CFI opcodes that 3463GAS does not yet support. 3464 34657.32 `.cfi_val_encoded_addr REGISTER, ENCODING, LABEL' 3466====================================================== 3467 3468The current value of REGISTER is LABEL. The value of LABEL will be 3469encoded in the output file according to ENCODING; see the description 3470of `.cfi_personality' for details on this encoding. 3471 3472 The usefulness of equating a register to a fixed label is probably 3473limited to the return address register. Here, it can be useful to mark 3474a code segment that has only one return address which is reached by a 3475direct branch and no copy of the return address exists in memory or 3476another register. 3477 34787.33 `.cfi_epilogue_begin' 3479========================== 3480 3481A pseudo-operation which marks the beginning of the epilogue in a given 3482function. This is currently used by the compact unwind-table 3483implementation (for exception handling), which assumes a single register 3484state for unwinding throughout the body of a function. The function is 3485scanned, and CFI directives are rewritten in a compact form. However, 3486recent versions of GCC emit unwind information for function epilogues, 3487which should not be represented in this compact form: hence, any CFI 3488directives which occur in a function after `.cfi_epilogue_end' are not 3489processed. 3490 3491 This operation only affects the internals of the assembler, and is 3492not represented in the binary output. 3493 3494 3495File: as.info, Node: Comm, Next: Data, Prev: CFI directives, Up: Pseudo Ops 3496 34977.34 `.comm SYMBOL , LENGTH ' 3498============================= 3499 3500`.comm' declares a common symbol named SYMBOL. When linking, a common 3501symbol in one object file may be merged with a defined or common symbol 3502of the same name in another object file. If `ld' does not see a 3503definition for the symbol-just one or more common symbols-then it will 3504allocate LENGTH bytes of uninitialized memory. LENGTH must be an 3505absolute expression. If `ld' sees multiple common symbols with the 3506same name, and they do not all have the same size, it will allocate 3507space using the largest size. 3508 3509 When using ELF or (as a GNU extension) PE, the `.comm' directive 3510takes an optional third argument. This is the desired alignment of the 3511symbol, specified for ELF as a byte boundary (for example, an alignment 3512of 16 means that the least significant 4 bits of the address should be 3513zero), and for PE as a power of two (for example, an alignment of 5 3514means aligned to a 32-byte boundary). The alignment must be an 3515absolute expression, and it must be a power of two. If `ld' allocates 3516uninitialized memory for the common symbol, it will use the alignment 3517when placing the symbol. If no alignment is specified, `as' will set 3518the alignment to the largest power of two less than or equal to the 3519size of the symbol, up to a maximum of 16 on ELF, or the default 3520section alignment of 4 on PE(1). 3521 3522 The syntax for `.comm' differs slightly on the HPPA. The syntax is 3523`SYMBOL .comm, LENGTH'; SYMBOL is optional. 3524 3525 ---------- Footnotes ---------- 3526 3527 (1) This is not the same as the executable image file alignment 3528controlled by `ld''s `--section-alignment' option; image file sections 3529in PE are aligned to multiples of 4096, which is far too large an 3530alignment for ordinary variables. It is rather the default alignment 3531for (non-debug) sections within object (`*.o') files, which are less 3532strictly aligned. 3533 3534 3535File: as.info, Node: Data, Next: Def, Prev: Comm, Up: Pseudo Ops 3536 35377.35 `.data SUBSECTION' 3538======================= 3539 3540`.data' tells `as' to assemble the following statements onto the end of 3541the data subsection numbered SUBSECTION (which is an absolute 3542expression). If SUBSECTION is omitted, it defaults to zero. 3543 3544 3545File: as.info, Node: Def, Next: Desc, Prev: Data, Up: Pseudo Ops 3546 35477.36 `.def NAME' 3548================ 3549 3550Begin defining debugging information for a symbol NAME; the definition 3551extends until the `.endef' directive is encountered. 3552 3553 3554File: as.info, Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops 3555 35567.37 `.desc SYMBOL, ABS-EXPRESSION' 3557=================================== 3558 3559This directive sets the descriptor of the symbol (*note Symbol 3560Attributes::) to the low 16 bits of an absolute expression. 3561 3562 The `.desc' directive is not available when `as' is configured for 3563COFF output; it is only for `a.out' or `b.out' object format. For the 3564sake of compatibility, `as' accepts it, but produces no output, when 3565configured for COFF. 3566 3567 3568File: as.info, Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops 3569 35707.38 `.dim' 3571=========== 3572 3573This directive is generated by compilers to include auxiliary debugging 3574information in the symbol table. It is only permitted inside 3575`.def'/`.endef' pairs. 3576 3577 3578File: as.info, Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops 3579 35807.39 `.double FLONUMS' 3581====================== 3582 3583`.double' expects zero or more flonums, separated by commas. It 3584assembles floating point numbers. The exact kind of floating point 3585numbers emitted depends on how `as' is configured. *Note Machine 3586Dependencies::. 3587 3588 3589File: as.info, Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops 3590 35917.40 `.eject' 3592============= 3593 3594Force a page break at this point, when generating assembly listings. 3595 3596 3597File: as.info, Node: Else, Next: Elseif, Prev: Eject, Up: Pseudo Ops 3598 35997.41 `.else' 3600============ 3601 3602`.else' is part of the `as' support for conditional assembly; see *note 3603`.if': If. It marks the beginning of a section of code to be assembled 3604if the condition for the preceding `.if' was false. 3605 3606 3607File: as.info, Node: Elseif, Next: End, Prev: Else, Up: Pseudo Ops 3608 36097.42 `.elseif' 3610============== 3611 3612`.elseif' is part of the `as' support for conditional assembly; see 3613*note `.if': If. It is shorthand for beginning a new `.if' block that 3614would otherwise fill the entire `.else' section. 3615 3616 3617File: as.info, Node: End, Next: Endef, Prev: Elseif, Up: Pseudo Ops 3618 36197.43 `.end' 3620=========== 3621 3622`.end' marks the end of the assembly file. `as' does not process 3623anything in the file past the `.end' directive. 3624 3625 3626File: as.info, Node: Endef, Next: Endfunc, Prev: End, Up: Pseudo Ops 3627 36287.44 `.endef' 3629============= 3630 3631This directive flags the end of a symbol definition begun with `.def'. 3632 3633 3634File: as.info, Node: Endfunc, Next: Endif, Prev: Endef, Up: Pseudo Ops 3635 36367.45 `.endfunc' 3637=============== 3638 3639`.endfunc' marks the end of a function specified with `.func'. 3640 3641 3642File: as.info, Node: Endif, Next: Equ, Prev: Endfunc, Up: Pseudo Ops 3643 36447.46 `.endif' 3645============= 3646 3647`.endif' is part of the `as' support for conditional assembly; it marks 3648the end of a block of code that is only assembled conditionally. *Note 3649`.if': If. 3650 3651 3652File: as.info, Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops 3653 36547.47 `.equ SYMBOL, EXPRESSION' 3655============================== 3656 3657This directive sets the value of SYMBOL to EXPRESSION. It is 3658synonymous with `.set'; see *note `.set': Set. 3659 3660 The syntax for `equ' on the HPPA is `SYMBOL .equ EXPRESSION'. 3661 3662 The syntax for `equ' on the Z80 is `SYMBOL equ EXPRESSION'. On the 3663Z80 it is an eror if SYMBOL is already defined, but the symbol is not 3664protected from later redefinition. Compare *note Equiv::. 3665 3666 3667File: as.info, Node: Equiv, Next: Eqv, Prev: Equ, Up: Pseudo Ops 3668 36697.48 `.equiv SYMBOL, EXPRESSION' 3670================================ 3671 3672The `.equiv' directive is like `.equ' and `.set', except that the 3673assembler will signal an error if SYMBOL is already defined. Note a 3674symbol which has been referenced but not actually defined is considered 3675to be undefined. 3676 3677 Except for the contents of the error message, this is roughly 3678equivalent to 3679 .ifdef SYM 3680 .err 3681 .endif 3682 .equ SYM,VAL 3683 plus it protects the symbol from later redefinition. 3684 3685 3686File: as.info, Node: Eqv, Next: Err, Prev: Equiv, Up: Pseudo Ops 3687 36887.49 `.eqv SYMBOL, EXPRESSION' 3689============================== 3690 3691The `.eqv' directive is like `.equiv', but no attempt is made to 3692evaluate the expression or any part of it immediately. Instead each 3693time the resulting symbol is used in an expression, a snapshot of its 3694current value is taken. 3695 3696 3697File: as.info, Node: Err, Next: Error, Prev: Eqv, Up: Pseudo Ops 3698 36997.50 `.err' 3700=========== 3701 3702If `as' assembles a `.err' directive, it will print an error message 3703and, unless the `-Z' option was used, it will not generate an object 3704file. This can be used to signal an error in conditionally compiled 3705code. 3706 3707 3708File: as.info, Node: Error, Next: Exitm, Prev: Err, Up: Pseudo Ops 3709 37107.51 `.error "STRING"' 3711====================== 3712 3713Similarly to `.err', this directive emits an error, but you can specify 3714a string that will be emitted as the error message. If you don't 3715specify the message, it defaults to `".error directive invoked in 3716source file"'. *Note Error and Warning Messages: Errors. 3717 3718 .error "This code has not been assembled and tested." 3719 3720 3721File: as.info, Node: Exitm, Next: Extern, Prev: Error, Up: Pseudo Ops 3722 37237.52 `.exitm' 3724============= 3725 3726Exit early from the current macro definition. *Note Macro::. 3727 3728 3729File: as.info, Node: Extern, Next: Fail, Prev: Exitm, Up: Pseudo Ops 3730 37317.53 `.extern' 3732============== 3733 3734`.extern' is accepted in the source program--for compatibility with 3735other assemblers--but it is ignored. `as' treats all undefined symbols 3736as external. 3737 3738 3739File: as.info, Node: Fail, Next: File, Prev: Extern, Up: Pseudo Ops 3740 37417.54 `.fail EXPRESSION' 3742======================= 3743 3744Generates an error or a warning. If the value of the EXPRESSION is 500 3745or more, `as' will print a warning message. If the value is less than 3746500, `as' will print an error message. The message will include the 3747value of EXPRESSION. This can occasionally be useful inside complex 3748nested macros or conditional assembly. 3749 3750 3751File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops 3752 37537.55 `.file' 3754============ 3755 3756There are two different versions of the `.file' directive. Targets 3757that support DWARF2 line number information use the DWARF2 version of 3758`.file'. Other targets use the default version. 3759 3760Default Version 3761--------------- 3762 3763This version of the `.file' directive tells `as' that we are about to 3764start a new logical file. The syntax is: 3765 3766 .file STRING 3767 3768 STRING is the new file name. In general, the filename is recognized 3769whether or not it is surrounded by quotes `"'; but if you wish to 3770specify an empty file name, you must give the quotes-`""'. This 3771statement may go away in future: it is only recognized to be compatible 3772with old `as' programs. 3773 3774DWARF2 Version 3775-------------- 3776 3777When emitting DWARF2 line number information, `.file' assigns filenames 3778to the `.debug_line' file name table. The syntax is: 3779 3780 .file FILENO FILENAME 3781 3782 The FILENO operand should be a unique positive integer to use as the 3783index of the entry in the table. The FILENAME operand is a C string 3784literal. 3785 3786 The detail of filename indices is exposed to the user because the 3787filename table is shared with the `.debug_info' section of the DWARF2 3788debugging information, and thus the user must know the exact indices 3789that table entries will have. 3790 3791 3792File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops 3793 37947.56 `.fill REPEAT , SIZE , VALUE' 3795================================== 3796 3797REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT 3798copies of SIZE bytes. REPEAT may be zero or more. SIZE may be zero or 3799more, but if it is more than 8, then it is deemed to have the value 8, 3800compatible with other people's assemblers. The contents of each REPEAT 3801bytes is taken from an 8-byte number. The highest order 4 bytes are 3802zero. The lowest order 4 bytes are VALUE rendered in the byte-order of 3803an integer on the computer `as' is assembling for. Each SIZE bytes in 3804a repetition is taken from the lowest order SIZE bytes of this number. 3805Again, this bizarre behavior is compatible with other people's 3806assemblers. 3807 3808 SIZE and VALUE are optional. If the second comma and VALUE are 3809absent, VALUE is assumed zero. If the first comma and following tokens 3810are absent, SIZE is assumed to be 1. 3811 3812 3813File: as.info, Node: Float, Next: Func, Prev: Fill, Up: Pseudo Ops 3814 38157.57 `.float FLONUMS' 3816===================== 3817 3818This directive assembles zero or more flonums, separated by commas. It 3819has the same effect as `.single'. The exact kind of floating point 3820numbers emitted depends on how `as' is configured. *Note Machine 3821Dependencies::. 3822 3823 3824File: as.info, Node: Func, Next: Global, Prev: Float, Up: Pseudo Ops 3825 38267.58 `.func NAME[,LABEL]' 3827========================= 3828 3829`.func' emits debugging information to denote function NAME, and is 3830ignored unless the file is assembled with debugging enabled. Only 3831`--gstabs[+]' is currently supported. LABEL is the entry point of the 3832function and if omitted NAME prepended with the `leading char' is used. 3833`leading char' is usually `_' or nothing, depending on the target. All 3834functions are currently defined to have `void' return type. The 3835function must be terminated with `.endfunc'. 3836 3837 3838File: as.info, Node: Global, Next: Gnu_attribute, Prev: Func, Up: Pseudo Ops 3839 38407.59 `.global SYMBOL', `.globl SYMBOL' 3841====================================== 3842 3843`.global' makes the symbol visible to `ld'. If you define SYMBOL in 3844your partial program, its value is made available to other partial 3845programs that are linked with it. Otherwise, SYMBOL takes its 3846attributes from a symbol of the same name from another file linked into 3847the same program. 3848 3849 Both spellings (`.globl' and `.global') are accepted, for 3850compatibility with other assemblers. 3851 3852 On the HPPA, `.global' is not always enough to make it accessible to 3853other partial programs. You may need the HPPA-only `.EXPORT' directive 3854as well. *Note HPPA Assembler Directives: HPPA Directives. 3855 3856 3857File: as.info, Node: Gnu_attribute, Next: Hidden, Prev: Global, Up: Pseudo Ops 3858 38597.60 `.gnu_attribute TAG,VALUE' 3860=============================== 3861 3862Record a GNU object attribute for this file. *Note Object Attributes::. 3863 3864 3865File: as.info, Node: Hidden, Next: hword, Prev: Gnu_attribute, Up: Pseudo Ops 3866 38677.61 `.hidden NAMES' 3868==================== 3869 3870This is one of the ELF visibility directives. The other two are 3871`.internal' (*note `.internal': Internal.) and `.protected' (*note 3872`.protected': Protected.). 3873 3874 This directive overrides the named symbols default visibility (which 3875is set by their binding: local, global or weak). The directive sets 3876the visibility to `hidden' which means that the symbols are not visible 3877to other components. Such symbols are always considered to be 3878`protected' as well. 3879 3880 3881File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops 3882 38837.62 `.hword EXPRESSIONS' 3884========================= 3885 3886This expects zero or more EXPRESSIONS, and emits a 16 bit number for 3887each. 3888 3889 This directive is a synonym for `.short'; depending on the target 3890architecture, it may also be a synonym for `.word'. 3891 3892 3893File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops 3894 38957.63 `.ident' 3896============= 3897 3898This directive is used by some assemblers to place tags in object 3899files. The behavior of this directive varies depending on the target. 3900When using the a.out object file format, `as' simply accepts the 3901directive for source-file compatibility with existing assemblers, but 3902does not emit anything for it. When using COFF, comments are emitted 3903to the `.comment' or `.rdata' section, depending on the target. When 3904using ELF, comments are emitted to the `.comment' section. 3905 3906 3907File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops 3908 39097.64 `.if ABSOLUTE EXPRESSION' 3910============================== 3911 3912`.if' marks the beginning of a section of code which is only considered 3913part of the source program being assembled if the argument (which must 3914be an ABSOLUTE EXPRESSION) is non-zero. The end of the conditional 3915section of code must be marked by `.endif' (*note `.endif': Endif.); 3916optionally, you may include code for the alternative condition, flagged 3917by `.else' (*note `.else': Else.). If you have several conditions to 3918check, `.elseif' may be used to avoid nesting blocks if/else within 3919each subsequent `.else' block. 3920 3921 The following variants of `.if' are also supported: 3922`.ifdef SYMBOL' 3923 Assembles the following section of code if the specified SYMBOL 3924 has been defined. Note a symbol which has been referenced but not 3925 yet defined is considered to be undefined. 3926 3927`.ifb TEXT' 3928 Assembles the following section of code if the operand is blank 3929 (empty). 3930 3931`.ifc STRING1,STRING2' 3932 Assembles the following section of code if the two strings are the 3933 same. The strings may be optionally quoted with single quotes. 3934 If they are not quoted, the first string stops at the first comma, 3935 and the second string stops at the end of the line. Strings which 3936 contain whitespace should be quoted. The string comparison is 3937 case sensitive. 3938 3939`.ifeq ABSOLUTE EXPRESSION' 3940 Assembles the following section of code if the argument is zero. 3941 3942`.ifeqs STRING1,STRING2' 3943 Another form of `.ifc'. The strings must be quoted using double 3944 quotes. 3945 3946`.ifge ABSOLUTE EXPRESSION' 3947 Assembles the following section of code if the argument is greater 3948 than or equal to zero. 3949 3950`.ifgt ABSOLUTE EXPRESSION' 3951 Assembles the following section of code if the argument is greater 3952 than zero. 3953 3954`.ifle ABSOLUTE EXPRESSION' 3955 Assembles the following section of code if the argument is less 3956 than or equal to zero. 3957 3958`.iflt ABSOLUTE EXPRESSION' 3959 Assembles the following section of code if the argument is less 3960 than zero. 3961 3962`.ifnb TEXT' 3963 Like `.ifb', but the sense of the test is reversed: this assembles 3964 the following section of code if the operand is non-blank 3965 (non-empty). 3966 3967`.ifnc STRING1,STRING2.' 3968 Like `.ifc', but the sense of the test is reversed: this assembles 3969 the following section of code if the two strings are not the same. 3970 3971`.ifndef SYMBOL' 3972`.ifnotdef SYMBOL' 3973 Assembles the following section of code if the specified SYMBOL 3974 has not been defined. Both spelling variants are equivalent. 3975 Note a symbol which has been referenced but not yet defined is 3976 considered to be undefined. 3977 3978`.ifne ABSOLUTE EXPRESSION' 3979 Assembles the following section of code if the argument is not 3980 equal to zero (in other words, this is equivalent to `.if'). 3981 3982`.ifnes STRING1,STRING2' 3983 Like `.ifeqs', but the sense of the test is reversed: this 3984 assembles the following section of code if the two strings are not 3985 the same. 3986 3987 3988File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops 3989 39907.65 `.incbin "FILE"[,SKIP[,COUNT]]' 3991==================================== 3992 3993The `incbin' directive includes FILE verbatim at the current location. 3994You can control the search paths used with the `-I' command-line option 3995(*note Command-Line Options: Invoking.). Quotation marks are required 3996around FILE. 3997 3998 The SKIP argument skips a number of bytes from the start of the 3999FILE. The COUNT argument indicates the maximum number of bytes to 4000read. Note that the data is not aligned in any way, so it is the user's 4001responsibility to make sure that proper alignment is provided both 4002before and after the `incbin' directive. 4003 4004 4005File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops 4006 40077.66 `.include "FILE"' 4008====================== 4009 4010This directive provides a way to include supporting files at specified 4011points in your source program. The code from FILE is assembled as if 4012it followed the point of the `.include'; when the end of the included 4013file is reached, assembly of the original file continues. You can 4014control the search paths used with the `-I' command-line option (*note 4015Command-Line Options: Invoking.). Quotation marks are required around 4016FILE. 4017 4018 4019File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops 4020 40217.67 `.int EXPRESSIONS' 4022======================= 4023 4024Expect zero or more EXPRESSIONS, of any section, separated by commas. 4025For each expression, emit a number that, at run time, is the value of 4026that expression. The byte order and bit size of the number depends on 4027what kind of target the assembly is for. 4028 4029 4030File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops 4031 40327.68 `.internal NAMES' 4033====================== 4034 4035This is one of the ELF visibility directives. The other two are 4036`.hidden' (*note `.hidden': Hidden.) and `.protected' (*note 4037`.protected': Protected.). 4038 4039 This directive overrides the named symbols default visibility (which 4040is set by their binding: local, global or weak). The directive sets 4041the visibility to `internal' which means that the symbols are 4042considered to be `hidden' (i.e., not visible to other components), and 4043that some extra, processor specific processing must also be performed 4044upon the symbols as well. 4045 4046 4047File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops 4048 40497.69 `.irp SYMBOL,VALUES'... 4050============================ 4051 4052Evaluate a sequence of statements assigning different values to SYMBOL. 4053The sequence of statements starts at the `.irp' directive, and is 4054terminated by an `.endr' directive. For each VALUE, SYMBOL is set to 4055VALUE, and the sequence of statements is assembled. If no VALUE is 4056listed, the sequence of statements is assembled once, with SYMBOL set 4057to the null string. To refer to SYMBOL within the sequence of 4058statements, use \SYMBOL. 4059 4060 For example, assembling 4061 4062 .irp param,1,2,3 4063 move d\param,sp@- 4064 .endr 4065 4066 is equivalent to assembling 4067 4068 move d1,sp@- 4069 move d2,sp@- 4070 move d3,sp@- 4071 4072 For some caveats with the spelling of SYMBOL, see also *note Macro::. 4073 4074 4075File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops 4076 40777.70 `.irpc SYMBOL,VALUES'... 4078============================= 4079 4080Evaluate a sequence of statements assigning different values to SYMBOL. 4081The sequence of statements starts at the `.irpc' directive, and is 4082terminated by an `.endr' directive. For each character in VALUE, 4083SYMBOL is set to the character, and the sequence of statements is 4084assembled. If no VALUE is listed, the sequence of statements is 4085assembled once, with SYMBOL set to the null string. To refer to SYMBOL 4086within the sequence of statements, use \SYMBOL. 4087 4088 For example, assembling 4089 4090 .irpc param,123 4091 move d\param,sp@- 4092 .endr 4093 4094 is equivalent to assembling 4095 4096 move d1,sp@- 4097 move d2,sp@- 4098 move d3,sp@- 4099 4100 For some caveats with the spelling of SYMBOL, see also the discussion 4101at *Note Macro::. 4102 4103 4104File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops 4105 41067.71 `.lcomm SYMBOL , LENGTH' 4107============================= 4108 4109Reserve LENGTH (an absolute expression) bytes for a local common 4110denoted by SYMBOL. The section and value of SYMBOL are those of the 4111new local common. The addresses are allocated in the bss section, so 4112that at run-time the bytes start off zeroed. SYMBOL is not declared 4113global (*note `.global': Global.), so is normally not visible to `ld'. 4114 4115 Some targets permit a third argument to be used with `.lcomm'. This 4116argument specifies the desired alignment of the symbol in the bss 4117section. 4118 4119 The syntax for `.lcomm' differs slightly on the HPPA. The syntax is 4120`SYMBOL .lcomm, LENGTH'; SYMBOL is optional. 4121 4122 4123File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops 4124 41257.72 `.lflags' 4126============== 4127 4128`as' accepts this directive, for compatibility with other assemblers, 4129but ignores it. 4130 4131 4132File: as.info, Node: Line, Next: Linkonce, Prev: Lflags, Up: Pseudo Ops 4133 41347.73 `.line LINE-NUMBER' 4135======================== 4136 4137Change the logical line number. LINE-NUMBER must be an absolute 4138expression. The next line has that logical line number. Therefore any 4139other statements on the current line (after a statement separator 4140character) are reported as on logical line number LINE-NUMBER - 1. One 4141day `as' will no longer support this directive: it is recognized only 4142for compatibility with existing assembler programs. 4143 4144Even though this is a directive associated with the `a.out' or `b.out' 4145object-code formats, `as' still recognizes it when producing COFF 4146output, and treats `.line' as though it were the COFF `.ln' _if_ it is 4147found outside a `.def'/`.endef' pair. 4148 4149 Inside a `.def', `.line' is, instead, one of the directives used by 4150compilers to generate auxiliary symbol information for debugging. 4151 4152 4153File: as.info, Node: Linkonce, Next: List, Prev: Line, Up: Pseudo Ops 4154 41557.74 `.linkonce [TYPE]' 4156======================= 4157 4158Mark the current section so that the linker only includes a single copy 4159of it. This may be used to include the same section in several 4160different object files, but ensure that the linker will only include it 4161once in the final output file. The `.linkonce' pseudo-op must be used 4162for each instance of the section. Duplicate sections are detected 4163based on the section name, so it should be unique. 4164 4165 This directive is only supported by a few object file formats; as of 4166this writing, the only object file format which supports it is the 4167Portable Executable format used on Windows NT. 4168 4169 The TYPE argument is optional. If specified, it must be one of the 4170following strings. For example: 4171 .linkonce same_size 4172 Not all types may be supported on all object file formats. 4173 4174`discard' 4175 Silently discard duplicate sections. This is the default. 4176 4177`one_only' 4178 Warn if there are duplicate sections, but still keep only one copy. 4179 4180`same_size' 4181 Warn if any of the duplicates have different sizes. 4182 4183`same_contents' 4184 Warn if any of the duplicates do not have exactly the same 4185 contents. 4186 4187 4188File: as.info, Node: List, Next: Ln, Prev: Linkonce, Up: Pseudo Ops 4189 41907.75 `.list' 4191============ 4192 4193Control (in conjunction with the `.nolist' directive) whether or not 4194assembly listings are generated. These two directives maintain an 4195internal counter (which is zero initially). `.list' increments the 4196counter, and `.nolist' decrements it. Assembly listings are generated 4197whenever the counter is greater than zero. 4198 4199 By default, listings are disabled. When you enable them (with the 4200`-a' command line option; *note Command-Line Options: Invoking.), the 4201initial value of the listing counter is one. 4202 4203 4204File: as.info, Node: Ln, Next: Loc, Prev: List, Up: Pseudo Ops 4205 42067.76 `.ln LINE-NUMBER' 4207====================== 4208 4209`.ln' is a synonym for `.line'. 4210 4211 4212File: as.info, Node: Loc, Next: Loc_mark_labels, Prev: Ln, Up: Pseudo Ops 4213 42147.77 `.loc FILENO LINENO [COLUMN] [OPTIONS]' 4215============================================ 4216 4217When emitting DWARF2 line number information, the `.loc' directive will 4218add a row to the `.debug_line' line number matrix corresponding to the 4219immediately following assembly instruction. The FILENO, LINENO, and 4220optional COLUMN arguments will be applied to the `.debug_line' state 4221machine before the row is added. 4222 4223 The OPTIONS are a sequence of the following tokens in any order: 4224 4225`basic_block' 4226 This option will set the `basic_block' register in the 4227 `.debug_line' state machine to `true'. 4228 4229`prologue_end' 4230 This option will set the `prologue_end' register in the 4231 `.debug_line' state machine to `true'. 4232 4233`epilogue_begin' 4234 This option will set the `epilogue_begin' register in the 4235 `.debug_line' state machine to `true'. 4236 4237`is_stmt VALUE' 4238 This option will set the `is_stmt' register in the `.debug_line' 4239 state machine to `value', which must be either 0 or 1. 4240 4241`isa VALUE' 4242 This directive will set the `isa' register in the `.debug_line' 4243 state machine to VALUE, which must be an unsigned integer. 4244 4245`discriminator VALUE' 4246 This directive will set the `discriminator' register in the 4247 `.debug_line' state machine to VALUE, which must be an unsigned 4248 integer. 4249 4250 4251 4252File: as.info, Node: Loc_mark_labels, Next: Local, Prev: Loc, Up: Pseudo Ops 4253 42547.78 `.loc_mark_labels ENABLE' 4255============================== 4256 4257When emitting DWARF2 line number information, the `.loc_mark_labels' 4258directive makes the assembler emit an entry to the `.debug_line' line 4259number matrix with the `basic_block' register in the state machine set 4260whenever a code label is seen. The ENABLE argument should be either 1 4261or 0, to enable or disable this function respectively. 4262 4263 4264File: as.info, Node: Local, Next: Long, Prev: Loc_mark_labels, Up: Pseudo Ops 4265 42667.79 `.local NAMES' 4267=================== 4268 4269This directive, which is available for ELF targets, marks each symbol in 4270the comma-separated list of `names' as a local symbol so that it will 4271not be externally visible. If the symbols do not already exist, they 4272will be created. 4273 4274 For targets where the `.lcomm' directive (*note Lcomm::) does not 4275accept an alignment argument, which is the case for most ELF targets, 4276the `.local' directive can be used in combination with `.comm' (*note 4277Comm::) to define aligned local common data. 4278 4279 4280File: as.info, Node: Long, Next: Macro, Prev: Local, Up: Pseudo Ops 4281 42827.80 `.long EXPRESSIONS' 4283======================== 4284 4285`.long' is the same as `.int'. *Note `.int': Int. 4286 4287 4288File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops 4289 42907.81 `.macro' 4291============= 4292 4293The commands `.macro' and `.endm' allow you to define macros that 4294generate assembly output. For example, this definition specifies a 4295macro `sum' that puts a sequence of numbers into memory: 4296 4297 .macro sum from=0, to=5 4298 .long \from 4299 .if \to-\from 4300 sum "(\from+1)",\to 4301 .endif 4302 .endm 4303 4304With that definition, `SUM 0,5' is equivalent to this assembly input: 4305 4306 .long 0 4307 .long 1 4308 .long 2 4309 .long 3 4310 .long 4 4311 .long 5 4312 4313`.macro MACNAME' 4314`.macro MACNAME MACARGS ...' 4315 Begin the definition of a macro called MACNAME. If your macro 4316 definition requires arguments, specify their names after the macro 4317 name, separated by commas or spaces. You can qualify the macro 4318 argument to indicate whether all invocations must specify a 4319 non-blank value (through `:`req''), or whether it takes all of the 4320 remaining arguments (through `:`vararg''). You can supply a 4321 default value for any macro argument by following the name with 4322 `=DEFLT'. You cannot define two macros with the same MACNAME 4323 unless it has been subject to the `.purgem' directive (*note 4324 Purgem::) between the two definitions. For example, these are all 4325 valid `.macro' statements: 4326 4327 `.macro comm' 4328 Begin the definition of a macro called `comm', which takes no 4329 arguments. 4330 4331 `.macro plus1 p, p1' 4332 `.macro plus1 p p1' 4333 Either statement begins the definition of a macro called 4334 `plus1', which takes two arguments; within the macro 4335 definition, write `\p' or `\p1' to evaluate the arguments. 4336 4337 `.macro reserve_str p1=0 p2' 4338 Begin the definition of a macro called `reserve_str', with two 4339 arguments. The first argument has a default value, but not 4340 the second. After the definition is complete, you can call 4341 the macro either as `reserve_str A,B' (with `\p1' evaluating 4342 to A and `\p2' evaluating to B), or as `reserve_str ,B' (with 4343 `\p1' evaluating as the default, in this case `0', and `\p2' 4344 evaluating to B). 4345 4346 `.macro m p1:req, p2=0, p3:vararg' 4347 Begin the definition of a macro called `m', with at least 4348 three arguments. The first argument must always have a value 4349 specified, but not the second, which instead has a default 4350 value. The third formal will get assigned all remaining 4351 arguments specified at invocation time. 4352 4353 When you call a macro, you can specify the argument values 4354 either by position, or by keyword. For example, `sum 9,17' 4355 is equivalent to `sum to=17, from=9'. 4356 4357 4358 Note that since each of the MACARGS can be an identifier exactly 4359 as any other one permitted by the target architecture, there may be 4360 occasional problems if the target hand-crafts special meanings to 4361 certain characters when they occur in a special position. For 4362 example, if the colon (`:') is generally permitted to be part of a 4363 symbol name, but the architecture specific code special-cases it 4364 when occurring as the final character of a symbol (to denote a 4365 label), then the macro parameter replacement code will have no way 4366 of knowing that and consider the whole construct (including the 4367 colon) an identifier, and check only this identifier for being the 4368 subject to parameter substitution. So for example this macro 4369 definition: 4370 4371 .macro label l 4372 \l: 4373 .endm 4374 4375 might not work as expected. Invoking `label foo' might not create 4376 a label called `foo' but instead just insert the text `\l:' into 4377 the assembler source, probably generating an error about an 4378 unrecognised identifier. 4379 4380 Similarly problems might occur with the period character (`.') 4381 which is often allowed inside opcode names (and hence identifier 4382 names). So for example constructing a macro to build an opcode 4383 from a base name and a length specifier like this: 4384 4385 .macro opcode base length 4386 \base.\length 4387 .endm 4388 4389 and invoking it as `opcode store l' will not create a `store.l' 4390 instruction but instead generate some kind of error as the 4391 assembler tries to interpret the text `\base.\length'. 4392 4393 There are several possible ways around this problem: 4394 4395 `Insert white space' 4396 If it is possible to use white space characters then this is 4397 the simplest solution. eg: 4398 4399 .macro label l 4400 \l : 4401 .endm 4402 4403 `Use `\()'' 4404 The string `\()' can be used to separate the end of a macro 4405 argument from the following text. eg: 4406 4407 .macro opcode base length 4408 \base\().\length 4409 .endm 4410 4411 `Use the alternate macro syntax mode' 4412 In the alternative macro syntax mode the ampersand character 4413 (`&') can be used as a separator. eg: 4414 4415 .altmacro 4416 .macro label l 4417 l&: 4418 .endm 4419 4420 Note: this problem of correctly identifying string parameters to 4421 pseudo ops also applies to the identifiers used in `.irp' (*note 4422 Irp::) and `.irpc' (*note Irpc::) as well. 4423 4424`.endm' 4425 Mark the end of a macro definition. 4426 4427`.exitm' 4428 Exit early from the current macro definition. 4429 4430`\@' 4431 `as' maintains a counter of how many macros it has executed in 4432 this pseudo-variable; you can copy that number to your output with 4433 `\@', but _only within a macro definition_. 4434 4435`LOCAL NAME [ , ... ]' 4436 _Warning: `LOCAL' is only available if you select "alternate macro 4437 syntax" with `--alternate' or `.altmacro'._ *Note `.altmacro': 4438 Altmacro. 4439 4440 4441File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops 4442 44437.82 `.mri VAL' 4444=============== 4445 4446If VAL is non-zero, this tells `as' to enter MRI mode. If VAL is zero, 4447this tells `as' to exit MRI mode. This change affects code assembled 4448until the next `.mri' directive, or until the end of the file. *Note 4449MRI mode: M. 4450 4451 4452File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops 4453 44547.83 `.noaltmacro' 4455================== 4456 4457Disable alternate macro mode. *Note Altmacro::. 4458 4459 4460File: as.info, Node: Nolist, Next: Octa, Prev: Noaltmacro, Up: Pseudo Ops 4461 44627.84 `.nolist' 4463============== 4464 4465Control (in conjunction with the `.list' directive) whether or not 4466assembly listings are generated. These two directives maintain an 4467internal counter (which is zero initially). `.list' increments the 4468counter, and `.nolist' decrements it. Assembly listings are generated 4469whenever the counter is greater than zero. 4470 4471 4472File: as.info, Node: Octa, Next: Offset, Prev: Nolist, Up: Pseudo Ops 4473 44747.85 `.octa BIGNUMS' 4475==================== 4476 4477This directive expects zero or more bignums, separated by commas. For 4478each bignum, it emits a 16-byte integer. 4479 4480 The term "octa" comes from contexts in which a "word" is two bytes; 4481hence _octa_-word for 16 bytes. 4482 4483 4484File: as.info, Node: Offset, Next: Org, Prev: Octa, Up: Pseudo Ops 4485 44867.86 `.offset LOC' 4487================== 4488 4489Set the location counter to LOC in the absolute section. LOC must be 4490an absolute expression. This directive may be useful for defining 4491symbols with absolute values. Do not confuse it with the `.org' 4492directive. 4493 4494 4495File: as.info, Node: Org, Next: P2align, Prev: Offset, Up: Pseudo Ops 4496 44977.87 `.org NEW-LC , FILL' 4498========================= 4499 4500Advance the location counter of the current section to NEW-LC. NEW-LC 4501is either an absolute expression or an expression with the same section 4502as the current subsection. That is, you can't use `.org' to cross 4503sections: if NEW-LC has the wrong section, the `.org' directive is 4504ignored. To be compatible with former assemblers, if the section of 4505NEW-LC is absolute, `as' issues a warning, then pretends the section of 4506NEW-LC is the same as the current subsection. 4507 4508 `.org' may only increase the location counter, or leave it 4509unchanged; you cannot use `.org' to move the location counter backwards. 4510 4511 Because `as' tries to assemble programs in one pass, NEW-LC may not 4512be undefined. If you really detest this restriction we eagerly await a 4513chance to share your improved assembler. 4514 4515 Beware that the origin is relative to the start of the section, not 4516to the start of the subsection. This is compatible with other people's 4517assemblers. 4518 4519 When the location counter (of the current subsection) is advanced, 4520the intervening bytes are filled with FILL which should be an absolute 4521expression. If the comma and FILL are omitted, FILL defaults to zero. 4522 4523 4524File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops 4525 45267.88 `.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' 4527================================================ 4528 4529Pad the location counter (in the current subsection) to a particular 4530storage boundary. The first expression (which must be absolute) is the 4531number of low-order zero bits the location counter must have after 4532advancement. For example `.p2align 3' advances the location counter 4533until it a multiple of 8. If the location counter is already a 4534multiple of 8, no change is needed. 4535 4536 The second expression (also absolute) gives the fill value to be 4537stored in the padding bytes. It (and the comma) may be omitted. If it 4538is omitted, the padding bytes are normally zero. However, on some 4539systems, if the section is marked as containing code and the fill value 4540is omitted, the space is filled with no-op instructions. 4541 4542 The third expression is also absolute, and is also optional. If it 4543is present, it is the maximum number of bytes that should be skipped by 4544this alignment directive. If doing the alignment would require 4545skipping more bytes than the specified maximum, then the alignment is 4546not done at all. You can omit the fill value (the second argument) 4547entirely by simply using two commas after the required alignment; this 4548can be useful if you want the alignment to be filled with no-op 4549instructions when appropriate. 4550 4551 The `.p2alignw' and `.p2alignl' directives are variants of the 4552`.p2align' directive. The `.p2alignw' directive treats the fill 4553pattern as a two byte word value. The `.p2alignl' directives treats the 4554fill pattern as a four byte longword value. For example, `.p2alignw 45552,0x368d' will align to a multiple of 4. If it skips two bytes, they 4556will be filled in with the value 0x368d (the exact placement of the 4557bytes depends upon the endianness of the processor). If it skips 1 or 45583 bytes, the fill value is undefined. 4559 4560 4561File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops 4562 45637.89 `.popsection' 4564================== 4565 4566This is one of the ELF section stack manipulation directives. The 4567others are `.section' (*note Section::), `.subsection' (*note 4568SubSection::), `.pushsection' (*note PushSection::), and `.previous' 4569(*note Previous::). 4570 4571 This directive replaces the current section (and subsection) with 4572the top section (and subsection) on the section stack. This section is 4573popped off the stack. 4574 4575 4576File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops 4577 45787.90 `.previous' 4579================ 4580 4581This is one of the ELF section stack manipulation directives. The 4582others are `.section' (*note Section::), `.subsection' (*note 4583SubSection::), `.pushsection' (*note PushSection::), and `.popsection' 4584(*note PopSection::). 4585 4586 This directive swaps the current section (and subsection) with most 4587recently referenced section/subsection pair prior to this one. Multiple 4588`.previous' directives in a row will flip between two sections (and 4589their subsections). For example: 4590 4591 .section A 4592 .subsection 1 4593 .word 0x1234 4594 .subsection 2 4595 .word 0x5678 4596 .previous 4597 .word 0x9abc 4598 4599 Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into 4600subsection 2 of section A. Whilst: 4601 4602 .section A 4603 .subsection 1 4604 # Now in section A subsection 1 4605 .word 0x1234 4606 .section B 4607 .subsection 0 4608 # Now in section B subsection 0 4609 .word 0x5678 4610 .subsection 1 4611 # Now in section B subsection 1 4612 .word 0x9abc 4613 .previous 4614 # Now in section B subsection 0 4615 .word 0xdef0 4616 4617 Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection 46180 of section B and 0x9abc into subsection 1 of section B. 4619 4620 In terms of the section stack, this directive swaps the current 4621section with the top section on the section stack. 4622 4623 4624File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops 4625 46267.91 `.print STRING' 4627==================== 4628 4629`as' will print STRING on the standard output during assembly. You 4630must put STRING in double quotes. 4631 4632 4633File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops 4634 46357.92 `.protected NAMES' 4636======================= 4637 4638This is one of the ELF visibility directives. The other two are 4639`.hidden' (*note Hidden::) and `.internal' (*note Internal::). 4640 4641 This directive overrides the named symbols default visibility (which 4642is set by their binding: local, global or weak). The directive sets 4643the visibility to `protected' which means that any references to the 4644symbols from within the components that defines them must be resolved 4645to the definition in that component, even if a definition in another 4646component would normally preempt this. 4647 4648 4649File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops 4650 46517.93 `.psize LINES , COLUMNS' 4652============================= 4653 4654Use this directive to declare the number of lines--and, optionally, the 4655number of columns--to use for each page, when generating listings. 4656 4657 If you do not use `.psize', listings use a default line-count of 60. 4658You may omit the comma and COLUMNS specification; the default width is 4659200 columns. 4660 4661 `as' generates formfeeds whenever the specified number of lines is 4662exceeded (or whenever you explicitly request one, using `.eject'). 4663 4664 If you specify LINES as `0', no formfeeds are generated save those 4665explicitly specified with `.eject'. 4666 4667 4668File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops 4669 46707.94 `.purgem NAME' 4671=================== 4672 4673Undefine the macro NAME, so that later uses of the string will not be 4674expanded. *Note Macro::. 4675 4676 4677File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops 4678 46797.95 `.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]' 4680======================================================================== 4681 4682This is one of the ELF section stack manipulation directives. The 4683others are `.section' (*note Section::), `.subsection' (*note 4684SubSection::), `.popsection' (*note PopSection::), and `.previous' 4685(*note Previous::). 4686 4687 This directive pushes the current section (and subsection) onto the 4688top of the section stack, and then replaces the current section and 4689subsection with `name' and `subsection'. The optional `flags', `type' 4690and `arguments' are treated the same as in the `.section' (*note 4691Section::) directive. 4692 4693 4694File: as.info, Node: Quad, Next: Reloc, Prev: PushSection, Up: Pseudo Ops 4695 46967.96 `.quad BIGNUMS' 4697==================== 4698 4699`.quad' expects zero or more bignums, separated by commas. For each 4700bignum, it emits an 8-byte integer. If the bignum won't fit in 8 4701bytes, it prints a warning message; and just takes the lowest order 8 4702bytes of the bignum. 4703 4704 The term "quad" comes from contexts in which a "word" is two bytes; 4705hence _quad_-word for 8 bytes. 4706 4707 4708File: as.info, Node: Reloc, Next: Rept, Prev: Quad, Up: Pseudo Ops 4709 47107.97 `.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 4711============================================== 4712 4713Generate a relocation at OFFSET of type RELOC_NAME with value 4714EXPRESSION. If OFFSET is a number, the relocation is generated in the 4715current section. If OFFSET is an expression that resolves to a symbol 4716plus offset, the relocation is generated in the given symbol's section. 4717EXPRESSION, if present, must resolve to a symbol plus addend or to an 4718absolute value, but note that not all targets support an addend. e.g. 4719ELF REL targets such as i386 store an addend in the section contents 4720rather than in the relocation. This low level interface does not 4721support addends stored in the section. 4722 4723 4724File: as.info, Node: Rept, Next: Sbttl, Prev: Reloc, Up: Pseudo Ops 4725 47267.98 `.rept COUNT' 4727================== 4728 4729Repeat the sequence of lines between the `.rept' directive and the next 4730`.endr' directive COUNT times. 4731 4732 For example, assembling 4733 4734 .rept 3 4735 .long 0 4736 .endr 4737 4738 is equivalent to assembling 4739 4740 .long 0 4741 .long 0 4742 .long 0 4743 4744 4745File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops 4746 47477.99 `.sbttl "SUBHEADING"' 4748========================== 4749 4750Use SUBHEADING as the title (third line, immediately after the title 4751line) when generating assembly listings. 4752 4753 This directive affects subsequent pages, as well as the current page 4754if it appears within ten lines of the top of a page. 4755 4756 4757File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops 4758 47597.100 `.scl CLASS' 4760================== 4761 4762Set the storage-class value for a symbol. This directive may only be 4763used inside a `.def'/`.endef' pair. Storage class may flag whether a 4764symbol is static or external, or it may record further symbolic 4765debugging information. 4766 4767 4768File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops 4769 47707.101 `.section NAME' 4771===================== 4772 4773Use the `.section' directive to assemble the following code into a 4774section named NAME. 4775 4776 This directive is only supported for targets that actually support 4777arbitrarily named sections; on `a.out' targets, for example, it is not 4778accepted, even with a standard `a.out' section name. 4779 4780COFF Version 4781------------ 4782 4783 For COFF targets, the `.section' directive is used in one of the 4784following ways: 4785 4786 .section NAME[, "FLAGS"] 4787 .section NAME[, SUBSECTION] 4788 4789 If the optional argument is quoted, it is taken as flags to use for 4790the section. Each flag is a single character. The following flags are 4791recognized: 4792`b' 4793 bss section (uninitialized data) 4794 4795`n' 4796 section is not loaded 4797 4798`w' 4799 writable section 4800 4801`d' 4802 data section 4803 4804`e' 4805 exclude section from linking 4806 4807`r' 4808 read-only section 4809 4810`x' 4811 executable section 4812 4813`s' 4814 shared section (meaningful for PE targets) 4815 4816`a' 4817 ignored. (For compatibility with the ELF version) 4818 4819`y' 4820 section is not readable (meaningful for PE targets) 4821 4822`0-9' 4823 single-digit power-of-two section alignment (GNU extension) 4824 4825 If no flags are specified, the default flags depend upon the section 4826name. If the section name is not recognized, the default will be for 4827the section to be loaded and writable. Note the `n' and `w' flags 4828remove attributes from the section, rather than adding them, so if they 4829are used on their own it will be as if no flags had been specified at 4830all. 4831 4832 If the optional argument to the `.section' directive is not quoted, 4833it is taken as a subsection number (*note Sub-Sections::). 4834 4835ELF Version 4836----------- 4837 4838 This is one of the ELF section stack manipulation directives. The 4839others are `.subsection' (*note SubSection::), `.pushsection' (*note 4840PushSection::), `.popsection' (*note PopSection::), and `.previous' 4841(*note Previous::). 4842 4843 For ELF targets, the `.section' directive is used like this: 4844 4845 .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]] 4846 4847 The optional FLAGS argument is a quoted string which may contain any 4848combination of the following characters: 4849`a' 4850 section is allocatable 4851 4852`e' 4853 section is excluded from executable and shared library. 4854 4855`w' 4856 section is writable 4857 4858`x' 4859 section is executable 4860 4861`M' 4862 section is mergeable 4863 4864`S' 4865 section contains zero terminated strings 4866 4867`G' 4868 section is a member of a section group 4869 4870`T' 4871 section is used for thread-local-storage 4872 4873`?' 4874 section is a member of the previously-current section's group, if 4875 any 4876 4877 The optional TYPE argument may contain one of the following 4878constants: 4879`@progbits' 4880 section contains data 4881 4882`@nobits' 4883 section does not contain data (i.e., section only occupies space) 4884 4885`@note' 4886 section contains data which is used by things other than the 4887 program 4888 4889`@init_array' 4890 section contains an array of pointers to init functions 4891 4892`@fini_array' 4893 section contains an array of pointers to finish functions 4894 4895`@preinit_array' 4896 section contains an array of pointers to pre-init functions 4897 4898 Many targets only support the first three section types. 4899 4900 Note on targets where the `@' character is the start of a comment (eg 4901ARM) then another character is used instead. For example the ARM port 4902uses the `%' character. 4903 4904 If FLAGS contains the `M' symbol then the TYPE argument must be 4905specified as well as an extra argument--ENTSIZE--like this: 4906 4907 .section NAME , "FLAGS"M, @TYPE, ENTSIZE 4908 4909 Sections with the `M' flag but not `S' flag must contain fixed size 4910constants, each ENTSIZE octets long. Sections with both `M' and `S' 4911must contain zero terminated strings where each character is ENTSIZE 4912bytes long. The linker may remove duplicates within sections with the 4913same name, same entity size and same flags. ENTSIZE must be an 4914absolute expression. For sections with both `M' and `S', a string 4915which is a suffix of a larger string is considered a duplicate. Thus 4916`"def"' will be merged with `"abcdef"'; A reference to the first 4917`"def"' will be changed to a reference to `"abcdef"+3'. 4918 4919 If FLAGS contains the `G' symbol then the TYPE argument must be 4920present along with an additional field like this: 4921 4922 .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE] 4923 4924 The GROUPNAME field specifies the name of the section group to which 4925this particular section belongs. The optional linkage field can 4926contain: 4927`comdat' 4928 indicates that only one copy of this section should be retained 4929 4930`.gnu.linkonce' 4931 an alias for comdat 4932 4933 Note: if both the M and G flags are present then the fields for the 4934Merge flag should come first, like this: 4935 4936 .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE] 4937 4938 If FLAGS contains the `?' symbol then it may not also contain the 4939`G' symbol and the GROUPNAME or LINKAGE fields should not be present. 4940Instead, `?' says to consider the section that's current before this 4941directive. If that section used `G', then the new section will use `G' 4942with those same GROUPNAME and LINKAGE fields implicitly. If not, then 4943the `?' symbol has no effect. 4944 4945 If no flags are specified, the default flags depend upon the section 4946name. If the section name is not recognized, the default will be for 4947the section to have none of the above flags: it will not be allocated 4948in memory, nor writable, nor executable. The section will contain data. 4949 4950 For ELF targets, the assembler supports another type of `.section' 4951directive for compatibility with the Solaris assembler: 4952 4953 .section "NAME"[, FLAGS...] 4954 4955 Note that the section name is quoted. There may be a sequence of 4956comma separated flags: 4957`#alloc' 4958 section is allocatable 4959 4960`#write' 4961 section is writable 4962 4963`#execinstr' 4964 section is executable 4965 4966`#exclude' 4967 section is excluded from executable and shared library. 4968 4969`#tls' 4970 section is used for thread local storage 4971 4972 This directive replaces the current section and subsection. See the 4973contents of the gas testsuite directory `gas/testsuite/gas/elf' for 4974some examples of how this directive and the other section stack 4975directives work. 4976 4977 4978File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops 4979 49807.102 `.set SYMBOL, EXPRESSION' 4981=============================== 4982 4983Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value and 4984type to conform to EXPRESSION. If SYMBOL was flagged as external, it 4985remains flagged (*note Symbol Attributes::). 4986 4987 You may `.set' a symbol many times in the same assembly. 4988 4989 If you `.set' a global symbol, the value stored in the object file 4990is the last value stored into it. 4991 4992 On Z80 `set' is a real instruction, use `SYMBOL defl EXPRESSION' 4993instead. 4994 4995 4996File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops 4997 49987.103 `.short EXPRESSIONS' 4999========================== 5000 5001`.short' is normally the same as `.word'. *Note `.word': Word. 5002 5003 In some configurations, however, `.short' and `.word' generate 5004numbers of different lengths. *Note Machine Dependencies::. 5005 5006 5007File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops 5008 50097.104 `.single FLONUMS' 5010======================= 5011 5012This directive assembles zero or more flonums, separated by commas. It 5013has the same effect as `.float'. The exact kind of floating point 5014numbers emitted depends on how `as' is configured. *Note Machine 5015Dependencies::. 5016 5017 5018File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops 5019 50207.105 `.size' 5021============= 5022 5023This directive is used to set the size associated with a symbol. 5024 5025COFF Version 5026------------ 5027 5028 For COFF targets, the `.size' directive is only permitted inside 5029`.def'/`.endef' pairs. It is used like this: 5030 5031 .size EXPRESSION 5032 5033ELF Version 5034----------- 5035 5036 For ELF targets, the `.size' directive is used like this: 5037 5038 .size NAME , EXPRESSION 5039 5040 This directive sets the size associated with a symbol NAME. The 5041size in bytes is computed from EXPRESSION which can make use of label 5042arithmetic. This directive is typically used to set the size of 5043function symbols. 5044 5045 5046File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops 5047 50487.106 `.skip SIZE , FILL' 5049========================= 5050 5051This directive emits SIZE bytes, each of value FILL. Both SIZE and 5052FILL are absolute expressions. If the comma and FILL are omitted, FILL 5053is assumed to be zero. This is the same as `.space'. 5054 5055 5056File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops 5057 50587.107 `.sleb128 EXPRESSIONS' 5059============================ 5060 5061SLEB128 stands for "signed little endian base 128." This is a compact, 5062variable length representation of numbers used by the DWARF symbolic 5063debugging format. *Note `.uleb128': Uleb128. 5064 5065 5066File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops 5067 50687.108 `.space SIZE , FILL' 5069========================== 5070 5071This directive emits SIZE bytes, each of value FILL. Both SIZE and 5072FILL are absolute expressions. If the comma and FILL are omitted, FILL 5073is assumed to be zero. This is the same as `.skip'. 5074 5075 _Warning:_ `.space' has a completely different meaning for HPPA 5076 targets; use `.block' as a substitute. See `HP9000 Series 800 5077 Assembly Language Reference Manual' (HP 92432-90001) for the 5078 meaning of the `.space' directive. *Note HPPA Assembler 5079 Directives: HPPA Directives, for a summary. 5080 5081 5082File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops 5083 50847.109 `.stabd, .stabn, .stabs' 5085============================== 5086 5087There are three directives that begin `.stab'. All emit symbols (*note 5088Symbols::), for use by symbolic debuggers. The symbols are not entered 5089in the `as' hash table: they cannot be referenced elsewhere in the 5090source file. Up to five fields are required: 5091 5092STRING 5093 This is the symbol's name. It may contain any character except 5094 `\000', so is more general than ordinary symbol names. Some 5095 debuggers used to code arbitrarily complex structures into symbol 5096 names using this field. 5097 5098TYPE 5099 An absolute expression. The symbol's type is set to the low 8 5100 bits of this expression. Any bit pattern is permitted, but `ld' 5101 and debuggers choke on silly bit patterns. 5102 5103OTHER 5104 An absolute expression. The symbol's "other" attribute is set to 5105 the low 8 bits of this expression. 5106 5107DESC 5108 An absolute expression. The symbol's descriptor is set to the low 5109 16 bits of this expression. 5110 5111VALUE 5112 An absolute expression which becomes the symbol's value. 5113 5114 If a warning is detected while reading a `.stabd', `.stabn', or 5115`.stabs' statement, the symbol has probably already been created; you 5116get a half-formed symbol in your object file. This is compatible with 5117earlier assemblers! 5118 5119`.stabd TYPE , OTHER , DESC' 5120 The "name" of the symbol generated is not even an empty string. 5121 It is a null pointer, for compatibility. Older assemblers used a 5122 null pointer so they didn't waste space in object files with empty 5123 strings. 5124 5125 The symbol's value is set to the location counter, relocatably. 5126 When your program is linked, the value of this symbol is the 5127 address of the location counter when the `.stabd' was assembled. 5128 5129`.stabn TYPE , OTHER , DESC , VALUE' 5130 The name of the symbol is set to the empty string `""'. 5131 5132`.stabs STRING , TYPE , OTHER , DESC , VALUE' 5133 All five fields are specified. 5134 5135 5136File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops 5137 51387.110 `.string' "STR", `.string8' "STR", `.string16' 5139==================================================== 5140 5141"STR", `.string32' "STR", `.string64' "STR" 5142 5143 Copy the characters in STR to the object file. You may specify more 5144than one string to copy, separated by commas. Unless otherwise 5145specified for a particular machine, the assembler marks the end of each 5146string with a 0 byte. You can use any of the escape sequences 5147described in *note Strings: Strings. 5148 5149 The variants `string16', `string32' and `string64' differ from the 5150`string' pseudo opcode in that each 8-bit character from STR is copied 5151and expanded to 16, 32 or 64 bits respectively. The expanded characters 5152are stored in target endianness byte order. 5153 5154 Example: 5155 .string32 "BYE" 5156 expands to: 5157 .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */ 5158 .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */ 5159 5160 5161File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops 5162 51637.111 `.struct EXPRESSION' 5164========================== 5165 5166Switch to the absolute section, and set the section offset to 5167EXPRESSION, which must be an absolute expression. You might use this 5168as follows: 5169 .struct 0 5170 field1: 5171 .struct field1 + 4 5172 field2: 5173 .struct field2 + 4 5174 field3: 5175 This would define the symbol `field1' to have the value 0, the symbol 5176`field2' to have the value 4, and the symbol `field3' to have the value 51778. Assembly would be left in the absolute section, and you would need 5178to use a `.section' directive of some sort to change to some other 5179section before further assembly. 5180 5181 5182File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops 5183 51847.112 `.subsection NAME' 5185======================== 5186 5187This is one of the ELF section stack manipulation directives. The 5188others are `.section' (*note Section::), `.pushsection' (*note 5189PushSection::), `.popsection' (*note PopSection::), and `.previous' 5190(*note Previous::). 5191 5192 This directive replaces the current subsection with `name'. The 5193current section is not changed. The replaced subsection is put onto 5194the section stack in place of the then current top of stack subsection. 5195 5196 5197File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops 5198 51997.113 `.symver' 5200=============== 5201 5202Use the `.symver' directive to bind symbols to specific version nodes 5203within a source file. This is only supported on ELF platforms, and is 5204typically used when assembling files to be linked into a shared library. 5205There are cases where it may make sense to use this in objects to be 5206bound into an application itself so as to override a versioned symbol 5207from a shared library. 5208 5209 For ELF targets, the `.symver' directive can be used like this: 5210 .symver NAME, NAME2@NODENAME 5211 If the symbol NAME is defined within the file being assembled, the 5212`.symver' directive effectively creates a symbol alias with the name 5213NAME2@NODENAME, and in fact the main reason that we just don't try and 5214create a regular alias is that the @ character isn't permitted in 5215symbol names. The NAME2 part of the name is the actual name of the 5216symbol by which it will be externally referenced. The name NAME itself 5217is merely a name of convenience that is used so that it is possible to 5218have definitions for multiple versions of a function within a single 5219source file, and so that the compiler can unambiguously know which 5220version of a function is being mentioned. The NODENAME portion of the 5221alias should be the name of a node specified in the version script 5222supplied to the linker when building a shared library. If you are 5223attempting to override a versioned symbol from a shared library, then 5224NODENAME should correspond to the nodename of the symbol you are trying 5225to override. 5226 5227 If the symbol NAME is not defined within the file being assembled, 5228all references to NAME will be changed to NAME2@NODENAME. If no 5229reference to NAME is made, NAME2@NODENAME will be removed from the 5230symbol table. 5231 5232 Another usage of the `.symver' directive is: 5233 .symver NAME, NAME2@@NODENAME 5234 In this case, the symbol NAME must exist and be defined within the 5235file being assembled. It is similar to NAME2@NODENAME. The difference 5236is NAME2@@NODENAME will also be used to resolve references to NAME2 by 5237the linker. 5238 5239 The third usage of the `.symver' directive is: 5240 .symver NAME, NAME2@@@NODENAME 5241 When NAME is not defined within the file being assembled, it is 5242treated as NAME2@NODENAME. When NAME is defined within the file being 5243assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME. 5244 5245 5246File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops 5247 52487.114 `.tag STRUCTNAME' 5249======================= 5250 5251This directive is generated by compilers to include auxiliary debugging 5252information in the symbol table. It is only permitted inside 5253`.def'/`.endef' pairs. Tags are used to link structure definitions in 5254the symbol table with instances of those structures. 5255 5256 5257File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops 5258 52597.115 `.text SUBSECTION' 5260======================== 5261 5262Tells `as' to assemble the following statements onto the end of the 5263text subsection numbered SUBSECTION, which is an absolute expression. 5264If SUBSECTION is omitted, subsection number zero is used. 5265 5266 5267File: as.info, Node: Title, Next: Type, Prev: Text, Up: Pseudo Ops 5268 52697.116 `.title "HEADING"' 5270======================== 5271 5272Use HEADING as the title (second line, immediately after the source 5273file name and pagenumber) when generating assembly listings. 5274 5275 This directive affects subsequent pages, as well as the current page 5276if it appears within ten lines of the top of a page. 5277 5278 5279File: as.info, Node: Type, Next: Uleb128, Prev: Title, Up: Pseudo Ops 5280 52817.117 `.type' 5282============= 5283 5284This directive is used to set the type of a symbol. 5285 5286COFF Version 5287------------ 5288 5289 For COFF targets, this directive is permitted only within 5290`.def'/`.endef' pairs. It is used like this: 5291 5292 .type INT 5293 5294 This records the integer INT as the type attribute of a symbol table 5295entry. 5296 5297ELF Version 5298----------- 5299 5300 For ELF targets, the `.type' directive is used like this: 5301 5302 .type NAME , TYPE DESCRIPTION 5303 5304 This sets the type of symbol NAME to be either a function symbol or 5305an object symbol. There are five different syntaxes supported for the 5306TYPE DESCRIPTION field, in order to provide compatibility with various 5307other assemblers. 5308 5309 Because some of the characters used in these syntaxes (such as `@' 5310and `#') are comment characters for some architectures, some of the 5311syntaxes below do not work on all architectures. The first variant 5312will be accepted by the GNU assembler on all architectures so that 5313variant should be used for maximum portability, if you do not need to 5314assemble your code with other assemblers. 5315 5316 The syntaxes supported are: 5317 5318 .type <name> STT_<TYPE_IN_UPPER_CASE> 5319 .type <name>,#<type> 5320 .type <name>,@<type> 5321 .type <name>,%<type> 5322 .type <name>,"<type>" 5323 5324 The types supported are: 5325 5326`STT_FUNC' 5327`function' 5328 Mark the symbol as being a function name. 5329 5330`STT_GNU_IFUNC' 5331`gnu_indirect_function' 5332 Mark the symbol as an indirect function when evaluated during reloc 5333 processing. (This is only supported on assemblers targeting GNU 5334 systems). 5335 5336`STT_OBJECT' 5337`object' 5338 Mark the symbol as being a data object. 5339 5340`STT_TLS' 5341`tls_object' 5342 Mark the symbol as being a thead-local data object. 5343 5344`STT_COMMON' 5345`common' 5346 Mark the symbol as being a common data object. 5347 5348`STT_NOTYPE' 5349`notype' 5350 Does not mark the symbol in any way. It is supported just for 5351 completeness. 5352 5353`gnu_unique_object' 5354 Marks the symbol as being a globally unique data object. The 5355 dynamic linker will make sure that in the entire process there is 5356 just one symbol with this name and type in use. (This is only 5357 supported on assemblers targeting GNU systems). 5358 5359 5360 Note: Some targets support extra types in addition to those listed 5361above. 5362 5363 5364File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops 5365 53667.118 `.uleb128 EXPRESSIONS' 5367============================ 5368 5369ULEB128 stands for "unsigned little endian base 128." This is a 5370compact, variable length representation of numbers used by the DWARF 5371symbolic debugging format. *Note `.sleb128': Sleb128. 5372 5373 5374File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops 5375 53767.119 `.val ADDR' 5377================= 5378 5379This directive, permitted only within `.def'/`.endef' pairs, records 5380the address ADDR as the value attribute of a symbol table entry. 5381 5382 5383File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops 5384 53857.120 `.version "STRING"' 5386========================= 5387 5388This directive creates a `.note' section and places into it an ELF 5389formatted note of type NT_VERSION. The note's name is set to `string'. 5390 5391 5392File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops 5393 53947.121 `.vtable_entry TABLE, OFFSET' 5395=================================== 5396 5397This directive finds or creates a symbol `table' and creates a 5398`VTABLE_ENTRY' relocation for it with an addend of `offset'. 5399 5400 5401File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops 5402 54037.122 `.vtable_inherit CHILD, PARENT' 5404===================================== 5405 5406This directive finds the symbol `child' and finds or creates the symbol 5407`parent' and then creates a `VTABLE_INHERIT' relocation for the parent 5408whose addend is the value of the child symbol. As a special case the 5409parent name of `0' is treated as referring to the `*ABS*' section. 5410 5411 5412File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops 5413 54147.123 `.warning "STRING"' 5415========================= 5416 5417Similar to the directive `.error' (*note `.error "STRING"': Error.), 5418but just emits a warning. 5419 5420 5421File: as.info, Node: Weak, Next: Weakref, Prev: Warning, Up: Pseudo Ops 5422 54237.124 `.weak NAMES' 5424=================== 5425 5426This directive sets the weak attribute on the comma separated list of 5427symbol `names'. If the symbols do not already exist, they will be 5428created. 5429 5430 On COFF targets other than PE, weak symbols are a GNU extension. 5431This directive sets the weak attribute on the comma separated list of 5432symbol `names'. If the symbols do not already exist, they will be 5433created. 5434 5435 On the PE target, weak symbols are supported natively as weak 5436aliases. When a weak symbol is created that is not an alias, GAS 5437creates an alternate symbol to hold the default value. 5438 5439 5440File: as.info, Node: Weakref, Next: Word, Prev: Weak, Up: Pseudo Ops 5441 54427.125 `.weakref ALIAS, TARGET' 5443============================== 5444 5445This directive creates an alias to the target symbol that enables the 5446symbol to be referenced with weak-symbol semantics, but without 5447actually making it weak. If direct references or definitions of the 5448symbol are present, then the symbol will not be weak, but if all 5449references to it are through weak references, the symbol will be marked 5450as weak in the symbol table. 5451 5452 The effect is equivalent to moving all references to the alias to a 5453separate assembly source file, renaming the alias to the symbol in it, 5454declaring the symbol as weak there, and running a reloadable link to 5455merge the object files resulting from the assembly of the new source 5456file and the old source file that had the references to the alias 5457removed. 5458 5459 The alias itself never makes to the symbol table, and is entirely 5460handled within the assembler. 5461 5462 5463File: as.info, Node: Word, Next: Deprecated, Prev: Weakref, Up: Pseudo Ops 5464 54657.126 `.word EXPRESSIONS' 5466========================= 5467 5468This directive expects zero or more EXPRESSIONS, of any section, 5469separated by commas. 5470 5471 The size of the number emitted, and its byte order, depend on what 5472target computer the assembly is for. 5473 5474 _Warning: Special Treatment to support Compilers_ 5475 5476 Machines with a 32-bit address space, but that do less than 32-bit 5477addressing, require the following special treatment. If the machine of 5478interest to you does 32-bit addressing (or doesn't require it; *note 5479Machine Dependencies::), you can ignore this issue. 5480 5481 In order to assemble compiler output into something that works, `as' 5482occasionally does strange things to `.word' directives. Directives of 5483the form `.word sym1-sym2' are often emitted by compilers as part of 5484jump tables. Therefore, when `as' assembles a directive of the form 5485`.word sym1-sym2', and the difference between `sym1' and `sym2' does 5486not fit in 16 bits, `as' creates a "secondary jump table", immediately 5487before the next label. This secondary jump table is preceded by a 5488short-jump to the first byte after the secondary table. This 5489short-jump prevents the flow of control from accidentally falling into 5490the new table. Inside the table is a long-jump to `sym2'. The 5491original `.word' contains `sym1' minus the address of the long-jump to 5492`sym2'. 5493 5494 If there were several occurrences of `.word sym1-sym2' before the 5495secondary jump table, all of them are adjusted. If there was a `.word 5496sym3-sym4', that also did not fit in sixteen bits, a long-jump to 5497`sym4' is included in the secondary jump table, and the `.word' 5498directives are adjusted to contain `sym3' minus the address of the 5499long-jump to `sym4'; and so on, for as many entries in the original 5500jump table as necessary. 5501 5502 5503File: as.info, Node: Deprecated, Prev: Word, Up: Pseudo Ops 5504 55057.127 Deprecated Directives 5506=========================== 5507 5508One day these directives won't work. They are included for 5509compatibility with older assemblers. 5510.abort 5511 5512.line 5513 5514 5515File: as.info, Node: Object Attributes, Next: Machine Dependencies, Prev: Pseudo Ops, Up: Top 5516 55178 Object Attributes 5518******************* 5519 5520`as' assembles source files written for a specific architecture into 5521object files for that architecture. But not all object files are alike. 5522Many architectures support incompatible variations. For instance, 5523floating point arguments might be passed in floating point registers if 5524the object file requires hardware floating point support--or floating 5525point arguments might be passed in integer registers if the object file 5526supports processors with no hardware floating point unit. Or, if two 5527objects are built for different generations of the same architecture, 5528the combination may require the newer generation at run-time. 5529 5530 This information is useful during and after linking. At link time, 5531`ld' can warn about incompatible object files. After link time, tools 5532like `gdb' can use it to process the linked file correctly. 5533 5534 Compatibility information is recorded as a series of object 5535attributes. Each attribute has a "vendor", "tag", and "value". The 5536vendor is a string, and indicates who sets the meaning of the tag. The 5537tag is an integer, and indicates what property the attribute describes. 5538The value may be a string or an integer, and indicates how the property 5539affects this object. Missing attributes are the same as attributes 5540with a zero value or empty string value. 5541 5542 Object attributes were developed as part of the ABI for the ARM 5543Architecture. The file format is documented in `ELF for the ARM 5544Architecture'. 5545 5546* Menu: 5547 5548* GNU Object Attributes:: GNU Object Attributes 5549* Defining New Object Attributes:: Defining New Object Attributes 5550 5551 5552File: as.info, Node: GNU Object Attributes, Next: Defining New Object Attributes, Up: Object Attributes 5553 55548.1 GNU Object Attributes 5555========================= 5556 5557The `.gnu_attribute' directive records an object attribute with vendor 5558`gnu'. 5559 5560 Except for `Tag_compatibility', which has both an integer and a 5561string for its value, GNU attributes have a string value if the tag 5562number is odd and an integer value if the tag number is even. The 5563second bit (`TAG & 2' is set for architecture-independent attributes 5564and clear for architecture-dependent ones. 5565 55668.1.1 Common GNU attributes 5567--------------------------- 5568 5569These attributes are valid on all architectures. 5570 5571Tag_compatibility (32) 5572 The compatibility attribute takes an integer flag value and a 5573 vendor name. If the flag value is 0, the file is compatible with 5574 other toolchains. If it is 1, then the file is only compatible 5575 with the named toolchain. If it is greater than 1, the file can 5576 only be processed by other toolchains under some private 5577 arrangement indicated by the flag value and the vendor name. 5578 55798.1.2 MIPS Attributes 5580--------------------- 5581 5582Tag_GNU_MIPS_ABI_FP (4) 5583 The floating-point ABI used by this object file. The value will 5584 be: 5585 5586 * 0 for files not affected by the floating-point ABI. 5587 5588 * 1 for files using the hardware floating-point with a standard 5589 double-precision FPU. 5590 5591 * 2 for files using the hardware floating-point ABI with a 5592 single-precision FPU. 5593 5594 * 3 for files using the software floating-point ABI. 5595 5596 * 4 for files using the hardware floating-point ABI with 64-bit 5597 wide double-precision floating-point registers and 32-bit 5598 wide general purpose registers. 5599 56008.1.3 PowerPC Attributes 5601------------------------ 5602 5603Tag_GNU_Power_ABI_FP (4) 5604 The floating-point ABI used by this object file. The value will 5605 be: 5606 5607 * 0 for files not affected by the floating-point ABI. 5608 5609 * 1 for files using double-precision hardware floating-point 5610 ABI. 5611 5612 * 2 for files using the software floating-point ABI. 5613 5614 * 3 for files using single-precision hardware floating-point 5615 ABI. 5616 5617Tag_GNU_Power_ABI_Vector (8) 5618 The vector ABI used by this object file. The value will be: 5619 5620 * 0 for files not affected by the vector ABI. 5621 5622 * 1 for files using general purpose registers to pass vectors. 5623 5624 * 2 for files using AltiVec registers to pass vectors. 5625 5626 * 3 for files using SPE registers to pass vectors. 5627 5628 5629File: as.info, Node: Defining New Object Attributes, Prev: GNU Object Attributes, Up: Object Attributes 5630 56318.2 Defining New Object Attributes 5632================================== 5633 5634If you want to define a new GNU object attribute, here are the places 5635you will need to modify. New attributes should be discussed on the 5636`binutils' mailing list. 5637 5638 * This manual, which is the official register of attributes. 5639 5640 * The header for your architecture `include/elf', to define the tag. 5641 5642 * The `bfd' support file for your architecture, to merge the 5643 attribute and issue any appropriate link warnings. 5644 5645 * Test cases in `ld/testsuite' for merging and link warnings. 5646 5647 * `binutils/readelf.c' to display your attribute. 5648 5649 * GCC, if you want the compiler to mark the attribute automatically. 5650 5651 5652File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Object Attributes, Up: Top 5653 56549 Machine Dependent Features 5655**************************** 5656 5657The machine instruction sets are (almost by definition) different on 5658each machine where `as' runs. Floating point representations vary as 5659well, and `as' often supports a few additional directives or 5660command-line options for compatibility with other assemblers on a 5661particular platform. Finally, some versions of `as' support special 5662pseudo-instructions for branch optimization. 5663 5664 This chapter discusses most of these differences, though it does not 5665include details on any machine's instruction set. For details on that 5666subject, see the hardware manufacturer's manual. 5667 5668* Menu: 5669 5670 5671* AArch64-Dependent:: AArch64 Dependent Features 5672 5673* Alpha-Dependent:: Alpha Dependent Features 5674 5675* ARC-Dependent:: ARC Dependent Features 5676 5677* ARM-Dependent:: ARM Dependent Features 5678 5679* AVR-Dependent:: AVR Dependent Features 5680 5681* Blackfin-Dependent:: Blackfin Dependent Features 5682 5683* CR16-Dependent:: CR16 Dependent Features 5684 5685* CRIS-Dependent:: CRIS Dependent Features 5686 5687* D10V-Dependent:: D10V Dependent Features 5688 5689* D30V-Dependent:: D30V Dependent Features 5690 5691* Epiphany-Dependent:: EPIPHANY Dependent Features 5692 5693* H8/300-Dependent:: Renesas H8/300 Dependent Features 5694 5695* HPPA-Dependent:: HPPA Dependent Features 5696 5697* ESA/390-Dependent:: IBM ESA/390 Dependent Features 5698 5699* i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features 5700 5701* i860-Dependent:: Intel 80860 Dependent Features 5702 5703* i960-Dependent:: Intel 80960 Dependent Features 5704 5705* IA-64-Dependent:: Intel IA-64 Dependent Features 5706 5707* IP2K-Dependent:: IP2K Dependent Features 5708 5709* LM32-Dependent:: LM32 Dependent Features 5710 5711* M32C-Dependent:: M32C Dependent Features 5712 5713* M32R-Dependent:: M32R Dependent Features 5714 5715* M68K-Dependent:: M680x0 Dependent Features 5716 5717* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features 5718 5719* Meta-Dependent :: Meta Dependent Features 5720 5721* MicroBlaze-Dependent:: MICROBLAZE Dependent Features 5722 5723* MIPS-Dependent:: MIPS Dependent Features 5724 5725* MMIX-Dependent:: MMIX Dependent Features 5726 5727* MSP430-Dependent:: MSP430 Dependent Features 5728 5729* NiosII-Dependent:: Altera Nios II Dependent Features 5730 5731* NS32K-Dependent:: NS32K Dependent Features 5732 5733* SH-Dependent:: Renesas / SuperH SH Dependent Features 5734* SH64-Dependent:: SuperH SH64 Dependent Features 5735 5736* PDP-11-Dependent:: PDP-11 Dependent Features 5737 5738* PJ-Dependent:: picoJava Dependent Features 5739 5740* PPC-Dependent:: PowerPC Dependent Features 5741 5742* RL78-Dependent:: RL78 Dependent Features 5743 5744* RX-Dependent:: RX Dependent Features 5745 5746* S/390-Dependent:: IBM S/390 Dependent Features 5747 5748* SCORE-Dependent:: SCORE Dependent Features 5749 5750* Sparc-Dependent:: SPARC Dependent Features 5751 5752* TIC54X-Dependent:: TI TMS320C54x Dependent Features 5753 5754* TIC6X-Dependent :: TI TMS320C6x Dependent Features 5755 5756* TILE-Gx-Dependent :: Tilera TILE-Gx Dependent Features 5757 5758* TILEPro-Dependent :: Tilera TILEPro Dependent Features 5759 5760* V850-Dependent:: V850 Dependent Features 5761 5762* XGATE-Dependent:: XGATE Features 5763 5764* XSTORMY16-Dependent:: XStormy16 Dependent Features 5765 5766* Xtensa-Dependent:: Xtensa Dependent Features 5767 5768* Z80-Dependent:: Z80 Dependent Features 5769 5770* Z8000-Dependent:: Z8000 Dependent Features 5771 5772* Vax-Dependent:: VAX Dependent Features 5773 5774 5775File: as.info, Node: AArch64-Dependent, Next: Alpha-Dependent, Up: Machine Dependencies 5776 57779.1 AArch64 Dependent Features 5778============================== 5779 5780* Menu: 5781 5782* AArch64 Options:: Options 5783* AArch64 Syntax:: Syntax 5784* AArch64 Floating Point:: Floating Point 5785* AArch64 Directives:: AArch64 Machine Directives 5786* AArch64 Opcodes:: Opcodes 5787* AArch64 Mapping Symbols:: Mapping Symbols 5788 5789 5790File: as.info, Node: AArch64 Options, Next: AArch64 Syntax, Up: AArch64-Dependent 5791 57929.1.1 Options 5793------------- 5794 5795`-EB' 5796 This option specifies that the output generated by the assembler 5797 should be marked as being encoded for a big-endian processor. 5798 5799`-EL' 5800 This option specifies that the output generated by the assembler 5801 should be marked as being encoded for a little-endian processor. 5802 5803`-mabi=ABI' 5804 Specify which ABI the source code uses. The recognized arguments 5805 are: `ilp32' and `lp64', which decides the generated object file 5806 in ELF32 and ELF64 format respectively. The default is `lp64'. 5807 5808 5809 5810File: as.info, Node: AArch64 Syntax, Next: AArch64 Floating Point, Prev: AArch64 Options, Up: AArch64-Dependent 5811 58129.1.2 Syntax 5813------------ 5814 5815* Menu: 5816 5817* AArch64-Chars:: Special Characters 5818* AArch64-Regs:: Register Names 5819* AArch64-Relocations:: Relocations 5820 5821 5822File: as.info, Node: AArch64-Chars, Next: AArch64-Regs, Up: AArch64 Syntax 5823 58249.1.2.1 Special Characters 5825.......................... 5826 5827The presence of a `//' on a line indicates the start of a comment that 5828extends to the end of the current line. If a `#' appears as the first 5829character of a line, the whole line is treated as a comment. 5830 5831 The `;' character can be used instead of a newline to separate 5832statements. 5833 5834 The `#' can be optionally used to indicate immediate operands. 5835 5836 5837File: as.info, Node: AArch64-Regs, Next: AArch64-Relocations, Prev: AArch64-Chars, Up: AArch64 Syntax 5838 58399.1.2.2 Register Names 5840...................... 5841 5842Please refer to the section `4.4 Register Names' of `ARMv8 Instruction 5843Set Overview', which is available at `http://infocenter.arm.com'. 5844 5845 5846File: as.info, Node: AArch64-Relocations, Prev: AArch64-Regs, Up: AArch64 Syntax 5847 58489.1.2.3 Relocations 5849................... 5850 5851Relocations for `MOVZ' and `MOVK' instructions can be generated by 5852prefixing the label with `#:abs_g2:' etc. For example to load the 585348-bit absolute address of FOO into x0: 5854 5855 movz x0, #:abs_g2:foo // bits 32-47, overflow check 5856 movk x0, #:abs_g1_nc:foo // bits 16-31, no overflow check 5857 movk x0, #:abs_g0_nc:foo // bits 0-15, no overflow check 5858 5859 Relocations for `ADRP', and `ADD', `LDR' or `STR' instructions can 5860be generated by prefixing the label with `#:pg_hi21:' and `#:lo12:' 5861respectively. 5862 5863 For example to use 33-bit (+/-4GB) pc-relative addressing to load 5864the address of FOO into x0: 5865 5866 adrp x0, #:pg_hi21:foo 5867 add x0, x0, #:lo12:foo 5868 5869 Or to load the value of FOO into x0: 5870 5871 adrp x0, #:pg_hi21:foo 5872 ldr x0, [x0, #:lo12:foo] 5873 5874 Note that `#:pg_hi21:' is optional. 5875 5876 adrp x0, foo 5877 5878 is equivalent to 5879 5880 adrp x0, #:pg_hi21:foo 5881 5882 5883File: as.info, Node: AArch64 Floating Point, Next: AArch64 Directives, Prev: AArch64 Syntax, Up: AArch64-Dependent 5884 58859.1.3 Floating Point 5886-------------------- 5887 5888The AArch64 architecture uses IEEE floating-point numbers. 5889 5890 5891File: as.info, Node: AArch64 Directives, Next: AArch64 Opcodes, Prev: AArch64 Floating Point, Up: AArch64-Dependent 5892 58939.1.4 AArch64 Machine Directives 5894-------------------------------- 5895 5896`.bss' 5897 This directive switches to the `.bss' section. 5898 5899`.ltorg' 5900 This directive causes the current contents of the literal pool to 5901 be dumped into the current section (which is assumed to be the 5902 .text section) at the current location (aligned to a word 5903 boundary). `GAS' maintains a separate literal pool for each 5904 section and each sub-section. The `.ltorg' directive will only 5905 affect the literal pool of the current section and sub-section. 5906 At the end of assembly all remaining, un-empty literal pools will 5907 automatically be dumped. 5908 5909 Note - older versions of `GAS' would dump the current literal pool 5910 any time a section change occurred. This is no longer done, since 5911 it prevents accurate control of the placement of literal pools. 5912 5913`.pool' 5914 This is a synonym for .ltorg. 5915 5916`NAME .req REGISTER NAME' 5917 This creates an alias for REGISTER NAME called NAME. For example: 5918 5919 foo .req w0 5920 5921`.unreq ALIAS-NAME' 5922 This undefines a register alias which was previously defined using 5923 the `req' directive. For example: 5924 5925 foo .req w0 5926 .unreq foo 5927 5928 An error occurs if the name is undefined. Note - this pseudo op 5929 can be used to delete builtin in register name aliases (eg 'w0'). 5930 This should only be done if it is really necessary. 5931 5932 5933 5934File: as.info, Node: AArch64 Opcodes, Next: AArch64 Mapping Symbols, Prev: AArch64 Directives, Up: AArch64-Dependent 5935 59369.1.5 Opcodes 5937------------- 5938 5939`as' implements all the standard AArch64 opcodes. It also implements 5940several pseudo opcodes, including several synthetic load instructions. 5941 5942`LDR =' 5943 ldr <register> , =<expression> 5944 5945 The constant expression will be placed into the nearest literal 5946 pool (if it not already there) and a PC-relative LDR instruction 5947 will be generated. 5948 5949 5950 For more information on the AArch64 instruction set and assembly 5951language notation, see `ARMv8 Instruction Set Overview' available at 5952`http://infocenter.arm.com'. 5953 5954 5955File: as.info, Node: AArch64 Mapping Symbols, Prev: AArch64 Opcodes, Up: AArch64-Dependent 5956 59579.1.6 Mapping Symbols 5958--------------------- 5959 5960The AArch64 ELF specification requires that special symbols be inserted 5961into object files to mark certain features: 5962 5963`$x' 5964 At the start of a region of code containing AArch64 instructions. 5965 5966`$d' 5967 At the start of a region of data. 5968 5969 5970 5971File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Prev: AArch64-Dependent, Up: Machine Dependencies 5972 59739.2 Alpha Dependent Features 5974============================ 5975 5976* Menu: 5977 5978* Alpha Notes:: Notes 5979* Alpha Options:: Options 5980* Alpha Syntax:: Syntax 5981* Alpha Floating Point:: Floating Point 5982* Alpha Directives:: Alpha Machine Directives 5983* Alpha Opcodes:: Opcodes 5984 5985 5986File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent 5987 59889.2.1 Notes 5989----------- 5990 5991The documentation here is primarily for the ELF object format. `as' 5992also supports the ECOFF and EVAX formats, but features specific to 5993these formats are not yet documented. 5994 5995 5996File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent 5997 59989.2.2 Options 5999------------- 6000 6001`-mCPU' 6002 This option specifies the target processor. If an attempt is made 6003 to assemble an instruction which will not execute on the target 6004 processor, the assembler may either expand the instruction as a 6005 macro or issue an error message. This option is equivalent to the 6006 `.arch' directive. 6007 6008 The following processor names are recognized: `21064', `21064a', 6009 `21066', `21068', `21164', `21164a', `21164pc', `21264', `21264a', 6010 `21264b', `ev4', `ev5', `lca45', `ev5', `ev56', `pca56', `ev6', 6011 `ev67', `ev68'. The special name `all' may be used to allow the 6012 assembler to accept instructions valid for any Alpha processor. 6013 6014 In order to support existing practice in OSF/1 with respect to 6015 `.arch', and existing practice within `MILO' (the Linux ARC 6016 bootloader), the numbered processor names (e.g. 21064) enable the 6017 processor-specific PALcode instructions, while the 6018 "electro-vlasic" names (e.g. `ev4') do not. 6019 6020`-mdebug' 6021`-no-mdebug' 6022 Enables or disables the generation of `.mdebug' encapsulation for 6023 stabs directives and procedure descriptors. The default is to 6024 automatically enable `.mdebug' when the first stabs directive is 6025 seen. 6026 6027`-relax' 6028 This option forces all relocations to be put into the object file, 6029 instead of saving space and resolving some relocations at assembly 6030 time. Note that this option does not propagate all symbol 6031 arithmetic into the object file, because not all symbol arithmetic 6032 can be represented. However, the option can still be useful in 6033 specific applications. 6034 6035`-replace' 6036`-noreplace' 6037 Enables or disables the optimization of procedure calls, both at 6038 assemblage and at link time. These options are only available for 6039 VMS targets and `-replace' is the default. See section 1.4.1 of 6040 the OpenVMS Linker Utility Manual. 6041 6042`-g' 6043 This option is used when the compiler generates debug information. 6044 When `gcc' is using `mips-tfile' to generate debug information for 6045 ECOFF, local labels must be passed through to the object file. 6046 Otherwise this option has no effect. 6047 6048`-GSIZE' 6049 A local common symbol larger than SIZE is placed in `.bss', while 6050 smaller symbols are placed in `.sbss'. 6051 6052`-F' 6053`-32addr' 6054 These options are ignored for backward compatibility. 6055 6056 6057File: as.info, Node: Alpha Syntax, Next: Alpha Floating Point, Prev: Alpha Options, Up: Alpha-Dependent 6058 60599.2.3 Syntax 6060------------ 6061 6062The assembler syntax closely follow the Alpha Reference Manual; 6063assembler directives and general syntax closely follow the OSF/1 and 6064OpenVMS syntax, with a few differences for ELF. 6065 6066* Menu: 6067 6068* Alpha-Chars:: Special Characters 6069* Alpha-Regs:: Register Names 6070* Alpha-Relocs:: Relocations 6071 6072 6073File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax 6074 60759.2.3.1 Special Characters 6076.......................... 6077 6078`#' is the line comment character. Note that if `#' is the first 6079character on a line then it can also be a logical line number directive 6080(*note Comments::) or a preprocessor control command (*note 6081Preprocessing::). 6082 6083 `;' can be used instead of a newline to separate statements. 6084 6085 6086File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax 6087 60889.2.3.2 Register Names 6089...................... 6090 6091The 32 integer registers are referred to as `$N' or `$rN'. In 6092addition, registers 15, 28, 29, and 30 may be referred to by the 6093symbols `$fp', `$at', `$gp', and `$sp' respectively. 6094 6095 The 32 floating-point registers are referred to as `$fN'. 6096 6097 6098File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax 6099 61009.2.3.3 Relocations 6101................... 6102 6103Some of these relocations are available for ECOFF, but mostly only for 6104ELF. They are modeled after the relocation format introduced in 6105Digital Unix 4.0, but there are additions. 6106 6107 The format is `!TAG' or `!TAG!NUMBER' where TAG is the name of the 6108relocation. In some cases NUMBER is used to relate specific 6109instructions. 6110 6111 The relocation is placed at the end of the instruction like so: 6112 6113 ldah $0,a($29) !gprelhigh 6114 lda $0,a($0) !gprellow 6115 ldq $1,b($29) !literal!100 6116 ldl $2,0($1) !lituse_base!100 6117 6118`!literal' 6119`!literal!N' 6120 Used with an `ldq' instruction to load the address of a symbol 6121 from the GOT. 6122 6123 A sequence number N is optional, and if present is used to pair 6124 `lituse' relocations with this `literal' relocation. The `lituse' 6125 relocations are used by the linker to optimize the code based on 6126 the final location of the symbol. 6127 6128 Note that these optimizations are dependent on the data flow of the 6129 program. Therefore, if _any_ `lituse' is paired with a `literal' 6130 relocation, then _all_ uses of the register set by the `literal' 6131 instruction must also be marked with `lituse' relocations. This 6132 is because the original `literal' instruction may be deleted or 6133 transformed into another instruction. 6134 6135 Also note that there may be a one-to-many relationship between 6136 `literal' and `lituse', but not a many-to-one. That is, if there 6137 are two code paths that load up the same address and feed the 6138 value to a single use, then the use may not use a `lituse' 6139 relocation. 6140 6141`!lituse_base!N' 6142 Used with any memory format instruction (e.g. `ldl') to indicate 6143 that the literal is used for an address load. The offset field of 6144 the instruction must be zero. During relaxation, the code may be 6145 altered to use a gp-relative load. 6146 6147`!lituse_jsr!N' 6148 Used with a register branch format instruction (e.g. `jsr') to 6149 indicate that the literal is used for a call. During relaxation, 6150 the code may be altered to use a direct branch (e.g. `bsr'). 6151 6152`!lituse_jsrdirect!N' 6153 Similar to `lituse_jsr', but also that this call cannot be vectored 6154 through a PLT entry. This is useful for functions with special 6155 calling conventions which do not allow the normal call-clobbered 6156 registers to be clobbered. 6157 6158`!lituse_bytoff!N' 6159 Used with a byte mask instruction (e.g. `extbl') to indicate that 6160 only the low 3 bits of the address are relevant. During 6161 relaxation, the code may be altered to use an immediate instead of 6162 a register shift. 6163 6164`!lituse_addr!N' 6165 Used with any other instruction to indicate that the original 6166 address is in fact used, and the original `ldq' instruction may 6167 not be altered or deleted. This is useful in conjunction with 6168 `lituse_jsr' to test whether a weak symbol is defined. 6169 6170 ldq $27,foo($29) !literal!1 6171 beq $27,is_undef !lituse_addr!1 6172 jsr $26,($27),foo !lituse_jsr!1 6173 6174`!lituse_tlsgd!N' 6175 Used with a register branch format instruction to indicate that the 6176 literal is the call to `__tls_get_addr' used to compute the 6177 address of the thread-local storage variable whose descriptor was 6178 loaded with `!tlsgd!N'. 6179 6180`!lituse_tlsldm!N' 6181 Used with a register branch format instruction to indicate that the 6182 literal is the call to `__tls_get_addr' used to compute the 6183 address of the base of the thread-local storage block for the 6184 current module. The descriptor for the module must have been 6185 loaded with `!tlsldm!N'. 6186 6187`!gpdisp!N' 6188 Used with `ldah' and `lda' to load the GP from the current 6189 address, a-la the `ldgp' macro. The source register for the 6190 `ldah' instruction must contain the address of the `ldah' 6191 instruction. There must be exactly one `lda' instruction paired 6192 with the `ldah' instruction, though it may appear anywhere in the 6193 instruction stream. The immediate operands must be zero. 6194 6195 bsr $26,foo 6196 ldah $29,0($26) !gpdisp!1 6197 lda $29,0($29) !gpdisp!1 6198 6199`!gprelhigh' 6200 Used with an `ldah' instruction to add the high 16 bits of a 6201 32-bit displacement from the GP. 6202 6203`!gprellow' 6204 Used with any memory format instruction to add the low 16 bits of a 6205 32-bit displacement from the GP. 6206 6207`!gprel' 6208 Used with any memory format instruction to add a 16-bit 6209 displacement from the GP. 6210 6211`!samegp' 6212 Used with any branch format instruction to skip the GP load at the 6213 target address. The referenced symbol must have the same GP as the 6214 source object file, and it must be declared to either not use `$27' 6215 or perform a standard GP load in the first two instructions via the 6216 `.prologue' directive. 6217 6218`!tlsgd' 6219`!tlsgd!N' 6220 Used with an `lda' instruction to load the address of a TLS 6221 descriptor for a symbol in the GOT. 6222 6223 The sequence number N is optional, and if present it used to pair 6224 the descriptor load with both the `literal' loading the address of 6225 the `__tls_get_addr' function and the `lituse_tlsgd' marking the 6226 call to that function. 6227 6228 For proper relaxation, both the `tlsgd', `literal' and `lituse' 6229 relocations must be in the same extended basic block. That is, 6230 the relocation with the lowest address must be executed first at 6231 runtime. 6232 6233`!tlsldm' 6234`!tlsldm!N' 6235 Used with an `lda' instruction to load the address of a TLS 6236 descriptor for the current module in the GOT. 6237 6238 Similar in other respects to `tlsgd'. 6239 6240`!gotdtprel' 6241 Used with an `ldq' instruction to load the offset of the TLS 6242 symbol within its module's thread-local storage block. Also known 6243 as the dynamic thread pointer offset or dtp-relative offset. 6244 6245`!dtprelhi' 6246`!dtprello' 6247`!dtprel' 6248 Like `gprel' relocations except they compute dtp-relative offsets. 6249 6250`!gottprel' 6251 Used with an `ldq' instruction to load the offset of the TLS 6252 symbol from the thread pointer. Also known as the tp-relative 6253 offset. 6254 6255`!tprelhi' 6256`!tprello' 6257`!tprel' 6258 Like `gprel' relocations except they compute tp-relative offsets. 6259 6260 6261File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent 6262 62639.2.4 Floating Point 6264-------------------- 6265 6266The Alpha family uses both IEEE and VAX floating-point numbers. 6267 6268 6269File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Floating Point, Up: Alpha-Dependent 6270 62719.2.5 Alpha Assembler Directives 6272-------------------------------- 6273 6274`as' for the Alpha supports many additional directives for 6275compatibility with the native assembler. This section describes them 6276only briefly. 6277 6278 These are the additional directives in `as' for the Alpha: 6279 6280`.arch CPU' 6281 Specifies the target processor. This is equivalent to the `-mCPU' 6282 command-line option. *Note Options: Alpha Options, for a list of 6283 values for CPU. 6284 6285`.ent FUNCTION[, N]' 6286 Mark the beginning of FUNCTION. An optional number may follow for 6287 compatibility with the OSF/1 assembler, but is ignored. When 6288 generating `.mdebug' information, this will create a procedure 6289 descriptor for the function. In ELF, it will mark the symbol as a 6290 function a-la the generic `.type' directive. 6291 6292`.end FUNCTION' 6293 Mark the end of FUNCTION. In ELF, it will set the size of the 6294 symbol a-la the generic `.size' directive. 6295 6296`.mask MASK, OFFSET' 6297 Indicate which of the integer registers are saved in the current 6298 function's stack frame. MASK is interpreted a bit mask in which 6299 bit N set indicates that register N is saved. The registers are 6300 saved in a block located OFFSET bytes from the "canonical frame 6301 address" (CFA) which is the value of the stack pointer on entry to 6302 the function. The registers are saved sequentially, except that 6303 the return address register (normally `$26') is saved first. 6304 6305 This and the other directives that describe the stack frame are 6306 currently only used when generating `.mdebug' information. They 6307 may in the future be used to generate DWARF2 `.debug_frame' unwind 6308 information for hand written assembly. 6309 6310`.fmask MASK, OFFSET' 6311 Indicate which of the floating-point registers are saved in the 6312 current stack frame. The MASK and OFFSET parameters are 6313 interpreted as with `.mask'. 6314 6315`.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]' 6316 Describes the shape of the stack frame. The frame pointer in use 6317 is FRAMEREG; normally this is either `$fp' or `$sp'. The frame 6318 pointer is FRAMEOFFSET bytes below the CFA. The return address is 6319 initially located in RETREG until it is saved as indicated in 6320 `.mask'. For compatibility with OSF/1 an optional ARGOFFSET 6321 parameter is accepted and ignored. It is believed to indicate the 6322 offset from the CFA to the saved argument registers. 6323 6324`.prologue N' 6325 Indicate that the stack frame is set up and all registers have been 6326 spilled. The argument N indicates whether and how the function 6327 uses the incoming "procedure vector" (the address of the called 6328 function) in `$27'. 0 indicates that `$27' is not used; 1 6329 indicates that the first two instructions of the function use `$27' 6330 to perform a load of the GP register; 2 indicates that `$27' is 6331 used in some non-standard way and so the linker cannot elide the 6332 load of the procedure vector during relaxation. 6333 6334`.usepv FUNCTION, WHICH' 6335 Used to indicate the use of the `$27' register, similar to 6336 `.prologue', but without the other semantics of needing to be 6337 inside an open `.ent'/`.end' block. 6338 6339 The WHICH argument should be either `no', indicating that `$27' is 6340 not used, or `std', indicating that the first two instructions of 6341 the function perform a GP load. 6342 6343 One might use this directive instead of `.prologue' if you are 6344 also using dwarf2 CFI directives. 6345 6346`.gprel32 EXPRESSION' 6347 Computes the difference between the address in EXPRESSION and the 6348 GP for the current object file, and stores it in 4 bytes. In 6349 addition to being smaller than a full 8 byte address, this also 6350 does not require a dynamic relocation when used in a shared 6351 library. 6352 6353`.t_floating EXPRESSION' 6354 Stores EXPRESSION as an IEEE double precision value. 6355 6356`.s_floating EXPRESSION' 6357 Stores EXPRESSION as an IEEE single precision value. 6358 6359`.f_floating EXPRESSION' 6360 Stores EXPRESSION as a VAX F format value. 6361 6362`.g_floating EXPRESSION' 6363 Stores EXPRESSION as a VAX G format value. 6364 6365`.d_floating EXPRESSION' 6366 Stores EXPRESSION as a VAX D format value. 6367 6368`.set FEATURE' 6369 Enables or disables various assembler features. Using the positive 6370 name of the feature enables while using `noFEATURE' disables. 6371 6372 `at' 6373 Indicates that macro expansions may clobber the "assembler 6374 temporary" (`$at' or `$28') register. Some macros may not be 6375 expanded without this and will generate an error message if 6376 `noat' is in effect. When `at' is in effect, a warning will 6377 be generated if `$at' is used by the programmer. 6378 6379 `macro' 6380 Enables the expansion of macro instructions. Note that 6381 variants of real instructions, such as `br label' vs `br 6382 $31,label' are considered alternate forms and not macros. 6383 6384 `move' 6385 `reorder' 6386 `volatile' 6387 These control whether and how the assembler may re-order 6388 instructions. Accepted for compatibility with the OSF/1 6389 assembler, but `as' does not do instruction scheduling, so 6390 these features are ignored. 6391 6392 The following directives are recognized for compatibility with the 6393OSF/1 assembler but are ignored. 6394 6395 .proc .aproc 6396 .reguse .livereg 6397 .option .aent 6398 .ugen .eflag 6399 .alias .noalias 6400 6401 6402File: as.info, Node: Alpha Opcodes, Prev: Alpha Directives, Up: Alpha-Dependent 6403 64049.2.6 Opcodes 6405------------- 6406 6407For detailed information on the Alpha machine instruction set, see the 6408Alpha Architecture Handbook 6409(ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf). 6410 6411 6412File: as.info, Node: ARC-Dependent, Next: ARM-Dependent, Prev: Alpha-Dependent, Up: Machine Dependencies 6413 64149.3 ARC Dependent Features 6415========================== 6416 6417* Menu: 6418 6419* ARC Options:: Options 6420* ARC Syntax:: Syntax 6421* ARC Floating Point:: Floating Point 6422* ARC Directives:: ARC Machine Directives 6423* ARC Opcodes:: Opcodes 6424 6425 6426File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent 6427 64289.3.1 Options 6429------------- 6430 6431`-marc[5|6|7|8]' 6432 This option selects the core processor variant. Using `-marc' is 6433 the same as `-marc6', which is also the default. 6434 6435 `arc5' 6436 Base instruction set. 6437 6438 `arc6' 6439 Jump-and-link (jl) instruction. No requirement of an 6440 instruction between setting flags and conditional jump. For 6441 example: 6442 6443 mov.f r0,r1 6444 beq foo 6445 6446 `arc7' 6447 Break (brk) and sleep (sleep) instructions. 6448 6449 `arc8' 6450 Software interrupt (swi) instruction. 6451 6452 6453 Note: the `.option' directive can to be used to select a core 6454 variant from within assembly code. 6455 6456`-EB' 6457 This option specifies that the output generated by the assembler 6458 should be marked as being encoded for a big-endian processor. 6459 6460`-EL' 6461 This option specifies that the output generated by the assembler 6462 should be marked as being encoded for a little-endian processor - 6463 this is the default. 6464 6465 6466 6467File: as.info, Node: ARC Syntax, Next: ARC Floating Point, Prev: ARC Options, Up: ARC-Dependent 6468 64699.3.2 Syntax 6470------------ 6471 6472* Menu: 6473 6474* ARC-Chars:: Special Characters 6475* ARC-Regs:: Register Names 6476 6477 6478File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax 6479 64809.3.2.1 Special Characters 6481.......................... 6482 6483The presence of a `#' on a line indicates the start of a comment that 6484extends to the end of the current line. Note that if a line starts 6485with a `#' character then it can also be a logical line number 6486directive (*note Comments::) or a preprocessor control command (*note 6487Preprocessing::). 6488 6489 The ARC assembler does not support a line separator character. 6490 6491 6492File: as.info, Node: ARC-Regs, Prev: ARC-Chars, Up: ARC Syntax 6493 64949.3.2.2 Register Names 6495...................... 6496 6497*TODO* 6498 6499 6500File: as.info, Node: ARC Floating Point, Next: ARC Directives, Prev: ARC Syntax, Up: ARC-Dependent 6501 65029.3.3 Floating Point 6503-------------------- 6504 6505The ARC core does not currently have hardware floating point support. 6506Software floating point support is provided by `GCC' and uses IEEE 6507floating-point numbers. 6508 6509 6510File: as.info, Node: ARC Directives, Next: ARC Opcodes, Prev: ARC Floating Point, Up: ARC-Dependent 6511 65129.3.4 ARC Machine Directives 6513---------------------------- 6514 6515The ARC version of `as' supports the following additional machine 6516directives: 6517 6518`.2byte EXPRESSIONS' 6519 *TODO* 6520 6521`.3byte EXPRESSIONS' 6522 *TODO* 6523 6524`.4byte EXPRESSIONS' 6525 *TODO* 6526 6527`.extAuxRegister NAME,ADDRESS,MODE' 6528 The ARCtangent A4 has extensible auxiliary register space. The 6529 auxiliary registers can be defined in the assembler source code by 6530 using this directive. The first parameter is the NAME of the new 6531 auxiallry register. The second parameter is the ADDRESS of the 6532 register in the auxiliary register memory map for the variant of 6533 the ARC. The third parameter specifies the MODE in which the 6534 register can be operated is and it can be one of: 6535 6536 `r (readonly)' 6537 6538 `w (write only)' 6539 6540 `r|w (read or write)' 6541 6542 For example: 6543 6544 .extAuxRegister mulhi,0x12,w 6545 6546 This specifies an extension auxiliary register called _mulhi_ 6547 which is at address 0x12 in the memory space and which is only 6548 writable. 6549 6550`.extCondCode SUFFIX,VALUE' 6551 The condition codes on the ARCtangent A4 are extensible and can be 6552 specified by means of this assembler directive. They are specified 6553 by the suffix and the value for the condition code. They can be 6554 used to specify extra condition codes with any values. For 6555 example: 6556 6557 .extCondCode is_busy,0x14 6558 6559 add.is_busy r1,r2,r3 6560 bis_busy _main 6561 6562`.extCoreRegister NAME,REGNUM,MODE,SHORTCUT' 6563 Specifies an extension core register NAME for the application. 6564 This allows a register NAME with a valid REGNUM between 0 and 60, 6565 with the following as valid values for MODE 6566 6567 `_r_ (readonly)' 6568 6569 `_w_ (write only)' 6570 6571 `_r|w_ (read or write)' 6572 6573 The other parameter gives a description of the register having a 6574 SHORTCUT in the pipeline. The valid values are: 6575 6576 `can_shortcut' 6577 6578 `cannot_shortcut' 6579 6580 For example: 6581 6582 .extCoreRegister mlo,57,r,can_shortcut 6583 6584 This defines an extension core register mlo with the value 57 which 6585 can shortcut the pipeline. 6586 6587`.extInstruction NAME,OPCODE,SUBOPCODE,SUFFIXCLASS,SYNTAXCLASS' 6588 The ARCtangent A4 allows the user to specify extension 6589 instructions. The extension instructions are not macros. The 6590 assembler creates encodings for use of these instructions 6591 according to the specification by the user. The parameters are: 6592 6593 * NAME Name of the extension instruction 6594 6595 * OPCODE Opcode to be used. (Bits 27:31 in the encoding). 6596 Valid values 0x10-0x1f or 0x03 6597 6598 * SUBOPCODE Subopcode to be used. Valid values are from 6599 0x09-0x3f. However the correct value also depends on 6600 SYNTAXCLASS 6601 6602 * SUFFIXCLASS Determines the kinds of suffixes to be allowed. 6603 Valid values are `SUFFIX_NONE', `SUFFIX_COND', `SUFFIX_FLAG' 6604 which indicates the absence or presence of conditional 6605 suffixes and flag setting by the extension instruction. It 6606 is also possible to specify that an instruction sets the 6607 flags and is conditional by using `SUFFIX_CODE' | 6608 `SUFFIX_FLAG'. 6609 6610 * SYNTAXCLASS Determines the syntax class for the instruction. 6611 It can have the following values: 6612 6613 ``SYNTAX_2OP':' 6614 2 Operand Instruction 6615 6616 ``SYNTAX_3OP':' 6617 3 Operand Instruction 6618 6619 In addition there could be modifiers for the syntax class as 6620 described below: 6621 6622 Syntax Class Modifiers are: 6623 6624 - `OP1_MUST_BE_IMM': Modifies syntax class SYNTAX_3OP, 6625 specifying that the first operand of a three-operand 6626 instruction must be an immediate (i.e., the result is 6627 discarded). OP1_MUST_BE_IMM is used by bitwise ORing it 6628 with SYNTAX_3OP as given in the example below. This 6629 could usually be used to set the flags using specific 6630 instructions and not retain results. 6631 6632 - `OP1_IMM_IMPLIED': Modifies syntax class SYNTAX_20P, it 6633 specifies that there is an implied immediate destination 6634 operand which does not appear in the syntax. For 6635 example, if the source code contains an instruction like: 6636 6637 inst r1,r2 6638 6639 it really means that the first argument is an implied 6640 immediate (that is, the result is discarded). This is 6641 the same as though the source code were: inst 0,r1,r2. 6642 You use OP1_IMM_IMPLIED by bitwise ORing it with 6643 SYNTAX_20P. 6644 6645 6646 For example, defining 64-bit multiplier with immediate operands: 6647 6648 .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG , 6649 SYNTAX_3OP|OP1_MUST_BE_IMM 6650 6651 The above specifies an extension instruction called mp64 which has 6652 3 operands, sets the flags, can be used with a condition code, for 6653 which the first operand is an immediate. (Equivalent to 6654 discarding the result of the operation). 6655 6656 .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED 6657 6658 This describes a 2 operand instruction with an implicit first 6659 immediate operand. The result of this operation would be 6660 discarded. 6661 6662`.half EXPRESSIONS' 6663 *TODO* 6664 6665`.long EXPRESSIONS' 6666 *TODO* 6667 6668`.option ARC|ARC5|ARC6|ARC7|ARC8' 6669 The `.option' directive must be followed by the desired core 6670 version. Again `arc' is an alias for `arc6'. 6671 6672 Note: the `.option' directive overrides the command line option 6673 `-marc'; a warning is emitted when the version is not consistent 6674 between the two - even for the implicit default core version 6675 (arc6). 6676 6677`.short EXPRESSIONS' 6678 *TODO* 6679 6680`.word EXPRESSIONS' 6681 *TODO* 6682 6683 6684 6685File: as.info, Node: ARC Opcodes, Prev: ARC Directives, Up: ARC-Dependent 6686 66879.3.5 Opcodes 6688------------- 6689 6690For information on the ARC instruction set, see `ARC Programmers 6691Reference Manual', ARC International (www.arc.com) 6692 6693 6694File: as.info, Node: ARM-Dependent, Next: AVR-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies 6695 66969.4 ARM Dependent Features 6697========================== 6698 6699* Menu: 6700 6701* ARM Options:: Options 6702* ARM Syntax:: Syntax 6703* ARM Floating Point:: Floating Point 6704* ARM Directives:: ARM Machine Directives 6705* ARM Opcodes:: Opcodes 6706* ARM Mapping Symbols:: Mapping Symbols 6707* ARM Unwinding Tutorial:: Unwinding 6708 6709 6710File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent 6711 67129.4.1 Options 6713------------- 6714 6715`-mcpu=PROCESSOR[+EXTENSION...]' 6716 This option specifies the target processor. The assembler will 6717 issue an error message if an attempt is made to assemble an 6718 instruction which will not execute on the target processor. The 6719 following processor names are recognized: `arm1', `arm2', `arm250', 6720 `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7', 6721 `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700', 6722 `arm700i', `arm710', `arm710t', `arm720', `arm720t', `arm740t', 6723 `arm710c', `arm7100', `arm7500', `arm7500fe', `arm7t', `arm7tdmi', 6724 `arm7tdmi-s', `arm8', `arm810', `strongarm', `strongarm1', 6725 `strongarm110', `strongarm1100', `strongarm1110', `arm9', `arm920', 6726 `arm920t', `arm922t', `arm940t', `arm9tdmi', `fa526' (Faraday 6727 FA526 processor), `fa626' (Faraday FA626 processor), `arm9e', 6728 `arm926e', `arm926ej-s', `arm946e-r0', `arm946e', `arm946e-s', 6729 `arm966e-r0', `arm966e', `arm966e-s', `arm968e-s', `arm10t', 6730 `arm10tdmi', `arm10e', `arm1020', `arm1020t', `arm1020e', 6731 `arm1022e', `arm1026ej-s', `fa606te' (Faraday FA606TE processor), 6732 `fa616te' (Faraday FA616TE processor), `fa626te' (Faraday FA626TE 6733 processor), `fmp626' (Faraday FMP626 processor), `fa726te' 6734 (Faraday FA726TE processor), `arm1136j-s', `arm1136jf-s', 6735 `arm1156t2-s', `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s', 6736 `mpcore', `mpcorenovfp', `cortex-a5', `cortex-a7', `cortex-a8', 6737 `cortex-a9', `cortex-a15', `cortex-r4', `cortex-r4f', `cortex-r5', 6738 `cortex-r7', `cortex-m4', `cortex-m3', `cortex-m1', `cortex-m0', 6739 `cortex-m0plus', `ep9312' (ARM920 with Cirrus Maverick 6740 coprocessor), `i80200' (Intel XScale processor) `iwmmxt' (Intel(r) 6741 XScale processor with Wireless MMX(tm) technology coprocessor) and 6742 `xscale'. The special name `all' may be used to allow the 6743 assembler to accept instructions valid for any ARM processor. 6744 6745 In addition to the basic instruction set, the assembler can be 6746 told to accept various extension mnemonics that extend the 6747 processor using the co-processor instruction space. For example, 6748 `-mcpu=arm920+maverick' is equivalent to specifying `-mcpu=ep9312'. 6749 6750 Multiple extensions may be specified, separated by a `+'. The 6751 extensions should be specified in ascending alphabetical order. 6752 6753 Some extensions may be restricted to particular architectures; 6754 this is documented in the list of extensions below. 6755 6756 Extension mnemonics may also be removed from those the assembler 6757 accepts. This is done be prepending `no' to the option that adds 6758 the extension. Extensions that are removed should be listed after 6759 all extensions which have been added, again in ascending 6760 alphabetical order. For example, `-mcpu=ep9312+nomaverick' is 6761 equivalent to specifying `-mcpu=arm920'. 6762 6763 The following extensions are currently supported: `crypto' 6764 (Cryptography Extensions for v8-A architecture, implies `fp+simd'), 6765 `fp' (Floating Point Extensions for v8-A architecture), `idiv' 6766 (Integer Divide Extensions for v7-A and v7-R architectures), 6767 `iwmmxt', `iwmmxt2', `maverick', `mp' (Multiprocessing Extensions 6768 for v7-A and v7-R architectures), `os' (Operating System for v6M 6769 architecture), `sec' (Security Extensions for v6K and v7-A 6770 architectures), `simd' (Advanced SIMD Extensions for v8-A 6771 architecture, implies `fp'), `virt' (Virtualization Extensions for 6772 v7-A architecture, implies `idiv'), and `xscale'. 6773 6774`-march=ARCHITECTURE[+EXTENSION...]' 6775 This option specifies the target architecture. The assembler will 6776 issue an error message if an attempt is made to assemble an 6777 instruction which will not execute on the target architecture. 6778 The following architecture names are recognized: `armv1', `armv2', 6779 `armv2a', `armv2s', `armv3', `armv3m', `armv4', `armv4xm', 6780 `armv4t', `armv4txm', `armv5', `armv5t', `armv5txm', `armv5te', 6781 `armv5texp', `armv6', `armv6j', `armv6k', `armv6z', `armv6zk', 6782 `armv6-m', `armv6s-m', `armv7', `armv7-a', `armv7-r', `armv7-m', 6783 `armv7e-m', `armv8-a', `iwmmxt' and `xscale'. If both `-mcpu' and 6784 `-march' are specified, the assembler will use the setting for 6785 `-mcpu'. 6786 6787 The architecture option can be extended with the same instruction 6788 set extension options as the `-mcpu' option. 6789 6790`-mfpu=FLOATING-POINT-FORMAT' 6791 This option specifies the floating point format to assemble for. 6792 The assembler will issue an error message if an attempt is made to 6793 assemble an instruction which will not execute on the target 6794 floating point unit. The following format options are recognized: 6795 `softfpa', `fpe', `fpe2', `fpe3', `fpa', `fpa10', `fpa11', 6796 `arm7500fe', `softvfp', `softvfp+vfp', `vfp', `vfp10', `vfp10-r0', 6797 `vfp9', `vfpxd', `vfpv2', `vfpv3', `vfpv3-fp16', `vfpv3-d16', 6798 `vfpv3-d16-fp16', `vfpv3xd', `vfpv3xd-d16', `vfpv4', `vfpv4-d16', 6799 `fpv4-sp-d16', `fp-armv8', `arm1020t', `arm1020e', `arm1136jf-s', 6800 `maverick', `neon', `neon-vfpv4', `neon-fp-armv8', and 6801 `crypto-neon-fp-armv8'. 6802 6803 In addition to determining which instructions are assembled, this 6804 option also affects the way in which the `.double' assembler 6805 directive behaves when assembling little-endian code. 6806 6807 The default is dependent on the processor selected. For 6808 Architecture 5 or later, the default is to assembler for VFP 6809 instructions; for earlier architectures the default is to assemble 6810 for FPA instructions. 6811 6812`-mthumb' 6813 This option specifies that the assembler should start assembling 6814 Thumb instructions; that is, it should behave as though the file 6815 starts with a `.code 16' directive. 6816 6817`-mthumb-interwork' 6818 This option specifies that the output generated by the assembler 6819 should be marked as supporting interworking. 6820 6821`-mimplicit-it=never' 6822`-mimplicit-it=always' 6823`-mimplicit-it=arm' 6824`-mimplicit-it=thumb' 6825 The `-mimplicit-it' option controls the behavior of the assembler 6826 when conditional instructions are not enclosed in IT blocks. 6827 There are four possible behaviors. If `never' is specified, such 6828 constructs cause a warning in ARM code and an error in Thumb-2 6829 code. If `always' is specified, such constructs are accepted in 6830 both ARM and Thumb-2 code, where the IT instruction is added 6831 implicitly. If `arm' is specified, such constructs are accepted 6832 in ARM code and cause an error in Thumb-2 code. If `thumb' is 6833 specified, such constructs cause a warning in ARM code and are 6834 accepted in Thumb-2 code. If you omit this option, the behavior 6835 is equivalent to `-mimplicit-it=arm'. 6836 6837`-mapcs-26' 6838`-mapcs-32' 6839 These options specify that the output generated by the assembler 6840 should be marked as supporting the indicated version of the Arm 6841 Procedure. Calling Standard. 6842 6843`-matpcs' 6844 This option specifies that the output generated by the assembler 6845 should be marked as supporting the Arm/Thumb Procedure Calling 6846 Standard. If enabled this option will cause the assembler to 6847 create an empty debugging section in the object file called 6848 .arm.atpcs. Debuggers can use this to determine the ABI being 6849 used by. 6850 6851`-mapcs-float' 6852 This indicates the floating point variant of the APCS should be 6853 used. In this variant floating point arguments are passed in FP 6854 registers rather than integer registers. 6855 6856`-mapcs-reentrant' 6857 This indicates that the reentrant variant of the APCS should be 6858 used. This variant supports position independent code. 6859 6860`-mfloat-abi=ABI' 6861 This option specifies that the output generated by the assembler 6862 should be marked as using specified floating point ABI. The 6863 following values are recognized: `soft', `softfp' and `hard'. 6864 6865`-meabi=VER' 6866 This option specifies which EABI version the produced object files 6867 should conform to. The following values are recognized: `gnu', `4' 6868 and `5'. 6869 6870`-EB' 6871 This option specifies that the output generated by the assembler 6872 should be marked as being encoded for a big-endian processor. 6873 6874`-EL' 6875 This option specifies that the output generated by the assembler 6876 should be marked as being encoded for a little-endian processor. 6877 6878`-k' 6879 This option specifies that the output of the assembler should be 6880 marked as position-independent code (PIC). 6881 6882`--fix-v4bx' 6883 Allow `BX' instructions in ARMv4 code. This is intended for use 6884 with the linker option of the same name. 6885 6886`-mwarn-deprecated' 6887`-mno-warn-deprecated' 6888 Enable or disable warnings about using deprecated options or 6889 features. The default is to warn. 6890 6891 6892 6893File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent 6894 68959.4.2 Syntax 6896------------ 6897 6898* Menu: 6899 6900* ARM-Instruction-Set:: Instruction Set 6901* ARM-Chars:: Special Characters 6902* ARM-Regs:: Register Names 6903* ARM-Relocations:: Relocations 6904* ARM-Neon-Alignment:: NEON Alignment Specifiers 6905 6906 6907File: as.info, Node: ARM-Instruction-Set, Next: ARM-Chars, Up: ARM Syntax 6908 69099.4.2.1 Instruction Set Syntax 6910.............................. 6911 6912Two slightly different syntaxes are support for ARM and THUMB 6913instructions. The default, `divided', uses the old style where ARM and 6914THUMB instructions had their own, separate syntaxes. The new, 6915`unified' syntax, which can be selected via the `.syntax' directive, 6916and has the following main features: 6917 6918 * Immediate operands do not require a `#' prefix. 6919 6920 * The `IT' instruction may appear, and if it does it is validated 6921 against subsequent conditional affixes. In ARM mode it does not 6922 generate machine code, in THUMB mode it does. 6923 6924 * For ARM instructions the conditional affixes always appear at the 6925 end of the instruction. For THUMB instructions conditional 6926 affixes can be used, but only inside the scope of an `IT' 6927 instruction. 6928 6929 * All of the instructions new to the V6T2 architecture (and later) 6930 are available. (Only a few such instructions can be written in the 6931 `divided' syntax). 6932 6933 * The `.N' and `.W' suffixes are recognized and honored. 6934 6935 * All instructions set the flags if and only if they have an `s' 6936 affix. 6937 6938 6939File: as.info, Node: ARM-Chars, Next: ARM-Regs, Prev: ARM-Instruction-Set, Up: ARM Syntax 6940 69419.4.2.2 Special Characters 6942.......................... 6943 6944The presence of a `@' anywhere on a line indicates the start of a 6945comment that extends to the end of that line. 6946 6947 If a `#' appears as the first character of a line then the whole 6948line is treated as a comment, but in this case the line could also be a 6949logical line number directive (*note Comments::) or a preprocessor 6950control command (*note Preprocessing::). 6951 6952 The `;' character can be used instead of a newline to separate 6953statements. 6954 6955 Either `#' or `$' can be used to indicate immediate operands. 6956 6957 *TODO* Explain about /data modifier on symbols. 6958 6959 6960File: as.info, Node: ARM-Regs, Next: ARM-Relocations, Prev: ARM-Chars, Up: ARM Syntax 6961 69629.4.2.3 Register Names 6963...................... 6964 6965*TODO* Explain about ARM register naming, and the predefined names. 6966 6967 6968File: as.info, Node: ARM-Relocations, Next: ARM-Neon-Alignment, Prev: ARM-Regs, Up: ARM Syntax 6969 69709.4.2.4 ARM relocation generation 6971................................. 6972 6973Specific data relocations can be generated by putting the relocation 6974name in parentheses after the symbol name. For example: 6975 6976 .word foo(TARGET1) 6977 6978 This will generate an `R_ARM_TARGET1' relocation against the symbol 6979FOO. The following relocations are supported: `GOT', `GOTOFF', 6980`TARGET1', `TARGET2', `SBREL', `TLSGD', `TLSLDM', `TLSLDO', `TLSDESC', 6981`TLSCALL', `GOTTPOFF', `GOT_PREL' and `TPOFF'. 6982 6983 For compatibility with older toolchains the assembler also accepts 6984`(PLT)' after branch targets. On legacy targets this will generate the 6985deprecated `R_ARM_PLT32' relocation. On EABI targets it will encode 6986either the `R_ARM_CALL' or `R_ARM_JUMP24' relocation, as appropriate. 6987 6988 Relocations for `MOVW' and `MOVT' instructions can be generated by 6989prefixing the value with `#:lower16:' and `#:upper16' respectively. 6990For example to load the 32-bit address of foo into r0: 6991 6992 MOVW r0, #:lower16:foo 6993 MOVT r0, #:upper16:foo 6994 6995 6996File: as.info, Node: ARM-Neon-Alignment, Prev: ARM-Relocations, Up: ARM Syntax 6997 69989.4.2.5 NEON Alignment Specifiers 6999................................. 7000 7001Some NEON load/store instructions allow an optional address alignment 7002qualifier. The ARM documentation specifies that this is indicated by 7003`@ ALIGN'. However GAS already interprets the `@' character as a "line 7004comment" start, so `: ALIGN' is used instead. For example: 7005 7006 vld1.8 {q0}, [r0, :128] 7007 7008 7009File: as.info, Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent 7010 70119.4.3 Floating Point 7012-------------------- 7013 7014The ARM family uses IEEE floating-point numbers. 7015 7016 7017File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent 7018 70199.4.4 ARM Machine Directives 7020---------------------------- 7021 7022`.2byte EXPRESSION [, EXPRESSION]*' 7023`.4byte EXPRESSION [, EXPRESSION]*' 7024`.8byte EXPRESSION [, EXPRESSION]*' 7025 These directives write 2, 4 or 8 byte values to the output section. 7026 7027`.align EXPRESSION [, EXPRESSION]' 7028 This is the generic .ALIGN directive. For the ARM however if the 7029 first argument is zero (ie no alignment is needed) the assembler 7030 will behave as if the argument had been 2 (ie pad to the next four 7031 byte boundary). This is for compatibility with ARM's own 7032 assembler. 7033 7034`.arch NAME' 7035 Select the target architecture. Valid values for NAME are the 7036 same as for the `-march' commandline option. 7037 7038 Specifying `.arch' clears any previously selected architecture 7039 extensions. 7040 7041`.arch_extension NAME' 7042 Add or remove an architecture extension to the target 7043 architecture. Valid values for NAME are the same as those 7044 accepted as architectural extensions by the `-mcpu' commandline 7045 option. 7046 7047 `.arch_extension' may be used multiple times to add or remove 7048 extensions incrementally to the architecture being compiled for. 7049 7050`.arm' 7051 This performs the same action as .CODE 32. 7052 7053`.pad #COUNT' 7054 Generate unwinder annotations for a stack adjustment of COUNT 7055 bytes. A positive value indicates the function prologue allocated 7056 stack space by decrementing the stack pointer. 7057 7058`.bss' 7059 This directive switches to the `.bss' section. 7060 7061`.cantunwind' 7062 Prevents unwinding through the current function. No personality 7063 routine or exception table data is required or permitted. 7064 7065`.code `[16|32]'' 7066 This directive selects the instruction set being generated. The 7067 value 16 selects Thumb, with the value 32 selecting ARM. 7068 7069`.cpu NAME' 7070 Select the target processor. Valid values for NAME are the same as 7071 for the `-mcpu' commandline option. 7072 7073 Specifying `.cpu' clears any previously selected architecture 7074 extensions. 7075 7076`NAME .dn REGISTER NAME [.TYPE] [[INDEX]]' 7077`NAME .qn REGISTER NAME [.TYPE] [[INDEX]]' 7078 The `dn' and `qn' directives are used to create typed and/or 7079 indexed register aliases for use in Advanced SIMD Extension (Neon) 7080 instructions. The former should be used to create aliases of 7081 double-precision registers, and the latter to create aliases of 7082 quad-precision registers. 7083 7084 If these directives are used to create typed aliases, those 7085 aliases can be used in Neon instructions instead of writing types 7086 after the mnemonic or after each operand. For example: 7087 7088 x .dn d2.f32 7089 y .dn d3.f32 7090 z .dn d4.f32[1] 7091 vmul x,y,z 7092 7093 This is equivalent to writing the following: 7094 7095 vmul.f32 d2,d3,d4[1] 7096 7097 Aliases created using `dn' or `qn' can be destroyed using `unreq'. 7098 7099`.eabi_attribute TAG, VALUE' 7100 Set the EABI object attribute TAG to VALUE. 7101 7102 The TAG is either an attribute number, or one of the following: 7103 `Tag_CPU_raw_name', `Tag_CPU_name', `Tag_CPU_arch', 7104 `Tag_CPU_arch_profile', `Tag_ARM_ISA_use', `Tag_THUMB_ISA_use', 7105 `Tag_FP_arch', `Tag_WMMX_arch', `Tag_Advanced_SIMD_arch', 7106 `Tag_PCS_config', `Tag_ABI_PCS_R9_use', `Tag_ABI_PCS_RW_data', 7107 `Tag_ABI_PCS_RO_data', `Tag_ABI_PCS_GOT_use', 7108 `Tag_ABI_PCS_wchar_t', `Tag_ABI_FP_rounding', 7109 `Tag_ABI_FP_denormal', `Tag_ABI_FP_exceptions', 7110 `Tag_ABI_FP_user_exceptions', `Tag_ABI_FP_number_model', 7111 `Tag_ABI_align_needed', `Tag_ABI_align_preserved', 7112 `Tag_ABI_enum_size', `Tag_ABI_HardFP_use', `Tag_ABI_VFP_args', 7113 `Tag_ABI_WMMX_args', `Tag_ABI_optimization_goals', 7114 `Tag_ABI_FP_optimization_goals', `Tag_compatibility', 7115 `Tag_CPU_unaligned_access', `Tag_FP_HP_extension', 7116 `Tag_ABI_FP_16bit_format', `Tag_MPextension_use', `Tag_DIV_use', 7117 `Tag_nodefaults', `Tag_also_compatible_with', `Tag_conformance', 7118 `Tag_T2EE_use', `Tag_Virtualization_use' 7119 7120 The VALUE is either a `number', `"string"', or `number, "string"' 7121 depending on the tag. 7122 7123 Note - the following legacy values are also accepted by TAG: 7124 `Tag_VFP_arch', `Tag_ABI_align8_needed', 7125 `Tag_ABI_align8_preserved', `Tag_VFP_HP_extension', 7126 7127`.even' 7128 This directive aligns to an even-numbered address. 7129 7130`.extend EXPRESSION [, EXPRESSION]*' 7131`.ldouble EXPRESSION [, EXPRESSION]*' 7132 These directives write 12byte long double floating-point values to 7133 the output section. These are not compatible with current ARM 7134 processors or ABIs. 7135 7136`.fnend' 7137 Marks the end of a function with an unwind table entry. The 7138 unwind index table entry is created when this directive is 7139 processed. 7140 7141 If no personality routine has been specified then standard 7142 personality routine 0 or 1 will be used, depending on the number 7143 of unwind opcodes required. 7144 7145`.fnstart' 7146 Marks the start of a function with an unwind table entry. 7147 7148`.force_thumb' 7149 This directive forces the selection of Thumb instructions, even if 7150 the target processor does not support those instructions 7151 7152`.fpu NAME' 7153 Select the floating-point unit to assemble for. Valid values for 7154 NAME are the same as for the `-mfpu' commandline option. 7155 7156`.handlerdata' 7157 Marks the end of the current function, and the start of the 7158 exception table entry for that function. Anything between this 7159 directive and the `.fnend' directive will be added to the 7160 exception table entry. 7161 7162 Must be preceded by a `.personality' or `.personalityindex' 7163 directive. 7164 7165`.inst OPCODE [ , ... ]' 7166`.inst.n OPCODE [ , ... ]' 7167`.inst.w OPCODE [ , ... ]' 7168 Generates the instruction corresponding to the numerical value 7169 OPCODE. `.inst.n' and `.inst.w' allow the Thumb instruction size 7170 to be specified explicitly, overriding the normal encoding rules. 7171 7172`.ldouble EXPRESSION [, EXPRESSION]*' 7173 See `.extend'. 7174 7175`.ltorg' 7176 This directive causes the current contents of the literal pool to 7177 be dumped into the current section (which is assumed to be the 7178 .text section) at the current location (aligned to a word 7179 boundary). `GAS' maintains a separate literal pool for each 7180 section and each sub-section. The `.ltorg' directive will only 7181 affect the literal pool of the current section and sub-section. 7182 At the end of assembly all remaining, un-empty literal pools will 7183 automatically be dumped. 7184 7185 Note - older versions of `GAS' would dump the current literal pool 7186 any time a section change occurred. This is no longer done, since 7187 it prevents accurate control of the placement of literal pools. 7188 7189`.movsp REG [, #OFFSET]' 7190 Tell the unwinder that REG contains an offset from the current 7191 stack pointer. If OFFSET is not specified then it is assumed to be 7192 zero. 7193 7194`.object_arch NAME' 7195 Override the architecture recorded in the EABI object attribute 7196 section. Valid values for NAME are the same as for the `.arch' 7197 directive. Typically this is useful when code uses runtime 7198 detection of CPU features. 7199 7200`.packed EXPRESSION [, EXPRESSION]*' 7201 This directive writes 12-byte packed floating-point values to the 7202 output section. These are not compatible with current ARM 7203 processors or ABIs. 7204 7205`.pad #COUNT' 7206 Generate unwinder annotations for a stack adjustment of COUNT 7207 bytes. A positive value indicates the function prologue allocated 7208 stack space by decrementing the stack pointer. 7209 7210`.personality NAME' 7211 Sets the personality routine for the current function to NAME. 7212 7213`.personalityindex INDEX' 7214 Sets the personality routine for the current function to the EABI 7215 standard routine number INDEX 7216 7217`.pool' 7218 This is a synonym for .ltorg. 7219 7220`NAME .req REGISTER NAME' 7221 This creates an alias for REGISTER NAME called NAME. For example: 7222 7223 foo .req r0 7224 7225`.save REGLIST' 7226 Generate unwinder annotations to restore the registers in REGLIST. 7227 The format of REGLIST is the same as the corresponding 7228 store-multiple instruction. 7229 7230 _core registers_ 7231 .save {r4, r5, r6, lr} 7232 stmfd sp!, {r4, r5, r6, lr} 7233 _FPA registers_ 7234 .save f4, 2 7235 sfmfd f4, 2, [sp]! 7236 _VFP registers_ 7237 .save {d8, d9, d10} 7238 fstmdx sp!, {d8, d9, d10} 7239 _iWMMXt registers_ 7240 .save {wr10, wr11} 7241 wstrd wr11, [sp, #-8]! 7242 wstrd wr10, [sp, #-8]! 7243 or 7244 .save wr11 7245 wstrd wr11, [sp, #-8]! 7246 .save wr10 7247 wstrd wr10, [sp, #-8]! 7248 7249`.setfp FPREG, SPREG [, #OFFSET]' 7250 Make all unwinder annotations relative to a frame pointer. 7251 Without this the unwinder will use offsets from the stack pointer. 7252 7253 The syntax of this directive is the same as the `add' or `mov' 7254 instruction used to set the frame pointer. SPREG must be either 7255 `sp' or mentioned in a previous `.movsp' directive. 7256 7257 .movsp ip 7258 mov ip, sp 7259 ... 7260 .setfp fp, ip, #4 7261 add fp, ip, #4 7262 7263`.secrel32 EXPRESSION [, EXPRESSION]*' 7264 This directive emits relocations that evaluate to the 7265 section-relative offset of each expression's symbol. This 7266 directive is only supported for PE targets. 7267 7268`.syntax [`unified' | `divided']' 7269 This directive sets the Instruction Set Syntax as described in the 7270 *note ARM-Instruction-Set:: section. 7271 7272`.thumb' 7273 This performs the same action as .CODE 16. 7274 7275`.thumb_func' 7276 This directive specifies that the following symbol is the name of a 7277 Thumb encoded function. This information is necessary in order to 7278 allow the assembler and linker to generate correct code for 7279 interworking between Arm and Thumb instructions and should be used 7280 even if interworking is not going to be performed. The presence 7281 of this directive also implies `.thumb' 7282 7283 This directive is not neccessary when generating EABI objects. On 7284 these targets the encoding is implicit when generating Thumb code. 7285 7286`.thumb_set' 7287 This performs the equivalent of a `.set' directive in that it 7288 creates a symbol which is an alias for another symbol (possibly 7289 not yet defined). This directive also has the added property in 7290 that it marks the aliased symbol as being a thumb function entry 7291 point, in the same way that the `.thumb_func' directive does. 7292 7293`.tlsdescseq TLS-VARIABLE' 7294 This directive is used to annotate parts of an inlined TLS 7295 descriptor trampoline. Normally the trampoline is provided by the 7296 linker, and this directive is not needed. 7297 7298`.unreq ALIAS-NAME' 7299 This undefines a register alias which was previously defined using 7300 the `req', `dn' or `qn' directives. For example: 7301 7302 foo .req r0 7303 .unreq foo 7304 7305 An error occurs if the name is undefined. Note - this pseudo op 7306 can be used to delete builtin in register name aliases (eg 'r0'). 7307 This should only be done if it is really necessary. 7308 7309`.unwind_raw OFFSET, BYTE1, ...' 7310 Insert one of more arbitary unwind opcode bytes, which are known 7311 to adjust the stack pointer by OFFSET bytes. 7312 7313 For example `.unwind_raw 4, 0xb1, 0x01' is equivalent to `.save 7314 {r0}' 7315 7316`.vsave VFP-REGLIST' 7317 Generate unwinder annotations to restore the VFP registers in 7318 VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are 7319 to be restored using VLDM. The format of VFP-REGLIST is the same 7320 as the corresponding store-multiple instruction. 7321 7322 _VFP registers_ 7323 .vsave {d8, d9, d10} 7324 fstmdd sp!, {d8, d9, d10} 7325 _VFPv3 registers_ 7326 .vsave {d15, d16, d17} 7327 vstm sp!, {d15, d16, d17} 7328 7329 Since FLDMX and FSTMX are now deprecated, this directive should be 7330 used in favour of `.save' for saving VFP registers for ARMv6 and 7331 above. 7332 7333 7334 7335File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent 7336 73379.4.5 Opcodes 7338------------- 7339 7340`as' implements all the standard ARM opcodes. It also implements 7341several pseudo opcodes, including several synthetic load instructions. 7342 7343`NOP' 7344 nop 7345 7346 This pseudo op will always evaluate to a legal ARM instruction 7347 that does nothing. Currently it will evaluate to MOV r0, r0. 7348 7349`LDR' 7350 ldr <register> , = <expression> 7351 7352 If expression evaluates to a numeric constant then a MOV or MVN 7353 instruction will be used in place of the LDR instruction, if the 7354 constant can be generated by either of these instructions. 7355 Otherwise the constant will be placed into the nearest literal 7356 pool (if it not already there) and a PC relative LDR instruction 7357 will be generated. 7358 7359`ADR' 7360 adr <register> <label> 7361 7362 This instruction will load the address of LABEL into the indicated 7363 register. The instruction will evaluate to a PC relative ADD or 7364 SUB instruction depending upon where the label is located. If the 7365 label is out of range, or if it is not defined in the same file 7366 (and section) as the ADR instruction, then an error will be 7367 generated. This instruction will not make use of the literal pool. 7368 7369`ADRL' 7370 adrl <register> <label> 7371 7372 This instruction will load the address of LABEL into the indicated 7373 register. The instruction will evaluate to one or two PC relative 7374 ADD or SUB instructions depending upon where the label is located. 7375 If a second instruction is not needed a NOP instruction will be 7376 generated in its place, so that this instruction is always 8 bytes 7377 long. 7378 7379 If the label is out of range, or if it is not defined in the same 7380 file (and section) as the ADRL instruction, then an error will be 7381 generated. This instruction will not make use of the literal pool. 7382 7383 7384 For information on the ARM or Thumb instruction sets, see `ARM 7385Software Development Toolkit Reference Manual', Advanced RISC Machines 7386Ltd. 7387 7388 7389File: as.info, Node: ARM Mapping Symbols, Next: ARM Unwinding Tutorial, Prev: ARM Opcodes, Up: ARM-Dependent 7390 73919.4.6 Mapping Symbols 7392--------------------- 7393 7394The ARM ELF specification requires that special symbols be inserted 7395into object files to mark certain features: 7396 7397`$a' 7398 At the start of a region of code containing ARM instructions. 7399 7400`$t' 7401 At the start of a region of code containing THUMB instructions. 7402 7403`$d' 7404 At the start of a region of data. 7405 7406 7407 The assembler will automatically insert these symbols for you - there 7408is no need to code them yourself. Support for tagging symbols ($b, $f, 7409$p and $m) which is also mentioned in the current ARM ELF specification 7410is not implemented. This is because they have been dropped from the 7411new EABI and so tools cannot rely upon their presence. 7412 7413 7414File: as.info, Node: ARM Unwinding Tutorial, Prev: ARM Mapping Symbols, Up: ARM-Dependent 7415 74169.4.7 Unwinding 7417--------------- 7418 7419The ABI for the ARM Architecture specifies a standard format for 7420exception unwind information. This information is used when an 7421exception is thrown to determine where control should be transferred. 7422In particular, the unwind information is used to determine which 7423function called the function that threw the exception, and which 7424function called that one, and so forth. This information is also used 7425to restore the values of callee-saved registers in the function 7426catching the exception. 7427 7428 If you are writing functions in assembly code, and those functions 7429call other functions that throw exceptions, you must use assembly 7430pseudo ops to ensure that appropriate exception unwind information is 7431generated. Otherwise, if one of the functions called by your assembly 7432code throws an exception, the run-time library will be unable to unwind 7433the stack through your assembly code and your program will not behave 7434correctly. 7435 7436 To illustrate the use of these pseudo ops, we will examine the code 7437that G++ generates for the following C++ input: 7438 7439void callee (int *); 7440 7441int 7442caller () 7443{ 7444 int i; 7445 callee (&i); 7446 return i; 7447} 7448 7449 This example does not show how to throw or catch an exception from 7450assembly code. That is a much more complex operation and should always 7451be done in a high-level language, such as C++, that directly supports 7452exceptions. 7453 7454 The code generated by one particular version of G++ when compiling 7455the example above is: 7456 7457_Z6callerv: 7458 .fnstart 7459.LFB2: 7460 @ Function supports interworking. 7461 @ args = 0, pretend = 0, frame = 8 7462 @ frame_needed = 1, uses_anonymous_args = 0 7463 stmfd sp!, {fp, lr} 7464 .save {fp, lr} 7465.LCFI0: 7466 .setfp fp, sp, #4 7467 add fp, sp, #4 7468.LCFI1: 7469 .pad #8 7470 sub sp, sp, #8 7471.LCFI2: 7472 sub r3, fp, #8 7473 mov r0, r3 7474 bl _Z6calleePi 7475 ldr r3, [fp, #-8] 7476 mov r0, r3 7477 sub sp, fp, #4 7478 ldmfd sp!, {fp, lr} 7479 bx lr 7480.LFE2: 7481 .fnend 7482 7483 Of course, the sequence of instructions varies based on the options 7484you pass to GCC and on the version of GCC in use. The exact 7485instructions are not important since we are focusing on the pseudo ops 7486that are used to generate unwind information. 7487 7488 An important assumption made by the unwinder is that the stack frame 7489does not change during the body of the function. In particular, since 7490we assume that the assembly code does not itself throw an exception, 7491the only point where an exception can be thrown is from a call, such as 7492the `bl' instruction above. At each call site, the same saved 7493registers (including `lr', which indicates the return address) must be 7494located in the same locations relative to the frame pointer. 7495 7496 The `.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op 7497appears immediately before the first instruction of the function while 7498the `.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears 7499immediately after the last instruction of the function. These pseudo 7500ops specify the range of the function. 7501 7502 Only the order of the other pseudos ops (e.g., `.setfp' or `.pad') 7503matters; their exact locations are irrelevant. In the example above, 7504the compiler emits the pseudo ops with particular instructions. That 7505makes it easier to understand the code, but it is not required for 7506correctness. It would work just as well to emit all of the pseudo ops 7507other than `.fnend' in the same order, but immediately after `.fnstart'. 7508 7509 The `.save' (*note .save pseudo op: arm_save.) pseudo op indicates 7510registers that have been saved to the stack so that they can be 7511restored before the function returns. The argument to the `.save' 7512pseudo op is a list of registers to save. If a register is 7513"callee-saved" (as specified by the ABI) and is modified by the 7514function you are writing, then your code must save the value before it 7515is modified and restore the original value before the function returns. 7516If an exception is thrown, the run-time library restores the values of 7517these registers from their locations on the stack before returning 7518control to the exception handler. (Of course, if an exception is not 7519thrown, the function that contains the `.save' pseudo op restores these 7520registers in the function epilogue, as is done with the `ldmfd' 7521instruction above.) 7522 7523 You do not have to save callee-saved registers at the very beginning 7524of the function and you do not need to use the `.save' pseudo op 7525immediately following the point at which the registers are saved. 7526However, if you modify a callee-saved register, you must save it on the 7527stack before modifying it and before calling any functions which might 7528throw an exception. And, you must use the `.save' pseudo op to 7529indicate that you have done so. 7530 7531 The `.pad' (*note .pad: arm_pad.) pseudo op indicates a modification 7532of the stack pointer that does not save any registers. The argument is 7533the number of bytes (in decimal) that are subtracted from the stack 7534pointer. (On ARM CPUs, the stack grows downwards, so subtracting from 7535the stack pointer increases the size of the stack.) 7536 7537 The `.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op 7538indicates the register that contains the frame pointer. The first 7539argument is the register that is set, which is typically `fp'. The 7540second argument indicates the register from which the frame pointer 7541takes its value. The third argument, if present, is the value (in 7542decimal) added to the register specified by the second argument to 7543compute the value of the frame pointer. You should not modify the 7544frame pointer in the body of the function. 7545 7546 If you do not use a frame pointer, then you should not use the 7547`.setfp' pseudo op. If you do not use a frame pointer, then you should 7548avoid modifying the stack pointer outside of the function prologue. 7549Otherwise, the run-time library will be unable to find saved registers 7550when it is unwinding the stack. 7551 7552 The pseudo ops described above are sufficient for writing assembly 7553code that calls functions which may throw exceptions. If you need to 7554know more about the object-file format used to represent unwind 7555information, you may consult the `Exception Handling ABI for the ARM 7556Architecture' available from `http://infocenter.arm.com'. 7557 7558 7559File: as.info, Node: AVR-Dependent, Next: Blackfin-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies 7560 75619.5 AVR Dependent Features 7562========================== 7563 7564* Menu: 7565 7566* AVR Options:: Options 7567* AVR Syntax:: Syntax 7568* AVR Opcodes:: Opcodes 7569 7570 7571File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent 7572 75739.5.1 Options 7574------------- 7575 7576`-mmcu=MCU' 7577 Specify ATMEL AVR instruction set or MCU type. 7578 7579 Instruction set avr1 is for the minimal AVR core, not supported by 7580 the C compiler, only for assembler programs (MCU types: at90s1200, 7581 attiny11, attiny12, attiny15, attiny28). 7582 7583 Instruction set avr2 (default) is for the classic AVR core with up 7584 to 8K program memory space (MCU types: at90s2313, at90s2323, 7585 at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433, 7586 at90s4434, at90s8515, at90c8534, at90s8535). 7587 7588 Instruction set avr25 is for the classic AVR core with up to 8K 7589 program memory space plus the MOVW instruction (MCU types: 7590 attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, 7591 attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, 7592 attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a, 7593 attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, 7594 at86rf401). 7595 7596 Instruction set avr3 is for the classic AVR core with up to 128K 7597 program memory space (MCU types: at43usb355, at76c711). 7598 7599 Instruction set avr31 is for the classic AVR core with exactly 7600 128K program memory space (MCU types: atmega103, at43usb320). 7601 7602 Instruction set avr35 is for classic AVR core plus MOVW, CALL, and 7603 JMP instructions (MCU types: attiny167, at90usb82, at90usb162, 7604 atmega8u2, atmega16u2, atmega32u2). 7605 7606 Instruction set avr4 is for the enhanced AVR core with up to 8K 7607 program memory space (MCU types: atmega48, atmega48a, atmega48p, 7608 atmega8, atmega88, atmega88a, atmega88p, atmega88pa, atmega8515, 7609 atmega8535, atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, 7610 at90pwm3b, at90pwm81, ata6289). 7611 7612 Instruction set avr5 is for the enhanced AVR core with up to 128K 7613 program memory space (MCU types: atmega16, atmega16a, atmega161, 7614 atmega162, atmega163, atmega164a, atmega164p, atmega165, 7615 atmega165a, atmega165p, atmega168, atmega168a, atmega168p, 7616 atmega169, atmega169a, atmega169p, atmega169pa, atmega32, 7617 atmega323, atmega324a, atmega324p, atmega325, atmega325a, 7618 atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, 7619 atmega3250pa, atmega328, atmega328p, atmega329, atmega329a, 7620 atmega329p, atmega329pa, atmega3290, atmega3290a, atmega3290p, 7621 atmega3290pa, atmega406, atmega64, atmega640, atmega644, 7622 atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, 7623 atmega645p, atmega6450, atmega6450a, atmega6450p, atmega649, 7624 atmega649a, atmega649p, atmega6490, atmega6490a, atmega6490p, 7625 atmega64rfr2, atmega644rfr2, atmega16hva, atmega16hva2, 7626 atmega16hvb, atmega16hvbrevb, atmega32hvb, atmega32hvbrevb, 7627 atmega64hve, at90can32, at90can64, at90pwm161, at90pwm216, 7628 at90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1, 7629 atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, 7630 at90usb647, at94k, at90scr100). 7631 7632 Instruction set avr51 is for the enhanced AVR core with exactly 7633 128K program memory space (MCU types: atmega128, atmega1280, 7634 atmega1281, atmega1284p, atmega128rfa1, atmega128rfr2, 7635 atmega1284rfr2, at90can128, at90usb1286, at90usb1287, m3000). 7636 7637 Instruction set avr6 is for the enhanced AVR core with a 3-byte PC 7638 (MCU types: atmega2560, atmega2561, atmega256rfr2, atmega2564rfr2). 7639 7640 Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K 7641 program memory space and less than 64K data space (MCU types: 7642 atxmega16a4, atxmega16d4, atxmega16x1, atxmega32a4, atxmega32d4, 7643 atxmega32x1). 7644 7645 Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K 7646 program memory space and greater than 64K data space (MCU types: 7647 none). 7648 7649 Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K 7650 program memory space and less than 64K data space (MCU types: 7651 atxmega64a3, atxmega64d3). 7652 7653 Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K 7654 program memory space and greater than 64K data space (MCU types: 7655 atxmega64a1, atxmega64a1u). 7656 7657 Instruction set avrxmega6 is for the XMEGA AVR core with up to 7658 256K program memory space and less than 64K data space (MCU types: 7659 atxmega128a3, atxmega128d3, atxmega192a3, atxmega128b1, 7660 atxmega192d3, atxmega256a3, atxmega256a3b, atxmega256a3bu, 7661 atxmega192d3). 7662 7663 Instruction set avrxmega7 is for the XMEGA AVR core with up to 7664 256K program memory space and greater than 64K data space (MCU 7665 types: atxmega128a1, atxmega128a1u). 7666 7667`-mall-opcodes' 7668 Accept all AVR opcodes, even if not supported by `-mmcu'. 7669 7670`-mno-skip-bug' 7671 This option disable warnings for skipping two-word instructions. 7672 7673`-mno-wrap' 7674 This option reject `rjmp/rcall' instructions with 8K wrap-around. 7675 7676 7677 7678File: as.info, Node: AVR Syntax, Next: AVR Opcodes, Prev: AVR Options, Up: AVR-Dependent 7679 76809.5.2 Syntax 7681------------ 7682 7683* Menu: 7684 7685* AVR-Chars:: Special Characters 7686* AVR-Regs:: Register Names 7687* AVR-Modifiers:: Relocatable Expression Modifiers 7688 7689 7690File: as.info, Node: AVR-Chars, Next: AVR-Regs, Up: AVR Syntax 7691 76929.5.2.1 Special Characters 7693.......................... 7694 7695The presence of a `;' anywhere on a line indicates the start of a 7696comment that extends to the end of that line. 7697 7698 If a `#' appears as the first character of a line, the whole line is 7699treated as a comment, but in this case the line can also be a logical 7700line number directive (*note Comments::) or a preprocessor control 7701command (*note Preprocessing::). 7702 7703 The `$' character can be used instead of a newline to separate 7704statements. 7705 7706 7707File: as.info, Node: AVR-Regs, Next: AVR-Modifiers, Prev: AVR-Chars, Up: AVR Syntax 7708 77099.5.2.2 Register Names 7710...................... 7711 7712The AVR has 32 x 8-bit general purpose working registers `r0', `r1', 7713... `r31'. Six of the 32 registers can be used as three 16-bit 7714indirect address register pointers for Data Space addressing. One of 7715the these address pointers can also be used as an address pointer for 7716look up tables in Flash program memory. These added function registers 7717are the 16-bit `X', `Y' and `Z' - registers. 7718 7719 X = r26:r27 7720 Y = r28:r29 7721 Z = r30:r31 7722 7723 7724File: as.info, Node: AVR-Modifiers, Prev: AVR-Regs, Up: AVR Syntax 7725 77269.5.2.3 Relocatable Expression Modifiers 7727........................................ 7728 7729The assembler supports several modifiers when using relocatable 7730addresses in AVR instruction operands. The general syntax is the 7731following: 7732 7733 modifier(relocatable-expression) 7734 7735`lo8' 7736 This modifier allows you to use bits 0 through 7 of an address 7737 expression as 8 bit relocatable expression. 7738 7739`hi8' 7740 This modifier allows you to use bits 7 through 15 of an address 7741 expression as 8 bit relocatable expression. This is useful with, 7742 for example, the AVR `ldi' instruction and `lo8' modifier. 7743 7744 For example 7745 7746 ldi r26, lo8(sym+10) 7747 ldi r27, hi8(sym+10) 7748 7749`hh8' 7750 This modifier allows you to use bits 16 through 23 of an address 7751 expression as 8 bit relocatable expression. Also, can be useful 7752 for loading 32 bit constants. 7753 7754`hlo8' 7755 Synonym of `hh8'. 7756 7757`hhi8' 7758 This modifier allows you to use bits 24 through 31 of an 7759 expression as 8 bit expression. This is useful with, for example, 7760 the AVR `ldi' instruction and `lo8', `hi8', `hlo8', `hhi8', 7761 modifier. 7762 7763 For example 7764 7765 ldi r26, lo8(285774925) 7766 ldi r27, hi8(285774925) 7767 ldi r28, hlo8(285774925) 7768 ldi r29, hhi8(285774925) 7769 ; r29,r28,r27,r26 = 285774925 7770 7771`pm_lo8' 7772 This modifier allows you to use bits 0 through 7 of an address 7773 expression as 8 bit relocatable expression. This modifier useful 7774 for addressing data or code from Flash/Program memory. The using 7775 of `pm_lo8' similar to `lo8'. 7776 7777`pm_hi8' 7778 This modifier allows you to use bits 8 through 15 of an address 7779 expression as 8 bit relocatable expression. This modifier useful 7780 for addressing data or code from Flash/Program memory. 7781 7782`pm_hh8' 7783 This modifier allows you to use bits 15 through 23 of an address 7784 expression as 8 bit relocatable expression. This modifier useful 7785 for addressing data or code from Flash/Program memory. 7786 7787 7788 7789File: as.info, Node: AVR Opcodes, Prev: AVR Syntax, Up: AVR-Dependent 7790 77919.5.3 Opcodes 7792------------- 7793 7794For detailed information on the AVR machine instruction set, see 7795`www.atmel.com/products/AVR'. 7796 7797 `as' implements all the standard AVR opcodes. The following table 7798summarizes the AVR opcodes, and their arguments. 7799 7800 Legend: 7801 r any register 7802 d `ldi' register (r16-r31) 7803 v `movw' even register (r0, r2, ..., r28, r30) 7804 a `fmul' register (r16-r23) 7805 w `adiw' register (r24,r26,r28,r30) 7806 e pointer registers (X,Y,Z) 7807 b base pointer register and displacement ([YZ]+disp) 7808 z Z pointer register (for [e]lpm Rd,Z[+]) 7809 M immediate value from 0 to 255 7810 n immediate value from 0 to 255 ( n = ~M ). Relocation impossible 7811 s immediate value from 0 to 7 7812 P Port address value from 0 to 63. (in, out) 7813 p Port address value from 0 to 31. (cbi, sbi, sbic, sbis) 7814 K immediate value from 0 to 63 (used in `adiw', `sbiw') 7815 i immediate value 7816 l signed pc relative offset from -64 to 63 7817 L signed pc relative offset from -2048 to 2047 7818 h absolute code address (call, jmp) 7819 S immediate value from 0 to 7 (S = s << 4) 7820 ? use this opcode entry if no parameters, else use next opcode entry 7821 7822 1001010010001000 clc 7823 1001010011011000 clh 7824 1001010011111000 cli 7825 1001010010101000 cln 7826 1001010011001000 cls 7827 1001010011101000 clt 7828 1001010010111000 clv 7829 1001010010011000 clz 7830 1001010000001000 sec 7831 1001010001011000 seh 7832 1001010001111000 sei 7833 1001010000101000 sen 7834 1001010001001000 ses 7835 1001010001101000 set 7836 1001010000111000 sev 7837 1001010000011000 sez 7838 100101001SSS1000 bclr S 7839 100101000SSS1000 bset S 7840 1001010100001001 icall 7841 1001010000001001 ijmp 7842 1001010111001000 lpm ? 7843 1001000ddddd010+ lpm r,z 7844 1001010111011000 elpm ? 7845 1001000ddddd011+ elpm r,z 7846 0000000000000000 nop 7847 1001010100001000 ret 7848 1001010100011000 reti 7849 1001010110001000 sleep 7850 1001010110011000 break 7851 1001010110101000 wdr 7852 1001010111101000 spm 7853 000111rdddddrrrr adc r,r 7854 000011rdddddrrrr add r,r 7855 001000rdddddrrrr and r,r 7856 000101rdddddrrrr cp r,r 7857 000001rdddddrrrr cpc r,r 7858 000100rdddddrrrr cpse r,r 7859 001001rdddddrrrr eor r,r 7860 001011rdddddrrrr mov r,r 7861 100111rdddddrrrr mul r,r 7862 001010rdddddrrrr or r,r 7863 000010rdddddrrrr sbc r,r 7864 000110rdddddrrrr sub r,r 7865 001001rdddddrrrr clr r 7866 000011rdddddrrrr lsl r 7867 000111rdddddrrrr rol r 7868 001000rdddddrrrr tst r 7869 0111KKKKddddKKKK andi d,M 7870 0111KKKKddddKKKK cbr d,n 7871 1110KKKKddddKKKK ldi d,M 7872 11101111dddd1111 ser d 7873 0110KKKKddddKKKK ori d,M 7874 0110KKKKddddKKKK sbr d,M 7875 0011KKKKddddKKKK cpi d,M 7876 0100KKKKddddKKKK sbci d,M 7877 0101KKKKddddKKKK subi d,M 7878 1111110rrrrr0sss sbrc r,s 7879 1111111rrrrr0sss sbrs r,s 7880 1111100ddddd0sss bld r,s 7881 1111101ddddd0sss bst r,s 7882 10110PPdddddPPPP in r,P 7883 10111PPrrrrrPPPP out P,r 7884 10010110KKddKKKK adiw w,K 7885 10010111KKddKKKK sbiw w,K 7886 10011000pppppsss cbi p,s 7887 10011010pppppsss sbi p,s 7888 10011001pppppsss sbic p,s 7889 10011011pppppsss sbis p,s 7890 111101lllllll000 brcc l 7891 111100lllllll000 brcs l 7892 111100lllllll001 breq l 7893 111101lllllll100 brge l 7894 111101lllllll101 brhc l 7895 111100lllllll101 brhs l 7896 111101lllllll111 brid l 7897 111100lllllll111 brie l 7898 111100lllllll000 brlo l 7899 111100lllllll100 brlt l 7900 111100lllllll010 brmi l 7901 111101lllllll001 brne l 7902 111101lllllll010 brpl l 7903 111101lllllll000 brsh l 7904 111101lllllll110 brtc l 7905 111100lllllll110 brts l 7906 111101lllllll011 brvc l 7907 111100lllllll011 brvs l 7908 111101lllllllsss brbc s,l 7909 111100lllllllsss brbs s,l 7910 1101LLLLLLLLLLLL rcall L 7911 1100LLLLLLLLLLLL rjmp L 7912 1001010hhhhh111h call h 7913 1001010hhhhh110h jmp h 7914 1001010rrrrr0101 asr r 7915 1001010rrrrr0000 com r 7916 1001010rrrrr1010 dec r 7917 1001010rrrrr0011 inc r 7918 1001010rrrrr0110 lsr r 7919 1001010rrrrr0001 neg r 7920 1001000rrrrr1111 pop r 7921 1001001rrrrr1111 push r 7922 1001010rrrrr0111 ror r 7923 1001010rrrrr0010 swap r 7924 00000001ddddrrrr movw v,v 7925 00000010ddddrrrr muls d,d 7926 000000110ddd0rrr mulsu a,a 7927 000000110ddd1rrr fmul a,a 7928 000000111ddd0rrr fmuls a,a 7929 000000111ddd1rrr fmulsu a,a 7930 1001001ddddd0000 sts i,r 7931 1001000ddddd0000 lds r,i 7932 10o0oo0dddddbooo ldd r,b 7933 100!000dddddee-+ ld r,e 7934 10o0oo1rrrrrbooo std b,r 7935 100!001rrrrree-+ st e,r 7936 1001010100011001 eicall 7937 1001010000011001 eijmp 7938 7939 7940File: as.info, Node: Blackfin-Dependent, Next: CR16-Dependent, Prev: AVR-Dependent, Up: Machine Dependencies 7941 79429.6 Blackfin Dependent Features 7943=============================== 7944 7945* Menu: 7946 7947* Blackfin Options:: Blackfin Options 7948* Blackfin Syntax:: Blackfin Syntax 7949* Blackfin Directives:: Blackfin Directives 7950 7951 7952File: as.info, Node: Blackfin Options, Next: Blackfin Syntax, Up: Blackfin-Dependent 7953 79549.6.1 Options 7955------------- 7956 7957`-mcpu=PROCESSOR[-SIREVISION]' 7958 This option specifies the target processor. The optional 7959 SIREVISION is not used in assembler. It's here such that GCC can 7960 easily pass down its `-mcpu=' option. The assembler will issue an 7961 error message if an attempt is made to assemble an instruction 7962 which will not execute on the target processor. The following 7963 processor names are recognized: `bf504', `bf506', `bf512', `bf514', 7964 `bf516', `bf518', `bf522', `bf523', `bf524', `bf525', `bf526', 7965 `bf527', `bf531', `bf532', `bf533', `bf534', `bf535' (not 7966 implemented yet), `bf536', `bf537', `bf538', `bf539', `bf542', 7967 `bf542m', `bf544', `bf544m', `bf547', `bf547m', `bf548', `bf548m', 7968 `bf549', `bf549m', `bf561', and `bf592'. 7969 7970`-mfdpic' 7971 Assemble for the FDPIC ABI. 7972 7973`-mno-fdpic' 7974`-mnopic' 7975 Disable -mfdpic. 7976 7977 7978File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackfin Options, Up: Blackfin-Dependent 7979 79809.6.2 Syntax 7981------------ 7982 7983`Special Characters' 7984 Assembler input is free format and may appear anywhere on the line. 7985 One instruction may extend across multiple lines or more than one 7986 instruction may appear on the same line. White space (space, tab, 7987 comments or newline) may appear anywhere between tokens. A token 7988 must not have embedded spaces. Tokens include numbers, register 7989 names, keywords, user identifiers, and also some multicharacter 7990 special symbols like "+=", "/*" or "||". 7991 7992 Comments are introduced by the `#' character and extend to the end 7993 of the current line. If the `#' appears as the first character of 7994 a line, the whole line is treated as a comment, but in this case 7995 the line can also be a logical line number directive (*note 7996 Comments::) or a preprocessor control command (*note 7997 Preprocessing::). 7998 7999`Instruction Delimiting' 8000 A semicolon must terminate every instruction. Sometimes a complete 8001 instruction will consist of more than one operation. There are two 8002 cases where this occurs. The first is when two general operations 8003 are combined. Normally a comma separates the different parts, as 8004 in 8005 8006 a0= r3.h * r2.l, a1 = r3.l * r2.h ; 8007 8008 The second case occurs when a general instruction is combined with 8009 one or two memory references for joint issue. The latter portions 8010 are set off by a "||" token. 8011 8012 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; 8013 8014 Multiple instructions can occur on the same line. Each must be 8015 terminated by a semicolon character. 8016 8017`Register Names' 8018 The assembler treats register names and instruction keywords in a 8019 case insensitive manner. User identifiers are case sensitive. 8020 Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the 8021 assembler. 8022 8023 Register names are reserved and may not be used as program 8024 identifiers. 8025 8026 Some operations (such as "Move Register") require a register pair. 8027 Register pairs are always data registers and are denoted using a 8028 colon, eg., R3:2. The larger number must be written firsts. Note 8029 that the hardware only supports odd-even pairs, eg., R7:6, R5:4, 8030 R3:2, and R1:0. 8031 8032 Some instructions (such as -SP (Push Multiple)) require a group of 8033 adjacent registers. Adjacent registers are denoted in the syntax 8034 by the range enclosed in parentheses and separated by a colon, 8035 eg., (R7:3). Again, the larger number appears first. 8036 8037 Portions of a particular register may be individually specified. 8038 This is written with a dot (".") following the register name and 8039 then a letter denoting the desired portion. For 32-bit registers, 8040 ".H" denotes the most significant ("High") portion. ".L" denotes 8041 the least-significant portion. The subdivisions of the 40-bit 8042 registers are described later. 8043 8044`Accumulators' 8045 The set of 40-bit registers A1 and A0 that normally contain data 8046 that is being manipulated. Each accumulator can be accessed in 8047 four ways. 8048 8049 `one 40-bit register' 8050 The register will be referred to as A1 or A0. 8051 8052 `one 32-bit register' 8053 The registers are designated as A1.W or A0.W. 8054 8055 `two 16-bit registers' 8056 The registers are designated as A1.H, A1.L, A0.H or A0.L. 8057 8058 `one 8-bit register' 8059 The registers are designated as A1.X or A0.X for the bits that 8060 extend beyond bit 31. 8061 8062`Data Registers' 8063 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) 8064 that normally contain data for manipulation. These are 8065 abbreviated as D-register or Dreg. Data registers can be accessed 8066 as 32-bit registers or as two independent 16-bit registers. The 8067 least significant 16 bits of each register is called the "low" 8068 half and is designated with ".L" following the register name. The 8069 most significant 16 bits are called the "high" half and is 8070 designated with ".H" following the name. 8071 8072 R7.L, r2.h, r4.L, R0.H 8073 8074`Pointer Registers' 8075 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) 8076 that normally contain byte addresses of data structures. These are 8077 abbreviated as P-register or Preg. 8078 8079 p2, p5, fp, sp 8080 8081`Stack Pointer SP' 8082 The stack pointer contains the 32-bit address of the last occupied 8083 byte location in the stack. The stack grows by decrementing the 8084 stack pointer. 8085 8086`Frame Pointer FP' 8087 The frame pointer contains the 32-bit address of the previous frame 8088 pointer in the stack. It is located at the top of a frame. 8089 8090`Loop Top' 8091 LT0 and LT1. These registers contain the 32-bit address of the 8092 top of a zero overhead loop. 8093 8094`Loop Count' 8095 LC0 and LC1. These registers contain the 32-bit counter of the 8096 zero overhead loop executions. 8097 8098`Loop Bottom' 8099 LB0 and LB1. These registers contain the 32-bit address of the 8100 bottom of a zero overhead loop. 8101 8102`Index Registers' 8103 The set of 32-bit registers (I0, I1, I2, I3) that normally contain 8104 byte addresses of data structures. Abbreviated I-register or Ireg. 8105 8106`Modify Registers' 8107 The set of 32-bit registers (M0, M1, M2, M3) that normally contain 8108 offset values that are added and subtracted to one of the index 8109 registers. Abbreviated as Mreg. 8110 8111`Length Registers' 8112 The set of 32-bit registers (L0, L1, L2, L3) that normally contain 8113 the length in bytes of the circular buffer. Abbreviated as Lreg. 8114 Clear the Lreg to disable circular addressing for the 8115 corresponding Ireg. 8116 8117`Base Registers' 8118 The set of 32-bit registers (B0, B1, B2, B3) that normally contain 8119 the base address in bytes of the circular buffer. Abbreviated as 8120 Breg. 8121 8122`Floating Point' 8123 The Blackfin family has no hardware floating point but the .float 8124 directive generates ieee floating point numbers for use with 8125 software floating point libraries. 8126 8127`Blackfin Opcodes' 8128 For detailed information on the Blackfin machine instruction set, 8129 see the Blackfin(r) Processor Instruction Set Reference. 8130 8131 8132 8133File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent 8134 81359.6.3 Directives 8136---------------- 8137 8138The following directives are provided for compatibility with the VDSP 8139assembler. 8140 8141`.byte2' 8142 Initializes a two byte data object. 8143 8144 This maps to the `.short' directive. 8145 8146`.byte4' 8147 Initializes a four byte data object. 8148 8149 This maps to the `.int' directive. 8150 8151`.db' 8152 Initializes a single byte data object. 8153 8154 This directive is a synonym for `.byte'. 8155 8156`.dw' 8157 Initializes a two byte data object. 8158 8159 This directive is a synonym for `.byte2'. 8160 8161`.dd' 8162 Initializes a four byte data object. 8163 8164 This directive is a synonym for `.byte4'. 8165 8166`.var' 8167 Define and initialize a 32 bit data object. 8168 8169 8170File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: Blackfin-Dependent, Up: Machine Dependencies 8171 81729.7 CR16 Dependent Features 8173=========================== 8174 8175* Menu: 8176 8177* CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers 8178* CR16 Syntax:: Syntax for the CR16 8179 8180 8181File: as.info, Node: CR16 Operand Qualifiers, Next: CR16 Syntax, Up: CR16-Dependent 8182 81839.7.1 CR16 Operand Qualifiers 8184----------------------------- 8185 8186The National Semiconductor CR16 target of `as' has a few machine 8187dependent operand qualifiers. 8188 8189 Operand expression type qualifier is an optional field in the 8190instruction operand, to determines the type of the expression field of 8191an operand. The `@' is required. CR16 architecture uses one of the 8192following expression qualifiers: 8193 8194`s' 8195 - `Specifies expression operand type as small' 8196 8197`m' 8198 - `Specifies expression operand type as medium' 8199 8200`l' 8201 - `Specifies expression operand type as large' 8202 8203`c' 8204 - `Specifies the CR16 Assembler generates a relocation entry for 8205 the operand, where pc has implied bit, the expression is adjusted 8206 accordingly. The linker uses the relocation entry to update the 8207 operand address at link time.' 8208 8209`got/GOT' 8210 - `Specifies the CR16 Assembler generates a relocation entry for 8211 the operand, offset from Global Offset Table. The linker uses this 8212 relocation entry to update the operand address at link time' 8213 8214`cgot/cGOT' 8215 - `Specifies the CompactRISC Assembler generates a relocation 8216 entry for the operand, where pc has implied bit, the expression is 8217 adjusted accordingly. The linker uses the relocation entry to 8218 update the operand address at link time.' 8219 8220 CR16 target operand qualifiers and its size (in bits): 8221 8222`Immediate Operand: s' 8223 4 bits. 8224 8225`Immediate Operand: m' 8226 16 bits, for movb and movw instructions. 8227 8228`Immediate Operand: m' 8229 20 bits, movd instructions. 8230 8231`Immediate Operand: l' 8232 32 bits. 8233 8234`Absolute Operand: s' 8235 Illegal specifier for this operand. 8236 8237`Absolute Operand: m' 8238 20 bits, movd instructions. 8239 8240`Displacement Operand: s' 8241 8 bits. 8242 8243`Displacement Operand: m' 8244 16 bits. 8245 8246`Displacement Operand: l' 8247 24 bits. 8248 8249 8250 For example: 8251 1 `movw $_myfun@c,r1' 8252 8253 This loads the address of _myfun, shifted right by 1, into r1. 8254 8255 2 `movd $_myfun@c,(r2,r1)' 8256 8257 This loads the address of _myfun, shifted right by 1, into register-pair r2-r1. 8258 8259 3 `_myfun_ptr:' 8260 `.long _myfun@c' 8261 `loadd _myfun_ptr, (r1,r0)' 8262 `jal (r1,r0)' 8263 8264 This .long directive, the address of _myfunc, shifted right by 1 at link time. 8265 8266 4 `loadd _data1@GOT(r12), (r1,r0)' 8267 8268 This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1. 8269 8270 5 `loadd _myfunc@cGOT(r12), (r1,r0)' 8271 8272 This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0. 8273 8274 8275File: as.info, Node: CR16 Syntax, Prev: CR16 Operand Qualifiers, Up: CR16-Dependent 8276 82779.7.2 CR16 Syntax 8278----------------- 8279 8280* Menu: 8281 8282* CR16-Chars:: Special Characters 8283 8284 8285File: as.info, Node: CR16-Chars, Up: CR16 Syntax 8286 82879.7.2.1 Special Characters 8288.......................... 8289 8290The presence of a `#' on a line indicates the start of a comment that 8291extends to the end of the current line. If the `#' appears as the 8292first character of a line, the whole line is treated as a comment, but 8293in this case the line can also be a logical line number directive 8294(*note Comments::) or a preprocessor control command (*note 8295Preprocessing::). 8296 8297 The `;' character can be used to separate statements on the same 8298line. 8299 8300 8301File: as.info, Node: CRIS-Dependent, Next: D10V-Dependent, Prev: CR16-Dependent, Up: Machine Dependencies 8302 83039.8 CRIS Dependent Features 8304=========================== 8305 8306* Menu: 8307 8308* CRIS-Opts:: Command-line Options 8309* CRIS-Expand:: Instruction expansion 8310* CRIS-Symbols:: Symbols 8311* CRIS-Syntax:: Syntax 8312 8313 8314File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent 8315 83169.8.1 Command-line Options 8317-------------------------- 8318 8319The CRIS version of `as' has these machine-dependent command-line 8320options. 8321 8322 The format of the generated object files can be either ELF or a.out, 8323specified by the command-line options `--emulation=crisaout' and 8324`--emulation=criself'. The default is ELF (criself), unless `as' has 8325been configured specifically for a.out by using the configuration name 8326`cris-axis-aout'. 8327 8328 There are two different link-incompatible ELF object file variants 8329for CRIS, for use in environments where symbols are expected to be 8330prefixed by a leading `_' character and for environments without such a 8331symbol prefix. The variant used for GNU/Linux port has no symbol 8332prefix. Which variant to produce is specified by either of the options 8333`--underscore' and `--no-underscore'. The default is `--underscore'. 8334Since symbols in CRIS a.out objects are expected to have a `_' prefix, 8335specifying `--no-underscore' when generating a.out objects is an error. 8336Besides the object format difference, the effect of this option is to 8337parse register names differently (*note crisnous::). The 8338`--no-underscore' option makes a `$' register prefix mandatory. 8339 8340 The option `--pic' must be passed to `as' in order to recognize the 8341symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note 8342crispic::). This will also affect expansion of instructions. The 8343expansion with `--pic' will use PC-relative rather than (slightly 8344faster) absolute addresses in those expansions. This option is only 8345valid when generating ELF format object files. 8346 8347 The option `--march=ARCHITECTURE' specifies the recognized 8348instruction set and recognized register names. It also controls the 8349architecture type of the object file. Valid values for ARCHITECTURE 8350are: 8351`v0_v10' 8352 All instructions and register names for any architecture variant 8353 in the set v0...v10 are recognized. This is the default if the 8354 target is configured as cris-*. 8355 8356`v10' 8357 Only instructions and register names for CRIS v10 (as found in 8358 ETRAX 100 LX) are recognized. This is the default if the target 8359 is configured as crisv10-*. 8360 8361`v32' 8362 Only instructions and register names for CRIS v32 (code name 8363 Guinness) are recognized. This is the default if the target is 8364 configured as crisv32-*. This value implies `--no-mul-bug-abort'. 8365 (A subsequent `--mul-bug-abort' will turn it back on.) 8366 8367`common_v10_v32' 8368 Only instructions with register names and addressing modes with 8369 opcodes common to the v10 and v32 are recognized. 8370 8371 When `-N' is specified, `as' will emit a warning when a 16-bit 8372branch instruction is expanded into a 32-bit multiple-instruction 8373construct (*note CRIS-Expand::). 8374 8375 Some versions of the CRIS v10, for example in the Etrax 100 LX, 8376contain a bug that causes destabilizing memory accesses when a multiply 8377instruction is executed with certain values in the first operand just 8378before a cache-miss. When the `--mul-bug-abort' command line option is 8379active (the default value), `as' will refuse to assemble a file 8380containing a multiply instruction at a dangerous offset, one that could 8381be the last on a cache-line, or is in a section with insufficient 8382alignment. This placement checking does not catch any case where the 8383multiply instruction is dangerously placed because it is located in a 8384delay-slot. The `--mul-bug-abort' command line option turns off the 8385checking. 8386 8387 8388File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent 8389 83909.8.2 Instruction expansion 8391--------------------------- 8392 8393`as' will silently choose an instruction that fits the operand size for 8394`[register+constant]' operands. For example, the offset `127' in 8395`move.d [r3+127],r4' fits in an instruction using a signed-byte offset. 8396Similarly, `move.d [r2+32767],r1' will generate an instruction using a 839716-bit offset. For symbolic expressions and constants that do not fit 8398in 16 bits including the sign bit, a 32-bit offset is generated. 8399 8400 For branches, `as' will expand from a 16-bit branch instruction into 8401a sequence of instructions that can reach a full 32-bit address. Since 8402this does not correspond to a single instruction, such expansions can 8403optionally be warned about. *Note CRIS-Opts::. 8404 8405 If the operand is found to fit the range, a `lapc' mnemonic will 8406translate to a `lapcq' instruction. Use `lapc.d' to force the 32-bit 8407`lapc' instruction. 8408 8409 Similarly, the `addo' mnemonic will translate to the shortest 8410fitting instruction of `addoq', `addo.w' and `addo.d', when used with a 8411operand that is a constant known at assembly time. 8412 8413 8414File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent 8415 84169.8.3 Symbols 8417------------- 8418 8419Some symbols are defined by the assembler. They're intended to be used 8420in conditional assembly, for example: 8421 .if ..asm.arch.cris.v32 8422 CODE FOR CRIS V32 8423 .elseif ..asm.arch.cris.common_v10_v32 8424 CODE COMMON TO CRIS V32 AND CRIS V10 8425 .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10 8426 CODE FOR V10 8427 .else 8428 .error "Code needs to be added here." 8429 .endif 8430 8431 These symbols are defined in the assembler, reflecting command-line 8432options, either when specified or the default. They are always 8433defined, to 0 or 1. 8434`..asm.arch.cris.any_v0_v10' 8435 This symbol is non-zero when `--march=v0_v10' is specified or the 8436 default. 8437 8438`..asm.arch.cris.common_v10_v32' 8439 Set according to the option `--march=common_v10_v32'. 8440 8441`..asm.arch.cris.v10' 8442 Reflects the option `--march=v10'. 8443 8444`..asm.arch.cris.v32' 8445 Corresponds to `--march=v10'. 8446 8447 Speaking of symbols, when a symbol is used in code, it can have a 8448suffix modifying its value for use in position-independent code. *Note 8449CRIS-Pic::. 8450 8451 8452File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent 8453 84549.8.4 Syntax 8455------------ 8456 8457There are different aspects of the CRIS assembly syntax. 8458 8459* Menu: 8460 8461* CRIS-Chars:: Special Characters 8462* CRIS-Pic:: Position-Independent Code Symbols 8463* CRIS-Regs:: Register Names 8464* CRIS-Pseudos:: Assembler Directives 8465 8466 8467File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax 8468 84699.8.4.1 Special Characters 8470.......................... 8471 8472The character `#' is a line comment character. It starts a comment if 8473and only if it is placed at the beginning of a line. 8474 8475 A `;' character starts a comment anywhere on the line, causing all 8476characters up to the end of the line to be ignored. 8477 8478 A `@' character is handled as a line separator equivalent to a 8479logical new-line character (except in a comment), so separate 8480instructions can be specified on a single line. 8481 8482 8483File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax 8484 84859.8.4.2 Symbols in position-independent code 8486............................................ 8487 8488When generating position-independent code (SVR4 PIC) for use in 8489cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol 8490suffixes are used to specify what kind of run-time symbol lookup will 8491be used, expressed in the object as different _relocation types_. 8492Usually, all absolute symbol values must be located in a table, the 8493_global offset table_, leaving the code position-independent; 8494independent of values of global symbols and independent of the address 8495of the code. The suffix modifies the value of the symbol, into for 8496example an index into the global offset table where the real symbol 8497value is entered, or a PC-relative value, or a value relative to the 8498start of the global offset table. All symbol suffixes start with the 8499character `:' (omitted in the list below). Every symbol use in code or 8500a read-only section must therefore have a PIC suffix to enable a useful 8501shared library to be created. Usually, these constructs must not be 8502used with an additive constant offset as is usually allowed, i.e. no 4 8503as in `symbol + 4' is allowed. This restriction is checked at 8504link-time, not at assembly-time. 8505 8506`GOT' 8507 Attaching this suffix to a symbol in an instruction causes the 8508 symbol to be entered into the global offset table. The value is a 8509 32-bit index for that symbol into the global offset table. The 8510 name of the corresponding relocation is `R_CRIS_32_GOT'. Example: 8511 `move.d [$r0+extsym:GOT],$r9' 8512 8513`GOT16' 8514 Same as for `GOT', but the value is a 16-bit index into the global 8515 offset table. The corresponding relocation is `R_CRIS_16_GOT'. 8516 Example: `move.d [$r0+asymbol:GOT16],$r10' 8517 8518`PLT' 8519 This suffix is used for function symbols. It causes a _procedure 8520 linkage table_, an array of code stubs, to be created at the time 8521 the shared object is created or linked against, together with a 8522 global offset table entry. The value is a pc-relative offset to 8523 the corresponding stub code in the procedure linkage table. This 8524 arrangement causes the run-time symbol resolver to be called to 8525 look up and set the value of the symbol the first time the 8526 function is called (at latest; depending environment variables). 8527 It is only safe to leave the symbol unresolved this way if all 8528 references are function calls. The name of the relocation is 8529 `R_CRIS_32_PLT_PCREL'. Example: `add.d fnname:PLT,$pc' 8530 8531`PLTG' 8532 Like PLT, but the value is relative to the beginning of the global 8533 offset table. The relocation is `R_CRIS_32_PLT_GOTREL'. Example: 8534 `move.d fnname:PLTG,$r3' 8535 8536`GOTPLT' 8537 Similar to `PLT', but the value of the symbol is a 32-bit index 8538 into the global offset table. This is somewhat of a mix between 8539 the effect of the `GOT' and the `PLT' suffix; the difference to 8540 `GOT' is that there will be a procedure linkage table entry 8541 created, and that the symbol is assumed to be a function entry and 8542 will be resolved by the run-time resolver as with `PLT'. The 8543 relocation is `R_CRIS_32_GOTPLT'. Example: `jsr 8544 [$r0+fnname:GOTPLT]' 8545 8546`GOTPLT16' 8547 A variant of `GOTPLT' giving a 16-bit value. Its relocation name 8548 is `R_CRIS_16_GOTPLT'. Example: `jsr [$r0+fnname:GOTPLT16]' 8549 8550`GOTOFF' 8551 This suffix must only be attached to a local symbol, but may be 8552 used in an expression adding an offset. The value is the address 8553 of the symbol relative to the start of the global offset table. 8554 The relocation name is `R_CRIS_32_GOTREL'. Example: `move.d 8555 [$r0+localsym:GOTOFF],r3' 8556 8557 8558File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax 8559 85609.8.4.3 Register names 8561...................... 8562 8563A `$' character may always prefix a general or special register name in 8564an instruction operand but is mandatory when the option 8565`--no-underscore' is specified or when the `.syntax register_prefix' 8566directive is in effect (*note crisnous::). Register names are 8567case-insensitive. 8568 8569 8570File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax 8571 85729.8.4.4 Assembler Directives 8573............................ 8574 8575There are a few CRIS-specific pseudo-directives in addition to the 8576generic ones. *Note Pseudo Ops::. Constants emitted by 8577pseudo-directives are in little-endian order for CRIS. There is no 8578support for floating-point-specific directives for CRIS. 8579 8580`.dword EXPRESSIONS' 8581 The `.dword' directive is a synonym for `.int', expecting zero or 8582 more EXPRESSIONS, separated by commas. For each expression, a 8583 32-bit little-endian constant is emitted. 8584 8585`.syntax ARGUMENT' 8586 The `.syntax' directive takes as ARGUMENT one of the following 8587 case-sensitive choices. 8588 8589 `no_register_prefix' 8590 The `.syntax no_register_prefix' directive makes a `$' 8591 character prefix on all registers optional. It overrides a 8592 previous setting, including the corresponding effect of the 8593 option `--no-underscore'. If this directive is used when 8594 ordinary symbols do not have a `_' character prefix, care 8595 must be taken to avoid ambiguities whether an operand is a 8596 register or a symbol; using symbols with names the same as 8597 general or special registers then invoke undefined behavior. 8598 8599 `register_prefix' 8600 This directive makes a `$' character prefix on all registers 8601 mandatory. It overrides a previous setting, including the 8602 corresponding effect of the option `--underscore'. 8603 8604 `leading_underscore' 8605 This is an assertion directive, emitting an error if the 8606 `--no-underscore' option is in effect. 8607 8608 `no_leading_underscore' 8609 This is the opposite of the `.syntax leading_underscore' 8610 directive and emits an error if the option `--underscore' is 8611 in effect. 8612 8613`.arch ARGUMENT' 8614 This is an assertion directive, giving an error if the specified 8615 ARGUMENT is not the same as the specified or default value for the 8616 `--march=ARCHITECTURE' option (*note march-option::). 8617 8618 8619 8620File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies 8621 86229.9 D10V Dependent Features 8623=========================== 8624 8625* Menu: 8626 8627* D10V-Opts:: D10V Options 8628* D10V-Syntax:: Syntax 8629* D10V-Float:: Floating Point 8630* D10V-Opcodes:: Opcodes 8631 8632 8633File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent 8634 86359.9.1 D10V Options 8636------------------ 8637 8638The Mitsubishi D10V version of `as' has a few machine dependent options. 8639 8640`-O' 8641 The D10V can often execute two sub-instructions in parallel. When 8642 this option is used, `as' will attempt to optimize its output by 8643 detecting when instructions can be executed in parallel. 8644 8645`--nowarnswap' 8646 To optimize execution performance, `as' will sometimes swap the 8647 order of instructions. Normally this generates a warning. When 8648 this option is used, no warning will be generated when 8649 instructions are swapped. 8650 8651`--gstabs-packing' 8652`--no-gstabs-packing' 8653 `as' packs adjacent short instructions into a single packed 8654 instruction. `--no-gstabs-packing' turns instruction packing off if 8655 `--gstabs' is specified as well; `--gstabs-packing' (the default) 8656 turns instruction packing on even when `--gstabs' is specified. 8657 8658 8659File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent 8660 86619.9.2 Syntax 8662------------ 8663 8664The D10V syntax is based on the syntax in Mitsubishi's D10V 8665architecture manual. The differences are detailed below. 8666 8667* Menu: 8668 8669* D10V-Size:: Size Modifiers 8670* D10V-Subs:: Sub-Instructions 8671* D10V-Chars:: Special Characters 8672* D10V-Regs:: Register Names 8673* D10V-Addressing:: Addressing Modes 8674* D10V-Word:: @WORD Modifier 8675 8676 8677File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax 8678 86799.9.2.1 Size Modifiers 8680...................... 8681 8682The D10V version of `as' uses the instruction names in the D10V 8683Architecture Manual. However, the names in the manual are sometimes 8684ambiguous. There are instruction names that can assemble to a short or 8685long form opcode. How does the assembler pick the correct form? `as' 8686will always pick the smallest form if it can. When dealing with a 8687symbol that is not defined yet when a line is being assembled, it will 8688always use the long form. If you need to force the assembler to use 8689either the short or long form of the instruction, you can append either 8690`.s' (short) or `.l' (long) to it. For example, if you are writing an 8691assembly program and you want to do a branch to a symbol that is 8692defined later in your program, you can write `bra.s foo'. Objdump 8693and GDB will always append `.s' or `.l' to instructions which have both 8694short and long forms. 8695 8696 8697File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax 8698 86999.9.2.2 Sub-Instructions 8700........................ 8701 8702The D10V assembler takes as input a series of instructions, either 8703one-per-line, or in the special two-per-line format described in the 8704next section. Some of these instructions will be short-form or 8705sub-instructions. These sub-instructions can be packed into a single 8706instruction. The assembler will do this automatically. It will also 8707detect when it should not pack instructions. For example, when a label 8708is defined, the next instruction will never be packaged with the 8709previous one. Whenever a branch and link instruction is called, it 8710will not be packaged with the next instruction so the return address 8711will be valid. Nops are automatically inserted when necessary. 8712 8713 If you do not want the assembler automatically making these 8714decisions, you can control the packaging and execution type (parallel 8715or sequential) with the special execution symbols described in the next 8716section. 8717 8718 8719File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax 8720 87219.9.2.3 Special Characters 8722.......................... 8723 8724A semicolon (`;') can be used anywhere on a line to start a comment 8725that extends to the end of the line. 8726 8727 If a `#' appears as the first character of a line, the whole line is 8728treated as a comment, but in this case the line could also be a logical 8729line number directive (*note Comments::) or a preprocessor control 8730command (*note Preprocessing::). 8731 8732 Sub-instructions may be executed in order, in reverse-order, or in 8733parallel. Instructions listed in the standard one-per-line format will 8734be executed sequentially. To specify the executing order, use the 8735following symbols: 8736`->' 8737 Sequential with instruction on the left first. 8738 8739`<-' 8740 Sequential with instruction on the right first. 8741 8742`||' 8743 Parallel 8744 The D10V syntax allows either one instruction per line, one 8745instruction per line with the execution symbol, or two instructions per 8746line. For example 8747`abs a1 -> abs r0' 8748 Execute these sequentially. The instruction on the right is in 8749 the right container and is executed second. 8750 8751`abs r0 <- abs a1' 8752 Execute these reverse-sequentially. The instruction on the right 8753 is in the right container, and is executed first. 8754 8755`ld2w r2,@r8+ || mac a0,r0,r7' 8756 Execute these in parallel. 8757 8758`ld2w r2,@r8+ ||' 8759`mac a0,r0,r7' 8760 Two-line format. Execute these in parallel. 8761 8762`ld2w r2,@r8+' 8763`mac a0,r0,r7' 8764 Two-line format. Execute these sequentially. Assembler will put 8765 them in the proper containers. 8766 8767`ld2w r2,@r8+ ->' 8768`mac a0,r0,r7' 8769 Two-line format. Execute these sequentially. Same as above but 8770 second instruction will always go into right container. 8771 Since `$' has no special meaning, you may use it in symbol names. 8772 8773 8774File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax 8775 87769.9.2.4 Register Names 8777...................... 8778 8779You can use the predefined symbols `r0' through `r15' to refer to the 8780D10V registers. You can also use `sp' as an alias for `r15'. The 8781accumulators are `a0' and `a1'. There are special register-pair names 8782that may optionally be used in opcodes that require even-numbered 8783registers. Register names are not case sensitive. 8784 8785 Register Pairs 8786`r0-r1' 8787 8788`r2-r3' 8789 8790`r4-r5' 8791 8792`r6-r7' 8793 8794`r8-r9' 8795 8796`r10-r11' 8797 8798`r12-r13' 8799 8800`r14-r15' 8801 8802 The D10V also has predefined symbols for these control registers and 8803status bits: 8804`psw' 8805 Processor Status Word 8806 8807`bpsw' 8808 Backup Processor Status Word 8809 8810`pc' 8811 Program Counter 8812 8813`bpc' 8814 Backup Program Counter 8815 8816`rpt_c' 8817 Repeat Count 8818 8819`rpt_s' 8820 Repeat Start address 8821 8822`rpt_e' 8823 Repeat End address 8824 8825`mod_s' 8826 Modulo Start address 8827 8828`mod_e' 8829 Modulo End address 8830 8831`iba' 8832 Instruction Break Address 8833 8834`f0' 8835 Flag 0 8836 8837`f1' 8838 Flag 1 8839 8840`c' 8841 Carry flag 8842 8843 8844File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax 8845 88469.9.2.5 Addressing Modes 8847........................ 8848 8849`as' understands the following addressing modes for the D10V. `RN' in 8850the following refers to any of the numbered registers, but _not_ the 8851control registers. 8852`RN' 8853 Register direct 8854 8855`@RN' 8856 Register indirect 8857 8858`@RN+' 8859 Register indirect with post-increment 8860 8861`@RN-' 8862 Register indirect with post-decrement 8863 8864`@-SP' 8865 Register indirect with pre-decrement 8866 8867`@(DISP, RN)' 8868 Register indirect with displacement 8869 8870`ADDR' 8871 PC relative address (for branch or rep). 8872 8873`#IMM' 8874 Immediate data (the `#' is optional and ignored) 8875 8876 8877File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax 8878 88799.9.2.6 @WORD Modifier 8880...................... 8881 8882Any symbol followed by `@word' will be replaced by the symbol's value 8883shifted right by 2. This is used in situations such as loading a 8884register with the address of a function (or any other code fragment). 8885For example, if you want to load a register with the location of the 8886function `main' then jump to that function, you could do it as follows: 8887 ldi r2, main@word 8888 jmp r2 8889 8890 8891File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent 8892 88939.9.3 Floating Point 8894-------------------- 8895 8896The D10V has no hardware floating point, but the `.float' and `.double' 8897directives generates IEEE floating-point numbers for compatibility with 8898other development tools. 8899 8900 8901File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent 8902 89039.9.4 Opcodes 8904------------- 8905 8906For detailed information on the D10V machine instruction set, see `D10V 8907Architecture: A VLIW Microprocessor for Multimedia Applications' 8908(Mitsubishi Electric Corp.). `as' implements all the standard D10V 8909opcodes. The only changes are those described in the section on size 8910modifiers 8911 8912 8913File: as.info, Node: D30V-Dependent, Next: Epiphany-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies 8914 89159.10 D30V Dependent Features 8916============================ 8917 8918* Menu: 8919 8920* D30V-Opts:: D30V Options 8921* D30V-Syntax:: Syntax 8922* D30V-Float:: Floating Point 8923* D30V-Opcodes:: Opcodes 8924 8925 8926File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent 8927 89289.10.1 D30V Options 8929------------------- 8930 8931The Mitsubishi D30V version of `as' has a few machine dependent options. 8932 8933`-O' 8934 The D30V can often execute two sub-instructions in parallel. When 8935 this option is used, `as' will attempt to optimize its output by 8936 detecting when instructions can be executed in parallel. 8937 8938`-n' 8939 When this option is used, `as' will issue a warning every time it 8940 adds a nop instruction. 8941 8942`-N' 8943 When this option is used, `as' will issue a warning if it needs to 8944 insert a nop after a 32-bit multiply before a load or 16-bit 8945 multiply instruction. 8946 8947 8948File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent 8949 89509.10.2 Syntax 8951------------- 8952 8953The D30V syntax is based on the syntax in Mitsubishi's D30V 8954architecture manual. The differences are detailed below. 8955 8956* Menu: 8957 8958* D30V-Size:: Size Modifiers 8959* D30V-Subs:: Sub-Instructions 8960* D30V-Chars:: Special Characters 8961* D30V-Guarded:: Guarded Execution 8962* D30V-Regs:: Register Names 8963* D30V-Addressing:: Addressing Modes 8964 8965 8966File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax 8967 89689.10.2.1 Size Modifiers 8969....................... 8970 8971The D30V version of `as' uses the instruction names in the D30V 8972Architecture Manual. However, the names in the manual are sometimes 8973ambiguous. There are instruction names that can assemble to a short or 8974long form opcode. How does the assembler pick the correct form? `as' 8975will always pick the smallest form if it can. When dealing with a 8976symbol that is not defined yet when a line is being assembled, it will 8977always use the long form. If you need to force the assembler to use 8978either the short or long form of the instruction, you can append either 8979`.s' (short) or `.l' (long) to it. For example, if you are writing an 8980assembly program and you want to do a branch to a symbol that is 8981defined later in your program, you can write `bra.s foo'. Objdump and 8982GDB will always append `.s' or `.l' to instructions which have both 8983short and long forms. 8984 8985 8986File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax 8987 89889.10.2.2 Sub-Instructions 8989......................... 8990 8991The D30V assembler takes as input a series of instructions, either 8992one-per-line, or in the special two-per-line format described in the 8993next section. Some of these instructions will be short-form or 8994sub-instructions. These sub-instructions can be packed into a single 8995instruction. The assembler will do this automatically. It will also 8996detect when it should not pack instructions. For example, when a label 8997is defined, the next instruction will never be packaged with the 8998previous one. Whenever a branch and link instruction is called, it 8999will not be packaged with the next instruction so the return address 9000will be valid. Nops are automatically inserted when necessary. 9001 9002 If you do not want the assembler automatically making these 9003decisions, you can control the packaging and execution type (parallel 9004or sequential) with the special execution symbols described in the next 9005section. 9006 9007 9008File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax 9009 90109.10.2.3 Special Characters 9011........................... 9012 9013A semicolon (`;') can be used anywhere on a line to start a comment 9014that extends to the end of the line. 9015 9016 If a `#' appears as the first character of a line, the whole line is 9017treated as a comment, but in this case the line could also be a logical 9018line number directive (*note Comments::) or a preprocessor control 9019command (*note Preprocessing::). 9020 9021 Sub-instructions may be executed in order, in reverse-order, or in 9022parallel. Instructions listed in the standard one-per-line format will 9023be executed sequentially unless you use the `-O' option. 9024 9025 To specify the executing order, use the following symbols: 9026`->' 9027 Sequential with instruction on the left first. 9028 9029`<-' 9030 Sequential with instruction on the right first. 9031 9032`||' 9033 Parallel 9034 9035 The D30V syntax allows either one instruction per line, one 9036instruction per line with the execution symbol, or two instructions per 9037line. For example 9038`abs r2,r3 -> abs r4,r5' 9039 Execute these sequentially. The instruction on the right is in 9040 the right container and is executed second. 9041 9042`abs r2,r3 <- abs r4,r5' 9043 Execute these reverse-sequentially. The instruction on the right 9044 is in the right container, and is executed first. 9045 9046`abs r2,r3 || abs r4,r5' 9047 Execute these in parallel. 9048 9049`ldw r2,@(r3,r4) ||' 9050`mulx r6,r8,r9' 9051 Two-line format. Execute these in parallel. 9052 9053`mulx a0,r8,r9' 9054`stw r2,@(r3,r4)' 9055 Two-line format. Execute these sequentially unless `-O' option is 9056 used. If the `-O' option is used, the assembler will determine if 9057 the instructions could be done in parallel (the above two 9058 instructions can be done in parallel), and if so, emit them as 9059 parallel instructions. The assembler will put them in the proper 9060 containers. In the above example, the assembler will put the 9061 `stw' instruction in left container and the `mulx' instruction in 9062 the right container. 9063 9064`stw r2,@(r3,r4) ->' 9065`mulx a0,r8,r9' 9066 Two-line format. Execute the `stw' instruction followed by the 9067 `mulx' instruction sequentially. The first instruction goes in the 9068 left container and the second instruction goes into right 9069 container. The assembler will give an error if the machine 9070 ordering constraints are violated. 9071 9072`stw r2,@(r3,r4) <-' 9073`mulx a0,r8,r9' 9074 Same as previous example, except that the `mulx' instruction is 9075 executed before the `stw' instruction. 9076 9077 Since `$' has no special meaning, you may use it in symbol names. 9078 9079 9080File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax 9081 90829.10.2.4 Guarded Execution 9083.......................... 9084 9085`as' supports the full range of guarded execution directives for each 9086instruction. Just append the directive after the instruction proper. 9087The directives are: 9088 9089`/tx' 9090 Execute the instruction if flag f0 is true. 9091 9092`/fx' 9093 Execute the instruction if flag f0 is false. 9094 9095`/xt' 9096 Execute the instruction if flag f1 is true. 9097 9098`/xf' 9099 Execute the instruction if flag f1 is false. 9100 9101`/tt' 9102 Execute the instruction if both flags f0 and f1 are true. 9103 9104`/tf' 9105 Execute the instruction if flag f0 is true and flag f1 is false. 9106 9107 9108File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax 9109 91109.10.2.5 Register Names 9111....................... 9112 9113You can use the predefined symbols `r0' through `r63' to refer to the 9114D30V registers. You can also use `sp' as an alias for `r63' and `link' 9115as an alias for `r62'. The accumulators are `a0' and `a1'. 9116 9117 The D30V also has predefined symbols for these control registers and 9118status bits: 9119`psw' 9120 Processor Status Word 9121 9122`bpsw' 9123 Backup Processor Status Word 9124 9125`pc' 9126 Program Counter 9127 9128`bpc' 9129 Backup Program Counter 9130 9131`rpt_c' 9132 Repeat Count 9133 9134`rpt_s' 9135 Repeat Start address 9136 9137`rpt_e' 9138 Repeat End address 9139 9140`mod_s' 9141 Modulo Start address 9142 9143`mod_e' 9144 Modulo End address 9145 9146`iba' 9147 Instruction Break Address 9148 9149`f0' 9150 Flag 0 9151 9152`f1' 9153 Flag 1 9154 9155`f2' 9156 Flag 2 9157 9158`f3' 9159 Flag 3 9160 9161`f4' 9162 Flag 4 9163 9164`f5' 9165 Flag 5 9166 9167`f6' 9168 Flag 6 9169 9170`f7' 9171 Flag 7 9172 9173`s' 9174 Same as flag 4 (saturation flag) 9175 9176`v' 9177 Same as flag 5 (overflow flag) 9178 9179`va' 9180 Same as flag 6 (sticky overflow flag) 9181 9182`c' 9183 Same as flag 7 (carry/borrow flag) 9184 9185`b' 9186 Same as flag 7 (carry/borrow flag) 9187 9188 9189File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax 9190 91919.10.2.6 Addressing Modes 9192......................... 9193 9194`as' understands the following addressing modes for the D30V. `RN' in 9195the following refers to any of the numbered registers, but _not_ the 9196control registers. 9197`RN' 9198 Register direct 9199 9200`@RN' 9201 Register indirect 9202 9203`@RN+' 9204 Register indirect with post-increment 9205 9206`@RN-' 9207 Register indirect with post-decrement 9208 9209`@-SP' 9210 Register indirect with pre-decrement 9211 9212`@(DISP, RN)' 9213 Register indirect with displacement 9214 9215`ADDR' 9216 PC relative address (for branch or rep). 9217 9218`#IMM' 9219 Immediate data (the `#' is optional and ignored) 9220 9221 9222File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent 9223 92249.10.3 Floating Point 9225--------------------- 9226 9227The D30V has no hardware floating point, but the `.float' and `.double' 9228directives generates IEEE floating-point numbers for compatibility with 9229other development tools. 9230 9231 9232File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent 9233 92349.10.4 Opcodes 9235-------------- 9236 9237For detailed information on the D30V machine instruction set, see `D30V 9238Architecture: A VLIW Microprocessor for Multimedia Applications' 9239(Mitsubishi Electric Corp.). `as' implements all the standard D30V 9240opcodes. The only changes are those described in the section on size 9241modifiers 9242 9243 9244File: as.info, Node: Epiphany-Dependent, Next: H8/300-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies 9245 92469.11 Epiphany Dependent Features 9247================================ 9248 9249* Menu: 9250 9251* Epiphany Options:: Options 9252* Epiphany Syntax:: Epiphany Syntax 9253 9254 9255File: as.info, Node: Epiphany Options, Next: Epiphany Syntax, Up: Epiphany-Dependent 9256 92579.11.1 Options 9258-------------- 9259 9260`as' has two additional command-line options for the Epiphany 9261architecture. 9262 9263`-mepiphany' 9264 Specifies that the both 32 and 16 bit instructions are allowed. 9265 This is the default behavior. 9266 9267`-mepiphany16' 9268 Restricts the permitted instructions to just the 16 bit set. 9269 9270 9271File: as.info, Node: Epiphany Syntax, Prev: Epiphany Options, Up: Epiphany-Dependent 9272 92739.11.2 Epiphany Syntax 9274---------------------- 9275 9276* Menu: 9277 9278* Epiphany-Chars:: Special Characters 9279 9280 9281File: as.info, Node: Epiphany-Chars, Up: Epiphany Syntax 9282 92839.11.2.1 Special Characters 9284........................... 9285 9286The presence of a `;' on a line indicates the start of a comment that 9287extends to the end of the current line. 9288 9289 If a `#' appears as the first character of a line then the whole 9290line is treated as a comment, but in this case the line could also be a 9291logical line number directive (*note Comments::) or a preprocessor 9292control command (*note Preprocessing::). 9293 9294 The ``' character can be used to separate statements on the same 9295line. 9296 9297 9298File: as.info, Node: H8/300-Dependent, Next: HPPA-Dependent, Prev: Epiphany-Dependent, Up: Machine Dependencies 9299 93009.12 H8/300 Dependent Features 9301============================== 9302 9303* Menu: 9304 9305* H8/300 Options:: Options 9306* H8/300 Syntax:: Syntax 9307* H8/300 Floating Point:: Floating Point 9308* H8/300 Directives:: H8/300 Machine Directives 9309* H8/300 Opcodes:: Opcodes 9310 9311 9312File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent 9313 93149.12.1 Options 9315-------------- 9316 9317The Renesas H8/300 version of `as' has one machine-dependent option: 9318 9319`-h-tick-hex' 9320 Support H'00 style hex constants in addition to 0x00 style. 9321 9322 9323 9324File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent 9325 93269.12.2 Syntax 9327------------- 9328 9329* Menu: 9330 9331* H8/300-Chars:: Special Characters 9332* H8/300-Regs:: Register Names 9333* H8/300-Addressing:: Addressing Modes 9334 9335 9336File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax 9337 93389.12.2.1 Special Characters 9339........................... 9340 9341`;' is the line comment character. 9342 9343 `$' can be used instead of a newline to separate statements. 9344Therefore _you may not use `$' in symbol names_ on the H8/300. 9345 9346 9347File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax 9348 93499.12.2.2 Register Names 9350....................... 9351 9352You can use predefined symbols of the form `rNh' and `rNl' to refer to 9353the H8/300 registers as sixteen 8-bit general-purpose registers. N is 9354a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid 9355register names. 9356 9357 You can also use the eight predefined symbols `rN' to refer to the 9358H8/300 registers as 16-bit registers (you must use this form for 9359addressing). 9360 9361 On the H8/300H, you can also use the eight predefined symbols `erN' 9362(`er0' ... `er7') to refer to the 32-bit general purpose registers. 9363 9364 The two control registers are called `pc' (program counter; a 16-bit 9365register, except on the H8/300H where it is 24 bits) and `ccr' 9366(condition code register; an 8-bit register). `r7' is used as the 9367stack pointer, and can also be called `sp'. 9368 9369 9370File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax 9371 93729.12.2.3 Addressing Modes 9373......................... 9374 9375as understands the following addressing modes for the H8/300: 9376`rN' 9377 Register direct 9378 9379`@rN' 9380 Register indirect 9381 9382`@(D, rN)' 9383`@(D:16, rN)' 9384`@(D:24, rN)' 9385 Register indirect: 16-bit or 24-bit displacement D from register 9386 N. (24-bit displacements are only meaningful on the H8/300H.) 9387 9388`@rN+' 9389 Register indirect with post-increment 9390 9391`@-rN' 9392 Register indirect with pre-decrement 9393 9394``@'AA' 9395``@'AA:8' 9396``@'AA:16' 9397``@'AA:24' 9398 Absolute address `aa'. (The address size `:24' only makes sense 9399 on the H8/300H.) 9400 9401`#XX' 9402`#XX:8' 9403`#XX:16' 9404`#XX:32' 9405 Immediate data XX. You may specify the `:8', `:16', or `:32' for 9406 clarity, if you wish; but `as' neither requires this nor uses 9407 it--the data size required is taken from context. 9408 9409``@'`@'AA' 9410``@'`@'AA:8' 9411 Memory indirect. You may specify the `:8' for clarity, if you 9412 wish; but `as' neither requires this nor uses it. 9413 9414 9415File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent 9416 94179.12.3 Floating Point 9418--------------------- 9419 9420The H8/300 family has no hardware floating point, but the `.float' 9421directive generates IEEE floating-point numbers for compatibility with 9422other development tools. 9423 9424 9425File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent 9426 94279.12.4 H8/300 Machine Directives 9428-------------------------------- 9429 9430`as' has the following machine-dependent directives for the H8/300: 9431 9432`.h8300h' 9433 Recognize and emit additional instructions for the H8/300H 9434 variant, and also make `.int' emit 32-bit numbers rather than the 9435 usual (16-bit) for the H8/300 family. 9436 9437`.h8300s' 9438 Recognize and emit additional instructions for the H8S variant, and 9439 also make `.int' emit 32-bit numbers rather than the usual (16-bit) 9440 for the H8/300 family. 9441 9442`.h8300hn' 9443 Recognize and emit additional instructions for the H8/300H variant 9444 in normal mode, and also make `.int' emit 32-bit numbers rather 9445 than the usual (16-bit) for the H8/300 family. 9446 9447`.h8300sn' 9448 Recognize and emit additional instructions for the H8S variant in 9449 normal mode, and also make `.int' emit 32-bit numbers rather than 9450 the usual (16-bit) for the H8/300 family. 9451 9452 On the H8/300 family (including the H8/300H) `.word' directives 9453generate 16-bit numbers. 9454 9455 9456File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent 9457 94589.12.5 Opcodes 9459-------------- 9460 9461For detailed information on the H8/300 machine instruction set, see 9462`H8/300 Series Programming Manual'. For information specific to the 9463H8/300H, see `H8/300H Series Programming Manual' (Renesas). 9464 9465 `as' implements all the standard H8/300 opcodes. No additional 9466pseudo-instructions are needed on this family. 9467 9468 The following table summarizes the H8/300 opcodes, and their 9469arguments. Entries marked `*' are opcodes used only on the H8/300H. 9470 9471 Legend: 9472 Rs source register 9473 Rd destination register 9474 abs absolute address 9475 imm immediate data 9476 disp:N N-bit displacement from a register 9477 pcrel:N N-bit displacement relative to program counter 9478 9479 add.b #imm,rd * andc #imm,ccr 9480 add.b rs,rd band #imm,rd 9481 add.w rs,rd band #imm,@rd 9482 * add.w #imm,rd band #imm,@abs:8 9483 * add.l rs,rd bra pcrel:8 9484 * add.l #imm,rd * bra pcrel:16 9485 adds #imm,rd bt pcrel:8 9486 addx #imm,rd * bt pcrel:16 9487 addx rs,rd brn pcrel:8 9488 and.b #imm,rd * brn pcrel:16 9489 and.b rs,rd bf pcrel:8 9490 * and.w rs,rd * bf pcrel:16 9491 * and.w #imm,rd bhi pcrel:8 9492 * and.l #imm,rd * bhi pcrel:16 9493 * and.l rs,rd bls pcrel:8 9494 9495 * bls pcrel:16 bld #imm,rd 9496 bcc pcrel:8 bld #imm,@rd 9497 * bcc pcrel:16 bld #imm,@abs:8 9498 bhs pcrel:8 bnot #imm,rd 9499 * bhs pcrel:16 bnot #imm,@rd 9500 bcs pcrel:8 bnot #imm,@abs:8 9501 * bcs pcrel:16 bnot rs,rd 9502 blo pcrel:8 bnot rs,@rd 9503 * blo pcrel:16 bnot rs,@abs:8 9504 bne pcrel:8 bor #imm,rd 9505 * bne pcrel:16 bor #imm,@rd 9506 beq pcrel:8 bor #imm,@abs:8 9507 * beq pcrel:16 bset #imm,rd 9508 bvc pcrel:8 bset #imm,@rd 9509 * bvc pcrel:16 bset #imm,@abs:8 9510 bvs pcrel:8 bset rs,rd 9511 * bvs pcrel:16 bset rs,@rd 9512 bpl pcrel:8 bset rs,@abs:8 9513 * bpl pcrel:16 bsr pcrel:8 9514 bmi pcrel:8 bsr pcrel:16 9515 * bmi pcrel:16 bst #imm,rd 9516 bge pcrel:8 bst #imm,@rd 9517 * bge pcrel:16 bst #imm,@abs:8 9518 blt pcrel:8 btst #imm,rd 9519 * blt pcrel:16 btst #imm,@rd 9520 bgt pcrel:8 btst #imm,@abs:8 9521 * bgt pcrel:16 btst rs,rd 9522 ble pcrel:8 btst rs,@rd 9523 * ble pcrel:16 btst rs,@abs:8 9524 bclr #imm,rd bxor #imm,rd 9525 bclr #imm,@rd bxor #imm,@rd 9526 bclr #imm,@abs:8 bxor #imm,@abs:8 9527 bclr rs,rd cmp.b #imm,rd 9528 bclr rs,@rd cmp.b rs,rd 9529 bclr rs,@abs:8 cmp.w rs,rd 9530 biand #imm,rd cmp.w rs,rd 9531 biand #imm,@rd * cmp.w #imm,rd 9532 biand #imm,@abs:8 * cmp.l #imm,rd 9533 bild #imm,rd * cmp.l rs,rd 9534 bild #imm,@rd daa rs 9535 bild #imm,@abs:8 das rs 9536 bior #imm,rd dec.b rs 9537 bior #imm,@rd * dec.w #imm,rd 9538 bior #imm,@abs:8 * dec.l #imm,rd 9539 bist #imm,rd divxu.b rs,rd 9540 bist #imm,@rd * divxu.w rs,rd 9541 bist #imm,@abs:8 * divxs.b rs,rd 9542 bixor #imm,rd * divxs.w rs,rd 9543 bixor #imm,@rd eepmov 9544 bixor #imm,@abs:8 * eepmovw 9545 9546 * exts.w rd mov.w rs,@abs:16 9547 * exts.l rd * mov.l #imm,rd 9548 * extu.w rd * mov.l rs,rd 9549 * extu.l rd * mov.l @rs,rd 9550 inc rs * mov.l @(disp:16,rs),rd 9551 * inc.w #imm,rd * mov.l @(disp:24,rs),rd 9552 * inc.l #imm,rd * mov.l @rs+,rd 9553 jmp @rs * mov.l @abs:16,rd 9554 jmp abs * mov.l @abs:24,rd 9555 jmp @@abs:8 * mov.l rs,@rd 9556 jsr @rs * mov.l rs,@(disp:16,rd) 9557 jsr abs * mov.l rs,@(disp:24,rd) 9558 jsr @@abs:8 * mov.l rs,@-rd 9559 ldc #imm,ccr * mov.l rs,@abs:16 9560 ldc rs,ccr * mov.l rs,@abs:24 9561 * ldc @abs:16,ccr movfpe @abs:16,rd 9562 * ldc @abs:24,ccr movtpe rs,@abs:16 9563 * ldc @(disp:16,rs),ccr mulxu.b rs,rd 9564 * ldc @(disp:24,rs),ccr * mulxu.w rs,rd 9565 * ldc @rs+,ccr * mulxs.b rs,rd 9566 * ldc @rs,ccr * mulxs.w rs,rd 9567 * mov.b @(disp:24,rs),rd neg.b rs 9568 * mov.b rs,@(disp:24,rd) * neg.w rs 9569 mov.b @abs:16,rd * neg.l rs 9570 mov.b rs,rd nop 9571 mov.b @abs:8,rd not.b rs 9572 mov.b rs,@abs:8 * not.w rs 9573 mov.b rs,rd * not.l rs 9574 mov.b #imm,rd or.b #imm,rd 9575 mov.b @rs,rd or.b rs,rd 9576 mov.b @(disp:16,rs),rd * or.w #imm,rd 9577 mov.b @rs+,rd * or.w rs,rd 9578 mov.b @abs:8,rd * or.l #imm,rd 9579 mov.b rs,@rd * or.l rs,rd 9580 mov.b rs,@(disp:16,rd) orc #imm,ccr 9581 mov.b rs,@-rd pop.w rs 9582 mov.b rs,@abs:8 * pop.l rs 9583 mov.w rs,@rd push.w rs 9584 * mov.w @(disp:24,rs),rd * push.l rs 9585 * mov.w rs,@(disp:24,rd) rotl.b rs 9586 * mov.w @abs:24,rd * rotl.w rs 9587 * mov.w rs,@abs:24 * rotl.l rs 9588 mov.w rs,rd rotr.b rs 9589 mov.w #imm,rd * rotr.w rs 9590 mov.w @rs,rd * rotr.l rs 9591 mov.w @(disp:16,rs),rd rotxl.b rs 9592 mov.w @rs+,rd * rotxl.w rs 9593 mov.w @abs:16,rd * rotxl.l rs 9594 mov.w rs,@(disp:16,rd) rotxr.b rs 9595 mov.w rs,@-rd * rotxr.w rs 9596 9597 * rotxr.l rs * stc ccr,@(disp:24,rd) 9598 bpt * stc ccr,@-rd 9599 rte * stc ccr,@abs:16 9600 rts * stc ccr,@abs:24 9601 shal.b rs sub.b rs,rd 9602 * shal.w rs sub.w rs,rd 9603 * shal.l rs * sub.w #imm,rd 9604 shar.b rs * sub.l rs,rd 9605 * shar.w rs * sub.l #imm,rd 9606 * shar.l rs subs #imm,rd 9607 shll.b rs subx #imm,rd 9608 * shll.w rs subx rs,rd 9609 * shll.l rs * trapa #imm 9610 shlr.b rs xor #imm,rd 9611 * shlr.w rs xor rs,rd 9612 * shlr.l rs * xor.w #imm,rd 9613 sleep * xor.w rs,rd 9614 stc ccr,rd * xor.l #imm,rd 9615 * stc ccr,@rs * xor.l rs,rd 9616 * stc ccr,@(disp:16,rd) xorc #imm,ccr 9617 9618 Four H8/300 instructions (`add', `cmp', `mov', `sub') are defined 9619with variants using the suffixes `.b', `.w', and `.l' to specify the 9620size of a memory operand. `as' supports these suffixes, but does not 9621require them; since one of the operands is always a register, `as' can 9622deduce the correct size. 9623 9624 For example, since `r0' refers to a 16-bit register, 9625 mov r0,@foo 9626is equivalent to 9627 mov.w r0,@foo 9628 9629 If you use the size suffixes, `as' issues a warning when the suffix 9630and the register size do not match. 9631 9632 9633File: as.info, Node: HPPA-Dependent, Next: ESA/390-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies 9634 96359.13 HPPA Dependent Features 9636============================ 9637 9638* Menu: 9639 9640* HPPA Notes:: Notes 9641* HPPA Options:: Options 9642* HPPA Syntax:: Syntax 9643* HPPA Floating Point:: Floating Point 9644* HPPA Directives:: HPPA Machine Directives 9645* HPPA Opcodes:: Opcodes 9646 9647 9648File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent 9649 96509.13.1 Notes 9651------------ 9652 9653As a back end for GNU CC `as' has been throughly tested and should work 9654extremely well. We have tested it only minimally on hand written 9655assembly code and no one has tested it much on the assembly output from 9656the HP compilers. 9657 9658 The format of the debugging sections has changed since the original 9659`as' port (version 1.3X) was released; therefore, you must rebuild all 9660HPPA objects and libraries with the new assembler so that you can debug 9661the final executable. 9662 9663 The HPPA `as' port generates a small subset of the relocations 9664available in the SOM and ELF object file formats. Additional relocation 9665support will be added as it becomes necessary. 9666 9667 9668File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent 9669 96709.13.2 Options 9671-------------- 9672 9673`as' has no machine-dependent command-line options for the HPPA. 9674 9675 9676File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent 9677 96789.13.3 Syntax 9679------------- 9680 9681The assembler syntax closely follows the HPPA instruction set reference 9682manual; assembler directives and general syntax closely follow the HPPA 9683assembly language reference manual, with a few noteworthy differences. 9684 9685 First, a colon may immediately follow a label definition. This is 9686simply for compatibility with how most assembly language programmers 9687write code. 9688 9689 Some obscure expression parsing problems may affect hand written 9690code which uses the `spop' instructions, or code which makes significant 9691use of the `!' line separator. 9692 9693 `as' is much less forgiving about missing arguments and other 9694similar oversights than the HP assembler. `as' notifies you of missing 9695arguments as syntax errors; this is regarded as a feature, not a bug. 9696 9697 Finally, `as' allows you to use an external symbol without 9698explicitly importing the symbol. _Warning:_ in the future this will be 9699an error for HPPA targets. 9700 9701 Special characters for HPPA targets include: 9702 9703 `;' is the line comment character. 9704 9705 `!' can be used instead of a newline to separate statements. 9706 9707 Since `$' has no special meaning, you may use it in symbol names. 9708 9709 9710File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent 9711 97129.13.4 Floating Point 9713--------------------- 9714 9715The HPPA family uses IEEE floating-point numbers. 9716 9717 9718File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent 9719 97209.13.5 HPPA Assembler Directives 9721-------------------------------- 9722 9723`as' for the HPPA supports many additional directives for compatibility 9724with the native assembler. This section describes them only briefly. 9725For detailed information on HPPA-specific assembler directives, see 9726`HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001). 9727 9728 `as' does _not_ support the following assembler directives described 9729in the HP manual: 9730 9731 .endm .liston 9732 .enter .locct 9733 .leave .macro 9734 .listoff 9735 9736 Beyond those implemented for compatibility, `as' supports one 9737additional assembler directive for the HPPA: `.param'. It conveys 9738register argument locations for static functions. Its syntax closely 9739follows the `.export' directive. 9740 9741 These are the additional directives in `as' for the HPPA: 9742 9743`.block N' 9744`.blockz N' 9745 Reserve N bytes of storage, and initialize them to zero. 9746 9747`.call' 9748 Mark the beginning of a procedure call. Only the special case 9749 with _no arguments_ is allowed. 9750 9751`.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]' 9752 Specify a number of parameters and flags that define the 9753 environment for a procedure. 9754 9755 PARAM may be any of `frame' (frame size), `entry_gr' (end of 9756 general register range), `entry_fr' (end of float register range), 9757 `entry_sr' (end of space register range). 9758 9759 The values for FLAG are `calls' or `caller' (proc has 9760 subroutines), `no_calls' (proc does not call subroutines), 9761 `save_rp' (preserve return pointer), `save_sp' (proc preserves 9762 stack pointer), `no_unwind' (do not unwind this proc), `hpux_int' 9763 (proc is interrupt routine). 9764 9765`.code' 9766 Assemble into the standard section called `$TEXT$', subsection 9767 `$CODE$'. 9768 9769`.copyright "STRING"' 9770 In the SOM object format, insert STRING into the object code, 9771 marked as a copyright string. 9772 9773`.copyright "STRING"' 9774 In the ELF object format, insert STRING into the object code, 9775 marked as a version string. 9776 9777`.enter' 9778 Not yet supported; the assembler rejects programs containing this 9779 directive. 9780 9781`.entry' 9782 Mark the beginning of a procedure. 9783 9784`.exit' 9785 Mark the end of a procedure. 9786 9787`.export NAME [ ,TYP ] [ ,PARAM=R ]' 9788 Make a procedure NAME available to callers. TYP, if present, must 9789 be one of `absolute', `code' (ELF only, not SOM), `data', `entry', 9790 `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'. 9791 9792 PARAM, if present, provides either relocation information for the 9793 procedure arguments and result, or a privilege level. PARAM may be 9794 `argwN' (where N ranges from `0' to `3', and indicates one of four 9795 one-word arguments); `rtnval' (the procedure's result); or 9796 `priv_lev' (privilege level). For arguments or the result, R 9797 specifies how to relocate, and must be one of `no' (not 9798 relocatable), `gr' (argument is in general register), `fr' (in 9799 floating point register), or `fu' (upper half of float register). 9800 For `priv_lev', R is an integer. 9801 9802`.half N' 9803 Define a two-byte integer constant N; synonym for the portable 9804 `as' directive `.short'. 9805 9806`.import NAME [ ,TYP ]' 9807 Converse of `.export'; make a procedure available to call. The 9808 arguments use the same conventions as the first two arguments for 9809 `.export'. 9810 9811`.label NAME' 9812 Define NAME as a label for the current assembly location. 9813 9814`.leave' 9815 Not yet supported; the assembler rejects programs containing this 9816 directive. 9817 9818`.origin LC' 9819 Advance location counter to LC. Synonym for the `as' portable 9820 directive `.org'. 9821 9822`.param NAME [ ,TYP ] [ ,PARAM=R ]' 9823 Similar to `.export', but used for static procedures. 9824 9825`.proc' 9826 Use preceding the first statement of a procedure. 9827 9828`.procend' 9829 Use following the last statement of a procedure. 9830 9831`LABEL .reg EXPR' 9832 Synonym for `.equ'; define LABEL with the absolute expression EXPR 9833 as its value. 9834 9835`.space SECNAME [ ,PARAMS ]' 9836 Switch to section SECNAME, creating a new section by that name if 9837 necessary. You may only use PARAMS when creating a new section, 9838 not when switching to an existing one. SECNAME may identify a 9839 section by number rather than by name. 9840 9841 If specified, the list PARAMS declares attributes of the section, 9842 identified by keywords. The keywords recognized are `spnum=EXP' 9843 (identify this section by the number EXP, an absolute expression), 9844 `sort=EXP' (order sections according to this sort key when linking; 9845 EXP is an absolute expression), `unloadable' (section contains no 9846 loadable data), `notdefined' (this section defined elsewhere), and 9847 `private' (data in this section not available to other programs). 9848 9849`.spnum SECNAM' 9850 Allocate four bytes of storage, and initialize them with the 9851 section number of the section named SECNAM. (You can define the 9852 section number with the HPPA `.space' directive.) 9853 9854`.string "STR"' 9855 Copy the characters in the string STR to the object file. *Note 9856 Strings: Strings, for information on escape sequences you can use 9857 in `as' strings. 9858 9859 _Warning!_ The HPPA version of `.string' differs from the usual 9860 `as' definition: it does _not_ write a zero byte after copying STR. 9861 9862`.stringz "STR"' 9863 Like `.string', but appends a zero byte after copying STR to object 9864 file. 9865 9866`.subspa NAME [ ,PARAMS ]' 9867`.nsubspa NAME [ ,PARAMS ]' 9868 Similar to `.space', but selects a subsection NAME within the 9869 current section. You may only specify PARAMS when you create a 9870 subsection (in the first instance of `.subspa' for this NAME). 9871 9872 If specified, the list PARAMS declares attributes of the 9873 subsection, identified by keywords. The keywords recognized are 9874 `quad=EXPR' ("quadrant" for this subsection), `align=EXPR' 9875 (alignment for beginning of this subsection; a power of two), 9876 `access=EXPR' (value for "access rights" field), `sort=EXPR' 9877 (sorting order for this subspace in link), `code_only' (subsection 9878 contains only code), `unloadable' (subsection cannot be loaded 9879 into memory), `comdat' (subsection is comdat), `common' 9880 (subsection is common block), `dup_comm' (subsection may have 9881 duplicate names), or `zero' (subsection is all zeros, do not write 9882 in object file). 9883 9884 `.nsubspa' always creates a new subspace with the given name, even 9885 if one with the same name already exists. 9886 9887 `comdat', `common' and `dup_comm' can be used to implement various 9888 flavors of one-only support when using the SOM linker. The SOM 9889 linker only supports specific combinations of these flags. The 9890 details are not documented. A brief description is provided here. 9891 9892 `comdat' provides a form of linkonce support. It is useful for 9893 both code and data subspaces. A `comdat' subspace has a key symbol 9894 marked by the `is_comdat' flag or `ST_COMDAT'. Only the first 9895 subspace for any given key is selected. The key symbol becomes 9896 universal in shared links. This is similar to the behavior of 9897 `secondary_def' symbols. 9898 9899 `common' provides Fortran named common support. It is only useful 9900 for data subspaces. Symbols with the flag `is_common' retain this 9901 flag in shared links. Referencing a `is_common' symbol in a shared 9902 library from outside the library doesn't work. Thus, `is_common' 9903 symbols must be output whenever they are needed. 9904 9905 `common' and `dup_comm' together provide Cobol common support. 9906 The subspaces in this case must all be the same length. 9907 Otherwise, this support is similar to the Fortran common support. 9908 9909 `dup_comm' by itself provides a type of one-only support for code. 9910 Only the first `dup_comm' subspace is selected. There is a rather 9911 complex algorithm to compare subspaces. Code symbols marked with 9912 the `dup_common' flag are hidden. This support was intended for 9913 "C++ duplicate inlines". 9914 9915 A simplified technique is used to mark the flags of symbols based 9916 on the flags of their subspace. A symbol with the scope 9917 SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with 9918 the corresponding settings of `comdat', `common' and `dup_comm' 9919 from the subspace, respectively. This avoids having to introduce 9920 additional directives to mark these symbols. The HP assembler 9921 sets `is_common' from `common'. However, it doesn't set the 9922 `dup_common' from `dup_comm'. It doesn't have `comdat' support. 9923 9924`.version "STR"' 9925 Write STR as version identifier in object code. 9926 9927 9928File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent 9929 99309.13.6 Opcodes 9931-------------- 9932 9933For detailed information on the HPPA machine instruction set, see 9934`PA-RISC Architecture and Instruction Set Reference Manual' (HP 993509740-90039). 9936 9937 9938File: as.info, Node: ESA/390-Dependent, Next: i386-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies 9939 99409.14 ESA/390 Dependent Features 9941=============================== 9942 9943* Menu: 9944 9945* ESA/390 Notes:: Notes 9946* ESA/390 Options:: Options 9947* ESA/390 Syntax:: Syntax 9948* ESA/390 Floating Point:: Floating Point 9949* ESA/390 Directives:: ESA/390 Machine Directives 9950* ESA/390 Opcodes:: Opcodes 9951 9952 9953File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Dependent 9954 99559.14.1 Notes 9956------------ 9957 9958The ESA/390 `as' port is currently intended to be a back-end for the 9959GNU CC compiler. It is not HLASM compatible, although it does support 9960a subset of some of the HLASM directives. The only supported binary 9961file format is ELF; none of the usual MVS/VM/OE/USS object file 9962formats, such as ESD or XSD, are supported. 9963 9964 When used with the GNU CC compiler, the ESA/390 `as' will produce 9965correct, fully relocated, functional binaries, and has been used to 9966compile and execute large projects. However, many aspects should still 9967be considered experimental; these include shared library support, 9968dynamically loadable objects, and any relocation other than the 31-bit 9969relocation. 9970 9971 9972File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Notes, Up: ESA/390-Dependent 9973 99749.14.2 Options 9975-------------- 9976 9977`as' has no machine-dependent command-line options for the ESA/390. 9978 9979 9980File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent 9981 99829.14.3 Syntax 9983------------- 9984 9985The opcode/operand syntax follows the ESA/390 Principles of Operation 9986manual; assembler directives and general syntax are loosely based on the 9987prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives 9988are _not_ supported for the most part, with the exception of those 9989described herein. 9990 9991 A leading dot in front of directives is optional, and the case of 9992directives is ignored; thus for example, .using and USING have the same 9993effect. 9994 9995 A colon may immediately follow a label definition. This is simply 9996for compatibility with how most assembly language programmers write 9997code. 9998 9999 `#' is the line comment character. 10000 10001 `;' can be used instead of a newline to separate statements. 10002 10003 Since `$' has no special meaning, you may use it in symbol names. 10004 10005 Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, 10006fp6. By using thesse symbolic names, `as' can detect simple syntax 10007errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for 10008r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base 10009for r3 and rpgt or r.pgt for r4. 10010 10011 `*' is the current location counter. Unlike `.' it is always 10012relative to the last USING directive. Note that this means that 10013expressions cannot use multiplication, as any occurrence of `*' will be 10014interpreted as a location counter. 10015 10016 All labels are relative to the last USING. Thus, branches to a label 10017always imply the use of base+displacement. 10018 10019 Many of the usual forms of address constants / address literals are 10020supported. Thus, 10021 .using *,r3 10022 L r15,=A(some_routine) 10023 LM r6,r7,=V(some_longlong_extern) 10024 A r1,=F'12' 10025 AH r0,=H'42' 10026 ME r6,=E'3.1416' 10027 MD r6,=D'3.14159265358979' 10028 O r6,=XL4'cacad0d0' 10029 .ltorg 10030 should all behave as expected: that is, an entry in the literal pool 10031will be created (or reused if it already exists), and the instruction 10032operands will be the displacement into the literal pool using the 10033current base register (as last declared with the `.using' directive). 10034 10035 10036File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent 10037 100389.14.4 Floating Point 10039--------------------- 10040 10041The assembler generates only IEEE floating-point numbers. The older 10042floating point formats are not supported. 10043 10044 10045File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 Floating Point, Up: ESA/390-Dependent 10046 100479.14.5 ESA/390 Assembler Directives 10048----------------------------------- 10049 10050`as' for the ESA/390 supports all of the standard ELF/SVR4 assembler 10051directives that are documented in the main part of this documentation. 10052Several additional directives are supported in order to implement the 10053ESA/390 addressing model. The most important of these are `.using' and 10054`.ltorg' 10055 10056 These are the additional directives in `as' for the ESA/390: 10057 10058`.dc' 10059 A small subset of the usual DC directive is supported. 10060 10061`.drop REGNO' 10062 Stop using REGNO as the base register. The REGNO must have been 10063 previously declared with a `.using' directive in the same section 10064 as the current section. 10065 10066`.ebcdic STRING' 10067 Emit the EBCDIC equivalent of the indicated string. The emitted 10068 string will be null terminated. Note that the directives 10069 `.string' etc. emit ascii strings by default. 10070 10071`EQU' 10072 The standard HLASM-style EQU directive is not supported; however, 10073 the standard `as' directive .equ can be used to the same effect. 10074 10075`.ltorg' 10076 Dump the literal pool accumulated so far; begin a new literal pool. 10077 The literal pool will be written in the current section; in order 10078 to generate correct assembly, a `.using' must have been previously 10079 specified in the same section. 10080 10081`.using EXPR,REGNO' 10082 Use REGNO as the base register for all subsequent RX, RS, and SS 10083 form instructions. The EXPR will be evaluated to obtain the base 10084 address; usually, EXPR will merely be `*'. 10085 10086 This assembler allows two `.using' directives to be simultaneously 10087 outstanding, one in the `.text' section, and one in another section 10088 (typically, the `.data' section). This feature allows dynamically 10089 loaded objects to be implemented in a relatively straightforward 10090 way. A `.using' directive must always be specified in the `.text' 10091 section; this will specify the base register that will be used for 10092 branches in the `.text' section. A second `.using' may be 10093 specified in another section; this will specify the base register 10094 that is used for non-label address literals. When a second 10095 `.using' is specified, then the subsequent `.ltorg' must be put in 10096 the same section; otherwise an error will result. 10097 10098 Thus, for example, the following code uses `r3' to address branch 10099 targets and `r4' to address the literal pool, which has been 10100 written to the `.data' section. The is, the constants 10101 `=A(some_routine)', `=H'42'' and `=E'3.1416'' will all appear in 10102 the `.data' section. 10103 10104 .data 10105 .using LITPOOL,r4 10106 .text 10107 BASR r3,0 10108 .using *,r3 10109 B START 10110 .long LITPOOL 10111 START: 10112 L r4,4(,r3) 10113 L r15,=A(some_routine) 10114 LTR r15,r15 10115 BNE LABEL 10116 AH r0,=H'42' 10117 LABEL: 10118 ME r6,=E'3.1416' 10119 .data 10120 LITPOOL: 10121 .ltorg 10122 10123 Note that this dual-`.using' directive semantics extends and is 10124 not compatible with HLASM semantics. Note that this assembler 10125 directive does not support the full range of HLASM semantics. 10126 10127 10128 10129File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent 10130 101319.14.6 Opcodes 10132-------------- 10133 10134For detailed information on the ESA/390 machine instruction set, see 10135`ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004). 10136 10137 10138File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies 10139 101409.15 80386 Dependent Features 10141============================= 10142 10143 The i386 version `as' supports both the original Intel 386 10144architecture in both 16 and 32-bit mode as well as AMD x86-64 10145architecture extending the Intel architecture to 64-bits. 10146 10147* Menu: 10148 10149* i386-Options:: Options 10150* i386-Directives:: X86 specific directives 10151* i386-Syntax:: Syntactical considerations 10152* i386-Mnemonics:: Instruction Naming 10153* i386-Regs:: Register Naming 10154* i386-Prefixes:: Instruction Prefixes 10155* i386-Memory:: Memory References 10156* i386-Jumps:: Handling of Jump Instructions 10157* i386-Float:: Floating Point 10158* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 10159* i386-LWP:: AMD's Lightweight Profiling Instructions 10160* i386-BMI:: Bit Manipulation Instruction 10161* i386-TBM:: AMD's Trailing Bit Manipulation Instructions 10162* i386-16bit:: Writing 16-bit Code 10163* i386-Arch:: Specifying an x86 CPU architecture 10164* i386-Bugs:: AT&T Syntax bugs 10165* i386-Notes:: Notes 10166 10167 10168File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent 10169 101709.15.1 Options 10171-------------- 10172 10173The i386 version of `as' has a few machine dependent options: 10174 10175`--32 | --x32 | --64' 10176 Select the word size, either 32 bits or 64 bits. `--32' implies 10177 Intel i386 architecture, while `--x32' and `--64' imply AMD x86-64 10178 architecture with 32-bit or 64-bit word-size respectively. 10179 10180 These options are only available with the ELF object file format, 10181 and require that the necessary BFD support has been included (on a 10182 32-bit platform you have to add -enable-64-bit-bfd to configure 10183 enable 64-bit usage and use x86-64 as target platform). 10184 10185`-n' 10186 By default, x86 GAS replaces multiple nop instructions used for 10187 alignment within code sections with multi-byte nop instructions 10188 such as leal 0(%esi,1),%esi. This switch disables the 10189 optimization. 10190 10191`--divide' 10192 On SVR4-derived platforms, the character `/' is treated as a 10193 comment character, which means that it cannot be used in 10194 expressions. The `--divide' option turns `/' into a normal 10195 character. This does not disable `/' at the beginning of a line 10196 starting a comment, or affect using `#' for starting a comment. 10197 10198`-march=CPU[+EXTENSION...]' 10199 This option specifies the target processor. The assembler will 10200 issue an error message if an attempt is made to assemble an 10201 instruction which will not execute on the target processor. The 10202 following processor names are recognized: `i8086', `i186', `i286', 10203 `i386', `i486', `i586', `i686', `pentium', `pentiumpro', 10204 `pentiumii', `pentiumiii', `pentium4', `prescott', `nocona', 10205 `core', `core2', `corei7', `l1om', `k1om', `k6', `k6_2', `athlon', 10206 `opteron', `k8', `amdfam10', `bdver1', `bdver2', `bdver3', 10207 `btver1', `btver2', `generic32' and `generic64'. 10208 10209 In addition to the basic instruction set, the assembler can be 10210 told to accept various extension mnemonics. For example, 10211 `-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The 10212 following extensions are currently supported: `8087', `287', `387', 10213 `no87', `mmx', `nommx', `sse', `sse2', `sse3', `ssse3', `sse4.1', 10214 `sse4.2', `sse4', `nosse', `avx', `avx2', `adx', `rdseed', 10215 `prfchw', `smap', `mpx', `sha', `avx512f', `avx512cd', `avx512er', 10216 `avx512pf', `noavx', `vmx', `vmfunc', `smx', `xsave', `xsaveopt', 10217 `aes', `pclmul', `fsgsbase', `rdrnd', `f16c', `bmi2', `fma', 10218 `movbe', `ept', `lzcnt', `hle', `rtm', `invpcid', `clflush', `lwp', 10219 `fma4', `xop', `cx16', `syscall', `rdtscp', `3dnow', `3dnowa', 10220 `sse4a', `sse5', `svme', `abm' and `padlock'. Note that rather 10221 than extending a basic instruction set, the extension mnemonics 10222 starting with `no' revoke the respective functionality. 10223 10224 When the `.arch' directive is used with `-march', the `.arch' 10225 directive will take precedent. 10226 10227`-mtune=CPU' 10228 This option specifies a processor to optimize for. When used in 10229 conjunction with the `-march' option, only instructions of the 10230 processor specified by the `-march' option will be generated. 10231 10232 Valid CPU values are identical to the processor list of 10233 `-march=CPU'. 10234 10235`-msse2avx' 10236 This option specifies that the assembler should encode SSE 10237 instructions with VEX prefix. 10238 10239`-msse-check=NONE' 10240`-msse-check=WARNING' 10241`-msse-check=ERROR' 10242 These options control if the assembler should check SSE 10243 instructions. `-msse-check=NONE' will make the assembler not to 10244 check SSE instructions, which is the default. 10245 `-msse-check=WARNING' will make the assembler issue a warning for 10246 any SSE instruction. `-msse-check=ERROR' will make the assembler 10247 issue an error for any SSE instruction. 10248 10249`-mavxscalar=128' 10250`-mavxscalar=256' 10251 These options control how the assembler should encode scalar AVX 10252 instructions. `-mavxscalar=128' will encode scalar AVX 10253 instructions with 128bit vector length, which is the default. 10254 `-mavxscalar=256' will encode scalar AVX instructions with 256bit 10255 vector length. 10256 10257`-mevexlig=128' 10258`-mevexlig=256' 10259`-mevexlig=512' 10260 These options control how the assembler should encode 10261 length-ignored (LIG) EVEX instructions. `-mevexlig=128' will 10262 encode LIG EVEX instructions with 128bit vector length, which is 10263 the default. `-mevexlig=256' and `-mevexlig=512' will encode LIG 10264 EVEX instructions with 256bit and 512bit vector length, 10265 respectively. 10266 10267`-mevexwig=0' 10268`-mevexwig=1' 10269 These options control how the assembler should encode w-ignored 10270 (WIG) EVEX instructions. `-mevexwig=0' will encode WIG EVEX 10271 instructions with evex.w = 0, which is the default. `-mevexwig=1' 10272 will encode WIG EVEX instructions with evex.w = 1. 10273 10274`-mmnemonic=ATT' 10275`-mmnemonic=INTEL' 10276 This option specifies instruction mnemonic for matching 10277 instructions. The `.att_mnemonic' and `.intel_mnemonic' 10278 directives will take precedent. 10279 10280`-msyntax=ATT' 10281`-msyntax=INTEL' 10282 This option specifies instruction syntax when processing 10283 instructions. The `.att_syntax' and `.intel_syntax' directives 10284 will take precedent. 10285 10286`-mnaked-reg' 10287 This opetion specifies that registers don't require a `%' prefix. 10288 The `.att_syntax' and `.intel_syntax' directives will take 10289 precedent. 10290 10291`-madd-bnd-prefix' 10292 This option forces the assembler to add BND prefix to all 10293 branches, even if such prefix was not explicitly specified in the 10294 source code. 10295 10296 10297 10298File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent 10299 103009.15.2 x86 specific Directives 10301------------------------------ 10302 10303`.lcomm SYMBOL , LENGTH[, ALIGNMENT]' 10304 Reserve LENGTH (an absolute expression) bytes for a local common 10305 denoted by SYMBOL. The section and value of SYMBOL are those of 10306 the new local common. The addresses are allocated in the bss 10307 section, so that at run-time the bytes start off zeroed. Since 10308 SYMBOL is not declared global, it is normally not visible to `ld'. 10309 The optional third parameter, ALIGNMENT, specifies the desired 10310 alignment of the symbol in the bss section. 10311 10312 This directive is only available for COFF based x86 targets. 10313 10314 10315 10316File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent 10317 103189.15.3 i386 Syntactical Considerations 10319-------------------------------------- 10320 10321* Menu: 10322 10323* i386-Variations:: AT&T Syntax versus Intel Syntax 10324* i386-Chars:: Special Characters 10325 10326 10327File: as.info, Node: i386-Variations, Next: i386-Chars, Up: i386-Syntax 10328 103299.15.3.1 AT&T Syntax versus Intel Syntax 10330........................................ 10331 10332`as' now supports assembly using Intel assembler syntax. 10333`.intel_syntax' selects Intel mode, and `.att_syntax' switches back to 10334the usual AT&T mode for compatibility with the output of `gcc'. Either 10335of these directives may have an optional argument, `prefix', or 10336`noprefix' specifying whether registers require a `%' prefix. AT&T 10337System V/386 assembler syntax is quite different from Intel syntax. We 10338mention these differences because almost all 80386 documents use Intel 10339syntax. Notable differences between the two syntaxes are: 10340 10341 * AT&T immediate operands are preceded by `$'; Intel immediate 10342 operands are undelimited (Intel `push 4' is AT&T `pushl $4'). 10343 AT&T register operands are preceded by `%'; Intel register operands 10344 are undelimited. AT&T absolute (as opposed to PC relative) 10345 jump/call operands are prefixed by `*'; they are undelimited in 10346 Intel syntax. 10347 10348 * AT&T and Intel syntax use the opposite order for source and 10349 destination operands. Intel `add eax, 4' is `addl $4, %eax'. The 10350 `source, dest' convention is maintained for compatibility with 10351 previous Unix assemblers. Note that `bound', `invlpga', and 10352 instructions with 2 immediate operands, such as the `enter' 10353 instruction, do _not_ have reversed order. *note i386-Bugs::. 10354 10355 * In AT&T syntax the size of memory operands is determined from the 10356 last character of the instruction mnemonic. Mnemonic suffixes of 10357 `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long 10358 (32-bit) and quadruple word (64-bit) memory references. Intel 10359 syntax accomplishes this by prefixing memory operands (_not_ the 10360 instruction mnemonics) with `byte ptr', `word ptr', `dword ptr' 10361 and `qword ptr'. Thus, Intel `mov al, byte ptr FOO' is `movb FOO, 10362 %al' in AT&T syntax. 10363 10364 In 64-bit code, `movabs' can be used to encode the `mov' 10365 instruction with the 64-bit displacement or immediate operand. 10366 10367 * Immediate form long jumps and calls are `lcall/ljmp $SECTION, 10368 $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far 10369 SECTION:OFFSET'. Also, the far return instruction is `lret 10370 $STACK-ADJUST' in AT&T syntax; Intel syntax is `ret far 10371 STACK-ADJUST'. 10372 10373 * The AT&T assembler does not provide support for multiple section 10374 programs. Unix style systems expect all programs to be single 10375 sections. 10376 10377 10378File: as.info, Node: i386-Chars, Prev: i386-Variations, Up: i386-Syntax 10379 103809.15.3.2 Special Characters 10381........................... 10382 10383The presence of a `#' appearing anywhere on a line indicates the start 10384of a comment that extends to the end of that line. 10385 10386 If a `#' appears as the first character of a line then the whole 10387line is treated as a comment, but in this case the line can also be a 10388logical line number directive (*note Comments::) or a preprocessor 10389control command (*note Preprocessing::). 10390 10391 If the `--divide' command line option has not been specified then 10392the `/' character appearing anywhere on a line also introduces a line 10393comment. 10394 10395 The `;' character can be used to separate statements on the same 10396line. 10397 10398 10399File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent 10400 104019.15.4 Instruction Naming 10402------------------------- 10403 10404Instruction mnemonics are suffixed with one character modifiers which 10405specify the size of operands. The letters `b', `w', `l' and `q' 10406specify byte, word, long and quadruple word operands. If no suffix is 10407specified by an instruction then `as' tries to fill in the missing 10408suffix based on the destination register operand (the last one by 10409convention). Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx'; 10410also, `mov $1, %bx' is equivalent to `movw $1, bx'. Note that this is 10411incompatible with the AT&T Unix assembler which assumes that a missing 10412mnemonic suffix implies long operand size. (This incompatibility does 10413not affect compiler output since compilers always explicitly specify 10414the mnemonic suffix.) 10415 10416 Almost all instructions have the same names in AT&T and Intel format. 10417There are a few exceptions. The sign extend and zero extend 10418instructions need two sizes to specify them. They need a size to 10419sign/zero extend _from_ and a size to zero extend _to_. This is 10420accomplished by using two instruction mnemonic suffixes in AT&T syntax. 10421Base names for sign extend and zero extend are `movs...' and `movz...' 10422in AT&T syntax (`movsx' and `movzx' in Intel syntax). The instruction 10423mnemonic suffixes are tacked on to this base name, the _from_ suffix 10424before the _to_ suffix. Thus, `movsbl %al, %edx' is AT&T syntax for 10425"move sign extend _from_ %al _to_ %edx." Possible suffixes, thus, are 10426`bl' (from byte to long), `bw' (from byte to word), `wl' (from word to 10427long), `bq' (from byte to quadruple word), `wq' (from word to quadruple 10428word), and `lq' (from long to quadruple word). 10429 10430 Different encoding options can be specified via optional mnemonic 10431suffix. `.s' suffix swaps 2 register operands in encoding when moving 10432from one register to another. `.d8' or `.d32' suffix prefers 8bit or 1043332bit displacement in encoding. 10434 10435 The Intel-syntax conversion instructions 10436 10437 * `cbw' -- sign-extend byte in `%al' to word in `%ax', 10438 10439 * `cwde' -- sign-extend word in `%ax' to long in `%eax', 10440 10441 * `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax', 10442 10443 * `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax', 10444 10445 * `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64 10446 only), 10447 10448 * `cqo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax' 10449 (x86-64 only), 10450 10451are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T 10452naming. `as' accepts either naming for these instructions. 10453 10454 Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax, 10455but are `call far' and `jump far' in Intel convention. 10456 104579.15.5 AT&T Mnemonic versus Intel Mnemonic 10458------------------------------------------ 10459 10460`as' supports assembly using Intel mnemonic. `.intel_mnemonic' selects 10461Intel mnemonic with Intel syntax, and `.att_mnemonic' switches back to 10462the usual AT&T mnemonic with AT&T syntax for compatibility with the 10463output of `gcc'. Several x87 instructions, `fadd', `fdiv', `fdivp', 10464`fdivr', `fdivrp', `fmul', `fsub', `fsubp', `fsubr' and `fsubrp', are 10465implemented in AT&T System V/386 assembler with different mnemonics 10466from those in Intel IA32 specification. `gcc' generates those 10467instructions with AT&T mnemonic. 10468 10469 10470File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent 10471 104729.15.6 Register Naming 10473---------------------- 10474 10475Register operands are always prefixed with `%'. The 80386 registers 10476consist of 10477 10478 * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx', 10479 `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp' 10480 (the stack pointer). 10481 10482 * the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di', 10483 `%si', `%bp', and `%sp'. 10484 10485 * the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl', 10486 `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax', 10487 `%bx', `%cx', and `%dx') 10488 10489 * the 6 section registers `%cs' (code section), `%ds' (data 10490 section), `%ss' (stack section), `%es', `%fs', and `%gs'. 10491 10492 * the 3 processor control registers `%cr0', `%cr2', and `%cr3'. 10493 10494 * the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and 10495 `%db7'. 10496 10497 * the 2 test registers `%tr6' and `%tr7'. 10498 10499 * the 8 floating point register stack `%st' or equivalently 10500 `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)', 10501 `%st(6)', and `%st(7)'. These registers are overloaded by 8 MMX 10502 registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6' 10503 and `%mm7'. 10504 10505 * the 8 SSE registers registers `%xmm0', `%xmm1', `%xmm2', `%xmm3', 10506 `%xmm4', `%xmm5', `%xmm6' and `%xmm7'. 10507 10508 The AMD x86-64 architecture extends the register set by: 10509 10510 * enhancing the 8 32-bit registers to 64-bit: `%rax' (the 10511 accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the 10512 frame pointer), `%rsp' (the stack pointer) 10513 10514 * the 8 extended registers `%r8'-`%r15'. 10515 10516 * the 8 32-bit low ends of the extended registers: `%r8d'-`%r15d' 10517 10518 * the 8 16-bit low ends of the extended registers: `%r8w'-`%r15w' 10519 10520 * the 8 8-bit low ends of the extended registers: `%r8b'-`%r15b' 10521 10522 * the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'. 10523 10524 * the 8 debug registers: `%db8'-`%db15'. 10525 10526 * the 8 SSE registers: `%xmm8'-`%xmm15'. 10527 10528 10529File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent 10530 105319.15.7 Instruction Prefixes 10532--------------------------- 10533 10534Instruction prefixes are used to modify the following instruction. They 10535are used to repeat string instructions, to provide section overrides, to 10536perform bus lock operations, and to change operand and address sizes. 10537(Most instructions that normally operate on 32-bit operands will use 1053816-bit operands if the instruction has an "operand size" prefix.) 10539Instruction prefixes are best written on the same line as the 10540instruction they act upon. For example, the `scas' (scan string) 10541instruction is repeated with: 10542 10543 repne scas %es:(%edi),%al 10544 10545 You may also place prefixes on the lines immediately preceding the 10546instruction, but this circumvents checks that `as' does with prefixes, 10547and will not work with all prefixes. 10548 10549 Here is a list of instruction prefixes: 10550 10551 * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'. 10552 These are automatically added by specifying using the 10553 SECTION:MEMORY-OPERAND form for memory references. 10554 10555 * Operand/Address size prefixes `data16' and `addr16' change 32-bit 10556 operands/addresses into 16-bit operands/addresses, while `data32' 10557 and `addr32' change 16-bit ones (in a `.code16' section) into 10558 32-bit operands/addresses. These prefixes _must_ appear on the 10559 same line of code as the instruction they modify. For example, in 10560 a 16-bit `.code16' section, you might write: 10561 10562 addr32 jmpl *(%ebx) 10563 10564 * The bus lock prefix `lock' inhibits interrupts during execution of 10565 the instruction it precedes. (This is only valid with certain 10566 instructions; see a 80386 manual for details). 10567 10568 * The wait for coprocessor prefix `wait' waits for the coprocessor to 10569 complete the current instruction. This should never be needed for 10570 the 80386/80387 combination. 10571 10572 * The `rep', `repe', and `repne' prefixes are added to string 10573 instructions to make them repeat `%ecx' times (`%cx' times if the 10574 current address size is 16-bits). 10575 10576 * The `rex' family of prefixes is used by x86-64 to encode 10577 extensions to i386 instruction set. The `rex' prefix has four 10578 bits -- an operand size overwrite (`64') used to change operand 10579 size from 32-bit to 64-bit and X, Y and Z extensions bits used to 10580 extend the register set. 10581 10582 You may write the `rex' prefixes directly. The `rex64xyz' 10583 instruction emits `rex' prefix with all the bits set. By omitting 10584 the `64', `x', `y' or `z' you may write other prefixes as well. 10585 Normally, there is no need to write the prefixes explicitly, since 10586 gas will automatically generate them based on the instruction 10587 operands. 10588 10589 10590File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent 10591 105929.15.8 Memory References 10593------------------------ 10594 10595An Intel syntax indirect memory reference of the form 10596 10597 SECTION:[BASE + INDEX*SCALE + DISP] 10598 10599is translated into the AT&T syntax 10600 10601 SECTION:DISP(BASE, INDEX, SCALE) 10602 10603where BASE and INDEX are the optional 32-bit base and index registers, 10604DISP is the optional displacement, and SCALE, taking the values 1, 2, 106054, and 8, multiplies INDEX to calculate the address of the operand. If 10606no SCALE is specified, SCALE is taken to be 1. SECTION specifies the 10607optional section register for the memory operand, and may override the 10608default section register (see a 80386 manual for section register 10609defaults). Note that section overrides in AT&T syntax _must_ be 10610preceded by a `%'. If you specify a section override which coincides 10611with the default section register, `as' does _not_ output any section 10612register override prefixes to assemble the given instruction. Thus, 10613section overrides can be specified to emphasize which section register 10614is used for a given memory operand. 10615 10616 Here are some examples of Intel and AT&T style memory references: 10617 10618AT&T: `-4(%ebp)', Intel: `[ebp - 4]' 10619 BASE is `%ebp'; DISP is `-4'. SECTION is missing, and the default 10620 section is used (`%ss' for addressing with `%ebp' as the base 10621 register). INDEX, SCALE are both missing. 10622 10623AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]' 10624 INDEX is `%eax' (scaled by a SCALE 4); DISP is `foo'. All other 10625 fields are missing. The section register here defaults to `%ds'. 10626 10627AT&T: `foo(,1)'; Intel `[foo]' 10628 This uses the value pointed to by `foo' as a memory operand. Note 10629 that BASE and INDEX are both missing, but there is only _one_ `,'. 10630 This is a syntactic exception. 10631 10632AT&T: `%gs:foo'; Intel `gs:foo' 10633 This selects the contents of the variable `foo' with section 10634 register SECTION being `%gs'. 10635 10636 Absolute (as opposed to PC relative) call and jump operands must be 10637prefixed with `*'. If no `*' is specified, `as' always chooses PC 10638relative addressing for jump/call labels. 10639 10640 Any instruction that has a memory operand, but no register operand, 10641_must_ specify its size (byte, word, long, or quadruple) with an 10642instruction mnemonic suffix (`b', `w', `l' or `q', respectively). 10643 10644 The x86-64 architecture adds an RIP (instruction pointer relative) 10645addressing. This addressing mode is specified by using `rip' as a base 10646register. Only constant offsets are valid. For example: 10647 10648AT&T: `1234(%rip)', Intel: `[rip + 1234]' 10649 Points to the address 1234 bytes past the end of the current 10650 instruction. 10651 10652AT&T: `symbol(%rip)', Intel: `[rip + symbol]' 10653 Points to the `symbol' in RIP relative way, this is shorter than 10654 the default absolute addressing. 10655 10656 Other addressing modes remain unchanged in x86-64 architecture, 10657except registers used are 64-bit instead of 32-bit. 10658 10659 10660File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent 10661 106629.15.9 Handling of Jump Instructions 10663------------------------------------ 10664 10665Jump instructions are always optimized to use the smallest possible 10666displacements. This is accomplished by using byte (8-bit) displacement 10667jumps whenever the target is sufficiently close. If a byte displacement 10668is insufficient a long displacement is used. We do not support word 10669(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 10670instruction with the `data16' instruction prefix), since the 80386 10671insists upon masking `%eip' to 16 bits after the word displacement is 10672added. (See also *note i386-Arch::) 10673 10674 Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz' 10675and `loopne' instructions only come in byte displacements, so that if 10676you use these instructions (`gcc' does not use them) you may get an 10677error message (and incorrect code). The AT&T 80386 assembler tries to 10678get around this problem by expanding `jcxz foo' to 10679 10680 jcxz cx_zero 10681 jmp cx_nonzero 10682 cx_zero: jmp foo 10683 cx_nonzero: 10684 10685 10686File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent 10687 106889.15.10 Floating Point 10689---------------------- 10690 10691All 80387 floating point types except packed BCD are supported. (BCD 10692support may be added without much difficulty). These data types are 1069316-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), 10694and extended (80-bit) precision floating point. Each supported type 10695has an instruction mnemonic suffix and a constructor associated with 10696it. Instruction mnemonic suffixes specify the operand's data type. 10697Constructors build these data types into memory. 10698 10699 * Floating point constructors are `.float' or `.single', `.double', 10700 and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond 10701 to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for 10702 80-bit (ten byte) real. The 80387 only supports this format via 10703 the `fldt' (load 80-bit real to stack top) and `fstpt' (store 10704 80-bit real and pop stack) instructions. 10705 10706 * Integer constructors are `.word', `.long' or `.int', and `.quad' 10707 for the 16-, 32-, and 64-bit integer formats. The corresponding 10708 instruction mnemonic suffixes are `s' (single), `l' (long), and 10709 `q' (quad). As with the 80-bit real format, the 64-bit `q' format 10710 is only present in the `fildq' (load quad integer to stack top) 10711 and `fistpq' (store quad integer and pop stack) instructions. 10712 10713 Register to register operations should not use instruction mnemonic 10714suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as 10715if you wrote `fst %st, %st(1)', since all register to register 10716operations use 80-bit floating point operands. (Contrast this with 10717`fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating 10718point format, then stores the result in the 4 byte location `mem') 10719 10720 10721File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-Dependent 10722 107239.15.11 Intel's MMX and AMD's 3DNow! SIMD Operations 10724---------------------------------------------------- 10725 10726`as' supports Intel's MMX instruction set (SIMD instructions for 10727integer data), available on Intel's Pentium MMX processors and Pentium 10728II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and 10729probably others. It also supports AMD's 3DNow! instruction set (SIMD 10730instructions for 32-bit floating point data) available on AMD's K6-2 10731processor and possibly others in the future. 10732 10733 Currently, `as' does not support Intel's floating point SIMD, Katmai 10734(KNI). 10735 10736 The eight 64-bit MMX operands, also used by 3DNow!, are called 10737`%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four 1073816-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 10739floating point values. The MMX registers cannot be used at the same 10740time as the floating point stack. 10741 10742 See Intel and AMD documentation, keeping in mind that the operand 10743order in instructions is reversed from the Intel syntax. 10744 10745 10746File: as.info, Node: i386-LWP, Next: i386-BMI, Prev: i386-SIMD, Up: i386-Dependent 10747 107489.15.12 AMD's Lightweight Profiling Instructions 10749------------------------------------------------ 10750 10751`as' supports AMD's Lightweight Profiling (LWP) instruction set, 10752available on AMD's Family 15h (Orochi) processors. 10753 10754 LWP enables applications to collect and manage performance data, and 10755react to performance events. The collection of performance data 10756requires no context switches. LWP runs in the context of a thread and 10757so several counters can be used independently across multiple threads. 10758LWP can be used in both 64-bit and legacy 32-bit modes. 10759 10760 For detailed information on the LWP instruction set, see the `AMD 10761Lightweight Profiling Specification' available at Lightweight Profiling 10762Specification (http://developer.amd.com/cpu/LWP). 10763 10764 10765File: as.info, Node: i386-BMI, Next: i386-TBM, Prev: i386-LWP, Up: i386-Dependent 10766 107679.15.13 Bit Manipulation Instructions 10768------------------------------------- 10769 10770`as' supports the Bit Manipulation (BMI) instruction set. 10771 10772 BMI instructions provide several instructions implementing individual 10773bit manipulation operations such as isolation, masking, setting, or 10774resetting. 10775 10776 10777File: as.info, Node: i386-TBM, Next: i386-16bit, Prev: i386-BMI, Up: i386-Dependent 10778 107799.15.14 AMD's Trailing Bit Manipulation Instructions 10780---------------------------------------------------- 10781 10782`as' supports AMD's Trailing Bit Manipulation (TBM) instruction set, 10783available on AMD's BDVER2 processors (Trinity and Viperfish). 10784 10785 TBM instructions provide instructions implementing individual bit 10786manipulation operations such as isolating, masking, setting, resetting, 10787complementing, and operations on trailing zeros and ones. 10788 10789 10790File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-TBM, Up: i386-Dependent 10791 107929.15.15 Writing 16-bit Code 10793--------------------------- 10794 10795While `as' normally writes only "pure" 32-bit i386 code or 64-bit 10796x86-64 code depending on the default configuration, it also supports 10797writing code to run in real mode or in 16-bit protected mode code 10798segments. To do this, put a `.code16' or `.code16gcc' directive before 10799the assembly language instructions to be run in 16-bit mode. You can 10800switch `as' to writing 32-bit code with the `.code32' directive or 1080164-bit code with the `.code64' directive. 10802 10803 `.code16gcc' provides experimental support for generating 16-bit 10804code from gcc, and differs from `.code16' in that `call', `ret', 10805`enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf' 10806instructions default to 32-bit size. This is so that the stack pointer 10807is manipulated in the same way over function calls, allowing access to 10808function parameters at the same stack offsets as in 32-bit mode. 10809`.code16gcc' also automatically adds address size prefixes where 10810necessary to use the 32-bit addressing modes that gcc generates. 10811 10812 The code which `as' generates in 16-bit mode will not necessarily 10813run on a 16-bit pre-80386 processor. To write code that runs on such a 10814processor, you must refrain from using _any_ 32-bit constructs which 10815require `as' to output address or operand size prefixes. 10816 10817 Note that writing 16-bit code instructions by explicitly specifying a 10818prefix or an instruction mnemonic suffix within a 32-bit code section 10819generates different machine instructions than those generated for a 1082016-bit code segment. In a 32-bit code section, the following code 10821generates the machine opcode bytes `66 6a 04', which pushes the value 10822`4' onto the stack, decrementing `%esp' by 2. 10823 10824 pushw $4 10825 10826 The same code in a 16-bit code section would generate the machine 10827opcode bytes `6a 04' (i.e., without the operand size prefix), which is 10828correct since the processor default operand size is assumed to be 16 10829bits in a 16-bit code section. 10830 10831 10832File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent 10833 108349.15.16 AT&T Syntax bugs 10835------------------------ 10836 10837The UnixWare assembler, and probably other AT&T derived ix86 Unix 10838assemblers, generate floating point instructions with reversed source 10839and destination registers in certain cases. Unfortunately, gcc and 10840possibly many other programs use this reversed syntax, so we're stuck 10841with it. 10842 10843 For example 10844 10845 fsub %st,%st(3) 10846 results in `%st(3)' being updated to `%st - %st(3)' rather than the 10847expected `%st(3) - %st'. This happens with all the non-commutative 10848arithmetic floating point operations with two register operands where 10849the source register is `%st' and the destination register is `%st(i)'. 10850 10851 10852File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent 10853 108549.15.17 Specifying CPU Architecture 10855----------------------------------- 10856 10857`as' may be told to assemble for a particular CPU (sub-)architecture 10858with the `.arch CPU_TYPE' directive. This directive enables a warning 10859when gas detects an instruction that is not supported on the CPU 10860specified. The choices for CPU_TYPE are: 10861 10862`i8086' `i186' `i286' `i386' 10863`i486' `i586' `i686' `pentium' 10864`pentiumpro' `pentiumii' `pentiumiii' `pentium4' 10865`prescott' `nocona' `core' `core2' 10866`corei7' `l1om' `k1om' 10867`k6' `k6_2' `athlon' `k8' 10868`amdfam10' `bdver1' `bdver2' `bdver3' 10869`btver1' `btver2' 10870`generic32' `generic64' 10871`.mmx' `.sse' `.sse2' `.sse3' 10872`.ssse3' `.sse4.1' `.sse4.2' `.sse4' 10873`.avx' `.vmx' `.smx' `.ept' 10874`.clflush' `.movbe' `.xsave' `.xsaveopt' 10875`.aes' `.pclmul' `.fma' `.fsgsbase' 10876`.rdrnd' `.f16c' `.avx2' `.bmi2' 10877`.lzcnt' `.invpcid' `.vmfunc' `.hle' 10878`.rtm' `.adx' `.rdseed' `.prfchw' 10879`.smap' `.mpx' 10880`.smap' `.sha' 10881`.3dnow' `.3dnowa' `.sse4a' `.sse5' 10882`.syscall' `.rdtscp' `.svme' `.abm' 10883`.lwp' `.fma4' `.xop' `.cx16' 10884`.padlock' 10885`.smap' `.avx512f' `.avx512cd' `.avx512er' 10886`.avx512pf' `.3dnow' `.3dnowa' `.sse4a' 10887`.sse5' `.syscall' `.rdtscp' `.svme' 10888`.abm' `.lwp' `.fma4' `.xop' 10889`.cx16' `.padlock' 10890 10891 Apart from the warning, there are only two other effects on `as' 10892operation; Firstly, if you specify a CPU other than `i486', then shift 10893by one instructions such as `sarl $1, %eax' will automatically use a 10894two byte opcode sequence. The larger three byte opcode sequence is 10895used on the 486 (and when no architecture is specified) because it 10896executes faster on the 486. Note that you can explicitly request the 10897two byte opcode by writing `sarl %eax'. Secondly, if you specify 10898`i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte 10899offset conditional jumps will be promoted when necessary to a two 10900instruction sequence consisting of a conditional jump of the opposite 10901sense around an unconditional jump to the target. 10902 10903 Following the CPU architecture (but not a sub-architecture, which 10904are those starting with a dot), you may specify `jumps' or `nojumps' to 10905control automatic promotion of conditional jumps. `jumps' is the 10906default, and enables jump promotion; All external jumps will be of the 10907long variety, and file-local jumps will be promoted as necessary. 10908(*note i386-Jumps::) `nojumps' leaves external conditional jumps as 10909byte offset jumps, and warns about file-local conditional jumps that 10910`as' promotes. Unconditional jumps are treated as for `jumps'. 10911 10912 For example 10913 10914 .arch i8086,nojumps 10915 10916 10917File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent 10918 109199.15.18 Notes 10920------------- 10921 10922There is some trickery concerning the `mul' and `imul' instructions 10923that deserves mention. The 16-, 32-, 64- and 128-bit expanding 10924multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul') 10925can be output only in the one operand form. Thus, `imul %ebx, %eax' 10926does _not_ select the expanding multiply; the expanding multiply would 10927clobber the `%edx' register, and this would confuse `gcc' output. Use 10928`imul %ebx' to get the 64-bit product in `%edx:%eax'. 10929 10930 We have added a two operand form of `imul' when the first operand is 10931an immediate mode expression and the second operand is a register. 10932This is just a shorthand, so that, multiplying `%eax' by 69, for 10933example, can be done with `imul $69, %eax' rather than `imul $69, %eax, 10934%eax'. 10935 10936 10937File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies 10938 109399.16 Intel i860 Dependent Features 10940================================== 10941 10942* Menu: 10943 10944* Notes-i860:: i860 Notes 10945* Options-i860:: i860 Command-line Options 10946* Directives-i860:: i860 Machine Directives 10947* Opcodes for i860:: i860 Opcodes 10948* Syntax of i860:: i860 Syntax 10949 10950 10951File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent 10952 109539.16.1 i860 Notes 10954----------------- 10955 10956This is a fairly complete i860 assembler which is compatible with the 10957UNIX System V/860 Release 4 assembler. However, it does not currently 10958support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT'). 10959 10960 Like the SVR4/860 assembler, the output object format is ELF32. 10961Currently, this is the only supported object format. If there is 10962sufficient interest, other formats such as COFF may be implemented. 10963 10964 Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter 10965being the default. One difference is that AT&T syntax requires the '%' 10966prefix on register names while Intel syntax does not. Another 10967difference is in the specification of relocatable expressions. The 10968Intel syntax is `ha%expression' whereas the SVR4 syntax is 10969`[expression]@ha' (and similarly for the "l" and "h" selectors). 10970 10971 10972File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent 10973 109749.16.2 i860 Command-line Options 10975-------------------------------- 10976 109779.16.2.1 SVR4 compatibility options 10978................................... 10979 10980`-V' 10981 Print assembler version. 10982 10983`-Qy' 10984 Ignored. 10985 10986`-Qn' 10987 Ignored. 10988 109899.16.2.2 Other options 10990...................... 10991 10992`-EL' 10993 Select little endian output (this is the default). 10994 10995`-EB' 10996 Select big endian output. Note that the i860 always reads 10997 instructions as little endian data, so this option only effects 10998 data and not instructions. 10999 11000`-mwarn-expand' 11001 Emit a warning message if any pseudo-instruction expansions 11002 occurred. For example, a `or' instruction with an immediate 11003 larger than 16-bits will be expanded into two instructions. This 11004 is a very undesirable feature to rely on, so this flag can help 11005 detect any code where it happens. One use of it, for instance, has 11006 been to find and eliminate any place where `gcc' may emit these 11007 pseudo-instructions. 11008 11009`-mxp' 11010 Enable support for the i860XP instructions and control registers. 11011 By default, this option is disabled so that only the base 11012 instruction set (i.e., i860XR) is supported. 11013 11014`-mintel-syntax' 11015 The i860 assembler defaults to AT&T/SVR4 syntax. This option 11016 enables the Intel syntax. 11017 11018 11019File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i860, Up: i860-Dependent 11020 110219.16.3 i860 Machine Directives 11022------------------------------ 11023 11024`.dual' 11025 Enter dual instruction mode. While this directive is supported, the 11026 preferred way to use dual instruction mode is to explicitly code 11027 the dual bit with the `d.' prefix. 11028 11029`.enddual' 11030 Exit dual instruction mode. While this directive is supported, the 11031 preferred way to use dual instruction mode is to explicitly code 11032 the dual bit with the `d.' prefix. 11033 11034`.atmp' 11035 Change the temporary register used when expanding pseudo 11036 operations. The default register is `r31'. 11037 11038 The `.dual', `.enddual', and `.atmp' directives are available only 11039in the Intel syntax mode. 11040 11041 Both syntaxes allow for the standard `.align' directive. However, 11042the Intel syntax additionally allows keywords for the alignment 11043parameter: "`.align type'", where `type' is one of `.short', `.long', 11044`.quad', `.single', `.double' representing alignments of 2, 4, 16, 4, 11045and 8, respectively. 11046 11047 11048File: as.info, Node: Opcodes for i860, Next: Syntax of i860, Prev: Directives-i860, Up: i860-Dependent 11049 110509.16.4 i860 Opcodes 11051------------------- 11052 11053All of the Intel i860XR and i860XP machine instructions are supported. 11054Please see either _i860 Microprocessor Programmer's Reference Manual_ 11055or _i860 Microprocessor Architecture_ for more information. 11056 110579.16.4.1 Other instruction support (pseudo-instructions) 11058........................................................ 11059 11060For compatibility with some other i860 assemblers, a number of 11061pseudo-instructions are supported. While these are supported, they are 11062a very undesirable feature that should be avoided - in particular, when 11063they result in an expansion to multiple actual i860 instructions. Below 11064are the pseudo-instructions that result in expansions. 11065 * Load large immediate into general register: 11066 11067 The pseudo-instruction `mov imm,%rn' (where the immediate does not 11068 fit within a signed 16-bit field) will be expanded into: 11069 orh large_imm@h,%r0,%rn 11070 or large_imm@l,%rn,%rn 11071 11072 * Load/store with relocatable address expression: 11073 11074 For example, the pseudo-instruction `ld.b addr_exp(%rx),%rn' will 11075 be expanded into: 11076 orh addr_exp@ha,%rx,%r31 11077 ld.l addr_exp@l(%r31),%rn 11078 11079 The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x, 11080 fst.x', and `pst.x' as well. 11081 11082 * Signed large immediate with add/subtract: 11083 11084 If any of the arithmetic operations `adds, addu, subs, subu' are 11085 used with an immediate larger than 16-bits (signed), then they 11086 will be expanded. For instance, the pseudo-instruction `adds 11087 large_imm,%rx,%rn' expands to: 11088 orh large_imm@h,%r0,%r31 11089 or large_imm@l,%r31,%r31 11090 adds %r31,%rx,%rn 11091 11092 * Unsigned large immediate with logical operations: 11093 11094 Logical operations (`or, andnot, or, xor') also result in 11095 expansions. The pseudo-instruction `or large_imm,%rx,%rn' results 11096 in: 11097 orh large_imm@h,%rx,%r31 11098 or large_imm@l,%r31,%rn 11099 11100 Similarly for the others, except for `and' which expands to: 11101 andnot (-1 - large_imm)@h,%rx,%r31 11102 andnot (-1 - large_imm)@l,%r31,%rn 11103 11104 11105File: as.info, Node: Syntax of i860, Prev: Opcodes for i860, Up: i860-Dependent 11106 111079.16.5 i860 Syntax 11108------------------ 11109 11110* Menu: 11111 11112* i860-Chars:: Special Characters 11113 11114 11115File: as.info, Node: i860-Chars, Up: Syntax of i860 11116 111179.16.5.1 Special Characters 11118........................... 11119 11120The presence of a `#' appearing anywhere on a line indicates the start 11121of a comment that extends to the end of that line. 11122 11123 If a `#' appears as the first character of a line then the whole 11124line is treated as a comment, but in this case the line can also be a 11125logical line number directive (*note Comments::) or a preprocessor 11126control command (*note Preprocessing::). 11127 11128 The `;' character can be used to separate statements on the same 11129line. 11130 11131 11132File: as.info, Node: i960-Dependent, Next: IA-64-Dependent, Prev: i860-Dependent, Up: Machine Dependencies 11133 111349.17 Intel 80960 Dependent Features 11135=================================== 11136 11137* Menu: 11138 11139* Options-i960:: i960 Command-line Options 11140* Floating Point-i960:: Floating Point 11141* Directives-i960:: i960 Machine Directives 11142* Opcodes for i960:: i960 Opcodes 11143* Syntax of i960:: i960 Syntax 11144 11145 11146File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent 11147 111489.17.1 i960 Command-line Options 11149-------------------------------- 11150 11151`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' 11152 Select the 80960 architecture. Instructions or features not 11153 supported by the selected architecture cause fatal errors. 11154 11155 `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'. 11156 Synonyms are provided for compatibility with other tools. 11157 11158 If you do not specify any of these options, `as' generates code 11159 for any instruction or feature that is supported by _some_ version 11160 of the 960 (even if this means mixing architectures!). In 11161 principle, `as' attempts to deduce the minimal sufficient 11162 processor type if none is specified; depending on the object code 11163 format, the processor type may be recorded in the object file. If 11164 it is critical that the `as' output match a specific architecture, 11165 specify that architecture explicitly. 11166 11167`-b' 11168 Add code to collect information about conditional branches taken, 11169 for later optimization using branch prediction bits. (The 11170 conditional branch instructions have branch prediction bits in the 11171 CA, CB, and CC architectures.) If BR represents a conditional 11172 branch instruction, the following represents the code generated by 11173 the assembler when `-b' is specified: 11174 11175 call INCREMENT ROUTINE 11176 .word 0 # pre-counter 11177 Label: BR 11178 call INCREMENT ROUTINE 11179 .word 0 # post-counter 11180 11181 The counter following a branch records the number of times that 11182 branch was _not_ taken; the difference between the two counters is 11183 the number of times the branch _was_ taken. 11184 11185 A table of every such `Label' is also generated, so that the 11186 external postprocessor `gbr960' (supplied by Intel) can locate all 11187 the counters. This table is always labeled `__BRANCH_TABLE__'; 11188 this is a local symbol to permit collecting statistics for many 11189 separate object files. The table is word aligned, and begins with 11190 a two-word header. The first word, initialized to 0, is used in 11191 maintaining linked lists of branch tables. The second word is a 11192 count of the number of entries in the table, which follow 11193 immediately: each is a word, pointing to one of the labels 11194 illustrated above. 11195 11196 +------------+------------+------------+ ... +------------+ 11197 | | | | | | 11198 | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N | 11199 | | | | | | 11200 +------------+------------+------------+ ... +------------+ 11201 11202 __BRANCH_TABLE__ layout 11203 11204 The first word of the header is used to locate multiple branch 11205 tables, since each object file may contain one. Normally the links 11206 are maintained with a call to an initialization routine, placed at 11207 the beginning of each function in the file. The GNU C compiler 11208 generates these calls automatically when you give it a `-b' option. 11209 For further details, see the documentation of `gbr960'. 11210 11211`-no-relax' 11212 Normally, Compare-and-Branch instructions with targets that require 11213 displacements greater than 13 bits (or that have external targets) 11214 are replaced with the corresponding compare (or `chkbit') and 11215 branch instructions. You can use the `-no-relax' option to 11216 specify that `as' should generate errors instead, if the target 11217 displacement is larger than 13 bits. 11218 11219 This option does not affect the Compare-and-Jump instructions; the 11220 code emitted for them is _always_ adjusted when necessary 11221 (depending on displacement size), regardless of whether you use 11222 `-no-relax'. 11223 11224 11225File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent 11226 112279.17.2 Floating Point 11228--------------------- 11229 11230`as' generates IEEE floating-point numbers for the directives `.float', 11231`.double', `.extended', and `.single'. 11232 11233 11234File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent 11235 112369.17.3 i960 Machine Directives 11237------------------------------ 11238 11239`.bss SYMBOL, LENGTH, ALIGN' 11240 Reserve LENGTH bytes in the bss section for a local SYMBOL, 11241 aligned to the power of two specified by ALIGN. LENGTH and ALIGN 11242 must be positive absolute expressions. This directive differs 11243 from `.lcomm' only in that it permits you to specify an alignment. 11244 *Note `.lcomm': Lcomm. 11245 11246`.extended FLONUMS' 11247 `.extended' expects zero or more flonums, separated by commas; for 11248 each flonum, `.extended' emits an IEEE extended-format (80-bit) 11249 floating-point number. 11250 11251`.leafproc CALL-LAB, BAL-LAB' 11252 You can use the `.leafproc' directive in conjunction with the 11253 optimized `callj' instruction to enable faster calls of leaf 11254 procedures. If a procedure is known to call no other procedures, 11255 you may define an entry point that skips procedure prolog code 11256 (and that does not depend on system-supplied saved context), and 11257 declare it as the BAL-LAB using `.leafproc'. If the procedure 11258 also has an entry point that goes through the normal prolog, you 11259 can specify that entry point as CALL-LAB. 11260 11261 A `.leafproc' declaration is meant for use in conjunction with the 11262 optimized call instruction `callj'; the directive records the data 11263 needed later to choose between converting the `callj' into a `bal' 11264 or a `call'. 11265 11266 CALL-LAB is optional; if only one argument is present, or if the 11267 two arguments are identical, the single argument is assumed to be 11268 the `bal' entry point. 11269 11270`.sysproc NAME, INDEX' 11271 The `.sysproc' directive defines a name for a system procedure. 11272 After you define it using `.sysproc', you can use NAME to refer to 11273 the system procedure identified by INDEX when calling procedures 11274 with the optimized call instruction `callj'. 11275 11276 Both arguments are required; INDEX must be between 0 and 31 11277 (inclusive). 11278 11279 11280File: as.info, Node: Opcodes for i960, Next: Syntax of i960, Prev: Directives-i960, Up: i960-Dependent 11281 112829.17.4 i960 Opcodes 11283------------------- 11284 11285All Intel 960 machine instructions are supported; *note i960 11286Command-line Options: Options-i960. for a discussion of selecting the 11287instruction subset for a particular 960 architecture. 11288 11289 Some opcodes are processed beyond simply emitting a single 11290corresponding instruction: `callj', and Compare-and-Branch or 11291Compare-and-Jump instructions with target displacements larger than 13 11292bits. 11293 11294* Menu: 11295 11296* callj-i960:: `callj' 11297* Compare-and-branch-i960:: Compare-and-Branch 11298 11299 11300File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960 11301 113029.17.4.1 `callj' 11303................ 11304 11305You can write `callj' to have the assembler or the linker determine the 11306most appropriate form of subroutine call: `call', `bal', or `calls'. 11307If the assembly source contains enough information--a `.leafproc' or 11308`.sysproc' directive defining the operand--then `as' translates the 11309`callj'; if not, it simply emits the `callj', leaving it for the linker 11310to resolve. 11311 11312 11313File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960 11314 113159.17.4.2 Compare-and-Branch 11316........................... 11317 11318The 960 architectures provide combined Compare-and-Branch instructions 11319that permit you to store the branch target in the lower 13 bits of the 11320instruction word itself. However, if you specify a branch target far 11321enough away that its address won't fit in 13 bits, the assembler can 11322either issue an error, or convert your Compare-and-Branch instruction 11323into separate instructions to do the compare and the branch. 11324 11325 Whether `as' gives an error or expands the instruction depends on 11326two choices you can make: whether you use the `-no-relax' option, and 11327whether you use a "Compare and Branch" instruction or a "Compare and 11328Jump" instruction. The "Jump" instructions are _always_ expanded if 11329necessary; the "Branch" instructions are expanded when necessary 11330_unless_ you specify `-no-relax'--in which case `as' gives an error 11331instead. 11332 11333 These are the Compare-and-Branch instructions, their "Jump" variants, 11334and the instruction pairs they may expand into: 11335 11336 Compare and 11337 Branch Jump Expanded to 11338 ------ ------ ------------ 11339 bbc chkbit; bno 11340 bbs chkbit; bo 11341 cmpibe cmpije cmpi; be 11342 cmpibg cmpijg cmpi; bg 11343 cmpibge cmpijge cmpi; bge 11344 cmpibl cmpijl cmpi; bl 11345 cmpible cmpijle cmpi; ble 11346 cmpibno cmpijno cmpi; bno 11347 cmpibne cmpijne cmpi; bne 11348 cmpibo cmpijo cmpi; bo 11349 cmpobe cmpoje cmpo; be 11350 cmpobg cmpojg cmpo; bg 11351 cmpobge cmpojge cmpo; bge 11352 cmpobl cmpojl cmpo; bl 11353 cmpoble cmpojle cmpo; ble 11354 cmpobne cmpojne cmpo; bne 11355 11356 11357File: as.info, Node: Syntax of i960, Prev: Opcodes for i960, Up: i960-Dependent 11358 113599.17.5 Syntax for the i960 11360-------------------------- 11361 11362* Menu: 11363 11364* i960-Chars:: Special Characters 11365 11366 11367File: as.info, Node: i960-Chars, Up: Syntax of i960 11368 113699.17.5.1 Special Characters 11370........................... 11371 11372The presence of a `#' on a line indicates the start of a comment that 11373extends to the end of the current line. 11374 11375 If a `#' appears as the first character of a line, the whole line is 11376treated as a comment, but in this case the line can also be a logical 11377line number directive (*note Comments::) or a preprocessor control 11378command (*note Preprocessing::). 11379 11380 The `;' character can be used to separate statements on the same 11381line. 11382 11383 11384File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies 11385 113869.18 IA-64 Dependent Features 11387============================= 11388 11389* Menu: 11390 11391* IA-64 Options:: Options 11392* IA-64 Syntax:: Syntax 11393* IA-64 Opcodes:: Opcodes 11394 11395 11396File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent 11397 113989.18.1 Options 11399-------------- 11400 11401`-mconstant-gp' 11402 This option instructs the assembler to mark the resulting object 11403 file as using the "constant GP" model. With this model, it is 11404 assumed that the entire program uses a single global pointer (GP) 11405 value. Note that this option does not in any fashion affect the 11406 machine code emitted by the assembler. All it does is turn on the 11407 EF_IA_64_CONS_GP flag in the ELF file header. 11408 11409`-mauto-pic' 11410 This option instructs the assembler to mark the resulting object 11411 file as using the "constant GP without function descriptor" data 11412 model. This model is like the "constant GP" model, except that it 11413 additionally does away with function descriptors. What this means 11414 is that the address of a function refers directly to the 11415 function's code entry-point. Normally, such an address would 11416 refer to a function descriptor, which contains both the code 11417 entry-point and the GP-value needed by the function. Note that 11418 this option does not in any fashion affect the machine code 11419 emitted by the assembler. All it does is turn on the 11420 EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. 11421 11422`-milp32' 11423`-milp64' 11424`-mlp64' 11425`-mp64' 11426 These options select the data model. The assembler defaults to 11427 `-mlp64' (LP64 data model). 11428 11429`-mle' 11430`-mbe' 11431 These options select the byte order. The `-mle' option selects 11432 little-endian byte order (default) and `-mbe' selects big-endian 11433 byte order. Note that IA-64 machine code always uses 11434 little-endian byte order. 11435 11436`-mtune=itanium1' 11437`-mtune=itanium2' 11438 Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default 11439 is ITANIUM2. 11440 11441`-munwind-check=warning' 11442`-munwind-check=error' 11443 These options control what the assembler will do when performing 11444 consistency checks on unwind directives. `-munwind-check=warning' 11445 will make the assembler issue a warning when an unwind directive 11446 check fails. This is the default. `-munwind-check=error' will 11447 make the assembler issue an error when an unwind directive check 11448 fails. 11449 11450`-mhint.b=ok' 11451`-mhint.b=warning' 11452`-mhint.b=error' 11453 These options control what the assembler will do when the `hint.b' 11454 instruction is used. `-mhint.b=ok' will make the assembler accept 11455 `hint.b'. `-mint.b=warning' will make the assembler issue a 11456 warning when `hint.b' is used. `-mhint.b=error' will make the 11457 assembler treat `hint.b' as an error, which is the default. 11458 11459`-x' 11460`-xexplicit' 11461 These options turn on dependency violation checking. 11462 11463`-xauto' 11464 This option instructs the assembler to automatically insert stop 11465 bits where necessary to remove dependency violations. This is the 11466 default mode. 11467 11468`-xnone' 11469 This option turns off dependency violation checking. 11470 11471`-xdebug' 11472 This turns on debug output intended to help tracking down bugs in 11473 the dependency violation checker. 11474 11475`-xdebugn' 11476 This is a shortcut for -xnone -xdebug. 11477 11478`-xdebugx' 11479 This is a shortcut for -xexplicit -xdebug. 11480 11481 11482 11483File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent 11484 114859.18.2 Syntax 11486------------- 11487 11488The assembler syntax closely follows the IA-64 Assembly Language 11489Reference Guide. 11490 11491* Menu: 11492 11493* IA-64-Chars:: Special Characters 11494* IA-64-Regs:: Register Names 11495* IA-64-Bits:: Bit Names 11496* IA-64-Relocs:: Relocations 11497 11498 11499File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax 11500 115019.18.2.1 Special Characters 11502........................... 11503 11504`//' is the line comment token. 11505 11506 `;' can be used instead of a newline to separate statements. 11507 11508 11509File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax 11510 115119.18.2.2 Register Names 11512....................... 11513 11514The 128 integer registers are referred to as `rN'. The 128 11515floating-point registers are referred to as `fN'. The 128 application 11516registers are referred to as `arN'. The 128 control registers are 11517referred to as `crN'. The 64 one-bit predicate registers are referred 11518to as `pN'. The 8 branch registers are referred to as `bN'. In 11519addition, the assembler defines a number of aliases: `gp' (`r1'), `sp' 11520(`r12'), `rp' (`b0'), `ret0' (`r8'), `ret1' (`r9'), `ret2' (`r10'), 11521`ret3' (`r9'), `fargN' (`f8+N'), and `fretN' (`f8+N'). 11522 11523 For convenience, the assembler also defines aliases for all named 11524application and control registers. For example, `ar.bsp' refers to the 11525register backing store pointer (`ar17'). Similarly, `cr.eoi' refers to 11526the end-of-interrupt register (`cr67'). 11527 11528 11529File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax 11530 115319.18.2.3 IA-64 Processor-Status-Register (PSR) Bit Names 11532........................................................ 11533 11534The assembler defines bit masks for each of the bits in the IA-64 11535processor status register. For example, `psr.ic' corresponds to a 11536value of 0x2000. These masks are primarily intended for use with the 11537`ssm'/`sum' and `rsm'/`rum' instructions, but they can be used anywhere 11538else where an integer constant is expected. 11539 11540 11541File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax 11542 115439.18.2.4 Relocations 11544.................... 11545 11546In addition to the standard IA-64 relocations, the following 11547relocations are implemented by `as': 11548 11549`@slotcount(V)' 11550 Convert the address offset V into a slot count. This pseudo 11551 function is available only on VMS. The expression V must be known 11552 at assembly time: it can't reference undefined symbols or symbols 11553 in different sections. 11554 11555 11556File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent 11557 115589.18.3 Opcodes 11559-------------- 11560 11561For detailed information on the IA-64 machine instruction set, see the 11562IA-64 Architecture Handbook 11563(http://developer.intel.com/design/itanium/arch_spec.htm). 11564 11565 11566File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies 11567 115689.19 IP2K Dependent Features 11569============================ 11570 11571* Menu: 11572 11573* IP2K-Opts:: IP2K Options 11574* IP2K-Syntax:: IP2K Syntax 11575 11576 11577File: as.info, Node: IP2K-Opts, Next: IP2K-Syntax, Up: IP2K-Dependent 11578 115799.19.1 IP2K Options 11580------------------- 11581 11582The Ubicom IP2K version of `as' has a few machine dependent options: 11583 11584`-mip2022ext' 11585 `as' can assemble the extended IP2022 instructions, but it will 11586 only do so if this is specifically allowed via this command line 11587 option. 11588 11589`-mip2022' 11590 This option restores the assembler's default behaviour of not 11591 permitting the extended IP2022 instructions to be assembled. 11592 11593 11594 11595File: as.info, Node: IP2K-Syntax, Prev: IP2K-Opts, Up: IP2K-Dependent 11596 115979.19.2 IP2K Syntax 11598------------------ 11599 11600* Menu: 11601 11602* IP2K-Chars:: Special Characters 11603 11604 11605File: as.info, Node: IP2K-Chars, Up: IP2K-Syntax 11606 116079.19.2.1 Special Characters 11608........................... 11609 11610The presence of a `;' on a line indicates the start of a comment that 11611extends to the end of the current line. 11612 11613 If a `#' appears as the first character of a line, the whole line is 11614treated as a comment, but in this case the line can also be a logical 11615line number directive (*note Comments::) or a preprocessor control 11616command (*note Preprocessing::). 11617 11618 The IP2K assembler does not currently support a line separator 11619character. 11620 11621 11622File: as.info, Node: LM32-Dependent, Next: M32C-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies 11623 116249.20 LM32 Dependent Features 11625============================ 11626 11627* Menu: 11628 11629* LM32 Options:: Options 11630* LM32 Syntax:: Syntax 11631* LM32 Opcodes:: Opcodes 11632 11633 11634File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent 11635 116369.20.1 Options 11637-------------- 11638 11639`-mmultiply-enabled' 11640 Enable multiply instructions. 11641 11642`-mdivide-enabled' 11643 Enable divide instructions. 11644 11645`-mbarrel-shift-enabled' 11646 Enable barrel-shift instructions. 11647 11648`-msign-extend-enabled' 11649 Enable sign extend instructions. 11650 11651`-muser-enabled' 11652 Enable user defined instructions. 11653 11654`-micache-enabled' 11655 Enable instruction cache related CSRs. 11656 11657`-mdcache-enabled' 11658 Enable data cache related CSRs. 11659 11660`-mbreak-enabled' 11661 Enable break instructions. 11662 11663`-mall-enabled' 11664 Enable all instructions and CSRs. 11665 11666 11667 11668File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent 11669 116709.20.2 Syntax 11671------------- 11672 11673* Menu: 11674 11675* LM32-Regs:: Register Names 11676* LM32-Modifiers:: Relocatable Expression Modifiers 11677* LM32-Chars:: Special Characters 11678 11679 11680File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax 11681 116829.20.2.1 Register Names 11683....................... 11684 11685LM32 has 32 x 32-bit general purpose registers `r0', `r1', ... `r31'. 11686 11687 The following aliases are defined: `gp' - `r26', `fp' - `r27', `sp' 11688- `r28', `ra' - `r29', `ea' - `r30', `ba' - `r31'. 11689 11690 LM32 has the following Control and Status Registers (CSRs). 11691 11692`IE' 11693 Interrupt enable. 11694 11695`IM' 11696 Interrupt mask. 11697 11698`IP' 11699 Interrupt pending. 11700 11701`ICC' 11702 Instruction cache control. 11703 11704`DCC' 11705 Data cache control. 11706 11707`CC' 11708 Cycle counter. 11709 11710`CFG' 11711 Configuration. 11712 11713`EBA' 11714 Exception base address. 11715 11716`DC' 11717 Debug control. 11718 11719`DEBA' 11720 Debug exception base address. 11721 11722`JTX' 11723 JTAG transmit. 11724 11725`JRX' 11726 JTAG receive. 11727 11728`BP0' 11729 Breakpoint 0. 11730 11731`BP1' 11732 Breakpoint 1. 11733 11734`BP2' 11735 Breakpoint 2. 11736 11737`BP3' 11738 Breakpoint 3. 11739 11740`WP0' 11741 Watchpoint 0. 11742 11743`WP1' 11744 Watchpoint 1. 11745 11746`WP2' 11747 Watchpoint 2. 11748 11749`WP3' 11750 Watchpoint 3. 11751 11752 11753File: as.info, Node: LM32-Modifiers, Next: LM32-Chars, Prev: LM32-Regs, Up: LM32 Syntax 11754 117559.20.2.2 Relocatable Expression Modifiers 11756......................................... 11757 11758The assembler supports several modifiers when using relocatable 11759addresses in LM32 instruction operands. The general syntax is the 11760following: 11761 11762 modifier(relocatable-expression) 11763 11764`lo' 11765 This modifier allows you to use bits 0 through 15 of an address 11766 expression as 16 bit relocatable expression. 11767 11768`hi' 11769 This modifier allows you to use bits 16 through 23 of an address 11770 expression as 16 bit relocatable expression. 11771 11772 For example 11773 11774 ori r4, r4, lo(sym+10) 11775 orhi r4, r4, hi(sym+10) 11776 11777`gp' 11778 This modified creates a 16-bit relocatable expression that is the 11779 offset of the symbol from the global pointer. 11780 11781 mva r4, gp(sym) 11782 11783`got' 11784 This modifier places a symbol in the GOT and creates a 16-bit 11785 relocatable expression that is the offset into the GOT of this 11786 symbol. 11787 11788 lw r4, (gp+got(sym)) 11789 11790`gotofflo16' 11791 This modifier allows you to use the bits 0 through 15 of an 11792 address which is an offset from the GOT. 11793 11794`gotoffhi16' 11795 This modifier allows you to use the bits 16 through 31 of an 11796 address which is an offset from the GOT. 11797 11798 orhi r4, r4, gotoffhi16(lsym) 11799 addi r4, r4, gotofflo16(lsym) 11800 11801 11802 11803File: as.info, Node: LM32-Chars, Prev: LM32-Modifiers, Up: LM32 Syntax 11804 118059.20.2.3 Special Characters 11806........................... 11807 11808The presence of a `#' on a line indicates the start of a comment that 11809extends to the end of the current line. Note that if a line starts 11810with a `#' character then it can also be a logical line number 11811directive (*note Comments::) or a preprocessor control command (*note 11812Preprocessing::). 11813 11814 A semicolon (`;') can be used to separate multiple statements on the 11815same line. 11816 11817 11818File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent 11819 118209.20.3 Opcodes 11821-------------- 11822 11823For detailed information on the LM32 machine instruction set, see 11824`http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/'. 11825 11826 `as' implements all the standard LM32 opcodes. 11827 11828 11829File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies 11830 118319.21 M32C Dependent Features 11832============================ 11833 11834 `as' can assemble code for several different members of the Renesas 11835M32C family. Normally the default is to assemble code for the M16C 11836microprocessor. The `-m32c' option may be used to change the default 11837to the M32C microprocessor. 11838 11839* Menu: 11840 11841* M32C-Opts:: M32C Options 11842* M32C-Syntax:: M32C Syntax 11843 11844 11845File: as.info, Node: M32C-Opts, Next: M32C-Syntax, Up: M32C-Dependent 11846 118479.21.1 M32C Options 11848------------------- 11849 11850The Renesas M32C version of `as' has these machine-dependent options: 11851 11852`-m32c' 11853 Assemble M32C instructions. 11854 11855`-m16c' 11856 Assemble M16C instructions (default). 11857 11858`-relax' 11859 Enable support for link-time relaxations. 11860 11861`-h-tick-hex' 11862 Support H'00 style hex constants in addition to 0x00 style. 11863 11864 11865 11866File: as.info, Node: M32C-Syntax, Prev: M32C-Opts, Up: M32C-Dependent 11867 118689.21.2 M32C Syntax 11869------------------ 11870 11871* Menu: 11872 11873* M32C-Modifiers:: Symbolic Operand Modifiers 11874* M32C-Chars:: Special Characters 11875 11876 11877File: as.info, Node: M32C-Modifiers, Next: M32C-Chars, Up: M32C-Syntax 11878 118799.21.2.1 Symbolic Operand Modifiers 11880................................... 11881 11882The assembler supports several modifiers when using symbol addresses in 11883M32C instruction operands. The general syntax is the following: 11884 11885 %modifier(symbol) 11886 11887`%dsp8' 11888`%dsp16' 11889 These modifiers override the assembler's assumptions about how big 11890 a symbol's address is. Normally, when it sees an operand like 11891 `sym[a0]' it assumes `sym' may require the widest displacement 11892 field (16 bits for `-m16c', 24 bits for `-m32c'). These modifiers 11893 tell it to assume the address will fit in an 8 or 16 bit 11894 (respectively) unsigned displacement. Note that, of course, if it 11895 doesn't actually fit you will get linker errors. Example: 11896 11897 mov.w %dsp8(sym)[a0],r1 11898 mov.b #0,%dsp8(sym)[a0] 11899 11900`%hi8' 11901 This modifier allows you to load bits 16 through 23 of a 24 bit 11902 address into an 8 bit register. This is useful with, for example, 11903 the M16C `smovf' instruction, which expects a 20 bit address in 11904 `r1h' and `a0'. Example: 11905 11906 mov.b #%hi8(sym),r1h 11907 mov.w #%lo16(sym),a0 11908 smovf.b 11909 11910`%lo16' 11911 Likewise, this modifier allows you to load bits 0 through 15 of a 11912 24 bit address into a 16 bit register. 11913 11914`%hi16' 11915 This modifier allows you to load bits 16 through 31 of a 32 bit 11916 address into a 16 bit register. While the M32C family only has 24 11917 bits of address space, it does support addresses in pairs of 16 bit 11918 registers (like `a1a0' for the `lde' instruction). This modifier 11919 is for loading the upper half in such cases. Example: 11920 11921 mov.w #%hi16(sym),a1 11922 mov.w #%lo16(sym),a0 11923 ... 11924 lde.w [a1a0],r1 11925 11926 11927 11928File: as.info, Node: M32C-Chars, Prev: M32C-Modifiers, Up: M32C-Syntax 11929 119309.21.2.2 Special Characters 11931........................... 11932 11933The presence of a `;' character on a line indicates the start of a 11934comment that extends to the end of that line. 11935 11936 If a `#' appears as the first character of a line, the whole line is 11937treated as a comment, but in this case the line can also be a logical 11938line number directive (*note Comments::) or a preprocessor control 11939command (*note Preprocessing::). 11940 11941 The `|' character can be used to separate statements on the same 11942line. 11943 11944 11945File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies 11946 119479.22 M32R Dependent Features 11948============================ 11949 11950* Menu: 11951 11952* M32R-Opts:: M32R Options 11953* M32R-Directives:: M32R Directives 11954* M32R-Warnings:: M32R Warnings 11955 11956 11957File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent 11958 119599.22.1 M32R Options 11960------------------- 11961 11962The Renease M32R version of `as' has a few machine dependent options: 11963 11964`-m32rx' 11965 `as' can assemble code for several different members of the 11966 Renesas M32R family. Normally the default is to assemble code for 11967 the M32R microprocessor. This option may be used to change the 11968 default to the M32RX microprocessor, which adds some more 11969 instructions to the basic M32R instruction set, and some 11970 additional parameters to some of the original instructions. 11971 11972`-m32r2' 11973 This option changes the target processor to the M32R2 11974 microprocessor. 11975 11976`-m32r' 11977 This option can be used to restore the assembler's default 11978 behaviour of assembling for the M32R microprocessor. This can be 11979 useful if the default has been changed by a previous command line 11980 option. 11981 11982`-little' 11983 This option tells the assembler to produce little-endian code and 11984 data. The default is dependent upon how the toolchain was 11985 configured. 11986 11987`-EL' 11988 This is a synonym for _-little_. 11989 11990`-big' 11991 This option tells the assembler to produce big-endian code and 11992 data. 11993 11994`-EB' 11995 This is a synonum for _-big_. 11996 11997`-KPIC' 11998 This option specifies that the output of the assembler should be 11999 marked as position-independent code (PIC). 12000 12001`-parallel' 12002 This option tells the assembler to attempts to combine two 12003 sequential instructions into a single, parallel instruction, where 12004 it is legal to do so. 12005 12006`-no-parallel' 12007 This option disables a previously enabled _-parallel_ option. 12008 12009`-no-bitinst' 12010 This option disables the support for the extended bit-field 12011 instructions provided by the M32R2. If this support needs to be 12012 re-enabled the _-bitinst_ switch can be used to restore it. 12013 12014`-O' 12015 This option tells the assembler to attempt to optimize the 12016 instructions that it produces. This includes filling delay slots 12017 and converting sequential instructions into parallel ones. This 12018 option implies _-parallel_. 12019 12020`-warn-explicit-parallel-conflicts' 12021 Instructs `as' to produce warning messages when questionable 12022 parallel instructions are encountered. This option is enabled by 12023 default, but `gcc' disables it when it invokes `as' directly. 12024 Questionable instructions are those whose behaviour would be 12025 different if they were executed sequentially. For example the 12026 code fragment `mv r1, r2 || mv r3, r1' produces a different result 12027 from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 12028 and then r2 into r1, whereas the later moves r2 into r1 and r3. 12029 12030`-Wp' 12031 This is a shorter synonym for the 12032 _-warn-explicit-parallel-conflicts_ option. 12033 12034`-no-warn-explicit-parallel-conflicts' 12035 Instructs `as' not to produce warning messages when questionable 12036 parallel instructions are encountered. 12037 12038`-Wnp' 12039 This is a shorter synonym for the 12040 _-no-warn-explicit-parallel-conflicts_ option. 12041 12042`-ignore-parallel-conflicts' 12043 This option tells the assembler's to stop checking parallel 12044 instructions for constraint violations. This ability is provided 12045 for hardware vendors testing chip designs and should not be used 12046 under normal circumstances. 12047 12048`-no-ignore-parallel-conflicts' 12049 This option restores the assembler's default behaviour of checking 12050 parallel instructions to detect constraint violations. 12051 12052`-Ip' 12053 This is a shorter synonym for the _-ignore-parallel-conflicts_ 12054 option. 12055 12056`-nIp' 12057 This is a shorter synonym for the _-no-ignore-parallel-conflicts_ 12058 option. 12059 12060`-warn-unmatched-high' 12061 This option tells the assembler to produce a warning message if a 12062 `.high' pseudo op is encountered without a matching `.low' pseudo 12063 op. The presence of such an unmatched pseudo op usually indicates 12064 a programming error. 12065 12066`-no-warn-unmatched-high' 12067 Disables a previously enabled _-warn-unmatched-high_ option. 12068 12069`-Wuh' 12070 This is a shorter synonym for the _-warn-unmatched-high_ option. 12071 12072`-Wnuh' 12073 This is a shorter synonym for the _-no-warn-unmatched-high_ option. 12074 12075 12076 12077File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent 12078 120799.22.2 M32R Directives 12080---------------------- 12081 12082The Renease M32R version of `as' has a few architecture specific 12083directives: 12084 12085`low EXPRESSION' 12086 The `low' directive computes the value of its expression and 12087 places the lower 16-bits of the result into the immediate-field of 12088 the instruction. For example: 12089 12090 or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 12091 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred 12092 12093`high EXPRESSION' 12094 The `high' directive computes the value of its expression and 12095 places the upper 16-bits of the result into the immediate-field of 12096 the instruction. For example: 12097 12098 seth r0, #high(0x12345678) ; compute r0 = 0x12340000 12099 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred 12100 12101`shigh EXPRESSION' 12102 The `shigh' directive is very similar to the `high' directive. It 12103 also computes the value of its expression and places the upper 12104 16-bits of the result into the immediate-field of the instruction. 12105 The difference is that `shigh' also checks to see if the lower 12106 16-bits could be interpreted as a signed number, and if so it 12107 assumes that a borrow will occur from the upper-16 bits. To 12108 compensate for this the `shigh' directive pre-biases the upper 16 12109 bit value by adding one to it. For example: 12110 12111 For example: 12112 12113 seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 12114 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 12115 12116 In the second example the lower 16-bits are 0x8000. If these are 12117 treated as a signed value and sign extended to 32-bits then the 12118 value becomes 0xffff8000. If this value is then added to 12119 0x00010000 then the result is 0x00008000. 12120 12121 This behaviour is to allow for the different semantics of the 12122 `or3' and `add3' instructions. The `or3' instruction treats its 12123 16-bit immediate argument as unsigned whereas the `add3' treats 12124 its 16-bit immediate as a signed value. So for example: 12125 12126 seth r0, #shigh(0x00008000) 12127 add3 r0, r0, #low(0x00008000) 12128 12129 Produces the correct result in r0, whereas: 12130 12131 seth r0, #shigh(0x00008000) 12132 or3 r0, r0, #low(0x00008000) 12133 12134 Stores 0xffff8000 into r0. 12135 12136 Note - the `shigh' directive does not know where in the assembly 12137 source code the lower 16-bits of the value are going set, so it 12138 cannot check to make sure that an `or3' instruction is being used 12139 rather than an `add3' instruction. It is up to the programmer to 12140 make sure that correct directives are used. 12141 12142`.m32r' 12143 The directive performs a similar thing as the _-m32r_ command line 12144 option. It tells the assembler to only accept M32R instructions 12145 from now on. An instructions from later M32R architectures are 12146 refused. 12147 12148`.m32rx' 12149 The directive performs a similar thing as the _-m32rx_ command 12150 line option. It tells the assembler to start accepting the extra 12151 instructions in the M32RX ISA as well as the ordinary M32R ISA. 12152 12153`.m32r2' 12154 The directive performs a similar thing as the _-m32r2_ command 12155 line option. It tells the assembler to start accepting the extra 12156 instructions in the M32R2 ISA as well as the ordinary M32R ISA. 12157 12158`.little' 12159 The directive performs a similar thing as the _-little_ command 12160 line option. It tells the assembler to start producing 12161 little-endian code and data. This option should be used with care 12162 as producing mixed-endian binary files is fraught with danger. 12163 12164`.big' 12165 The directive performs a similar thing as the _-big_ command line 12166 option. It tells the assembler to start producing big-endian code 12167 and data. This option should be used with care as producing 12168 mixed-endian binary files is fraught with danger. 12169 12170 12171 12172File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent 12173 121749.22.3 M32R Warnings 12175-------------------- 12176 12177There are several warning and error messages that can be produced by 12178`as' which are specific to the M32R: 12179 12180`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?' 12181 This message is only produced if warnings for explicit parallel 12182 conflicts have been enabled. It indicates that the assembler has 12183 encountered a parallel instruction in which the destination 12184 register of the left hand instruction is used as an input register 12185 in the right hand instruction. For example in this code fragment 12186 `mv r1, r2 || neg r3, r1' register r1 is the destination of the 12187 move instruction and the input to the neg instruction. 12188 12189`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?' 12190 This message is only produced if warnings for explicit parallel 12191 conflicts have been enabled. It indicates that the assembler has 12192 encountered a parallel instruction in which the destination 12193 register of the right hand instruction is used as an input 12194 register in the left hand instruction. For example in this code 12195 fragment `mv r1, r2 || neg r2, r3' register r2 is the destination 12196 of the neg instruction and the input to the move instruction. 12197 12198`instruction `...' is for the M32RX only' 12199 This message is produced when the assembler encounters an 12200 instruction which is only supported by the M32Rx processor, and 12201 the `-m32rx' command line flag has not been specified to allow 12202 assembly of such instructions. 12203 12204`unknown instruction `...'' 12205 This message is produced when the assembler encounters an 12206 instruction which it does not recognize. 12207 12208`only the NOP instruction can be issued in parallel on the m32r' 12209 This message is produced when the assembler encounters a parallel 12210 instruction which does not involve a NOP instruction and the 12211 `-m32rx' command line flag has not been specified. Only the M32Rx 12212 processor is able to execute two instructions in parallel. 12213 12214`instruction `...' cannot be executed in parallel.' 12215 This message is produced when the assembler encounters a parallel 12216 instruction which is made up of one or two instructions which 12217 cannot be executed in parallel. 12218 12219`Instructions share the same execution pipeline' 12220 This message is produced when the assembler encounters a parallel 12221 instruction whoes components both use the same execution pipeline. 12222 12223`Instructions write to the same destination register.' 12224 This message is produced when the assembler encounters a parallel 12225 instruction where both components attempt to modify the same 12226 register. For example these code fragments will produce this 12227 message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2, 12228 @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx 12229 r3, r4' (Both write to the condition bit) 12230 12231 12232 12233File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies 12234 122359.23 M680x0 Dependent Features 12236============================== 12237 12238* Menu: 12239 12240* M68K-Opts:: M680x0 Options 12241* M68K-Syntax:: Syntax 12242* M68K-Moto-Syntax:: Motorola Syntax 12243* M68K-Float:: Floating Point 12244* M68K-Directives:: 680x0 Machine Directives 12245* M68K-opcodes:: Opcodes 12246 12247 12248File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent 12249 122509.23.1 M680x0 Options 12251--------------------- 12252 12253The Motorola 680x0 version of `as' has a few machine dependent options: 12254 12255`-march=ARCHITECTURE' 12256 This option specifies a target architecture. The following 12257 architectures are recognized: `68000', `68010', `68020', `68030', 12258 `68040', `68060', `cpu32', `isaa', `isaaplus', `isab', `isac' and 12259 `cfv4e'. 12260 12261`-mcpu=CPU' 12262 This option specifies a target cpu. When used in conjunction with 12263 the `-march' option, the cpu must be within the specified 12264 architecture. Also, the generic features of the architecture are 12265 used for instruction generation, rather than those of the specific 12266 chip. 12267 12268`-m[no-]68851' 12269`-m[no-]68881' 12270`-m[no-]div' 12271`-m[no-]usp' 12272`-m[no-]float' 12273`-m[no-]mac' 12274`-m[no-]emac' 12275 Enable or disable various architecture specific features. If a 12276 chip or architecture by default supports an option (for instance 12277 `-march=isaaplus' includes the `-mdiv' option), explicitly 12278 disabling the option will override the default. 12279 12280`-l' 12281 You can use the `-l' option to shorten the size of references to 12282 undefined symbols. If you do not use the `-l' option, references 12283 to undefined symbols are wide enough for a full `long' (32 bits). 12284 (Since `as' cannot know where these symbols end up, `as' can only 12285 allocate space for the linker to fill in later. Since `as' does 12286 not know how far away these symbols are, it allocates as much 12287 space as it can.) If you use this option, the references are only 12288 one word wide (16 bits). This may be useful if you want the 12289 object file to be as small as possible, and you know that the 12290 relevant symbols are always less than 17 bits away. 12291 12292`--register-prefix-optional' 12293 For some configurations, especially those where the compiler 12294 normally does not prepend an underscore to the names of user 12295 variables, the assembler requires a `%' before any use of a 12296 register name. This is intended to let the assembler distinguish 12297 between C variables and functions named `a0' through `a7', and so 12298 on. The `%' is always accepted, but is not required for certain 12299 configurations, notably `sun3'. The `--register-prefix-optional' 12300 option may be used to permit omitting the `%' even for 12301 configurations for which it is normally required. If this is 12302 done, it will generally be impossible to refer to C variables and 12303 functions with the same names as register names. 12304 12305`--bitwise-or' 12306 Normally the character `|' is treated as a comment character, which 12307 means that it can not be used in expressions. The `--bitwise-or' 12308 option turns `|' into a normal character. In this mode, you must 12309 either use C style comments, or start comments with a `#' character 12310 at the beginning of a line. 12311 12312`--base-size-default-16 --base-size-default-32' 12313 If you use an addressing mode with a base register without 12314 specifying the size, `as' will normally use the full 32 bit value. 12315 For example, the addressing mode `%a0@(%d0)' is equivalent to 12316 `%a0@(%d0:l)'. You may use the `--base-size-default-16' option to 12317 tell `as' to default to using the 16 bit value. In this case, 12318 `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'. You may use the 12319 `--base-size-default-32' option to restore the default behaviour. 12320 12321`--disp-size-default-16 --disp-size-default-32' 12322 If you use an addressing mode with a displacement, and the value 12323 of the displacement is not known, `as' will normally assume that 12324 the value is 32 bits. For example, if the symbol `disp' has not 12325 been defined, `as' will assemble the addressing mode 12326 `%a0@(disp,%d0)' as though `disp' is a 32 bit value. You may use 12327 the `--disp-size-default-16' option to tell `as' to instead assume 12328 that the displacement is 16 bits. In this case, `as' will 12329 assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value. You 12330 may use the `--disp-size-default-32' option to restore the default 12331 behaviour. 12332 12333`--pcrel' 12334 Always keep branches PC-relative. In the M680x0 architecture all 12335 branches are defined as PC-relative. However, on some processors 12336 they are limited to word displacements maximum. When `as' needs a 12337 long branch that is not available, it normally emits an absolute 12338 jump instead. This option disables this substitution. When this 12339 option is given and no long branches are available, only word 12340 branches will be emitted. An error message will be generated if a 12341 word branch cannot reach its target. This option has no effect on 12342 68020 and other processors that have long branches. *note Branch 12343 Improvement: M68K-Branch. 12344 12345`-m68000' 12346 `as' can assemble code for several different members of the 12347 Motorola 680x0 family. The default depends upon how `as' was 12348 configured when it was built; normally, the default is to assemble 12349 code for the 68020 microprocessor. The following options may be 12350 used to change the default. These options control which 12351 instructions and addressing modes are permitted. The members of 12352 the 680x0 family are very similar. For detailed information about 12353 the differences, see the Motorola manuals. 12354 12355 `-m68000' 12356 `-m68ec000' 12357 `-m68hc000' 12358 `-m68hc001' 12359 `-m68008' 12360 `-m68302' 12361 `-m68306' 12362 `-m68307' 12363 `-m68322' 12364 `-m68356' 12365 Assemble for the 68000. `-m68008', `-m68302', and so on are 12366 synonyms for `-m68000', since the chips are the same from the 12367 point of view of the assembler. 12368 12369 `-m68010' 12370 Assemble for the 68010. 12371 12372 `-m68020' 12373 `-m68ec020' 12374 Assemble for the 68020. This is normally the default. 12375 12376 `-m68030' 12377 `-m68ec030' 12378 Assemble for the 68030. 12379 12380 `-m68040' 12381 `-m68ec040' 12382 Assemble for the 68040. 12383 12384 `-m68060' 12385 `-m68ec060' 12386 Assemble for the 68060. 12387 12388 `-mcpu32' 12389 `-m68330' 12390 `-m68331' 12391 `-m68332' 12392 `-m68333' 12393 `-m68334' 12394 `-m68336' 12395 `-m68340' 12396 `-m68341' 12397 `-m68349' 12398 `-m68360' 12399 Assemble for the CPU32 family of chips. 12400 12401 `-m5200' 12402 `-m5202' 12403 `-m5204' 12404 `-m5206' 12405 `-m5206e' 12406 `-m521x' 12407 `-m5249' 12408 `-m528x' 12409 `-m5307' 12410 `-m5407' 12411 `-m547x' 12412 `-m548x' 12413 `-mcfv4' 12414 `-mcfv4e' 12415 Assemble for the ColdFire family of chips. 12416 12417 `-m68881' 12418 `-m68882' 12419 Assemble 68881 floating point instructions. This is the 12420 default for the 68020, 68030, and the CPU32. The 68040 and 12421 68060 always support floating point instructions. 12422 12423 `-mno-68881' 12424 Do not assemble 68881 floating point instructions. This is 12425 the default for 68000 and the 68010. The 68040 and 68060 12426 always support floating point instructions, even if this 12427 option is used. 12428 12429 `-m68851' 12430 Assemble 68851 MMU instructions. This is the default for the 12431 68020, 68030, and 68060. The 68040 accepts a somewhat 12432 different set of MMU instructions; `-m68851' and `-m68040' 12433 should not be used together. 12434 12435 `-mno-68851' 12436 Do not assemble 68851 MMU instructions. This is the default 12437 for the 68000, 68010, and the CPU32. The 68040 accepts a 12438 somewhat different set of MMU instructions. 12439 12440 12441File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent 12442 124439.23.2 Syntax 12444------------- 12445 12446This syntax for the Motorola 680x0 was developed at MIT. 12447 12448 The 680x0 version of `as' uses instructions names and syntax 12449compatible with the Sun assembler. Intervening periods are ignored; 12450for example, `movl' is equivalent to `mov.l'. 12451 12452 In the following table APC stands for any of the address registers 12453(`%a0' through `%a7'), the program counter (`%pc'), the zero-address 12454relative to the program counter (`%zpc'), a suppressed address register 12455(`%za0' through `%za7'), or it may be omitted entirely. The use of 12456SIZE means one of `w' or `l', and it may be omitted, along with the 12457leading colon, unless a scale is also specified. The use of SCALE 12458means one of `1', `2', `4', or `8', and it may always be omitted along 12459with the leading colon. 12460 12461 The following addressing modes are understood: 12462"Immediate" 12463 `#NUMBER' 12464 12465"Data Register" 12466 `%d0' through `%d7' 12467 12468"Address Register" 12469 `%a0' through `%a7' 12470 `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is 12471 also known as `%fp', the Frame Pointer. 12472 12473"Address Register Indirect" 12474 `%a0@' through `%a7@' 12475 12476"Address Register Postincrement" 12477 `%a0@+' through `%a7@+' 12478 12479"Address Register Predecrement" 12480 `%a0@-' through `%a7@-' 12481 12482"Indirect Plus Offset" 12483 `APC@(NUMBER)' 12484 12485"Index" 12486 `APC@(NUMBER,REGISTER:SIZE:SCALE)' 12487 12488 The NUMBER may be omitted. 12489 12490"Postindex" 12491 `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)' 12492 12493 The ONUMBER or the REGISTER, but not both, may be omitted. 12494 12495"Preindex" 12496 `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)' 12497 12498 The NUMBER may be omitted. Omitting the REGISTER produces the 12499 Postindex addressing mode. 12500 12501"Absolute" 12502 `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'. 12503 12504 12505File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent 12506 125079.23.3 Motorola Syntax 12508---------------------- 12509 12510The standard Motorola syntax for this chip differs from the syntax 12511already discussed (*note Syntax: M68K-Syntax.). `as' can accept 12512Motorola syntax for operands, even if MIT syntax is used for other 12513operands in the same instruction. The two kinds of syntax are fully 12514compatible. 12515 12516 In the following table APC stands for any of the address registers 12517(`%a0' through `%a7'), the program counter (`%pc'), the zero-address 12518relative to the program counter (`%zpc'), or a suppressed address 12519register (`%za0' through `%za7'). The use of SIZE means one of `w' or 12520`l', and it may always be omitted along with the leading dot. The use 12521of SCALE means one of `1', `2', `4', or `8', and it may always be 12522omitted along with the leading asterisk. 12523 12524 The following additional addressing modes are understood: 12525 12526"Address Register Indirect" 12527 `(%a0)' through `(%a7)' 12528 `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is 12529 also known as `%fp', the Frame Pointer. 12530 12531"Address Register Postincrement" 12532 `(%a0)+' through `(%a7)+' 12533 12534"Address Register Predecrement" 12535 `-(%a0)' through `-(%a7)' 12536 12537"Indirect Plus Offset" 12538 `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'. 12539 12540 The NUMBER may also appear within the parentheses, as in 12541 `(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted 12542 (with an address register, omitting the NUMBER produces Address 12543 Register Indirect mode). 12544 12545"Index" 12546 `NUMBER(APC,REGISTER.SIZE*SCALE)' 12547 12548 The NUMBER may be omitted, or it may appear within the 12549 parentheses. The APC may be omitted. The REGISTER and the APC 12550 may appear in either order. If both APC and REGISTER are address 12551 registers, and the SIZE and SCALE are omitted, then the first 12552 register is taken as the base register, and the second as the 12553 index register. 12554 12555"Postindex" 12556 `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)' 12557 12558 The ONUMBER, or the REGISTER, or both, may be omitted. Either the 12559 NUMBER or the APC may be omitted, but not both. 12560 12561"Preindex" 12562 `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)' 12563 12564 The NUMBER, or the APC, or the REGISTER, or any two of them, may 12565 be omitted. The ONUMBER may be omitted. The REGISTER and the APC 12566 may appear in either order. If both APC and REGISTER are address 12567 registers, and the SIZE and SCALE are omitted, then the first 12568 register is taken as the base register, and the second as the 12569 index register. 12570 12571 12572File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent 12573 125749.23.4 Floating Point 12575--------------------- 12576 12577Packed decimal (P) format floating literals are not supported. Feel 12578free to add the code! 12579 12580 The floating point formats generated by directives are these. 12581 12582`.float' 12583 `Single' precision floating point constants. 12584 12585`.double' 12586 `Double' precision floating point constants. 12587 12588`.extend' 12589`.ldouble' 12590 `Extended' precision (`long double') floating point constants. 12591 12592 12593File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent 12594 125959.23.5 680x0 Machine Directives 12596------------------------------- 12597 12598In order to be compatible with the Sun assembler the 680x0 assembler 12599understands the following directives. 12600 12601`.data1' 12602 This directive is identical to a `.data 1' directive. 12603 12604`.data2' 12605 This directive is identical to a `.data 2' directive. 12606 12607`.even' 12608 This directive is a special case of the `.align' directive; it 12609 aligns the output to an even byte boundary. 12610 12611`.skip' 12612 This directive is identical to a `.space' directive. 12613 12614`.arch NAME' 12615 Select the target architecture and extension features. Valid 12616 values for NAME are the same as for the `-march' command line 12617 option. This directive cannot be specified after any instructions 12618 have been assembled. If it is given multiple times, or in 12619 conjunction with the `-march' option, all uses must be for the 12620 same architecture and extension set. 12621 12622`.cpu NAME' 12623 Select the target cpu. Valid valuse for NAME are the same as for 12624 the `-mcpu' command line option. This directive cannot be 12625 specified after any instructions have been assembled. If it is 12626 given multiple times, or in conjunction with the `-mopt' option, 12627 all uses must be for the same cpu. 12628 12629 12630 12631File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent 12632 126339.23.6 Opcodes 12634-------------- 12635 12636* Menu: 12637 12638* M68K-Branch:: Branch Improvement 12639* M68K-Chars:: Special Characters 12640 12641 12642File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes 12643 126449.23.6.1 Branch Improvement 12645........................... 12646 12647Certain pseudo opcodes are permitted for branch instructions. They 12648expand to the shortest branch instruction that reach the target. 12649Generally these mnemonics are made by substituting `j' for `b' at the 12650start of a Motorola mnemonic. 12651 12652 The following table summarizes the pseudo-operations. A `*' flags 12653cases that are more fully described after the table: 12654 12655 Displacement 12656 +------------------------------------------------------------ 12657 | 68020 68000/10, not PC-relative OK 12658 Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** 12659 +------------------------------------------------------------ 12660 jbsr |bsrs bsrw bsrl jsr 12661 jra |bras braw bral jmp 12662 * jXX |bXXs bXXw bXXl bNXs;jmp 12663 * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp 12664 fjXX | N/A fbXXw fbXXl N/A 12665 12666 XX: condition 12667 NX: negative of condition XX 12668 `*'--see full description below 12669 `**'--this expansion mode is disallowed by `--pcrel' 12670 12671`jbsr' 12672`jra' 12673 These are the simplest jump pseudo-operations; they always map to 12674 one particular machine instruction, depending on the displacement 12675 to the branch target. This instruction will be a byte or word 12676 branch is that is sufficient. Otherwise, a long branch will be 12677 emitted if available. If no long branches are available and the 12678 `--pcrel' option is not given, an absolute long jump will be 12679 emitted instead. If no long branches are available, the `--pcrel' 12680 option is given, and a word branch cannot reach the target, an 12681 error message is generated. 12682 12683 In addition to standard branch operands, `as' allows these 12684 pseudo-operations to have all operands that are allowed for jsr 12685 and jmp, substituting these instructions if the operand given is 12686 not valid for a branch instruction. 12687 12688`jXX' 12689 Here, `jXX' stands for an entire family of pseudo-operations, 12690 where XX is a conditional branch or condition-code test. The full 12691 list of pseudo-ops in this family is: 12692 jhi jls jcc jcs jne jeq jvc 12693 jvs jpl jmi jge jlt jgt jle 12694 12695 Usually, each of these pseudo-operations expands to a single branch 12696 instruction. However, if a word branch is not sufficient, no long 12697 branches are available, and the `--pcrel' option is not given, `as' 12698 issues a longer code fragment in terms of NX, the opposite 12699 condition to XX. For example, under these conditions: 12700 jXX foo 12701 gives 12702 bNXs oof 12703 jmp foo 12704 oof: 12705 12706`dbXX' 12707 The full family of pseudo-operations covered here is 12708 dbhi dbls dbcc dbcs dbne dbeq dbvc 12709 dbvs dbpl dbmi dbge dblt dbgt dble 12710 dbf dbra dbt 12711 12712 Motorola `dbXX' instructions allow word displacements only. When 12713 a word displacement is sufficient, each of these pseudo-operations 12714 expands to the corresponding Motorola instruction. When a word 12715 displacement is not sufficient and long branches are available, 12716 when the source reads `dbXX foo', `as' emits 12717 dbXX oo1 12718 bras oo2 12719 oo1:bral foo 12720 oo2: 12721 12722 If, however, long branches are not available and the `--pcrel' 12723 option is not given, `as' emits 12724 dbXX oo1 12725 bras oo2 12726 oo1:jmp foo 12727 oo2: 12728 12729`fjXX' 12730 This family includes 12731 fjne fjeq fjge fjlt fjgt fjle fjf 12732 fjt fjgl fjgle fjnge fjngl fjngle fjngt 12733 fjnle fjnlt fjoge fjogl fjogt fjole fjolt 12734 fjor fjseq fjsf fjsne fjst fjueq fjuge 12735 fjugt fjule fjult fjun 12736 12737 Each of these pseudo-operations always expands to a single Motorola 12738 coprocessor branch instruction, word or long. All Motorola 12739 coprocessor branch instructions allow both word and long 12740 displacements. 12741 12742 12743 12744File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes 12745 127469.23.6.2 Special Characters 12747........................... 12748 12749Line comments are introduced by the `|' character appearing anywhere on 12750a line, unless the `--bitwise-or' command line option has been 12751specified. 12752 12753 An asterisk (`*') as the first character on a line marks the start 12754of a line comment as well. 12755 12756 A hash character (`#') as the first character on a line also marks 12757the start of a line comment, but in this case it could also be a 12758logical line number directive (*note Comments::) or a preprocessor 12759control command (*note Preprocessing::). If the hash character appears 12760elsewhere on a line it is used to introduce an immediate value. (This 12761is for compatibility with Sun's assembler). 12762 12763 Multiple statements on the same line can appear if they are separated 12764by the `;' character. 12765 12766 12767File: as.info, Node: M68HC11-Dependent, Next: Meta-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies 12768 127699.24 M68HC11 and M68HC12 Dependent Features 12770=========================================== 12771 12772* Menu: 12773 12774* M68HC11-Opts:: M68HC11 and M68HC12 Options 12775* M68HC11-Syntax:: Syntax 12776* M68HC11-Modifiers:: Symbolic Operand Modifiers 12777* M68HC11-Directives:: Assembler Directives 12778* M68HC11-Float:: Floating Point 12779* M68HC11-opcodes:: Opcodes 12780 12781 12782File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent 12783 127849.24.1 M68HC11 and M68HC12 Options 12785---------------------------------- 12786 12787The Motorola 68HC11 and 68HC12 version of `as' have a few machine 12788dependent options. 12789 12790`-m68hc11' 12791 This option switches the assembler into the M68HC11 mode. In this 12792 mode, the assembler only accepts 68HC11 operands and mnemonics. It 12793 produces code for the 68HC11. 12794 12795`-m68hc12' 12796 This option switches the assembler into the M68HC12 mode. In this 12797 mode, the assembler also accepts 68HC12 operands and mnemonics. It 12798 produces code for the 68HC12. A few 68HC11 instructions are 12799 replaced by some 68HC12 instructions as recommended by Motorola 12800 specifications. 12801 12802`-m68hcs12' 12803 This option switches the assembler into the M68HCS12 mode. This 12804 mode is similar to `-m68hc12' but specifies to assemble for the 12805 68HCS12 series. The only difference is on the assembling of the 12806 `movb' and `movw' instruction when a PC-relative operand is used. 12807 12808`-mm9s12x' 12809 This option switches the assembler into the M9S12X mode. This 12810 mode is similar to `-m68hc12' but specifies to assemble for the 12811 S12X series which is a superset of the HCS12. 12812 12813`-mm9s12xg' 12814 This option switches the assembler into the XGATE mode for the RISC 12815 co-processor featured on some S12X-family chips. 12816 12817`--xgate-ramoffset' 12818 This option instructs the linker to offset RAM addresses from S12X 12819 address space into XGATE address space. 12820 12821`-mshort' 12822 This option controls the ABI and indicates to use a 16-bit integer 12823 ABI. It has no effect on the assembled instructions. This is the 12824 default. 12825 12826`-mlong' 12827 This option controls the ABI and indicates to use a 32-bit integer 12828 ABI. 12829 12830`-mshort-double' 12831 This option controls the ABI and indicates to use a 32-bit float 12832 ABI. This is the default. 12833 12834`-mlong-double' 12835 This option controls the ABI and indicates to use a 64-bit float 12836 ABI. 12837 12838`--strict-direct-mode' 12839 You can use the `--strict-direct-mode' option to disable the 12840 automatic translation of direct page mode addressing into extended 12841 mode when the instruction does not support direct mode. For 12842 example, the `clr' instruction does not support direct page mode 12843 addressing. When it is used with the direct page mode, `as' will 12844 ignore it and generate an absolute addressing. This option 12845 prevents `as' from doing this, and the wrong usage of the direct 12846 page mode will raise an error. 12847 12848`--short-branches' 12849 The `--short-branches' option turns off the translation of 12850 relative branches into absolute branches when the branch offset is 12851 out of range. By default `as' transforms the relative branch 12852 (`bsr', `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc', 12853 `bls', `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch 12854 when the offset is out of the -128 .. 127 range. In that case, 12855 the `bsr' instruction is translated into a `jsr', the `bra' 12856 instruction is translated into a `jmp' and the conditional 12857 branches instructions are inverted and followed by a `jmp'. This 12858 option disables these translations and `as' will generate an error 12859 if a relative branch is out of range. This option does not affect 12860 the optimization associated to the `jbra', `jbsr' and `jbXX' 12861 pseudo opcodes. 12862 12863`--force-long-branches' 12864 The `--force-long-branches' option forces the translation of 12865 relative branches into absolute branches. This option does not 12866 affect the optimization associated to the `jbra', `jbsr' and 12867 `jbXX' pseudo opcodes. 12868 12869`--print-insn-syntax' 12870 You can use the `--print-insn-syntax' option to obtain the syntax 12871 description of the instruction when an error is detected. 12872 12873`--print-opcodes' 12874 The `--print-opcodes' option prints the list of all the 12875 instructions with their syntax. The first item of each line 12876 represents the instruction name and the rest of the line indicates 12877 the possible operands for that instruction. The list is printed in 12878 alphabetical order. Once the list is printed `as' exits. 12879 12880`--generate-example' 12881 The `--generate-example' option is similar to `--print-opcodes' 12882 but it generates an example for each instruction instead. 12883 12884 12885File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent 12886 128879.24.2 Syntax 12888------------- 12889 12890In the M68HC11 syntax, the instruction name comes first and it may be 12891followed by one or several operands (up to three). Operands are 12892separated by comma (`,'). In the normal mode, `as' will complain if too 12893many operands are specified for a given instruction. In the MRI mode 12894(turned on with `-M' option), it will treat them as comments. Example: 12895 12896 inx 12897 lda #23 12898 bset 2,x #4 12899 brclr *bot #8 foo 12900 12901 The presence of a `;' character or a `!' character anywhere on a 12902line indicates the start of a comment that extends to the end of that 12903line. 12904 12905 A `*' or a `#' character at the start of a line also introduces a 12906line comment, but these characters do not work elsewhere on the line. 12907If the first character of the line is a `#' then as well as starting a 12908comment, the line could also be logical line number directive (*note 12909Comments::) or a preprocessor control command (*note Preprocessing::). 12910 12911 The M68HC11 assembler does not currently support a line separator 12912character. 12913 12914 The following addressing modes are understood for 68HC11 and 68HC12: 12915"Immediate" 12916 `#NUMBER' 12917 12918"Address Register" 12919 `NUMBER,X', `NUMBER,Y' 12920 12921 The NUMBER may be omitted in which case 0 is assumed. 12922 12923"Direct Addressing mode" 12924 `*SYMBOL', or `*DIGITS' 12925 12926"Absolute" 12927 `SYMBOL', or `DIGITS' 12928 12929 The M68HC12 has other more complex addressing modes. All of them are 12930supported and they are represented below: 12931 12932"Constant Offset Indexed Addressing Mode" 12933 `NUMBER,REG' 12934 12935 The NUMBER may be omitted in which case 0 is assumed. The 12936 register can be either `X', `Y', `SP' or `PC'. The assembler will 12937 use the smaller post-byte definition according to the constant 12938 value (5-bit constant offset, 9-bit constant offset or 16-bit 12939 constant offset). If the constant is not known by the assembler 12940 it will use the 16-bit constant offset post-byte and the value 12941 will be resolved at link time. 12942 12943"Offset Indexed Indirect" 12944 `[NUMBER,REG]' 12945 12946 The register can be either `X', `Y', `SP' or `PC'. 12947 12948"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" 12949 `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+' 12950 12951 The number must be in the range `-8'..`+8' and must not be 0. The 12952 register can be either `X', `Y', `SP' or `PC'. 12953 12954"Accumulator Offset" 12955 `ACC,REG' 12956 12957 The accumulator register can be either `A', `B' or `D'. The 12958 register can be either `X', `Y', `SP' or `PC'. 12959 12960"Accumulator D offset indexed-indirect" 12961 `[D,REG]' 12962 12963 The register can be either `X', `Y', `SP' or `PC'. 12964 12965 12966 For example: 12967 12968 ldab 1024,sp 12969 ldd [10,x] 12970 orab 3,+x 12971 stab -2,y- 12972 ldx a,pc 12973 sty [d,sp] 12974 12975 12976File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent 12977 129789.24.3 Symbolic Operand Modifiers 12979--------------------------------- 12980 12981The assembler supports several modifiers when using symbol addresses in 1298268HC11 and 68HC12 instruction operands. The general syntax is the 12983following: 12984 12985 %modifier(symbol) 12986 12987`%addr' 12988 This modifier indicates to the assembler and linker to use the 12989 16-bit physical address corresponding to the symbol. This is 12990 intended to be used on memory window systems to map a symbol in 12991 the memory bank window. If the symbol is in a memory expansion 12992 part, the physical address corresponds to the symbol address 12993 within the memory bank window. If the symbol is not in a memory 12994 expansion part, this is the symbol address (using or not using the 12995 %addr modifier has no effect in that case). 12996 12997`%page' 12998 This modifier indicates to use the memory page number corresponding 12999 to the symbol. If the symbol is in a memory expansion part, its 13000 page number is computed by the linker as a number used to map the 13001 page containing the symbol in the memory bank window. If the 13002 symbol is not in a memory expansion part, the page number is 0. 13003 13004`%hi' 13005 This modifier indicates to use the 8-bit high part of the physical 13006 address of the symbol. 13007 13008`%lo' 13009 This modifier indicates to use the 8-bit low part of the physical 13010 address of the symbol. 13011 13012 13013 For example a 68HC12 call to a function `foo_example' stored in 13014memory expansion part could be written as follows: 13015 13016 call %addr(foo_example),%page(foo_example) 13017 13018 and this is equivalent to 13019 13020 call foo_example 13021 13022 And for 68HC11 it could be written as follows: 13023 13024 ldab #%page(foo_example) 13025 stab _page_switch 13026 jsr %addr(foo_example) 13027 13028 13029File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent 13030 130319.24.4 Assembler Directives 13032--------------------------- 13033 13034The 68HC11 and 68HC12 version of `as' have the following specific 13035assembler directives: 13036 13037`.relax' 13038 The relax directive is used by the `GNU Compiler' to emit a 13039 specific relocation to mark a group of instructions for linker 13040 relaxation. The sequence of instructions within the group must be 13041 known to the linker so that relaxation can be performed. 13042 13043`.mode [mshort|mlong|mshort-double|mlong-double]' 13044 This directive specifies the ABI. It overrides the `-mshort', 13045 `-mlong', `-mshort-double' and `-mlong-double' options. 13046 13047`.far SYMBOL' 13048 This directive marks the symbol as a `far' symbol meaning that it 13049 uses a `call/rtc' calling convention as opposed to `jsr/rts'. 13050 During a final link, the linker will identify references to the 13051 `far' symbol and will verify the proper calling convention. 13052 13053`.interrupt SYMBOL' 13054 This directive marks the symbol as an interrupt entry point. This 13055 information is then used by the debugger to correctly unwind the 13056 frame across interrupts. 13057 13058`.xrefb SYMBOL' 13059 This directive is defined for compatibility with the 13060 `Specification for Motorola 8 and 16-Bit Assembly Language Input 13061 Standard' and is ignored. 13062 13063 13064 13065File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent 13066 130679.24.5 Floating Point 13068--------------------- 13069 13070Packed decimal (P) format floating literals are not supported. Feel 13071free to add the code! 13072 13073 The floating point formats generated by directives are these. 13074 13075`.float' 13076 `Single' precision floating point constants. 13077 13078`.double' 13079 `Double' precision floating point constants. 13080 13081`.extend' 13082`.ldouble' 13083 `Extended' precision (`long double') floating point constants. 13084 13085 13086File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent 13087 130889.24.6 Opcodes 13089-------------- 13090 13091* Menu: 13092 13093* M68HC11-Branch:: Branch Improvement 13094 13095 13096File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes 13097 130989.24.6.1 Branch Improvement 13099........................... 13100 13101Certain pseudo opcodes are permitted for branch instructions. They 13102expand to the shortest branch instruction that reach the target. 13103Generally these mnemonics are made by prepending `j' to the start of 13104Motorola mnemonic. These pseudo opcodes are not affected by the 13105`--short-branches' or `--force-long-branches' options. 13106 13107 The following table summarizes the pseudo-operations. 13108 13109 Displacement Width 13110 +-------------------------------------------------------------+ 13111 | Options | 13112 | --short-branches --force-long-branches | 13113 +--------------------------+----------------------------------+ 13114 Op |BYTE WORD | BYTE WORD | 13115 +--------------------------+----------------------------------+ 13116 bsr | bsr <pc-rel> <error> | jsr <abs> | 13117 bra | bra <pc-rel> <error> | jmp <abs> | 13118 jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | 13119 jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | 13120 bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | 13121 jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | 13122 | jmp <abs> | | 13123 +--------------------------+----------------------------------+ 13124 XX: condition 13125 NX: negative of condition XX 13126 13127`jbsr' 13128`jbra' 13129 These are the simplest jump pseudo-operations; they always map to 13130 one particular machine instruction, depending on the displacement 13131 to the branch target. 13132 13133`jbXX' 13134 Here, `jbXX' stands for an entire family of pseudo-operations, 13135 where XX is a conditional branch or condition-code test. The full 13136 list of pseudo-ops in this family is: 13137 jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo 13138 jbcs jbne jblt jble jbls jbvc jbmi 13139 13140 For the cases of non-PC relative displacements and long 13141 displacements, `as' issues a longer code fragment in terms of NX, 13142 the opposite condition to XX. For example, for the non-PC 13143 relative case: 13144 jbXX foo 13145 gives 13146 bNXs oof 13147 jmp foo 13148 oof: 13149 13150 13151 13152File: as.info, Node: Meta-Dependent, Next: MicroBlaze-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies 13153 131549.25 Meta Dependent Features 13155============================ 13156 13157* Menu: 13158 13159* Meta Options:: Options 13160* Meta Syntax:: Meta Assembler Syntax 13161 13162 13163File: as.info, Node: Meta Options, Next: Meta Syntax, Up: Meta-Dependent 13164 131659.25.1 Options 13166-------------- 13167 13168The Imagination Technologies Meta architecture is implemented in a 13169number of versions, with each new version adding new features such as 13170instructions and registers. For precise details of what instructions 13171each core supports, please see the chip's technical reference manual. 13172 13173 The following table lists all available Meta options. 13174 13175`-mcpu=metac11' 13176 Generate code for Meta 1.1. 13177 13178`-mcpu=metac12' 13179 Generate code for Meta 1.2. 13180 13181`-mcpu=metac21' 13182 Generate code for Meta 2.1. 13183 13184`-mfpu=metac21' 13185 Allow code to use FPU hardware of Meta 2.1. 13186 13187 13188 13189File: as.info, Node: Meta Syntax, Prev: Meta Options, Up: Meta-Dependent 13190 131919.25.2 Syntax 13192------------- 13193 13194* Menu: 13195 13196* Meta-Chars:: Special Characters 13197* Meta-Regs:: Register Names 13198 13199 13200File: as.info, Node: Meta-Chars, Next: Meta-Regs, Up: Meta Syntax 13201 132029.25.2.1 Special Characters 13203........................... 13204 13205`!' is the line comment character. 13206 13207 You can use `;' instead of a newline to separate statements. 13208 13209 Since `$' has no special meaning, you may use it in symbol names. 13210 13211 13212File: as.info, Node: Meta-Regs, Prev: Meta-Chars, Up: Meta Syntax 13213 132149.25.2.2 Register Names 13215....................... 13216 13217Registers can be specified either using their mnemonic names, such as 13218`D0Re0', or using the unit plus register number separated by a `.', 13219such as `D0.0'. 13220 13221 13222File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: Meta-Dependent, Up: Machine Dependencies 13223 132249.26 MicroBlaze Dependent Features 13225================================== 13226 13227 The Xilinx MicroBlaze processor family includes several variants, 13228all using the same core instruction set. This chapter covers features 13229of the GNU assembler that are specific to the MicroBlaze architecture. 13230For details about the MicroBlaze instruction set, please see the 13231`MicroBlaze Processor Reference Guide (UG081)' available at 13232www.xilinx.com. 13233 13234* Menu: 13235 13236* MicroBlaze Directives:: Directives for MicroBlaze Processors. 13237* MicroBlaze Syntax:: Syntax for the MicroBlaze 13238 13239 13240File: as.info, Node: MicroBlaze Directives, Next: MicroBlaze Syntax, Up: MicroBlaze-Dependent 13241 132429.26.1 Directives 13243----------------- 13244 13245A number of assembler directives are available for MicroBlaze. 13246 13247`.data8 EXPRESSION,...' 13248 This directive is an alias for `.byte'. Each expression is 13249 assembled into an eight-bit value. 13250 13251`.data16 EXPRESSION,...' 13252 This directive is an alias for `.hword'. Each expression is 13253 assembled into an 16-bit value. 13254 13255`.data32 EXPRESSION,...' 13256 This directive is an alias for `.word'. Each expression is 13257 assembled into an 32-bit value. 13258 13259`.ent NAME[,LABEL]' 13260 This directive is an alias for `.func' denoting the start of 13261 function NAME at (optional) LABEL. 13262 13263`.end NAME[,LABEL]' 13264 This directive is an alias for `.endfunc' denoting the end of 13265 function NAME. 13266 13267`.gpword LABEL,...' 13268 This directive is an alias for `.rva'. The resolved address of 13269 LABEL is stored in the data section. 13270 13271`.weakext LABEL' 13272 Declare that LABEL is a weak external symbol. 13273 13274`.rodata' 13275 Switch to .rodata section. Equivalent to `.section .rodata' 13276 13277`.sdata2' 13278 Switch to .sdata2 section. Equivalent to `.section .sdata2' 13279 13280`.sdata' 13281 Switch to .sdata section. Equivalent to `.section .sdata' 13282 13283`.bss' 13284 Switch to .bss section. Equivalent to `.section .bss' 13285 13286`.sbss' 13287 Switch to .sbss section. Equivalent to `.section .sbss' 13288 13289 13290File: as.info, Node: MicroBlaze Syntax, Prev: MicroBlaze Directives, Up: MicroBlaze-Dependent 13291 132929.26.2 Syntax for the MicroBlaze 13293-------------------------------- 13294 13295* Menu: 13296 13297* MicroBlaze-Chars:: Special Characters 13298 13299 13300File: as.info, Node: MicroBlaze-Chars, Up: MicroBlaze Syntax 13301 133029.26.2.1 Special Characters 13303........................... 13304 13305The presence of a `#' on a line indicates the start of a comment that 13306extends to the end of the current line. 13307 13308 If a `#' appears as the first character of a line, the whole line is 13309treated as a comment, but in this case the line can also be a logical 13310line number directive (*note Comments::) or a preprocessor control 13311command (*note Preprocessing::). 13312 13313 The `;' character can be used to separate statements on the same 13314line. 13315 13316 13317File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies 13318 133199.27 MIPS Dependent Features 13320============================ 13321 13322 GNU `as' for MIPS architectures supports several different MIPS 13323processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For 13324information about the MIPS instruction set, see `MIPS RISC 13325Architecture', by Kane and Heindrich (Prentice-Hall). For an overview 13326of MIPS assembly conventions, see "Appendix D: Assembly Language 13327Programming" in the same work. 13328 13329* Menu: 13330 13331* MIPS Options:: Assembler options 13332* MIPS Macros:: High-level assembly macros 13333* MIPS Symbol Sizes:: Directives to override the size of symbols 13334* MIPS Small Data:: Controlling the use of small data accesses 13335* MIPS ISA:: Directives to override the ISA level 13336* MIPS assembly options:: Directives to control code generation 13337* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 13338* MIPS insn:: Directive to mark data as an instruction 13339* MIPS NaN Encodings:: Directives to record which NaN encoding is being used 13340* MIPS Option Stack:: Directives to save and restore options 13341* MIPS ASE Instruction Generation Overrides:: Directives to control 13342 generation of MIPS ASE instructions 13343* MIPS Floating-Point:: Directives to override floating-point options 13344* MIPS Syntax:: MIPS specific syntactical considerations 13345 13346 13347File: as.info, Node: MIPS Options, Next: MIPS Macros, Up: MIPS-Dependent 13348 133499.27.1 Assembler options 13350------------------------ 13351 13352The MIPS configurations of GNU `as' support these special options: 13353 13354`-G NUM' 13355 Set the "small data" limit to N bytes. The default limit is 8 13356 bytes. *Note Controlling the use of small data accesses: MIPS 13357 Small Data. 13358 13359`-EB' 13360`-EL' 13361 Any MIPS configuration of `as' can select big-endian or 13362 little-endian output at run time (unlike the other GNU development 13363 tools, which must be configured for one or the other). Use `-EB' 13364 to select big-endian output, and `-EL' for little-endian. 13365 13366`-KPIC' 13367 Generate SVR4-style PIC. This option tells the assembler to 13368 generate SVR4-style position-independent macro expansions. It 13369 also tells the assembler to mark the output file as PIC. 13370 13371`-mvxworks-pic' 13372 Generate VxWorks PIC. This option tells the assembler to generate 13373 VxWorks-style position-independent macro expansions. 13374 13375`-mips1' 13376`-mips2' 13377`-mips3' 13378`-mips4' 13379`-mips5' 13380`-mips32' 13381`-mips32r2' 13382`-mips64' 13383`-mips64r2' 13384 Generate code for a particular MIPS Instruction Set Architecture 13385 level. `-mips1' corresponds to the R2000 and R3000 processors, 13386 `-mips2' to the R6000 processor, `-mips3' to the R4000 processor, 13387 and `-mips4' to the R8000 and R10000 processors. `-mips5', 13388 `-mips32', `-mips32r2', `-mips64', and `-mips64r2' correspond to 13389 generic MIPS V, MIPS32, MIPS32 Release 2, MIPS64, and MIPS64 13390 Release 2 ISA processors, respectively. You can also switch 13391 instruction sets during the assembly; see *note Directives to 13392 override the ISA level: MIPS ISA. 13393 13394`-mgp32' 13395`-mfp32' 13396 Some macros have different expansions for 32-bit and 64-bit 13397 registers. The register sizes are normally inferred from the ISA 13398 and ABI, but these flags force a certain group of registers to be 13399 treated as 32 bits wide at all times. `-mgp32' controls the size 13400 of general-purpose registers and `-mfp32' controls the size of 13401 floating-point registers. 13402 13403 The `.set gp=32' and `.set fp=32' directives allow the size of 13404 registers to be changed for parts of an object. The default value 13405 is restored by `.set gp=default' and `.set fp=default'. 13406 13407 On some MIPS variants there is a 32-bit mode flag; when this flag 13408 is set, 64-bit instructions generate a trap. Also, some 32-bit 13409 OSes only save the 32-bit registers on a context switch, so it is 13410 essential never to use the 64-bit registers. 13411 13412`-mgp64' 13413`-mfp64' 13414 Assume that 64-bit registers are available. This is provided in 13415 the interests of symmetry with `-mgp32' and `-mfp32'. 13416 13417 The `.set gp=64' and `.set fp=64' directives allow the size of 13418 registers to be changed for parts of an object. The default value 13419 is restored by `.set gp=default' and `.set fp=default'. 13420 13421`-mips16' 13422`-no-mips16' 13423 Generate code for the MIPS 16 processor. This is equivalent to 13424 putting `.set mips16' at the start of the assembly file. 13425 `-no-mips16' turns off this option. 13426 13427`-mmicromips' 13428`-mno-micromips' 13429 Generate code for the microMIPS processor. This is equivalent to 13430 putting `.set micromips' at the start of the assembly file. 13431 `-mno-micromips' turns off this option. This is equivalent to 13432 putting `.set nomicromips' at the start of the assembly file. 13433 13434`-msmartmips' 13435`-mno-smartmips' 13436 Enables the SmartMIPS extensions to the MIPS32 instruction set, 13437 which provides a number of new instructions which target smartcard 13438 and cryptographic applications. This is equivalent to putting 13439 `.set smartmips' at the start of the assembly file. 13440 `-mno-smartmips' turns off this option. 13441 13442`-mips3d' 13443`-no-mips3d' 13444 Generate code for the MIPS-3D Application Specific Extension. 13445 This tells the assembler to accept MIPS-3D instructions. 13446 `-no-mips3d' turns off this option. 13447 13448`-mdmx' 13449`-no-mdmx' 13450 Generate code for the MDMX Application Specific Extension. This 13451 tells the assembler to accept MDMX instructions. `-no-mdmx' turns 13452 off this option. 13453 13454`-mdsp' 13455`-mno-dsp' 13456 Generate code for the DSP Release 1 Application Specific Extension. 13457 This tells the assembler to accept DSP Release 1 instructions. 13458 `-mno-dsp' turns off this option. 13459 13460`-mdspr2' 13461`-mno-dspr2' 13462 Generate code for the DSP Release 2 Application Specific Extension. 13463 This option implies -mdsp. This tells the assembler to accept DSP 13464 Release 2 instructions. `-mno-dspr2' turns off this option. 13465 13466`-mmt' 13467`-mno-mt' 13468 Generate code for the MT Application Specific Extension. This 13469 tells the assembler to accept MT instructions. `-mno-mt' turns 13470 off this option. 13471 13472`-mmcu' 13473`-mno-mcu' 13474 Generate code for the MCU Application Specific Extension. This 13475 tells the assembler to accept MCU instructions. `-mno-mcu' turns 13476 off this option. 13477 13478`-mvirt' 13479`-mno-virt' 13480 Generate code for the Virtualization Application Specific 13481 Extension. This tells the assembler to accept Virtualization 13482 instructions. `-mno-virt' turns off this option. 13483 13484`-minsn32' 13485`-mno-insn32' 13486 Only use 32-bit instruction encodings when generating code for the 13487 microMIPS processor. This option inhibits the use of any 16-bit 13488 instructions. This is equivalent to putting `.set insn32' at the 13489 start of the assembly file. `-mno-insn32' turns off this option. 13490 This is equivalent to putting `.set noinsn32' at the start of the 13491 assembly file. By default `-mno-insn32' is selected, allowing all 13492 instructions to be used. 13493 13494`-mfix7000' 13495`-mno-fix7000' 13496 Cause nops to be inserted if the read of the destination register 13497 of an mfhi or mflo instruction occurs in the following two 13498 instructions. 13499 13500`-mfix-rm7000' 13501`-mno-fix-rm7000' 13502 Cause nops to be inserted if a dmult or dmultu instruction is 13503 followed by a load instruction. 13504 13505`-mfix-loongson2f-jump' 13506`-mno-fix-loongson2f-jump' 13507 Eliminate instruction fetch from outside 256M region to work 13508 around the Loongson2F `jump' instructions. Without it, under 13509 extreme cases, the kernel may crash. The issue has been solved in 13510 latest processor batches, but this fix has no side effect to them. 13511 13512`-mfix-loongson2f-nop' 13513`-mno-fix-loongson2f-nop' 13514 Replace nops by `or at,at,zero' to work around the Loongson2F 13515 `nop' errata. Without it, under extreme cases, the CPU might 13516 deadlock. The issue has been solved in later Loongson2F batches, 13517 but this fix has no side effect to them. 13518 13519`-mfix-vr4120' 13520`-mno-fix-vr4120' 13521 Insert nops to work around certain VR4120 errata. This option is 13522 intended to be used on GCC-generated code: it is not designed to 13523 catch all problems in hand-written assembler code. 13524 13525`-mfix-vr4130' 13526`-mno-fix-vr4130' 13527 Insert nops to work around the VR4130 `mflo'/`mfhi' errata. 13528 13529`-mfix-24k' 13530`-mno-fix-24k' 13531 Insert nops to work around the 24K `eret'/`deret' errata. 13532 13533`-mfix-cn63xxp1' 13534`-mno-fix-cn63xxp1' 13535 Replace `pref' hints 0 - 4 and 6 - 24 with hint 28 to work around 13536 certain CN63XXP1 errata. 13537 13538`-m4010' 13539`-no-m4010' 13540 Generate code for the LSI R4010 chip. This tells the assembler to 13541 accept the R4010-specific instructions (`addciu', `ffc', etc.), 13542 and to not schedule `nop' instructions around accesses to the `HI' 13543 and `LO' registers. `-no-m4010' turns off this option. 13544 13545`-m4650' 13546`-no-m4650' 13547 Generate code for the MIPS R4650 chip. This tells the assembler 13548 to accept the `mad' and `madu' instruction, and to not schedule 13549 `nop' instructions around accesses to the `HI' and `LO' registers. 13550 `-no-m4650' turns off this option. 13551 13552`-m3900' 13553`-no-m3900' 13554`-m4100' 13555`-no-m4100' 13556 For each option `-mNNNN', generate code for the MIPS RNNNN chip. 13557 This tells the assembler to accept instructions specific to that 13558 chip, and to schedule for that chip's hazards. 13559 13560`-march=CPU' 13561 Generate code for a particular MIPS CPU. It is exactly equivalent 13562 to `-mCPU', except that there are more value of CPU understood. 13563 Valid CPU value are: 13564 13565 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, 13566 vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, 13567 rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 13568 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 13569 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc, 13570 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1, 13571 34kc, 34kf2_1, 34kf, 34kf1_1, 34kn, 74kc, 74kf2_1, 74kf, 13572 74kf1_1, 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1, 5kc, 13573 5kf, 20kc, 25kf, sb1, sb1a, loongson2e, loongson2f, 13574 loongson3a, octeon, octeon+, octeon2, xlr, xlp 13575 13576 For compatibility reasons, `Nx' and `Bfx' are accepted as synonyms 13577 for `Nf1_1'. These values are deprecated. 13578 13579`-mtune=CPU' 13580 Schedule and tune for a particular MIPS CPU. Valid CPU values are 13581 identical to `-march=CPU'. 13582 13583`-mabi=ABI' 13584 Record which ABI the source code uses. The recognized arguments 13585 are: `32', `n32', `o64', `64' and `eabi'. 13586 13587`-msym32' 13588`-mno-sym32' 13589 Equivalent to adding `.set sym32' or `.set nosym32' to the 13590 beginning of the assembler input. *Note MIPS Symbol Sizes::. 13591 13592`-nocpp' 13593 This option is ignored. It is accepted for command-line 13594 compatibility with other assemblers, which use it to turn off C 13595 style preprocessing. With GNU `as', there is no need for 13596 `-nocpp', because the GNU assembler itself never runs the C 13597 preprocessor. 13598 13599`-msoft-float' 13600`-mhard-float' 13601 Disable or enable floating-point instructions. Note that by 13602 default floating-point instructions are always allowed even with 13603 CPU targets that don't have support for these instructions. 13604 13605`-msingle-float' 13606`-mdouble-float' 13607 Disable or enable double-precision floating-point operations. Note 13608 that by default double-precision floating-point operations are 13609 always allowed even with CPU targets that don't have support for 13610 these operations. 13611 13612`--construct-floats' 13613`--no-construct-floats' 13614 The `--no-construct-floats' option disables the construction of 13615 double width floating point constants by loading the two halves of 13616 the value into the two single width floating point registers that 13617 make up the double width register. This feature is useful if the 13618 processor support the FR bit in its status register, and this bit 13619 is known (by the programmer) to be set. This bit prevents the 13620 aliasing of the double width register by the single width 13621 registers. 13622 13623 By default `--construct-floats' is selected, allowing construction 13624 of these floating point constants. 13625 13626`--relax-branch' 13627`--no-relax-branch' 13628 The `--relax-branch' option enables the relaxation of out-of-range 13629 branches. Any branches whose target cannot be reached directly are 13630 converted to a small instruction sequence including an 13631 inverse-condition branch to the physically next instruction, and a 13632 jump to the original target is inserted between the two 13633 instructions. In PIC code the jump will involve further 13634 instructions for address calculation. 13635 13636 The `BC1ANY2F', `BC1ANY2T', `BC1ANY4F', `BC1ANY4T', `BPOSGE32' and 13637 `BPOSGE64' instructions are excluded from relaxation, because they 13638 have no complementing counterparts. They could be relaxed with 13639 the use of a longer sequence involving another branch, however 13640 this has not been implemented and if their target turns out of 13641 reach, they produce an error even if branch relaxation is enabled. 13642 13643 Also no MIPS16 branches are ever relaxed. 13644 13645 By default `--no-relax-branch' is selected, causing any 13646 out-of-range branches to produce an error. 13647 13648`-mnan=ENCODING' 13649 This option indicates whether the source code uses the IEEE 2008 13650 NaN encoding (`-mnan=2008') or the original MIPS encoding 13651 (`-mnan=legacy'). It is equivalent to adding a `.nan' directive 13652 to the beginning of the source file. *Note MIPS NaN Encodings::. 13653 13654 `-mnan=legacy' is the default if no `-mnan' option or `.nan' 13655 directive is used. 13656 13657`--trap' 13658`--no-break' 13659 `as' automatically macro expands certain division and 13660 multiplication instructions to check for overflow and division by 13661 zero. This option causes `as' to generate code to take a trap 13662 exception rather than a break exception when an error is detected. 13663 The trap instructions are only supported at Instruction Set 13664 Architecture level 2 and higher. 13665 13666`--break' 13667`--no-trap' 13668 Generate code to take a break exception rather than a trap 13669 exception when an error is detected. This is the default. 13670 13671`-mpdr' 13672`-mno-pdr' 13673 Control generation of `.pdr' sections. Off by default on IRIX, on 13674 elsewhere. 13675 13676`-mshared' 13677`-mno-shared' 13678 When generating code using the Unix calling conventions (selected 13679 by `-KPIC' or `-mcall_shared'), gas will normally generate code 13680 which can go into a shared library. The `-mno-shared' option 13681 tells gas to generate code which uses the calling convention, but 13682 can not go into a shared library. The resulting code is slightly 13683 more efficient. This option only affects the handling of the 13684 `.cpload' and `.cpsetup' pseudo-ops. 13685 13686 13687File: as.info, Node: MIPS Macros, Next: MIPS Symbol Sizes, Prev: MIPS Options, Up: MIPS-Dependent 13688 136899.27.2 High-level assembly macros 13690--------------------------------- 13691 13692MIPS assemblers have traditionally provided a wider range of 13693instructions than the MIPS architecture itself. These extra 13694instructions are usually referred to as "macro" instructions (1). 13695 13696 Some MIPS macro instructions extend an underlying architectural 13697instruction while others are entirely new. An example of the former 13698type is `and', which allows the third operand to be either a register 13699or an arbitrary immediate value. Examples of the latter type include 13700`bgt', which branches to the third operand when the first operand is 13701greater than the second operand, and `ulh', which implements an 13702unaligned 2-byte load. 13703 13704 One of the most common extensions provided by macros is to expand 13705memory offsets to the full address range (32 or 64 bits) and to allow 13706symbolic offsets such as `my_data + 4' to be used in place of integer 13707constants. For example, the architectural instruction `lbu' allows 13708only a signed 16-bit offset, whereas the macro `lbu' allows code such 13709as `lbu $4,array+32769($5)'. The implementation of these symbolic 13710offsets depends on several factors, such as whether the assembler is 13711generating SVR4-style PIC (selected by `-KPIC', *note Assembler 13712options: MIPS Options.), the size of symbols (*note Directives to 13713override the size of symbols: MIPS Symbol Sizes.), and the small data 13714limit (*note Controlling the use of small data accesses: MIPS Small 13715Data.). 13716 13717 Sometimes it is undesirable to have one assembly instruction expand 13718to several machine instructions. The directive `.set nomacro' tells 13719the assembler to warn when this happens. `.set macro' restores the 13720default behavior. 13721 13722 Some macro instructions need a temporary register to store 13723intermediate results. This register is usually `$1', also known as 13724`$at', but it can be changed to any core register REG using `.set 13725at=REG'. Note that `$at' always refers to `$1' regardless of which 13726register is being used as the temporary register. 13727 13728 Implicit uses of the temporary register in macros could interfere 13729with explicit uses in the assembly code. The assembler therefore warns 13730whenever it sees an explicit use of the temporary register. The 13731directive `.set noat' silences this warning while `.set at' restores 13732the default behavior. It is safe to use `.set noat' while `.set 13733nomacro' is in effect since single-instruction macros never need a 13734temporary register. 13735 13736 Note that while the GNU assembler provides these macros for 13737compatibility, it does not make any attempt to optimize them with the 13738surrounding code. 13739 13740 ---------- Footnotes ---------- 13741 13742 (1) The term "macro" is somewhat overloaded here, since these macros 13743have no relation to those defined by `.macro', *note `.macro': Macro. 13744 13745 13746File: as.info, Node: MIPS Symbol Sizes, Next: MIPS Small Data, Prev: MIPS Macros, Up: MIPS-Dependent 13747 137489.27.3 Directives to override the size of symbols 13749------------------------------------------------- 13750 13751The n64 ABI allows symbols to have any 64-bit value. Although this 13752provides a great deal of flexibility, it means that some macros have 13753much longer expansions than their 32-bit counterparts. For example, 13754the non-PIC expansion of `dla $4,sym' is usually: 13755 13756 lui $4,%highest(sym) 13757 lui $1,%hi(sym) 13758 daddiu $4,$4,%higher(sym) 13759 daddiu $1,$1,%lo(sym) 13760 dsll32 $4,$4,0 13761 daddu $4,$4,$1 13762 13763 whereas the 32-bit expansion is simply: 13764 13765 lui $4,%hi(sym) 13766 daddiu $4,$4,%lo(sym) 13767 13768 n64 code is sometimes constructed in such a way that all symbolic 13769constants are known to have 32-bit values, and in such cases, it's 13770preferable to use the 32-bit expansion instead of the 64-bit expansion. 13771 13772 You can use the `.set sym32' directive to tell the assembler that, 13773from this point on, all expressions of the form `SYMBOL' or `SYMBOL + 13774OFFSET' have 32-bit values. For example: 13775 13776 .set sym32 13777 dla $4,sym 13778 lw $4,sym+16 13779 sw $4,sym+0x8000($4) 13780 13781 will cause the assembler to treat `sym', `sym+16' and `sym+0x8000' 13782as 32-bit values. The handling of non-symbolic addresses is not 13783affected. 13784 13785 The directive `.set nosym32' ends a `.set sym32' block and reverts 13786to the normal behavior. It is also possible to change the symbol size 13787using the command-line options `-msym32' and `-mno-sym32'. 13788 13789 These options and directives are always accepted, but at present, 13790they have no effect for anything other than n64. 13791 13792 13793File: as.info, Node: MIPS Small Data, Next: MIPS ISA, Prev: MIPS Symbol Sizes, Up: MIPS-Dependent 13794 137959.27.4 Controlling the use of small data accesses 13796------------------------------------------------- 13797 13798It often takes several instructions to load the address of a symbol. 13799For example, when `addr' is a 32-bit symbol, the non-PIC expansion of 13800`dla $4,addr' is usually: 13801 13802 lui $4,%hi(addr) 13803 daddiu $4,$4,%lo(addr) 13804 13805 The sequence is much longer when `addr' is a 64-bit symbol. *Note 13806Directives to override the size of symbols: MIPS Symbol Sizes. 13807 13808 In order to cut down on this overhead, most embedded MIPS systems 13809set aside a 64-kilobyte "small data" area and guarantee that all data 13810of size N and smaller will be placed in that area. The limit N is 13811passed to both the assembler and the linker using the command-line 13812option `-G N', *note Assembler options: MIPS Options. Note that the 13813same value of N must be used when linking and when assembling all input 13814files to the link; any inconsistency could cause a relocation overflow 13815error. 13816 13817 The size of an object in the `.bss' section is set by the `.comm' or 13818`.lcomm' directive that defines it. The size of an external object may 13819be set with the `.extern' directive. For example, `.extern sym,4' 13820declares that the object at `sym' is 4 bytes in length, while leaving 13821`sym' otherwise undefined. 13822 13823 When no `-G' option is given, the default limit is 8 bytes. The 13824option `-G 0' prevents any data from being automatically classified as 13825small. 13826 13827 It is also possible to mark specific objects as small by putting them 13828in the special sections `.sdata' and `.sbss', which are "small" 13829counterparts of `.data' and `.bss' respectively. The toolchain will 13830treat such data as small regardless of the `-G' setting. 13831 13832 On startup, systems that support a small data area are expected to 13833initialize register `$28', also known as `$gp', in such a way that 13834small data can be accessed using a 16-bit offset from that register. 13835For example, when `addr' is small data, the `dla $4,addr' instruction 13836above is equivalent to: 13837 13838 daddiu $4,$28,%gp_rel(addr) 13839 13840 Small data is not supported for SVR4-style PIC. 13841 13842 13843File: as.info, Node: MIPS ISA, Next: MIPS assembly options, Prev: MIPS Small Data, Up: MIPS-Dependent 13844 138459.27.5 Directives to override the ISA level 13846------------------------------------------- 13847 13848GNU `as' supports an additional directive to change the MIPS 13849Instruction Set Architecture level on the fly: `.set mipsN'. N should 13850be a number from 0 to 5, or 32, 32r2, 64 or 64r2. The values other 13851than 0 make the assembler accept instructions for the corresponding ISA 13852level, from that point on in the assembly. `.set mipsN' affects not 13853only which instructions are permitted, but also how certain macros are 13854expanded. `.set mips0' restores the ISA level to its original level: 13855either the level you selected with command line options, or the default 13856for your configuration. You can use this feature to permit specific 13857MIPS III instructions while assembling in 32 bit mode. Use this 13858directive with care! 13859 13860 The `.set arch=CPU' directive provides even finer control. It 13861changes the effective CPU target and allows the assembler to use 13862instructions specific to a particular CPU. All CPUs supported by the 13863`-march' command line option are also selectable by this directive. 13864The original value is restored by `.set arch=default'. 13865 13866 The directive `.set mips16' puts the assembler into MIPS 16 mode, in 13867which it will assemble instructions for the MIPS 16 processor. Use 13868`.set nomips16' to return to normal 32 bit mode. 13869 13870 Traditional MIPS assemblers do not support this directive. 13871 13872 The directive `.set micromips' puts the assembler into microMIPS 13873mode, in which it will assemble instructions for the microMIPS 13874processor. Use `.set nomicromips' to return to normal 32 bit mode. 13875 13876 Traditional MIPS assemblers do not support this directive. 13877 13878 13879File: as.info, Node: MIPS assembly options, Next: MIPS autoextend, Prev: MIPS ISA, Up: MIPS-Dependent 13880 138819.27.6 Directives to control code generation 13882-------------------------------------------- 13883 13884The directive `.set insn32' makes the assembler only use 32-bit 13885instruction encodings when generating code for the microMIPS processor. 13886This directive inhibits the use of any 16-bit instructions from that 13887point on in the assembly. The `.set noinsn32' directive allows 16-bit 13888instructions to be accepted. 13889 13890 Traditional MIPS assemblers do not support this directive. 13891 13892 13893File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS assembly options, Up: MIPS-Dependent 13894 138959.27.7 Directives for extending MIPS 16 bit instructions 13896-------------------------------------------------------- 13897 13898By default, MIPS 16 instructions are automatically extended to 32 bits 13899when necessary. The directive `.set noautoextend' will turn this off. 13900When `.set noautoextend' is in effect, any 32 bit instruction must be 13901explicitly extended with the `.e' modifier (e.g., `li.e $4,1000'). The 13902directive `.set autoextend' may be used to once again automatically 13903extend instructions when necessary. 13904 13905 This directive is only meaningful when in MIPS 16 mode. Traditional 13906MIPS assemblers do not support this directive. 13907 13908 13909File: as.info, Node: MIPS insn, Next: MIPS NaN Encodings, Prev: MIPS autoextend, Up: MIPS-Dependent 13910 139119.27.8 Directive to mark data as an instruction 13912----------------------------------------------- 13913 13914The `.insn' directive tells `as' that the following data is actually 13915instructions. This makes a difference in MIPS 16 and microMIPS modes: 13916when loading the address of a label which precedes instructions, `as' 13917automatically adds 1 to the value, so that jumping to the loaded 13918address will do the right thing. 13919 13920 The `.global' and `.globl' directives supported by `as' will by 13921default mark the symbol as pointing to a region of data not code. This 13922means that, for example, any instructions following such a symbol will 13923not be disassembled by `objdump' as it will regard them as data. To 13924change this behaviour an optional section name can be placed after the 13925symbol name in the `.global' directive. If this section exists and is 13926known to be a code section, then the symbol will be marked as poiting at 13927code not data. Ie the syntax for the directive is: 13928 13929 `.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...', 13930 13931 Here is a short example: 13932 13933 .global foo .text, bar, baz .data 13934 foo: 13935 nop 13936 bar: 13937 .word 0x0 13938 baz: 13939 .word 0x1 13940 13941 13942File: as.info, Node: MIPS NaN Encodings, Next: MIPS Option Stack, Prev: MIPS insn, Up: MIPS-Dependent 13943 139449.27.9 Directives to record which NaN encoding is being used 13945------------------------------------------------------------ 13946 13947The IEEE 754 floating-point standard defines two types of not-a-number 13948(NaN) data: "signalling" NaNs and "quiet" NaNs. The original version 13949of the standard did not specify how these two types should be 13950distinguished. Most implementations followed the i387 model, in which 13951the first bit of the significand is set for quiet NaNs and clear for 13952signalling NaNs. However, the original MIPS implementation assigned the 13953opposite meaning to the bit, so that it was set for signalling NaNs and 13954clear for quiet NaNs. 13955 13956 The 2008 revision of the standard formally suggested the i387 choice 13957and as from Sep 2012 the current release of the MIPS architecture 13958therefore optionally supports that form. Code that uses one NaN 13959encoding would usually be incompatible with code that uses the other 13960NaN encoding, so MIPS ELF objects have a flag (`EF_MIPS_NAN2008') to 13961record which encoding is being used. 13962 13963 Assembly files can use the `.nan' directive to select between the 13964two encodings. `.nan 2008' says that the assembly file uses the IEEE 13965754-2008 encoding while `.nan legacy' says that the file uses the 13966original MIPS encoding. If several `.nan' directives are given, the 13967final setting is the one that is used. 13968 13969 The command-line options `-mnan=legacy' and `-mnan=2008' can be used 13970instead of `.nan legacy' and `.nan 2008' respectively. However, any 13971`.nan' directive overrides the command-line setting. 13972 13973 `.nan legacy' is the default if no `.nan' directive or `-mnan' 13974option is given. 13975 13976 Note that GNU `as' does not produce NaNs itself and therefore these 13977directives do not affect code generation. They simply control the 13978setting of the `EF_MIPS_NAN2008' flag. 13979 13980 Traditional MIPS assemblers do not support these directives. 13981 13982 13983File: as.info, Node: MIPS Option Stack, Next: MIPS ASE Instruction Generation Overrides, Prev: MIPS NaN Encodings, Up: MIPS-Dependent 13984 139859.27.10 Directives to save and restore options 13986---------------------------------------------- 13987 13988The directives `.set push' and `.set pop' may be used to save and 13989restore the current settings for all the options which are controlled 13990by `.set'. The `.set push' directive saves the current settings on a 13991stack. The `.set pop' directive pops the stack and restores the 13992settings. 13993 13994 These directives can be useful inside an macro which must change an 13995option such as the ISA level or instruction reordering but does not want 13996to change the state of the code which invoked the macro. 13997 13998 Traditional MIPS assemblers do not support these directives. 13999 14000 14001File: as.info, Node: MIPS ASE Instruction Generation Overrides, Next: MIPS Floating-Point, Prev: MIPS Option Stack, Up: MIPS-Dependent 14002 140039.27.11 Directives to control generation of MIPS ASE instructions 14004----------------------------------------------------------------- 14005 14006The directive `.set mips3d' makes the assembler accept instructions 14007from the MIPS-3D Application Specific Extension from that point on in 14008the assembly. The `.set nomips3d' directive prevents MIPS-3D 14009instructions from being accepted. 14010 14011 The directive `.set smartmips' makes the assembler accept 14012instructions from the SmartMIPS Application Specific Extension to the 14013MIPS32 ISA from that point on in the assembly. The `.set nosmartmips' 14014directive prevents SmartMIPS instructions from being accepted. 14015 14016 The directive `.set mdmx' makes the assembler accept instructions 14017from the MDMX Application Specific Extension from that point on in the 14018assembly. The `.set nomdmx' directive prevents MDMX instructions from 14019being accepted. 14020 14021 The directive `.set dsp' makes the assembler accept instructions 14022from the DSP Release 1 Application Specific Extension from that point 14023on in the assembly. The `.set nodsp' directive prevents DSP Release 1 14024instructions from being accepted. 14025 14026 The directive `.set dspr2' makes the assembler accept instructions 14027from the DSP Release 2 Application Specific Extension from that point 14028on in the assembly. This dirctive implies `.set dsp'. The `.set 14029nodspr2' directive prevents DSP Release 2 instructions from being 14030accepted. 14031 14032 The directive `.set mt' makes the assembler accept instructions from 14033the MT Application Specific Extension from that point on in the 14034assembly. The `.set nomt' directive prevents MT instructions from 14035being accepted. 14036 14037 The directive `.set mcu' makes the assembler accept instructions 14038from the MCU Application Specific Extension from that point on in the 14039assembly. The `.set nomcu' directive prevents MCU instructions from 14040being accepted. 14041 14042 The directive `.set virt' makes the assembler accept instructions 14043from the Virtualization Application Specific Extension from that point 14044on in the assembly. The `.set novirt' directive prevents Virtualization 14045instructions from being accepted. 14046 14047 Traditional MIPS assemblers do not support these directives. 14048 14049 14050File: as.info, Node: MIPS Floating-Point, Next: MIPS Syntax, Prev: MIPS ASE Instruction Generation Overrides, Up: MIPS-Dependent 14051 140529.27.12 Directives to override floating-point options 14053----------------------------------------------------- 14054 14055The directives `.set softfloat' and `.set hardfloat' provide finer 14056control of disabling and enabling float-point instructions. These 14057directives always override the default (that hard-float instructions 14058are accepted) or the command-line options (`-msoft-float' and 14059`-mhard-float'). 14060 14061 The directives `.set singlefloat' and `.set doublefloat' provide 14062finer control of disabling and enabling double-precision float-point 14063operations. These directives always override the default (that 14064double-precision operations are accepted) or the command-line options 14065(`-msingle-float' and `-mdouble-float'). 14066 14067 Traditional MIPS assemblers do not support these directives. 14068 14069 14070File: as.info, Node: MIPS Syntax, Prev: MIPS Floating-Point, Up: MIPS-Dependent 14071 140729.27.13 Syntactical considerations for the MIPS assembler 14073--------------------------------------------------------- 14074 14075* Menu: 14076 14077* MIPS-Chars:: Special Characters 14078 14079 14080File: as.info, Node: MIPS-Chars, Up: MIPS Syntax 14081 140829.27.13.1 Special Characters 14083............................ 14084 14085The presence of a `#' on a line indicates the start of a comment that 14086extends to the end of the current line. 14087 14088 If a `#' appears as the first character of a line, the whole line is 14089treated as a comment, but in this case the line can also be a logical 14090line number directive (*note Comments::) or a preprocessor control 14091command (*note Preprocessing::). 14092 14093 The `;' character can be used to separate statements on the same 14094line. 14095 14096 14097File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies 14098 140999.28 MMIX Dependent Features 14100============================ 14101 14102* Menu: 14103 14104* MMIX-Opts:: Command-line Options 14105* MMIX-Expand:: Instruction expansion 14106* MMIX-Syntax:: Syntax 14107* MMIX-mmixal:: Differences to `mmixal' syntax and semantics 14108 14109 14110File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent 14111 141129.28.1 Command-line Options 14113--------------------------- 14114 14115The MMIX version of `as' has some machine-dependent options. 14116 14117 When `--fixed-special-register-names' is specified, only the register 14118names specified in *note MMIX-Regs:: are recognized in the instructions 14119`PUT' and `GET'. 14120 14121 You can use the `--globalize-symbols' to make all symbols global. 14122This option is useful when splitting up a `mmixal' program into several 14123files. 14124 14125 The `--gnu-syntax' turns off most syntax compatibility with 14126`mmixal'. Its usability is currently doubtful. 14127 14128 The `--relax' option is not fully supported, but will eventually make 14129the object file prepared for linker relaxation. 14130 14131 If you want to avoid inadvertently calling a predefined symbol and 14132would rather get an error, for example when using `as' with a compiler 14133or other machine-generated code, specify `--no-predefined-syms'. This 14134turns off built-in predefined definitions of all such symbols, 14135including rounding-mode symbols, segment symbols, `BIT' symbols, and 14136`TRAP' symbols used in `mmix' "system calls". It also turns off 14137predefined special-register names, except when used in `PUT' and `GET' 14138instructions. 14139 14140 By default, some instructions are expanded to fit the size of the 14141operand or an external symbol (*note MMIX-Expand::). By passing 14142`--no-expand', no such expansion will be done, instead causing errors 14143at link time if the operand does not fit. 14144 14145 The `mmixal' documentation (*note mmixsite::) specifies that global 14146registers allocated with the `GREG' directive (*note MMIX-greg::) and 14147initialized to the same non-zero value, will refer to the same global 14148register. This isn't strictly enforceable in `as' since the final 14149addresses aren't known until link-time, but it will do an effort unless 14150the `--no-merge-gregs' option is specified. (Register merging isn't 14151yet implemented in `ld'.) 14152 14153 `as' will warn every time it expands an instruction to fit an 14154operand unless the option `-x' is specified. It is believed that this 14155behaviour is more useful than just mimicking `mmixal''s behaviour, in 14156which instructions are only expanded if the `-x' option is specified, 14157and assembly fails otherwise, when an instruction needs to be expanded. 14158It needs to be kept in mind that `mmixal' is both an assembler and 14159linker, while `as' will expand instructions that at link stage can be 14160contracted. (Though linker relaxation isn't yet implemented in `ld'.) 14161The option `-x' also imples `--linker-allocated-gregs'. 14162 14163 If instruction expansion is enabled, `as' can expand a `PUSHJ' 14164instruction into a series of instructions. The shortest expansion is 14165to not expand it, but just mark the call as redirectable to a stub, 14166which `ld' creates at link-time, but only if the original `PUSHJ' 14167instruction is found not to reach the target. The stub consists of the 14168necessary instructions to form a jump to the target. This happens if 14169`as' can assert that the `PUSHJ' instruction can reach such a stub. 14170The option `--no-pushj-stubs' disables this shorter expansion, and the 14171longer series of instructions is then created at assembly-time. The 14172option `--no-stubs' is a synonym, intended for compatibility with 14173future releases, where generation of stubs for other instructions may 14174be implemented. 14175 14176 Usually a two-operand-expression (*note GREG-base::) without a 14177matching `GREG' directive is treated as an error by `as'. When the 14178option `--linker-allocated-gregs' is in effect, they are instead passed 14179through to the linker, which will allocate as many global registers as 14180is needed. 14181 14182 14183File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent 14184 141859.28.2 Instruction expansion 14186---------------------------- 14187 14188When `as' encounters an instruction with an operand that is either not 14189known or does not fit the operand size of the instruction, `as' (and 14190`ld') will expand the instruction into a sequence of instructions 14191semantically equivalent to the operand fitting the instruction. 14192Expansion will take place for the following instructions: 14193 14194`GETA' 14195 Expands to a sequence of four instructions: `SETL', `INCML', 14196 `INCMH' and `INCH'. The operand must be a multiple of four. 14197 14198Conditional branches 14199 A branch instruction is turned into a branch with the complemented 14200 condition and prediction bit over five instructions; four 14201 instructions setting `$255' to the operand value, which like with 14202 `GETA' must be a multiple of four, and a final `GO $255,$255,0'. 14203 14204`PUSHJ' 14205 Similar to expansion for conditional branches; four instructions 14206 set `$255' to the operand value, followed by a `PUSHGO 14207 $255,$255,0'. 14208 14209`JMP' 14210 Similar to conditional branches and `PUSHJ'. The final instruction 14211 is `GO $255,$255,0'. 14212 14213 The linker `ld' is expected to shrink these expansions for code 14214assembled with `--relax' (though not currently implemented). 14215 14216 14217File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent 14218 142199.28.3 Syntax 14220------------- 14221 14222The assembly syntax is supposed to be upward compatible with that 14223described in Sections 1.3 and 1.4 of `The Art of Computer Programming, 14224Volume 1'. Draft versions of those chapters as well as other MMIX 14225information is located at 14226`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html'. Most code 14227examples from the mmixal package located there should work unmodified 14228when assembled and linked as single files, with a few noteworthy 14229exceptions (*note MMIX-mmixal::). 14230 14231 Before an instruction is emitted, the current location is aligned to 14232the next four-byte boundary. If a label is defined at the beginning of 14233the line, its value will be the aligned value. 14234 14235 In addition to the traditional hex-prefix `0x', a hexadecimal number 14236can also be specified by the prefix character `#'. 14237 14238 After all operands to an MMIX instruction or directive have been 14239specified, the rest of the line is ignored, treated as a comment. 14240 14241* Menu: 14242 14243* MMIX-Chars:: Special Characters 14244* MMIX-Symbols:: Symbols 14245* MMIX-Regs:: Register Names 14246* MMIX-Pseudos:: Assembler Directives 14247 14248 14249File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax 14250 142519.28.3.1 Special Characters 14252........................... 14253 14254The characters `*' and `#' are line comment characters; each start a 14255comment at the beginning of a line, but only at the beginning of a 14256line. A `#' prefixes a hexadecimal number if found elsewhere on a 14257line. If a `#' appears at the start of a line the whole line is 14258treated as a comment, but the line can also act as a logical line 14259number directive (*note Comments::) or a preprocessor control command 14260(*note Preprocessing::). 14261 14262 Two other characters, `%' and `!', each start a comment anywhere on 14263the line. Thus you can't use the `modulus' and `not' operators in 14264expressions normally associated with these two characters. 14265 14266 A `;' is a line separator, treated as a new-line, so separate 14267instructions can be specified on a single line. 14268 14269 14270File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax 14271 142729.28.3.2 Symbols 14273................ 14274 14275The character `:' is permitted in identifiers. There are two 14276exceptions to it being treated as any other symbol character: if a 14277symbol begins with `:', it means that the symbol is in the global 14278namespace and that the current prefix should not be prepended to that 14279symbol (*note MMIX-prefix::). The `:' is then not considered part of 14280the symbol. For a symbol in the label position (first on a line), a `:' 14281at the end of a symbol is silently stripped off. A label is permitted, 14282but not required, to be followed by a `:', as with many other assembly 14283formats. 14284 14285 The character `@' in an expression, is a synonym for `.', the 14286current location. 14287 14288 In addition to the common forward and backward local symbol formats 14289(*note Symbol Names::), they can be specified with upper-case `B' and 14290`F', as in `8B' and `9F'. A local label defined for the current 14291position is written with a `H' appended to the number: 14292 3H LDB $0,$1,2 14293 This and traditional local-label formats cannot be mixed: a label 14294must be defined and referred to using the same format. 14295 14296 There's a minor caveat: just as for the ordinary local symbols, the 14297local symbols are translated into ordinary symbols using control 14298characters are to hide the ordinal number of the symbol. 14299Unfortunately, these symbols are not translated back in error messages. 14300Thus you may see confusing error messages when local symbols are used. 14301Control characters `\003' (control-C) and `\004' (control-D) are used 14302for the MMIX-specific local-symbol syntax. 14303 14304 The symbol `Main' is handled specially; it is always global. 14305 14306 By defining the symbols `__.MMIX.start..text' and 14307`__.MMIX.start..data', the address of respectively the `.text' and 14308`.data' segments of the final program can be defined, though when 14309linking more than one object file, the code or data in the object file 14310containing the symbol is not guaranteed to be start at that position; 14311just the final executable. *Note MMIX-loc::. 14312 14313 14314File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax 14315 143169.28.3.3 Register names 14317....................... 14318 14319Local and global registers are specified as `$0' to `$255'. The 14320recognized special register names are `rJ', `rA', `rB', `rC', `rD', 14321`rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ', 14322`rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT', 14323`rWW', `rXX', `rYY' and `rZZ'. A leading `:' is optional for special 14324register names. 14325 14326 Local and global symbols can be equated to register names and used in 14327place of ordinary registers. 14328 14329 Similarly for special registers, local and global symbols can be 14330used. Also, symbols equated from numbers and constant expressions are 14331allowed in place of a special register, except when either of the 14332options `--no-predefined-syms' and `--fixed-special-register-names' are 14333specified. Then only the special register names above are allowed for 14334the instructions having a special register operand; `GET' and `PUT'. 14335 14336 14337File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax 14338 143399.28.3.4 Assembler Directives 14340............................. 14341 14342`LOC' 14343 The `LOC' directive sets the current location to the value of the 14344 operand field, which may include changing sections. If the 14345 operand is a constant, the section is set to either `.data' if the 14346 value is `0x2000000000000000' or larger, else it is set to `.text'. 14347 Within a section, the current location may only be changed to 14348 monotonically higher addresses. A LOC expression must be a 14349 previously defined symbol or a "pure" constant. 14350 14351 An example, which sets the label PREV to the current location, and 14352 updates the current location to eight bytes forward: 14353 prev LOC @+8 14354 14355 When a LOC has a constant as its operand, a symbol 14356 `__.MMIX.start..text' or `__.MMIX.start..data' is defined 14357 depending on the address as mentioned above. Each such symbol is 14358 interpreted as special by the linker, locating the section at that 14359 address. Note that if multiple files are linked, the first object 14360 file with that section will be mapped to that address (not 14361 necessarily the file with the LOC definition). 14362 14363`LOCAL' 14364 Example: 14365 LOCAL external_symbol 14366 LOCAL 42 14367 .local asymbol 14368 14369 This directive-operation generates a link-time assertion that the 14370 operand does not correspond to a global register. The operand is 14371 an expression that at link-time resolves to a register symbol or a 14372 number. A number is treated as the register having that number. 14373 There is one restriction on the use of this directive: the 14374 pseudo-directive must be placed in a section with contents, code 14375 or data. 14376 14377`IS' 14378 The `IS' directive: 14379 asymbol IS an_expression 14380 sets the symbol `asymbol' to `an_expression'. A symbol may not be 14381 set more than once using this directive. Local labels may be set 14382 using this directive, for example: 14383 5H IS @+4 14384 14385`GREG' 14386 This directive reserves a global register, gives it an initial 14387 value and optionally gives it a symbolic name. Some examples: 14388 14389 areg GREG 14390 breg GREG data_value 14391 GREG data_buffer 14392 .greg creg, another_data_value 14393 14394 The symbolic register name can be used in place of a (non-special) 14395 register. If a value isn't provided, it defaults to zero. Unless 14396 the option `--no-merge-gregs' is specified, non-zero registers 14397 allocated with this directive may be eliminated by `as'; another 14398 register with the same value used in its place. Any of the 14399 instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU', 14400 `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW', 14401 `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT', 14402 `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can 14403 have a value nearby an initial value in place of its second and 14404 third operands. Here, "nearby" is defined as within the range 14405 0...255 from the initial value of such an allocated register. 14406 14407 buffer1 BYTE 0,0,0,0,0 14408 buffer2 BYTE 0,0,0,0,0 14409 ... 14410 GREG buffer1 14411 LDOU $42,buffer2 14412 In the example above, the `Y' field of the `LDOUI' instruction 14413 (LDOU with a constant Z) will be replaced with the global register 14414 allocated for `buffer1', and the `Z' field will have the value 5, 14415 the offset from `buffer1' to `buffer2'. The result is equivalent 14416 to this code: 14417 buffer1 BYTE 0,0,0,0,0 14418 buffer2 BYTE 0,0,0,0,0 14419 ... 14420 tmpreg GREG buffer1 14421 LDOU $42,tmpreg,(buffer2-buffer1) 14422 14423 Global registers allocated with this directive are allocated in 14424 order higher-to-lower within a file. Other than that, the exact 14425 order of register allocation and elimination is undefined. For 14426 example, the order is undefined when more than one file with such 14427 directives are linked together. With the options `-x' and 14428 `--linker-allocated-gregs', `GREG' directives for two-operand 14429 cases like the one mentioned above can be omitted. Sufficient 14430 global registers will then be allocated by the linker. 14431 14432`BYTE' 14433 The `BYTE' directive takes a series of operands separated by a 14434 comma. If an operand is a string (*note Strings::), each 14435 character of that string is emitted as a byte. Other operands 14436 must be constant expressions without forward references, in the 14437 range 0...255. If you need operands having expressions with 14438 forward references, use `.byte' (*note Byte::). An operand can be 14439 omitted, defaulting to a zero value. 14440 14441`WYDE' 14442`TETRA' 14443`OCTA' 14444 The directives `WYDE', `TETRA' and `OCTA' emit constants of two, 14445 four and eight bytes size respectively. Before anything else 14446 happens for the directive, the current location is aligned to the 14447 respective constant-size boundary. If a label is defined at the 14448 beginning of the line, its value will be that after the alignment. 14449 A single operand can be omitted, defaulting to a zero value 14450 emitted for the directive. Operands can be expressed as strings 14451 (*note Strings::), in which case each character in the string is 14452 emitted as a separate constant of the size indicated by the 14453 directive. 14454 14455`PREFIX' 14456 The `PREFIX' directive sets a symbol name prefix to be prepended to 14457 all symbols (except local symbols, *note MMIX-Symbols::), that are 14458 not prefixed with `:', until the next `PREFIX' directive. Such 14459 prefixes accumulate. For example, 14460 PREFIX a 14461 PREFIX b 14462 c IS 0 14463 defines a symbol `abc' with the value 0. 14464 14465`BSPEC' 14466`ESPEC' 14467 A pair of `BSPEC' and `ESPEC' directives delimit a section of 14468 special contents (without specified semantics). Example: 14469 BSPEC 42 14470 TETRA 1,2,3 14471 ESPEC 14472 The single operand to `BSPEC' must be number in the range 0...255. 14473 The `BSPEC' number 80 is used by the GNU binutils implementation. 14474 14475 14476File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent 14477 144789.28.4 Differences to `mmixal' 14479------------------------------ 14480 14481The binutils `as' and `ld' combination has a few differences in 14482function compared to `mmixal' (*note mmixsite::). 14483 14484 The replacement of a symbol with a GREG-allocated register (*note 14485GREG-base::) is not handled the exactly same way in `as' as in 14486`mmixal'. This is apparent in the `mmixal' example file `inout.mms', 14487where different registers with different offsets, eventually yielding 14488the same address, are used in the first instruction. This type of 14489difference should however not affect the function of any program unless 14490it has specific assumptions about the allocated register number. 14491 14492 Line numbers (in the `mmo' object format) are currently not 14493supported. 14494 14495 Expression operator precedence is not that of mmixal: operator 14496precedence is that of the C programming language. It's recommended to 14497use parentheses to explicitly specify wanted operator precedence 14498whenever more than one type of operators are used. 14499 14500 The serialize unary operator `&', the fractional division operator 14501`//', the logical not operator `!' and the modulus operator `%' are not 14502available. 14503 14504 Symbols are not global by default, unless the option 14505`--globalize-symbols' is passed. Use the `.global' directive to 14506globalize symbols (*note Global::). 14507 14508 Operand syntax is a bit stricter with `as' than `mmixal'. For 14509example, you can't say `addu 1,2,3', instead you must write `addu 14510$1,$2,3'. 14511 14512 You can't LOC to a lower address than those already visited (i.e., 14513"backwards"). 14514 14515 A LOC directive must come before any emitted code. 14516 14517 Predefined symbols are visible as file-local symbols after use. (In 14518the ELF file, that is--the linked mmo file has no notion of a file-local 14519symbol.) 14520 14521 Some mapping of constant expressions to sections in LOC expressions 14522is attempted, but that functionality is easily confused and should be 14523avoided unless compatibility with `mmixal' is required. A LOC 14524expression to `0x2000000000000000' or higher, maps to the `.data' 14525section and lower addresses map to the `.text' section (*note 14526MMIX-loc::). 14527 14528 The code and data areas are each contiguous. Sparse programs with 14529far-away LOC directives will take up the same amount of space as a 14530contiguous program with zeros filled in the gaps between the LOC 14531directives. If you need sparse programs, you might try and get the 14532wanted effect with a linker script and splitting up the code parts into 14533sections (*note Section::). Assembly code for this, to be compatible 14534with `mmixal', would look something like: 14535 .if 0 14536 LOC away_expression 14537 .else 14538 .section away,"ax" 14539 .fi 14540 `as' will not execute the LOC directive and `mmixal' ignores the 14541lines with `.'. This construct can be used generally to help 14542compatibility. 14543 14544 Symbols can't be defined twice-not even to the same value. 14545 14546 Instruction mnemonics are recognized case-insensitive, though the 14547`IS' and `GREG' pseudo-operations must be specified in upper-case 14548characters. 14549 14550 There's no unicode support. 14551 14552 The following is a list of programs in `mmix.tar.gz', available at 14553`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html', last 14554checked with the version dated 2001-08-25 (md5sum 14555c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do 14556not assemble with `as': 14557 14558`silly.mms' 14559 LOC to a previous address. 14560 14561`sim.mms' 14562 Redefines symbol `Done'. 14563 14564`test.mms' 14565 Uses the serial operator `&'. 14566 14567 14568File: as.info, Node: MSP430-Dependent, Next: NiosII-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies 14569 145709.29 MSP 430 Dependent Features 14571=============================== 14572 14573* Menu: 14574 14575* MSP430 Options:: Options 14576* MSP430 Syntax:: Syntax 14577* MSP430 Floating Point:: Floating Point 14578* MSP430 Directives:: MSP 430 Machine Directives 14579* MSP430 Opcodes:: Opcodes 14580* MSP430 Profiling Capability:: Profiling Capability 14581 14582 14583File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent 14584 145859.29.1 Options 14586-------------- 14587 14588`-mmcu' 14589 selects the mpu arch. If the architecture is 430Xv2 then this also 14590 enables NOP generation unless the `-mN' is also specified. 14591 14592`-mcpu' 14593 selects the cpu architecture. If the architecture is 430Xv2 then 14594 this also enables NOP generation unless the `-mN' is also 14595 specified. 14596 14597`-mP' 14598 enables polymorph instructions handler. 14599 14600`-mQ' 14601 enables relaxation at assembly time. DANGEROUS! 14602 14603`-ml' 14604 indicates that the input uses the large code model. 14605 14606`-mN' 14607 disables the generation of a NOP instruction following any 14608 instruction that might change the interrupts enabled/disabled 14609 state. For the 430Xv2 architecture the instructions: `EINT', 14610 `DINT', `BIC #8, SR', `BIS #8, SR' and `MOV.W <>, SR' must be 14611 followed by a NOP instruction in order to ensure the correct 14612 processing of interrupts. By default generation of the NOP 14613 instruction happens automatically, but this command line option 14614 disables this behaviour. It is then up to the programmer to ensure 14615 that interrupts are enabled and disabled correctly. 14616 14617 14618 14619File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent 14620 146219.29.2 Syntax 14622------------- 14623 14624* Menu: 14625 14626* MSP430-Macros:: Macros 14627* MSP430-Chars:: Special Characters 14628* MSP430-Regs:: Register Names 14629* MSP430-Ext:: Assembler Extensions 14630 14631 14632File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax 14633 146349.29.2.1 Macros 14635............... 14636 14637The macro syntax used on the MSP 430 is like that described in the MSP 14638430 Family Assembler Specification. Normal `as' macros should still 14639work. 14640 14641 Additional built-in macros are: 14642 14643`llo(exp)' 14644 Extracts least significant word from 32-bit expression 'exp'. 14645 14646`lhi(exp)' 14647 Extracts most significant word from 32-bit expression 'exp'. 14648 14649`hlo(exp)' 14650 Extracts 3rd word from 64-bit expression 'exp'. 14651 14652`hhi(exp)' 14653 Extracts 4rd word from 64-bit expression 'exp'. 14654 14655 14656 They normally being used as an immediate source operand. 14657 mov #llo(1), r10 ; == mov #1, r10 14658 mov #lhi(1), r10 ; == mov #0, r10 14659 14660 14661File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax 14662 146639.29.2.2 Special Characters 14664........................... 14665 14666A semicolon (`;') appearing anywhere on a line starts a comment that 14667extends to the end of that line. 14668 14669 If a `#' appears as the first character of a line then the whole 14670line is treated as a comment, but it can also be a logical line number 14671directive (*note Comments::) or a preprocessor control command (*note 14672Preprocessing::). 14673 14674 Multiple statements can appear on the same line provided that they 14675are separated by the `{' character. 14676 14677 The character `$' in jump instructions indicates current location and 14678implemented only for TI syntax compatibility. 14679 14680 14681File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax 14682 146839.29.2.3 Register Names 14684....................... 14685 14686General-purpose registers are represented by predefined symbols of the 14687form `rN' (for global registers), where N represents a number between 14688`0' and `15'. The leading letters may be in either upper or lower 14689case; for example, `r13' and `R7' are both valid register names. 14690 14691 Register names `PC', `SP' and `SR' cannot be used as register names 14692and will be treated as variables. Use `r0', `r1', and `r2' instead. 14693 14694 14695File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax 14696 146979.29.2.4 Assembler Extensions 14698............................. 14699 14700`@rN' 14701 As destination operand being treated as `0(rn)' 14702 14703`0(rN)' 14704 As source operand being treated as `@rn' 14705 14706`jCOND +N' 14707 Skips next N bytes followed by jump instruction and equivalent to 14708 `jCOND $+N+2' 14709 14710 14711 Also, there are some instructions, which cannot be found in other 14712assemblers. These are branch instructions, which has different opcodes 14713upon jump distance. They all got PC relative addressing mode. 14714 14715`beq label' 14716 A polymorph instruction which is `jeq label' in case if jump 14717 distance within allowed range for cpu's jump instruction. If not, 14718 this unrolls into a sequence of 14719 jne $+6 14720 br label 14721 14722`bne label' 14723 A polymorph instruction which is `jne label' or `jeq +4; br label' 14724 14725`blt label' 14726 A polymorph instruction which is `jl label' or `jge +4; br label' 14727 14728`bltn label' 14729 A polymorph instruction which is `jn label' or `jn +2; jmp +4; br 14730 label' 14731 14732`bltu label' 14733 A polymorph instruction which is `jlo label' or `jhs +2; br label' 14734 14735`bge label' 14736 A polymorph instruction which is `jge label' or `jl +4; br label' 14737 14738`bgeu label' 14739 A polymorph instruction which is `jhs label' or `jlo +4; br label' 14740 14741`bgt label' 14742 A polymorph instruction which is `jeq +2; jge label' or `jeq +6; 14743 jl +4; br label' 14744 14745`bgtu label' 14746 A polymorph instruction which is `jeq +2; jhs label' or `jeq +6; 14747 jlo +4; br label' 14748 14749`bleu label' 14750 A polymorph instruction which is `jeq label; jlo label' or `jeq 14751 +2; jhs +4; br label' 14752 14753`ble label' 14754 A polymorph instruction which is `jeq label; jl label' or `jeq 14755 +2; jge +4; br label' 14756 14757`jump label' 14758 A polymorph instruction which is `jmp label' or `br label' 14759 14760 14761File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent 14762 147639.29.3 Floating Point 14764--------------------- 14765 14766The MSP 430 family uses IEEE 32-bit floating-point numbers. 14767 14768 14769File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent 14770 147719.29.4 MSP 430 Machine Directives 14772--------------------------------- 14773 14774`.file' 14775 This directive is ignored; it is accepted for compatibility with 14776 other MSP 430 assemblers. 14777 14778 _Warning:_ in other versions of the GNU assembler, `.file' is 14779 used for the directive called `.app-file' in the MSP 430 14780 support. 14781 14782`.line' 14783 This directive is ignored; it is accepted for compatibility with 14784 other MSP 430 assemblers. 14785 14786`.arch' 14787 Sets the target microcontroller in the same way as the `-mmcu' 14788 command line option. 14789 14790`.cpu' 14791 Sets the target architecture in the same way as the `-mcpu' 14792 command line option. 14793 14794`.profiler' 14795 This directive instructs assembler to add new profile entry to the 14796 object file. 14797 14798 14799 14800File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent 14801 148029.29.5 Opcodes 14803-------------- 14804 14805`as' implements all the standard MSP 430 opcodes. No additional 14806pseudo-instructions are needed on this family. 14807 14808 For information on the 430 machine instruction set, see `MSP430 14809User's Manual, document slau049d', Texas Instrument, Inc. 14810 14811 14812File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent 14813 148149.29.6 Profiling Capability 14815--------------------------- 14816 14817It is a performance hit to use gcc's profiling approach for this tiny 14818target. Even more - jtag hardware facility does not perform any 14819profiling functions. However we've got gdb's built-in simulator where 14820we can do anything. 14821 14822 We define new section `.profiler' which holds all profiling 14823information. We define new pseudo operation `.profiler' which will 14824instruct assembler to add new profile entry to the object file. Profile 14825should take place at the present address. 14826 14827 Pseudo operation format: 14828 14829 `.profiler flags,function_to_profile [, cycle_corrector, extra]' 14830 14831 where: 14832 14833 `flags' is a combination of the following characters: 14834 14835 `s' 14836 function entry 14837 14838 `x' 14839 function exit 14840 14841 `i' 14842 function is in init section 14843 14844 `f' 14845 function is in fini section 14846 14847 `l' 14848 library call 14849 14850 `c' 14851 libc standard call 14852 14853 `d' 14854 stack value demand 14855 14856 `I' 14857 interrupt service routine 14858 14859 `P' 14860 prologue start 14861 14862 `p' 14863 prologue end 14864 14865 `E' 14866 epilogue start 14867 14868 `e' 14869 epilogue end 14870 14871 `j' 14872 long jump / sjlj unwind 14873 14874 `a' 14875 an arbitrary code fragment 14876 14877 `t' 14878 extra parameter saved (a constant value like frame size) 14879 14880`function_to_profile' 14881 a function address 14882 14883`cycle_corrector' 14884 a value which should be added to the cycle counter, zero if 14885 omitted. 14886 14887`extra' 14888 any extra parameter, zero if omitted. 14889 14890 14891 For example: 14892 .global fxx 14893 .type fxx,@function 14894 fxx: 14895 .LFrameOffset_fxx=0x08 14896 .profiler "scdP", fxx ; function entry. 14897 ; we also demand stack value to be saved 14898 push r11 14899 push r10 14900 push r9 14901 push r8 14902 .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point 14903 ; (this is a prologue end) 14904 ; note, that spare var filled with 14905 ; the farme size 14906 mov r15,r8 14907 ... 14908 .profiler cdE,fxx ; check stack 14909 pop r8 14910 pop r9 14911 pop r10 14912 pop r11 14913 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter 14914 ret ; cause 'ret' insn takes 3 cycles 14915 14916 14917File: as.info, Node: NiosII-Dependent, Next: NS32K-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies 14918 149199.30 Nios II Dependent Features 14920=============================== 14921 14922* Menu: 14923 14924* Nios II Options:: Options 14925* Nios II Syntax:: Syntax 14926* Nios II Relocations:: Relocations 14927* Nios II Directives:: Nios II Machine Directives 14928* Nios II Opcodes:: Opcodes 14929 14930 14931File: as.info, Node: Nios II Options, Next: Nios II Syntax, Up: NiosII-Dependent 14932 149339.30.1 Options 14934-------------- 14935 14936`-relax-section' 14937 Replace identified out-of-range branches with PC-relative `jmp' 14938 sequences when possible. The generated code sequences are suitable 14939 for use in position-independent code, but there is a practical 14940 limit on the extended branch range because of the length of the 14941 sequences. This option is the default. 14942 14943`-relax-all' 14944 Replace branch instructions not determinable to be in range and 14945 all call instructions with `jmp' and `callr' sequences 14946 (respectively). This option generates absolute relocations 14947 against the target symbols and is not appropriate for 14948 position-independent code. 14949 14950`-no-relax' 14951 Do not replace any branches or calls. 14952 14953`-EB' 14954 Generate big-endian output. 14955 14956`-EL' 14957 Generate little-endian output. This is the default. 14958 14959 14960 14961File: as.info, Node: Nios II Syntax, Next: Nios II Relocations, Prev: Nios II Options, Up: NiosII-Dependent 14962 149639.30.2 Syntax 14964------------- 14965 14966* Menu: 14967 14968* Nios II Chars:: Special Characters 14969 14970 14971File: as.info, Node: Nios II Chars, Up: Nios II Syntax 14972 149739.30.2.1 Special Characters 14974........................... 14975 14976`#' is the line comment character. `;' is the line separator character. 14977 14978 14979File: as.info, Node: Nios II Relocations, Next: Nios II Directives, Prev: Nios II Syntax, Up: NiosII-Dependent 14980 149819.30.3 Nios II Machine Relocations 14982---------------------------------- 14983 14984`%hiadj(EXPRESSION)' 14985 Extract the upper 16 bits of EXPRESSION and add one if the 15th 14986 bit is set. 14987 14988 The value of `%hiadj(EXPRESSION)' is: 14989 ((EXPRESSION >> 16) & 0xffff) + ((EXPRESSION >> 15) & 0x01) 14990 14991 The `%hiadj' relocation is intended to be used with the `addi', 14992 `ld' or `st' instructions along with a `%lo', in order to load a 14993 32-bit constant. 14994 14995 movhi r2, %hiadj(symbol) 14996 addi r2, r2, %lo(symbol) 14997 14998`%hi(EXPRESSION)' 14999 Extract the upper 16 bits of EXPRESSION. 15000 15001`%lo(EXPRESSION)' 15002 Extract the lower 16 bits of EXPRESSION. 15003 15004`%gprel(EXPRESSION)' 15005 Subtract the value of the symbol `_gp' from EXPRESSION. 15006 15007 The intention of the `%gprel' relocation is to have a fast small 15008 area of memory which only takes a 16-bit immediate to access. 15009 15010 .section .sdata 15011 fastint: 15012 .int 123 15013 .section .text 15014 ldw r4, %gprel(fastint)(gp) 15015 15016`%call(EXPRESSION)' 15017`%got(EXPRESSION)' 15018`%gotoff(EXPRESSION)' 15019`%gotoff_lo(EXPRESSION)' 15020`%gotoff_hiadj(EXPRESSION)' 15021`%tls_gd(EXPRESSION)' 15022`%tls_ie(EXPRESSION)' 15023`%tls_le(EXPRESSION)' 15024`%tls_ldm(EXPRESSION)' 15025`%tls_ldo(EXPRESSION)' 15026 These relocations support the ABI for Linux Systems documented in 15027 the `Nios II Processor Reference Handbook'. 15028 15029 15030File: as.info, Node: Nios II Directives, Next: Nios II Opcodes, Prev: Nios II Relocations, Up: NiosII-Dependent 15031 150329.30.4 Nios II Machine Directives 15033--------------------------------- 15034 15035`.align EXPRESSION [, EXPRESSION]' 15036 This is the generic `.align' directive, however this aligns to a 15037 power of two. 15038 15039`.half EXPRESSION' 15040 Create an aligned constant 2 bytes in size. 15041 15042`.word EXPRESSION' 15043 Create an aligned constant 4 bytes in size. 15044 15045`.dword EXPRESSION' 15046 Create an aligned constant 8 bytes in size. 15047 15048`.2byte EXPRESSION' 15049 Create an unaligned constant 2 bytes in size. 15050 15051`.4byte EXPRESSION' 15052 Create an unaligned constant 4 bytes in size. 15053 15054`.8byte EXPRESSION' 15055 Create an unaligned constant 8 bytes in size. 15056 15057`.16byte EXPRESSION' 15058 Create an unaligned constant 16 bytes in size. 15059 15060`.set noat' 15061 Allows assembly code to use `at' register without warning. Macro 15062 or relaxation expansions generate warnings. 15063 15064`.set at' 15065 Assembly code using `at' register generates warnings, and macro 15066 expansion and relaxation are enabled. 15067 15068`.set nobreak' 15069 Allows assembly code to use `ba' and `bt' registers without 15070 warning. 15071 15072`.set break' 15073 Turns warnings back on for using `ba' and `bt' registers. 15074 15075`.set norelax' 15076 Do not replace any branches or calls. 15077 15078`.set relaxsection' 15079 Replace identified out-of-range branches with `jmp' sequences 15080 (default). 15081 15082`.set relaxsection' 15083 Replace all branch and call instructions with `jmp' and `callr' 15084 sequences. 15085 15086`.set ...' 15087 All other `.set' are the normal use. 15088 15089 15090 15091File: as.info, Node: Nios II Opcodes, Prev: Nios II Directives, Up: NiosII-Dependent 15092 150939.30.5 Opcodes 15094-------------- 15095 15096`as' implements all the standard Nios II opcodes documented in the 15097`Nios II Processor Reference Handbook', including the assembler 15098pseudo-instructions. 15099 15100 15101File: as.info, Node: NS32K-Dependent, Next: SH-Dependent, Prev: NiosII-Dependent, Up: Machine Dependencies 15102 151039.31 NS32K Dependent Features 15104============================= 15105 15106* Menu: 15107 15108* NS32K Syntax:: Syntax 15109 15110 15111File: as.info, Node: NS32K Syntax, Up: NS32K-Dependent 15112 151139.31.1 Syntax 15114------------- 15115 15116* Menu: 15117 15118* NS32K-Chars:: Special Characters 15119 15120 15121File: as.info, Node: NS32K-Chars, Up: NS32K Syntax 15122 151239.31.1.1 Special Characters 15124........................... 15125 15126The presence of a `#' appearing anywhere on a line indicates the start 15127of a comment that extends to the end of that line. 15128 15129 If a `#' appears as the first character of a line then the whole 15130line is treated as a comment, but in this case the line can also be a 15131logical line number directive (*note Comments::) or a preprocessor 15132control command (*note Preprocessing::). 15133 15134 If Sequent compatibility has been configured into the assembler then 15135the `|' character appearing as the first character on a line will also 15136indicate the start of a line comment. 15137 15138 The `;' character can be used to separate statements on the same 15139line. 15140 15141 15142File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies 15143 151449.32 PDP-11 Dependent Features 15145============================== 15146 15147* Menu: 15148 15149* PDP-11-Options:: Options 15150* PDP-11-Pseudos:: Assembler Directives 15151* PDP-11-Syntax:: DEC Syntax versus BSD Syntax 15152* PDP-11-Mnemonics:: Instruction Naming 15153* PDP-11-Synthetic:: Synthetic Instructions 15154 15155 15156File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent 15157 151589.32.1 Options 15159-------------- 15160 15161The PDP-11 version of `as' has a rich set of machine dependent options. 15162 151639.32.1.1 Code Generation Options 15164................................ 15165 15166`-mpic | -mno-pic' 15167 Generate position-independent (or position-dependent) code. 15168 15169 The default is to generate position-independent code. 15170 151719.32.1.2 Instruction Set Extension Options 15172.......................................... 15173 15174These options enables or disables the use of extensions over the base 15175line instruction set as introduced by the first PDP-11 CPU: the KA11. 15176Most options come in two variants: a `-m'EXTENSION that enables 15177EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION. 15178 15179 The default is to enable all extensions. 15180 15181`-mall | -mall-extensions' 15182 Enable all instruction set extensions. 15183 15184`-mno-extensions' 15185 Disable all instruction set extensions. 15186 15187`-mcis | -mno-cis' 15188 Enable (or disable) the use of the commercial instruction set, 15189 which consists of these instructions: `ADDNI', `ADDN', `ADDPI', 15190 `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC', 15191 `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI', 15192 `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL', 15193 `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI', 15194 `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC', 15195 `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI', 15196 `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'. 15197 15198`-mcsm | -mno-csm' 15199 Enable (or disable) the use of the `CSM' instruction. 15200 15201`-meis | -mno-eis' 15202 Enable (or disable) the use of the extended instruction set, which 15203 consists of these instructions: `ASHC', `ASH', `DIV', `MARK', 15204 `MUL', `RTT', `SOB' `SXT', and `XOR'. 15205 15206`-mfis | -mkev11' 15207`-mno-fis | -mno-kev11' 15208 Enable (or disable) the use of the KEV11 floating-point 15209 instructions: `FADD', `FDIV', `FMUL', and `FSUB'. 15210 15211`-mfpp | -mfpu | -mfp-11' 15212`-mno-fpp | -mno-fpu | -mno-fp-11' 15213 Enable (or disable) the use of FP-11 floating-point instructions: 15214 `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF', 15215 `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF', 15216 `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST', 15217 `SUBF', and `TSTF'. 15218 15219`-mlimited-eis | -mno-limited-eis' 15220 Enable (or disable) the use of the limited extended instruction 15221 set: `MARK', `RTT', `SOB', `SXT', and `XOR'. 15222 15223 The -mno-limited-eis options also implies -mno-eis. 15224 15225`-mmfpt | -mno-mfpt' 15226 Enable (or disable) the use of the `MFPT' instruction. 15227 15228`-mmultiproc | -mno-multiproc' 15229 Enable (or disable) the use of multiprocessor instructions: 15230 `TSTSET' and `WRTLCK'. 15231 15232`-mmxps | -mno-mxps' 15233 Enable (or disable) the use of the `MFPS' and `MTPS' instructions. 15234 15235`-mspl | -mno-spl' 15236 Enable (or disable) the use of the `SPL' instruction. 15237 15238 Enable (or disable) the use of the microcode instructions: `LDUB', 15239 `MED', and `XFC'. 15240 152419.32.1.3 CPU Model Options 15242.......................... 15243 15244These options enable the instruction set extensions supported by a 15245particular CPU, and disables all other extensions. 15246 15247`-mka11' 15248 KA11 CPU. Base line instruction set only. 15249 15250`-mkb11' 15251 KB11 CPU. Enable extended instruction set and `SPL'. 15252 15253`-mkd11a' 15254 KD11-A CPU. Enable limited extended instruction set. 15255 15256`-mkd11b' 15257 KD11-B CPU. Base line instruction set only. 15258 15259`-mkd11d' 15260 KD11-D CPU. Base line instruction set only. 15261 15262`-mkd11e' 15263 KD11-E CPU. Enable extended instruction set, `MFPS', and `MTPS'. 15264 15265`-mkd11f | -mkd11h | -mkd11q' 15266 KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended 15267 instruction set, `MFPS', and `MTPS'. 15268 15269`-mkd11k' 15270 KD11-K CPU. Enable extended instruction set, `LDUB', `MED', 15271 `MFPS', `MFPT', `MTPS', and `XFC'. 15272 15273`-mkd11z' 15274 KD11-Z CPU. Enable extended instruction set, `CSM', `MFPS', 15275 `MFPT', `MTPS', and `SPL'. 15276 15277`-mf11' 15278 F11 CPU. Enable extended instruction set, `MFPS', `MFPT', and 15279 `MTPS'. 15280 15281`-mj11' 15282 J11 CPU. Enable extended instruction set, `CSM', `MFPS', `MFPT', 15283 `MTPS', `SPL', `TSTSET', and `WRTLCK'. 15284 15285`-mt11' 15286 T11 CPU. Enable limited extended instruction set, `MFPS', and 15287 `MTPS'. 15288 152899.32.1.4 Machine Model Options 15290.............................. 15291 15292These options enable the instruction set extensions supported by a 15293particular machine model, and disables all other extensions. 15294 15295`-m11/03' 15296 Same as `-mkd11f'. 15297 15298`-m11/04' 15299 Same as `-mkd11d'. 15300 15301`-m11/05 | -m11/10' 15302 Same as `-mkd11b'. 15303 15304`-m11/15 | -m11/20' 15305 Same as `-mka11'. 15306 15307`-m11/21' 15308 Same as `-mt11'. 15309 15310`-m11/23 | -m11/24' 15311 Same as `-mf11'. 15312 15313`-m11/34' 15314 Same as `-mkd11e'. 15315 15316`-m11/34a' 15317 Ame as `-mkd11e' `-mfpp'. 15318 15319`-m11/35 | -m11/40' 15320 Same as `-mkd11a'. 15321 15322`-m11/44' 15323 Same as `-mkd11z'. 15324 15325`-m11/45 | -m11/50 | -m11/55 | -m11/70' 15326 Same as `-mkb11'. 15327 15328`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94' 15329 Same as `-mj11'. 15330 15331`-m11/60' 15332 Same as `-mkd11k'. 15333 15334 15335File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent 15336 153379.32.2 Assembler Directives 15338--------------------------- 15339 15340The PDP-11 version of `as' has a few machine dependent assembler 15341directives. 15342 15343`.bss' 15344 Switch to the `bss' section. 15345 15346`.even' 15347 Align the location counter to an even number. 15348 15349 15350File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent 15351 153529.32.3 PDP-11 Assembly Language Syntax 15353-------------------------------------- 15354 15355`as' supports both DEC syntax and BSD syntax. The only difference is 15356that in DEC syntax, a `#' character is used to denote an immediate 15357constants, while in BSD syntax the character for this purpose is `$'. 15358 15359 general-purpose registers are named `r0' through `r7'. Mnemonic 15360alternatives for `r6' and `r7' are `sp' and `pc', respectively. 15361 15362 Floating-point registers are named `ac0' through `ac3', or 15363alternatively `fr0' through `fr3'. 15364 15365 Comments are started with a `#' or a `/' character, and extend to 15366the end of the line. (FIXME: clash with immediates?) 15367 15368 Multiple statements on the same line can be separated by the `;' 15369character. 15370 15371 15372File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent 15373 153749.32.4 Instruction Naming 15375------------------------- 15376 15377Some instructions have alternative names. 15378 15379`BCC' 15380 `BHIS' 15381 15382`BCS' 15383 `BLO' 15384 15385`L2DR' 15386 `L2D' 15387 15388`L3DR' 15389 `L3D' 15390 15391`SYS' 15392 `TRAP' 15393 15394 15395File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent 15396 153979.32.5 Synthetic Instructions 15398----------------------------- 15399 15400The `JBR' and `J'CC synthetic instructions are not supported yet. 15401 15402 15403File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies 15404 154059.33 picoJava Dependent Features 15406================================ 15407 15408* Menu: 15409 15410* PJ Options:: Options 15411* PJ Syntax:: PJ Syntax 15412 15413 15414File: as.info, Node: PJ Options, Next: PJ Syntax, Up: PJ-Dependent 15415 154169.33.1 Options 15417-------------- 15418 15419`as' has two additional command-line options for the picoJava 15420architecture. 15421`-ml' 15422 This option selects little endian data output. 15423 15424`-mb' 15425 This option selects big endian data output. 15426 15427 15428File: as.info, Node: PJ Syntax, Prev: PJ Options, Up: PJ-Dependent 15429 154309.33.2 PJ Syntax 15431---------------- 15432 15433* Menu: 15434 15435* PJ-Chars:: Special Characters 15436 15437 15438File: as.info, Node: PJ-Chars, Up: PJ Syntax 15439 154409.33.2.1 Special Characters 15441........................... 15442 15443The presence of a `!' or `/' on a line indicates the start of a comment 15444that extends to the end of the current line. 15445 15446 If a `#' appears as the first character of a line then the whole 15447line is treated as a comment, but in this case the line could also be a 15448logical line number directive (*note Comments::) or a preprocessor 15449control command (*note Preprocessing::). 15450 15451 The `;' character can be used to separate statements on the same 15452line. 15453 15454 15455File: as.info, Node: PPC-Dependent, Next: RL78-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies 15456 154579.34 PowerPC Dependent Features 15458=============================== 15459 15460* Menu: 15461 15462* PowerPC-Opts:: Options 15463* PowerPC-Pseudo:: PowerPC Assembler Directives 15464* PowerPC-Syntax:: PowerPC Syntax 15465 15466 15467File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent 15468 154699.34.1 Options 15470-------------- 15471 15472The PowerPC chip family includes several successive levels, using the 15473same core instruction set, but including a few additional instructions 15474at each level. There are exceptions to this however. For details on 15475what instructions each variant supports, please see the chip's 15476architecture reference manual. 15477 15478 The following table lists all available PowerPC options. 15479 15480`-a32' 15481 Generate ELF32 or XCOFF32. 15482 15483`-a64' 15484 Generate ELF64 or XCOFF64. 15485 15486`-K PIC' 15487 Set EF_PPC_RELOCATABLE_LIB in ELF flags. 15488 15489`-mpwrx | -mpwr2' 15490 Generate code for POWER/2 (RIOS2). 15491 15492`-mpwr' 15493 Generate code for POWER (RIOS1) 15494 15495`-m601' 15496 Generate code for PowerPC 601. 15497 15498`-mppc, -mppc32, -m603, -m604' 15499 Generate code for PowerPC 603/604. 15500 15501`-m403, -m405' 15502 Generate code for PowerPC 403/405. 15503 15504`-m440' 15505 Generate code for PowerPC 440. BookE and some 405 instructions. 15506 15507`-m464' 15508 Generate code for PowerPC 464. 15509 15510`-m476' 15511 Generate code for PowerPC 476. 15512 15513`-m7400, -m7410, -m7450, -m7455' 15514 Generate code for PowerPC 7400/7410/7450/7455. 15515 15516`-m750cl' 15517 Generate code for PowerPC 750CL. 15518 15519`-mppc64, -m620' 15520 Generate code for PowerPC 620/625/630. 15521 15522`-me500, -me500x2' 15523 Generate code for Motorola e500 core complex. 15524 15525`-me500mc' 15526 Generate code for Freescale e500mc core complex. 15527 15528`-me500mc64' 15529 Generate code for Freescale e500mc64 core complex. 15530 15531`-me5500' 15532 Generate code for Freescale e5500 core complex. 15533 15534`-me6500' 15535 Generate code for Freescale e6500 core complex. 15536 15537`-mspe' 15538 Generate code for Motorola SPE instructions. 15539 15540`-mtitan' 15541 Generate code for AppliedMicro Titan core complex. 15542 15543`-mppc64bridge' 15544 Generate code for PowerPC 64, including bridge insns. 15545 15546`-mbooke' 15547 Generate code for 32-bit BookE. 15548 15549`-ma2' 15550 Generate code for A2 architecture. 15551 15552`-me300' 15553 Generate code for PowerPC e300 family. 15554 15555`-maltivec' 15556 Generate code for processors with AltiVec instructions. 15557 15558`-mvle' 15559 Generate code for Freescale PowerPC VLE instructions. 15560 15561`-mvsx' 15562 Generate code for processors with Vector-Scalar (VSX) instructions. 15563 15564`-mhtm' 15565 Generate code for processors with Hardware Transactional Memory 15566 instructions. 15567 15568`-mpower4, -mpwr4' 15569 Generate code for Power4 architecture. 15570 15571`-mpower5, -mpwr5, -mpwr5x' 15572 Generate code for Power5 architecture. 15573 15574`-mpower6, -mpwr6' 15575 Generate code for Power6 architecture. 15576 15577`-mpower7, -mpwr7' 15578 Generate code for Power7 architecture. 15579 15580`-mpower8, -mpwr8' 15581 Generate code for Power8 architecture. 15582 15583`-mcell' 15584 15585`-mcell' 15586 Generate code for Cell Broadband Engine architecture. 15587 15588`-mcom' 15589 Generate code Power/PowerPC common instructions. 15590 15591`-many' 15592 Generate code for any architecture (PWR/PWRX/PPC). 15593 15594`-mregnames' 15595 Allow symbolic names for registers. 15596 15597`-mno-regnames' 15598 Do not allow symbolic names for registers. 15599 15600`-mrelocatable' 15601 Support for GCC's -mrelocatable option. 15602 15603`-mrelocatable-lib' 15604 Support for GCC's -mrelocatable-lib option. 15605 15606`-memb' 15607 Set PPC_EMB bit in ELF flags. 15608 15609`-mlittle, -mlittle-endian, -le' 15610 Generate code for a little endian machine. 15611 15612`-mbig, -mbig-endian, -be' 15613 Generate code for a big endian machine. 15614 15615`-msolaris' 15616 Generate code for Solaris. 15617 15618`-mno-solaris' 15619 Do not generate code for Solaris. 15620 15621`-nops=COUNT' 15622 If an alignment directive inserts more than COUNT nops, put a 15623 branch at the beginning to skip execution of the nops. 15624 15625 15626File: as.info, Node: PowerPC-Pseudo, Next: PowerPC-Syntax, Prev: PowerPC-Opts, Up: PPC-Dependent 15627 156289.34.2 PowerPC Assembler Directives 15629----------------------------------- 15630 15631A number of assembler directives are available for PowerPC. The 15632following table is far from complete. 15633 15634`.machine "string"' 15635 This directive allows you to change the machine for which code is 15636 generated. `"string"' may be any of the -m cpu selection options 15637 (without the -m) enclosed in double quotes, `"push"', or `"pop"'. 15638 `.machine "push"' saves the currently selected cpu, which may be 15639 restored with `.machine "pop"'. 15640 15641 15642File: as.info, Node: PowerPC-Syntax, Prev: PowerPC-Pseudo, Up: PPC-Dependent 15643 156449.34.3 PowerPC Syntax 15645--------------------- 15646 15647* Menu: 15648 15649* PowerPC-Chars:: Special Characters 15650 15651 15652File: as.info, Node: PowerPC-Chars, Up: PowerPC-Syntax 15653 156549.34.3.1 Special Characters 15655........................... 15656 15657The presence of a `#' on a line indicates the start of a comment that 15658extends to the end of the current line. 15659 15660 If a `#' appears as the first character of a line then the whole 15661line is treated as a comment, but in this case the line could also be a 15662logical line number directive (*note Comments::) or a preprocessor 15663control command (*note Preprocessing::). 15664 15665 If the assembler has been configured for the ppc-*-solaris* target 15666then the `!' character also acts as a line comment character. This can 15667be disabled via the `-mno-solaris' command line option. 15668 15669 The `;' character can be used to separate statements on the same 15670line. 15671 15672 15673File: as.info, Node: RL78-Dependent, Next: RX-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies 15674 156759.35 RL78 Dependent Features 15676============================ 15677 15678* Menu: 15679 15680* RL78-Opts:: RL78 Assembler Command Line Options 15681* RL78-Modifiers:: Symbolic Operand Modifiers 15682* RL78-Directives:: Assembler Directives 15683* RL78-Syntax:: Syntax 15684 15685 15686File: as.info, Node: RL78-Opts, Next: RL78-Modifiers, Up: RL78-Dependent 15687 156889.35.1 RL78 Options 15689------------------- 15690 15691`relax' 15692 Enable support for link-time relaxation. 15693 15694`mg10' 15695 Mark the generated binary as targeting the G10 variant of the RL78 15696 architecture. 15697 15698 15699 15700File: as.info, Node: RL78-Modifiers, Next: RL78-Directives, Prev: RL78-Opts, Up: RL78-Dependent 15701 157029.35.2 Symbolic Operand Modifiers 15703--------------------------------- 15704 15705The RL78 has three modifiers that adjust the relocations used by the 15706linker: 15707 15708`%lo16()' 15709 When loading a 20-bit (or wider) address into registers, this 15710 modifier selects the 16 least significant bits. 15711 15712 movw ax,#%lo16(_sym) 15713 15714`%hi16()' 15715 When loading a 20-bit (or wider) address into registers, this 15716 modifier selects the 16 most significant bits. 15717 15718 movw ax,#%hi16(_sym) 15719 15720`%hi8()' 15721 When loading a 20-bit (or wider) address into registers, this 15722 modifier selects the 8 bits that would go into CS or ES (i.e. bits 15723 23..16). 15724 15725 mov es, #%hi8(_sym) 15726 15727 15728 15729File: as.info, Node: RL78-Directives, Next: RL78-Syntax, Prev: RL78-Modifiers, Up: RL78-Dependent 15730 157319.35.3 Assembler Directives 15732--------------------------- 15733 15734In addition to the common directives, the RL78 adds these: 15735 15736`.double' 15737 Output a constant in "double" format, which is a 32-bit floating 15738 point value on RL78. 15739 15740`.bss' 15741 Select the BSS section. 15742 15743`.3byte' 15744 Output a constant value in a three byte format. 15745 15746`.int' 15747`.word' 15748 Output a constant value in a four byte format. 15749 15750 15751 15752File: as.info, Node: RL78-Syntax, Prev: RL78-Directives, Up: RL78-Dependent 15753 157549.35.4 Syntax for the RL78 15755-------------------------- 15756 15757* Menu: 15758 15759* RL78-Chars:: Special Characters 15760 15761 15762File: as.info, Node: RL78-Chars, Up: RL78-Syntax 15763 157649.35.4.1 Special Characters 15765........................... 15766 15767The presence of a `;' appearing anywhere on a line indicates the start 15768of a comment that extends to the end of that line. 15769 15770 If a `#' appears as the first character of a line then the whole 15771line is treated as a comment, but in this case the line can also be a 15772logical line number directive (*note Comments::) or a preprocessor 15773control command (*note Preprocessing::). 15774 15775 The `|' character can be used to separate statements on the same 15776line. 15777 15778 15779File: as.info, Node: RX-Dependent, Next: S/390-Dependent, Prev: RL78-Dependent, Up: Machine Dependencies 15780 157819.36 RX Dependent Features 15782========================== 15783 15784* Menu: 15785 15786* RX-Opts:: RX Assembler Command Line Options 15787* RX-Modifiers:: Symbolic Operand Modifiers 15788* RX-Directives:: Assembler Directives 15789* RX-Float:: Floating Point 15790* RX-Syntax:: Syntax 15791 15792 15793File: as.info, Node: RX-Opts, Next: RX-Modifiers, Up: RX-Dependent 15794 157959.36.1 RX Options 15796----------------- 15797 15798The Renesas RX port of `as' has a few target specfic command line 15799options: 15800 15801`-m32bit-doubles' 15802 This option controls the ABI and indicates to use a 32-bit float 15803 ABI. It has no effect on the assembled instructions, but it does 15804 influence the behaviour of the `.double' pseudo-op. This is the 15805 default. 15806 15807`-m64bit-doubles' 15808 This option controls the ABI and indicates to use a 64-bit float 15809 ABI. It has no effect on the assembled instructions, but it does 15810 influence the behaviour of the `.double' pseudo-op. 15811 15812`-mbig-endian' 15813 This option controls the ABI and indicates to use a big-endian data 15814 ABI. It has no effect on the assembled instructions, but it does 15815 influence the behaviour of the `.short', `.hword', `.int', 15816 `.word', `.long', `.quad' and `.octa' pseudo-ops. 15817 15818`-mlittle-endian' 15819 This option controls the ABI and indicates to use a little-endian 15820 data ABI. It has no effect on the assembled instructions, but it 15821 does influence the behaviour of the `.short', `.hword', `.int', 15822 `.word', `.long', `.quad' and `.octa' pseudo-ops. This is the 15823 default. 15824 15825`-muse-conventional-section-names' 15826 This option controls the default names given to the code (.text), 15827 initialised data (.data) and uninitialised data sections (.bss). 15828 15829`-muse-renesas-section-names' 15830 This option controls the default names given to the code (.P), 15831 initialised data (.D_1) and uninitialised data sections (.B_1). 15832 This is the default. 15833 15834`-msmall-data-limit' 15835 This option tells the assembler that the small data limit feature 15836 of the RX port of GCC is being used. This results in the assembler 15837 generating an undefined reference to a symbol called `__gp' for 15838 use by the relocations that are needed to support the small data 15839 limit feature. This option is not enabled by default as it would 15840 otherwise pollute the symbol table. 15841 15842`-mpid' 15843 This option tells the assembler that the position independent data 15844 of the RX port of GCC is being used. This results in the assembler 15845 generating an undefined reference to a symbol called `__pid_base', 15846 and also setting the RX_PID flag bit in the e_flags field of the 15847 ELF header of the object file. 15848 15849`-mint-register=NUM' 15850 This option tells the assembler how many registers have been 15851 reserved for use by interrupt handlers. This is needed in order 15852 to compute the correct values for the `%gpreg' and `%pidreg' meta 15853 registers. 15854 15855`-mgcc-abi' 15856 This option tells the assembler that the old GCC ABI is being used 15857 by the assembled code. With this version of the ABI function 15858 arguments that are passed on the stack are aligned to a 32-bit 15859 boundary. 15860 15861`-mrx-abi' 15862 This option tells the assembler that the official RX ABI is being 15863 used by the assembled code. With this version of the ABI function 15864 arguments that are passed on the stack are aligned to their natural 15865 alignments. This option is the default. 15866 15867`-mcpu=NAME' 15868 This option tells the assembler the target CPU type. Currently the 15869 `rx200', `rx600' and `rx610' are recognised as valid cpu names. 15870 Attempting to assemble an instruction not supported by the 15871 indicated cpu type will result in an error message being generated. 15872 15873 15874 15875File: as.info, Node: RX-Modifiers, Next: RX-Directives, Prev: RX-Opts, Up: RX-Dependent 15876 158779.36.2 Symbolic Operand Modifiers 15878--------------------------------- 15879 15880The assembler supports one modifier when using symbol addresses in RX 15881instruction operands. The general syntax is the following: 15882 15883 %gp(symbol) 15884 15885 The modifier returns the offset from the __GP symbol to the 15886specified symbol as a 16-bit value. The intent is that this offset 15887should be used in a register+offset move instruction when generating 15888references to small data. Ie, like this: 15889 15890 mov.W %gp(_foo)[%gpreg], r1 15891 15892 The assembler also supports two meta register names which can be used 15893to refer to registers whose values may not be known to the programmer. 15894These meta register names are: 15895 15896`%gpreg' 15897 The small data address register. 15898 15899`%pidreg' 15900 The PID base address register. 15901 15902 15903 Both registers normally have the value r13, but this can change if 15904some registers have been reserved for use by interrupt handlers or if 15905both the small data limit and position independent data features are 15906being used at the same time. 15907 15908 15909File: as.info, Node: RX-Directives, Next: RX-Float, Prev: RX-Modifiers, Up: RX-Dependent 15910 159119.36.3 Assembler Directives 15912--------------------------- 15913 15914The RX version of `as' has the following specific assembler directives: 15915 15916`.3byte' 15917 Inserts a 3-byte value into the output file at the current 15918 location. 15919 15920`.fetchalign' 15921 If the next opcode following this directive spans a fetch line 15922 boundary (8 byte boundary), the opcode is aligned to that boundary. 15923 If the next opcode does not span a fetch line, this directive has 15924 no effect. Note that one or more labels may be between this 15925 directive and the opcode; those labels are aligned as well. Any 15926 inserted bytes due to alignment will form a NOP opcode. 15927 15928 15929 15930File: as.info, Node: RX-Float, Next: RX-Syntax, Prev: RX-Directives, Up: RX-Dependent 15931 159329.36.4 Floating Point 15933--------------------- 15934 15935The floating point formats generated by directives are these. 15936 15937`.float' 15938 `Single' precision (32-bit) floating point constants. 15939 15940`.double' 15941 If the `-m64bit-doubles' command line option has been specified 15942 then then `double' directive generates `double' precision (64-bit) 15943 floating point constants, otherwise it generates `single' 15944 precision (32-bit) floating point constants. To force the 15945 generation of 64-bit floating point constants used the `dc.d' 15946 directive instead. 15947 15948 15949 15950File: as.info, Node: RX-Syntax, Prev: RX-Float, Up: RX-Dependent 15951 159529.36.5 Syntax for the RX 15953------------------------ 15954 15955* Menu: 15956 15957* RX-Chars:: Special Characters 15958 15959 15960File: as.info, Node: RX-Chars, Up: RX-Syntax 15961 159629.36.5.1 Special Characters 15963........................... 15964 15965The presence of a `;' appearing anywhere on a line indicates the start 15966of a comment that extends to the end of that line. 15967 15968 If a `#' appears as the first character of a line then the whole 15969line is treated as a comment, but in this case the line can also be a 15970logical line number directive (*note Comments::) or a preprocessor 15971control command (*note Preprocessing::). 15972 15973 The `!' character can be used to separate statements on the same 15974line. 15975 15976 15977File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: RX-Dependent, Up: Machine Dependencies 15978 159799.37 IBM S/390 Dependent Features 15980================================= 15981 15982 The s390 version of `as' supports two architectures modes and seven 15983chip levels. The architecture modes are the Enterprise System 15984Architecture (ESA) and the newer z/Architecture mode. The chip levels 15985are g5, g6, z900, z990, z9-109, z9-ec, z10, z196, and zEC12. 15986 15987* Menu: 15988 15989* s390 Options:: Command-line Options. 15990* s390 Characters:: Special Characters. 15991* s390 Syntax:: Assembler Instruction syntax. 15992* s390 Directives:: Assembler Directives. 15993* s390 Floating Point:: Floating Point. 15994 15995 15996File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent 15997 159989.37.1 Options 15999-------------- 16000 16001The following table lists all available s390 specific options: 16002 16003`-m31 | -m64' 16004 Select 31- or 64-bit ABI implying a word size of 32- or 64-bit. 16005 16006 These options are only available with the ELF object file format, 16007 and require that the necessary BFD support has been included (on a 16008 31-bit platform you must add -enable-64-bit-bfd on the call to the 16009 configure script to enable 64-bit usage and use s390x as target 16010 platform). 16011 16012`-mesa | -mzarch' 16013 Select the architecture mode, either the Enterprise System 16014 Architecture (esa) mode or the z/Architecture mode (zarch). 16015 16016 The 64-bit instructions are only available with the z/Architecture 16017 mode. The combination of `-m64' and `-mesa' results in a warning 16018 message. 16019 16020`-march=CPU' 16021 This option specifies the target processor. The following 16022 processor names are recognized: `g5', `g6', `z900', `z990', 16023 `z9-109', `z9-ec', `z10' and `z196'. Assembling an instruction 16024 that is not supported on the target processor results in an error 16025 message. Do not specify `g5' or `g6' with `-mzarch'. 16026 16027`-mregnames' 16028 Allow symbolic names for registers. 16029 16030`-mno-regnames' 16031 Do not allow symbolic names for registers. 16032 16033`-mwarn-areg-zero' 16034 Warn whenever the operand for a base or index register has been 16035 specified but evaluates to zero. This can indicate the misuse of 16036 general purpose register 0 as an address register. 16037 16038 16039 16040File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent 16041 160429.37.2 Special Characters 16043------------------------- 16044 16045`#' is the line comment character. 16046 16047 If a `#' appears as the first character of a line then the whole 16048line is treated as a comment, but in this case the line could also be a 16049logical line number directive (*note Comments::) or a preprocessor 16050control command (*note Preprocessing::). 16051 16052 The `;' character can be used instead of a newline to separate 16053statements. 16054 16055 16056File: as.info, Node: s390 Syntax, Next: s390 Directives, Prev: s390 Characters, Up: S/390-Dependent 16057 160589.37.3 Instruction syntax 16059------------------------- 16060 16061The assembler syntax closely follows the syntax outlined in Enterprise 16062Systems Architecture/390 Principles of Operation (SA22-7201) and the 16063z/Architecture Principles of Operation (SA22-7832). 16064 16065 Each instruction has two major parts, the instruction mnemonic and 16066the instruction operands. The instruction format varies. 16067 16068* Menu: 16069 16070* s390 Register:: Register Naming 16071* s390 Mnemonics:: Instruction Mnemonics 16072* s390 Operands:: Instruction Operands 16073* s390 Formats:: Instruction Formats 16074* s390 Aliases:: Instruction Aliases 16075* s390 Operand Modifier:: Instruction Operand Modifier 16076* s390 Instruction Marker:: Instruction Marker 16077* s390 Literal Pool Entries:: Literal Pool Entries 16078 16079 16080File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax 16081 160829.37.3.1 Register naming 16083........................ 16084 16085The `as' recognizes a number of predefined symbols for the various 16086processor registers. A register specification in one of the instruction 16087formats is an unsigned integer between 0 and 15. The specific 16088instruction and the position of the register in the instruction format 16089denotes the type of the register. The register symbols are prefixed with 16090`%': 16091 16092 %rN the 16 general purpose registers, 0 <= N <= 15 16093 %fN the 16 floating point registers, 0 <= N <= 15 16094 %aN the 16 access registers, 0 <= N <= 15 16095 %cN the 16 control registers, 0 <= N <= 15 16096 %lit an alias for the general purpose register %r13 16097 %sp an alias for the general purpose register %r15 16098 16099 16100File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register, Up: s390 Syntax 16101 161029.37.3.2 Instruction Mnemonics 16103.............................. 16104 16105All instructions documented in the Principles of Operation are supported 16106with the mnemonic and order of operands as described. The instruction 16107mnemonic identifies the instruction format (*note s390 Formats::) and 16108the specific operation code for the instruction. For example, the `lr' 16109mnemonic denotes the instruction format `RR' with the operation code 16110`0x18'. 16111 16112 The definition of the various mnemonics follows a scheme, where the 16113first character usually hint at the type of the instruction: 16114 16115 a add instruction, for example `al' for add logical 32-bit 16116 b branch instruction, for example `bc' for branch on condition 16117 c compare or convert instruction, for example `cr' for compare 16118 register 32-bit 16119 d divide instruction, for example `dlr' devide logical register 16120 64-bit to 32-bit 16121 i insert instruction, for example `ic' insert character 16122 l load instruction, for example `ltr' load and test register 16123 mv move instruction, for example `mvc' move character 16124 m multiply instruction, for example `mh' multiply halfword 16125 n and instruction, for example `ni' and immediate 16126 o or instruction, for example `oc' or character 16127 sla, sll shift left single instruction 16128 sra, srl shift right single instruction 16129 st store instruction, for example `stm' store multiple 16130 s subtract instruction, for example `slr' subtract 16131 logical 32-bit 16132 t test or translate instruction, of example `tm' test under mask 16133 x exclusive or instruction, for example `xc' exclusive or 16134 character 16135 16136 Certain characters at the end of the mnemonic may describe a property 16137of the instruction: 16138 16139 c the instruction uses a 8-bit character operand 16140 f the instruction extends a 32-bit operand to 64 bit 16141 g the operands are treated as 64-bit values 16142 h the operand uses a 16-bit halfword operand 16143 i the instruction uses an immediate operand 16144 l the instruction uses unsigned, logical operands 16145 m the instruction uses a mask or operates on multiple values 16146 r if r is the last character, the instruction operates on registers 16147 y the instruction uses 20-bit displacements 16148 16149 There are many exceptions to the scheme outlined in the above lists, 16150in particular for the priviledged instructions. For non-priviledged 16151instruction it works quite well, for example the instruction `clgfr' c: 16152compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- 16153to 64-bit extension, r: register operands. The instruction compares an 1615464-bit value in a register with the zero extended 32-bit value from a 16155second register. For a complete list of all mnemonics see appendix B 16156in the Principles of Operation. 16157 16158 16159File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax 16160 161619.37.3.3 Instruction Operands 16162............................. 16163 16164Instruction operands can be grouped into three classes, operands located 16165in registers, immediate operands, and operands in storage. 16166 16167 A register operand can be located in general, floating-point, access, 16168or control register. The register is identified by a four-bit field. 16169The field containing the register operand is called the R field. 16170 16171 Immediate operands are contained within the instruction and can have 161728, 16 or 32 bits. The field containing the immediate operand is called 16173the I field. Dependent on the instruction the I field is either signed 16174or unsigned. 16175 16176 A storage operand consists of an address and a length. The address 16177of a storage operands can be specified in any of these ways: 16178 16179 * The content of a single general R 16180 16181 * The sum of the content of a general register called the base 16182 register B plus the content of a displacement field D 16183 16184 * The sum of the contents of two general registers called the index 16185 register X and the base register B plus the content of a 16186 displacement field 16187 16188 * The sum of the current instruction address and a 32-bit signed 16189 immediate field multiplied by two. 16190 16191 The length of a storage operand can be: 16192 16193 * Implied by the instruction 16194 16195 * Specified by a bitmask 16196 16197 * Specified by a four-bit or eight-bit length field L 16198 16199 * Specified by the content of a general register 16200 16201 The notation for storage operand addresses formed from multiple 16202fields is as follows: 16203 16204`Dn(Bn)' 16205 the address for operand number n is formed from the content of 16206 general register Bn called the base register and the displacement 16207 field Dn. 16208 16209`Dn(Xn,Bn)' 16210 the address for operand number n is formed from the content of 16211 general register Xn called the index register, general register Bn 16212 called the base register and the displacement field Dn. 16213 16214`Dn(Ln,Bn)' 16215 the address for operand number n is formed from the content of 16216 general regiser Bn called the base register and the displacement 16217 field Dn. The length of the operand n is specified by the field 16218 Ln. 16219 16220 The base registers Bn and the index registers Xn of a storage 16221operand can be skipped. If Bn and Xn are skipped, a zero will be stored 16222to the operand field. The notation changes as follows: 16223 16224 full notation short notation 16225 ------------------------------------------ 16226 Dn(0,Bn) Dn(Bn) 16227 Dn(0,0) Dn 16228 Dn(0) Dn 16229 Dn(Ln,0) Dn(Ln) 16230 16231 16232File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax 16233 162349.37.3.4 Instruction Formats 16235............................ 16236 16237The Principles of Operation manuals lists 26 instruction formats where 16238some of the formats have multiple variants. For the `.insn' pseudo 16239directive the assembler recognizes some of the formats. Typically, the 16240most general variant of the instruction format is used by the `.insn' 16241directive. 16242 16243 The following table lists the abbreviations used in the table of 16244instruction formats: 16245 16246 OpCode / OpCd Part of the op code. 16247 Bx Base register number for operand x. 16248 Dx Displacement for operand x. 16249 DLx Displacement lower 12 bits for operand x. 16250 DHx Displacement higher 8-bits for operand x. 16251 Rx Register number for operand x. 16252 Xx Index register number for operand x. 16253 Ix Signed immediate for operand x. 16254 Ux Unsigned immediate for operand x. 16255 16256 An instruction is two, four, or six bytes in length and must be 16257aligned on a 2 byte boundary. The first two bits of the instruction 16258specify the length of the instruction, 00 indicates a two byte 16259instruction, 01 and 10 indicates a four byte instruction, and 11 16260indicates a six byte instruction. 16261 16262 The following table lists the s390 instruction formats that are 16263available with the `.insn' pseudo directive: 16264 16265`E format' 16266 +-------------+ 16267 | OpCode | 16268 +-------------+ 16269 0 15 16270 16271`RI format: <insn> R1,I2' 16272 +--------+----+----+------------------+ 16273 | OpCode | R1 |OpCd| I2 | 16274 +--------+----+----+------------------+ 16275 0 8 12 16 31 16276 16277`RIE format: <insn> R1,R3,I2' 16278 +--------+----+----+------------------+--------+--------+ 16279 | OpCode | R1 | R3 | I2 |////////| OpCode | 16280 +--------+----+----+------------------+--------+--------+ 16281 0 8 12 16 32 40 47 16282 16283`RIL format: <insn> R1,I2' 16284 +--------+----+----+------------------------------------+ 16285 | OpCode | R1 |OpCd| I2 | 16286 +--------+----+----+------------------------------------+ 16287 0 8 12 16 47 16288 16289`RILU format: <insn> R1,U2' 16290 +--------+----+----+------------------------------------+ 16291 | OpCode | R1 |OpCd| U2 | 16292 +--------+----+----+------------------------------------+ 16293 0 8 12 16 47 16294 16295`RIS format: <insn> R1,I2,M3,D4(B4)' 16296 +--------+----+----+----+-------------+--------+--------+ 16297 | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | 16298 +--------+----+----+----+-------------+--------+--------+ 16299 0 8 12 16 20 32 36 47 16300 16301`RR format: <insn> R1,R2' 16302 +--------+----+----+ 16303 | OpCode | R1 | R2 | 16304 +--------+----+----+ 16305 0 8 12 15 16306 16307`RRE format: <insn> R1,R2' 16308 +------------------+--------+----+----+ 16309 | OpCode |////////| R1 | R2 | 16310 +------------------+--------+----+----+ 16311 0 16 24 28 31 16312 16313`RRF format: <insn> R1,R2,R3,M4' 16314 +------------------+----+----+----+----+ 16315 | OpCode | R3 | M4 | R1 | R2 | 16316 +------------------+----+----+----+----+ 16317 0 16 20 24 28 31 16318 16319`RRS format: <insn> R1,R2,M3,D4(B4)' 16320 +--------+----+----+----+-------------+----+----+--------+ 16321 | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | 16322 +--------+----+----+----+-------------+----+----+--------+ 16323 0 8 12 16 20 32 36 40 47 16324 16325`RS format: <insn> R1,R3,D2(B2)' 16326 +--------+----+----+----+-------------+ 16327 | OpCode | R1 | R3 | B2 | D2 | 16328 +--------+----+----+----+-------------+ 16329 0 8 12 16 20 31 16330 16331`RSE format: <insn> R1,R3,D2(B2)' 16332 +--------+----+----+----+-------------+--------+--------+ 16333 | OpCode | R1 | R3 | B2 | D2 |////////| OpCode | 16334 +--------+----+----+----+-------------+--------+--------+ 16335 0 8 12 16 20 32 40 47 16336 16337`RSI format: <insn> R1,R3,I2' 16338 +--------+----+----+------------------------------------+ 16339 | OpCode | R1 | R3 | I2 | 16340 +--------+----+----+------------------------------------+ 16341 0 8 12 16 47 16342 16343`RSY format: <insn> R1,R3,D2(B2)' 16344 +--------+----+----+----+-------------+--------+--------+ 16345 | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | 16346 +--------+----+----+----+-------------+--------+--------+ 16347 0 8 12 16 20 32 40 47 16348 16349`RX format: <insn> R1,D2(X2,B2)' 16350 +--------+----+----+----+-------------+ 16351 | OpCode | R1 | X2 | B2 | D2 | 16352 +--------+----+----+----+-------------+ 16353 0 8 12 16 20 31 16354 16355`RXE format: <insn> R1,D2(X2,B2)' 16356 +--------+----+----+----+-------------+--------+--------+ 16357 | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | 16358 +--------+----+----+----+-------------+--------+--------+ 16359 0 8 12 16 20 32 40 47 16360 16361`RXF format: <insn> R1,R3,D2(X2,B2)' 16362 +--------+----+----+----+-------------+----+---+--------+ 16363 | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | 16364 +--------+----+----+----+-------------+----+---+--------+ 16365 0 8 12 16 20 32 36 40 47 16366 16367`RXY format: <insn> R1,D2(X2,B2)' 16368 +--------+----+----+----+-------------+--------+--------+ 16369 | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | 16370 +--------+----+----+----+-------------+--------+--------+ 16371 0 8 12 16 20 32 36 40 47 16372 16373`S format: <insn> D2(B2)' 16374 +------------------+----+-------------+ 16375 | OpCode | B2 | D2 | 16376 +------------------+----+-------------+ 16377 0 16 20 31 16378 16379`SI format: <insn> D1(B1),I2' 16380 +--------+---------+----+-------------+ 16381 | OpCode | I2 | B1 | D1 | 16382 +--------+---------+----+-------------+ 16383 0 8 16 20 31 16384 16385`SIY format: <insn> D1(B1),U2' 16386 +--------+---------+----+-------------+--------+--------+ 16387 | OpCode | I2 | B1 | DL1 | DH1 | OpCode | 16388 +--------+---------+----+-------------+--------+--------+ 16389 0 8 16 20 32 36 40 47 16390 16391`SIL format: <insn> D1(B1),I2' 16392 +------------------+----+-------------+-----------------+ 16393 | OpCode | B1 | D1 | I2 | 16394 +------------------+----+-------------+-----------------+ 16395 0 16 20 32 47 16396 16397`SS format: <insn> D1(R1,B1),D2(B3),R3' 16398 +--------+----+----+----+-------------+----+------------+ 16399 | OpCode | R1 | R3 | B1 | D1 | B2 | D2 | 16400 +--------+----+----+----+-------------+----+------------+ 16401 0 8 12 16 20 32 36 47 16402 16403`SSE format: <insn> D1(B1),D2(B2)' 16404 +------------------+----+-------------+----+------------+ 16405 | OpCode | B1 | D1 | B2 | D2 | 16406 +------------------+----+-------------+----+------------+ 16407 0 8 12 16 20 32 36 47 16408 16409`SSF format: <insn> D1(B1),D2(B2),R3' 16410 +--------+----+----+----+-------------+----+------------+ 16411 | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | 16412 +--------+----+----+----+-------------+----+------------+ 16413 0 8 12 16 20 32 36 47 16414 16415 16416 For the complete list of all instruction format variants see the 16417Principles of Operation manuals. 16418 16419 16420File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Formats, Up: s390 Syntax 16421 164229.37.3.5 Instruction Aliases 16423............................ 16424 16425A specific bit pattern can have multiple mnemonics, for example the bit 16426pattern `0xa7000000' has the mnemonics `tmh' and `tmlh'. In addition, 16427there are a number of mnemonics recognized by `as' that are not present 16428in the Principles of Operation. These are the short forms of the 16429branch instructions, where the condition code mask operand is encoded 16430in the mnemonic. This is relevant for the branch instructions, the 16431compare and branch instructions, and the compare and trap instructions. 16432 16433 For the branch instructions there are 20 condition code strings that 16434can be used as part of the mnemonic in place of a mask operand in the 16435instruction format: 16436 16437 instruction short form 16438 ------------------------------------------ 16439 bcr M1,R2 b<m>r R2 16440 bc M1,D2(X2,B2) b<m> D2(X2,B2) 16441 brc M1,I2 j<m> I2 16442 brcl M1,I2 jg<m> I2 16443 16444 In the mnemonic for a branch instruction the condition code string 16445<m> can be any of the following: 16446 16447 o jump on overflow / if ones 16448 h jump on A high 16449 p jump on plus 16450 nle jump on not low or equal 16451 l jump on A low 16452 m jump on minus 16453 nhe jump on not high or equal 16454 lh jump on low or high 16455 ne jump on A not equal B 16456 nz jump on not zero / if not zeros 16457 e jump on A equal B 16458 z jump on zero / if zeroes 16459 nlh jump on not low or high 16460 he jump on high or equal 16461 nl jump on A not low 16462 nm jump on not minus / if not mixed 16463 le jump on low or equal 16464 nh jump on A not high 16465 np jump on not plus 16466 no jump on not overflow / if not ones 16467 16468 For the compare and branch, and compare and trap instructions there 16469are 12 condition code strings that can be used as part of the mnemonic 16470in place of a mask operand in the instruction format: 16471 16472 instruction short form 16473 -------------------------------------------------------- 16474 crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4) 16475 cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4) 16476 crj R1,R2,M3,I4 crj<m> R1,R2,I4 16477 cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4 16478 cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4) 16479 cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4) 16480 cij R1,I2,M3,I4 cij<m> R1,I2,I4 16481 cgij R1,I2,M3,I4 cgij<m> R1,I2,I4 16482 crt R1,R2,M3 crt<m> R1,R2 16483 cgrt R1,R2,M3 cgrt<m> R1,R2 16484 cit R1,I2,M3 cit<m> R1,I2 16485 cgit R1,I2,M3 cgit<m> R1,I2 16486 clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4) 16487 clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4) 16488 clrj R1,R2,M3,I4 clrj<m> R1,R2,I4 16489 clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4 16490 clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4) 16491 clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4) 16492 clij R1,I2,M3,I4 clij<m> R1,I2,I4 16493 clgij R1,I2,M3,I4 clgij<m> R1,I2,I4 16494 clrt R1,R2,M3 clrt<m> R1,R2 16495 clgrt R1,R2,M3 clgrt<m> R1,R2 16496 clfit R1,I2,M3 clfit<m> R1,I2 16497 clgit R1,I2,M3 clgit<m> R1,I2 16498 16499 In the mnemonic for a compare and branch and compare and trap 16500instruction the condition code string <m> can be any of the following: 16501 16502 h jump on A high 16503 nle jump on not low or equal 16504 l jump on A low 16505 nhe jump on not high or equal 16506 ne jump on A not equal B 16507 lh jump on low or high 16508 e jump on A equal B 16509 nlh jump on not low or high 16510 nl jump on A not low 16511 he jump on high or equal 16512 nh jump on A not high 16513 le jump on low or equal 16514 16515 16516File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Prev: s390 Aliases, Up: s390 Syntax 16517 165189.37.3.6 Instruction Operand Modifier 16519..................................... 16520 16521If a symbol modifier is attached to a symbol in an expression for an 16522instruction operand field, the symbol term is replaced with a reference 16523to an object in the global offset table (GOT) or the procedure linkage 16524table (PLT). The following expressions are allowed: `symbol@modifier + 16525constant', `symbol@modifier + label + constant', and `symbol@modifier - 16526label + constant'. The term `symbol' is the symbol that will be 16527entered into the GOT or PLT, `label' is a local label, and `constant' 16528is an arbitrary expression that the assembler can evaluate to a 16529constant value. 16530 16531 The term `(symbol + constant1)@modifier +/- label + constant2' is 16532also accepted but a warning message is printed and the term is 16533converted to `symbol@modifier +/- label + constant1 + constant2'. 16534 16535`@got' 16536`@got12' 16537 The @got modifier can be used for displacement fields, 16-bit 16538 immediate fields and 32-bit pc-relative immediate fields. The 16539 @got12 modifier is synonym to @got. The symbol is added to the 16540 GOT. For displacement fields and 16-bit immediate fields the 16541 symbol term is replaced with the offset from the start of the GOT 16542 to the GOT slot for the symbol. For a 32-bit pc-relative field 16543 the pc-relative offset to the GOT slot from the current 16544 instruction address is used. 16545 16546`@gotent' 16547 The @gotent modifier can be used for 32-bit pc-relative immediate 16548 fields. The symbol is added to the GOT and the symbol term is 16549 replaced with the pc-relative offset from the current instruction 16550 to the GOT slot for the symbol. 16551 16552`@gotoff' 16553 The @gotoff modifier can be used for 16-bit immediate fields. The 16554 symbol term is replaced with the offset from the start of the GOT 16555 to the address of the symbol. 16556 16557`@gotplt' 16558 The @gotplt modifier can be used for displacement fields, 16-bit 16559 immediate fields, and 32-bit pc-relative immediate fields. A 16560 procedure linkage table entry is generated for the symbol and a 16561 jump slot for the symbol is added to the GOT. For displacement 16562 fields and 16-bit immediate fields the symbol term is replaced 16563 with the offset from the start of the GOT to the jump slot for the 16564 symbol. For a 32-bit pc-relative field the pc-relative offset to 16565 the jump slot from the current instruction address is used. 16566 16567`@plt' 16568 The @plt modifier can be used for 16-bit and 32-bit pc-relative 16569 immediate fields. A procedure linkage table entry is generated for 16570 the symbol. The symbol term is replaced with the relative offset 16571 from the current instruction to the PLT entry for the symbol. 16572 16573`@pltoff' 16574 The @pltoff modifier can be used for 16-bit immediate fields. The 16575 symbol term is replaced with the offset from the start of the PLT 16576 to the address of the symbol. 16577 16578`@gotntpoff' 16579 The @gotntpoff modifier can be used for displacement fields. The 16580 symbol is added to the static TLS block and the negated offset to 16581 the symbol in the static TLS block is added to the GOT. The symbol 16582 term is replaced with the offset to the GOT slot from the start of 16583 the GOT. 16584 16585`@indntpoff' 16586 The @indntpoff modifier can be used for 32-bit pc-relative 16587 immediate fields. The symbol is added to the static TLS block and 16588 the negated offset to the symbol in the static TLS block is added 16589 to the GOT. The symbol term is replaced with the pc-relative 16590 offset to the GOT slot from the current instruction address. 16591 16592 For more information about the thread local storage modifiers 16593`gotntpoff' and `indntpoff' see the ELF extension documentation `ELF 16594Handling For Thread-Local Storage'. 16595 16596 16597File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, Prev: s390 Operand Modifier, Up: s390 Syntax 16598 165999.37.3.7 Instruction Marker 16600........................... 16601 16602The thread local storage instruction markers are used by the linker to 16603perform code optimization. 16604 16605`:tls_load' 16606 The :tls_load marker is used to flag the load instruction in the 16607 initial exec TLS model that retrieves the offset from the thread 16608 pointer to a thread local storage variable from the GOT. 16609 16610`:tls_gdcall' 16611 The :tls_gdcall marker is used to flag the branch-and-save 16612 instruction to the __tls_get_offset function in the global dynamic 16613 TLS model. 16614 16615`:tls_ldcall' 16616 The :tls_ldcall marker is used to flag the branch-and-save 16617 instruction to the __tls_get_offset function in the local dynamic 16618 TLS model. 16619 16620 For more information about the thread local storage instruction 16621marker and the linker optimizations see the ELF extension documentation 16622`ELF Handling For Thread-Local Storage'. 16623 16624 16625File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax 16626 166279.37.3.8 Literal Pool Entries 16628............................. 16629 16630A literal pool is a collection of values. To access the values a pointer 16631to the literal pool is loaded to a register, the literal pool register. 16632Usually, register %r13 is used as the literal pool register (*note s390 16633Register::). Literal pool entries are created by adding the suffix 16634:lit1, :lit2, :lit4, or :lit8 to the end of an expression for an 16635instruction operand. The expression is added to the literal pool and the 16636operand is replaced with the offset to the literal in the literal pool. 16637 16638`:lit1' 16639 The literal pool entry is created as an 8-bit value. An operand 16640 modifier must not be used for the original expression. 16641 16642`:lit2' 16643 The literal pool entry is created as a 16 bit value. The operand 16644 modifier @got may be used in the original expression. The term 16645 `x@got:lit2' will put the got offset for the global symbol x to 16646 the literal pool as 16 bit value. 16647 16648`:lit4' 16649 The literal pool entry is created as a 32-bit value. The operand 16650 modifier @got and @plt may be used in the original expression. The 16651 term `x@got:lit4' will put the got offset for the global symbol x 16652 to the literal pool as a 32-bit value. The term `x@plt:lit4' will 16653 put the plt offset for the global symbol x to the literal pool as 16654 a 32-bit value. 16655 16656`:lit8' 16657 The literal pool entry is created as a 64-bit value. The operand 16658 modifier @got and @plt may be used in the original expression. The 16659 term `x@got:lit8' will put the got offset for the global symbol x 16660 to the literal pool as a 64-bit value. The term `x@plt:lit8' will 16661 put the plt offset for the global symbol x to the literal pool as 16662 a 64-bit value. 16663 16664 The assembler directive `.ltorg' is used to emit all literal pool 16665entries to the current position. 16666 16667 16668File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 Syntax, Up: S/390-Dependent 16669 166709.37.4 Assembler Directives 16671--------------------------- 16672 16673`as' for s390 supports all of the standard ELF assembler directives as 16674outlined in the main part of this document. Some directives have been 16675extended and there are some additional directives, which are only 16676available for the s390 `as'. 16677 16678`.insn' 16679 This directive permits the numeric representation of an 16680 instructions and makes the assembler insert the operands according 16681 to one of the instructions formats for `.insn' (*note s390 16682 Formats::). For example, the instruction `l %r1,24(%r15)' could 16683 be written as `.insn rx,0x58000000,%r1,24(%r15)'. 16684 16685`.short' 16686`.long' 16687`.quad' 16688 This directive places one or more 16-bit (.short), 32-bit (.long), 16689 or 64-bit (.quad) values into the current section. If an ELF or 16690 TLS modifier is used only the following expressions are allowed: 16691 `symbol@modifier + constant', `symbol@modifier + label + 16692 constant', and `symbol@modifier - label + constant'. The 16693 following modifiers are available: 16694 `@got' 16695 `@got12' 16696 The @got modifier can be used for .short, .long and .quad. 16697 The @got12 modifier is synonym to @got. The symbol is added 16698 to the GOT. The symbol term is replaced with offset from the 16699 start of the GOT to the GOT slot for the symbol. 16700 16701 `@gotoff' 16702 The @gotoff modifier can be used for .short, .long and .quad. 16703 The symbol term is replaced with the offset from the start of 16704 the GOT to the address of the symbol. 16705 16706 `@gotplt' 16707 The @gotplt modifier can be used for .long and .quad. A 16708 procedure linkage table entry is generated for the symbol and 16709 a jump slot for the symbol is added to the GOT. The symbol 16710 term is replaced with the offset from the start of the GOT to 16711 the jump slot for the symbol. 16712 16713 `@plt' 16714 The @plt modifier can be used for .long and .quad. A 16715 procedure linkage table entry us generated for the symbol. 16716 The symbol term is replaced with the address of the PLT entry 16717 for the symbol. 16718 16719 `@pltoff' 16720 The @pltoff modifier can be used for .short, .long and .quad. 16721 The symbol term is replaced with the offset from the start of 16722 the PLT to the address of the symbol. 16723 16724 `@tlsgd' 16725 `@tlsldm' 16726 The @tlsgd and @tlsldm modifier can be used for .long and 16727 .quad. A tls_index structure for the symbol is added to the 16728 GOT. The symbol term is replaced with the offset from the 16729 start of the GOT to the tls_index structure. 16730 16731 `@gotntpoff' 16732 `@indntpoff' 16733 The @gotntpoff and @indntpoff modifier can be used for .long 16734 and .quad. The symbol is added to the static TLS block and 16735 the negated offset to the symbol in the static TLS block is 16736 added to the GOT. For @gotntpoff the symbol term is replaced 16737 with the offset from the start of the GOT to the GOT slot, 16738 for @indntpoff the symbol term is replaced with the address 16739 of the GOT slot. 16740 16741 `@dtpoff' 16742 The @dtpoff modifier can be used for .long and .quad. The 16743 symbol term is replaced with the offset of the symbol 16744 relative to the start of the TLS block it is contained in. 16745 16746 `@ntpoff' 16747 The @ntpoff modifier can be used for .long and .quad. The 16748 symbol term is replaced with the offset of the symbol 16749 relative to the TCB pointer. 16750 16751 For more information about the thread local storage modifiers see 16752 the ELF extension documentation `ELF Handling For Thread-Local 16753 Storage'. 16754 16755`.ltorg' 16756 This directive causes the current contents of the literal pool to 16757 be dumped to the current location (*note s390 Literal Pool 16758 Entries::). 16759 16760`.machine string' 16761 This directive allows you to change the machine for which code is 16762 generated. `string' may be any of the `-march=' selection options 16763 (without the -march=), `push', or `pop'. `.machine push' saves 16764 the currently selected cpu, which may be restored with `.machine 16765 pop'. Be aware that the cpu string has to be put into double 16766 quotes in case it contains characters not appropriate for 16767 identifiers. So you have to write `"z9-109"' instead of just 16768 `z9-109'. 16769 16770`.machinemode string' 16771 This directive allows to change the architecture mode for which 16772 code is being generated. `string' may be `esa', `zarch', 16773 `zarch_nohighgprs', `push', or `pop'. `.machinemode 16774 zarch_nohighgprs' can be used to prevent the `highgprs' flag from 16775 being set in the ELF header of the output file. This is useful in 16776 situations where the code is gated with a runtime check which 16777 makes sure that the code is only executed on kernels providing the 16778 `highgprs' feature. `.machinemode push' saves the currently 16779 selected mode, which may be restored with `.machinemode pop'. 16780 16781 16782File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent 16783 167849.37.5 Floating Point 16785--------------------- 16786 16787The assembler recognizes both the IEEE floating-point instruction and 16788the hexadecimal floating-point instructions. The floating-point 16789constructors `.float', `.single', and `.double' always emit the IEEE 16790format. To assemble hexadecimal floating-point constants the `.long' 16791and `.quad' directives must be used. 16792 16793 16794File: as.info, Node: SCORE-Dependent, Next: Sparc-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies 16795 167969.38 SCORE Dependent Features 16797============================= 16798 16799* Menu: 16800 16801* SCORE-Opts:: Assembler options 16802* SCORE-Pseudo:: SCORE Assembler Directives 16803* SCORE-Syntax:: Syntax 16804 16805 16806File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent 16807 168089.38.1 Options 16809-------------- 16810 16811The following table lists all available SCORE options. 16812 16813`-G NUM' 16814 This option sets the largest size of an object that can be 16815 referenced implicitly with the `gp' register. The default value is 16816 8. 16817 16818`-EB' 16819 Assemble code for a big-endian cpu 16820 16821`-EL' 16822 Assemble code for a little-endian cpu 16823 16824`-FIXDD' 16825 Assemble code for fix data dependency 16826 16827`-NWARN' 16828 Assemble code for no warning message for fix data dependency 16829 16830`-SCORE5' 16831 Assemble code for target is SCORE5 16832 16833`-SCORE5U' 16834 Assemble code for target is SCORE5U 16835 16836`-SCORE7' 16837 Assemble code for target is SCORE7, this is default setting 16838 16839`-SCORE3' 16840 Assemble code for target is SCORE3 16841 16842`-march=score7' 16843 Assemble code for target is SCORE7, this is default setting 16844 16845`-march=score3' 16846 Assemble code for target is SCORE3 16847 16848`-USE_R1' 16849 Assemble code for no warning message when using temp register r1 16850 16851`-KPIC' 16852 Generate code for PIC. This option tells the assembler to generate 16853 score position-independent macro expansions. It also tells the 16854 assembler to mark the output file as PIC. 16855 16856`-O0' 16857 Assembler will not perform any optimizations 16858 16859`-V' 16860 Sunplus release version 16861 16862 16863 16864File: as.info, Node: SCORE-Pseudo, Next: SCORE-Syntax, Prev: SCORE-Opts, Up: SCORE-Dependent 16865 168669.38.2 SCORE Assembler Directives 16867--------------------------------- 16868 16869A number of assembler directives are available for SCORE. The 16870following table is far from complete. 16871 16872`.set nwarn' 16873 Let the assembler not to generate warnings if the source machine 16874 language instructions happen data dependency. 16875 16876`.set fixdd' 16877 Let the assembler to insert bubbles (32 bit nop instruction / 16 16878 bit nop! Instruction) if the source machine language instructions 16879 happen data dependency. 16880 16881`.set nofixdd' 16882 Let the assembler to generate warnings if the source machine 16883 language instructions happen data dependency. (Default) 16884 16885`.set r1' 16886 Let the assembler not to generate warnings if the source program 16887 uses r1. allow user to use r1 16888 16889`set nor1' 16890 Let the assembler to generate warnings if the source program uses 16891 r1. (Default) 16892 16893`.sdata' 16894 Tell the assembler to add subsequent data into the sdata section 16895 16896`.rdata' 16897 Tell the assembler to add subsequent data into the rdata section 16898 16899`.frame "frame-register", "offset", "return-pc-register"' 16900 Describe a stack frame. "frame-register" is the frame register, 16901 "offset" is the distance from the frame register to the virtual 16902 frame pointer, "return-pc-register" is the return program register. 16903 You must use ".ent" before ".frame" and only one ".frame" can be 16904 used per ".ent". 16905 16906`.mask "bitmask", "frameoffset"' 16907 Indicate which of the integer registers are saved in the current 16908 function's stack frame, this is for the debugger to explain the 16909 frame chain. 16910 16911`.ent "proc-name"' 16912 Set the beginning of the procedure "proc_name". Use this directive 16913 when you want to generate information for the debugger. 16914 16915`.end proc-name' 16916 Set the end of a procedure. Use this directive to generate 16917 information for the debugger. 16918 16919`.bss' 16920 Switch the destination of following statements into the bss 16921 section, which is used for data that is uninitialized anywhere. 16922 16923 16924 16925File: as.info, Node: SCORE-Syntax, Prev: SCORE-Pseudo, Up: SCORE-Dependent 16926 169279.38.3 SCORE Syntax 16928------------------- 16929 16930* Menu: 16931 16932* SCORE-Chars:: Special Characters 16933 16934 16935File: as.info, Node: SCORE-Chars, Up: SCORE-Syntax 16936 169379.38.3.1 Special Characters 16938........................... 16939 16940The presence of a `#' appearing anywhere on a line indicates the start 16941of a comment that extends to the end of that line. 16942 16943 If a `#' appears as the first character of a line then the whole 16944line is treated as a comment, but in this case the line can also be a 16945logical line number directive (*note Comments::) or a preprocessor 16946control command (*note Preprocessing::). 16947 16948 The `;' character can be used to separate statements on the same 16949line. 16950 16951 16952File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: NS32K-Dependent, Up: Machine Dependencies 16953 169549.39 Renesas / SuperH SH Dependent Features 16955=========================================== 16956 16957* Menu: 16958 16959* SH Options:: Options 16960* SH Syntax:: Syntax 16961* SH Floating Point:: Floating Point 16962* SH Directives:: SH Machine Directives 16963* SH Opcodes:: Opcodes 16964 16965 16966File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent 16967 169689.39.1 Options 16969-------------- 16970 16971`as' has following command-line options for the Renesas (formerly 16972Hitachi) / SuperH SH family. 16973 16974`--little' 16975 Generate little endian code. 16976 16977`--big' 16978 Generate big endian code. 16979 16980`--relax' 16981 Alter jump instructions for long displacements. 16982 16983`--small' 16984 Align sections to 4 byte boundaries, not 16. 16985 16986`--dsp' 16987 Enable sh-dsp insns, and disable sh3e / sh4 insns. 16988 16989`--renesas' 16990 Disable optimization with section symbol for compatibility with 16991 Renesas assembler. 16992 16993`--allow-reg-prefix' 16994 Allow '$' as a register name prefix. 16995 16996`--fdpic' 16997 Generate an FDPIC object file. 16998 16999`--isa=sh4 | sh4a' 17000 Specify the sh4 or sh4a instruction set. 17001 17002`--isa=dsp' 17003 Enable sh-dsp insns, and disable sh3e / sh4 insns. 17004 17005`--isa=fp' 17006 Enable sh2e, sh3e, sh4, and sh4a insn sets. 17007 17008`--isa=all' 17009 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 17010 17011`-h-tick-hex' 17012 Support H'00 style hex constants in addition to 0x00 style. 17013 17014 17015 17016File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent 17017 170189.39.2 Syntax 17019------------- 17020 17021* Menu: 17022 17023* SH-Chars:: Special Characters 17024* SH-Regs:: Register Names 17025* SH-Addressing:: Addressing Modes 17026 17027 17028File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax 17029 170309.39.2.1 Special Characters 17031........................... 17032 17033`!' is the line comment character. 17034 17035 You can use `;' instead of a newline to separate statements. 17036 17037 If a `#' appears as the first character of a line then the whole 17038line is treated as a comment, but in this case the line could also be a 17039logical line number directive (*note Comments::) or a preprocessor 17040control command (*note Preprocessing::). 17041 17042 Since `$' has no special meaning, you may use it in symbol names. 17043 17044 17045File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax 17046 170479.39.2.2 Register Names 17048....................... 17049 17050You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5', 17051`r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to 17052refer to the SH registers. 17053 17054 The SH also has these control registers: 17055 17056`pr' 17057 procedure register (holds return address) 17058 17059`pc' 17060 program counter 17061 17062`mach' 17063`macl' 17064 high and low multiply accumulator registers 17065 17066`sr' 17067 status register 17068 17069`gbr' 17070 global base register 17071 17072`vbr' 17073 vector base register (for interrupt vectors) 17074 17075 17076File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax 17077 170789.39.2.3 Addressing Modes 17079......................... 17080 17081`as' understands the following addressing modes for the SH. `RN' in 17082the following refers to any of the numbered registers, but _not_ the 17083control registers. 17084 17085`RN' 17086 Register direct 17087 17088`@RN' 17089 Register indirect 17090 17091`@-RN' 17092 Register indirect with pre-decrement 17093 17094`@RN+' 17095 Register indirect with post-increment 17096 17097`@(DISP, RN)' 17098 Register indirect with displacement 17099 17100`@(R0, RN)' 17101 Register indexed 17102 17103`@(DISP, GBR)' 17104 `GBR' offset 17105 17106`@(R0, GBR)' 17107 GBR indexed 17108 17109`ADDR' 17110`@(DISP, PC)' 17111 PC relative address (for branch or for addressing memory). The 17112 `as' implementation allows you to use the simpler form ADDR 17113 anywhere a PC relative address is called for; the alternate form 17114 is supported for compatibility with other assemblers. 17115 17116`#IMM' 17117 Immediate data 17118 17119 17120File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent 17121 171229.39.3 Floating Point 17123--------------------- 17124 17125SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other 17126SH groups can use `.float' directive to generate IEEE floating-point 17127numbers. 17128 17129 SH2E and SH3E support single-precision floating point calculations as 17130well as entirely PCAPI compatible emulation of double-precision 17131floating point calculations. SH2E and SH3E instructions are a subset of 17132the floating point calculations conforming to the IEEE754 standard. 17133 17134 In addition to single-precision and double-precision floating-point 17135operation capability, the on-chip FPU of SH4 has a 128-bit graphic 17136engine that enables 32-bit floating-point data to be processed 128 bits 17137at a time. It also supports 4 * 4 array operations and inner product 17138operations. Also, a superscalar architecture is employed that enables 17139simultaneous execution of two instructions (including FPU 17140instructions), providing performance of up to twice that of 17141conventional architectures at the same frequency. 17142 17143 17144File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent 17145 171469.39.4 SH Machine Directives 17147---------------------------- 17148 17149`uaword' 17150`ualong' 17151`uaquad' 17152 `as' will issue a warning when a misaligned `.word', `.long', or 17153 `.quad' directive is used. You may use `.uaword', `.ualong', or 17154 `.uaquad' to indicate that the value is intentionally misaligned. 17155 17156 17157File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent 17158 171599.39.5 Opcodes 17160-------------- 17161 17162For detailed information on the SH machine instruction set, see 17163`SH-Microcomputer User's Manual' (Renesas) or `SH-4 32-bit CPU Core 17164Architecture' (SuperH) and `SuperH (SH) 64-Bit RISC Series' (SuperH). 17165 17166 `as' implements all the standard SH opcodes. No additional 17167pseudo-instructions are needed on this family. Note, however, that 17168because `as' supports a simpler form of PC-relative addressing, you may 17169simply write (for example) 17170 17171 mov.l bar,r0 17172 17173where other assemblers might require an explicit displacement to `bar' 17174from the program counter: 17175 17176 mov.l @(DISP, PC) 17177 17178 Here is a summary of SH opcodes: 17179 17180 Legend: 17181 Rn a numbered register 17182 Rm another numbered register 17183 #imm immediate data 17184 disp displacement 17185 disp8 8-bit displacement 17186 disp12 12-bit displacement 17187 17188 add #imm,Rn lds.l @Rn+,PR 17189 add Rm,Rn mac.w @Rm+,@Rn+ 17190 addc Rm,Rn mov #imm,Rn 17191 addv Rm,Rn mov Rm,Rn 17192 and #imm,R0 mov.b Rm,@(R0,Rn) 17193 and Rm,Rn mov.b Rm,@-Rn 17194 and.b #imm,@(R0,GBR) mov.b Rm,@Rn 17195 bf disp8 mov.b @(disp,Rm),R0 17196 bra disp12 mov.b @(disp,GBR),R0 17197 bsr disp12 mov.b @(R0,Rm),Rn 17198 bt disp8 mov.b @Rm+,Rn 17199 clrmac mov.b @Rm,Rn 17200 clrt mov.b R0,@(disp,Rm) 17201 cmp/eq #imm,R0 mov.b R0,@(disp,GBR) 17202 cmp/eq Rm,Rn mov.l Rm,@(disp,Rn) 17203 cmp/ge Rm,Rn mov.l Rm,@(R0,Rn) 17204 cmp/gt Rm,Rn mov.l Rm,@-Rn 17205 cmp/hi Rm,Rn mov.l Rm,@Rn 17206 cmp/hs Rm,Rn mov.l @(disp,Rn),Rm 17207 cmp/pl Rn mov.l @(disp,GBR),R0 17208 cmp/pz Rn mov.l @(disp,PC),Rn 17209 cmp/str Rm,Rn mov.l @(R0,Rm),Rn 17210 div0s Rm,Rn mov.l @Rm+,Rn 17211 div0u mov.l @Rm,Rn 17212 div1 Rm,Rn mov.l R0,@(disp,GBR) 17213 exts.b Rm,Rn mov.w Rm,@(R0,Rn) 17214 exts.w Rm,Rn mov.w Rm,@-Rn 17215 extu.b Rm,Rn mov.w Rm,@Rn 17216 extu.w Rm,Rn mov.w @(disp,Rm),R0 17217 jmp @Rn mov.w @(disp,GBR),R0 17218 jsr @Rn mov.w @(disp,PC),Rn 17219 ldc Rn,GBR mov.w @(R0,Rm),Rn 17220 ldc Rn,SR mov.w @Rm+,Rn 17221 ldc Rn,VBR mov.w @Rm,Rn 17222 ldc.l @Rn+,GBR mov.w R0,@(disp,Rm) 17223 ldc.l @Rn+,SR mov.w R0,@(disp,GBR) 17224 ldc.l @Rn+,VBR mova @(disp,PC),R0 17225 lds Rn,MACH movt Rn 17226 lds Rn,MACL muls Rm,Rn 17227 lds Rn,PR mulu Rm,Rn 17228 lds.l @Rn+,MACH neg Rm,Rn 17229 lds.l @Rn+,MACL negc Rm,Rn 17230 17231 nop stc VBR,Rn 17232 not Rm,Rn stc.l GBR,@-Rn 17233 or #imm,R0 stc.l SR,@-Rn 17234 or Rm,Rn stc.l VBR,@-Rn 17235 or.b #imm,@(R0,GBR) sts MACH,Rn 17236 rotcl Rn sts MACL,Rn 17237 rotcr Rn sts PR,Rn 17238 rotl Rn sts.l MACH,@-Rn 17239 rotr Rn sts.l MACL,@-Rn 17240 rte sts.l PR,@-Rn 17241 rts sub Rm,Rn 17242 sett subc Rm,Rn 17243 shal Rn subv Rm,Rn 17244 shar Rn swap.b Rm,Rn 17245 shll Rn swap.w Rm,Rn 17246 shll16 Rn tas.b @Rn 17247 shll2 Rn trapa #imm 17248 shll8 Rn tst #imm,R0 17249 shlr Rn tst Rm,Rn 17250 shlr16 Rn tst.b #imm,@(R0,GBR) 17251 shlr2 Rn xor #imm,R0 17252 shlr8 Rn xor Rm,Rn 17253 sleep xor.b #imm,@(R0,GBR) 17254 stc GBR,Rn xtrct Rm,Rn 17255 stc SR,Rn 17256 17257 17258File: as.info, Node: SH64-Dependent, Next: PDP-11-Dependent, Prev: SH-Dependent, Up: Machine Dependencies 17259 172609.40 SuperH SH64 Dependent Features 17261=================================== 17262 17263* Menu: 17264 17265* SH64 Options:: Options 17266* SH64 Syntax:: Syntax 17267* SH64 Directives:: SH64 Machine Directives 17268* SH64 Opcodes:: Opcodes 17269 17270 17271File: as.info, Node: SH64 Options, Next: SH64 Syntax, Up: SH64-Dependent 17272 172739.40.1 Options 17274-------------- 17275 17276`-isa=sh4 | sh4a' 17277 Specify the sh4 or sh4a instruction set. 17278 17279`-isa=dsp' 17280 Enable sh-dsp insns, and disable sh3e / sh4 insns. 17281 17282`-isa=fp' 17283 Enable sh2e, sh3e, sh4, and sh4a insn sets. 17284 17285`-isa=all' 17286 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 17287 17288`-isa=shmedia | -isa=shcompact' 17289 Specify the default instruction set. `SHmedia' specifies the 17290 32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes 17291 compatible with previous SH families. The default depends on the 17292 ABI selected; the default for the 64-bit ABI is SHmedia, and the 17293 default for the 32-bit ABI is SHcompact. If neither the ABI nor 17294 the ISA is specified, the default is 32-bit SHcompact. 17295 17296 Note that the `.mode' pseudo-op is not permitted if the ISA is not 17297 specified on the command line. 17298 17299`-abi=32 | -abi=64' 17300 Specify the default ABI. If the ISA is specified and the ABI is 17301 not, the default ABI depends on the ISA, with SHmedia defaulting 17302 to 64-bit and SHcompact defaulting to 32-bit. 17303 17304 Note that the `.abi' pseudo-op is not permitted if the ABI is not 17305 specified on the command line. When the ABI is specified on the 17306 command line, any `.abi' pseudo-ops in the source must match it. 17307 17308`-shcompact-const-crange' 17309 Emit code-range descriptors for constants in SHcompact code 17310 sections. 17311 17312`-no-mix' 17313 Disallow SHmedia code in the same section as constants and 17314 SHcompact code. 17315 17316`-no-expand' 17317 Do not expand MOVI, PT, PTA or PTB instructions. 17318 17319`-expand-pt32' 17320 With -abi=64, expand PT, PTA and PTB instructions to 32 bits only. 17321 17322`-h-tick-hex' 17323 Support H'00 style hex constants in addition to 0x00 style. 17324 17325 17326 17327File: as.info, Node: SH64 Syntax, Next: SH64 Directives, Prev: SH64 Options, Up: SH64-Dependent 17328 173299.40.2 Syntax 17330------------- 17331 17332* Menu: 17333 17334* SH64-Chars:: Special Characters 17335* SH64-Regs:: Register Names 17336* SH64-Addressing:: Addressing Modes 17337 17338 17339File: as.info, Node: SH64-Chars, Next: SH64-Regs, Up: SH64 Syntax 17340 173419.40.2.1 Special Characters 17342........................... 17343 17344`!' is the line comment character. 17345 17346 If a `#' appears as the first character of a line then the whole 17347line is treated as a comment, but in this case the line could also be a 17348logical line number directive (*note Comments::) or a preprocessor 17349control command (*note Preprocessing::). 17350 17351 You can use `;' instead of a newline to separate statements. 17352 17353 Since `$' has no special meaning, you may use it in symbol names. 17354 17355 17356File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: SH64 Syntax 17357 173589.40.2.2 Register Names 17359....................... 17360 17361You can use the predefined symbols `r0' through `r63' to refer to the 17362SH64 general registers, `cr0' through `cr63' for control registers, 17363`tr0' through `tr7' for target address registers, `fr0' through `fr63' 17364for single-precision floating point registers, `dr0' through `dr62' 17365(even numbered registers only) for double-precision floating point 17366registers, `fv0' through `fv60' (multiples of four only) for 17367single-precision floating point vectors, `fp0' through `fp62' (even 17368numbered registers only) for single-precision floating point pairs, 17369`mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of 17370single-precision floating point registers, `pc' for the program 17371counter, and `fpscr' for the floating point status and control register. 17372 17373 You can also refer to the control registers by the mnemonics `sr', 17374`ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc', 17375`resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'. 17376 17377 17378File: as.info, Node: SH64-Addressing, Prev: SH64-Regs, Up: SH64 Syntax 17379 173809.40.2.3 Addressing Modes 17381......................... 17382 17383SH64 operands consist of either a register or immediate value. The 17384immediate value can be a constant or label reference (or portion of a 17385label reference), as in this example: 17386 17387 movi 4,r2 17388 pt function, tr4 17389 movi (function >> 16) & 65535,r0 17390 shori function & 65535, r0 17391 ld.l r0,4,r0 17392 17393 Instruction label references can reference labels in either SHmedia 17394or SHcompact. To differentiate between the two, labels in SHmedia 17395sections will always have the least significant bit set (i.e. they will 17396be odd), which SHcompact labels will have the least significant bit 17397reset (i.e. they will be even). If you need to reference the actual 17398address of a label, you can use the `datalabel' modifier, as in this 17399example: 17400 17401 .long function 17402 .long datalabel function 17403 17404 In that example, the first longword may or may not have the least 17405significant bit set depending on whether the label is an SHmedia label 17406or an SHcompact label. The second longword will be the actual address 17407of the label, regardless of what type of label it is. 17408 17409 17410File: as.info, Node: SH64 Directives, Next: SH64 Opcodes, Prev: SH64 Syntax, Up: SH64-Dependent 17411 174129.40.3 SH64 Machine Directives 17413------------------------------ 17414 17415In addition to the SH directives, the SH64 provides the following 17416directives: 17417 17418`.mode [shmedia|shcompact]' 17419`.isa [shmedia|shcompact]' 17420 Specify the ISA for the following instructions (the two directives 17421 are equivalent). Note that programs such as `objdump' rely on 17422 symbolic labels to determine when such mode switches occur (by 17423 checking the least significant bit of the label's address), so 17424 such mode/isa changes should always be followed by a label (in 17425 practice, this is true anyway). Note that you cannot use these 17426 directives if you didn't specify an ISA on the command line. 17427 17428`.abi [32|64]' 17429 Specify the ABI for the following instructions. Note that you 17430 cannot use this directive unless you specified an ABI on the 17431 command line, and the ABIs specified must match. 17432 17433 17434 17435File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent 17436 174379.40.4 Opcodes 17438-------------- 17439 17440For detailed information on the SH64 machine instruction set, see 17441`SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.). 17442 17443 `as' implements all the standard SH64 opcodes. In addition, the 17444following pseudo-opcodes may be expanded into one or more alternate 17445opcodes: 17446 17447`movi' 17448 If the value doesn't fit into a standard `movi' opcode, `as' will 17449 replace the `movi' with a sequence of `movi' and `shori' opcodes. 17450 17451`pt' 17452 This expands to a sequence of `movi' and `shori' opcode, followed 17453 by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on 17454 the label referenced. 17455 17456 17457 17458File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies 17459 174609.41 SPARC Dependent Features 17461============================= 17462 17463* Menu: 17464 17465* Sparc-Opts:: Options 17466* Sparc-Aligned-Data:: Option to enforce aligned data 17467* Sparc-Syntax:: Syntax 17468* Sparc-Float:: Floating Point 17469* Sparc-Directives:: Sparc Machine Directives 17470 17471 17472File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent 17473 174749.41.1 Options 17475-------------- 17476 17477The SPARC chip family includes several successive versions, using the 17478same core instruction set, but including a few additional instructions 17479at each version. There are exceptions to this however. For details on 17480what instructions each variant supports, please see the chip's 17481architecture reference manual. 17482 17483 By default, `as' assumes the core instruction set (SPARC v6), but 17484"bumps" the architecture level as needed: it switches to successively 17485higher architectures as it encounters instructions that only exist in 17486the higher levels. 17487 17488 If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump 17489past sparclite by default, an option must be passed to enable the v9 17490instructions. 17491 17492 GAS treats sparclite as being compatible with v8, unless an 17493architecture is explicitly requested. SPARC v9 is always incompatible 17494with sparclite. 17495 17496`-Av6 | -Av7 | -Av8 | -Aleon | -Asparclet | -Asparclite' 17497`-Av8plus | -Av8plusa | -Av8plusb | -Av8plusc | -Av8plusd | -Av8plusv' 17498`-Av9 | -Av9a | -Av9b | -Av9c | -Av9d | -Av9v' 17499`-Asparc | -Asparcvis | -Asparcvis2 | -Asparcfmaf | -Asparcima' 17500`-Asparcvis3 | -Asparcvis3r' 17501 Use one of the `-A' options to select one of the SPARC 17502 architectures explicitly. If you select an architecture 17503 explicitly, `as' reports a fatal error if it encounters an 17504 instruction or feature requiring an incompatible or higher level. 17505 17506 `-Av8plus', `-Av8plusa', `-Av8plusb', `-Av8plusc', `-Av8plusd', 17507 and `-Av8plusv' select a 32 bit environment. 17508 17509 `-Av9', `-Av9a', `-Av9b', `-Av9c', `-Av9d', and `-Av9v' select a 17510 64 bit environment and are not available unless GAS is explicitly 17511 configured with 64 bit environment support. 17512 17513 `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with 17514 UltraSPARC VIS 1.0 extensions. 17515 17516 `-Av8plusb' and `-Av9b' enable the UltraSPARC VIS 2.0 instructions, 17517 as well as the instructions enabled by `-Av8plusa' and `-Av9a'. 17518 17519 `-Av8plusc' and `-Av9c' enable the UltraSPARC Niagara instructions, 17520 as well as the instructions enabled by `-Av8plusb' and `-Av9b'. 17521 17522 `-Av8plusd' and `-Av9d' enable the floating point fused 17523 multiply-add, VIS 3.0, and HPC extension instructions, as well as 17524 the instructions enabled by `-Av8plusc' and `-Av9c'. 17525 17526 `-Av8plusv' and `-Av9v' enable the 'random', transactional memory, 17527 floating point unfused multiply-add, integer multiply-add, and 17528 cache sparing store instructions, as well as the instructions 17529 enabled by `-Av8plusd' and `-Av9d'. 17530 17531 `-Asparc' specifies a v9 environment. It is equivalent to `-Av9' 17532 if the word size is 64-bit, and `-Av8plus' otherwise. 17533 17534 `-Asparcvis' specifies a v9a environment. It is equivalent to 17535 `-Av9a' if the word size is 64-bit, and `-Av8plusa' otherwise. 17536 17537 `-Asparcvis2' specifies a v9b environment. It is equivalent to 17538 `-Av9b' if the word size is 64-bit, and `-Av8plusb' otherwise. 17539 17540 `-Asparcfmaf' specifies a v9b environment with the floating point 17541 fused multiply-add instructions enabled. 17542 17543 `-Asparcima' specifies a v9b environment with the integer 17544 multiply-add instructions enabled. 17545 17546 `-Asparcvis3' specifies a v9b environment with the VIS 3.0, HPC , 17547 and floating point fused multiply-add instructions enabled. 17548 17549 `-Asparcvis3r' specifies a v9b environment with the VIS 3.0, HPC, 17550 transactional memory, random, and floating point unfused 17551 multiply-add instructions enabled. 17552 17553`-xarch=v8plus | -xarch=v8plusa | -xarch=v8plusb | -xarch=v8plusc' 17554`-xarch=v8plusd | -xarch=v8plusv | -xarch=v9 | -xarch=v9a' 17555`-xarch=v9b | -xarch=v9c | -xarch=v9d | -xarch=v9v' 17556`-xarch=sparc | -xarch=sparcvis | -xarch=sparcvis2' 17557`-xarch=sparcfmaf | -xarch=sparcima | -xarch=sparcvis3' 17558`-xarch=sparcvis3r' 17559 For compatibility with the SunOS v9 assembler. These options are 17560 equivalent to -Av8plus, -Av8plusa, -Av8plusb, -Av8plusc, -Av8plusd, 17561 -Av8plusv, -Av9, -Av9a, -Av9b, -Av9c, -Av9d, -Av9v, -Asparc, 17562 -Asparcvis, -Asparcvis2, -Asparcfmaf, -Asparcima, -Asparcvis3, and 17563 -Asparcvis3r, respectively. 17564 17565`-bump' 17566 Warn whenever it is necessary to switch to another level. If an 17567 architecture level is explicitly requested, GAS will not issue 17568 warnings until that level is reached, and will then bump the level 17569 as required (except between incompatible levels). 17570 17571`-32 | -64' 17572 Select the word size, either 32 bits or 64 bits. These options 17573 are only available with the ELF object file format, and require 17574 that the necessary BFD support has been included. 17575 17576 17577File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent 17578 175799.41.2 Enforcing aligned data 17580----------------------------- 17581 17582SPARC GAS normally permits data to be misaligned. For example, it 17583permits the `.long' pseudo-op to be used on a byte boundary. However, 17584the native SunOS assemblers issue an error when they see misaligned 17585data. 17586 17587 You can use the `--enforce-aligned-data' option to make SPARC GAS 17588also issue an error about misaligned data, just as the SunOS assemblers 17589do. 17590 17591 The `--enforce-aligned-data' option is not the default because gcc 17592issues misaligned data pseudo-ops when it initializes certain packed 17593data structures (structures defined using the `packed' attribute). You 17594may have to assemble with GAS in order to initialize packed data 17595structures in your own code. 17596 17597 17598File: as.info, Node: Sparc-Syntax, Next: Sparc-Float, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent 17599 176009.41.3 Sparc Syntax 17601------------------- 17602 17603The assembler syntax closely follows The Sparc Architecture Manual, 17604versions 8 and 9, as well as most extensions defined by Sun for their 17605UltraSPARC and Niagara line of processors. 17606 17607* Menu: 17608 17609* Sparc-Chars:: Special Characters 17610* Sparc-Regs:: Register Names 17611* Sparc-Constants:: Constant Names 17612* Sparc-Relocs:: Relocations 17613* Sparc-Size-Translations:: Size Translations 17614 17615 17616File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax 17617 176189.41.3.1 Special Characters 17619........................... 17620 17621A `!' character appearing anywhere on a line indicates the start of a 17622comment that extends to the end of that line. 17623 17624 If a `#' appears as the first character of a line then the whole 17625line is treated as a comment, but in this case the line could also be a 17626logical line number directive (*note Comments::) or a preprocessor 17627control command (*note Preprocessing::). 17628 17629 `;' can be used instead of a newline to separate statements. 17630 17631 17632File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax 17633 176349.41.3.2 Register Names 17635....................... 17636 17637The Sparc integer register file is broken down into global, outgoing, 17638local, and incoming. 17639 17640 * The 8 global registers are referred to as `%gN'. 17641 17642 * The 8 outgoing registers are referred to as `%oN'. 17643 17644 * The 8 local registers are referred to as `%lN'. 17645 17646 * The 8 incoming registers are referred to as `%iN'. 17647 17648 * The frame pointer register `%i6' can be referenced using the alias 17649 `%fp'. 17650 17651 * The stack pointer register `%o6' can be referenced using the alias 17652 `%sp'. 17653 17654 Floating point registers are simply referred to as `%fN'. When 17655assembling for pre-V9, only 32 floating point registers are available. 17656For V9 and later there are 64, but there are restrictions when 17657referencing the upper 32 registers. They can only be accessed as 17658double or quad, and thus only even or quad numbered accesses are 17659allowed. For example, `%f34' is a legal floating point register, but 17660`%f35' is not. 17661 17662 Certain V9 instructions allow access to ancillary state registers. 17663Most simply they can be referred to as `%asrN' where N can be from 16 17664to 31. However, there are some aliases defined to reference ASR 17665registers defined for various UltraSPARC processors: 17666 17667 * The tick compare register is referred to as `%tick_cmpr'. 17668 17669 * The system tick register is referred to as `%stick'. An alias, 17670 `%sys_tick', exists but is deprecated and should not be used by 17671 new software. 17672 17673 * The system tick compare register is referred to as `%stick_cmpr'. 17674 An alias, `%sys_tick_cmpr', exists but is deprecated and should 17675 not be used by new software. 17676 17677 * The software interrupt register is referred to as `%softint'. 17678 17679 * The set software interrupt register is referred to as 17680 `%set_softint'. The mnemonic `%softint_set' is provided as an 17681 alias. 17682 17683 * The clear software interrupt register is referred to as 17684 `%clear_softint'. The mnemonic `%softint_clear' is provided as an 17685 alias. 17686 17687 * The performance instrumentation counters register is referred to as 17688 `%pic'. 17689 17690 * The performance control register is referred to as `%pcr'. 17691 17692 * The graphics status register is referred to as `%gsr'. 17693 17694 * The V9 dispatch control register is referred to as `%dcr'. 17695 17696 Various V9 branch and conditional move instructions allow 17697specification of which set of integer condition codes to test. These 17698are referred to as `%xcc' and `%icc'. 17699 17700 In V9, there are 4 sets of floating point condition codes which are 17701referred to as `%fccN'. 17702 17703 Several special privileged and non-privileged registers exist: 17704 17705 * The V9 address space identifier register is referred to as `%asi'. 17706 17707 * The V9 restorable windows register is referred to as `%canrestore'. 17708 17709 * The V9 savable windows register is referred to as `%cansave'. 17710 17711 * The V9 clean windows register is referred to as `%cleanwin'. 17712 17713 * The V9 current window pointer register is referred to as `%cwp'. 17714 17715 * The floating-point queue register is referred to as `%fq'. 17716 17717 * The V8 co-processor queue register is referred to as `%cq'. 17718 17719 * The floating point status register is referred to as `%fsr'. 17720 17721 * The other windows register is referred to as `%otherwin'. 17722 17723 * The V9 program counter register is referred to as `%pc'. 17724 17725 * The V9 next program counter register is referred to as `%npc'. 17726 17727 * The V9 processor interrupt level register is referred to as `%pil'. 17728 17729 * The V9 processor state register is referred to as `%pstate'. 17730 17731 * The trap base address register is referred to as `%tba'. 17732 17733 * The V9 tick register is referred to as `%tick'. 17734 17735 * The V9 trap level is referred to as `%tl'. 17736 17737 * The V9 trap program counter is referred to as `%tpc'. 17738 17739 * The V9 trap next program counter is referred to as `%tnpc'. 17740 17741 * The V9 trap state is referred to as `%tstate'. 17742 17743 * The V9 trap type is referred to as `%tt'. 17744 17745 * The V9 condition codes is referred to as `%ccr'. 17746 17747 * The V9 floating-point registers state is referred to as `%fprs'. 17748 17749 * The V9 version register is referred to as `%ver'. 17750 17751 * The V9 window state register is referred to as `%wstate'. 17752 17753 * The Y register is referred to as `%y'. 17754 17755 * The V8 window invalid mask register is referred to as `%wim'. 17756 17757 * The V8 processor state register is referred to as `%psr'. 17758 17759 * The V9 global register level register is referred to as `%gl'. 17760 17761 Several special register names exist for hypervisor mode code: 17762 17763 * The hyperprivileged processor state register is referred to as 17764 `%hpstate'. 17765 17766 * The hyperprivileged trap state register is referred to as 17767 `%htstate'. 17768 17769 * The hyperprivileged interrupt pending register is referred to as 17770 `%hintp'. 17771 17772 * The hyperprivileged trap base address register is referred to as 17773 `%htba'. 17774 17775 * The hyperprivileged implementation version register is referred to 17776 as `%hver'. 17777 17778 * The hyperprivileged system tick compare register is referred to as 17779 `%hstick_cmpr'. Note that there is no `%hstick' register, the 17780 normal `%stick' is used. 17781 17782 17783File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax 17784 177859.41.3.3 Constants 17786.................. 17787 17788Several Sparc instructions take an immediate operand field for which 17789mnemonic names exist. Two such examples are `membar' and `prefetch'. 17790Another example are the set of V9 memory access instruction that allow 17791specification of an address space identifier. 17792 17793 The `membar' instruction specifies a memory barrier that is the 17794defined by the operand which is a bitmask. The supported mask 17795mnemonics are: 17796 17797 * `#Sync' requests that all operations (including nonmemory 17798 reference operations) appearing prior to the `membar' must have 17799 been performed and the effects of any exceptions become visible 17800 before any instructions after the `membar' may be initiated. This 17801 corresponds to `membar' cmask field bit 2. 17802 17803 * `#MemIssue' requests that all memory reference operations 17804 appearing prior to the `membar' must have been performed before 17805 any memory operation after the `membar' may be initiated. This 17806 corresponds to `membar' cmask field bit 1. 17807 17808 * `#Lookaside' requests that a store appearing prior to the `membar' 17809 must complete before any load following the `membar' referencing 17810 the same address can be initiated. This corresponds to `membar' 17811 cmask field bit 0. 17812 17813 * `#StoreStore' defines that the effects of all stores appearing 17814 prior to the `membar' instruction must be visible to all 17815 processors before the effect of any stores following the `membar'. 17816 Equivalent to the deprecated `stbar' instruction. This 17817 corresponds to `membar' mmask field bit 3. 17818 17819 * `#LoadStore' defines all loads appearing prior to the `membar' 17820 instruction must have been performed before the effect of any 17821 stores following the `membar' is visible to any other processor. 17822 This corresponds to `membar' mmask field bit 2. 17823 17824 * `#StoreLoad' defines that the effects of all stores appearing 17825 prior to the `membar' instruction must be visible to all 17826 processors before loads following the `membar' may be performed. 17827 This corresponds to `membar' mmask field bit 1. 17828 17829 * `#LoadLoad' defines that all loads appearing prior to the `membar' 17830 instruction must have been performed before any loads following 17831 the `membar' may be performed. This corresponds to `membar' mmask 17832 field bit 0. 17833 17834 17835 These values can be ored together, for example: 17836 17837 membar #Sync 17838 membar #StoreLoad | #LoadLoad 17839 membar #StoreLoad | #StoreStore 17840 17841 The `prefetch' and `prefetcha' instructions take a prefetch function 17842code. The following prefetch function code constant mnemonics are 17843available: 17844 17845 * `#n_reads' requests a prefetch for several reads, and corresponds 17846 to a prefetch function code of 0. 17847 17848 `#one_read' requests a prefetch for one read, and corresponds to a 17849 prefetch function code of 1. 17850 17851 `#n_writes' requests a prefetch for several writes (and possibly 17852 reads), and corresponds to a prefetch function code of 2. 17853 17854 `#one_write' requests a prefetch for one write, and corresponds to 17855 a prefetch function code of 3. 17856 17857 `#page' requests a prefetch page, and corresponds to a prefetch 17858 function code of 4. 17859 17860 `#invalidate' requests a prefetch invalidate, and corresponds to a 17861 prefetch function code of 16. 17862 17863 `#unified' requests a prefetch to the nearest unified cache, and 17864 corresponds to a prefetch function code of 17. 17865 17866 `#n_reads_strong' requests a strong prefetch for several reads, 17867 and corresponds to a prefetch function code of 20. 17868 17869 `#one_read_strong' requests a strong prefetch for one read, and 17870 corresponds to a prefetch function code of 21. 17871 17872 `#n_writes_strong' requests a strong prefetch for several writes, 17873 and corresponds to a prefetch function code of 22. 17874 17875 `#one_write_strong' requests a strong prefetch for one write, and 17876 corresponds to a prefetch function code of 23. 17877 17878 Onle one prefetch code may be specified. Here are some examples: 17879 17880 prefetch [%l0 + %l2], #one_read 17881 prefetch [%g2 + 8], #n_writes 17882 prefetcha [%g1] 0x8, #unified 17883 prefetcha [%o0 + 0x10] %asi, #n_reads 17884 17885 The actual behavior of a given prefetch function code is processor 17886 specific. If a processor does not implement a given prefetch 17887 function code, it will treat the prefetch instruction as a nop. 17888 17889 For instructions that accept an immediate address space identifier, 17890 `as' provides many mnemonics corresponding to V9 defined as well 17891 as UltraSPARC and Niagara extended values. For example, `#ASI_P' 17892 and `#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor 17893 specific manuals for details. 17894 17895 17896 17897File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax 17898 178999.41.3.4 Relocations 17900.................... 17901 17902ELF relocations are available as defined in the 32-bit and 64-bit Sparc 17903ELF specifications. 17904 17905 `R_SPARC_HI22' is obtained using `%hi' and `R_SPARC_LO10' is 17906obtained using `%lo'. Likewise `R_SPARC_HIX22' is obtained from `%hix' 17907and `R_SPARC_LOX10' is obtained using `%lox'. For example: 17908 17909 sethi %hi(symbol), %g1 17910 or %g1, %lo(symbol), %g1 17911 17912 sethi %hix(symbol), %g1 17913 xor %g1, %lox(symbol), %g1 17914 17915 These "high" mnemonics extract bits 31:10 of their operand, and the 17916"low" mnemonics extract bits 9:0 of their operand. 17917 17918 V9 code model relocations can be requested as follows: 17919 17920 * `R_SPARC_HH22' is requested using `%hh'. It can also be generated 17921 using `%uhi'. 17922 17923 * `R_SPARC_HM10' is requested using `%hm'. It can also be generated 17924 using `%ulo'. 17925 17926 * `R_SPARC_LM22' is requested using `%lm'. 17927 17928 * `R_SPARC_H44' is requested using `%h44'. 17929 17930 * `R_SPARC_M44' is requested using `%m44'. 17931 17932 * `R_SPARC_L44' is requested using `%l44' or `%l34'. 17933 17934 * `R_SPARC_H34' is requested using `%h34'. 17935 17936 The `%l34' generates a `R_SPARC_L44' relocation because it 17937calculates the necessary value, and therefore no explicit `R_SPARC_L34' 17938relocation needed to be created for this purpose. 17939 17940 The `%h34' and `%l34' relocations are used for the abs34 code model. 17941Here is an example abs34 address generation sequence: 17942 17943 sethi %h34(symbol), %g1 17944 sllx %g1, 2, %g1 17945 or %g1, %l34(symbol), %g1 17946 17947 The PC relative relocation `R_SPARC_PC22' can be obtained by 17948enclosing an operand inside of `%pc22'. Likewise, the `R_SPARC_PC10' 17949relocation can be obtained using `%pc10'. These are mostly used when 17950assembling PIC code. For example, the standard PIC sequence on Sparc 17951to get the base of the global offset table, PC relative, into a 17952register, can be performed as: 17953 17954 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 17955 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 17956 17957 Several relocations exist to allow the link editor to potentially 17958optimize GOT data references. The `R_SPARC_GOTDATA_OP_HIX22' 17959relocation can obtained by enclosing an operand inside of 17960`%gdop_hix22'. The `R_SPARC_GOTDATA_OP_LOX10' relocation can obtained 17961by enclosing an operand inside of `%gdop_lox10'. Likewise, 17962`R_SPARC_GOTDATA_OP' can be obtained by enclosing an operand inside of 17963`%gdop'. For example, assuming the GOT base is in register `%l7': 17964 17965 sethi %gdop_hix22(symbol), %l1 17966 xor %l1, %gdop_lox10(symbol), %l1 17967 ld [%l7 + %l1], %l2, %gdop(symbol) 17968 17969 There are many relocations that can be requested for access to 17970thread local storage variables. All of the Sparc TLS mnemonics are 17971supported: 17972 17973 * `R_SPARC_TLS_GD_HI22' is requested using `%tgd_hi22'. 17974 17975 * `R_SPARC_TLS_GD_LO10' is requested using `%tgd_lo10'. 17976 17977 * `R_SPARC_TLS_GD_ADD' is requested using `%tgd_add'. 17978 17979 * `R_SPARC_TLS_GD_CALL' is requested using `%tgd_call'. 17980 17981 * `R_SPARC_TLS_LDM_HI22' is requested using `%tldm_hi22'. 17982 17983 * `R_SPARC_TLS_LDM_LO10' is requested using `%tldm_lo10'. 17984 17985 * `R_SPARC_TLS_LDM_ADD' is requested using `%tldm_add'. 17986 17987 * `R_SPARC_TLS_LDM_CALL' is requested using `%tldm_call'. 17988 17989 * `R_SPARC_TLS_LDO_HIX22' is requested using `%tldo_hix22'. 17990 17991 * `R_SPARC_TLS_LDO_LOX10' is requested using `%tldo_lox10'. 17992 17993 * `R_SPARC_TLS_LDO_ADD' is requested using `%tldo_add'. 17994 17995 * `R_SPARC_TLS_IE_HI22' is requested using `%tie_hi22'. 17996 17997 * `R_SPARC_TLS_IE_LO10' is requested using `%tie_lo10'. 17998 17999 * `R_SPARC_TLS_IE_LD' is requested using `%tie_ld'. 18000 18001 * `R_SPARC_TLS_IE_LDX' is requested using `%tie_ldx'. 18002 18003 * `R_SPARC_TLS_IE_ADD' is requested using `%tie_add'. 18004 18005 * `R_SPARC_TLS_LE_HIX22' is requested using `%tle_hix22'. 18006 18007 * `R_SPARC_TLS_LE_LOX10' is requested using `%tle_lox10'. 18008 18009 Here are some example TLS model sequences. 18010 18011 First, General Dynamic: 18012 18013 sethi %tgd_hi22(symbol), %l1 18014 add %l1, %tgd_lo10(symbol), %l1 18015 add %l7, %l1, %o0, %tgd_add(symbol) 18016 call __tls_get_addr, %tgd_call(symbol) 18017 nop 18018 18019 Local Dynamic: 18020 18021 sethi %tldm_hi22(symbol), %l1 18022 add %l1, %tldm_lo10(symbol), %l1 18023 add %l7, %l1, %o0, %tldm_add(symbol) 18024 call __tls_get_addr, %tldm_call(symbol) 18025 nop 18026 18027 sethi %tldo_hix22(symbol), %l1 18028 xor %l1, %tldo_lox10(symbol), %l1 18029 add %o0, %l1, %l1, %tldo_add(symbol) 18030 18031 Initial Exec: 18032 18033 sethi %tie_hi22(symbol), %l1 18034 add %l1, %tie_lo10(symbol), %l1 18035 ld [%l7 + %l1], %o0, %tie_ld(symbol) 18036 add %g7, %o0, %o0, %tie_add(symbol) 18037 18038 sethi %tie_hi22(symbol), %l1 18039 add %l1, %tie_lo10(symbol), %l1 18040 ldx [%l7 + %l1], %o0, %tie_ldx(symbol) 18041 add %g7, %o0, %o0, %tie_add(symbol) 18042 18043 And finally, Local Exec: 18044 18045 sethi %tle_hix22(symbol), %l1 18046 add %l1, %tle_lox10(symbol), %l1 18047 add %g7, %l1, %l1 18048 18049 When assembling for 64-bit, and a secondary constant addend is 18050specified in an address expression that would normally generate an 18051`R_SPARC_LO10' relocation, the assembler will emit an `R_SPARC_OLO10' 18052instead. 18053 18054 18055File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-Syntax 18056 180579.41.3.5 Size Translations 18058.......................... 18059 18060Often it is desirable to write code in an operand size agnostic manner. 18061`as' provides support for this via operand size opcode translations. 18062Translations are supported for loads, stores, shifts, compare-and-swap 18063atomics, and the `clr' synthetic instruction. 18064 18065 If generating 32-bit code, `as' will generate the 32-bit opcode. 18066Whereas if 64-bit code is being generated, the 64-bit opcode will be 18067emitted. For example `ldn' will be transformed into `ld' for 32-bit 18068code and `ldx' for 64-bit code. 18069 18070 Here is an example meant to demonstrate all the supported opcode 18071translations: 18072 18073 ldn [%o0], %o1 18074 ldna [%o0] %asi, %o2 18075 stn %o1, [%o0] 18076 stna %o2, [%o0] %asi 18077 slln %o3, 3, %o3 18078 srln %o4, 8, %o4 18079 sran %o5, 12, %o5 18080 casn [%o0], %o1, %o2 18081 casna [%o0] %asi, %o1, %o2 18082 clrn %g1 18083 18084 In 32-bit mode `as' will emit: 18085 18086 ld [%o0], %o1 18087 lda [%o0] %asi, %o2 18088 st %o1, [%o0] 18089 sta %o2, [%o0] %asi 18090 sll %o3, 3, %o3 18091 srl %o4, 8, %o4 18092 sra %o5, 12, %o5 18093 cas [%o0], %o1, %o2 18094 casa [%o0] %asi, %o1, %o2 18095 clr %g1 18096 18097 And in 64-bit mode `as' will emit: 18098 18099 ldx [%o0], %o1 18100 ldxa [%o0] %asi, %o2 18101 stx %o1, [%o0] 18102 stxa %o2, [%o0] %asi 18103 sllx %o3, 3, %o3 18104 srlx %o4, 8, %o4 18105 srax %o5, 12, %o5 18106 casx [%o0], %o1, %o2 18107 casxa [%o0] %asi, %o1, %o2 18108 clrx %g1 18109 18110 Finally, the `.nword' translating directive is supported as well. 18111It is documented in the section on Sparc machine directives. 18112 18113 18114File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent 18115 181169.41.4 Floating Point 18117--------------------- 18118 18119The Sparc uses IEEE floating-point numbers. 18120 18121 18122File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent 18123 181249.41.5 Sparc Machine Directives 18125------------------------------- 18126 18127The Sparc version of `as' supports the following additional machine 18128directives: 18129 18130`.align' 18131 This must be followed by the desired alignment in bytes. 18132 18133`.common' 18134 This must be followed by a symbol name, a positive number, and 18135 `"bss"'. This behaves somewhat like `.comm', but the syntax is 18136 different. 18137 18138`.half' 18139 This is functionally identical to `.short'. 18140 18141`.nword' 18142 On the Sparc, the `.nword' directive produces native word sized 18143 value, ie. if assembling with -32 it is equivalent to `.word', if 18144 assembling with -64 it is equivalent to `.xword'. 18145 18146`.proc' 18147 This directive is ignored. Any text following it on the same line 18148 is also ignored. 18149 18150`.register' 18151 This directive declares use of a global application or system 18152 register. It must be followed by a register name %g2, %g3, %g6 or 18153 %g7, comma and the symbol name for that register. If symbol name 18154 is `#scratch', it is a scratch register, if it is `#ignore', it 18155 just suppresses any errors about using undeclared global register, 18156 but does not emit any information about it into the object file. 18157 This can be useful e.g. if you save the register before use and 18158 restore it after. 18159 18160`.reserve' 18161 This must be followed by a symbol name, a positive number, and 18162 `"bss"'. This behaves somewhat like `.lcomm', but the syntax is 18163 different. 18164 18165`.seg' 18166 This must be followed by `"text"', `"data"', or `"data1"'. It 18167 behaves like `.text', `.data', or `.data 1'. 18168 18169`.skip' 18170 This is functionally identical to the `.space' directive. 18171 18172`.word' 18173 On the Sparc, the `.word' directive produces 32 bit values, 18174 instead of the 16 bit values it produces on many other machines. 18175 18176`.xword' 18177 On the Sparc V9 processor, the `.xword' directive produces 64 bit 18178 values. 18179 18180 18181File: as.info, Node: TIC54X-Dependent, Next: TIC6X-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies 18182 181839.42 TIC54X Dependent Features 18184============================== 18185 18186* Menu: 18187 18188* TIC54X-Opts:: Command-line Options 18189* TIC54X-Block:: Blocking 18190* TIC54X-Env:: Environment Settings 18191* TIC54X-Constants:: Constants Syntax 18192* TIC54X-Subsyms:: String Substitution 18193* TIC54X-Locals:: Local Label Syntax 18194* TIC54X-Builtins:: Builtin Assembler Math Functions 18195* TIC54X-Ext:: Extended Addressing Support 18196* TIC54X-Directives:: Directives 18197* TIC54X-Macros:: Macro Features 18198* TIC54X-MMRegs:: Memory-mapped Registers 18199* TIC54X-Syntax:: Syntax 18200 18201 18202File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent 18203 182049.42.1 Options 18205-------------- 18206 18207The TMS320C54X version of `as' has a few machine-dependent options. 18208 18209 You can use the `-mfar-mode' option to enable extended addressing 18210mode. All addresses will be assumed to be > 16 bits, and the 18211appropriate relocation types will be used. This option is equivalent 18212to using the `.far_mode' directive in the assembly code. If you do not 18213use the `-mfar-mode' option, all references will be assumed to be 16 18214bits. This option may be abbreviated to `-mf'. 18215 18216 You can use the `-mcpu' option to specify a particular CPU. This 18217option is equivalent to using the `.version' directive in the assembly 18218code. For recognized CPU codes, see *Note `.version': 18219TIC54X-Directives. The default CPU version is `542'. 18220 18221 You can use the `-merrors-to-file' option to redirect error output 18222to a file (this provided for those deficient environments which don't 18223provide adequate output redirection). This option may be abbreviated to 18224`-me'. 18225 18226 18227File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent 18228 182299.42.2 Blocking 18230--------------- 18231 18232A blocked section or memory block is guaranteed not to cross the 18233blocking boundary (usually a page, or 128 words) if it is smaller than 18234the blocking size, or to start on a page boundary if it is larger than 18235the blocking size. 18236 18237 18238File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent 18239 182409.42.3 Environment Settings 18241--------------------------- 18242 18243`C54XDSP_DIR' and `A_DIR' are semicolon-separated paths which are added 18244to the list of directories normally searched for source and include 18245files. `C54XDSP_DIR' will override `A_DIR'. 18246 18247 18248File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent 18249 182509.42.4 Constants Syntax 18251----------------------- 18252 18253The TIC54X version of `as' allows the following additional constant 18254formats, using a suffix to indicate the radix: 18255 18256 Binary `000000B, 011000b' 18257 Octal `10Q, 224q' 18258 Hexadecimal `45h, 0FH' 18259 18260 18261File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent 18262 182639.42.5 String Substitution 18264-------------------------- 18265 18266A subset of allowable symbols (which we'll call subsyms) may be assigned 18267arbitrary string values. This is roughly equivalent to C preprocessor 18268#define macros. When `as' encounters one of these symbols, the symbol 18269is replaced in the input stream by its string value. Subsym names 18270*must* begin with a letter. 18271 18272 Subsyms may be defined using the `.asg' and `.eval' directives 18273(*Note `.asg': TIC54X-Directives, *Note `.eval': TIC54X-Directives. 18274 18275 Expansion is recursive until a previously encountered symbol is 18276seen, at which point substitution stops. 18277 18278 In this example, x is replaced with SYM2; SYM2 is replaced with 18279SYM1, and SYM1 is replaced with x. At this point, x has already been 18280encountered and the substitution stops. 18281 18282 .asg "x",SYM1 18283 .asg "SYM1",SYM2 18284 .asg "SYM2",x 18285 add x,a ; final code assembled is "add x, a" 18286 18287 Macro parameters are converted to subsyms; a side effect of this is 18288the normal `as' '\ARG' dereferencing syntax is unnecessary. Subsyms 18289defined within a macro will have global scope, unless the `.var' 18290directive is used to identify the subsym as a local macro variable 18291*note `.var': TIC54X-Directives. 18292 18293 Substitution may be forced in situations where replacement might be 18294ambiguous by placing colons on either side of the subsym. The following 18295code: 18296 18297 .eval "10",x 18298 LAB:X: add #x, a 18299 18300 When assembled becomes: 18301 18302 LAB10 add #10, a 18303 18304 Smaller parts of the string assigned to a subsym may be accessed with 18305the following syntax: 18306 18307``:SYMBOL(CHAR_INDEX):'' 18308 Evaluates to a single-character string, the character at 18309 CHAR_INDEX. 18310 18311``:SYMBOL(START,LENGTH):'' 18312 Evaluates to a substring of SYMBOL beginning at START with length 18313 LENGTH. 18314 18315 18316File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent 18317 183189.42.6 Local Labels 18319------------------- 18320 18321Local labels may be defined in two ways: 18322 18323 * $N, where N is a decimal number between 0 and 9 18324 18325 * LABEL?, where LABEL is any legal symbol name. 18326 18327 Local labels thus defined may be redefined or automatically 18328generated. The scope of a local label is based on when it may be 18329undefined or reset. This happens when one of the following situations 18330is encountered: 18331 18332 * .newblock directive *note `.newblock': TIC54X-Directives. 18333 18334 * The current section is changed (.sect, .text, or .data) 18335 18336 * Entering or leaving an included file 18337 18338 * The macro scope where the label was defined is exited 18339 18340 18341File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent 18342 183439.42.7 Math Builtins 18344-------------------- 18345 18346The following built-in functions may be used to generate a 18347floating-point value. All return a floating-point value except `$cvi', 18348`$int', and `$sgn', which return an integer value. 18349 18350``$acos(EXPR)'' 18351 Returns the floating point arccosine of EXPR. 18352 18353``$asin(EXPR)'' 18354 Returns the floating point arcsine of EXPR. 18355 18356``$atan(EXPR)'' 18357 Returns the floating point arctangent of EXPR. 18358 18359``$atan2(EXPR1,EXPR2)'' 18360 Returns the floating point arctangent of EXPR1 / EXPR2. 18361 18362``$ceil(EXPR)'' 18363 Returns the smallest integer not less than EXPR as floating point. 18364 18365``$cosh(EXPR)'' 18366 Returns the floating point hyperbolic cosine of EXPR. 18367 18368``$cos(EXPR)'' 18369 Returns the floating point cosine of EXPR. 18370 18371``$cvf(EXPR)'' 18372 Returns the integer value EXPR converted to floating-point. 18373 18374``$cvi(EXPR)'' 18375 Returns the floating point value EXPR converted to integer. 18376 18377``$exp(EXPR)'' 18378 Returns the floating point value e ^ EXPR. 18379 18380``$fabs(EXPR)'' 18381 Returns the floating point absolute value of EXPR. 18382 18383``$floor(EXPR)'' 18384 Returns the largest integer that is not greater than EXPR as 18385 floating point. 18386 18387``$fmod(EXPR1,EXPR2)'' 18388 Returns the floating point remainder of EXPR1 / EXPR2. 18389 18390``$int(EXPR)'' 18391 Returns 1 if EXPR evaluates to an integer, zero otherwise. 18392 18393``$ldexp(EXPR1,EXPR2)'' 18394 Returns the floating point value EXPR1 * 2 ^ EXPR2. 18395 18396``$log10(EXPR)'' 18397 Returns the base 10 logarithm of EXPR. 18398 18399``$log(EXPR)'' 18400 Returns the natural logarithm of EXPR. 18401 18402``$max(EXPR1,EXPR2)'' 18403 Returns the floating point maximum of EXPR1 and EXPR2. 18404 18405``$min(EXPR1,EXPR2)'' 18406 Returns the floating point minimum of EXPR1 and EXPR2. 18407 18408``$pow(EXPR1,EXPR2)'' 18409 Returns the floating point value EXPR1 ^ EXPR2. 18410 18411``$round(EXPR)'' 18412 Returns the nearest integer to EXPR as a floating point number. 18413 18414``$sgn(EXPR)'' 18415 Returns -1, 0, or 1 based on the sign of EXPR. 18416 18417``$sin(EXPR)'' 18418 Returns the floating point sine of EXPR. 18419 18420``$sinh(EXPR)'' 18421 Returns the floating point hyperbolic sine of EXPR. 18422 18423``$sqrt(EXPR)'' 18424 Returns the floating point square root of EXPR. 18425 18426``$tan(EXPR)'' 18427 Returns the floating point tangent of EXPR. 18428 18429``$tanh(EXPR)'' 18430 Returns the floating point hyperbolic tangent of EXPR. 18431 18432``$trunc(EXPR)'' 18433 Returns the integer value of EXPR truncated towards zero as 18434 floating point. 18435 18436 18437 18438File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent 18439 184409.42.8 Extended Addressing 18441-------------------------- 18442 18443The `LDX' pseudo-op is provided for loading the extended addressing bits 18444of a label or address. For example, if an address `_label' resides in 18445extended program memory, the value of `_label' may be loaded as follows: 18446 ldx #_label,16,a ; loads extended bits of _label 18447 or #_label,a ; loads lower 16 bits of _label 18448 bacc a ; full address is in accumulator A 18449 18450 18451File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent 18452 184539.42.9 Directives 18454----------------- 18455 18456`.align [SIZE]' 18457`.even' 18458 Align the section program counter on the next boundary, based on 18459 SIZE. SIZE may be any power of 2. `.even' is equivalent to 18460 `.align' with a SIZE of 2. 18461 `1' 18462 Align SPC to word boundary 18463 18464 `2' 18465 Align SPC to longword boundary (same as .even) 18466 18467 `128' 18468 Align SPC to page boundary 18469 18470`.asg STRING, NAME' 18471 Assign NAME the string STRING. String replacement is performed on 18472 STRING before assignment. 18473 18474`.eval STRING, NAME' 18475 Evaluate the contents of string STRING and assign the result as a 18476 string to the subsym NAME. String replacement is performed on 18477 STRING before assignment. 18478 18479`.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 18480 Reserve space for SYMBOL in the .bss section. SIZE is in words. 18481 If present, BLOCKING_FLAG indicates the allocated space should be 18482 aligned on a page boundary if it would otherwise cross a page 18483 boundary. If present, ALIGNMENT_FLAG causes the assembler to 18484 allocate SIZE on a long word boundary. 18485 18486`.byte VALUE [,...,VALUE_N]' 18487`.ubyte VALUE [,...,VALUE_N]' 18488`.char VALUE [,...,VALUE_N]' 18489`.uchar VALUE [,...,VALUE_N]' 18490 Place one or more bytes into consecutive words of the current 18491 section. The upper 8 bits of each word is zero-filled. If a 18492 label is used, it points to the word allocated for the first byte 18493 encountered. 18494 18495`.clink ["SECTION_NAME"]' 18496 Set STYP_CLINK flag for this section, which indicates to the 18497 linker that if no symbols from this section are referenced, the 18498 section should not be included in the link. If SECTION_NAME is 18499 omitted, the current section is used. 18500 18501`.c_mode' 18502 TBD. 18503 18504`.copy "FILENAME" | FILENAME' 18505`.include "FILENAME" | FILENAME' 18506 Read source statements from FILENAME. The normal include search 18507 path is used. Normally .copy will cause statements from the 18508 included file to be printed in the assembly listing and .include 18509 will not, but this distinction is not currently implemented. 18510 18511`.data' 18512 Begin assembling code into the .data section. 18513 18514`.double VALUE [,...,VALUE_N]' 18515`.ldouble VALUE [,...,VALUE_N]' 18516`.float VALUE [,...,VALUE_N]' 18517`.xfloat VALUE [,...,VALUE_N]' 18518 Place an IEEE single-precision floating-point representation of 18519 one or more floating-point values into the current section. All 18520 but `.xfloat' align the result on a longword boundary. Values are 18521 stored most-significant word first. 18522 18523`.drlist' 18524`.drnolist' 18525 Control printing of directives to the listing file. Ignored. 18526 18527`.emsg STRING' 18528`.mmsg STRING' 18529`.wmsg STRING' 18530 Emit a user-defined error, message, or warning, respectively. 18531 18532`.far_mode' 18533 Use extended addressing when assembling statements. This should 18534 appear only once per file, and is equivalent to the -mfar-mode 18535 option *note `-mfar-mode': TIC54X-Opts. 18536 18537`.fclist' 18538`.fcnolist' 18539 Control printing of false conditional blocks to the listing file. 18540 18541`.field VALUE [,SIZE]' 18542 Initialize a bitfield of SIZE bits in the current section. If 18543 VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16 18544 bits. If VALUE does not fit into SIZE bits, the value will be 18545 truncated. Successive `.field' directives will pack starting at 18546 the current word, filling the most significant bits first, and 18547 aligning to the start of the next word if the field size does not 18548 fit into the space remaining in the current word. A `.align' 18549 directive with an operand of 1 will force the next `.field' 18550 directive to begin packing into a new word. If a label is used, it 18551 points to the word that contains the specified field. 18552 18553`.global SYMBOL [,...,SYMBOL_N]' 18554`.def SYMBOL [,...,SYMBOL_N]' 18555`.ref SYMBOL [,...,SYMBOL_N]' 18556 `.def' nominally identifies a symbol defined in the current file 18557 and available to other files. `.ref' identifies a symbol used in 18558 the current file but defined elsewhere. Both map to the standard 18559 `.global' directive. 18560 18561`.half VALUE [,...,VALUE_N]' 18562`.uhalf VALUE [,...,VALUE_N]' 18563`.short VALUE [,...,VALUE_N]' 18564`.ushort VALUE [,...,VALUE_N]' 18565`.int VALUE [,...,VALUE_N]' 18566`.uint VALUE [,...,VALUE_N]' 18567`.word VALUE [,...,VALUE_N]' 18568`.uword VALUE [,...,VALUE_N]' 18569 Place one or more values into consecutive words of the current 18570 section. If a label is used, it points to the word allocated for 18571 the first value encountered. 18572 18573`.label SYMBOL' 18574 Define a special SYMBOL to refer to the load time address of the 18575 current section program counter. 18576 18577`.length' 18578`.width' 18579 Set the page length and width of the output listing file. Ignored. 18580 18581`.list' 18582`.nolist' 18583 Control whether the source listing is printed. Ignored. 18584 18585`.long VALUE [,...,VALUE_N]' 18586`.ulong VALUE [,...,VALUE_N]' 18587`.xlong VALUE [,...,VALUE_N]' 18588 Place one or more 32-bit values into consecutive words in the 18589 current section. The most significant word is stored first. 18590 `.long' and `.ulong' align the result on a longword boundary; 18591 `xlong' does not. 18592 18593`.loop [COUNT]' 18594`.break [CONDITION]' 18595`.endloop' 18596 Repeatedly assemble a block of code. `.loop' begins the block, and 18597 `.endloop' marks its termination. COUNT defaults to 1024, and 18598 indicates the number of times the block should be repeated. 18599 `.break' terminates the loop so that assembly begins after the 18600 `.endloop' directive. The optional CONDITION will cause the loop 18601 to terminate only if it evaluates to zero. 18602 18603`MACRO_NAME .macro [PARAM1][,...PARAM_N]' 18604`[.mexit]' 18605`.endm' 18606 See the section on macros for more explanation (*Note 18607 TIC54X-Macros::. 18608 18609`.mlib "FILENAME" | FILENAME' 18610 Load the macro library FILENAME. FILENAME must be an archived 18611 library (BFD ar-compatible) of text files, expected to contain 18612 only macro definitions. The standard include search path is used. 18613 18614`.mlist' 18615`.mnolist' 18616 Control whether to include macro and loop block expansions in the 18617 listing output. Ignored. 18618 18619`.mmregs' 18620 Define global symbolic names for the 'c54x registers. Supposedly 18621 equivalent to executing `.set' directives for each register with 18622 its memory-mapped value, but in reality is provided only for 18623 compatibility and does nothing. 18624 18625`.newblock' 18626 This directive resets any TIC54X local labels currently defined. 18627 Normal `as' local labels are unaffected. 18628 18629`.option OPTION_LIST' 18630 Set listing options. Ignored. 18631 18632`.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]' 18633 Designate SECTION_NAME for blocking. Blocking guarantees that a 18634 section will start on a page boundary (128 words) if it would 18635 otherwise cross a page boundary. Only initialized sections may be 18636 designated with this directive. See also *Note TIC54X-Block::. 18637 18638`.sect "SECTION_NAME"' 18639 Define a named initialized section and make it the current section. 18640 18641`SYMBOL .set "VALUE"' 18642`SYMBOL .equ "VALUE"' 18643 Equate a constant VALUE to a SYMBOL, which is placed in the symbol 18644 table. SYMBOL may not be previously defined. 18645 18646`.space SIZE_IN_BITS' 18647`.bes SIZE_IN_BITS' 18648 Reserve the given number of bits in the current section and 18649 zero-fill them. If a label is used with `.space', it points to the 18650 *first* word reserved. With `.bes', the label points to the 18651 *last* word reserved. 18652 18653`.sslist' 18654`.ssnolist' 18655 Controls the inclusion of subsym replacement in the listing 18656 output. Ignored. 18657 18658`.string "STRING" [,...,"STRING_N"]' 18659`.pstring "STRING" [,...,"STRING_N"]' 18660 Place 8-bit characters from STRING into the current section. 18661 `.string' zero-fills the upper 8 bits of each word, while 18662 `.pstring' puts two characters into each word, filling the 18663 most-significant bits first. Unused space is zero-filled. If a 18664 label is used, it points to the first word initialized. 18665 18666`[STAG] .struct [OFFSET]' 18667`[NAME_1] element [COUNT_1]' 18668`[NAME_2] element [COUNT_2]' 18669`[TNAME] .tag STAGX [TCOUNT]' 18670`...' 18671`[NAME_N] element [COUNT_N]' 18672`[SSIZE] .endstruct' 18673`LABEL .tag [STAG]' 18674 Assign symbolic offsets to the elements of a structure. STAG 18675 defines a symbol to use to reference the structure. OFFSET 18676 indicates a starting value to use for the first element 18677 encountered; otherwise it defaults to zero. Each element can have 18678 a named offset, NAME, which is a symbol assigned the value of the 18679 element's offset into the structure. If STAG is missing, these 18680 become global symbols. COUNT adjusts the offset that many times, 18681 as if `element' were an array. `element' may be one of `.byte', 18682 `.word', `.long', `.float', or any equivalent of those, and the 18683 structure offset is adjusted accordingly. `.field' and `.string' 18684 are also allowed; the size of `.field' is one bit, and `.string' 18685 is considered to be one word in size. Only element descriptors, 18686 structure/union tags, `.align' and conditional assembly directives 18687 are allowed within `.struct'/`.endstruct'. `.align' aligns member 18688 offsets to word boundaries only. SSIZE, if provided, will always 18689 be assigned the size of the structure. 18690 18691 The `.tag' directive, in addition to being used to define a 18692 structure/union element within a structure, may be used to apply a 18693 structure to a symbol. Once applied to LABEL, the individual 18694 structure elements may be applied to LABEL to produce the desired 18695 offsets using LABEL as the structure base. 18696 18697`.tab' 18698 Set the tab size in the output listing. Ignored. 18699 18700`[UTAG] .union' 18701`[NAME_1] element [COUNT_1]' 18702`[NAME_2] element [COUNT_2]' 18703`[TNAME] .tag UTAGX[,TCOUNT]' 18704`...' 18705`[NAME_N] element [COUNT_N]' 18706`[USIZE] .endstruct' 18707`LABEL .tag [UTAG]' 18708 Similar to `.struct', but the offset after each element is reset to 18709 zero, and the USIZE is set to the maximum of all defined elements. 18710 Starting offset for the union is always zero. 18711 18712`[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 18713 Reserve space for variables in a named, uninitialized section 18714 (similar to .bss). `.usect' allows definitions sections 18715 independent of .bss. SYMBOL points to the first location reserved 18716 by this allocation. The symbol may be used as a variable name. 18717 SIZE is the allocated size in words. BLOCKING_FLAG indicates 18718 whether to block this section on a page boundary (128 words) 18719 (*note TIC54X-Block::). ALIGNMENT FLAG indicates whether the 18720 section should be longword-aligned. 18721 18722`.var SYM[,..., SYM_N]' 18723 Define a subsym to be a local variable within a macro. See *Note 18724 TIC54X-Macros::. 18725 18726`.version VERSION' 18727 Set which processor to build instructions for. Though the 18728 following values are accepted, the op is ignored. 18729 `541' 18730 `542' 18731 `543' 18732 `545' 18733 `545LP' 18734 `546LP' 18735 `548' 18736 `549' 18737 18738 18739File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent 18740 187419.42.10 Macros 18742-------------- 18743 18744Macros do not require explicit dereferencing of arguments (i.e., \ARG). 18745 18746 During macro expansion, the macro parameters are converted to 18747subsyms. If the number of arguments passed the macro invocation 18748exceeds the number of parameters defined, the last parameter is 18749assigned the string equivalent of all remaining arguments. If fewer 18750arguments are given than parameters, the missing parameters are 18751assigned empty strings. To include a comma in an argument, you must 18752enclose the argument in quotes. 18753 18754 The following built-in subsym functions allow examination of the 18755string value of subsyms (or ordinary strings). The arguments are 18756strings unless otherwise indicated (subsyms passed as args will be 18757replaced by the strings they represent). 18758``$symlen(STR)'' 18759 Returns the length of STR. 18760 18761``$symcmp(STR1,STR2)'' 18762 Returns 0 if STR1 == STR2, non-zero otherwise. 18763 18764``$firstch(STR,CH)'' 18765 Returns index of the first occurrence of character constant CH in 18766 STR. 18767 18768``$lastch(STR,CH)'' 18769 Returns index of the last occurrence of character constant CH in 18770 STR. 18771 18772``$isdefed(SYMBOL)'' 18773 Returns zero if the symbol SYMBOL is not in the symbol table, 18774 non-zero otherwise. 18775 18776``$ismember(SYMBOL,LIST)'' 18777 Assign the first member of comma-separated string LIST to SYMBOL; 18778 LIST is reassigned the remainder of the list. Returns zero if 18779 LIST is a null string. Both arguments must be subsyms. 18780 18781``$iscons(EXPR)'' 18782 Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, 18783 4 if a character, 5 if decimal, and zero if not an integer. 18784 18785``$isname(NAME)'' 18786 Returns 1 if NAME is a valid symbol name, zero otherwise. 18787 18788``$isreg(REG)'' 18789 Returns 1 if REG is a valid predefined register name (AR0-AR7 18790 only). 18791 18792``$structsz(STAG)'' 18793 Returns the size of the structure or union represented by STAG. 18794 18795``$structacc(STAG)'' 18796 Returns the reference point of the structure or union represented 18797 by STAG. Always returns zero. 18798 18799 18800 18801File: as.info, Node: TIC54X-MMRegs, Next: TIC54X-Syntax, Prev: TIC54X-Macros, Up: TIC54X-Dependent 18802 188039.42.11 Memory-mapped Registers 18804------------------------------- 18805 18806The following symbols are recognized as memory-mapped registers: 18807 18808 18809 18810File: as.info, Node: TIC54X-Syntax, Prev: TIC54X-MMRegs, Up: TIC54X-Dependent 18811 188129.42.12 TIC54X Syntax 18813--------------------- 18814 18815* Menu: 18816 18817* TIC54X-Chars:: Special Characters 18818 18819 18820File: as.info, Node: TIC54X-Chars, Up: TIC54X-Syntax 18821 188229.42.12.1 Special Characters 18823............................ 18824 18825The presence of a `;' appearing anywhere on a line indicates the start 18826of a comment that extends to the end of that line. 18827 18828 If a `#' appears as the first character of a line then the whole 18829line is treated as a comment, but in this case the line can also be a 18830logical line number directive (*note Comments::) or a preprocessor 18831control command (*note Preprocessing::). 18832 18833 The presence of an asterisk (`*') at the start of a line also 18834indicates a comment that extends to the end of that line. 18835 18836 The TIC54X assembler does not currently support a line separator 18837character. 18838 18839 18840File: as.info, Node: TIC6X-Dependent, Next: TILE-Gx-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies 18841 188429.43 TIC6X Dependent Features 18843============================= 18844 18845* Menu: 18846 18847* TIC6X Options:: Options 18848* TIC6X Syntax:: Syntax 18849* TIC6X Directives:: Directives 18850 18851 18852File: as.info, Node: TIC6X Options, Next: TIC6X Syntax, Up: TIC6X-Dependent 18853 188549.43.1 TIC6X Options 18855-------------------- 18856 18857`-march=ARCH' 18858 Enable (only) instructions from architecture ARCH. By default, 18859 all instructions are permitted. 18860 18861 The following values of ARCH are accepted: `c62x', `c64x', 18862 `c64x+', `c67x', `c67x+', `c674x'. 18863 18864`-mdsbt' 18865`-mno-dsbt' 18866 The `-mdsbt' option causes the assembler to generate the 18867 `Tag_ABI_DSBT' attribute with a value of 1, indicating that the 18868 code is using DSBT addressing. The `-mno-dsbt' option, the 18869 default, causes the tag to have a value of 0, indicating that the 18870 code does not use DSBT addressing. The linker will emit a warning 18871 if objects of different type (DSBT and non-DSBT) are linked 18872 together. 18873 18874`-mpid=no' 18875`-mpid=near' 18876`-mpid=far' 18877 The `-mpid=' option causes the assembler to generate the 18878 `Tag_ABI_PID' attribute with a value indicating the form of data 18879 addressing used by the code. `-mpid=no', the default, indicates 18880 position-dependent data addressing, `-mpid=near' indicates 18881 position-independent addressing with GOT accesses using near DP 18882 addressing, and `-mpid=far' indicates position-independent 18883 addressing with GOT accesses using far DP addressing. The linker 18884 will emit a warning if objects built with different settings of 18885 this option are linked together. 18886 18887`-mpic' 18888`-mno-pic' 18889 The `-mpic' option causes the assembler to generate the 18890 `Tag_ABI_PIC' attribute with a value of 1, indicating that the 18891 code is using position-independent code addressing, The 18892 `-mno-pic' option, the default, causes the tag to have a value of 18893 0, indicating position-dependent code addressing. The linker will 18894 emit a warning if objects of different type (position-dependent and 18895 position-independent) are linked together. 18896 18897`-mbig-endian' 18898`-mlittle-endian' 18899 Generate code for the specified endianness. The default is 18900 little-endian. 18901 18902 18903 18904File: as.info, Node: TIC6X Syntax, Next: TIC6X Directives, Prev: TIC6X Options, Up: TIC6X-Dependent 18905 189069.43.2 TIC6X Syntax 18907------------------- 18908 18909The presence of a `;' on a line indicates the start of a comment that 18910extends to the end of the current line. If a `#' or `*' appears as the 18911first character of a line, the whole line is treated as a comment. 18912Note that if a line starts with a `#' character then it can also be a 18913logical line number directive (*note Comments::) or a preprocessor 18914control command (*note Preprocessing::). 18915 18916 The `@' character can be used instead of a newline to separate 18917statements. 18918 18919 Instruction, register and functional unit names are case-insensitive. 18920`as' requires fully-specified functional unit names, such as `.S1', 18921`.L1X' or `.D1T2', on all instructions using a functional unit. 18922 18923 For some instructions, there may be syntactic ambiguity between 18924register or functional unit names and the names of labels or other 18925symbols. To avoid this, enclose the ambiguous symbol name in 18926parentheses; register and functional unit names may not be enclosed in 18927parentheses. 18928 18929 18930File: as.info, Node: TIC6X Directives, Prev: TIC6X Syntax, Up: TIC6X-Dependent 18931 189329.43.3 TIC6X Directives 18933----------------------- 18934 18935Directives controlling the set of instructions accepted by the 18936assembler have effect for instructions between the directive and any 18937subsequent directive overriding it. 18938 18939`.arch ARCH' 18940 This has the same effect as `-march=ARCH'. 18941 18942`.cantunwind' 18943 Prevents unwinding through the current function. No personality 18944 routine or exception table data is required or permitted. 18945 18946 If this is not specified then frame unwinding information will be 18947 constructed from CFI directives. *note CFI directives::. 18948 18949`.c6xabi_attribute TAG, VALUE' 18950 Set the C6000 EABI build attribute TAG to VALUE. 18951 18952 The TAG is either an attribute number or one of `Tag_ISA', 18953 `Tag_ABI_wchar_t', `Tag_ABI_stack_align_needed', 18954 `Tag_ABI_stack_align_preserved', `Tag_ABI_DSBT', `Tag_ABI_PID', 18955 `Tag_ABI_PIC', `TAG_ABI_array_object_alignment', 18956 `TAG_ABI_array_object_align_expected', `Tag_ABI_compatibility' and 18957 `Tag_ABI_conformance'. The VALUE is either a `number', 18958 `"string"', or `number, "string"' depending on the tag. 18959 18960`.ehtype SYMBOL' 18961 Output an exception type table reference to SYMBOL. 18962 18963`.endp' 18964 Marks the end of and exception table or function. If preceeded by 18965 a `.handlerdata' directive then this also switched back to the 18966 previous text section. 18967 18968`.handlerdata' 18969 Marks the end of the current function, and the start of the 18970 exception table entry for that function. Anything between this 18971 directive and the `.endp' directive will be added to the exception 18972 table entry. 18973 18974 Must be preceded by a CFI block containing a `.cfi_lsda' directive. 18975 18976`.nocmp' 18977 Disallow use of C64x+ compact instructions in the current text 18978 section. 18979 18980`.personalityindex INDEX' 18981 Sets the personality routine for the current function to the ABI 18982 specified compact routine number INDEX 18983 18984`.personality NAME' 18985 Sets the personality routine for the current function to NAME. 18986 18987`.scomm SYMBOL, SIZE, ALIGN' 18988 Like `.comm', creating a common symbol SYMBOL with size SIZE and 18989 alignment ALIGN, but unlike when using `.comm', this symbol will 18990 be placed into the small BSS section by the linker. 18991 18992 18993 18994File: as.info, Node: TILE-Gx-Dependent, Next: TILEPro-Dependent, Prev: TIC6X-Dependent, Up: Machine Dependencies 18995 189969.44 TILE-Gx Dependent Features 18997=============================== 18998 18999* Menu: 19000 19001* TILE-Gx Options:: TILE-Gx Options 19002* TILE-Gx Syntax:: TILE-Gx Syntax 19003* TILE-Gx Directives:: TILE-Gx Directives 19004 19005 19006File: as.info, Node: TILE-Gx Options, Next: TILE-Gx Syntax, Up: TILE-Gx-Dependent 19007 190089.44.1 Options 19009-------------- 19010 19011The following table lists all available TILE-Gx specific options: 19012 19013`-m32 | -m64' 19014 Select the word size, either 32 bits or 64 bits. 19015 19016`-EB | -EL' 19017 Select the endianness, either big-endian (-EB) or little-endian 19018 (-EL). 19019 19020 19021 19022File: as.info, Node: TILE-Gx Syntax, Next: TILE-Gx Directives, Prev: TILE-Gx Options, Up: TILE-Gx-Dependent 19023 190249.44.2 Syntax 19025------------- 19026 19027Block comments are delimited by `/*' and `*/'. End of line comments 19028may be introduced by `#'. 19029 19030 Instructions consist of a leading opcode or macro name followed by 19031whitespace and an optional comma-separated list of operands: 19032 19033 OPCODE [OPERAND, ...] 19034 19035 Instructions must be separated by a newline or semicolon. 19036 19037 There are two ways to write code: either write naked instructions, 19038which the assembler is free to combine into VLIW bundles, or specify 19039the VLIW bundles explicitly. 19040 19041 Bundles are specified using curly braces: 19042 19043 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } 19044 19045 A bundle can span multiple lines. If you want to put multiple 19046instructions on a line, whether in a bundle or not, you need to 19047separate them with semicolons as in this example. 19048 19049 A bundle may contain one or more instructions, up to the limit 19050specified by the ISA (currently three). If fewer instructions are 19051specified than the hardware supports in a bundle, the assembler inserts 19052`fnop' instructions automatically. 19053 19054 The assembler will prefer to preserve the ordering of instructions 19055within the bundle, putting the first instruction in a lower-numbered 19056pipeline than the next one, etc. This fact, combined with the optional 19057use of explicit `fnop' or `nop' instructions, allows precise control 19058over which pipeline executes each instruction. 19059 19060 If the instructions cannot be bundled in the listed order, the 19061assembler will automatically try to find a valid pipeline assignment. 19062If there is no way to bundle the instructions together, the assembler 19063reports an error. 19064 19065 The assembler does not yet auto-bundle (automatically combine 19066multiple instructions into one bundle), but it reserves the right to do 19067so in the future. If you want to force an instruction to run by 19068itself, put it in a bundle explicitly with curly braces and use `nop' 19069instructions (not `fnop') to fill the remaining pipeline slots in that 19070bundle. 19071 19072* Menu: 19073 19074* TILE-Gx Opcodes:: Opcode Naming Conventions. 19075* TILE-Gx Registers:: Register Naming. 19076* TILE-Gx Modifiers:: Symbolic Operand Modifiers. 19077 19078 19079File: as.info, Node: TILE-Gx Opcodes, Next: TILE-Gx Registers, Up: TILE-Gx Syntax 19080 190819.44.2.1 Opcode Names 19082..................... 19083 19084For a complete list of opcodes and descriptions of their semantics, see 19085`TILE-Gx Instruction Set Architecture', available upon request at 19086www.tilera.com. 19087 19088 19089File: as.info, Node: TILE-Gx Registers, Next: TILE-Gx Modifiers, Prev: TILE-Gx Opcodes, Up: TILE-Gx Syntax 19090 190919.44.2.2 Register Names 19092....................... 19093 19094General-purpose registers are represented by predefined symbols of the 19095form `rN', where N represents a number between `0' and `63'. However, 19096the following registers have canonical names that must be used instead: 19097 19098`r54' 19099 sp 19100 19101`r55' 19102 lr 19103 19104`r56' 19105 sn 19106 19107`r57' 19108 idn0 19109 19110`r58' 19111 idn1 19112 19113`r59' 19114 udn0 19115 19116`r60' 19117 udn1 19118 19119`r61' 19120 udn2 19121 19122`r62' 19123 udn3 19124 19125`r63' 19126 zero 19127 19128 19129 The assembler will emit a warning if a numeric name is used instead 19130of the non-numeric name. The `.no_require_canonical_reg_names' 19131assembler pseudo-op turns off this warning. 19132`.require_canonical_reg_names' turns it back on. 19133 19134 19135File: as.info, Node: TILE-Gx Modifiers, Prev: TILE-Gx Registers, Up: TILE-Gx Syntax 19136 191379.44.2.3 Symbolic Operand Modifiers 19138................................... 19139 19140The assembler supports several modifiers when using symbol addresses in 19141TILE-Gx instruction operands. The general syntax is the following: 19142 19143 modifier(symbol) 19144 19145 The following modifiers are supported: 19146 19147`hw0' 19148 This modifier is used to load bits 0-15 of the symbol's address. 19149 19150`hw1' 19151 This modifier is used to load bits 16-31 of the symbol's address. 19152 19153`hw2' 19154 This modifier is used to load bits 32-47 of the symbol's address. 19155 19156`hw3' 19157 This modifier is used to load bits 48-63 of the symbol's address. 19158 19159`hw0_last' 19160 This modifier yields the same value as `hw0', but it also checks 19161 that the value does not overflow. 19162 19163`hw1_last' 19164 This modifier yields the same value as `hw1', but it also checks 19165 that the value does not overflow. 19166 19167`hw2_last' 19168 This modifier yields the same value as `hw2', but it also checks 19169 that the value does not overflow. 19170 19171 A 48-bit symbolic value is constructed by using the following 19172 idiom: 19173 19174 moveli r0, hw2_last(sym) 19175 shl16insli r0, r0, hw1(sym) 19176 shl16insli r0, r0, hw0(sym) 19177 19178`hw0_got' 19179 This modifier is used to load bits 0-15 of the symbol's offset in 19180 the GOT entry corresponding to the symbol. 19181 19182`hw0_last_got' 19183 This modifier yields the same value as `hw0_got', but it also 19184 checks that the value does not overflow. 19185 19186`hw1_last_got' 19187 This modifier is used to load bits 16-31 of the symbol's offset in 19188 the GOT entry corresponding to the symbol, and it also checks that 19189 the value does not overflow. 19190 19191`plt' 19192 This modifier is used for function symbols. It causes a 19193 _procedure linkage table_, an array of code stubs, to be created 19194 at the time the shared object is created or linked against, 19195 together with a global offset table entry. The value is a 19196 pc-relative offset to the corresponding stub code in the procedure 19197 linkage table. This arrangement causes the run-time symbol 19198 resolver to be called to look up and set the value of the symbol 19199 the first time the function is called (at latest; depending 19200 environment variables). It is only safe to leave the symbol 19201 unresolved this way if all references are function calls. 19202 19203`hw0_plt' 19204 This modifier is used to load bits 0-15 of the pc-relative address 19205 of a plt entry. 19206 19207`hw1_plt' 19208 This modifier is used to load bits 16-31 of the pc-relative 19209 address of a plt entry. 19210 19211`hw1_last_plt' 19212 This modifier yields the same value as `hw1_plt', but it also 19213 checks that the value does not overflow. 19214 19215`hw2_last_plt' 19216 This modifier is used to load bits 32-47 of the pc-relative 19217 address of a plt entry, and it also checks that the value does not 19218 overflow. 19219 19220`hw0_tls_gd' 19221 This modifier is used to load bits 0-15 of the offset of the GOT 19222 entry of the symbol's TLS descriptor, to be used for 19223 general-dynamic TLS accesses. 19224 19225`hw0_last_tls_gd' 19226 This modifier yields the same value as `hw0_tls_gd', but it also 19227 checks that the value does not overflow. 19228 19229`hw1_last_tls_gd' 19230 This modifier is used to load bits 16-31 of the offset of the GOT 19231 entry of the symbol's TLS descriptor, to be used for 19232 general-dynamic TLS accesses. It also checks that the value does 19233 not overflow. 19234 19235`hw0_tls_ie' 19236 This modifier is used to load bits 0-15 of the offset of the GOT 19237 entry containing the offset of the symbol's address from the TCB, 19238 to be used for initial-exec TLS accesses. 19239 19240`hw0_last_tls_ie' 19241 This modifier yields the same value as `hw0_tls_ie', but it also 19242 checks that the value does not overflow. 19243 19244`hw1_last_tls_ie' 19245 This modifier is used to load bits 16-31 of the offset of the GOT 19246 entry containing the offset of the symbol's address from the TCB, 19247 to be used for initial-exec TLS accesses. It also checks that the 19248 value does not overflow. 19249 19250`hw0_tls_le' 19251 This modifier is used to load bits 0-15 of the offset of the 19252 symbol's address from the TCB, to be used for local-exec TLS 19253 accesses. 19254 19255`hw0_last_tls_le' 19256 This modifier yields the same value as `hw0_tls_le', but it also 19257 checks that the value does not overflow. 19258 19259`hw1_last_tls_le' 19260 This modifier is used to load bits 16-31 of the offset of the 19261 symbol's address from the TCB, to be used for local-exec TLS 19262 accesses. It also checks that the value does not overflow. 19263 19264`tls_gd_call' 19265 This modifier is used to tag an instrution as the "call" part of a 19266 calling sequence for a TLS GD reference of its operand. 19267 19268`tls_gd_add' 19269 This modifier is used to tag an instruction as the "add" part of a 19270 calling sequence for a TLS GD reference of its operand. 19271 19272`tls_ie_load' 19273 This modifier is used to tag an instruction as the "load" part of a 19274 calling sequence for a TLS IE reference of its operand. 19275 19276 19277 19278File: as.info, Node: TILE-Gx Directives, Prev: TILE-Gx Syntax, Up: TILE-Gx-Dependent 19279 192809.44.3 TILE-Gx Directives 19281------------------------- 19282 19283`.align EXPRESSION [, EXPRESSION]' 19284 This is the generic .ALIGN directive. The first argument is the 19285 requested alignment in bytes. 19286 19287`.allow_suspicious_bundles' 19288 Turns on error checking for combinations of instructions in a 19289 bundle that probably indicate a programming error. This is on by 19290 default. 19291 19292`.no_allow_suspicious_bundles' 19293 Turns off error checking for combinations of instructions in a 19294 bundle that probably indicate a programming error. 19295 19296`.require_canonical_reg_names' 19297 Require that canonical register names be used, and emit a warning 19298 if the numeric names are used. This is on by default. 19299 19300`.no_require_canonical_reg_names' 19301 Permit the use of numeric names for registers that have canonical 19302 names. 19303 19304 19305 19306File: as.info, Node: TILEPro-Dependent, Next: V850-Dependent, Prev: TILE-Gx-Dependent, Up: Machine Dependencies 19307 193089.45 TILEPro Dependent Features 19309=============================== 19310 19311* Menu: 19312 19313* TILEPro Options:: TILEPro Options 19314* TILEPro Syntax:: TILEPro Syntax 19315* TILEPro Directives:: TILEPro Directives 19316 19317 19318File: as.info, Node: TILEPro Options, Next: TILEPro Syntax, Up: TILEPro-Dependent 19319 193209.45.1 Options 19321-------------- 19322 19323`as' has no machine-dependent command-line options for TILEPro. 19324 19325 19326File: as.info, Node: TILEPro Syntax, Next: TILEPro Directives, Prev: TILEPro Options, Up: TILEPro-Dependent 19327 193289.45.2 Syntax 19329------------- 19330 19331Block comments are delimited by `/*' and `*/'. End of line comments 19332may be introduced by `#'. 19333 19334 Instructions consist of a leading opcode or macro name followed by 19335whitespace and an optional comma-separated list of operands: 19336 19337 OPCODE [OPERAND, ...] 19338 19339 Instructions must be separated by a newline or semicolon. 19340 19341 There are two ways to write code: either write naked instructions, 19342which the assembler is free to combine into VLIW bundles, or specify 19343the VLIW bundles explicitly. 19344 19345 Bundles are specified using curly braces: 19346 19347 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } 19348 19349 A bundle can span multiple lines. If you want to put multiple 19350instructions on a line, whether in a bundle or not, you need to 19351separate them with semicolons as in this example. 19352 19353 A bundle may contain one or more instructions, up to the limit 19354specified by the ISA (currently three). If fewer instructions are 19355specified than the hardware supports in a bundle, the assembler inserts 19356`fnop' instructions automatically. 19357 19358 The assembler will prefer to preserve the ordering of instructions 19359within the bundle, putting the first instruction in a lower-numbered 19360pipeline than the next one, etc. This fact, combined with the optional 19361use of explicit `fnop' or `nop' instructions, allows precise control 19362over which pipeline executes each instruction. 19363 19364 If the instructions cannot be bundled in the listed order, the 19365assembler will automatically try to find a valid pipeline assignment. 19366If there is no way to bundle the instructions together, the assembler 19367reports an error. 19368 19369 The assembler does not yet auto-bundle (automatically combine 19370multiple instructions into one bundle), but it reserves the right to do 19371so in the future. If you want to force an instruction to run by 19372itself, put it in a bundle explicitly with curly braces and use `nop' 19373instructions (not `fnop') to fill the remaining pipeline slots in that 19374bundle. 19375 19376* Menu: 19377 19378* TILEPro Opcodes:: Opcode Naming Conventions. 19379* TILEPro Registers:: Register Naming. 19380* TILEPro Modifiers:: Symbolic Operand Modifiers. 19381 19382 19383File: as.info, Node: TILEPro Opcodes, Next: TILEPro Registers, Up: TILEPro Syntax 19384 193859.45.2.1 Opcode Names 19386..................... 19387 19388For a complete list of opcodes and descriptions of their semantics, see 19389`TILE Processor User Architecture Manual', available upon request at 19390www.tilera.com. 19391 19392 19393File: as.info, Node: TILEPro Registers, Next: TILEPro Modifiers, Prev: TILEPro Opcodes, Up: TILEPro Syntax 19394 193959.45.2.2 Register Names 19396....................... 19397 19398General-purpose registers are represented by predefined symbols of the 19399form `rN', where N represents a number between `0' and `63'. However, 19400the following registers have canonical names that must be used instead: 19401 19402`r54' 19403 sp 19404 19405`r55' 19406 lr 19407 19408`r56' 19409 sn 19410 19411`r57' 19412 idn0 19413 19414`r58' 19415 idn1 19416 19417`r59' 19418 udn0 19419 19420`r60' 19421 udn1 19422 19423`r61' 19424 udn2 19425 19426`r62' 19427 udn3 19428 19429`r63' 19430 zero 19431 19432 19433 The assembler will emit a warning if a numeric name is used instead 19434of the canonical name. The `.no_require_canonical_reg_names' assembler 19435pseudo-op turns off this warning. `.require_canonical_reg_names' turns 19436it back on. 19437 19438 19439File: as.info, Node: TILEPro Modifiers, Prev: TILEPro Registers, Up: TILEPro Syntax 19440 194419.45.2.3 Symbolic Operand Modifiers 19442................................... 19443 19444The assembler supports several modifiers when using symbol addresses in 19445TILEPro instruction operands. The general syntax is the following: 19446 19447 modifier(symbol) 19448 19449 The following modifiers are supported: 19450 19451`lo16' 19452 This modifier is used to load the low 16 bits of the symbol's 19453 address, sign-extended to a 32-bit value (sign-extension allows it 19454 to be range-checked against signed 16 bit immediate operands 19455 without complaint). 19456 19457`hi16' 19458 This modifier is used to load the high 16 bits of the symbol's 19459 address, also sign-extended to a 32-bit value. 19460 19461`ha16' 19462 `ha16(N)' is identical to `hi16(N)', except if `lo16(N)' is 19463 negative it adds one to the `hi16(N)' value. This way `lo16' and 19464 `ha16' can be added to create any 32-bit value using `auli'. For 19465 example, here is how you move an arbitrary 32-bit address into r3: 19466 19467 moveli r3, lo16(sym) 19468 auli r3, r3, ha16(sym) 19469 19470`got' 19471 This modifier is used to load the offset of the GOT entry 19472 corresponding to the symbol. 19473 19474`got_lo16' 19475 This modifier is used to load the sign-extended low 16 bits of the 19476 offset of the GOT entry corresponding to the symbol. 19477 19478`got_hi16' 19479 This modifier is used to load the sign-extended high 16 bits of the 19480 offset of the GOT entry corresponding to the symbol. 19481 19482`got_ha16' 19483 This modifier is like `got_hi16', but it adds one if `got_lo16' of 19484 the input value is negative. 19485 19486`plt' 19487 This modifier is used for function symbols. It causes a 19488 _procedure linkage table_, an array of code stubs, to be created 19489 at the time the shared object is created or linked against, 19490 together with a global offset table entry. The value is a 19491 pc-relative offset to the corresponding stub code in the procedure 19492 linkage table. This arrangement causes the run-time symbol 19493 resolver to be called to look up and set the value of the symbol 19494 the first time the function is called (at latest; depending 19495 environment variables). It is only safe to leave the symbol 19496 unresolved this way if all references are function calls. 19497 19498`tls_gd' 19499 This modifier is used to load the offset of the GOT entry of the 19500 symbol's TLS descriptor, to be used for general-dynamic TLS 19501 accesses. 19502 19503`tls_gd_lo16' 19504 This modifier is used to load the sign-extended low 16 bits of the 19505 offset of the GOT entry of the symbol's TLS descriptor, to be used 19506 for general dynamic TLS accesses. 19507 19508`tls_gd_hi16' 19509 This modifier is used to load the sign-extended high 16 bits of the 19510 offset of the GOT entry of the symbol's TLS descriptor, to be used 19511 for general dynamic TLS accesses. 19512 19513`tls_gd_ha16' 19514 This modifier is like `tls_gd_hi16', but it adds one to the value 19515 if `tls_gd_lo16' of the input value is negative. 19516 19517`tls_ie' 19518 This modifier is used to load the offset of the GOT entry 19519 containing the offset of the symbol's address from the TCB, to be 19520 used for initial-exec TLS accesses. 19521 19522`tls_ie_lo16' 19523 This modifier is used to load the low 16 bits of the offset of the 19524 GOT entry containing the offset of the symbol's address from the 19525 TCB, to be used for initial-exec TLS accesses. 19526 19527`tls_ie_hi16' 19528 This modifier is used to load the high 16 bits of the offset of the 19529 GOT entry containing the offset of the symbol's address from the 19530 TCB, to be used for initial-exec TLS accesses. 19531 19532`tls_ie_ha16' 19533 This modifier is like `tls_ie_hi16', but it adds one to the value 19534 if `tls_ie_lo16' of the input value is negative. 19535 19536`tls_le' 19537 This modifier is used to load the offset of the symbol's address 19538 from the TCB, to be used for local-exec TLS accesses. 19539 19540`tls_le_lo16' 19541 This modifier is used to load the low 16 bits of the offset of the 19542 symbol's address from the TCB, to be used for local-exec TLS 19543 accesses. 19544 19545`tls_le_hi16' 19546 This modifier is used to load the high 16 bits of the offset of the 19547 symbol's address from the TCB, to be used for local-exec TLS 19548 accesses. 19549 19550`tls_le_ha16' 19551 This modifier is like `tls_le_hi16', but it adds one to the value 19552 if `tls_le_lo16' of the input value is negative. 19553 19554`tls_gd_call' 19555 This modifier is used to tag an instrution as the "call" part of a 19556 calling sequence for a TLS GD reference of its operand. 19557 19558`tls_gd_add' 19559 This modifier is used to tag an instruction as the "add" part of a 19560 calling sequence for a TLS GD reference of its operand. 19561 19562`tls_ie_load' 19563 This modifier is used to tag an instruction as the "load" part of a 19564 calling sequence for a TLS IE reference of its operand. 19565 19566 19567 19568File: as.info, Node: TILEPro Directives, Prev: TILEPro Syntax, Up: TILEPro-Dependent 19569 195709.45.3 TILEPro Directives 19571------------------------- 19572 19573`.align EXPRESSION [, EXPRESSION]' 19574 This is the generic .ALIGN directive. The first argument is the 19575 requested alignment in bytes. 19576 19577`.allow_suspicious_bundles' 19578 Turns on error checking for combinations of instructions in a 19579 bundle that probably indicate a programming error. This is on by 19580 default. 19581 19582`.no_allow_suspicious_bundles' 19583 Turns off error checking for combinations of instructions in a 19584 bundle that probably indicate a programming error. 19585 19586`.require_canonical_reg_names' 19587 Require that canonical register names be used, and emit a warning 19588 if the numeric names are used. This is on by default. 19589 19590`.no_require_canonical_reg_names' 19591 Permit the use of numeric names for registers that have canonical 19592 names. 19593 19594 19595 19596File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies 19597 195989.46 Z80 Dependent Features 19599=========================== 19600 19601* Menu: 19602 19603* Z80 Options:: Options 19604* Z80 Syntax:: Syntax 19605* Z80 Floating Point:: Floating Point 19606* Z80 Directives:: Z80 Machine Directives 19607* Z80 Opcodes:: Opcodes 19608 19609 19610File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent 19611 196129.46.1 Options 19613-------------- 19614 19615The Zilog Z80 and Ascii R800 version of `as' have a few machine 19616dependent options. 19617`-z80' 19618 Produce code for the Z80 processor. There are additional options to 19619 request warnings and error messages for undocumented instructions. 19620 19621`-ignore-undocumented-instructions' 19622`-Wnud' 19623 Silently assemble undocumented Z80-instructions that have been 19624 adopted as documented R800-instructions. 19625 19626`-ignore-unportable-instructions' 19627`-Wnup' 19628 Silently assemble all undocumented Z80-instructions. 19629 19630`-warn-undocumented-instructions' 19631`-Wud' 19632 Issue warnings for undocumented Z80-instructions that work on 19633 R800, do not assemble other undocumented instructions without 19634 warning. 19635 19636`-warn-unportable-instructions' 19637`-Wup' 19638 Issue warnings for other undocumented Z80-instructions, do not 19639 treat any undocumented instructions as errors. 19640 19641`-forbid-undocumented-instructions' 19642`-Fud' 19643 Treat all undocumented z80-instructions as errors. 19644 19645`-forbid-unportable-instructions' 19646`-Fup' 19647 Treat undocumented z80-instructions that do not work on R800 as 19648 errors. 19649 19650`-r800' 19651 Produce code for the R800 processor. The assembler does not support 19652 undocumented instructions for the R800. In line with common 19653 practice, `as' uses Z80 instruction names for the R800 processor, 19654 as far as they exist. 19655 19656 19657File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent 19658 196599.46.2 Syntax 19660------------- 19661 19662The assembler syntax closely follows the 'Z80 family CPU User Manual' by 19663Zilog. In expressions a single `=' may be used as "is equal to" 19664comparison operator. 19665 19666 Suffices can be used to indicate the radix of integer constants; `H' 19667or `h' for hexadecimal, `D' or `d' for decimal, `Q', `O', `q' or `o' 19668for octal, and `B' for binary. 19669 19670 The suffix `b' denotes a backreference to local label. 19671 19672* Menu: 19673 19674* Z80-Chars:: Special Characters 19675* Z80-Regs:: Register Names 19676* Z80-Case:: Case Sensitivity 19677 19678 19679File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax 19680 196819.46.2.1 Special Characters 19682........................... 19683 19684The semicolon `;' is the line comment character; 19685 19686 If a `#' appears as the first character of a line then the whole 19687line is treated as a comment, but in this case the line could also be a 19688logical line number directive (*note Comments::) or a preprocessor 19689control command (*note Preprocessing::). 19690 19691 The Z80 assembler does not support a line separator character. 19692 19693 The dollar sign `$' can be used as a prefix for hexadecimal numbers 19694and as a symbol denoting the current location counter. 19695 19696 A backslash `\' is an ordinary character for the Z80 assembler. 19697 19698 The single quote `'' must be followed by a closing quote. If there 19699is one character in between, it is a character constant, otherwise it is 19700a string constant. 19701 19702 19703File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Syntax 19704 197059.46.2.2 Register Names 19706....................... 19707 19708The registers are referred to with the letters assigned to them by 19709Zilog. In addition `as' recognizes `ixl' and `ixh' as the least and 19710most significant octet in `ix', and similarly `iyl' and `iyh' as parts 19711of `iy'. 19712 19713 19714File: as.info, Node: Z80-Case, Prev: Z80-Regs, Up: Z80 Syntax 19715 197169.46.2.3 Case Sensitivity 19717......................... 19718 19719Upper and lower case are equivalent in register names, opcodes, 19720condition codes and assembler directives. The case of letters is 19721significant in labels and symbol names. The case is also important to 19722distinguish the suffix `b' for a backward reference to a local label 19723from the suffix `B' for a number in binary notation. 19724 19725 19726File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent 19727 197289.46.3 Floating Point 19729--------------------- 19730 19731Floating-point numbers are not supported. 19732 19733 19734File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Point, Up: Z80-Dependent 19735 197369.46.4 Z80 Assembler Directives 19737------------------------------- 19738 19739`as' for the Z80 supports some additional directives for compatibility 19740with other assemblers. 19741 19742 These are the additional directives in `as' for the Z80: 19743 19744`db EXPRESSION|STRING[,EXPRESSION|STRING...]' 19745`defb EXPRESSION|STRING[,EXPRESSION|STRING...]' 19746 For each STRING the characters are copied to the object file, for 19747 each other EXPRESSION the value is stored in one byte. A warning 19748 is issued in case of an overflow. 19749 19750`dw EXPRESSION[,EXPRESSION...]' 19751`defw EXPRESSION[,EXPRESSION...]' 19752 For each EXPRESSION the value is stored in two bytes, ignoring 19753 overflow. 19754 19755`d24 EXPRESSION[,EXPRESSION...]' 19756`def24 EXPRESSION[,EXPRESSION...]' 19757 For each EXPRESSION the value is stored in three bytes, ignoring 19758 overflow. 19759 19760`d32 EXPRESSION[,EXPRESSION...]' 19761`def32 EXPRESSION[,EXPRESSION...]' 19762 For each EXPRESSION the value is stored in four bytes, ignoring 19763 overflow. 19764 19765`ds COUNT[, VALUE]' 19766`defs COUNT[, VALUE]' 19767 Fill COUNT bytes in the object file with VALUE, if VALUE is 19768 omitted it defaults to zero. 19769 19770`SYMBOL equ EXPRESSION' 19771`SYMBOL defl EXPRESSION' 19772 These directives set the value of SYMBOL to EXPRESSION. If `equ' 19773 is used, it is an error if SYMBOL is already defined. Symbols 19774 defined with `equ' are not protected from redefinition. 19775 19776`set' 19777 This is a normal instruction on Z80, and not an assembler 19778 directive. 19779 19780`psect NAME' 19781 A synonym for *Note Section::, no second argument should be given. 19782 19783 19784 19785File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent 19786 197879.46.5 Opcodes 19788-------------- 19789 19790In line with common practice, Z80 mnemonics are used for both the Z80 19791and the R800. 19792 19793 In many instructions it is possible to use one of the half index 19794registers (`ixl',`ixh',`iyl',`iyh') in stead of an 8-bit general 19795purpose register. This yields instructions that are documented on the 19796R800 and undocumented on the Z80. Similarly `in f,(c)' is documented 19797on the R800 and undocumented on the Z80. 19798 19799 The assembler also supports the following undocumented 19800Z80-instructions, that have not been adopted in the R800 instruction 19801set: 19802`out (c),0' 19803 Sends zero to the port pointed to by register c. 19804 19805`sli M' 19806 Equivalent to `M = (M<<1)+1', the operand M can be any operand 19807 that is valid for `sla'. One can use `sll' as a synonym for `sli'. 19808 19809`OP (ix+D), R' 19810 This is equivalent to 19811 19812 ld R, (ix+D) 19813 OPC R 19814 ld (ix+D), R 19815 19816 The operation `OPC' may be any of `res B,', `set B,', `rl', `rlc', 19817 `rr', `rrc', `sla', `sli', `sra' and `srl', and the register `R' 19818 may be any of `a', `b', `c', `d', `e', `h' and `l'. 19819 19820`OPC (iy+D), R' 19821 As above, but with `iy' instead of `ix'. 19822 19823 The web site at `http://www.z80.info' is a good starting place to 19824find more information on programming the Z80. 19825 19826 19827File: as.info, Node: Z8000-Dependent, Next: Vax-Dependent, Prev: Z80-Dependent, Up: Machine Dependencies 19828 198299.47 Z8000 Dependent Features 19830============================= 19831 19832 The Z8000 as supports both members of the Z8000 family: the 19833unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with 1983424 bit addresses. 19835 19836 When the assembler is in unsegmented mode (specified with the 19837`unsegm' directive), an address takes up one word (16 bit) sized 19838register. When the assembler is in segmented mode (specified with the 19839`segm' directive), a 24-bit address takes up a long (32 bit) register. 19840*Note Assembler Directives for the Z8000: Z8000 Directives, for a list 19841of other Z8000 specific assembler directives. 19842 19843* Menu: 19844 19845* Z8000 Options:: Command-line options for the Z8000 19846* Z8000 Syntax:: Assembler syntax for the Z8000 19847* Z8000 Directives:: Special directives for the Z8000 19848* Z8000 Opcodes:: Opcodes 19849 19850 19851File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent 19852 198539.47.1 Options 19854-------------- 19855 19856`-z8001' 19857 Generate segmented code by default. 19858 19859`-z8002' 19860 Generate unsegmented code by default. 19861 19862 19863File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent 19864 198659.47.2 Syntax 19866------------- 19867 19868* Menu: 19869 19870* Z8000-Chars:: Special Characters 19871* Z8000-Regs:: Register Names 19872* Z8000-Addressing:: Addressing Modes 19873 19874 19875File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax 19876 198779.47.2.1 Special Characters 19878........................... 19879 19880`!' is the line comment character. 19881 19882 If a `#' appears as the first character of a line then the whole 19883line is treated as a comment, but in this case the line could also be a 19884logical line number directive (*note Comments::) or a preprocessor 19885control command (*note Preprocessing::). 19886 19887 You can use `;' instead of a newline to separate statements. 19888 19889 19890File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax 19891 198929.47.2.2 Register Names 19893....................... 19894 19895The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer 19896to different sized groups of registers by register number, with the 19897prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' for 1989864 bit registers. You can also refer to the contents of the first 19899eight (of the sixteen 16 bit registers) by bytes. They are named `rlN' 19900and `rhN'. 19901 19902_byte registers_ 19903 rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3 19904 rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7 19905 19906_word registers_ 19907 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 19908 19909_long word registers_ 19910 rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14 19911 19912_quad word registers_ 19913 rq0 rq4 rq8 rq12 19914 19915 19916File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax 19917 199189.47.2.3 Addressing Modes 19919......................... 19920 19921as understands the following addressing modes for the Z8000: 19922 19923`rlN' 19924`rhN' 19925`rN' 19926`rrN' 19927`rqN' 19928 Register direct: 8bit, 16bit, 32bit, and 64bit registers. 19929 19930`@rN' 19931`@rrN' 19932 Indirect register: @rrN in segmented mode, @rN in unsegmented 19933 mode. 19934 19935`ADDR' 19936 Direct: the 16 bit or 24 bit address (depending on whether the 19937 assembler is in segmented or unsegmented mode) of the operand is 19938 in the instruction. 19939 19940`address(rN)' 19941 Indexed: the 16 or 24 bit address is added to the 16 bit register 19942 to produce the final address in memory of the operand. 19943 19944`rN(#IMM)' 19945`rrN(#IMM)' 19946 Base Address: the 16 or 24 bit register is added to the 16 bit sign 19947 extended immediate displacement to produce the final address in 19948 memory of the operand. 19949 19950`rN(rM)' 19951`rrN(rM)' 19952 Base Index: the 16 or 24 bit register rN or rrN is added to the 19953 sign extended 16 bit index register rM to produce the final 19954 address in memory of the operand. 19955 19956`#XX' 19957 Immediate data XX. 19958 19959 19960File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent 19961 199629.47.3 Assembler Directives for the Z8000 19963----------------------------------------- 19964 19965The Z8000 port of as includes additional assembler directives, for 19966compatibility with other Z8000 assemblers. These do not begin with `.' 19967(unlike the ordinary as directives). 19968 19969`segm' 19970`.z8001' 19971 Generate code for the segmented Z8001. 19972 19973`unsegm' 19974`.z8002' 19975 Generate code for the unsegmented Z8002. 19976 19977`name' 19978 Synonym for `.file' 19979 19980`global' 19981 Synonym for `.global' 19982 19983`wval' 19984 Synonym for `.word' 19985 19986`lval' 19987 Synonym for `.long' 19988 19989`bval' 19990 Synonym for `.byte' 19991 19992`sval' 19993 Assemble a string. `sval' expects one string literal, delimited by 19994 single quotes. It assembles each byte of the string into 19995 consecutive addresses. You can use the escape sequence `%XX' 19996 (where XX represents a two-digit hexadecimal number) to represent 19997 the character whose ASCII value is XX. Use this feature to 19998 describe single quote and other characters that may not appear in 19999 string literals as themselves. For example, the C statement 20000 `char *a = "he said \"it's 50% off\"";' is represented in Z8000 20001 assembly language (shown with the assembler output in hex at the 20002 left) as 20003 20004 68652073 sval 'he said %22it%27s 50%25 off%22%00' 20005 61696420 20006 22697427 20007 73203530 20008 25206F66 20009 662200 20010 20011`rsect' 20012 synonym for `.section' 20013 20014`block' 20015 synonym for `.space' 20016 20017`even' 20018 special case of `.align'; aligns output to even byte boundary. 20019 20020 20021File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent 20022 200239.47.4 Opcodes 20024-------------- 20025 20026For detailed information on the Z8000 machine instruction set, see 20027`Z8000 Technical Manual'. 20028 20029 The following table summarizes the opcodes and their arguments: 20030 20031 rs 16 bit source register 20032 rd 16 bit destination register 20033 rbs 8 bit source register 20034 rbd 8 bit destination register 20035 rrs 32 bit source register 20036 rrd 32 bit destination register 20037 rqs 64 bit source register 20038 rqd 64 bit destination register 20039 addr 16/24 bit address 20040 imm immediate data 20041 20042 adc rd,rs clrb addr cpsir @rd,@rs,rr,cc 20043 adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc 20044 add rd,@rs clrb rbd dab rbd 20045 add rd,addr com @rd dbjnz rbd,disp7 20046 add rd,addr(rs) com addr dec @rd,imm4m1 20047 add rd,imm16 com addr(rd) dec addr(rd),imm4m1 20048 add rd,rs com rd dec addr,imm4m1 20049 addb rbd,@rs comb @rd dec rd,imm4m1 20050 addb rbd,addr comb addr decb @rd,imm4m1 20051 addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1 20052 addb rbd,imm8 comb rbd decb addr,imm4m1 20053 addb rbd,rbs comflg flags decb rbd,imm4m1 20054 addl rrd,@rs cp @rd,imm16 di i2 20055 addl rrd,addr cp addr(rd),imm16 div rrd,@rs 20056 addl rrd,addr(rs) cp addr,imm16 div rrd,addr 20057 addl rrd,imm32 cp rd,@rs div rrd,addr(rs) 20058 addl rrd,rrs cp rd,addr div rrd,imm16 20059 and rd,@rs cp rd,addr(rs) div rrd,rs 20060 and rd,addr cp rd,imm16 divl rqd,@rs 20061 and rd,addr(rs) cp rd,rs divl rqd,addr 20062 and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs) 20063 and rd,rs cpb addr(rd),imm8 divl rqd,imm32 20064 andb rbd,@rs cpb addr,imm8 divl rqd,rrs 20065 andb rbd,addr cpb rbd,@rs djnz rd,disp7 20066 andb rbd,addr(rs) cpb rbd,addr ei i2 20067 andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs 20068 andb rbd,rbs cpb rbd,imm8 ex rd,addr 20069 bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs) 20070 bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs 20071 bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs 20072 bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr 20073 bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs) 20074 bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs 20075 bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8 20076 bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8 20077 bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8 20078 bitb rbd,rs cpl rrd,@rs ext8f imm8 20079 bpt cpl rrd,addr exts rrd 20080 call @rd cpl rrd,addr(rs) extsb rd 20081 call addr cpl rrd,imm32 extsl rqd 20082 call addr(rd) cpl rrd,rrs halt 20083 calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs 20084 clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16 20085 clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs 20086 clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16 20087 clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1 20088 clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1 20089 inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs) 20090 inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16 20091 incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs 20092 incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs 20093 incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr 20094 incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs) 20095 ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32 20096 indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs 20097 inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd 20098 inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr 20099 iret ldib @rd,@rs,rr neg addr(rd) 20100 jp cc,@rd ldir @rd,@rs,rr neg rd 20101 jp cc,addr ldirb @rd,@rs,rr negb @rd 20102 jp cc,addr(rd) ldk rd,imm4 negb addr 20103 jr cc,disp8 ldl @rd,rrs negb addr(rd) 20104 ld @rd,imm16 ldl addr(rd),rrs negb rbd 20105 ld @rd,rs ldl addr,rrs nop 20106 ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs 20107 ld addr(rd),rs ldl rd(rx),rrs or rd,addr 20108 ld addr,imm16 ldl rrd,@rs or rd,addr(rs) 20109 ld addr,rs ldl rrd,addr or rd,imm16 20110 ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs 20111 ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs 20112 ld rd,@rs ldl rrd,rrs orb rbd,addr 20113 ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs) 20114 ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8 20115 ld rd,imm16 ldm @rd,rs,n orb rbd,rbs 20116 ld rd,rs ldm addr(rd),rs,n out @rd,rs 20117 ld rd,rs(imm16) ldm addr,rs,n out imm16,rs 20118 ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs 20119 lda rd,addr ldm rd,addr(rs),n outb imm16,rbs 20120 lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra 20121 lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba 20122 lda rd,rs(rx) ldps addr outib @rd,@rs,ra 20123 ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra 20124 ldb @rd,imm8 ldr disp16,rs pop @rd,@rs 20125 ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs 20126 ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs 20127 ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs 20128 ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs 20129 ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs 20130 ldb rbd,@rs mbit popl addr,@rs 20131 ldb rbd,addr mreq rd popl rrd,@rs 20132 ldb rbd,addr(rs) mres push @rd,@rs 20133 ldb rbd,imm8 mset push @rd,addr 20134 ldb rbd,rbs mult rrd,@rs push @rd,addr(rs) 20135 ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16 20136 push @rd,rs set addr,imm4 subl rrd,imm32 20137 pushl @rd,@rs set rd,imm4 subl rrd,rrs 20138 pushl @rd,addr set rd,rs tcc cc,rd 20139 pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd 20140 pushl @rd,rrs setb addr(rd),imm4 test @rd 20141 res @rd,imm4 setb addr,imm4 test addr 20142 res addr(rd),imm4 setb rbd,imm4 test addr(rd) 20143 res addr,imm4 setb rbd,rs test rd 20144 res rd,imm4 setflg imm4 testb @rd 20145 res rd,rs sinb rbd,imm16 testb addr 20146 resb @rd,imm4 sinb rd,imm16 testb addr(rd) 20147 resb addr(rd),imm4 sind @rd,@rs,ra testb rbd 20148 resb addr,imm4 sindb @rd,@rs,rba testl @rd 20149 resb rbd,imm4 sinib @rd,@rs,ra testl addr 20150 resb rbd,rs sinibr @rd,@rs,ra testl addr(rd) 20151 resflg imm4 sla rd,imm8 testl rrd 20152 ret cc slab rbd,imm8 trdb @rd,@rs,rba 20153 rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba 20154 rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr 20155 rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr 20156 rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr 20157 rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr 20158 rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr 20159 rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr 20160 rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd 20161 rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr 20162 rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd) 20163 rsvd36 sra rd,imm8 tset rd 20164 rsvd38 srab rbd,imm8 tsetb @rd 20165 rsvd78 sral rrd,imm8 tsetb addr 20166 rsvd7e srl rd,imm8 tsetb addr(rd) 20167 rsvd9d srlb rbd,imm8 tsetb rbd 20168 rsvd9f srll rrd,imm8 xor rd,@rs 20169 rsvdb9 sub rd,@rs xor rd,addr 20170 rsvdbf sub rd,addr xor rd,addr(rs) 20171 sbc rd,rs sub rd,addr(rs) xor rd,imm16 20172 sbcb rbd,rbs sub rd,imm16 xor rd,rs 20173 sc imm8 sub rd,rs xorb rbd,@rs 20174 sda rd,rs subb rbd,@rs xorb rbd,addr 20175 sdab rbd,rs subb rbd,addr xorb rbd,addr(rs) 20176 sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8 20177 sdl rd,rs subb rbd,imm8 xorb rbd,rbs 20178 sdlb rbd,rs subb rbd,rbs xorb rbd,rbs 20179 sdll rrd,rs subl rrd,@rs 20180 set @rd,imm4 subl rrd,addr 20181 set addr(rd),imm4 subl rrd,addr(rs) 20182 20183 20184File: as.info, Node: Vax-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies 20185 201869.48 VAX Dependent Features 20187=========================== 20188 20189* Menu: 20190 20191* VAX-Opts:: VAX Command-Line Options 20192* VAX-float:: VAX Floating Point 20193* VAX-directives:: Vax Machine Directives 20194* VAX-opcodes:: VAX Opcodes 20195* VAX-branch:: VAX Branch Improvement 20196* VAX-operands:: VAX Operands 20197* VAX-no:: Not Supported on VAX 20198* VAX-Syntax:: VAX Syntax 20199 20200 20201File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent 20202 202039.48.1 VAX Command-Line Options 20204------------------------------- 20205 20206The Vax version of `as' accepts any of the following options, gives a 20207warning message that the option was ignored and proceeds. These 20208options are for compatibility with scripts designed for other people's 20209assemblers. 20210 20211``-D' (Debug)' 20212``-S' (Symbol Table)' 20213``-T' (Token Trace)' 20214 These are obsolete options used to debug old assemblers. 20215 20216``-d' (Displacement size for JUMPs)' 20217 This option expects a number following the `-d'. Like options 20218 that expect filenames, the number may immediately follow the `-d' 20219 (old standard) or constitute the whole of the command line 20220 argument that follows `-d' (GNU standard). 20221 20222``-V' (Virtualize Interpass Temporary File)' 20223 Some other assemblers use a temporary file. This option commanded 20224 them to keep the information in active memory rather than in a 20225 disk file. `as' always does this, so this option is redundant. 20226 20227``-J' (JUMPify Longer Branches)' 20228 Many 32-bit computers permit a variety of branch instructions to 20229 do the same job. Some of these instructions are short (and fast) 20230 but have a limited range; others are long (and slow) but can 20231 branch anywhere in virtual memory. Often there are 3 flavors of 20232 branch: short, medium and long. Some other assemblers would emit 20233 short and medium branches, unless told by this option to emit 20234 short and long branches. 20235 20236``-t' (Temporary File Directory)' 20237 Some other assemblers may use a temporary file, and this option 20238 takes a filename being the directory to site the temporary file. 20239 Since `as' does not use a temporary disk file, this option makes 20240 no difference. `-t' needs exactly one filename. 20241 20242 The Vax version of the assembler accepts additional options when 20243compiled for VMS: 20244 20245`-h N' 20246 External symbol or section (used for global variables) names are 20247 not case sensitive on VAX/VMS and always mapped to upper case. 20248 This is contrary to the C language definition which explicitly 20249 distinguishes upper and lower case. To implement a standard 20250 conforming C compiler, names must be changed (mapped) to preserve 20251 the case information. The default mapping is to convert all lower 20252 case characters to uppercase and adding an underscore followed by 20253 a 6 digit hex value, representing a 24 digit binary value. The 20254 one digits in the binary value represent which characters are 20255 uppercase in the original symbol name. 20256 20257 The `-h N' option determines how we map names. This takes several 20258 values. No `-h' switch at all allows case hacking as described 20259 above. A value of zero (`-h0') implies names should be upper 20260 case, and inhibits the case hack. A value of 2 (`-h2') implies 20261 names should be all lower case, with no case hack. A value of 3 20262 (`-h3') implies that case should be preserved. The value 1 is 20263 unused. The `-H' option directs `as' to display every mapped 20264 symbol during assembly. 20265 20266 Symbols whose names include a dollar sign `$' are exceptions to the 20267 general name mapping. These symbols are normally only used to 20268 reference VMS library names. Such symbols are always mapped to 20269 upper case. 20270 20271`-+' 20272 The `-+' option causes `as' to truncate any symbol name larger 20273 than 31 characters. The `-+' option also prevents some code 20274 following the `_main' symbol normally added to make the object 20275 file compatible with Vax-11 "C". 20276 20277`-1' 20278 This option is ignored for backward compatibility with `as' 20279 version 1.x. 20280 20281`-H' 20282 The `-H' option causes `as' to print every symbol which was 20283 changed by case mapping. 20284 20285 20286File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent 20287 202889.48.2 VAX Floating Point 20289------------------------- 20290 20291Conversion of flonums to floating point is correct, and compatible with 20292previous assemblers. Rounding is towards zero if the remainder is 20293exactly half the least significant bit. 20294 20295 `D', `F', `G' and `H' floating point formats are understood. 20296 20297 Immediate floating literals (_e.g._ `S`$6.9') are rendered 20298correctly. Again, rounding is towards zero in the boundary case. 20299 20300 The `.float' directive produces `f' format numbers. The `.double' 20301directive produces `d' format numbers. 20302 20303 20304File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent 20305 203069.48.3 Vax Machine Directives 20307----------------------------- 20308 20309The Vax version of the assembler supports four directives for 20310generating Vax floating point constants. They are described in the 20311table below. 20312 20313`.dfloat' 20314 This expects zero or more flonums, separated by commas, and 20315 assembles Vax `d' format 64-bit floating point constants. 20316 20317`.ffloat' 20318 This expects zero or more flonums, separated by commas, and 20319 assembles Vax `f' format 32-bit floating point constants. 20320 20321`.gfloat' 20322 This expects zero or more flonums, separated by commas, and 20323 assembles Vax `g' format 64-bit floating point constants. 20324 20325`.hfloat' 20326 This expects zero or more flonums, separated by commas, and 20327 assembles Vax `h' format 128-bit floating point constants. 20328 20329 20330 20331File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent 20332 203339.48.4 VAX Opcodes 20334------------------ 20335 20336All DEC mnemonics are supported. Beware that `case...' instructions 20337have exactly 3 operands. The dispatch table that follows the `case...' 20338instruction should be made with `.word' statements. This is compatible 20339with all unix assemblers we know of. 20340 20341 20342File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent 20343 203449.48.5 VAX Branch Improvement 20345----------------------------- 20346 20347Certain pseudo opcodes are permitted. They are for branch 20348instructions. They expand to the shortest branch instruction that 20349reaches the target. Generally these mnemonics are made by substituting 20350`j' for `b' at the start of a DEC mnemonic. This feature is included 20351both for compatibility and to help compilers. If you do not need this 20352feature, avoid these opcodes. Here are the mnemonics, and the code 20353they can expand into. 20354 20355`jbsb' 20356 `Jsb' is already an instruction mnemonic, so we chose `jbsb'. 20357 (byte displacement) 20358 `bsbb ...' 20359 20360 (word displacement) 20361 `bsbw ...' 20362 20363 (long displacement) 20364 `jsb ...' 20365 20366`jbr' 20367`jr' 20368 Unconditional branch. 20369 (byte displacement) 20370 `brb ...' 20371 20372 (word displacement) 20373 `brw ...' 20374 20375 (long displacement) 20376 `jmp ...' 20377 20378`jCOND' 20379 COND may be any one of the conditional branches `neq', `nequ', 20380 `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs', 20381 `gequ', `cc', `lssu', `cs'. COND may also be one of the bit tests 20382 `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs', 20383 `lbc'. NOTCOND is the opposite condition to COND. 20384 (byte displacement) 20385 `bCOND ...' 20386 20387 (word displacement) 20388 `bNOTCOND foo ; brw ... ; foo:' 20389 20390 (long displacement) 20391 `bNOTCOND foo ; jmp ... ; foo:' 20392 20393`jacbX' 20394 X may be one of `b d f g h l w'. 20395 (word displacement) 20396 `OPCODE ...' 20397 20398 (long displacement) 20399 OPCODE ..., foo ; 20400 brb bar ; 20401 foo: jmp ... ; 20402 bar: 20403 20404`jaobYYY' 20405 YYY may be one of `lss leq'. 20406 20407`jsobZZZ' 20408 ZZZ may be one of `geq gtr'. 20409 (byte displacement) 20410 `OPCODE ...' 20411 20412 (word displacement) 20413 OPCODE ..., foo ; 20414 brb bar ; 20415 foo: brw DESTINATION ; 20416 bar: 20417 20418 (long displacement) 20419 OPCODE ..., foo ; 20420 brb bar ; 20421 foo: jmp DESTINATION ; 20422 bar: 20423 20424`aobleq' 20425`aoblss' 20426`sobgeq' 20427`sobgtr' 20428 20429 (byte displacement) 20430 `OPCODE ...' 20431 20432 (word displacement) 20433 OPCODE ..., foo ; 20434 brb bar ; 20435 foo: brw DESTINATION ; 20436 bar: 20437 20438 (long displacement) 20439 OPCODE ..., foo ; 20440 brb bar ; 20441 foo: jmp DESTINATION ; 20442 bar: 20443 20444 20445File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent 20446 204479.48.6 VAX Operands 20448------------------- 20449 20450The immediate character is `$' for Unix compatibility, not `#' as DEC 20451writes it. 20452 20453 The indirect character is `*' for Unix compatibility, not `@' as DEC 20454writes it. 20455 20456 The displacement sizing character is ``' (an accent grave) for Unix 20457compatibility, not `^' as DEC writes it. The letter preceding ``' may 20458have either case. `G' is not understood, but all other letters (`b i l 20459s w') are understood. 20460 20461 Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'. Upper 20462and lower case letters are equivalent. 20463 20464 For instance 20465 tstb *w`$4(r5) 20466 20467 Any expression is permitted in an operand. Operands are comma 20468separated. 20469 20470 20471File: as.info, Node: VAX-no, Next: VAX-Syntax, Prev: VAX-operands, Up: Vax-Dependent 20472 204739.48.7 Not Supported on VAX 20474--------------------------- 20475 20476Vax bit fields can not be assembled with `as'. Someone can add the 20477required code if they really need it. 20478 20479 20480File: as.info, Node: VAX-Syntax, Prev: VAX-no, Up: Vax-Dependent 20481 204829.48.8 VAX Syntax 20483----------------- 20484 20485* Menu: 20486 20487* VAX-Chars:: Special Characters 20488 20489 20490File: as.info, Node: VAX-Chars, Up: VAX-Syntax 20491 204929.48.8.1 Special Characters 20493........................... 20494 20495The presence of a `#' appearing anywhere on a line indicates the start 20496of a comment that extends to the end of that line. 20497 20498 If a `#' appears as the first character of a line then the whole 20499line is treated as a comment, but in this case the line can also be a 20500logical line number directive (*note Comments::) or a preprocessor 20501control command (*note Preprocessing::). 20502 20503 The `;' character can be used to separate statements on the same 20504line. 20505 20506 20507File: as.info, Node: V850-Dependent, Next: XGATE-Dependent, Prev: TILEPro-Dependent, Up: Machine Dependencies 20508 205099.49 v850 Dependent Features 20510============================ 20511 20512* Menu: 20513 20514* V850 Options:: Options 20515* V850 Syntax:: Syntax 20516* V850 Floating Point:: Floating Point 20517* V850 Directives:: V850 Machine Directives 20518* V850 Opcodes:: Opcodes 20519 20520 20521File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent 20522 205239.49.1 Options 20524-------------- 20525 20526`as' supports the following additional command-line options for the 20527V850 processor family: 20528 20529`-wsigned_overflow' 20530 Causes warnings to be produced when signed immediate values 20531 overflow the space available for then within their opcodes. By 20532 default this option is disabled as it is possible to receive 20533 spurious warnings due to using exact bit patterns as immediate 20534 constants. 20535 20536`-wunsigned_overflow' 20537 Causes warnings to be produced when unsigned immediate values 20538 overflow the space available for then within their opcodes. By 20539 default this option is disabled as it is possible to receive 20540 spurious warnings due to using exact bit patterns as immediate 20541 constants. 20542 20543`-mv850' 20544 Specifies that the assembled code should be marked as being 20545 targeted at the V850 processor. This allows the linker to detect 20546 attempts to link such code with code assembled for other 20547 processors. 20548 20549`-mv850e' 20550 Specifies that the assembled code should be marked as being 20551 targeted at the V850E processor. This allows the linker to detect 20552 attempts to link such code with code assembled for other 20553 processors. 20554 20555`-mv850e1' 20556 Specifies that the assembled code should be marked as being 20557 targeted at the V850E1 processor. This allows the linker to 20558 detect attempts to link such code with code assembled for other 20559 processors. 20560 20561`-mv850any' 20562 Specifies that the assembled code should be marked as being 20563 targeted at the V850 processor but support instructions that are 20564 specific to the extended variants of the process. This allows the 20565 production of binaries that contain target specific code, but 20566 which are also intended to be used in a generic fashion. For 20567 example libgcc.a contains generic routines used by the code 20568 produced by GCC for all versions of the v850 architecture, 20569 together with support routines only used by the V850E architecture. 20570 20571`-mv850e2' 20572 Specifies that the assembled code should be marked as being 20573 targeted at the V850E2 processor. This allows the linker to 20574 detect attempts to link such code with code assembled for other 20575 processors. 20576 20577`-mv850e2v3' 20578 Specifies that the assembled code should be marked as being 20579 targeted at the V850E2V3 processor. This allows the linker to 20580 detect attempts to link such code with code assembled for other 20581 processors. 20582 20583`-mv850e2v4' 20584 This is an alias for `-mv850e3v5'. 20585 20586`-mv850e3v5' 20587 Specifies that the assembled code should be marked as being 20588 targeted at the V850E3V5 processor. This allows the linker to 20589 detect attempts to link such code with code assembled for other 20590 processors. 20591 20592`-mrelax' 20593 Enables relaxation. This allows the .longcall and .longjump pseudo 20594 ops to be used in the assembler source code. These ops label 20595 sections of code which are either a long function call or a long 20596 branch. The assembler will then flag these sections of code and 20597 the linker will attempt to relax them. 20598 20599`-mgcc-abi' 20600 Marks the generated objecy file as supporting the old GCC ABI. 20601 20602`-mrh850-abi' 20603 Marks the generated objecy file as supporting the RH850 ABI. This 20604 is the default. 20605 20606`-m8byte-align' 20607 Marks the generated objecy file as supporting a maximum 64-bits of 20608 alignment for variables defined in the source code. 20609 20610`-m4byte-align' 20611 Marks the generated objecy file as supporting a maximum 32-bits of 20612 alignment for variables defined in the source code. This is the 20613 default. 20614 20615 20616 20617File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent 20618 206199.49.2 Syntax 20620------------- 20621 20622* Menu: 20623 20624* V850-Chars:: Special Characters 20625* V850-Regs:: Register Names 20626 20627 20628File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax 20629 206309.49.2.1 Special Characters 20631........................... 20632 20633`#' is the line comment character. If a `#' appears as the first 20634character of a line, the whole line is treated as a comment, but in 20635this case the line can also be a logical line number directive (*note 20636Comments::) or a preprocessor control command (*note Preprocessing::). 20637 20638 Two dashes (`--') can also be used to start a line comment. 20639 20640 The `;' character can be used to separate statements on the same 20641line. 20642 20643 20644File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax 20645 206469.49.2.2 Register Names 20647....................... 20648 20649`as' supports the following names for registers: 20650`general register 0' 20651 r0, zero 20652 20653`general register 1' 20654 r1 20655 20656`general register 2' 20657 r2, hp 20658 20659`general register 3' 20660 r3, sp 20661 20662`general register 4' 20663 r4, gp 20664 20665`general register 5' 20666 r5, tp 20667 20668`general register 6' 20669 r6 20670 20671`general register 7' 20672 r7 20673 20674`general register 8' 20675 r8 20676 20677`general register 9' 20678 r9 20679 20680`general register 10' 20681 r10 20682 20683`general register 11' 20684 r11 20685 20686`general register 12' 20687 r12 20688 20689`general register 13' 20690 r13 20691 20692`general register 14' 20693 r14 20694 20695`general register 15' 20696 r15 20697 20698`general register 16' 20699 r16 20700 20701`general register 17' 20702 r17 20703 20704`general register 18' 20705 r18 20706 20707`general register 19' 20708 r19 20709 20710`general register 20' 20711 r20 20712 20713`general register 21' 20714 r21 20715 20716`general register 22' 20717 r22 20718 20719`general register 23' 20720 r23 20721 20722`general register 24' 20723 r24 20724 20725`general register 25' 20726 r25 20727 20728`general register 26' 20729 r26 20730 20731`general register 27' 20732 r27 20733 20734`general register 28' 20735 r28 20736 20737`general register 29' 20738 r29 20739 20740`general register 30' 20741 r30, ep 20742 20743`general register 31' 20744 r31, lp 20745 20746`system register 0' 20747 eipc 20748 20749`system register 1' 20750 eipsw 20751 20752`system register 2' 20753 fepc 20754 20755`system register 3' 20756 fepsw 20757 20758`system register 4' 20759 ecr 20760 20761`system register 5' 20762 psw 20763 20764`system register 16' 20765 ctpc 20766 20767`system register 17' 20768 ctpsw 20769 20770`system register 18' 20771 dbpc 20772 20773`system register 19' 20774 dbpsw 20775 20776`system register 20' 20777 ctbp 20778 20779 20780File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent 20781 207829.49.3 Floating Point 20783--------------------- 20784 20785The V850 family uses IEEE floating-point numbers. 20786 20787 20788File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent 20789 207909.49.4 V850 Machine Directives 20791------------------------------ 20792 20793`.offset <EXPRESSION>' 20794 Moves the offset into the current section to the specified amount. 20795 20796`.section "name", <type>' 20797 This is an extension to the standard .section directive. It sets 20798 the current section to be <type> and creates an alias for this 20799 section called "name". 20800 20801`.v850' 20802 Specifies that the assembled code should be marked as being 20803 targeted at the V850 processor. This allows the linker to detect 20804 attempts to link such code with code assembled for other 20805 processors. 20806 20807`.v850e' 20808 Specifies that the assembled code should be marked as being 20809 targeted at the V850E processor. This allows the linker to detect 20810 attempts to link such code with code assembled for other 20811 processors. 20812 20813`.v850e1' 20814 Specifies that the assembled code should be marked as being 20815 targeted at the V850E1 processor. This allows the linker to 20816 detect attempts to link such code with code assembled for other 20817 processors. 20818 20819`.v850e2' 20820 Specifies that the assembled code should be marked as being 20821 targeted at the V850E2 processor. This allows the linker to 20822 detect attempts to link such code with code assembled for other 20823 processors. 20824 20825`.v850e2v3' 20826 Specifies that the assembled code should be marked as being 20827 targeted at the V850E2V3 processor. This allows the linker to 20828 detect attempts to link such code with code assembled for other 20829 processors. 20830 20831`.v850e2v4' 20832 Specifies that the assembled code should be marked as being 20833 targeted at the V850E3V5 processor. This allows the linker to 20834 detect attempts to link such code with code assembled for other 20835 processors. 20836 20837`.v850e3v5' 20838 Specifies that the assembled code should be marked as being 20839 targeted at the V850E3V5 processor. This allows the linker to 20840 detect attempts to link such code with code assembled for other 20841 processors. 20842 20843 20844 20845File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent 20846 208479.49.5 Opcodes 20848-------------- 20849 20850`as' implements all the standard V850 opcodes. 20851 20852 `as' also implements the following pseudo ops: 20853 20854`hi0()' 20855 Computes the higher 16 bits of the given expression and stores it 20856 into the immediate operand field of the given instruction. For 20857 example: 20858 20859 `mulhi hi0(here - there), r5, r6' 20860 20861 computes the difference between the address of labels 'here' and 20862 'there', takes the upper 16 bits of this difference, shifts it 20863 down 16 bits and then multiplies it by the lower 16 bits in 20864 register 5, putting the result into register 6. 20865 20866`lo()' 20867 Computes the lower 16 bits of the given expression and stores it 20868 into the immediate operand field of the given instruction. For 20869 example: 20870 20871 `addi lo(here - there), r5, r6' 20872 20873 computes the difference between the address of labels 'here' and 20874 'there', takes the lower 16 bits of this difference and adds it to 20875 register 5, putting the result into register 6. 20876 20877`hi()' 20878 Computes the higher 16 bits of the given expression and then adds 20879 the value of the most significant bit of the lower 16 bits of the 20880 expression and stores the result into the immediate operand field 20881 of the given instruction. For example the following code can be 20882 used to compute the address of the label 'here' and store it into 20883 register 6: 20884 20885 `movhi hi(here), r0, r6' `movea lo(here), r6, r6' 20886 20887 The reason for this special behaviour is that movea performs a sign 20888 extension on its immediate operand. So for example if the address 20889 of 'here' was 0xFFFFFFFF then without the special behaviour of the 20890 hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, 20891 then the movea instruction would takes its immediate operand, 20892 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it 20893 into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). 20894 With the hi() pseudo op adding in the top bit of the lo() pseudo 20895 op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 20896 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 - 20897 the right value. 20898 20899`hilo()' 20900 Computes the 32 bit value of the given expression and stores it 20901 into the immediate operand field of the given instruction (which 20902 must be a mov instruction). For example: 20903 20904 `mov hilo(here), r6' 20905 20906 computes the absolute address of label 'here' and puts the result 20907 into register 6. 20908 20909`sdaoff()' 20910 Computes the offset of the named variable from the start of the 20911 Small Data Area (whoes address is held in register 4, the GP 20912 register) and stores the result as a 16 bit signed value in the 20913 immediate operand field of the given instruction. For example: 20914 20915 `ld.w sdaoff(_a_variable)[gp],r6' 20916 20917 loads the contents of the location pointed to by the label 20918 '_a_variable' into register 6, provided that the label is located 20919 somewhere within +/- 32K of the address held in the GP register. 20920 [Note the linker assumes that the GP register contains a fixed 20921 address set to the address of the label called '__gp'. This can 20922 either be set up automatically by the linker, or specifically set 20923 by using the `--defsym __gp=<value>' command line option]. 20924 20925`tdaoff()' 20926 Computes the offset of the named variable from the start of the 20927 Tiny Data Area (whoes address is held in register 30, the EP 20928 register) and stores the result as a 4,5, 7 or 8 bit unsigned 20929 value in the immediate operand field of the given instruction. 20930 For example: 20931 20932 `sld.w tdaoff(_a_variable)[ep],r6' 20933 20934 loads the contents of the location pointed to by the label 20935 '_a_variable' into register 6, provided that the label is located 20936 somewhere within +256 bytes of the address held in the EP 20937 register. [Note the linker assumes that the EP register contains 20938 a fixed address set to the address of the label called '__ep'. 20939 This can either be set up automatically by the linker, or 20940 specifically set by using the `--defsym __ep=<value>' command line 20941 option]. 20942 20943`zdaoff()' 20944 Computes the offset of the named variable from address 0 and 20945 stores the result as a 16 bit signed value in the immediate 20946 operand field of the given instruction. For example: 20947 20948 `movea zdaoff(_a_variable),zero,r6' 20949 20950 puts the address of the label '_a_variable' into register 6, 20951 assuming that the label is somewhere within the first 32K of 20952 memory. (Strictly speaking it also possible to access the last 20953 32K of memory as well, as the offsets are signed). 20954 20955`ctoff()' 20956 Computes the offset of the named variable from the start of the 20957 Call Table Area (whoes address is helg in system register 20, the 20958 CTBP register) and stores the result a 6 or 16 bit unsigned value 20959 in the immediate field of then given instruction or piece of data. 20960 For example: 20961 20962 `callt ctoff(table_func1)' 20963 20964 will put the call the function whoes address is held in the call 20965 table at the location labeled 'table_func1'. 20966 20967`.longcall `name'' 20968 Indicates that the following sequence of instructions is a long 20969 call to function `name'. The linker will attempt to shorten this 20970 call sequence if `name' is within a 22bit offset of the call. Only 20971 valid if the `-mrelax' command line switch has been enabled. 20972 20973`.longjump `name'' 20974 Indicates that the following sequence of instructions is a long 20975 jump to label `name'. The linker will attempt to shorten this code 20976 sequence if `name' is within a 22bit offset of the jump. Only 20977 valid if the `-mrelax' command line switch has been enabled. 20978 20979 20980 For information on the V850 instruction set, see `V850 Family 2098132-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC. 20982Ltd. 20983 20984 20985File: as.info, Node: XGATE-Dependent, Next: XSTORMY16-Dependent, Prev: V850-Dependent, Up: Machine Dependencies 20986 209879.50 XGATE Dependent Features 20988============================= 20989 20990* Menu: 20991 20992* XGATE-Opts:: XGATE Options 20993* XGATE-Syntax:: Syntax 20994* XGATE-Directives:: Assembler Directives 20995* XGATE-Float:: Floating Point 20996* XGATE-opcodes:: Opcodes 20997 20998 20999File: as.info, Node: XGATE-Opts, Next: XGATE-Syntax, Up: XGATE-Dependent 21000 210019.50.1 XGATE Options 21002-------------------- 21003 21004The Freescale XGATE version of `as' has a few machine dependent options. 21005 21006`-mshort' 21007 This option controls the ABI and indicates to use a 16-bit integer 21008 ABI. It has no effect on the assembled instructions. This is the 21009 default. 21010 21011`-mlong' 21012 This option controls the ABI and indicates to use a 32-bit integer 21013 ABI. 21014 21015`-mshort-double' 21016 This option controls the ABI and indicates to use a 32-bit float 21017 ABI. This is the default. 21018 21019`-mlong-double' 21020 This option controls the ABI and indicates to use a 64-bit float 21021 ABI. 21022 21023`--print-insn-syntax' 21024 You can use the `--print-insn-syntax' option to obtain the syntax 21025 description of the instruction when an error is detected. 21026 21027`--print-opcodes' 21028 The `--print-opcodes' option prints the list of all the 21029 instructions with their syntax. Once the list is printed `as' 21030 exits. 21031 21032 21033 21034File: as.info, Node: XGATE-Syntax, Next: XGATE-Directives, Prev: XGATE-Opts, Up: XGATE-Dependent 21035 210369.50.2 Syntax 21037------------- 21038 21039In XGATE RISC syntax, the instruction name comes first and it may be 21040followed by up to three operands. Operands are separated by commas 21041(`,'). `as' will complain if too many operands are specified for a 21042given instruction. The same will happen if you specified too few 21043operands. 21044 21045 nop 21046 ldl #23 21047 CMP R1, R2 21048 21049 The presence of a `;' character or a `!' character anywhere on a 21050line indicates the start of a comment that extends to the end of that 21051line. 21052 21053 A `*' or a `#' character at the start of a line also introduces a 21054line comment, but these characters do not work elsewhere on the line. 21055If the first character of the line is a `#' then as well as starting a 21056comment, the line could also be logical line number directive (*note 21057Comments::) or a preprocessor control command (*note Preprocessing::). 21058 21059 The XGATE assembler does not currently support a line separator 21060character. 21061 21062 The following addressing modes are understood for XGATE: 21063"Inherent" 21064 `' 21065 21066"Immediate 3 Bit Wide" 21067 `#NUMBER' 21068 21069"Immediate 4 Bit Wide" 21070 `#NUMBER' 21071 21072"Immediate 8 Bit Wide" 21073 `#NUMBER' 21074 21075"Monadic Addressing" 21076 `REG' 21077 21078"Dyadic Addressing" 21079 `REG, REG' 21080 21081"Triadic Addressing" 21082 `REG, REG, REG' 21083 21084"Relative Addressing 9 Bit Wide" 21085 `*SYMBOL' 21086 21087"Relative Addressing 10 Bit Wide" 21088 `*SYMBOL' 21089 21090"Index Register plus Immediate Offset" 21091 `REG, (REG, #NUMBER)' 21092 21093"Index Register plus Register Offset" 21094 `REG, REG, REG' 21095 21096"Index Register plus Register Offset with Post-increment" 21097 `REG, REG, REG+' 21098 21099"Index Register plus Register Offset with Pre-decrement" 21100 `REG, REG, -REG' 21101 21102 The register can be either `R0', `R1', `R2', `R3', `R4', `R5', 21103 `R6' or `R7'. 21104 21105 21106 Convience macro opcodes to deal with 16-bit values have been added. 21107 21108"Immediate 16 Bit Wide" 21109 `#NUMBER', or `*SYMBOL' 21110 21111 For example: 21112 21113 ldw R1, #1024 21114 ldw R3, timer 21115 ldw R1, (R1, #0) 21116 COM R1 21117 stw R2, (R1, #0) 21118 21119 21120File: as.info, Node: XGATE-Directives, Next: XGATE-Float, Prev: XGATE-Syntax, Up: XGATE-Dependent 21121 211229.50.3 Assembler Directives 21123--------------------------- 21124 21125The XGATE version of `as' have the following specific assembler 21126directives: 21127 21128 21129File: as.info, Node: XGATE-Float, Next: XGATE-opcodes, Prev: XGATE-Directives, Up: XGATE-Dependent 21130 211319.50.4 Floating Point 21132--------------------- 21133 21134Packed decimal (P) format floating literals are not supported(yet). 21135 21136 The floating point formats generated by directives are these. 21137 21138`.float' 21139 `Single' precision floating point constants. 21140 21141`.double' 21142 `Double' precision floating point constants. 21143 21144`.extend' 21145`.ldouble' 21146 `Extended' precision (`long double') floating point constants. 21147 21148 21149File: as.info, Node: XGATE-opcodes, Prev: XGATE-Float, Up: XGATE-Dependent 21150 211519.50.5 Opcodes 21152-------------- 21153 21154 21155File: as.info, Node: XSTORMY16-Dependent, Next: Xtensa-Dependent, Prev: XGATE-Dependent, Up: Machine Dependencies 21156 211579.51 XStormy16 Dependent Features 21158================================= 21159 21160* Menu: 21161 21162* XStormy16 Syntax:: Syntax 21163* XStormy16 Directives:: Machine Directives 21164* XStormy16 Opcodes:: Pseudo-Opcodes 21165 21166 21167File: as.info, Node: XStormy16 Syntax, Next: XStormy16 Directives, Up: XSTORMY16-Dependent 21168 211699.51.1 Syntax 21170------------- 21171 21172* Menu: 21173 21174* XStormy16-Chars:: Special Characters 21175 21176 21177File: as.info, Node: XStormy16-Chars, Up: XStormy16 Syntax 21178 211799.51.1.1 Special Characters 21180........................... 21181 21182`#' is the line comment character. If a `#' appears as the first 21183character of a line, the whole line is treated as a comment, but in 21184this case the line can also be a logical line number directive (*note 21185Comments::) or a preprocessor control command (*note Preprocessing::). 21186 21187 A semicolon (`;') can be used to start a comment that extends from 21188wherever the character appears on the line up to the end of the line. 21189 21190 The `|' character can be used to separate statements on the same 21191line. 21192 21193 21194File: as.info, Node: XStormy16 Directives, Next: XStormy16 Opcodes, Prev: XStormy16 Syntax, Up: XSTORMY16-Dependent 21195 211969.51.2 XStormy16 Machine Directives 21197----------------------------------- 21198 21199`.16bit_pointers' 21200 Like the `--16bit-pointers' command line option this directive 21201 indicates that the assembly code makes use of 16-bit pointers. 21202 21203`.32bit_pointers' 21204 Like the `--32bit-pointers' command line option this directive 21205 indicates that the assembly code makes use of 32-bit pointers. 21206 21207`.no_pointers' 21208 Like the `--no-pointers' command line option this directive 21209 indicates that the assembly code does not makes use pointers. 21210 21211 21212 21213File: as.info, Node: XStormy16 Opcodes, Prev: XStormy16 Directives, Up: XSTORMY16-Dependent 21214 212159.51.3 XStormy16 Pseudo-Opcodes 21216------------------------------- 21217 21218`as' implements all the standard XStormy16 opcodes. 21219 21220 `as' also implements the following pseudo ops: 21221 21222`@lo()' 21223 Computes the lower 16 bits of the given expression and stores it 21224 into the immediate operand field of the given instruction. For 21225 example: 21226 21227 `add r6, @lo(here - there)' 21228 21229 computes the difference between the address of labels 'here' and 21230 'there', takes the lower 16 bits of this difference and adds it to 21231 register 6. 21232 21233`@hi()' 21234 Computes the higher 16 bits of the given expression and stores it 21235 into the immediate operand field of the given instruction. For 21236 example: 21237 21238 `addc r7, @hi(here - there)' 21239 21240 computes the difference between the address of labels 'here' and 21241 'there', takes the upper 16 bits of this difference, shifts it 21242 down 16 bits and then adds it, along with the carry bit, to the 21243 value in register 7. 21244 21245 21246 21247File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: XSTORMY16-Dependent, Up: Machine Dependencies 21248 212499.52 Xtensa Dependent Features 21250============================== 21251 21252 This chapter covers features of the GNU assembler that are specific 21253to the Xtensa architecture. For details about the Xtensa instruction 21254set, please consult the `Xtensa Instruction Set Architecture (ISA) 21255Reference Manual'. 21256 21257* Menu: 21258 21259* Xtensa Options:: Command-line Options. 21260* Xtensa Syntax:: Assembler Syntax for Xtensa Processors. 21261* Xtensa Optimizations:: Assembler Optimizations. 21262* Xtensa Relaxation:: Other Automatic Transformations. 21263* Xtensa Directives:: Directives for Xtensa Processors. 21264 21265 21266File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent 21267 212689.52.1 Command Line Options 21269--------------------------- 21270 21271`--text-section-literals | --no-text-section-literals' 21272 Control the treatment of literal pools. The default is 21273 `--no-text-section-literals', which places literals in separate 21274 sections in the output file. This allows the literal pool to be 21275 placed in a data RAM/ROM. With `--text-section-literals', the 21276 literals are interspersed in the text section in order to keep 21277 them as close as possible to their references. This may be 21278 necessary for large assembly files, where the literals would 21279 otherwise be out of range of the `L32R' instructions in the text 21280 section. These options only affect literals referenced via 21281 PC-relative `L32R' instructions; literals for absolute mode `L32R' 21282 instructions are handled separately. *Note literal: Literal 21283 Directive. 21284 21285`--absolute-literals | --no-absolute-literals' 21286 Indicate to the assembler whether `L32R' instructions use absolute 21287 or PC-relative addressing. If the processor includes the absolute 21288 addressing option, the default is to use absolute `L32R' 21289 relocations. Otherwise, only the PC-relative `L32R' relocations 21290 can be used. 21291 21292`--target-align | --no-target-align' 21293 Enable or disable automatic alignment to reduce branch penalties 21294 at some expense in code size. *Note Automatic Instruction 21295 Alignment: Xtensa Automatic Alignment. This optimization is 21296 enabled by default. Note that the assembler will always align 21297 instructions like `LOOP' that have fixed alignment requirements. 21298 21299`--longcalls | --no-longcalls' 21300 Enable or disable transformation of call instructions to allow 21301 calls across a greater range of addresses. *Note Function Call 21302 Relaxation: Xtensa Call Relaxation. This option should be used 21303 when call targets can potentially be out of range. It may degrade 21304 both code size and performance, but the linker can generally 21305 optimize away the unnecessary overhead when a call ends up within 21306 range. The default is `--no-longcalls'. 21307 21308`--transform | --no-transform' 21309 Enable or disable all assembler transformations of Xtensa 21310 instructions, including both relaxation and optimization. The 21311 default is `--transform'; `--no-transform' should only be used in 21312 the rare cases when the instructions must be exactly as specified 21313 in the assembly source. Using `--no-transform' causes out of range 21314 instruction operands to be errors. 21315 21316`--rename-section OLDNAME=NEWNAME' 21317 Rename the OLDNAME section to NEWNAME. This option can be used 21318 multiple times to rename multiple sections. 21319 21320 21321File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent 21322 213239.52.2 Assembler Syntax 21324----------------------- 21325 21326Block comments are delimited by `/*' and `*/'. End of line comments 21327may be introduced with either `#' or `//'. 21328 21329 If a `#' appears as the first character of a line then the whole 21330line is treated as a comment, but in this case the line could also be a 21331logical line number directive (*note Comments::) or a preprocessor 21332control command (*note Preprocessing::). 21333 21334 Instructions consist of a leading opcode or macro name followed by 21335whitespace and an optional comma-separated list of operands: 21336 21337 OPCODE [OPERAND, ...] 21338 21339 Instructions must be separated by a newline or semicolon (`;'). 21340 21341 FLIX instructions, which bundle multiple opcodes together in a single 21342instruction, are specified by enclosing the bundled opcodes inside 21343braces: 21344 21345 { 21346 [FORMAT] 21347 OPCODE0 [OPERANDS] 21348 OPCODE1 [OPERANDS] 21349 OPCODE2 [OPERANDS] 21350 ... 21351 } 21352 21353 The opcodes in a FLIX instruction are listed in the same order as the 21354corresponding instruction slots in the TIE format declaration. 21355Directives and labels are not allowed inside the braces of a FLIX 21356instruction. A particular TIE format name can optionally be specified 21357immediately after the opening brace, but this is usually unnecessary. 21358The assembler will automatically search for a format that can encode the 21359specified opcodes, so the format name need only be specified in rare 21360cases where there is more than one applicable format and where it 21361matters which of those formats is used. A FLIX instruction can also be 21362specified on a single line by separating the opcodes with semicolons: 21363 21364 { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... } 21365 21366 If an opcode can only be encoded in a FLIX instruction but is not 21367specified as part of a FLIX bundle, the assembler will choose the 21368smallest format where the opcode can be encoded and will fill unused 21369instruction slots with no-ops. 21370 21371* Menu: 21372 21373* Xtensa Opcodes:: Opcode Naming Conventions. 21374* Xtensa Registers:: Register Naming. 21375 21376 21377File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax 21378 213799.52.2.1 Opcode Names 21380..................... 21381 21382See the `Xtensa Instruction Set Architecture (ISA) Reference Manual' 21383for a complete list of opcodes and descriptions of their semantics. 21384 21385 If an opcode name is prefixed with an underscore character (`_'), 21386`as' will not transform that instruction in any way. The underscore 21387prefix disables both optimization (*note Xtensa Optimizations: Xtensa 21388Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa 21389Relaxation.) for that particular instruction. Only use the underscore 21390prefix when it is essential to select the exact opcode produced by the 21391assembler. Using this feature unnecessarily makes the code less 21392efficient by disabling assembler optimization and less flexible by 21393disabling relaxation. 21394 21395 Note that this special handling of underscore prefixes only applies 21396to Xtensa opcodes, not to either built-in macros or user-defined macros. 21397When an underscore prefix is used with a macro (e.g., `_MOV'), it 21398refers to a different macro. The assembler generally provides built-in 21399macros both with and without the underscore prefix, where the underscore 21400versions behave as if the underscore carries through to the instructions 21401in the macros. For example, `_MOV' may expand to `_MOV.N'. 21402 21403 The underscore prefix only applies to individual instructions, not to 21404series of instructions. For example, if a series of instructions have 21405underscore prefixes, the assembler will not transform the individual 21406instructions, but it may insert other instructions between them (e.g., 21407to align a `LOOP' instruction). To prevent the assembler from 21408modifying a series of instructions as a whole, use the `no-transform' 21409directive. *Note transform: Transform Directive. 21410 21411 21412File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax 21413 214149.52.2.2 Register Names 21415....................... 21416 21417The assembly syntax for a register file entry is the "short" name for a 21418TIE register file followed by the index into that register file. For 21419example, the general-purpose `AR' register file has a short name of 21420`a', so these registers are named `a0'...`a15'. As a special feature, 21421`sp' is also supported as a synonym for `a1'. Additional registers may 21422be added by processor configuration options and by designer-defined TIE 21423extensions. An initial `$' character is optional in all register names. 21424 21425 21426File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent 21427 214289.52.3 Xtensa Optimizations 21429--------------------------- 21430 21431The optimizations currently supported by `as' are generation of density 21432instructions where appropriate and automatic branch target alignment. 21433 21434* Menu: 21435 21436* Density Instructions:: Using Density Instructions. 21437* Xtensa Automatic Alignment:: Automatic Instruction Alignment. 21438 21439 21440File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations 21441 214429.52.3.1 Using Density Instructions 21443................................... 21444 21445The Xtensa instruction set has a code density option that provides 2144616-bit versions of some of the most commonly used opcodes. Use of these 21447opcodes can significantly reduce code size. When possible, the 21448assembler automatically translates instructions from the core Xtensa 21449instruction set into equivalent instructions from the Xtensa code 21450density option. This translation can be disabled by using underscore 21451prefixes (*note Opcode Names: Xtensa Opcodes.), by using the 21452`--no-transform' command-line option (*note Command Line Options: 21453Xtensa Options.), or by using the `no-transform' directive (*note 21454transform: Transform Directive.). 21455 21456 It is a good idea _not_ to use the density instructions directly. 21457The assembler will automatically select dense instructions where 21458possible. If you later need to use an Xtensa processor without the code 21459density option, the same assembly code will then work without 21460modification. 21461 21462 21463File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations 21464 214659.52.3.2 Automatic Instruction Alignment 21466........................................ 21467 21468The Xtensa assembler will automatically align certain instructions, both 21469to optimize performance and to satisfy architectural requirements. 21470 21471 As an optimization to improve performance, the assembler attempts to 21472align branch targets so they do not cross instruction fetch boundaries. 21473(Xtensa processors can be configured with either 32-bit or 64-bit 21474instruction fetch widths.) An instruction immediately following a call 21475is treated as a branch target in this context, because it will be the 21476target of a return from the call. This alignment has the potential to 21477reduce branch penalties at some expense in code size. This 21478optimization is enabled by default. You can disable it with the 21479`--no-target-align' command-line option (*note Command Line Options: 21480Xtensa Options.). 21481 21482 The target alignment optimization is done without adding instructions 21483that could increase the execution time of the program. If there are 21484density instructions in the code preceding a target, the assembler can 21485change the target alignment by widening some of those instructions to 21486the equivalent 24-bit instructions. Extra bytes of padding can be 21487inserted immediately following unconditional jump and return 21488instructions. This approach is usually successful in aligning many, 21489but not all, branch targets. 21490 21491 The `LOOP' family of instructions must be aligned such that the 21492first instruction in the loop body does not cross an instruction fetch 21493boundary (e.g., with a 32-bit fetch width, a `LOOP' instruction must be 21494on either a 1 or 2 mod 4 byte boundary). The assembler knows about 21495this restriction and inserts the minimal number of 2 or 3 byte no-op 21496instructions to satisfy it. When no-op instructions are added, any 21497label immediately preceding the original loop will be moved in order to 21498refer to the loop instruction, not the newly generated no-op 21499instruction. To preserve binary compatibility across processors with 21500different fetch widths, the assembler conservatively assumes a 32-bit 21501fetch width when aligning `LOOP' instructions (except if the first 21502instruction in the loop is a 64-bit instruction). 21503 21504 Previous versions of the assembler automatically aligned `ENTRY' 21505instructions to 4-byte boundaries, but that alignment is now the 21506programmer's responsibility. 21507 21508 21509File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent 21510 215119.52.4 Xtensa Relaxation 21512------------------------ 21513 21514When an instruction operand is outside the range allowed for that 21515particular instruction field, `as' can transform the code to use a 21516functionally-equivalent instruction or sequence of instructions. This 21517process is known as "relaxation". This is typically done for branch 21518instructions because the distance of the branch targets is not known 21519until assembly-time. The Xtensa assembler offers branch relaxation and 21520also extends this concept to function calls, `MOVI' instructions and 21521other instructions with immediate fields. 21522 21523* Menu: 21524 21525* Xtensa Branch Relaxation:: Relaxation of Branches. 21526* Xtensa Call Relaxation:: Relaxation of Function Calls. 21527* Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields. 21528 21529 21530File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation 21531 215329.52.4.1 Conditional Branch Relaxation 21533...................................... 21534 21535When the target of a branch is too far away from the branch itself, 21536i.e., when the offset from the branch to the target is too large to fit 21537in the immediate field of the branch instruction, it may be necessary to 21538replace the branch with a branch around a jump. For example, 21539 21540 beqz a2, L 21541 21542 may result in: 21543 21544 bnez.n a2, M 21545 j L 21546 M: 21547 21548 (The `BNEZ.N' instruction would be used in this example only if the 21549density option is available. Otherwise, `BNEZ' would be used.) 21550 21551 This relaxation works well because the unconditional jump instruction 21552has a much larger offset range than the various conditional branches. 21553However, an error will occur if a branch target is beyond the range of a 21554jump instruction. `as' cannot relax unconditional jumps. Similarly, 21555an error will occur if the original input contains an unconditional 21556jump to a target that is out of range. 21557 21558 Branch relaxation is enabled by default. It can be disabled by using 21559underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the 21560`--no-transform' command-line option (*note Command Line Options: 21561Xtensa Options.), or the `no-transform' directive (*note transform: 21562Transform Directive.). 21563 21564 21565File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation 21566 215679.52.4.2 Function Call Relaxation 21568................................. 21569 21570Function calls may require relaxation because the Xtensa immediate call 21571instructions (`CALL0', `CALL4', `CALL8' and `CALL12') provide a 21572PC-relative offset of only 512 Kbytes in either direction. For larger 21573programs, it may be necessary to use indirect calls (`CALLX0', 21574`CALLX4', `CALLX8' and `CALLX12') where the target address is specified 21575in a register. The Xtensa assembler can automatically relax immediate 21576call instructions into indirect call instructions. This relaxation is 21577done by loading the address of the called function into the callee's 21578return address register and then using a `CALLX' instruction. So, for 21579example: 21580 21581 call8 func 21582 21583 might be relaxed to: 21584 21585 .literal .L1, func 21586 l32r a8, .L1 21587 callx8 a8 21588 21589 Because the addresses of targets of function calls are not generally 21590known until link-time, the assembler must assume the worst and relax all 21591the calls to functions in other source files, not just those that really 21592will be out of range. The linker can recognize calls that were 21593unnecessarily relaxed, and it will remove the overhead introduced by the 21594assembler for those cases where direct calls are sufficient. 21595 21596 Call relaxation is disabled by default because it can have a negative 21597effect on both code size and performance, although the linker can 21598usually eliminate the unnecessary overhead. If a program is too large 21599and some of the calls are out of range, function call relaxation can be 21600enabled using the `--longcalls' command-line option or the `longcalls' 21601directive (*note longcalls: Longcalls Directive.). 21602 21603 21604File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation 21605 216069.52.4.3 Other Immediate Field Relaxation 21607......................................... 21608 21609The assembler normally performs the following other relaxations. They 21610can be disabled by using underscore prefixes (*note Opcode Names: 21611Xtensa Opcodes.), the `--no-transform' command-line option (*note 21612Command Line Options: Xtensa Options.), or the `no-transform' directive 21613(*note transform: Transform Directive.). 21614 21615 The `MOVI' machine instruction can only materialize values in the 21616range from -2048 to 2047. Values outside this range are best 21617materialized with `L32R' instructions. Thus: 21618 21619 movi a0, 100000 21620 21621 is assembled into the following machine code: 21622 21623 .literal .L1, 100000 21624 l32r a0, .L1 21625 21626 The `L8UI' machine instruction can only be used with immediate 21627offsets in the range from 0 to 255. The `L16SI' and `L16UI' machine 21628instructions can only be used with offsets from 0 to 510. The `L32I' 21629machine instruction can only be used with offsets from 0 to 1020. A 21630load offset outside these ranges can be materialized with an `L32R' 21631instruction if the destination register of the load is different than 21632the source address register. For example: 21633 21634 l32i a1, a0, 2040 21635 21636 is translated to: 21637 21638 .literal .L1, 2040 21639 l32r a1, .L1 21640 add a1, a0, a1 21641 l32i a1, a1, 0 21642 21643If the load destination and source address register are the same, an 21644out-of-range offset causes an error. 21645 21646 The Xtensa `ADDI' instruction only allows immediate operands in the 21647range from -128 to 127. There are a number of alternate instruction 21648sequences for the `ADDI' operation. First, if the immediate is 0, the 21649`ADDI' will be turned into a `MOV.N' instruction (or the equivalent 21650`OR' instruction if the code density option is not available). If the 21651`ADDI' immediate is outside of the range -128 to 127, but inside the 21652range -32896 to 32639, an `ADDMI' instruction or `ADDMI'/`ADDI' 21653sequence will be used. Finally, if the immediate is outside of this 21654range and a free register is available, an `L32R'/`ADD' sequence will 21655be used with a literal allocated from the literal pool. 21656 21657 For example: 21658 21659 addi a5, a6, 0 21660 addi a5, a6, 512 21661 addi a5, a6, 513 21662 addi a5, a6, 50000 21663 21664 is assembled into the following: 21665 21666 .literal .L1, 50000 21667 mov.n a5, a6 21668 addmi a5, a6, 0x200 21669 addmi a5, a6, 0x200 21670 addi a5, a5, 1 21671 l32r a5, .L1 21672 add a5, a6, a5 21673 21674 21675File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent 21676 216779.52.5 Directives 21678----------------- 21679 21680The Xtensa assembler supports a region-based directive syntax: 21681 21682 .begin DIRECTIVE [OPTIONS] 21683 ... 21684 .end DIRECTIVE 21685 21686 All the Xtensa-specific directives that apply to a region of code use 21687this syntax. 21688 21689 The directive applies to code between the `.begin' and the `.end'. 21690The state of the option after the `.end' reverts to what it was before 21691the `.begin'. A nested `.begin'/`.end' region can further change the 21692state of the directive without having to be aware of its outer state. 21693For example, consider: 21694 21695 .begin no-transform 21696 L: add a0, a1, a2 21697 .begin transform 21698 M: add a0, a1, a2 21699 .end transform 21700 N: add a0, a1, a2 21701 .end no-transform 21702 21703 The `ADD' opcodes at `L' and `N' in the outer `no-transform' region 21704both result in `ADD' machine instructions, but the assembler selects an 21705`ADD.N' instruction for the `ADD' at `M' in the inner `transform' 21706region. 21707 21708 The advantage of this style is that it works well inside macros 21709which can preserve the context of their callers. 21710 21711 The following directives are available: 21712 21713* Menu: 21714 21715* Schedule Directive:: Enable instruction scheduling. 21716* Longcalls Directive:: Use Indirect Calls for Greater Range. 21717* Transform Directive:: Disable All Assembler Transformations. 21718* Literal Directive:: Intermix Literals with Instructions. 21719* Literal Position Directive:: Specify Inline Literal Pool Locations. 21720* Literal Prefix Directive:: Specify Literal Section Name Prefix. 21721* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals. 21722 21723 21724File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives 21725 217269.52.5.1 schedule 21727................. 21728 21729The `schedule' directive is recognized only for compatibility with 21730Tensilica's assembler. 21731 21732 .begin [no-]schedule 21733 .end [no-]schedule 21734 21735 This directive is ignored and has no effect on `as'. 21736 21737 21738File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives 21739 217409.52.5.2 longcalls 21741.................. 21742 21743The `longcalls' directive enables or disables function call relaxation. 21744*Note Function Call Relaxation: Xtensa Call Relaxation. 21745 21746 .begin [no-]longcalls 21747 .end [no-]longcalls 21748 21749 Call relaxation is disabled by default unless the `--longcalls' 21750command-line option is specified. The `longcalls' directive overrides 21751the default determined by the command-line options. 21752 21753 21754File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives 21755 217569.52.5.3 transform 21757.................. 21758 21759This directive enables or disables all assembler transformation, 21760including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and 21761optimization (*note Xtensa Optimizations: Xtensa Optimizations.). 21762 21763 .begin [no-]transform 21764 .end [no-]transform 21765 21766 Transformations are enabled by default unless the `--no-transform' 21767option is used. The `transform' directive overrides the default 21768determined by the command-line options. An underscore opcode prefix, 21769disabling transformation of that opcode, always takes precedence over 21770both directives and command-line flags. 21771 21772 21773File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives 21774 217759.52.5.4 literal 21776................ 21777 21778The `.literal' directive is used to define literal pool data, i.e., 21779read-only 32-bit data accessed via `L32R' instructions. 21780 21781 .literal LABEL, VALUE[, VALUE...] 21782 21783 This directive is similar to the standard `.word' directive, except 21784that the actual location of the literal data is determined by the 21785assembler and linker, not by the position of the `.literal' directive. 21786Using this directive gives the assembler freedom to locate the literal 21787data in the most appropriate place and possibly to combine identical 21788literals. For example, the code: 21789 21790 entry sp, 40 21791 .literal .L1, sym 21792 l32r a4, .L1 21793 21794 can be used to load a pointer to the symbol `sym' into register 21795`a4'. The value of `sym' will not be placed between the `ENTRY' and 21796`L32R' instructions; instead, the assembler puts the data in a literal 21797pool. 21798 21799 Literal pools are placed by default in separate literal sections; 21800however, when using the `--text-section-literals' option (*note Command 21801Line Options: Xtensa Options.), the literal pools for PC-relative mode 21802`L32R' instructions are placed in the current section.(1) These text 21803section literal pools are created automatically before `ENTRY' 21804instructions and manually after `.literal_position' directives (*note 21805literal_position: Literal Position Directive.). If there are no 21806preceding `ENTRY' instructions, explicit `.literal_position' directives 21807must be used to place the text section literal pools; otherwise, `as' 21808will report an error. 21809 21810 When literals are placed in separate sections, the literal section 21811names are derived from the names of the sections where the literals are 21812defined. The base literal section names are `.literal' for PC-relative 21813mode `L32R' instructions and `.lit4' for absolute mode `L32R' 21814instructions (*note absolute-literals: Absolute Literals Directive.). 21815These base names are used for literals defined in the default `.text' 21816section. For literals defined in other sections or within the scope of 21817a `literal_prefix' directive (*note literal_prefix: Literal Prefix 21818Directive.), the following rules determine the literal section name: 21819 21820 1. If the current section is a member of a section group, the literal 21821 section name includes the group name as a suffix to the base 21822 `.literal' or `.lit4' name, with a period to separate the base 21823 name and group name. The literal section is also made a member of 21824 the group. 21825 21826 2. If the current section name (or `literal_prefix' value) begins with 21827 "`.gnu.linkonce.KIND.'", the literal section name is formed by 21828 replacing "`.KIND'" with the base `.literal' or `.lit4' name. For 21829 example, for literals defined in a section named 21830 `.gnu.linkonce.t.func', the literal section will be 21831 `.gnu.linkonce.literal.func' or `.gnu.linkonce.lit4.func'. 21832 21833 3. If the current section name (or `literal_prefix' value) ends with 21834 `.text', the literal section name is formed by replacing that 21835 suffix with the base `.literal' or `.lit4' name. For example, for 21836 literals defined in a section named `.iram0.text', the literal 21837 section will be `.iram0.literal' or `.iram0.lit4'. 21838 21839 4. If none of the preceding conditions apply, the literal section 21840 name is formed by adding the base `.literal' or `.lit4' name as a 21841 suffix to the current section name (or `literal_prefix' value). 21842 21843 ---------- Footnotes ---------- 21844 21845 (1) Literals for the `.init' and `.fini' sections are always placed 21846in separate sections, even when `--text-section-literals' is enabled. 21847 21848 21849File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives 21850 218519.52.5.5 literal_position 21852......................... 21853 21854When using `--text-section-literals' to place literals inline in the 21855section being assembled, the `.literal_position' directive can be used 21856to mark a potential location for a literal pool. 21857 21858 .literal_position 21859 21860 The `.literal_position' directive is ignored when the 21861`--text-section-literals' option is not used or when `L32R' 21862instructions use the absolute addressing mode. 21863 21864 The assembler will automatically place text section literal pools 21865before `ENTRY' instructions, so the `.literal_position' directive is 21866only needed to specify some other location for a literal pool. You may 21867need to add an explicit jump instruction to skip over an inline literal 21868pool. 21869 21870 For example, an interrupt vector does not begin with an `ENTRY' 21871instruction so the assembler will be unable to automatically find a good 21872place to put a literal pool. Moreover, the code for the interrupt 21873vector must be at a specific starting address, so the literal pool 21874cannot come before the start of the code. The literal pool for the 21875vector must be explicitly positioned in the middle of the vector (before 21876any uses of the literals, due to the negative offsets used by 21877PC-relative `L32R' instructions). The `.literal_position' directive 21878can be used to do this. In the following code, the literal for `M' 21879will automatically be aligned correctly and is placed after the 21880unconditional jump. 21881 21882 .global M 21883 code_start: 21884 j continue 21885 .literal_position 21886 .align 4 21887 continue: 21888 movi a4, M 21889 21890 21891File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives 21892 218939.52.5.6 literal_prefix 21894....................... 21895 21896The `literal_prefix' directive allows you to override the default 21897literal section names, which are derived from the names of the sections 21898where the literals are defined. 21899 21900 .begin literal_prefix [NAME] 21901 .end literal_prefix 21902 21903 For literals defined within the delimited region, the literal section 21904names are derived from the NAME argument instead of the name of the 21905current section. The rules used to derive the literal section names do 21906not change. *Note literal: Literal Directive. If the NAME argument is 21907omitted, the literal sections revert to the defaults. This directive 21908has no effect when using the `--text-section-literals' option (*note 21909Command Line Options: Xtensa Options.). 21910 21911 21912File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives 21913 219149.52.5.7 absolute-literals 21915.......................... 21916 21917The `absolute-literals' and `no-absolute-literals' directives control 21918the absolute vs. PC-relative mode for `L32R' instructions. These are 21919relevant only for Xtensa configurations that include the absolute 21920addressing option for `L32R' instructions. 21921 21922 .begin [no-]absolute-literals 21923 .end [no-]absolute-literals 21924 21925 These directives do not change the `L32R' mode--they only cause the 21926assembler to emit the appropriate kind of relocation for `L32R' 21927instructions and to place the literal values in the appropriate section. 21928To change the `L32R' mode, the program must write the `LITBASE' special 21929register. It is the programmer's responsibility to keep track of the 21930mode and indicate to the assembler which mode is used in each region of 21931code. 21932 21933 If the Xtensa configuration includes the absolute `L32R' addressing 21934option, the default is to assume absolute `L32R' addressing unless the 21935`--no-absolute-literals' command-line option is specified. Otherwise, 21936the default is to assume PC-relative `L32R' addressing. The 21937`absolute-literals' directive can then be used to override the default 21938determined by the command-line options. 21939 21940 21941File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top 21942 2194310 Reporting Bugs 21944***************** 21945 21946Your bug reports play an essential role in making `as' reliable. 21947 21948 Reporting a bug may help you by bringing a solution to your problem, 21949or it may not. But in any case the principal function of a bug report 21950is to help the entire community by making the next version of `as' work 21951better. Bug reports are your contribution to the maintenance of `as'. 21952 21953 In order for a bug report to serve its purpose, you must include the 21954information that enables us to fix the bug. 21955 21956* Menu: 21957 21958* Bug Criteria:: Have you found a bug? 21959* Bug Reporting:: How to report bugs 21960 21961 21962File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs 21963 2196410.1 Have You Found a Bug? 21965========================== 21966 21967If you are not sure whether you have found a bug, here are some 21968guidelines: 21969 21970 * If the assembler gets a fatal signal, for any input whatever, that 21971 is a `as' bug. Reliable assemblers never crash. 21972 21973 * If `as' produces an error message for valid input, that is a bug. 21974 21975 * If `as' does not produce an error message for invalid input, that 21976 is a bug. However, you should note that your idea of "invalid 21977 input" might be our idea of "an extension" or "support for 21978 traditional practice". 21979 21980 * If you are an experienced user of assemblers, your suggestions for 21981 improvement of `as' are welcome in any case. 21982 21983 21984File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs 21985 2198610.2 How to Report Bugs 21987======================= 21988 21989A number of companies and individuals offer support for GNU products. 21990If you obtained `as' from a support organization, we recommend you 21991contact that organization first. 21992 21993 You can find contact information for many support companies and 21994individuals in the file `etc/SERVICE' in the GNU Emacs distribution. 21995 21996 In any event, we also recommend that you send bug reports for `as' 21997to `https://sourcery.mentor.com/GNUToolchain/'. 21998 21999 The fundamental principle of reporting bugs usefully is this: 22000*report all the facts*. If you are not sure whether to state a fact or 22001leave it out, state it! 22002 22003 Often people omit facts because they think they know what causes the 22004problem and assume that some details do not matter. Thus, you might 22005assume that the name of a symbol you use in an example does not matter. 22006Well, probably it does not, but one cannot be sure. Perhaps the bug is 22007a stray memory reference which happens to fetch from the location where 22008that name is stored in memory; perhaps, if the name were different, the 22009contents of that location would fool the assembler into doing the right 22010thing despite the bug. Play it safe and give a specific, complete 22011example. That is the easiest thing for you to do, and the most helpful. 22012 22013 Keep in mind that the purpose of a bug report is to enable us to fix 22014the bug if it is new to us. Therefore, always write your bug reports 22015on the assumption that the bug has not been reported previously. 22016 22017 Sometimes people give a few sketchy facts and ask, "Does this ring a 22018bell?" This cannot help us fix a bug, so it is basically useless. We 22019respond by asking for enough details to enable us to investigate. You 22020might as well expedite matters by sending them to begin with. 22021 22022 To enable us to fix the bug, you should include all these things: 22023 22024 * The version of `as'. `as' announces it if you start it with the 22025 `--version' argument. 22026 22027 Without this, we will not know whether there is any point in 22028 looking for the bug in the current version of `as'. 22029 22030 * Any patches you may have applied to the `as' source. 22031 22032 * The type of machine you are using, and the operating system name 22033 and version number. 22034 22035 * What compiler (and its version) was used to compile `as'--e.g. 22036 "`gcc-2.7'". 22037 22038 * The command arguments you gave the assembler to assemble your 22039 example and observe the bug. To guarantee you will not omit 22040 something important, list them all. A copy of the Makefile (or 22041 the output from make) is sufficient. 22042 22043 If we were to try to guess the arguments, we would probably guess 22044 wrong and then we might not encounter the bug. 22045 22046 * A complete input file that will reproduce the bug. If the bug is 22047 observed when the assembler is invoked via a compiler, send the 22048 assembler source, not the high level language source. Most 22049 compilers will produce the assembler source when run with the `-S' 22050 option. If you are using `gcc', use the options `-v 22051 --save-temps'; this will save the assembler source in a file with 22052 an extension of `.s', and also show you exactly how `as' is being 22053 run. 22054 22055 * A description of what behavior you observe that you believe is 22056 incorrect. For example, "It gets a fatal signal." 22057 22058 Of course, if the bug is that `as' gets a fatal signal, then we 22059 will certainly notice it. But if the bug is incorrect output, we 22060 might not notice unless it is glaringly wrong. You might as well 22061 not give us a chance to make a mistake. 22062 22063 Even if the problem you experience is a fatal signal, you should 22064 still say so explicitly. Suppose something strange is going on, 22065 such as, your copy of `as' is out of sync, or you have encountered 22066 a bug in the C library on your system. (This has happened!) Your 22067 copy might crash and ours would not. If you told us to expect a 22068 crash, then when ours fails to crash, we would know that the bug 22069 was not happening for us. If you had not told us to expect a 22070 crash, then we would not be able to draw any conclusion from our 22071 observations. 22072 22073 * If you wish to suggest changes to the `as' source, send us context 22074 diffs, as generated by `diff' with the `-u', `-c', or `-p' option. 22075 Always send diffs from the old file to the new file. If you even 22076 discuss something in the `as' source, refer to it by context, not 22077 by line number. 22078 22079 The line numbers in our development sources will not match those 22080 in your sources. Your line numbers would convey no useful 22081 information to us. 22082 22083 Here are some things that are not necessary: 22084 22085 * A description of the envelope of the bug. 22086 22087 Often people who encounter a bug spend a lot of time investigating 22088 which changes to the input file will make the bug go away and which 22089 changes will not affect it. 22090 22091 This is often time consuming and not very useful, because the way 22092 we will find the bug is by running a single example under the 22093 debugger with breakpoints, not by pure deduction from a series of 22094 examples. We recommend that you save your time for something else. 22095 22096 Of course, if you can find a simpler example to report _instead_ 22097 of the original one, that is a convenience for us. Errors in the 22098 output will be easier to spot, running under the debugger will take 22099 less time, and so on. 22100 22101 However, simplification is not vital; if you do not want to do 22102 this, report the bug anyway and send us the entire test case you 22103 used. 22104 22105 * A patch for the bug. 22106 22107 A patch for the bug does help us if it is a good one. But do not 22108 omit the necessary information, such as the test case, on the 22109 assumption that a patch is all we need. We might see problems 22110 with your patch and decide to fix the problem another way, or we 22111 might not understand it at all. 22112 22113 Sometimes with a program as complicated as `as' it is very hard to 22114 construct an example that will make the program follow a certain 22115 path through the code. If you do not send us the example, we will 22116 not be able to construct one, so we will not be able to verify 22117 that the bug is fixed. 22118 22119 And if we cannot understand what bug you are trying to fix, or why 22120 your patch should be an improvement, we will not install it. A 22121 test case will help us to understand. 22122 22123 * A guess about what the bug is or what it depends on. 22124 22125 Such guesses are usually wrong. Even we cannot guess right about 22126 such things without first using the debugger to find the facts. 22127 22128 22129File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top 22130 2213111 Acknowledgements 22132******************* 22133 22134If you have contributed to GAS and your name isn't listed here, it is 22135not meant as a slight. We just don't know about it. Send mail to the 22136maintainer, and we'll correct the situation. Currently the maintainer 22137is Nick Clifton (email address `nickc@redhat.com'). 22138 22139 Dean Elsner wrote the original GNU assembler for the VAX.(1) 22140 22141 Jay Fenlason maintained GAS for a while, adding support for 22142GDB-specific debug information and the 68k series machines, most of the 22143preprocessing pass, and extensive changes in `messages.c', 22144`input-file.c', `write.c'. 22145 22146 K. Richard Pixley maintained GAS for a while, adding various 22147enhancements and many bug fixes, including merging support for several 22148processors, breaking GAS up to handle multiple object file format back 22149ends (including heavy rewrite, testing, an integration of the coff and 22150b.out back ends), adding configuration including heavy testing and 22151verification of cross assemblers and file splits and renaming, 22152converted GAS to strictly ANSI C including full prototypes, added 22153support for m680[34]0 and cpu32, did considerable work on i960 22154including a COFF port (including considerable amounts of reverse 22155engineering), a SPARC opcode file rewrite, DECstation, rs6000, and 22156hp300hpux host ports, updated "know" assertions and made them work, 22157much other reorganization, cleanup, and lint. 22158 22159 Ken Raeburn wrote the high-level BFD interface code to replace most 22160of the code in format-specific I/O modules. 22161 22162 The original VMS support was contributed by David L. Kashtan. Eric 22163Youngdale has done much work with it since. 22164 22165 The Intel 80386 machine description was written by Eliot Dresselhaus. 22166 22167 Minh Tran-Le at IntelliCorp contributed some AIX 386 support. 22168 22169 The Motorola 88k machine description was contributed by Devon Bowen 22170of Buffalo University and Torbjorn Granlund of the Swedish Institute of 22171Computer Science. 22172 22173 Keith Knowles at the Open Software Foundation wrote the original 22174MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format 22175support (which hasn't been merged in yet). Ralph Campbell worked with 22176the MIPS code to support a.out format. 22177 22178 Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k, 22179tc-h8300), and IEEE 695 object file format (obj-ieee), was written by 22180Steve Chamberlain of Cygnus Support. Steve also modified the COFF back 22181end to use BFD for some low-level operations, for use with the H8/300 22182and AMD 29k targets. 22183 22184 John Gilmore built the AMD 29000 support, added `.include' support, 22185and simplified the configuration of which versions accept which 22186directives. He updated the 68k machine description so that Motorola's 22187opcodes always produced fixed-size instructions (e.g., `jsr'), while 22188synthetic instructions remained shrinkable (`jbsr'). John fixed many 22189bugs, including true tested cross-compilation support, and one bug in 22190relaxation that took a week and required the proverbial one-bit fix. 22191 22192 Ian Lance Taylor of Cygnus Support merged the Motorola and MIT 22193syntax for the 68k, completed support for some COFF targets (68k, i386 22194SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets, 22195wrote the initial RS/6000 and PowerPC assembler, and made a few other 22196minor patches. 22197 22198 Steve Chamberlain made GAS able to generate listings. 22199 22200 Hewlett-Packard contributed support for the HP9000/300. 22201 22202 Jeff Law wrote GAS and BFD support for the native HPPA object format 22203(SOM) along with a fairly extensive HPPA testsuite (for both SOM and 22204ELF object formats). This work was supported by both the Center for 22205Software Science at the University of Utah and Cygnus Support. 22206 22207 Support for ELF format files has been worked on by Mark Eichin of 22208Cygnus Support (original, incomplete implementation for SPARC), Pete 22209Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), 22210Michael Meissner of the Open Software Foundation (i386 mainly), and Ken 22211Raeburn of Cygnus Support (sparc, and some initial 64-bit support). 22212 22213 Linas Vepstas added GAS support for the ESA/390 "IBM 370" 22214architecture. 22215 22216 Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote 22217GAS and BFD support for openVMS/Alpha. 22218 22219 Timothy Wall, Michael Hayes, and Greg Smart contributed to the 22220various tic* flavors. 22221 22222 David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from 22223Tensilica, Inc. added support for Xtensa processors. 22224 22225 Several engineers at Cygnus Support have also provided many small 22226bug fixes and configuration enhancements. 22227 22228 Jon Beniston added support for the Lattice Mico32 architecture. 22229 22230 Many others have contributed large or small bugfixes and 22231enhancements. If you have contributed significant work and are not 22232mentioned on this list, and want to be, let us know. Some of the 22233history has been lost; we are not intentionally leaving anyone out. 22234 22235 ---------- Footnotes ---------- 22236 22237 (1) Any more details? 22238 22239 22240File: as.info, Node: GNU Free Documentation License, Next: AS Index, Prev: Acknowledgements, Up: Top 22241 22242Appendix A GNU Free Documentation License 22243***************************************** 22244 22245 Version 1.3, 3 November 2008 22246 22247 Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. 22248 `http://fsf.org/' 22249 22250 Everyone is permitted to copy and distribute verbatim copies 22251 of this license document, but changing it is not allowed. 22252 22253 0. PREAMBLE 22254 22255 The purpose of this License is to make a manual, textbook, or other 22256 functional and useful document "free" in the sense of freedom: to 22257 assure everyone the effective freedom to copy and redistribute it, 22258 with or without modifying it, either commercially or 22259 noncommercially. Secondarily, this License preserves for the 22260 author and publisher a way to get credit for their work, while not 22261 being considered responsible for modifications made by others. 22262 22263 This License is a kind of "copyleft", which means that derivative 22264 works of the document must themselves be free in the same sense. 22265 It complements the GNU General Public License, which is a copyleft 22266 license designed for free software. 22267 22268 We have designed this License in order to use it for manuals for 22269 free software, because free software needs free documentation: a 22270 free program should come with manuals providing the same freedoms 22271 that the software does. But this License is not limited to 22272 software manuals; it can be used for any textual work, regardless 22273 of subject matter or whether it is published as a printed book. 22274 We recommend this License principally for works whose purpose is 22275 instruction or reference. 22276 22277 1. APPLICABILITY AND DEFINITIONS 22278 22279 This License applies to any manual or other work, in any medium, 22280 that contains a notice placed by the copyright holder saying it 22281 can be distributed under the terms of this License. Such a notice 22282 grants a world-wide, royalty-free license, unlimited in duration, 22283 to use that work under the conditions stated herein. The 22284 "Document", below, refers to any such manual or work. Any member 22285 of the public is a licensee, and is addressed as "you". You 22286 accept the license if you copy, modify or distribute the work in a 22287 way requiring permission under copyright law. 22288 22289 A "Modified Version" of the Document means any work containing the 22290 Document or a portion of it, either copied verbatim, or with 22291 modifications and/or translated into another language. 22292 22293 A "Secondary Section" is a named appendix or a front-matter section 22294 of the Document that deals exclusively with the relationship of the 22295 publishers or authors of the Document to the Document's overall 22296 subject (or to related matters) and contains nothing that could 22297 fall directly within that overall subject. (Thus, if the Document 22298 is in part a textbook of mathematics, a Secondary Section may not 22299 explain any mathematics.) The relationship could be a matter of 22300 historical connection with the subject or with related matters, or 22301 of legal, commercial, philosophical, ethical or political position 22302 regarding them. 22303 22304 The "Invariant Sections" are certain Secondary Sections whose 22305 titles are designated, as being those of Invariant Sections, in 22306 the notice that says that the Document is released under this 22307 License. If a section does not fit the above definition of 22308 Secondary then it is not allowed to be designated as Invariant. 22309 The Document may contain zero Invariant Sections. If the Document 22310 does not identify any Invariant Sections then there are none. 22311 22312 The "Cover Texts" are certain short passages of text that are 22313 listed, as Front-Cover Texts or Back-Cover Texts, in the notice 22314 that says that the Document is released under this License. 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A 22330 copy that is not "Transparent" is called "Opaque". 22331 22332 Examples of suitable formats for Transparent copies include plain 22333 ASCII without markup, Texinfo input format, LaTeX input format, 22334 SGML or XML using a publicly available DTD, and 22335 standard-conforming simple HTML, PostScript or PDF designed for 22336 human modification. Examples of transparent image formats include 22337 PNG, XCF and JPG. Opaque formats include proprietary formats that 22338 can be read and edited only by proprietary word processors, SGML or 22339 XML for which the DTD and/or processing tools are not generally 22340 available, and the machine-generated HTML, PostScript or PDF 22341 produced by some word processors for output purposes only. 22342 22343 The "Title Page" means, for a printed book, the title page itself, 22344 plus such following pages as are needed to hold, legibly, the 22345 material this License requires to appear in the title page. For 22346 works in formats which do not have any title page as such, "Title 22347 Page" means the text near the most prominent appearance of the 22348 work's title, preceding the beginning of the body of the text. 22349 22350 The "publisher" means any person or entity that distributes copies 22351 of the Document to the public. 22352 22353 A section "Entitled XYZ" means a named subunit of the Document 22354 whose title either is precisely XYZ or contains XYZ in parentheses 22355 following text that translates XYZ in another language. (Here XYZ 22356 stands for a specific section name mentioned below, such as 22357 "Acknowledgements", "Dedications", "Endorsements", or "History".) 22358 To "Preserve the Title" of such a section when you modify the 22359 Document means that it remains a section "Entitled XYZ" according 22360 to this definition. 22361 22362 The Document may include Warranty Disclaimers next to the notice 22363 which states that this License applies to the Document. These 22364 Warranty Disclaimers are considered to be included by reference in 22365 this License, but only as regards disclaiming warranties: any other 22366 implication that these Warranty Disclaimers may have is void and 22367 has no effect on the meaning of this License. 22368 22369 2. VERBATIM COPYING 22370 22371 You may copy and distribute the Document in any medium, either 22372 commercially or noncommercially, provided that this License, the 22373 copyright notices, and the license notice saying this License 22374 applies to the Document are reproduced in all copies, and that you 22375 add no other conditions whatsoever to those of this License. You 22376 may not use technical measures to obstruct or control the reading 22377 or further copying of the copies you make or distribute. However, 22378 you may accept compensation in exchange for copies. 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If you use the 22413 latter option, you must take reasonably prudent steps, when you 22414 begin distribution of Opaque copies in quantity, to ensure that 22415 this Transparent copy will remain thus accessible at the stated 22416 location until at least one year after the last time you 22417 distribute an Opaque copy (directly or through your agents or 22418 retailers) of that edition to the public. 22419 22420 It is requested, but not required, that you contact the authors of 22421 the Document well before redistributing any large number of 22422 copies, to give them a chance to provide you with an updated 22423 version of the Document. 22424 22425 4. MODIFICATIONS 22426 22427 You may copy and distribute a Modified Version of the Document 22428 under the conditions of sections 2 and 3 above, provided that you 22429 release the Modified Version under precisely this License, with 22430 the Modified Version filling the role of the Document, thus 22431 licensing distribution and modification of the Modified Version to 22432 whoever possesses a copy of it. In addition, you must do these 22433 things in the Modified Version: 22434 22435 A. Use in the Title Page (and on the covers, if any) a title 22436 distinct from that of the Document, and from those of 22437 previous versions (which should, if there were any, be listed 22438 in the History section of the Document). You may use the 22439 same title as a previous version if the original publisher of 22440 that version gives permission. 22441 22442 B. List on the Title Page, as authors, one or more persons or 22443 entities responsible for authorship of the modifications in 22444 the Modified Version, together with at least five of the 22445 principal authors of the Document (all of its principal 22446 authors, if it has fewer than five), unless they release you 22447 from this requirement. 22448 22449 C. State on the Title page the name of the publisher of the 22450 Modified Version, as the publisher. 22451 22452 D. Preserve all the copyright notices of the Document. 22453 22454 E. Add an appropriate copyright notice for your modifications 22455 adjacent to the other copyright notices. 22456 22457 F. Include, immediately after the copyright notices, a license 22458 notice giving the public permission to use the Modified 22459 Version under the terms of this License, in the form shown in 22460 the Addendum below. 22461 22462 G. Preserve in that license notice the full lists of Invariant 22463 Sections and required Cover Texts given in the Document's 22464 license notice. 22465 22466 H. Include an unaltered copy of this License. 22467 22468 I. Preserve the section Entitled "History", Preserve its Title, 22469 and add to it an item stating at least the title, year, new 22470 authors, and publisher of the Modified Version as given on 22471 the Title Page. If there is no section Entitled "History" in 22472 the Document, create one stating the title, year, authors, 22473 and publisher of the Document as given on its Title Page, 22474 then add an item describing the Modified Version as stated in 22475 the previous sentence. 22476 22477 J. Preserve the network location, if any, given in the Document 22478 for public access to a Transparent copy of the Document, and 22479 likewise the network locations given in the Document for 22480 previous versions it was based on. These may be placed in 22481 the "History" section. You may omit a network location for a 22482 work that was published at least four years before the 22483 Document itself, or if the original publisher of the version 22484 it refers to gives permission. 22485 22486 K. For any section Entitled "Acknowledgements" or "Dedications", 22487 Preserve the Title of the section, and preserve in the 22488 section all the substance and tone of each of the contributor 22489 acknowledgements and/or dedications given therein. 22490 22491 L. Preserve all the Invariant Sections of the Document, 22492 unaltered in their text and in their titles. Section numbers 22493 or the equivalent are not considered part of the section 22494 titles. 22495 22496 M. Delete any section Entitled "Endorsements". Such a section 22497 may not be included in the Modified Version. 22498 22499 N. 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These titles must be distinct from any 22511 other section titles. 22512 22513 You may add a section Entitled "Endorsements", provided it contains 22514 nothing but endorsements of your Modified Version by various 22515 parties--for example, statements of peer review or that the text 22516 has been approved by an organization as the authoritative 22517 definition of a standard. 22518 22519 You may add a passage of up to five words as a Front-Cover Text, 22520 and a passage of up to 25 words as a Back-Cover Text, to the end 22521 of the list of Cover Texts in the Modified Version. Only one 22522 passage of Front-Cover Text and one of Back-Cover Text may be 22523 added by (or through arrangements made by) any one entity. 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COMBINING DOCUMENTS 22535 22536 You may combine the Document with other documents released under 22537 this License, under the terms defined in section 4 above for 22538 modified versions, provided that you include in the combination 22539 all of the Invariant Sections of all of the original documents, 22540 unmodified, and list them all as Invariant Sections of your 22541 combined work in its license notice, and that you preserve all 22542 their Warranty Disclaimers. 22543 22544 The combined work need only contain one copy of this License, and 22545 multiple identical Invariant Sections may be replaced with a single 22546 copy. If there are multiple Invariant Sections with the same name 22547 but different contents, make the title of each such section unique 22548 by adding at the end of it, in parentheses, the name of the 22549 original author or publisher of that section if known, or else a 22550 unique number. Make the same adjustment to the section titles in 22551 the list of Invariant Sections in the license notice of the 22552 combined work. 22553 22554 In the combination, you must combine any sections Entitled 22555 "History" in the various original documents, forming one section 22556 Entitled "History"; likewise combine any sections Entitled 22557 "Acknowledgements", and any sections Entitled "Dedications". You 22558 must delete all sections Entitled "Endorsements." 22559 22560 6. COLLECTIONS OF DOCUMENTS 22561 22562 You may make a collection consisting of the Document and other 22563 documents released under this License, and replace the individual 22564 copies of this License in the various documents with a single copy 22565 that is included in the collection, provided that you follow the 22566 rules of this License for verbatim copying of each of the 22567 documents in all other respects. 22568 22569 You may extract a single document from such a collection, and 22570 distribute it individually under this License, provided you insert 22571 a copy of this License into the extracted document, and follow 22572 this License in all other respects regarding verbatim copying of 22573 that document. 22574 22575 7. AGGREGATION WITH INDEPENDENT WORKS 22576 22577 A compilation of the Document or its derivatives with other 22578 separate and independent documents or works, in or on a volume of 22579 a storage or distribution medium, is called an "aggregate" if the 22580 copyright resulting from the compilation is not used to limit the 22581 legal rights of the compilation's users beyond what the individual 22582 works permit. When the Document is included in an aggregate, this 22583 License does not apply to the other works in the aggregate which 22584 are not themselves derivative works of the Document. 22585 22586 If the Cover Text requirement of section 3 is applicable to these 22587 copies of the Document, then if the Document is less than one half 22588 of the entire aggregate, the Document's Cover Texts may be placed 22589 on covers that bracket the Document within the aggregate, or the 22590 electronic equivalent of covers if the Document is in electronic 22591 form. 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Any attempt 22619 otherwise to copy, modify, sublicense, or distribute it is void, 22620 and will automatically terminate your rights under this License. 22621 22622 However, if you cease all violation of this License, then your 22623 license from a particular copyright holder is reinstated (a) 22624 provisionally, unless and until the copyright holder explicitly 22625 and finally terminates your license, and (b) permanently, if the 22626 copyright holder fails to notify you of the violation by some 22627 reasonable means prior to 60 days after the cessation. 22628 22629 Moreover, your license from a particular copyright holder is 22630 reinstated permanently if the copyright holder notifies you of the 22631 violation by some reasonable means, this is the first time you have 22632 received notice of violation of this License (for any work) from 22633 that copyright holder, and you cure the violation prior to 30 days 22634 after your receipt of the notice. 22635 22636 Termination of your rights under this section does not terminate 22637 the licenses of parties who have received copies or rights from 22638 you under this License. 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A copy of the license is included in the section entitled ``GNU 22707 Free Documentation License''. 22708 22709 If you have Invariant Sections, Front-Cover Texts and Back-Cover 22710Texts, replace the "with...Texts." line with this: 22711 22712 with the Invariant Sections being LIST THEIR TITLES, with 22713 the Front-Cover Texts being LIST, and with the Back-Cover Texts 22714 being LIST. 22715 22716 If you have Invariant Sections without Cover Texts, or some other 22717combination of the three, merge those two alternatives to suit the 22718situation. 22719 22720 If your document contains nontrivial examples of program code, we 22721recommend releasing these examples in parallel under your choice of 22722free software license, such as the GNU General Public License, to 22723permit their use in free software. 22724 22725 22726File: as.info, Node: AS Index, Prev: GNU Free Documentation License, Up: Top 22727 22728AS Index 22729******** 22730 22731[index] 22732* Menu: 22733 22734* #: Comments. (line 33) 22735* #APP: Preprocessing. (line 26) 22736* #NO_APP: Preprocessing. (line 26) 22737* $ in symbol names <1>: SH64-Chars. (line 15) 22738* $ in symbol names <2>: SH-Chars. (line 15) 22739* $ in symbol names <3>: Meta-Chars. (line 10) 22740* $ in symbol names <4>: D30V-Chars. (line 70) 22741* $ in symbol names: D10V-Chars. (line 53) 22742* $a: ARM Mapping Symbols. (line 9) 22743* $acos math builtin, TIC54X: TIC54X-Builtins. (line 10) 22744* $asin math builtin, TIC54X: TIC54X-Builtins. (line 13) 22745* $atan math builtin, TIC54X: TIC54X-Builtins. (line 16) 22746* $atan2 math builtin, TIC54X: TIC54X-Builtins. (line 19) 22747* $ceil math builtin, TIC54X: TIC54X-Builtins. (line 22) 22748* $cos math builtin, TIC54X: TIC54X-Builtins. (line 28) 22749* $cosh math builtin, TIC54X: TIC54X-Builtins. (line 25) 22750* $cvf math builtin, TIC54X: TIC54X-Builtins. (line 31) 22751* $cvi math builtin, TIC54X: TIC54X-Builtins. (line 34) 22752* $d <1>: ARM Mapping Symbols. (line 15) 22753* $d: AArch64 Mapping Symbols. 22754 (line 12) 22755* $exp math builtin, TIC54X: TIC54X-Builtins. (line 37) 22756* $fabs math builtin, TIC54X: TIC54X-Builtins. (line 40) 22757* $firstch subsym builtin, TIC54X: TIC54X-Macros. (line 26) 22758* $floor math builtin, TIC54X: TIC54X-Builtins. (line 43) 22759* $fmod math builtin, TIC54X: TIC54X-Builtins. (line 47) 22760* $int math builtin, TIC54X: TIC54X-Builtins. (line 50) 22761* $iscons subsym builtin, TIC54X: TIC54X-Macros. (line 43) 22762* $isdefed subsym builtin, TIC54X: TIC54X-Macros. (line 34) 22763* $ismember subsym builtin, TIC54X: TIC54X-Macros. (line 38) 22764* $isname subsym builtin, TIC54X: TIC54X-Macros. (line 47) 22765* $isreg subsym builtin, TIC54X: TIC54X-Macros. (line 50) 22766* $lastch subsym builtin, TIC54X: TIC54X-Macros. (line 30) 22767* $ldexp math builtin, TIC54X: TIC54X-Builtins. (line 53) 22768* $log math builtin, TIC54X: TIC54X-Builtins. (line 59) 22769* $log10 math builtin, TIC54X: TIC54X-Builtins. (line 56) 22770* $max math builtin, TIC54X: TIC54X-Builtins. (line 62) 22771* $min math builtin, TIC54X: TIC54X-Builtins. (line 65) 22772* $pow math builtin, TIC54X: TIC54X-Builtins. (line 68) 22773* $round math builtin, TIC54X: TIC54X-Builtins. (line 71) 22774* $sgn math builtin, TIC54X: TIC54X-Builtins. (line 74) 22775* $sin math builtin, TIC54X: TIC54X-Builtins. (line 77) 22776* $sinh math builtin, TIC54X: TIC54X-Builtins. (line 80) 22777* $sqrt math builtin, TIC54X: TIC54X-Builtins. (line 83) 22778* $structacc subsym builtin, TIC54X: TIC54X-Macros. (line 57) 22779* $structsz subsym builtin, TIC54X: TIC54X-Macros. (line 54) 22780* $symcmp subsym builtin, TIC54X: TIC54X-Macros. (line 23) 22781* $symlen subsym builtin, TIC54X: TIC54X-Macros. (line 20) 22782* $t: ARM Mapping Symbols. (line 12) 22783* $tan math builtin, TIC54X: TIC54X-Builtins. (line 86) 22784* $tanh math builtin, TIC54X: TIC54X-Builtins. (line 89) 22785* $trunc math builtin, TIC54X: TIC54X-Builtins. (line 92) 22786* $x: AArch64 Mapping Symbols. 22787 (line 9) 22788* %gp: RX-Modifiers. (line 6) 22789* %gpreg: RX-Modifiers. (line 22) 22790* %pidreg: RX-Modifiers. (line 25) 22791* -+ option, VAX/VMS: VAX-Opts. (line 71) 22792* --: Command Line. (line 10) 22793* --32 option, i386: i386-Options. (line 8) 22794* --32 option, x86-64: i386-Options. (line 8) 22795* --64 option, i386: i386-Options. (line 8) 22796* --64 option, x86-64: i386-Options. (line 8) 22797* --absolute-literals: Xtensa Options. (line 21) 22798* --allow-reg-prefix: SH Options. (line 9) 22799* --alternate: alternate. (line 6) 22800* --base-size-default-16: M68K-Opts. (line 65) 22801* --base-size-default-32: M68K-Opts. (line 65) 22802* --big: SH Options. (line 9) 22803* --bitwise-or option, M680x0: M68K-Opts. (line 58) 22804* --disp-size-default-16: M68K-Opts. (line 74) 22805* --disp-size-default-32: M68K-Opts. (line 74) 22806* --divide option, i386: i386-Options. (line 24) 22807* --dsp: SH Options. (line 9) 22808* --emulation=crisaout command line option, CRIS: CRIS-Opts. (line 9) 22809* --emulation=criself command line option, CRIS: CRIS-Opts. (line 9) 22810* --enforce-aligned-data: Sparc-Aligned-Data. (line 11) 22811* --fatal-warnings: W. (line 16) 22812* --fdpic: SH Options. (line 31) 22813* --fix-v4bx command line option, ARM: ARM Options. (line 173) 22814* --fixed-special-register-names command line option, MMIX: MMIX-Opts. 22815 (line 8) 22816* --force-long-branches: M68HC11-Opts. (line 82) 22817* --generate-example: M68HC11-Opts. (line 99) 22818* --globalize-symbols command line option, MMIX: MMIX-Opts. (line 12) 22819* --gnu-syntax command line option, MMIX: MMIX-Opts. (line 16) 22820* --hash-size=NUMBER: Overview. (line 401) 22821* --linker-allocated-gregs command line option, MMIX: MMIX-Opts. 22822 (line 67) 22823* --listing-cont-lines: listing. (line 34) 22824* --listing-lhs-width: listing. (line 16) 22825* --listing-lhs-width2: listing. (line 21) 22826* --listing-rhs-width: listing. (line 28) 22827* --little: SH Options. (line 9) 22828* --longcalls: Xtensa Options. (line 35) 22829* --march=ARCHITECTURE command line option, CRIS: CRIS-Opts. (line 34) 22830* --MD: MD. (line 6) 22831* --mul-bug-abort command line option, CRIS: CRIS-Opts. (line 62) 22832* --no-absolute-literals: Xtensa Options. (line 21) 22833* --no-expand command line option, MMIX: MMIX-Opts. (line 31) 22834* --no-longcalls: Xtensa Options. (line 35) 22835* --no-merge-gregs command line option, MMIX: MMIX-Opts. (line 36) 22836* --no-mul-bug-abort command line option, CRIS: CRIS-Opts. (line 62) 22837* --no-predefined-syms command line option, MMIX: MMIX-Opts. (line 22) 22838* --no-pushj-stubs command line option, MMIX: MMIX-Opts. (line 54) 22839* --no-stubs command line option, MMIX: MMIX-Opts. (line 54) 22840* --no-target-align: Xtensa Options. (line 28) 22841* --no-text-section-literals: Xtensa Options. (line 7) 22842* --no-transform: Xtensa Options. (line 44) 22843* --no-underscore command line option, CRIS: CRIS-Opts. (line 15) 22844* --no-warn: W. (line 11) 22845* --pcrel: M68K-Opts. (line 86) 22846* --pic command line option, CRIS: CRIS-Opts. (line 27) 22847* --print-insn-syntax <1>: XGATE-Opts. (line 25) 22848* --print-insn-syntax: M68HC11-Opts. (line 88) 22849* --print-opcodes <1>: XGATE-Opts. (line 29) 22850* --print-opcodes: M68HC11-Opts. (line 92) 22851* --register-prefix-optional option, M680x0: M68K-Opts. (line 45) 22852* --relax: SH Options. (line 9) 22853* --relax command line option, MMIX: MMIX-Opts. (line 19) 22854* --rename-section: Xtensa Options. (line 52) 22855* --renesas: SH Options. (line 9) 22856* --short-branches: M68HC11-Opts. (line 67) 22857* --small: SH Options. (line 9) 22858* --statistics: statistics. (line 6) 22859* --strict-direct-mode: M68HC11-Opts. (line 57) 22860* --target-align: Xtensa Options. (line 28) 22861* --text-section-literals: Xtensa Options. (line 7) 22862* --traditional-format: traditional-format. (line 6) 22863* --transform: Xtensa Options. (line 44) 22864* --underscore command line option, CRIS: CRIS-Opts. (line 15) 22865* --warn: W. (line 19) 22866* --x32 option, i386: i386-Options. (line 8) 22867* --x32 option, x86-64: i386-Options. (line 8) 22868* --xgate-ramoffset: M68HC11-Opts. (line 36) 22869* -1 option, VAX/VMS: VAX-Opts. (line 77) 22870* -32addr command line option, Alpha: Alpha Options. (line 57) 22871* -a: a. (line 6) 22872* -A options, i960: Options-i960. (line 6) 22873* -ac: a. (line 6) 22874* -ad: a. (line 6) 22875* -ag: a. (line 6) 22876* -ah: a. (line 6) 22877* -al: a. (line 6) 22878* -Aleon: Sparc-Opts. (line 25) 22879* -an: a. (line 6) 22880* -as: a. (line 6) 22881* -Asparc: Sparc-Opts. (line 25) 22882* -Asparcfmaf: Sparc-Opts. (line 25) 22883* -Asparcima: Sparc-Opts. (line 25) 22884* -Asparclet: Sparc-Opts. (line 25) 22885* -Asparclite: Sparc-Opts. (line 25) 22886* -Asparcvis: Sparc-Opts. (line 25) 22887* -Asparcvis2: Sparc-Opts. (line 25) 22888* -Asparcvis3: Sparc-Opts. (line 25) 22889* -Asparcvis3r: Sparc-Opts. (line 25) 22890* -Av6: Sparc-Opts. (line 25) 22891* -Av7: Sparc-Opts. (line 25) 22892* -Av8: Sparc-Opts. (line 25) 22893* -Av9: Sparc-Opts. (line 25) 22894* -Av9a: Sparc-Opts. (line 25) 22895* -Av9b: Sparc-Opts. (line 25) 22896* -Av9c: Sparc-Opts. (line 25) 22897* -Av9d: Sparc-Opts. (line 25) 22898* -Av9v: Sparc-Opts. (line 25) 22899* -b option, i960: Options-i960. (line 22) 22900* -big option, M32R: M32R-Opts. (line 35) 22901* -D: D. (line 6) 22902* -D, ignored on VAX: VAX-Opts. (line 11) 22903* -d, VAX option: VAX-Opts. (line 16) 22904* -eabi= command line option, ARM: ARM Options. (line 156) 22905* -EB command line option, AArch64: AArch64 Options. (line 6) 22906* -EB command line option, ARC: ARC Options. (line 31) 22907* -EB command line option, ARM: ARM Options. (line 161) 22908* -EB option (MIPS): MIPS Options. (line 13) 22909* -EB option, M32R: M32R-Opts. (line 39) 22910* -EB option, TILE-Gx: TILE-Gx Options. (line 11) 22911* -EL command line option, AArch64: AArch64 Options. (line 10) 22912* -EL command line option, ARC: ARC Options. (line 35) 22913* -EL command line option, ARM: ARM Options. (line 165) 22914* -EL option (MIPS): MIPS Options. (line 13) 22915* -EL option, M32R: M32R-Opts. (line 32) 22916* -EL option, TILE-Gx: TILE-Gx Options. (line 11) 22917* -f: f. (line 6) 22918* -F command line option, Alpha: Alpha Options. (line 57) 22919* -G command line option, Alpha: Alpha Options. (line 53) 22920* -g command line option, Alpha: Alpha Options. (line 47) 22921* -G option (MIPS): MIPS Options. (line 8) 22922* -H option, VAX/VMS: VAX-Opts. (line 81) 22923* -h option, VAX/VMS: VAX-Opts. (line 45) 22924* -I PATH: I. (line 6) 22925* -ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 87) 22926* -Ip option, M32RX: M32R-Opts. (line 97) 22927* -J, ignored on VAX: VAX-Opts. (line 27) 22928* -K: K. (line 6) 22929* -k command line option, ARM: ARM Options. (line 169) 22930* -KPIC option, M32R: M32R-Opts. (line 42) 22931* -KPIC option, MIPS: MIPS Options. (line 21) 22932* -L: L. (line 6) 22933* -l option, M680x0: M68K-Opts. (line 33) 22934* -little option, M32R: M32R-Opts. (line 27) 22935* -M: M. (line 6) 22936* -m11/03: PDP-11-Options. (line 140) 22937* -m11/04: PDP-11-Options. (line 143) 22938* -m11/05: PDP-11-Options. (line 146) 22939* -m11/10: PDP-11-Options. (line 146) 22940* -m11/15: PDP-11-Options. (line 149) 22941* -m11/20: PDP-11-Options. (line 149) 22942* -m11/21: PDP-11-Options. (line 152) 22943* -m11/23: PDP-11-Options. (line 155) 22944* -m11/24: PDP-11-Options. (line 155) 22945* -m11/34: PDP-11-Options. (line 158) 22946* -m11/34a: PDP-11-Options. (line 161) 22947* -m11/35: PDP-11-Options. (line 164) 22948* -m11/40: PDP-11-Options. (line 164) 22949* -m11/44: PDP-11-Options. (line 167) 22950* -m11/45: PDP-11-Options. (line 170) 22951* -m11/50: PDP-11-Options. (line 170) 22952* -m11/53: PDP-11-Options. (line 173) 22953* -m11/55: PDP-11-Options. (line 170) 22954* -m11/60: PDP-11-Options. (line 176) 22955* -m11/70: PDP-11-Options. (line 170) 22956* -m11/73: PDP-11-Options. (line 173) 22957* -m11/83: PDP-11-Options. (line 173) 22958* -m11/84: PDP-11-Options. (line 173) 22959* -m11/93: PDP-11-Options. (line 173) 22960* -m11/94: PDP-11-Options. (line 173) 22961* -m16c option, M16C: M32C-Opts. (line 12) 22962* -m31 option, s390: s390 Options. (line 8) 22963* -m32 option, TILE-Gx: TILE-Gx Options. (line 8) 22964* -m32bit-doubles: RX-Opts. (line 9) 22965* -m32c option, M32C: M32C-Opts. (line 9) 22966* -m32r option, M32R: M32R-Opts. (line 21) 22967* -m32rx option, M32R2: M32R-Opts. (line 17) 22968* -m32rx option, M32RX: M32R-Opts. (line 9) 22969* -m4byte-align command line option, V850: V850 Options. (line 90) 22970* -m64 option, s390: s390 Options. (line 8) 22971* -m64 option, TILE-Gx: TILE-Gx Options. (line 8) 22972* -m64bit-doubles: RX-Opts. (line 15) 22973* -m68000 and related options: M68K-Opts. (line 98) 22974* -m68hc11: M68HC11-Opts. (line 9) 22975* -m68hc12: M68HC11-Opts. (line 14) 22976* -m68hcs12: M68HC11-Opts. (line 21) 22977* -m8byte-align command line option, V850: V850 Options. (line 86) 22978* -m[no-]68851 command line option, M680x0: M68K-Opts. (line 21) 22979* -m[no-]68881 command line option, M680x0: M68K-Opts. (line 21) 22980* -m[no-]div command line option, M680x0: M68K-Opts. (line 21) 22981* -m[no-]emac command line option, M680x0: M68K-Opts. (line 21) 22982* -m[no-]float command line option, M680x0: M68K-Opts. (line 21) 22983* -m[no-]mac command line option, M680x0: M68K-Opts. (line 21) 22984* -m[no-]usp command line option, M680x0: M68K-Opts. (line 21) 22985* -mabi= command line option, AArch64: AArch64 Options. (line 14) 22986* -madd-bnd-prefix option, i386: i386-Options. (line 124) 22987* -madd-bnd-prefix option, x86-64: i386-Options. (line 124) 22988* -mall: PDP-11-Options. (line 26) 22989* -mall-enabled command line option, LM32: LM32 Options. (line 30) 22990* -mall-extensions: PDP-11-Options. (line 26) 22991* -mall-opcodes command line option, AVR: AVR Options. (line 97) 22992* -mapcs-26 command line option, ARM: ARM Options. (line 128) 22993* -mapcs-32 command line option, ARM: ARM Options. (line 128) 22994* -mapcs-float command line option, ARM: ARM Options. (line 142) 22995* -mapcs-reentrant command line option, ARM: ARM Options. (line 147) 22996* -marc[5|6|7|8] command line option, ARC: ARC Options. (line 6) 22997* -march= command line option, ARM: ARM Options. (line 65) 22998* -march= command line option, M680x0: M68K-Opts. (line 8) 22999* -march= command line option, TIC6X: TIC6X Options. (line 6) 23000* -march= option, i386: i386-Options. (line 31) 23001* -march= option, s390: s390 Options. (line 25) 23002* -march= option, x86-64: i386-Options. (line 31) 23003* -matpcs command line option, ARM: ARM Options. (line 134) 23004* -mavxscalar= option, i386: i386-Options. (line 82) 23005* -mavxscalar= option, x86-64: i386-Options. (line 82) 23006* -mbarrel-shift-enabled command line option, LM32: LM32 Options. 23007 (line 12) 23008* -mbig-endian: RX-Opts. (line 20) 23009* -mbreak-enabled command line option, LM32: LM32 Options. (line 27) 23010* -mcis: PDP-11-Options. (line 32) 23011* -mconstant-gp command line option, IA-64: IA-64 Options. (line 6) 23012* -mCPU command line option, Alpha: Alpha Options. (line 6) 23013* -mcpu option, cpu: TIC54X-Opts. (line 15) 23014* -mcpu=: RX-Opts. (line 75) 23015* -mcpu= command line option, ARM: ARM Options. (line 6) 23016* -mcpu= command line option, Blackfin: Blackfin Options. (line 6) 23017* -mcpu= command line option, M680x0: M68K-Opts. (line 14) 23018* -mcsm: PDP-11-Options. (line 43) 23019* -mdcache-enabled command line option, LM32: LM32 Options. (line 24) 23020* -mdebug command line option, Alpha: Alpha Options. (line 25) 23021* -mdivide-enabled command line option, LM32: LM32 Options. (line 9) 23022* -mdsbt command line option, TIC6X: TIC6X Options. (line 13) 23023* -me option, stderr redirect: TIC54X-Opts. (line 20) 23024* -meis: PDP-11-Options. (line 46) 23025* -mepiphany command line option, Epiphany: Epiphany Options. (line 9) 23026* -mepiphany16 command line option, Epiphany: Epiphany Options. 23027 (line 13) 23028* -merrors-to-file option, stderr redirect: TIC54X-Opts. (line 20) 23029* -mesa option, s390: s390 Options. (line 17) 23030* -mevexlig= option, i386: i386-Options. (line 90) 23031* -mevexlig= option, x86-64: i386-Options. (line 90) 23032* -mevexwig= option, i386: i386-Options. (line 100) 23033* -mevexwig= option, x86-64: i386-Options. (line 100) 23034* -mf option, far-mode: TIC54X-Opts. (line 8) 23035* -mf11: PDP-11-Options. (line 122) 23036* -mfar-mode option, far-mode: TIC54X-Opts. (line 8) 23037* -mfdpic command line option, Blackfin: Blackfin Options. (line 19) 23038* -mfis: PDP-11-Options. (line 51) 23039* -mfloat-abi= command line option, ARM: ARM Options. (line 151) 23040* -mfp-11: PDP-11-Options. (line 56) 23041* -mfpp: PDP-11-Options. (line 56) 23042* -mfpu: PDP-11-Options. (line 56) 23043* -mfpu= command line option, ARM: ARM Options. (line 81) 23044* -mgcc-abi: RX-Opts. (line 63) 23045* -mgcc-abi command line option, V850: V850 Options. (line 79) 23046* -micache-enabled command line option, LM32: LM32 Options. (line 21) 23047* -mimplicit-it command line option, ARM: ARM Options. (line 112) 23048* -mint-register: RX-Opts. (line 57) 23049* -mip2022 option, IP2K: IP2K-Opts. (line 14) 23050* -mip2022ext option, IP2022: IP2K-Opts. (line 9) 23051* -mj11: PDP-11-Options. (line 126) 23052* -mka11: PDP-11-Options. (line 92) 23053* -mkb11: PDP-11-Options. (line 95) 23054* -mkd11a: PDP-11-Options. (line 98) 23055* -mkd11b: PDP-11-Options. (line 101) 23056* -mkd11d: PDP-11-Options. (line 104) 23057* -mkd11e: PDP-11-Options. (line 107) 23058* -mkd11f: PDP-11-Options. (line 110) 23059* -mkd11h: PDP-11-Options. (line 110) 23060* -mkd11k: PDP-11-Options. (line 114) 23061* -mkd11q: PDP-11-Options. (line 110) 23062* -mkd11z: PDP-11-Options. (line 118) 23063* -mkev11: PDP-11-Options. (line 51) 23064* -mlimited-eis: PDP-11-Options. (line 64) 23065* -mlittle-endian: RX-Opts. (line 26) 23066* -mlong <1>: XGATE-Opts. (line 13) 23067* -mlong: M68HC11-Opts. (line 45) 23068* -mlong-double <1>: XGATE-Opts. (line 21) 23069* -mlong-double: M68HC11-Opts. (line 53) 23070* -mm9s12x: M68HC11-Opts. (line 27) 23071* -mm9s12xg: M68HC11-Opts. (line 32) 23072* -mmcu= command line option, AVR: AVR Options. (line 6) 23073* -mmfpt: PDP-11-Options. (line 70) 23074* -mmicrocode: PDP-11-Options. (line 83) 23075* -mmnemonic= option, i386: i386-Options. (line 107) 23076* -mmnemonic= option, x86-64: i386-Options. (line 107) 23077* -mmultiply-enabled command line option, LM32: LM32 Options. (line 6) 23078* -mmutiproc: PDP-11-Options. (line 73) 23079* -mmxps: PDP-11-Options. (line 77) 23080* -mnaked-reg option, i386: i386-Options. (line 119) 23081* -mnaked-reg option, x86-64: i386-Options. (line 119) 23082* -mnan= command line option, MIPS: MIPS Options. (line 302) 23083* -mno-cis: PDP-11-Options. (line 32) 23084* -mno-csm: PDP-11-Options. (line 43) 23085* -mno-dsbt command line option, TIC6X: TIC6X Options. (line 13) 23086* -mno-eis: PDP-11-Options. (line 46) 23087* -mno-extensions: PDP-11-Options. (line 29) 23088* -mno-fdpic command line option, Blackfin: Blackfin Options. (line 22) 23089* -mno-fis: PDP-11-Options. (line 51) 23090* -mno-fp-11: PDP-11-Options. (line 56) 23091* -mno-fpp: PDP-11-Options. (line 56) 23092* -mno-fpu: PDP-11-Options. (line 56) 23093* -mno-kev11: PDP-11-Options. (line 51) 23094* -mno-limited-eis: PDP-11-Options. (line 64) 23095* -mno-mfpt: PDP-11-Options. (line 70) 23096* -mno-microcode: PDP-11-Options. (line 83) 23097* -mno-mutiproc: PDP-11-Options. (line 73) 23098* -mno-mxps: PDP-11-Options. (line 77) 23099* -mno-pic: PDP-11-Options. (line 11) 23100* -mno-pic command line option, TIC6X: TIC6X Options. (line 36) 23101* -mno-regnames option, s390: s390 Options. (line 35) 23102* -mno-skip-bug command line option, AVR: AVR Options. (line 100) 23103* -mno-spl: PDP-11-Options. (line 80) 23104* -mno-sym32: MIPS Options. (line 243) 23105* -mno-wrap command line option, AVR: AVR Options. (line 103) 23106* -mnopic command line option, Blackfin: Blackfin Options. (line 22) 23107* -mpic: PDP-11-Options. (line 11) 23108* -mpic command line option, TIC6X: TIC6X Options. (line 36) 23109* -mpid: RX-Opts. (line 50) 23110* -mpid= command line option, TIC6X: TIC6X Options. (line 23) 23111* -mregnames option, s390: s390 Options. (line 32) 23112* -mrelax command line option, V850: V850 Options. (line 72) 23113* -mrh850-abi command line option, V850: V850 Options. (line 82) 23114* -mrx-abi: RX-Opts. (line 69) 23115* -mshort <1>: XGATE-Opts. (line 8) 23116* -mshort: M68HC11-Opts. (line 40) 23117* -mshort-double <1>: XGATE-Opts. (line 17) 23118* -mshort-double: M68HC11-Opts. (line 49) 23119* -msign-extend-enabled command line option, LM32: LM32 Options. 23120 (line 15) 23121* -msmall-data-limit: RX-Opts. (line 42) 23122* -mspl: PDP-11-Options. (line 80) 23123* -msse-check= option, i386: i386-Options. (line 72) 23124* -msse-check= option, x86-64: i386-Options. (line 72) 23125* -msse2avx option, i386: i386-Options. (line 68) 23126* -msse2avx option, x86-64: i386-Options. (line 68) 23127* -msym32: MIPS Options. (line 243) 23128* -msyntax= option, i386: i386-Options. (line 113) 23129* -msyntax= option, x86-64: i386-Options. (line 113) 23130* -mt11: PDP-11-Options. (line 130) 23131* -mthumb command line option, ARM: ARM Options. (line 103) 23132* -mthumb-interwork command line option, ARM: ARM Options. (line 108) 23133* -mtune= option, i386: i386-Options. (line 60) 23134* -mtune= option, x86-64: i386-Options. (line 60) 23135* -muse-conventional-section-names: RX-Opts. (line 33) 23136* -muse-renesas-section-names: RX-Opts. (line 37) 23137* -muser-enabled command line option, LM32: LM32 Options. (line 18) 23138* -mv850 command line option, V850: V850 Options. (line 23) 23139* -mv850any command line option, V850: V850 Options. (line 41) 23140* -mv850e command line option, V850: V850 Options. (line 29) 23141* -mv850e1 command line option, V850: V850 Options. (line 35) 23142* -mv850e2 command line option, V850: V850 Options. (line 51) 23143* -mv850e2v3 command line option, V850: V850 Options. (line 57) 23144* -mv850e2v4 command line option, V850: V850 Options. (line 63) 23145* -mv850e3v5 command line option, V850: V850 Options. (line 66) 23146* -mvxworks-pic option, MIPS: MIPS Options. (line 26) 23147* -mwarn-areg-zero option, s390: s390 Options. (line 38) 23148* -mwarn-deprecated command line option, ARM: ARM Options. (line 177) 23149* -mzarch option, s390: s390 Options. (line 17) 23150* -N command line option, CRIS: CRIS-Opts. (line 58) 23151* -nIp option, M32RX: M32R-Opts. (line 101) 23152* -no-bitinst, M32R2: M32R-Opts. (line 54) 23153* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 93) 23154* -no-mdebug command line option, Alpha: Alpha Options. (line 25) 23155* -no-parallel option, M32RX: M32R-Opts. (line 51) 23156* -no-relax option, i960: Options-i960. (line 66) 23157* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. 23158 (line 79) 23159* -no-warn-unmatched-high option, M32R: M32R-Opts. (line 111) 23160* -nocpp ignored (MIPS): MIPS Options. (line 246) 23161* -noreplace command line option, Alpha: Alpha Options. (line 40) 23162* -o: o. (line 6) 23163* -O option, M32RX: M32R-Opts. (line 59) 23164* -parallel option, M32RX: M32R-Opts. (line 46) 23165* -R: R. (line 6) 23166* -r800 command line option, Z80: Z80 Options. (line 41) 23167* -relax command line option, Alpha: Alpha Options. (line 32) 23168* -replace command line option, Alpha: Alpha Options. (line 40) 23169* -S, ignored on VAX: VAX-Opts. (line 11) 23170* -t, ignored on VAX: VAX-Opts. (line 36) 23171* -T, ignored on VAX: VAX-Opts. (line 11) 23172* -v: v. (line 6) 23173* -V, redundant on VAX: VAX-Opts. (line 22) 23174* -version: v. (line 6) 23175* -W: W. (line 11) 23176* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. (line 65) 23177* -warn-unmatched-high option, M32R: M32R-Opts. (line 105) 23178* -Wnp option, M32RX: M32R-Opts. (line 83) 23179* -Wnuh option, M32RX: M32R-Opts. (line 117) 23180* -Wp option, M32RX: M32R-Opts. (line 75) 23181* -wsigned_overflow command line option, V850: V850 Options. (line 9) 23182* -Wuh option, M32RX: M32R-Opts. (line 114) 23183* -wunsigned_overflow command line option, V850: V850 Options. 23184 (line 16) 23185* -x command line option, MMIX: MMIX-Opts. (line 44) 23186* -z80 command line option, Z80: Z80 Options. (line 8) 23187* -z8001 command line option, Z8000: Z8000 Options. (line 6) 23188* -z8002 command line option, Z8000: Z8000 Options. (line 9) 23189* . (symbol): Dot. (line 6) 23190* .2byte directive, ARM: ARM Directives. (line 6) 23191* .4byte directive, ARM: ARM Directives. (line 6) 23192* .8byte directive, ARM: ARM Directives. (line 6) 23193* .align directive, ARM: ARM Directives. (line 11) 23194* .align directive, TILE-Gx: TILE-Gx Directives. (line 6) 23195* .align directive, TILEPro: TILEPro Directives. (line 6) 23196* .allow_suspicious_bundles directive, TILE-Gx: TILE-Gx Directives. 23197 (line 10) 23198* .allow_suspicious_bundles directive, TILEPro: TILEPro Directives. 23199 (line 10) 23200* .arch directive, ARM: ARM Directives. (line 18) 23201* .arch directive, TIC6X: TIC6X Directives. (line 10) 23202* .arch_extension directive, ARM: ARM Directives. (line 25) 23203* .arm directive, ARM: ARM Directives. (line 34) 23204* .big directive, M32RX: M32R-Directives. (line 88) 23205* .bss directive, AArch64: AArch64 Directives. (line 6) 23206* .bss directive, ARM: ARM Directives. (line 42) 23207* .c6xabi_attribute directive, TIC6X: TIC6X Directives. (line 20) 23208* .cantunwind directive, ARM: ARM Directives. (line 45) 23209* .cantunwind directive, TIC6X: TIC6X Directives. (line 13) 23210* .code directive, ARM: ARM Directives. (line 49) 23211* .cpu directive, ARM: ARM Directives. (line 53) 23212* .dn and .qn directives, ARM: ARM Directives. (line 60) 23213* .eabi_attribute directive, ARM: ARM Directives. (line 83) 23214* .ehtype directive, TIC6X: TIC6X Directives. (line 31) 23215* .endp directive, TIC6X: TIC6X Directives. (line 34) 23216* .even directive, ARM: ARM Directives. (line 111) 23217* .extend directive, ARM: ARM Directives. (line 114) 23218* .fnend directive, ARM: ARM Directives. (line 120) 23219* .fnstart directive, ARM: ARM Directives. (line 129) 23220* .force_thumb directive, ARM: ARM Directives. (line 132) 23221* .fpu directive, ARM: ARM Directives. (line 136) 23222* .global: MIPS insn. (line 12) 23223* .handlerdata directive, ARM: ARM Directives. (line 140) 23224* .handlerdata directive, TIC6X: TIC6X Directives. (line 39) 23225* .insn: MIPS insn. (line 6) 23226* .insn directive, s390: s390 Directives. (line 11) 23227* .inst directive, ARM: ARM Directives. (line 149) 23228* .ldouble directive, ARM: ARM Directives. (line 114) 23229* .little directive, M32RX: M32R-Directives. (line 82) 23230* .long directive, s390: s390 Directives. (line 16) 23231* .ltorg directive, AArch64: AArch64 Directives. (line 9) 23232* .ltorg directive, ARM: ARM Directives. (line 159) 23233* .ltorg directive, s390: s390 Directives. (line 88) 23234* .m32r directive, M32R: M32R-Directives. (line 66) 23235* .m32r2 directive, M32R2: M32R-Directives. (line 77) 23236* .m32rx directive, M32RX: M32R-Directives. (line 72) 23237* .machine directive, s390: s390 Directives. (line 93) 23238* .machinemode directive, s390: s390 Directives. (line 103) 23239* .movsp directive, ARM: ARM Directives. (line 173) 23240* .nan directive, MIPS: MIPS NaN Encodings. (line 6) 23241* .no_pointers directive, XStormy16: XStormy16 Directives. 23242 (line 14) 23243* .nocmp directive, TIC6X: TIC6X Directives. (line 47) 23244* .o: Object. (line 6) 23245* .object_arch directive, ARM: ARM Directives. (line 178) 23246* .packed directive, ARM: ARM Directives. (line 184) 23247* .pad directive, ARM: ARM Directives. (line 37) 23248* .param on HPPA: HPPA Directives. (line 19) 23249* .personality directive, ARM: ARM Directives. (line 194) 23250* .personality directive, TIC6X: TIC6X Directives. (line 55) 23251* .personalityindex directive, ARM: ARM Directives. (line 197) 23252* .personalityindex directive, TIC6X: TIC6X Directives. (line 51) 23253* .pool directive, AArch64: AArch64 Directives. (line 23) 23254* .pool directive, ARM: ARM Directives. (line 201) 23255* .quad directive, s390: s390 Directives. (line 16) 23256* .req directive, AArch64: AArch64 Directives. (line 26) 23257* .req directive, ARM: ARM Directives. (line 204) 23258* .require_canonical_reg_names directive, TILE-Gx: TILE-Gx Directives. 23259 (line 19) 23260* .require_canonical_reg_names directive, TILEPro: TILEPro Directives. 23261 (line 19) 23262* .save directive, ARM: ARM Directives. (line 209) 23263* .scomm directive, TIC6X: TIC6X Directives. (line 58) 23264* .secrel32 directive, ARM: ARM Directives. (line 247) 23265* .set arch=CPU: MIPS ISA. (line 18) 23266* .set at: MIPS Macros. (line 42) 23267* .set at=REG: MIPS Macros. (line 36) 23268* .set autoextend: MIPS autoextend. (line 6) 23269* .set doublefloat: MIPS Floating-Point. (line 12) 23270* .set dsp: MIPS ASE Instruction Generation Overrides. 23271 (line 21) 23272* .set dspr2: MIPS ASE Instruction Generation Overrides. 23273 (line 26) 23274* .set hardfloat: MIPS Floating-Point. (line 6) 23275* .set insn32: MIPS assembly options. 23276 (line 6) 23277* .set macro: MIPS Macros. (line 31) 23278* .set mcu: MIPS ASE Instruction Generation Overrides. 23279 (line 37) 23280* .set mdmx: MIPS ASE Instruction Generation Overrides. 23281 (line 16) 23282* .set mips3d: MIPS ASE Instruction Generation Overrides. 23283 (line 6) 23284* .set mipsN: MIPS ISA. (line 6) 23285* .set mt: MIPS ASE Instruction Generation Overrides. 23286 (line 32) 23287* .set noat: MIPS Macros. (line 42) 23288* .set noautoextend: MIPS autoextend. (line 6) 23289* .set nodsp: MIPS ASE Instruction Generation Overrides. 23290 (line 21) 23291* .set nodspr2: MIPS ASE Instruction Generation Overrides. 23292 (line 26) 23293* .set noinsn32: MIPS assembly options. 23294 (line 6) 23295* .set nomacro: MIPS Macros. (line 31) 23296* .set nomcu: MIPS ASE Instruction Generation Overrides. 23297 (line 37) 23298* .set nomdmx: MIPS ASE Instruction Generation Overrides. 23299 (line 16) 23300* .set nomips3d: MIPS ASE Instruction Generation Overrides. 23301 (line 6) 23302* .set nomt: MIPS ASE Instruction Generation Overrides. 23303 (line 32) 23304* .set nosmartmips: MIPS ASE Instruction Generation Overrides. 23305 (line 11) 23306* .set nosym32: MIPS Symbol Sizes. (line 6) 23307* .set novirt: MIPS ASE Instruction Generation Overrides. 23308 (line 42) 23309* .set pop: MIPS Option Stack. (line 6) 23310* .set push: MIPS Option Stack. (line 6) 23311* .set singlefloat: MIPS Floating-Point. (line 12) 23312* .set smartmips: MIPS ASE Instruction Generation Overrides. 23313 (line 11) 23314* .set softfloat: MIPS Floating-Point. (line 6) 23315* .set sym32: MIPS Symbol Sizes. (line 6) 23316* .set virt: MIPS ASE Instruction Generation Overrides. 23317 (line 42) 23318* .setfp directive, ARM: ARM Directives. (line 233) 23319* .short directive, s390: s390 Directives. (line 16) 23320* .syntax directive, ARM: ARM Directives. (line 252) 23321* .thumb directive, ARM: ARM Directives. (line 256) 23322* .thumb_func directive, ARM: ARM Directives. (line 259) 23323* .thumb_set directive, ARM: ARM Directives. (line 270) 23324* .tlsdescseq directive, ARM: ARM Directives. (line 277) 23325* .unreq directive, AArch64: AArch64 Directives. (line 31) 23326* .unreq directive, ARM: ARM Directives. (line 282) 23327* .unwind_raw directive, ARM: ARM Directives. (line 293) 23328* .v850 directive, V850: V850 Directives. (line 14) 23329* .v850e directive, V850: V850 Directives. (line 20) 23330* .v850e1 directive, V850: V850 Directives. (line 26) 23331* .v850e2 directive, V850: V850 Directives. (line 32) 23332* .v850e2v3 directive, V850: V850 Directives. (line 38) 23333* .v850e2v4 directive, V850: V850 Directives. (line 44) 23334* .v850e3v5 directive, V850: V850 Directives. (line 50) 23335* .vsave directive, ARM: ARM Directives. (line 300) 23336* .z8001: Z8000 Directives. (line 11) 23337* .z8002: Z8000 Directives. (line 15) 23338* 16-bit code, i386: i386-16bit. (line 6) 23339* 16bit_pointers directive, XStormy16: XStormy16 Directives. 23340 (line 6) 23341* 16byte directive, Nios II: Nios II Directives. (line 28) 23342* 2byte directive, ARC: ARC Directives. (line 9) 23343* 2byte directive, Nios II: Nios II Directives. (line 19) 23344* 32bit_pointers directive, XStormy16: XStormy16 Directives. 23345 (line 10) 23346* 3byte directive, ARC: ARC Directives. (line 12) 23347* 3DNow!, i386: i386-SIMD. (line 6) 23348* 3DNow!, x86-64: i386-SIMD. (line 6) 23349* 430 support: MSP430-Dependent. (line 6) 23350* 4byte directive, ARC: ARC Directives. (line 15) 23351* 4byte directive, Nios II: Nios II Directives. (line 22) 23352* 8byte directive, Nios II: Nios II Directives. (line 25) 23353* : (label): Statements. (line 31) 23354* @hi pseudo-op, XStormy16: XStormy16 Opcodes. (line 21) 23355* @lo pseudo-op, XStormy16: XStormy16 Opcodes. (line 10) 23356* @word modifier, D10V: D10V-Word. (line 6) 23357* \" (doublequote character): Strings. (line 43) 23358* \\ (\ character): Strings. (line 40) 23359* \b (backspace character): Strings. (line 15) 23360* \DDD (octal character code): Strings. (line 30) 23361* \f (formfeed character): Strings. (line 18) 23362* \n (newline character): Strings. (line 21) 23363* \r (carriage return character): Strings. (line 24) 23364* \t (tab): Strings. (line 27) 23365* \XD... (hex character code): Strings. (line 36) 23366* _ opcode prefix: Xtensa Opcodes. (line 9) 23367* a.out: Object. (line 6) 23368* a.out symbol attributes: a.out Symbols. (line 6) 23369* A_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 23370* AArch64 floating point (IEEE): AArch64 Floating Point. 23371 (line 6) 23372* AArch64 immediate character: AArch64-Chars. (line 13) 23373* AArch64 line comment character: AArch64-Chars. (line 6) 23374* AArch64 line separator: AArch64-Chars. (line 10) 23375* AArch64 machine directives: AArch64 Directives. (line 6) 23376* AArch64 opcodes: AArch64 Opcodes. (line 6) 23377* AArch64 options (none): AArch64 Options. (line 6) 23378* AArch64 register names: AArch64-Regs. (line 6) 23379* AArch64 relocations: AArch64-Relocations. (line 6) 23380* AArch64 support: AArch64-Dependent. (line 6) 23381* ABI options, SH64: SH64 Options. (line 29) 23382* ABORT directive: ABORT (COFF). (line 6) 23383* abort directive: Abort. (line 6) 23384* absolute section: Ld Sections. (line 29) 23385* absolute-literals directive: Absolute Literals Directive. 23386 (line 6) 23387* ADDI instructions, relaxation: Xtensa Immediate Relaxation. 23388 (line 43) 23389* addition, permitted arguments: Infix Ops. (line 44) 23390* addresses: Expressions. (line 6) 23391* addresses, format of: Secs Background. (line 68) 23392* addressing modes, D10V: D10V-Addressing. (line 6) 23393* addressing modes, D30V: D30V-Addressing. (line 6) 23394* addressing modes, H8/300: H8/300-Addressing. (line 6) 23395* addressing modes, M680x0: M68K-Syntax. (line 21) 23396* addressing modes, M68HC11: M68HC11-Syntax. (line 30) 23397* addressing modes, SH: SH-Addressing. (line 6) 23398* addressing modes, SH64: SH64-Addressing. (line 6) 23399* addressing modes, XGATE: XGATE-Syntax. (line 29) 23400* addressing modes, Z8000: Z8000-Addressing. (line 6) 23401* ADR reg,<label> pseudo op, ARM: ARM Opcodes. (line 25) 23402* ADRL reg,<label> pseudo op, ARM: ARM Opcodes. (line 35) 23403* ADRP, ADD, LDR/STR group relocations, AArch64: AArch64-Relocations. 23404 (line 14) 23405* advancing location counter: Org. (line 6) 23406* align directive: Align. (line 6) 23407* align directive, Nios II: Nios II Directives. (line 6) 23408* align directive, SPARC: Sparc-Directives. (line 9) 23409* align directive, TIC54X: TIC54X-Directives. (line 6) 23410* aligned instruction bundle: Bundle directives. (line 6) 23411* alignment for NEON instructions: ARM-Neon-Alignment. (line 6) 23412* alignment of branch targets: Xtensa Automatic Alignment. 23413 (line 6) 23414* alignment of LOOP instructions: Xtensa Automatic Alignment. 23415 (line 6) 23416* Alpha floating point (IEEE): Alpha Floating Point. 23417 (line 6) 23418* Alpha line comment character: Alpha-Chars. (line 6) 23419* Alpha line separator: Alpha-Chars. (line 11) 23420* Alpha notes: Alpha Notes. (line 6) 23421* Alpha options: Alpha Options. (line 6) 23422* Alpha registers: Alpha-Regs. (line 6) 23423* Alpha relocations: Alpha-Relocs. (line 6) 23424* Alpha support: Alpha-Dependent. (line 6) 23425* Alpha Syntax: Alpha Options. (line 61) 23426* Alpha-only directives: Alpha Directives. (line 10) 23427* Altera Nios II support: NiosII-Dependent. (line 6) 23428* altered difference tables: Word. (line 12) 23429* alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6) 23430* ARC floating point (IEEE): ARC Floating Point. (line 6) 23431* ARC line comment character: ARC-Chars. (line 6) 23432* ARC line separator: ARC-Chars. (line 12) 23433* ARC machine directives: ARC Directives. (line 6) 23434* ARC opcodes: ARC Opcodes. (line 6) 23435* ARC options (none): ARC Options. (line 6) 23436* ARC register names: ARC-Regs. (line 6) 23437* ARC support: ARC-Dependent. (line 6) 23438* arc5 arc5, ARC: ARC Options. (line 10) 23439* arc6 arc6, ARC: ARC Options. (line 13) 23440* arc7 arc7, ARC: ARC Options. (line 21) 23441* arc8 arc8, ARC: ARC Options. (line 24) 23442* arch directive, i386: i386-Arch. (line 6) 23443* arch directive, M680x0: M68K-Directives. (line 22) 23444* arch directive, MSP 430: MSP430 Directives. (line 18) 23445* arch directive, x86-64: i386-Arch. (line 6) 23446* architecture options, i960: Options-i960. (line 6) 23447* architecture options, IP2022: IP2K-Opts. (line 9) 23448* architecture options, IP2K: IP2K-Opts. (line 14) 23449* architecture options, M16C: M32C-Opts. (line 12) 23450* architecture options, M32C: M32C-Opts. (line 9) 23451* architecture options, M32R: M32R-Opts. (line 21) 23452* architecture options, M32R2: M32R-Opts. (line 17) 23453* architecture options, M32RX: M32R-Opts. (line 9) 23454* architecture options, M680x0: M68K-Opts. (line 98) 23455* Architecture variant option, CRIS: CRIS-Opts. (line 34) 23456* architectures, Meta: Meta Options. (line 6) 23457* architectures, PowerPC: PowerPC-Opts. (line 6) 23458* architectures, SCORE: SCORE-Opts. (line 6) 23459* architectures, SPARC: Sparc-Opts. (line 6) 23460* arguments for addition: Infix Ops. (line 44) 23461* arguments for subtraction: Infix Ops. (line 49) 23462* arguments in expressions: Arguments. (line 6) 23463* arithmetic functions: Operators. (line 6) 23464* arithmetic operands: Arguments. (line 6) 23465* ARM data relocations: ARM-Relocations. (line 6) 23466* ARM floating point (IEEE): ARM Floating Point. (line 6) 23467* ARM identifiers: ARM-Chars. (line 19) 23468* ARM immediate character: ARM-Chars. (line 17) 23469* ARM line comment character: ARM-Chars. (line 6) 23470* ARM line separator: ARM-Chars. (line 14) 23471* ARM machine directives: ARM Directives. (line 6) 23472* ARM opcodes: ARM Opcodes. (line 6) 23473* ARM options (none): ARM Options. (line 6) 23474* ARM register names: ARM-Regs. (line 6) 23475* ARM support: ARM-Dependent. (line 6) 23476* ascii directive: Ascii. (line 6) 23477* asciz directive: Asciz. (line 6) 23478* asg directive, TIC54X: TIC54X-Directives. (line 20) 23479* assembler bugs, reporting: Bug Reporting. (line 6) 23480* assembler crash: Bug Criteria. (line 9) 23481* assembler directive .3byte, RX: RX-Directives. (line 9) 23482* assembler directive .arch, CRIS: CRIS-Pseudos. (line 45) 23483* assembler directive .dword, CRIS: CRIS-Pseudos. (line 12) 23484* assembler directive .far, M68HC11: M68HC11-Directives. (line 20) 23485* assembler directive .fetchalign, RX: RX-Directives. (line 13) 23486* assembler directive .interrupt, M68HC11: M68HC11-Directives. 23487 (line 26) 23488* assembler directive .mode, M68HC11: M68HC11-Directives. (line 16) 23489* assembler directive .relax, M68HC11: M68HC11-Directives. (line 10) 23490* assembler directive .syntax, CRIS: CRIS-Pseudos. (line 17) 23491* assembler directive .xrefb, M68HC11: M68HC11-Directives. (line 31) 23492* assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 131) 23493* assembler directive BYTE, MMIX: MMIX-Pseudos. (line 97) 23494* assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 131) 23495* assembler directive GREG, MMIX: MMIX-Pseudos. (line 50) 23496* assembler directive IS, MMIX: MMIX-Pseudos. (line 42) 23497* assembler directive LOC, MMIX: MMIX-Pseudos. (line 7) 23498* assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 28) 23499* assembler directive OCTA, MMIX: MMIX-Pseudos. (line 108) 23500* assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 120) 23501* assembler directive TETRA, MMIX: MMIX-Pseudos. (line 108) 23502* assembler directive WYDE, MMIX: MMIX-Pseudos. (line 108) 23503* assembler directives, CRIS: CRIS-Pseudos. (line 6) 23504* assembler directives, M68HC11: M68HC11-Directives. (line 6) 23505* assembler directives, M68HC12: M68HC11-Directives. (line 6) 23506* assembler directives, MMIX: MMIX-Pseudos. (line 6) 23507* assembler directives, RL78: RL78-Directives. (line 6) 23508* assembler directives, RX: RX-Directives. (line 6) 23509* assembler directives, XGATE: XGATE-Directives. (line 6) 23510* assembler internal logic error: As Sections. (line 13) 23511* assembler version: v. (line 6) 23512* assembler, and linker: Secs Background. (line 10) 23513* assembly listings, enabling: a. (line 6) 23514* assigning values to symbols <1>: Equ. (line 6) 23515* assigning values to symbols: Setting Symbols. (line 6) 23516* at register, MIPS: MIPS Macros. (line 36) 23517* atmp directive, i860: Directives-i860. (line 16) 23518* att_syntax pseudo op, i386: i386-Variations. (line 6) 23519* att_syntax pseudo op, x86-64: i386-Variations. (line 6) 23520* attributes, symbol: Symbol Attributes. (line 6) 23521* auxiliary attributes, COFF symbols: COFF Symbols. (line 19) 23522* auxiliary symbol information, COFF: Dim. (line 6) 23523* AVR line comment character: AVR-Chars. (line 6) 23524* AVR line separator: AVR-Chars. (line 14) 23525* AVR modifiers: AVR-Modifiers. (line 6) 23526* AVR opcode summary: AVR Opcodes. (line 6) 23527* AVR options (none): AVR Options. (line 6) 23528* AVR register names: AVR-Regs. (line 6) 23529* AVR support: AVR-Dependent. (line 6) 23530* backslash (\\): Strings. (line 40) 23531* backspace (\b): Strings. (line 15) 23532* balign directive: Balign. (line 6) 23533* balignl directive: Balign. (line 27) 23534* balignw directive: Balign. (line 27) 23535* bes directive, TIC54X: TIC54X-Directives. (line 196) 23536* big endian output, MIPS: Overview. (line 741) 23537* big endian output, PJ: Overview. (line 644) 23538* big-endian output, MIPS: MIPS Options. (line 13) 23539* big-endian output, TIC6X: TIC6X Options. (line 46) 23540* bignums: Bignums. (line 6) 23541* binary constants, TIC54X: TIC54X-Constants. (line 8) 23542* binary files, including: Incbin. (line 6) 23543* binary integers: Integers. (line 6) 23544* bit names, IA-64: IA-64-Bits. (line 6) 23545* bitfields, not supported on VAX: VAX-no. (line 6) 23546* Blackfin directives: Blackfin Directives. (line 6) 23547* Blackfin options (none): Blackfin Options. (line 6) 23548* Blackfin support: Blackfin-Dependent. (line 6) 23549* Blackfin syntax: Blackfin Syntax. (line 6) 23550* block: Z8000 Directives. (line 55) 23551* BMI, i386: i386-BMI. (line 6) 23552* BMI, x86-64: i386-BMI. (line 6) 23553* branch improvement, M680x0: M68K-Branch. (line 6) 23554* branch improvement, M68HC11: M68HC11-Branch. (line 6) 23555* branch improvement, VAX: VAX-branch. (line 6) 23556* branch instructions, relaxation: Xtensa Branch Relaxation. 23557 (line 6) 23558* branch recording, i960: Options-i960. (line 22) 23559* branch statistics table, i960: Options-i960. (line 40) 23560* branch target alignment: Xtensa Automatic Alignment. 23561 (line 6) 23562* break directive, TIC54X: TIC54X-Directives. (line 143) 23563* BSD syntax: PDP-11-Syntax. (line 6) 23564* bss directive, i960: Directives-i960. (line 6) 23565* bss directive, TIC54X: TIC54X-Directives. (line 29) 23566* bss section <1>: bss. (line 6) 23567* bss section: Ld Sections. (line 20) 23568* bug criteria: Bug Criteria. (line 6) 23569* bug reports: Bug Reporting. (line 6) 23570* bugs in assembler: Reporting Bugs. (line 6) 23571* Built-in symbols, CRIS: CRIS-Symbols. (line 6) 23572* builtin math functions, TIC54X: TIC54X-Builtins. (line 6) 23573* builtin subsym functions, TIC54X: TIC54X-Macros. (line 16) 23574* bundle: Bundle directives. (line 6) 23575* bundle-locked: Bundle directives. (line 35) 23576* bundle_align_mode directive: Bundle directives. (line 6) 23577* bundle_lock directive: Bundle directives. (line 28) 23578* bundle_unlock directive: Bundle directives. (line 28) 23579* bus lock prefixes, i386: i386-Prefixes. (line 36) 23580* bval: Z8000 Directives. (line 30) 23581* byte directive: Byte. (line 6) 23582* byte directive, TIC54X: TIC54X-Directives. (line 36) 23583* C54XDSP_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 23584* c_mode directive, TIC54X: TIC54X-Directives. (line 51) 23585* call directive, Nios II: Nios II Relocations. (line 38) 23586* call instructions, i386: i386-Mnemonics. (line 56) 23587* call instructions, relaxation: Xtensa Call Relaxation. 23588 (line 6) 23589* call instructions, x86-64: i386-Mnemonics. (line 56) 23590* callj, i960 pseudo-opcode: callj-i960. (line 6) 23591* carriage return (\r): Strings. (line 24) 23592* case sensitivity, Z80: Z80-Case. (line 6) 23593* cfi_endproc directive: CFI directives. (line 29) 23594* cfi_sections directive: CFI directives. (line 6) 23595* cfi_startproc directive: CFI directives. (line 19) 23596* char directive, TIC54X: TIC54X-Directives. (line 36) 23597* character constant, Z80: Z80-Chars. (line 20) 23598* character constants: Characters. (line 6) 23599* character escape codes: Strings. (line 15) 23600* character escapes, Z80: Z80-Chars. (line 18) 23601* character, single: Chars. (line 6) 23602* characters used in symbols: Symbol Intro. (line 6) 23603* clink directive, TIC54X: TIC54X-Directives. (line 45) 23604* code16 directive, i386: i386-16bit. (line 6) 23605* code16gcc directive, i386: i386-16bit. (line 6) 23606* code32 directive, i386: i386-16bit. (line 6) 23607* code64 directive, i386: i386-16bit. (line 6) 23608* code64 directive, x86-64: i386-16bit. (line 6) 23609* COFF auxiliary symbol information: Dim. (line 6) 23610* COFF structure debugging: Tag. (line 6) 23611* COFF symbol attributes: COFF Symbols. (line 6) 23612* COFF symbol descriptor: Desc. (line 6) 23613* COFF symbol storage class: Scl. (line 6) 23614* COFF symbol type: Type. (line 11) 23615* COFF symbols, debugging: Def. (line 6) 23616* COFF value attribute: Val. (line 6) 23617* COMDAT: Linkonce. (line 6) 23618* comm directive: Comm. (line 6) 23619* command line conventions: Command Line. (line 6) 23620* command line options, V850: V850 Options. (line 9) 23621* command-line options ignored, VAX: VAX-Opts. (line 6) 23622* comment character, XStormy16: XStormy16-Chars. (line 11) 23623* comments: Comments. (line 6) 23624* comments, M680x0: M68K-Chars. (line 6) 23625* comments, removed by preprocessor: Preprocessing. (line 11) 23626* common directive, SPARC: Sparc-Directives. (line 12) 23627* common sections: Linkonce. (line 6) 23628* common variable storage: bss. (line 6) 23629* compare and jump expansions, i960: Compare-and-branch-i960. 23630 (line 13) 23631* compare/branch instructions, i960: Compare-and-branch-i960. 23632 (line 6) 23633* comparison expressions: Infix Ops. (line 55) 23634* conditional assembly: If. (line 6) 23635* constant, single character: Chars. (line 6) 23636* constants: Constants. (line 6) 23637* constants, bignum: Bignums. (line 6) 23638* constants, character: Characters. (line 6) 23639* constants, converted by preprocessor: Preprocessing. (line 14) 23640* constants, floating point: Flonums. (line 6) 23641* constants, integer: Integers. (line 6) 23642* constants, number: Numbers. (line 6) 23643* constants, Sparc: Sparc-Constants. (line 6) 23644* constants, string: Strings. (line 6) 23645* constants, TIC54X: TIC54X-Constants. (line 6) 23646* conversion instructions, i386: i386-Mnemonics. (line 37) 23647* conversion instructions, x86-64: i386-Mnemonics. (line 37) 23648* coprocessor wait, i386: i386-Prefixes. (line 40) 23649* copy directive, TIC54X: TIC54X-Directives. (line 54) 23650* cpu directive, M680x0: M68K-Directives. (line 30) 23651* cpu directive, MSP 430: MSP430 Directives. (line 22) 23652* CR16 line comment character: CR16-Chars. (line 6) 23653* CR16 line separator: CR16-Chars. (line 13) 23654* CR16 Operand Qualifiers: CR16 Operand Qualifiers. 23655 (line 6) 23656* CR16 support: CR16-Dependent. (line 6) 23657* crash of assembler: Bug Criteria. (line 9) 23658* CRIS --emulation=crisaout command line option: CRIS-Opts. (line 9) 23659* CRIS --emulation=criself command line option: CRIS-Opts. (line 9) 23660* CRIS --march=ARCHITECTURE command line option: CRIS-Opts. (line 34) 23661* CRIS --mul-bug-abort command line option: CRIS-Opts. (line 62) 23662* CRIS --no-mul-bug-abort command line option: CRIS-Opts. (line 62) 23663* CRIS --no-underscore command line option: CRIS-Opts. (line 15) 23664* CRIS --pic command line option: CRIS-Opts. (line 27) 23665* CRIS --underscore command line option: CRIS-Opts. (line 15) 23666* CRIS -N command line option: CRIS-Opts. (line 58) 23667* CRIS architecture variant option: CRIS-Opts. (line 34) 23668* CRIS assembler directive .arch: CRIS-Pseudos. (line 45) 23669* CRIS assembler directive .dword: CRIS-Pseudos. (line 12) 23670* CRIS assembler directive .syntax: CRIS-Pseudos. (line 17) 23671* CRIS assembler directives: CRIS-Pseudos. (line 6) 23672* CRIS built-in symbols: CRIS-Symbols. (line 6) 23673* CRIS instruction expansion: CRIS-Expand. (line 6) 23674* CRIS line comment characters: CRIS-Chars. (line 6) 23675* CRIS options: CRIS-Opts. (line 6) 23676* CRIS position-independent code: CRIS-Opts. (line 27) 23677* CRIS pseudo-op .arch: CRIS-Pseudos. (line 45) 23678* CRIS pseudo-op .dword: CRIS-Pseudos. (line 12) 23679* CRIS pseudo-op .syntax: CRIS-Pseudos. (line 17) 23680* CRIS pseudo-ops: CRIS-Pseudos. (line 6) 23681* CRIS register names: CRIS-Regs. (line 6) 23682* CRIS support: CRIS-Dependent. (line 6) 23683* CRIS symbols in position-independent code: CRIS-Pic. (line 6) 23684* ctbp register, V850: V850-Regs. (line 131) 23685* ctoff pseudo-op, V850: V850 Opcodes. (line 111) 23686* ctpc register, V850: V850-Regs. (line 119) 23687* ctpsw register, V850: V850-Regs. (line 122) 23688* current address: Dot. (line 6) 23689* current address, advancing: Org. (line 6) 23690* D10V @word modifier: D10V-Word. (line 6) 23691* D10V addressing modes: D10V-Addressing. (line 6) 23692* D10V floating point: D10V-Float. (line 6) 23693* D10V line comment character: D10V-Chars. (line 6) 23694* D10V opcode summary: D10V-Opcodes. (line 6) 23695* D10V optimization: Overview. (line 504) 23696* D10V options: D10V-Opts. (line 6) 23697* D10V registers: D10V-Regs. (line 6) 23698* D10V size modifiers: D10V-Size. (line 6) 23699* D10V sub-instruction ordering: D10V-Chars. (line 14) 23700* D10V sub-instructions: D10V-Subs. (line 6) 23701* D10V support: D10V-Dependent. (line 6) 23702* D10V syntax: D10V-Syntax. (line 6) 23703* D30V addressing modes: D30V-Addressing. (line 6) 23704* D30V floating point: D30V-Float. (line 6) 23705* D30V Guarded Execution: D30V-Guarded. (line 6) 23706* D30V line comment character: D30V-Chars. (line 6) 23707* D30V nops: Overview. (line 512) 23708* D30V nops after 32-bit multiply: Overview. (line 515) 23709* D30V opcode summary: D30V-Opcodes. (line 6) 23710* D30V optimization: Overview. (line 509) 23711* D30V options: D30V-Opts. (line 6) 23712* D30V registers: D30V-Regs. (line 6) 23713* D30V size modifiers: D30V-Size. (line 6) 23714* D30V sub-instruction ordering: D30V-Chars. (line 14) 23715* D30V sub-instructions: D30V-Subs. (line 6) 23716* D30V support: D30V-Dependent. (line 6) 23717* D30V syntax: D30V-Syntax. (line 6) 23718* data alignment on SPARC: Sparc-Aligned-Data. (line 6) 23719* data and text sections, joining: R. (line 6) 23720* data directive: Data. (line 6) 23721* data directive, TIC54X: TIC54X-Directives. (line 61) 23722* data relocations, ARM: ARM-Relocations. (line 6) 23723* data section: Ld Sections. (line 9) 23724* data1 directive, M680x0: M68K-Directives. (line 9) 23725* data2 directive, M680x0: M68K-Directives. (line 12) 23726* datalabel, SH64: SH64-Addressing. (line 16) 23727* dbpc register, V850: V850-Regs. (line 125) 23728* dbpsw register, V850: V850-Regs. (line 128) 23729* debuggers, and symbol order: Symbols. (line 10) 23730* debugging COFF symbols: Def. (line 6) 23731* DEC syntax: PDP-11-Syntax. (line 6) 23732* decimal integers: Integers. (line 12) 23733* def directive: Def. (line 6) 23734* def directive, TIC54X: TIC54X-Directives. (line 103) 23735* density instructions: Density Instructions. 23736 (line 6) 23737* dependency tracking: MD. (line 6) 23738* deprecated directives: Deprecated. (line 6) 23739* desc directive: Desc. (line 6) 23740* descriptor, of a.out symbol: Symbol Desc. (line 6) 23741* dfloat directive, VAX: VAX-directives. (line 10) 23742* difference tables altered: Word. (line 12) 23743* difference tables, warning: K. (line 6) 23744* differences, mmixal: MMIX-mmixal. (line 6) 23745* dim directive: Dim. (line 6) 23746* directives and instructions: Statements. (line 20) 23747* directives for PowerPC: PowerPC-Pseudo. (line 6) 23748* directives for SCORE: SCORE-Pseudo. (line 6) 23749* directives, Blackfin: Blackfin Directives. (line 6) 23750* directives, M32R: M32R-Directives. (line 6) 23751* directives, M680x0: M68K-Directives. (line 6) 23752* directives, machine independent: Pseudo Ops. (line 6) 23753* directives, Xtensa: Xtensa Directives. (line 6) 23754* directives, Z8000: Z8000 Directives. (line 6) 23755* Disable floating-point instructions: MIPS Floating-Point. (line 6) 23756* Disable single-precision floating-point operations: MIPS Floating-Point. 23757 (line 12) 23758* displacement sizing character, VAX: VAX-operands. (line 12) 23759* dollar local symbols: Symbol Names. (line 110) 23760* dot (symbol): Dot. (line 6) 23761* double directive: Double. (line 6) 23762* double directive, i386: i386-Float. (line 14) 23763* double directive, M680x0: M68K-Float. (line 14) 23764* double directive, M68HC11: M68HC11-Float. (line 14) 23765* double directive, RX: RX-Float. (line 11) 23766* double directive, TIC54X: TIC54X-Directives. (line 64) 23767* double directive, VAX: VAX-float. (line 15) 23768* double directive, x86-64: i386-Float. (line 14) 23769* double directive, XGATE: XGATE-Float. (line 13) 23770* doublequote (\"): Strings. (line 43) 23771* drlist directive, TIC54X: TIC54X-Directives. (line 73) 23772* drnolist directive, TIC54X: TIC54X-Directives. (line 73) 23773* dual directive, i860: Directives-i860. (line 6) 23774* dword directive, Nios II: Nios II Directives. (line 16) 23775* EB command line option, Nios II: Nios II Options. (line 23) 23776* ecr register, V850: V850-Regs. (line 113) 23777* eight-byte integer: Quad. (line 9) 23778* eipc register, V850: V850-Regs. (line 101) 23779* eipsw register, V850: V850-Regs. (line 104) 23780* eject directive: Eject. (line 6) 23781* EL command line option, Nios II: Nios II Options. (line 26) 23782* ELF symbol type: Type. (line 22) 23783* else directive: Else. (line 6) 23784* elseif directive: Elseif. (line 6) 23785* empty expressions: Empty Exprs. (line 6) 23786* emsg directive, TIC54X: TIC54X-Directives. (line 77) 23787* emulation: Overview. (line 882) 23788* encoding options, i386: i386-Mnemonics. (line 32) 23789* encoding options, x86-64: i386-Mnemonics. (line 32) 23790* end directive: End. (line 6) 23791* enddual directive, i860: Directives-i860. (line 11) 23792* endef directive: Endef. (line 6) 23793* endfunc directive: Endfunc. (line 6) 23794* endianness, MIPS: Overview. (line 741) 23795* endianness, PJ: Overview. (line 644) 23796* endif directive: Endif. (line 6) 23797* endloop directive, TIC54X: TIC54X-Directives. (line 143) 23798* endm directive: Macro. (line 138) 23799* endm directive, TIC54X: TIC54X-Directives. (line 153) 23800* endstruct directive, TIC54X: TIC54X-Directives. (line 216) 23801* endunion directive, TIC54X: TIC54X-Directives. (line 250) 23802* environment settings, TIC54X: TIC54X-Env. (line 6) 23803* EOF, newline must precede: Statements. (line 14) 23804* ep register, V850: V850-Regs. (line 95) 23805* Epiphany line comment character: Epiphany-Chars. (line 6) 23806* Epiphany line separator: Epiphany-Chars. (line 14) 23807* Epiphany options: Epiphany Options. (line 6) 23808* Epiphany support: Epiphany-Dependent. (line 6) 23809* equ directive: Equ. (line 6) 23810* equ directive, TIC54X: TIC54X-Directives. (line 191) 23811* equiv directive: Equiv. (line 6) 23812* eqv directive: Eqv. (line 6) 23813* err directive: Err. (line 6) 23814* error directive: Error. (line 6) 23815* error messages: Errors. (line 6) 23816* error on valid input: Bug Criteria. (line 12) 23817* errors, caused by warnings: W. (line 16) 23818* errors, continuing after: Z. (line 6) 23819* ESA/390 floating point (IEEE): ESA/390 Floating Point. 23820 (line 6) 23821* ESA/390 support: ESA/390-Dependent. (line 6) 23822* ESA/390 Syntax: ESA/390 Options. (line 8) 23823* ESA/390-only directives: ESA/390 Directives. (line 12) 23824* escape codes, character: Strings. (line 15) 23825* eval directive, TIC54X: TIC54X-Directives. (line 24) 23826* even: Z8000 Directives. (line 58) 23827* even directive, M680x0: M68K-Directives. (line 15) 23828* even directive, TIC54X: TIC54X-Directives. (line 6) 23829* exitm directive: Macro. (line 141) 23830* expr (internal section): As Sections. (line 17) 23831* expression arguments: Arguments. (line 6) 23832* expressions: Expressions. (line 6) 23833* expressions, comparison: Infix Ops. (line 55) 23834* expressions, empty: Empty Exprs. (line 6) 23835* expressions, integer: Integer Exprs. (line 6) 23836* extAuxRegister directive, ARC: ARC Directives. (line 18) 23837* extCondCode directive, ARC: ARC Directives. (line 41) 23838* extCoreRegister directive, ARC: ARC Directives. (line 53) 23839* extend directive M680x0: M68K-Float. (line 17) 23840* extend directive M68HC11: M68HC11-Float. (line 17) 23841* extend directive XGATE: XGATE-Float. (line 16) 23842* extended directive, i960: Directives-i960. (line 13) 23843* extern directive: Extern. (line 6) 23844* extInstruction directive, ARC: ARC Directives. (line 78) 23845* fail directive: Fail. (line 6) 23846* far_mode directive, TIC54X: TIC54X-Directives. (line 82) 23847* faster processing (-f): f. (line 6) 23848* fatal signal: Bug Criteria. (line 9) 23849* fclist directive, TIC54X: TIC54X-Directives. (line 87) 23850* fcnolist directive, TIC54X: TIC54X-Directives. (line 87) 23851* fepc register, V850: V850-Regs. (line 107) 23852* fepsw register, V850: V850-Regs. (line 110) 23853* ffloat directive, VAX: VAX-directives. (line 14) 23854* field directive, TIC54X: TIC54X-Directives. (line 91) 23855* file directive: File. (line 6) 23856* file directive, MSP 430: MSP430 Directives. (line 6) 23857* file name, logical: File. (line 13) 23858* files, including: Include. (line 6) 23859* files, input: Input Files. (line 6) 23860* fill directive: Fill. (line 6) 23861* filling memory <1>: Space. (line 6) 23862* filling memory: Skip. (line 6) 23863* FLIX syntax: Xtensa Syntax. (line 6) 23864* float directive: Float. (line 6) 23865* float directive, i386: i386-Float. (line 14) 23866* float directive, M680x0: M68K-Float. (line 11) 23867* float directive, M68HC11: M68HC11-Float. (line 11) 23868* float directive, RX: RX-Float. (line 8) 23869* float directive, TIC54X: TIC54X-Directives. (line 64) 23870* float directive, VAX: VAX-float. (line 15) 23871* float directive, x86-64: i386-Float. (line 14) 23872* float directive, XGATE: XGATE-Float. (line 10) 23873* floating point numbers: Flonums. (line 6) 23874* floating point numbers (double): Double. (line 6) 23875* floating point numbers (single) <1>: Single. (line 6) 23876* floating point numbers (single): Float. (line 6) 23877* floating point, AArch64 (IEEE): AArch64 Floating Point. 23878 (line 6) 23879* floating point, Alpha (IEEE): Alpha Floating Point. 23880 (line 6) 23881* floating point, ARC (IEEE): ARC Floating Point. (line 6) 23882* floating point, ARM (IEEE): ARM Floating Point. (line 6) 23883* floating point, D10V: D10V-Float. (line 6) 23884* floating point, D30V: D30V-Float. (line 6) 23885* floating point, ESA/390 (IEEE): ESA/390 Floating Point. 23886 (line 6) 23887* floating point, H8/300 (IEEE): H8/300 Floating Point. 23888 (line 6) 23889* floating point, HPPA (IEEE): HPPA Floating Point. (line 6) 23890* floating point, i386: i386-Float. (line 6) 23891* floating point, i960 (IEEE): Floating Point-i960. (line 6) 23892* floating point, M680x0: M68K-Float. (line 6) 23893* floating point, M68HC11: M68HC11-Float. (line 6) 23894* floating point, MSP 430 (IEEE): MSP430 Floating Point. 23895 (line 6) 23896* floating point, RX: RX-Float. (line 6) 23897* floating point, s390: s390 Floating Point. (line 6) 23898* floating point, SH (IEEE): SH Floating Point. (line 6) 23899* floating point, SPARC (IEEE): Sparc-Float. (line 6) 23900* floating point, V850 (IEEE): V850 Floating Point. (line 6) 23901* floating point, VAX: VAX-float. (line 6) 23902* floating point, x86-64: i386-Float. (line 6) 23903* floating point, XGATE: XGATE-Float. (line 6) 23904* floating point, Z80: Z80 Floating Point. (line 6) 23905* flonums: Flonums. (line 6) 23906* format of error messages: Errors. (line 24) 23907* format of warning messages: Errors. (line 12) 23908* formfeed (\f): Strings. (line 18) 23909* func directive: Func. (line 6) 23910* functions, in expressions: Operators. (line 6) 23911* gbr960, i960 postprocessor: Options-i960. (line 40) 23912* gfloat directive, VAX: VAX-directives. (line 18) 23913* global: Z8000 Directives. (line 21) 23914* global directive: Global. (line 6) 23915* global directive, TIC54X: TIC54X-Directives. (line 103) 23916* got directive, Nios II: Nios II Relocations. (line 38) 23917* gotoff directive, Nios II: Nios II Relocations. (line 38) 23918* gotoff_hiadj directive, Nios II: Nios II Relocations. (line 38) 23919* gotoff_lo directive, Nios II: Nios II Relocations. (line 38) 23920* gp register, MIPS: MIPS Small Data. (line 6) 23921* gp register, V850: V850-Regs. (line 17) 23922* gprel directive, Nios II: Nios II Relocations. (line 26) 23923* grouping data: Sub-Sections. (line 6) 23924* H8/300 addressing modes: H8/300-Addressing. (line 6) 23925* H8/300 floating point (IEEE): H8/300 Floating Point. 23926 (line 6) 23927* H8/300 line comment character: H8/300-Chars. (line 6) 23928* H8/300 line separator: H8/300-Chars. (line 8) 23929* H8/300 machine directives (none): H8/300 Directives. (line 6) 23930* H8/300 opcode summary: H8/300 Opcodes. (line 6) 23931* H8/300 options: H8/300 Options. (line 6) 23932* H8/300 registers: H8/300-Regs. (line 6) 23933* H8/300 size suffixes: H8/300 Opcodes. (line 163) 23934* H8/300 support: H8/300-Dependent. (line 6) 23935* H8/300H, assembling for: H8/300 Directives. (line 8) 23936* half directive, ARC: ARC Directives. (line 153) 23937* half directive, Nios II: Nios II Directives. (line 10) 23938* half directive, SPARC: Sparc-Directives. (line 17) 23939* half directive, TIC54X: TIC54X-Directives. (line 111) 23940* hex character code (\XD...): Strings. (line 36) 23941* hexadecimal integers: Integers. (line 15) 23942* hexadecimal prefix, Z80: Z80-Chars. (line 15) 23943* hfloat directive, VAX: VAX-directives. (line 22) 23944* hi directive, Nios II: Nios II Relocations. (line 20) 23945* hi pseudo-op, V850: V850 Opcodes. (line 33) 23946* hi0 pseudo-op, V850: V850 Opcodes. (line 10) 23947* hiadj directive, Nios II: Nios II Relocations. (line 6) 23948* hidden directive: Hidden. (line 6) 23949* high directive, M32R: M32R-Directives. (line 18) 23950* hilo pseudo-op, V850: V850 Opcodes. (line 55) 23951* HPPA directives not supported: HPPA Directives. (line 11) 23952* HPPA floating point (IEEE): HPPA Floating Point. (line 6) 23953* HPPA Syntax: HPPA Options. (line 8) 23954* HPPA-only directives: HPPA Directives. (line 24) 23955* hword directive: hword. (line 6) 23956* i370 support: ESA/390-Dependent. (line 6) 23957* i386 16-bit code: i386-16bit. (line 6) 23958* i386 arch directive: i386-Arch. (line 6) 23959* i386 att_syntax pseudo op: i386-Variations. (line 6) 23960* i386 conversion instructions: i386-Mnemonics. (line 37) 23961* i386 floating point: i386-Float. (line 6) 23962* i386 immediate operands: i386-Variations. (line 15) 23963* i386 instruction naming: i386-Mnemonics. (line 6) 23964* i386 instruction prefixes: i386-Prefixes. (line 6) 23965* i386 intel_syntax pseudo op: i386-Variations. (line 6) 23966* i386 jump optimization: i386-Jumps. (line 6) 23967* i386 jump, call, return: i386-Variations. (line 41) 23968* i386 jump/call operands: i386-Variations. (line 15) 23969* i386 line comment character: i386-Chars. (line 6) 23970* i386 line separator: i386-Chars. (line 18) 23971* i386 memory references: i386-Memory. (line 6) 23972* i386 mnemonic compatibility: i386-Mnemonics. (line 62) 23973* i386 mul, imul instructions: i386-Notes. (line 6) 23974* i386 options: i386-Options. (line 6) 23975* i386 register operands: i386-Variations. (line 15) 23976* i386 registers: i386-Regs. (line 6) 23977* i386 sections: i386-Variations. (line 47) 23978* i386 size suffixes: i386-Variations. (line 29) 23979* i386 source, destination operands: i386-Variations. (line 22) 23980* i386 support: i386-Dependent. (line 6) 23981* i386 syntax compatibility: i386-Variations. (line 6) 23982* i80386 support: i386-Dependent. (line 6) 23983* i860 line comment character: i860-Chars. (line 6) 23984* i860 line separator: i860-Chars. (line 14) 23985* i860 machine directives: Directives-i860. (line 6) 23986* i860 opcodes: Opcodes for i860. (line 6) 23987* i860 support: i860-Dependent. (line 6) 23988* i960 architecture options: Options-i960. (line 6) 23989* i960 branch recording: Options-i960. (line 22) 23990* i960 callj pseudo-opcode: callj-i960. (line 6) 23991* i960 compare and jump expansions: Compare-and-branch-i960. 23992 (line 13) 23993* i960 compare/branch instructions: Compare-and-branch-i960. 23994 (line 6) 23995* i960 floating point (IEEE): Floating Point-i960. (line 6) 23996* i960 line comment character: i960-Chars. (line 6) 23997* i960 line separator: i960-Chars. (line 14) 23998* i960 machine directives: Directives-i960. (line 6) 23999* i960 opcodes: Opcodes for i960. (line 6) 24000* i960 options: Options-i960. (line 6) 24001* i960 support: i960-Dependent. (line 6) 24002* IA-64 line comment character: IA-64-Chars. (line 6) 24003* IA-64 line separator: IA-64-Chars. (line 8) 24004* IA-64 options: IA-64 Options. (line 6) 24005* IA-64 Processor-status-Register bit names: IA-64-Bits. (line 6) 24006* IA-64 registers: IA-64-Regs. (line 6) 24007* IA-64 relocations: IA-64-Relocs. (line 6) 24008* IA-64 support: IA-64-Dependent. (line 6) 24009* IA-64 Syntax: IA-64 Options. (line 87) 24010* ident directive: Ident. (line 6) 24011* identifiers, ARM: ARM-Chars. (line 19) 24012* identifiers, MSP 430: MSP430-Chars. (line 17) 24013* if directive: If. (line 6) 24014* ifb directive: If. (line 21) 24015* ifc directive: If. (line 25) 24016* ifdef directive: If. (line 16) 24017* ifeq directive: If. (line 33) 24018* ifeqs directive: If. (line 36) 24019* ifge directive: If. (line 40) 24020* ifgt directive: If. (line 44) 24021* ifle directive: If. (line 48) 24022* iflt directive: If. (line 52) 24023* ifnb directive: If. (line 56) 24024* ifnc directive: If. (line 61) 24025* ifndef directive: If. (line 65) 24026* ifne directive: If. (line 72) 24027* ifnes directive: If. (line 76) 24028* ifnotdef directive: If. (line 65) 24029* immediate character, AArch64: AArch64-Chars. (line 13) 24030* immediate character, ARM: ARM-Chars. (line 17) 24031* immediate character, M680x0: M68K-Chars. (line 13) 24032* immediate character, VAX: VAX-operands. (line 6) 24033* immediate fields, relaxation: Xtensa Immediate Relaxation. 24034 (line 6) 24035* immediate operands, i386: i386-Variations. (line 15) 24036* immediate operands, x86-64: i386-Variations. (line 15) 24037* imul instruction, i386: i386-Notes. (line 6) 24038* imul instruction, x86-64: i386-Notes. (line 6) 24039* incbin directive: Incbin. (line 6) 24040* include directive: Include. (line 6) 24041* include directive search path: I. (line 6) 24042* indirect character, VAX: VAX-operands. (line 9) 24043* infix operators: Infix Ops. (line 6) 24044* inhibiting interrupts, i386: i386-Prefixes. (line 36) 24045* input: Input Files. (line 6) 24046* input file linenumbers: Input Files. (line 35) 24047* instruction aliases, s390: s390 Aliases. (line 6) 24048* instruction bundle: Bundle directives. (line 6) 24049* instruction expansion, CRIS: CRIS-Expand. (line 6) 24050* instruction expansion, MMIX: MMIX-Expand. (line 6) 24051* instruction formats, s390: s390 Formats. (line 6) 24052* instruction marker, s390: s390 Instruction Marker. 24053 (line 6) 24054* instruction mnemonics, s390: s390 Mnemonics. (line 6) 24055* instruction naming, i386: i386-Mnemonics. (line 6) 24056* instruction naming, x86-64: i386-Mnemonics. (line 6) 24057* instruction operand modifier, s390: s390 Operand Modifier. 24058 (line 6) 24059* instruction operands, s390: s390 Operands. (line 6) 24060* instruction prefixes, i386: i386-Prefixes. (line 6) 24061* instruction set, M680x0: M68K-opcodes. (line 6) 24062* instruction set, M68HC11: M68HC11-opcodes. (line 6) 24063* instruction set, XGATE: XGATE-opcodes. (line 6) 24064* instruction summary, AVR: AVR Opcodes. (line 6) 24065* instruction summary, D10V: D10V-Opcodes. (line 6) 24066* instruction summary, D30V: D30V-Opcodes. (line 6) 24067* instruction summary, H8/300: H8/300 Opcodes. (line 6) 24068* instruction summary, LM32: LM32 Opcodes. (line 6) 24069* instruction summary, SH: SH Opcodes. (line 6) 24070* instruction summary, SH64: SH64 Opcodes. (line 6) 24071* instruction summary, Z8000: Z8000 Opcodes. (line 6) 24072* instruction syntax, s390: s390 Syntax. (line 6) 24073* instructions and directives: Statements. (line 20) 24074* int directive: Int. (line 6) 24075* int directive, H8/300: H8/300 Directives. (line 6) 24076* int directive, i386: i386-Float. (line 21) 24077* int directive, TIC54X: TIC54X-Directives. (line 111) 24078* int directive, x86-64: i386-Float. (line 21) 24079* integer expressions: Integer Exprs. (line 6) 24080* integer, 16-byte: Octa. (line 6) 24081* integer, 8-byte: Quad. (line 9) 24082* integers: Integers. (line 6) 24083* integers, 16-bit: hword. (line 6) 24084* integers, 32-bit: Int. (line 6) 24085* integers, binary: Integers. (line 6) 24086* integers, decimal: Integers. (line 12) 24087* integers, hexadecimal: Integers. (line 15) 24088* integers, octal: Integers. (line 9) 24089* integers, one byte: Byte. (line 6) 24090* intel_syntax pseudo op, i386: i386-Variations. (line 6) 24091* intel_syntax pseudo op, x86-64: i386-Variations. (line 6) 24092* internal assembler sections: As Sections. (line 6) 24093* internal directive: Internal. (line 6) 24094* invalid input: Bug Criteria. (line 14) 24095* invocation summary: Overview. (line 6) 24096* IP2K architecture options: IP2K-Opts. (line 9) 24097* IP2K line comment character: IP2K-Chars. (line 6) 24098* IP2K line separator: IP2K-Chars. (line 14) 24099* IP2K options: IP2K-Opts. (line 6) 24100* IP2K support: IP2K-Dependent. (line 6) 24101* irp directive: Irp. (line 6) 24102* irpc directive: Irpc. (line 6) 24103* ISA options, SH64: SH64 Options. (line 6) 24104* joining text and data sections: R. (line 6) 24105* jump instructions, i386: i386-Mnemonics. (line 56) 24106* jump instructions, x86-64: i386-Mnemonics. (line 56) 24107* jump optimization, i386: i386-Jumps. (line 6) 24108* jump optimization, x86-64: i386-Jumps. (line 6) 24109* jump/call operands, i386: i386-Variations. (line 15) 24110* jump/call operands, x86-64: i386-Variations. (line 15) 24111* L16SI instructions, relaxation: Xtensa Immediate Relaxation. 24112 (line 23) 24113* L16UI instructions, relaxation: Xtensa Immediate Relaxation. 24114 (line 23) 24115* L32I instructions, relaxation: Xtensa Immediate Relaxation. 24116 (line 23) 24117* L8UI instructions, relaxation: Xtensa Immediate Relaxation. 24118 (line 23) 24119* label (:): Statements. (line 31) 24120* label directive, TIC54X: TIC54X-Directives. (line 123) 24121* labels: Labels. (line 6) 24122* lcomm directive: Lcomm. (line 6) 24123* lcomm directive, COFF: i386-Directives. (line 6) 24124* ld: Object. (line 15) 24125* ldouble directive M680x0: M68K-Float. (line 17) 24126* ldouble directive M68HC11: M68HC11-Float. (line 17) 24127* ldouble directive XGATE: XGATE-Float. (line 16) 24128* ldouble directive, TIC54X: TIC54X-Directives. (line 64) 24129* LDR reg,=<expr> pseudo op, AArch64: AArch64 Opcodes. (line 9) 24130* LDR reg,=<label> pseudo op, ARM: ARM Opcodes. (line 15) 24131* leafproc directive, i960: Directives-i960. (line 18) 24132* length directive, TIC54X: TIC54X-Directives. (line 127) 24133* length of symbols: Symbol Intro. (line 14) 24134* lflags directive (ignored): Lflags. (line 6) 24135* line comment character: Comments. (line 19) 24136* line comment character, AArch64: AArch64-Chars. (line 6) 24137* line comment character, Alpha: Alpha-Chars. (line 6) 24138* line comment character, ARC: ARC-Chars. (line 6) 24139* line comment character, ARM: ARM-Chars. (line 6) 24140* line comment character, AVR: AVR-Chars. (line 6) 24141* line comment character, CR16: CR16-Chars. (line 6) 24142* line comment character, D10V: D10V-Chars. (line 6) 24143* line comment character, D30V: D30V-Chars. (line 6) 24144* line comment character, Epiphany: Epiphany-Chars. (line 6) 24145* line comment character, H8/300: H8/300-Chars. (line 6) 24146* line comment character, i386: i386-Chars. (line 6) 24147* line comment character, i860: i860-Chars. (line 6) 24148* line comment character, i960: i960-Chars. (line 6) 24149* line comment character, IA-64: IA-64-Chars. (line 6) 24150* line comment character, IP2K: IP2K-Chars. (line 6) 24151* line comment character, LM32: LM32-Chars. (line 6) 24152* line comment character, M32C: M32C-Chars. (line 6) 24153* line comment character, M680x0: M68K-Chars. (line 6) 24154* line comment character, M68HC11: M68HC11-Syntax. (line 17) 24155* line comment character, Meta: Meta-Chars. (line 6) 24156* line comment character, MicroBlaze: MicroBlaze-Chars. (line 6) 24157* line comment character, MIPS: MIPS-Chars. (line 6) 24158* line comment character, MSP 430: MSP430-Chars. (line 6) 24159* line comment character, Nios II: Nios II Chars. (line 6) 24160* line comment character, NS32K: NS32K-Chars. (line 6) 24161* line comment character, PJ: PJ-Chars. (line 6) 24162* line comment character, PowerPC: PowerPC-Chars. (line 6) 24163* line comment character, RL78: RL78-Chars. (line 6) 24164* line comment character, RX: RX-Chars. (line 6) 24165* line comment character, s390: s390 Characters. (line 6) 24166* line comment character, SCORE: SCORE-Chars. (line 6) 24167* line comment character, SH: SH-Chars. (line 6) 24168* line comment character, SH64: SH64-Chars. (line 6) 24169* line comment character, Sparc: Sparc-Chars. (line 6) 24170* line comment character, TIC54X: TIC54X-Chars. (line 6) 24171* line comment character, TIC6X: TIC6X Syntax. (line 6) 24172* line comment character, V850: V850-Chars. (line 6) 24173* line comment character, VAX: VAX-Chars. (line 6) 24174* line comment character, XGATE: XGATE-Syntax. (line 16) 24175* line comment character, XStormy16: XStormy16-Chars. (line 6) 24176* line comment character, Z80: Z80-Chars. (line 6) 24177* line comment character, Z8000: Z8000-Chars. (line 6) 24178* line comment characters, CRIS: CRIS-Chars. (line 6) 24179* line comment characters, MMIX: MMIX-Chars. (line 6) 24180* line directive: Line. (line 6) 24181* line directive, MSP 430: MSP430 Directives. (line 14) 24182* line numbers, in input files: Input Files. (line 35) 24183* line numbers, in warnings/errors: Errors. (line 16) 24184* line separator character: Statements. (line 6) 24185* line separator character, Nios II: Nios II Chars. (line 6) 24186* line separator, AArch64: AArch64-Chars. (line 10) 24187* line separator, Alpha: Alpha-Chars. (line 11) 24188* line separator, ARC: ARC-Chars. (line 12) 24189* line separator, ARM: ARM-Chars. (line 14) 24190* line separator, AVR: AVR-Chars. (line 14) 24191* line separator, CR16: CR16-Chars. (line 13) 24192* line separator, Epiphany: Epiphany-Chars. (line 14) 24193* line separator, H8/300: H8/300-Chars. (line 8) 24194* line separator, i386: i386-Chars. (line 18) 24195* line separator, i860: i860-Chars. (line 14) 24196* line separator, i960: i960-Chars. (line 14) 24197* line separator, IA-64: IA-64-Chars. (line 8) 24198* line separator, IP2K: IP2K-Chars. (line 14) 24199* line separator, LM32: LM32-Chars. (line 12) 24200* line separator, M32C: M32C-Chars. (line 14) 24201* line separator, M680x0: M68K-Chars. (line 20) 24202* line separator, M68HC11: M68HC11-Syntax. (line 27) 24203* line separator, Meta: Meta-Chars. (line 8) 24204* line separator, MicroBlaze: MicroBlaze-Chars. (line 14) 24205* line separator, MIPS: MIPS-Chars. (line 14) 24206* line separator, MSP 430: MSP430-Chars. (line 14) 24207* line separator, NS32K: NS32K-Chars. (line 18) 24208* line separator, PJ: PJ-Chars. (line 14) 24209* line separator, PowerPC: PowerPC-Chars. (line 18) 24210* line separator, RL78: RL78-Chars. (line 14) 24211* line separator, RX: RX-Chars. (line 14) 24212* line separator, s390: s390 Characters. (line 13) 24213* line separator, SCORE: SCORE-Chars. (line 14) 24214* line separator, SH: SH-Chars. (line 8) 24215* line separator, SH64: SH64-Chars. (line 13) 24216* line separator, Sparc: Sparc-Chars. (line 14) 24217* line separator, TIC54X: TIC54X-Chars. (line 17) 24218* line separator, TIC6X: TIC6X Syntax. (line 13) 24219* line separator, V850: V850-Chars. (line 13) 24220* line separator, VAX: VAX-Chars. (line 14) 24221* line separator, XGATE: XGATE-Syntax. (line 26) 24222* line separator, XStormy16: XStormy16-Chars. (line 14) 24223* line separator, Z80: Z80-Chars. (line 13) 24224* line separator, Z8000: Z8000-Chars. (line 13) 24225* lines starting with #: Comments. (line 33) 24226* linker: Object. (line 15) 24227* linker, and assembler: Secs Background. (line 10) 24228* linkonce directive: Linkonce. (line 6) 24229* list directive: List. (line 6) 24230* list directive, TIC54X: TIC54X-Directives. (line 131) 24231* listing control, turning off: Nolist. (line 6) 24232* listing control, turning on: List. (line 6) 24233* listing control: new page: Eject. (line 6) 24234* listing control: paper size: Psize. (line 6) 24235* listing control: subtitle: Sbttl. (line 6) 24236* listing control: title line: Title. (line 6) 24237* listings, enabling: a. (line 6) 24238* literal directive: Literal Directive. (line 6) 24239* literal pool entries, s390: s390 Literal Pool Entries. 24240 (line 6) 24241* literal_position directive: Literal Position Directive. 24242 (line 6) 24243* literal_prefix directive: Literal Prefix Directive. 24244 (line 6) 24245* little endian output, MIPS: Overview. (line 744) 24246* little endian output, PJ: Overview. (line 647) 24247* little-endian output, MIPS: MIPS Options. (line 13) 24248* little-endian output, TIC6X: TIC6X Options. (line 46) 24249* LM32 line comment character: LM32-Chars. (line 6) 24250* LM32 line separator: LM32-Chars. (line 12) 24251* LM32 modifiers: LM32-Modifiers. (line 6) 24252* LM32 opcode summary: LM32 Opcodes. (line 6) 24253* LM32 options (none): LM32 Options. (line 6) 24254* LM32 register names: LM32-Regs. (line 6) 24255* LM32 support: LM32-Dependent. (line 6) 24256* ln directive: Ln. (line 6) 24257* lo directive, Nios II: Nios II Relocations. (line 23) 24258* lo pseudo-op, V850: V850 Opcodes. (line 22) 24259* loc directive: Loc. (line 6) 24260* loc_mark_labels directive: Loc_mark_labels. (line 6) 24261* local common symbols: Lcomm. (line 6) 24262* local directive: Local. (line 6) 24263* local labels: Symbol Names. (line 40) 24264* local symbol names: Symbol Names. (line 27) 24265* local symbols, retaining in output: L. (line 6) 24266* location counter: Dot. (line 6) 24267* location counter, advancing: Org. (line 6) 24268* location counter, Z80: Z80-Chars. (line 15) 24269* logical file name: File. (line 13) 24270* logical line number: Line. (line 6) 24271* logical line numbers: Comments. (line 33) 24272* long directive: Long. (line 6) 24273* long directive, ARC: ARC Directives. (line 156) 24274* long directive, i386: i386-Float. (line 21) 24275* long directive, TIC54X: TIC54X-Directives. (line 135) 24276* long directive, x86-64: i386-Float. (line 21) 24277* longcall pseudo-op, V850: V850 Opcodes. (line 123) 24278* longcalls directive: Longcalls Directive. (line 6) 24279* longjump pseudo-op, V850: V850 Opcodes. (line 129) 24280* loop directive, TIC54X: TIC54X-Directives. (line 143) 24281* LOOP instructions, alignment: Xtensa Automatic Alignment. 24282 (line 6) 24283* low directive, M32R: M32R-Directives. (line 9) 24284* lp register, V850: V850-Regs. (line 98) 24285* lval: Z8000 Directives. (line 27) 24286* LWP, i386: i386-LWP. (line 6) 24287* LWP, x86-64: i386-LWP. (line 6) 24288* M16C architecture option: M32C-Opts. (line 12) 24289* M32C architecture option: M32C-Opts. (line 9) 24290* M32C line comment character: M32C-Chars. (line 6) 24291* M32C line separator: M32C-Chars. (line 14) 24292* M32C modifiers: M32C-Modifiers. (line 6) 24293* M32C options: M32C-Opts. (line 6) 24294* M32C support: M32C-Dependent. (line 6) 24295* M32R architecture options: M32R-Opts. (line 9) 24296* M32R directives: M32R-Directives. (line 6) 24297* M32R options: M32R-Opts. (line 6) 24298* M32R support: M32R-Dependent. (line 6) 24299* M32R warnings: M32R-Warnings. (line 6) 24300* M680x0 addressing modes: M68K-Syntax. (line 21) 24301* M680x0 architecture options: M68K-Opts. (line 98) 24302* M680x0 branch improvement: M68K-Branch. (line 6) 24303* M680x0 directives: M68K-Directives. (line 6) 24304* M680x0 floating point: M68K-Float. (line 6) 24305* M680x0 immediate character: M68K-Chars. (line 13) 24306* M680x0 line comment character: M68K-Chars. (line 6) 24307* M680x0 line separator: M68K-Chars. (line 20) 24308* M680x0 opcodes: M68K-opcodes. (line 6) 24309* M680x0 options: M68K-Opts. (line 6) 24310* M680x0 pseudo-opcodes: M68K-Branch. (line 6) 24311* M680x0 size modifiers: M68K-Syntax. (line 8) 24312* M680x0 support: M68K-Dependent. (line 6) 24313* M680x0 syntax: M68K-Syntax. (line 8) 24314* M68HC11 addressing modes: M68HC11-Syntax. (line 30) 24315* M68HC11 and M68HC12 support: M68HC11-Dependent. (line 6) 24316* M68HC11 assembler directive .far: M68HC11-Directives. (line 20) 24317* M68HC11 assembler directive .interrupt: M68HC11-Directives. (line 26) 24318* M68HC11 assembler directive .mode: M68HC11-Directives. (line 16) 24319* M68HC11 assembler directive .relax: M68HC11-Directives. (line 10) 24320* M68HC11 assembler directive .xrefb: M68HC11-Directives. (line 31) 24321* M68HC11 assembler directives: M68HC11-Directives. (line 6) 24322* M68HC11 branch improvement: M68HC11-Branch. (line 6) 24323* M68HC11 floating point: M68HC11-Float. (line 6) 24324* M68HC11 line comment character: M68HC11-Syntax. (line 17) 24325* M68HC11 line separator: M68HC11-Syntax. (line 27) 24326* M68HC11 modifiers: M68HC11-Modifiers. (line 6) 24327* M68HC11 opcodes: M68HC11-opcodes. (line 6) 24328* M68HC11 options: M68HC11-Opts. (line 6) 24329* M68HC11 pseudo-opcodes: M68HC11-Branch. (line 6) 24330* M68HC11 syntax: M68HC11-Syntax. (line 6) 24331* M68HC12 assembler directives: M68HC11-Directives. (line 6) 24332* machine dependencies: Machine Dependencies. 24333 (line 6) 24334* machine directives, AArch64: AArch64 Directives. (line 6) 24335* machine directives, ARC: ARC Directives. (line 6) 24336* machine directives, ARM: ARM Directives. (line 6) 24337* machine directives, H8/300 (none): H8/300 Directives. (line 6) 24338* machine directives, i860: Directives-i860. (line 6) 24339* machine directives, i960: Directives-i960. (line 6) 24340* machine directives, MSP 430: MSP430 Directives. (line 6) 24341* machine directives, Nios II: Nios II Directives. (line 6) 24342* machine directives, SH: SH Directives. (line 6) 24343* machine directives, SH64: SH64 Directives. (line 9) 24344* machine directives, SPARC: Sparc-Directives. (line 6) 24345* machine directives, TIC54X: TIC54X-Directives. (line 6) 24346* machine directives, TIC6X: TIC6X Directives. (line 6) 24347* machine directives, TILE-Gx: TILE-Gx Directives. (line 6) 24348* machine directives, TILEPro: TILEPro Directives. (line 6) 24349* machine directives, V850: V850 Directives. (line 6) 24350* machine directives, VAX: VAX-directives. (line 6) 24351* machine directives, x86: i386-Directives. (line 6) 24352* machine directives, XStormy16: XStormy16 Directives. 24353 (line 6) 24354* machine independent directives: Pseudo Ops. (line 6) 24355* machine instructions (not covered): Manual. (line 14) 24356* machine relocations, Nios II: Nios II Relocations. (line 6) 24357* machine-independent syntax: Syntax. (line 6) 24358* macro directive: Macro. (line 28) 24359* macro directive, TIC54X: TIC54X-Directives. (line 153) 24360* macros: Macro. (line 6) 24361* macros, count executed: Macro. (line 143) 24362* Macros, MSP 430: MSP430-Macros. (line 6) 24363* macros, TIC54X: TIC54X-Macros. (line 6) 24364* make rules: MD. (line 6) 24365* manual, structure and purpose: Manual. (line 6) 24366* math builtins, TIC54X: TIC54X-Builtins. (line 6) 24367* Maximum number of continuation lines: listing. (line 34) 24368* memory references, i386: i386-Memory. (line 6) 24369* memory references, x86-64: i386-Memory. (line 6) 24370* memory-mapped registers, TIC54X: TIC54X-MMRegs. (line 6) 24371* merging text and data sections: R. (line 6) 24372* messages from assembler: Errors. (line 6) 24373* Meta architectures: Meta Options. (line 6) 24374* Meta line comment character: Meta-Chars. (line 6) 24375* Meta line separator: Meta-Chars. (line 8) 24376* Meta options: Meta Options. (line 6) 24377* Meta registers: Meta-Regs. (line 6) 24378* Meta support: Meta-Dependent. (line 6) 24379* MicroBlaze architectures: MicroBlaze-Dependent. 24380 (line 6) 24381* MicroBlaze directives: MicroBlaze Directives. 24382 (line 6) 24383* MicroBlaze line comment character: MicroBlaze-Chars. (line 6) 24384* MicroBlaze line separator: MicroBlaze-Chars. (line 14) 24385* MicroBlaze support: MicroBlaze-Dependent. 24386 (line 13) 24387* minus, permitted arguments: Infix Ops. (line 49) 24388* MIPS 32-bit microMIPS instruction generation override: MIPS assembly options. 24389 (line 6) 24390* MIPS architecture options: MIPS Options. (line 29) 24391* MIPS big-endian output: MIPS Options. (line 13) 24392* MIPS CPU override: MIPS ISA. (line 18) 24393* MIPS DSP Release 1 instruction generation override: MIPS ASE Instruction Generation Overrides. 24394 (line 21) 24395* MIPS DSP Release 2 instruction generation override: MIPS ASE Instruction Generation Overrides. 24396 (line 26) 24397* MIPS endianness: Overview. (line 741) 24398* MIPS IEEE 754 NaN data encoding selection: MIPS NaN Encodings. 24399 (line 6) 24400* MIPS ISA: Overview. (line 747) 24401* MIPS ISA override: MIPS ISA. (line 6) 24402* MIPS line comment character: MIPS-Chars. (line 6) 24403* MIPS line separator: MIPS-Chars. (line 14) 24404* MIPS little-endian output: MIPS Options. (line 13) 24405* MIPS MCU instruction generation override: MIPS ASE Instruction Generation Overrides. 24406 (line 37) 24407* MIPS MDMX instruction generation override: MIPS ASE Instruction Generation Overrides. 24408 (line 16) 24409* MIPS MIPS-3D instruction generation override: MIPS ASE Instruction Generation Overrides. 24410 (line 6) 24411* MIPS MT instruction generation override: MIPS ASE Instruction Generation Overrides. 24412 (line 32) 24413* MIPS option stack: MIPS Option Stack. (line 6) 24414* MIPS processor: MIPS-Dependent. (line 6) 24415* MIT: M68K-Syntax. (line 6) 24416* mlib directive, TIC54X: TIC54X-Directives. (line 159) 24417* mlist directive, TIC54X: TIC54X-Directives. (line 164) 24418* MMIX assembler directive BSPEC: MMIX-Pseudos. (line 131) 24419* MMIX assembler directive BYTE: MMIX-Pseudos. (line 97) 24420* MMIX assembler directive ESPEC: MMIX-Pseudos. (line 131) 24421* MMIX assembler directive GREG: MMIX-Pseudos. (line 50) 24422* MMIX assembler directive IS: MMIX-Pseudos. (line 42) 24423* MMIX assembler directive LOC: MMIX-Pseudos. (line 7) 24424* MMIX assembler directive LOCAL: MMIX-Pseudos. (line 28) 24425* MMIX assembler directive OCTA: MMIX-Pseudos. (line 108) 24426* MMIX assembler directive PREFIX: MMIX-Pseudos. (line 120) 24427* MMIX assembler directive TETRA: MMIX-Pseudos. (line 108) 24428* MMIX assembler directive WYDE: MMIX-Pseudos. (line 108) 24429* MMIX assembler directives: MMIX-Pseudos. (line 6) 24430* MMIX line comment characters: MMIX-Chars. (line 6) 24431* MMIX options: MMIX-Opts. (line 6) 24432* MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 131) 24433* MMIX pseudo-op BYTE: MMIX-Pseudos. (line 97) 24434* MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 131) 24435* MMIX pseudo-op GREG: MMIX-Pseudos. (line 50) 24436* MMIX pseudo-op IS: MMIX-Pseudos. (line 42) 24437* MMIX pseudo-op LOC: MMIX-Pseudos. (line 7) 24438* MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 28) 24439* MMIX pseudo-op OCTA: MMIX-Pseudos. (line 108) 24440* MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 120) 24441* MMIX pseudo-op TETRA: MMIX-Pseudos. (line 108) 24442* MMIX pseudo-op WYDE: MMIX-Pseudos. (line 108) 24443* MMIX pseudo-ops: MMIX-Pseudos. (line 6) 24444* MMIX register names: MMIX-Regs. (line 6) 24445* MMIX support: MMIX-Dependent. (line 6) 24446* mmixal differences: MMIX-mmixal. (line 6) 24447* mmregs directive, TIC54X: TIC54X-Directives. (line 169) 24448* mmsg directive, TIC54X: TIC54X-Directives. (line 77) 24449* MMX, i386: i386-SIMD. (line 6) 24450* MMX, x86-64: i386-SIMD. (line 6) 24451* mnemonic compatibility, i386: i386-Mnemonics. (line 62) 24452* mnemonic suffixes, i386: i386-Variations. (line 29) 24453* mnemonic suffixes, x86-64: i386-Variations. (line 29) 24454* mnemonics for opcodes, VAX: VAX-opcodes. (line 6) 24455* mnemonics, AVR: AVR Opcodes. (line 6) 24456* mnemonics, D10V: D10V-Opcodes. (line 6) 24457* mnemonics, D30V: D30V-Opcodes. (line 6) 24458* mnemonics, H8/300: H8/300 Opcodes. (line 6) 24459* mnemonics, LM32: LM32 Opcodes. (line 6) 24460* mnemonics, SH: SH Opcodes. (line 6) 24461* mnemonics, SH64: SH64 Opcodes. (line 6) 24462* mnemonics, Z8000: Z8000 Opcodes. (line 6) 24463* mnolist directive, TIC54X: TIC54X-Directives. (line 164) 24464* modifiers, M32C: M32C-Modifiers. (line 6) 24465* Motorola syntax for the 680x0: M68K-Moto-Syntax. (line 6) 24466* MOVI instructions, relaxation: Xtensa Immediate Relaxation. 24467 (line 12) 24468* MOVN, MOVZ and MOVK group relocations, AArch64: AArch64-Relocations. 24469 (line 6) 24470* MOVW and MOVT relocations, ARM: ARM-Relocations. (line 21) 24471* MRI compatibility mode: M. (line 6) 24472* mri directive: MRI. (line 6) 24473* MRI mode, temporarily: MRI. (line 6) 24474* MSP 430 floating point (IEEE): MSP430 Floating Point. 24475 (line 6) 24476* MSP 430 identifiers: MSP430-Chars. (line 17) 24477* MSP 430 line comment character: MSP430-Chars. (line 6) 24478* MSP 430 line separator: MSP430-Chars. (line 14) 24479* MSP 430 machine directives: MSP430 Directives. (line 6) 24480* MSP 430 macros: MSP430-Macros. (line 6) 24481* MSP 430 opcodes: MSP430 Opcodes. (line 6) 24482* MSP 430 options (none): MSP430 Options. (line 6) 24483* MSP 430 profiling capability: MSP430 Profiling Capability. 24484 (line 6) 24485* MSP 430 register names: MSP430-Regs. (line 6) 24486* MSP 430 support: MSP430-Dependent. (line 6) 24487* MSP430 Assembler Extensions: MSP430-Ext. (line 6) 24488* mul instruction, i386: i386-Notes. (line 6) 24489* mul instruction, x86-64: i386-Notes. (line 6) 24490* N32K support: NS32K-Dependent. (line 6) 24491* name: Z8000 Directives. (line 18) 24492* named section: Section. (line 6) 24493* named sections: Ld Sections. (line 8) 24494* names, symbol: Symbol Names. (line 6) 24495* naming object file: o. (line 6) 24496* new page, in listings: Eject. (line 6) 24497* newblock directive, TIC54X: TIC54X-Directives. (line 175) 24498* newline (\n): Strings. (line 21) 24499* newline, required at file end: Statements. (line 14) 24500* Nios II line comment character: Nios II Chars. (line 6) 24501* Nios II line separator character: Nios II Chars. (line 6) 24502* Nios II machine directives: Nios II Directives. (line 6) 24503* Nios II machine relocations: Nios II Relocations. (line 6) 24504* Nios II opcodes: Nios II Opcodes. (line 6) 24505* Nios II options: Nios II Options. (line 6) 24506* Nios II support: NiosII-Dependent. (line 6) 24507* Nios support: NiosII-Dependent. (line 6) 24508* no-absolute-literals directive: Absolute Literals Directive. 24509 (line 6) 24510* no-longcalls directive: Longcalls Directive. (line 6) 24511* no-relax command line option, Nios II: Nios II Options. (line 20) 24512* no-schedule directive: Schedule Directive. (line 6) 24513* no-transform directive: Transform Directive. (line 6) 24514* nolist directive: Nolist. (line 6) 24515* nolist directive, TIC54X: TIC54X-Directives. (line 131) 24516* NOP pseudo op, ARM: ARM Opcodes. (line 9) 24517* notes for Alpha: Alpha Notes. (line 6) 24518* NS32K line comment character: NS32K-Chars. (line 6) 24519* NS32K line separator: NS32K-Chars. (line 18) 24520* null-terminated strings: Asciz. (line 6) 24521* number constants: Numbers. (line 6) 24522* number of macros executed: Macro. (line 143) 24523* numbered subsections: Sub-Sections. (line 6) 24524* numbers, 16-bit: hword. (line 6) 24525* numeric values: Expressions. (line 6) 24526* nword directive, SPARC: Sparc-Directives. (line 20) 24527* object attributes: Object Attributes. (line 6) 24528* object file: Object. (line 6) 24529* object file format: Object Formats. (line 6) 24530* object file name: o. (line 6) 24531* object file, after errors: Z. (line 6) 24532* obsolescent directives: Deprecated. (line 6) 24533* octa directive: Octa. (line 6) 24534* octal character code (\DDD): Strings. (line 30) 24535* octal integers: Integers. (line 9) 24536* offset directive: Offset. (line 6) 24537* offset directive, V850: V850 Directives. (line 6) 24538* opcode mnemonics, VAX: VAX-opcodes. (line 6) 24539* opcode names, TILE-Gx: TILE-Gx Opcodes. (line 6) 24540* opcode names, TILEPro: TILEPro Opcodes. (line 6) 24541* opcode names, Xtensa: Xtensa Opcodes. (line 6) 24542* opcode summary, AVR: AVR Opcodes. (line 6) 24543* opcode summary, D10V: D10V-Opcodes. (line 6) 24544* opcode summary, D30V: D30V-Opcodes. (line 6) 24545* opcode summary, H8/300: H8/300 Opcodes. (line 6) 24546* opcode summary, LM32: LM32 Opcodes. (line 6) 24547* opcode summary, SH: SH Opcodes. (line 6) 24548* opcode summary, SH64: SH64 Opcodes. (line 6) 24549* opcode summary, Z8000: Z8000 Opcodes. (line 6) 24550* opcodes for AArch64: AArch64 Opcodes. (line 6) 24551* opcodes for ARC: ARC Opcodes. (line 6) 24552* opcodes for ARM: ARM Opcodes. (line 6) 24553* opcodes for MSP 430: MSP430 Opcodes. (line 6) 24554* opcodes for Nios II: Nios II Opcodes. (line 6) 24555* opcodes for V850: V850 Opcodes. (line 6) 24556* opcodes, i860: Opcodes for i860. (line 6) 24557* opcodes, i960: Opcodes for i960. (line 6) 24558* opcodes, M680x0: M68K-opcodes. (line 6) 24559* opcodes, M68HC11: M68HC11-opcodes. (line 6) 24560* operand delimiters, i386: i386-Variations. (line 15) 24561* operand delimiters, x86-64: i386-Variations. (line 15) 24562* operand notation, VAX: VAX-operands. (line 6) 24563* operands in expressions: Arguments. (line 6) 24564* operator precedence: Infix Ops. (line 11) 24565* operators, in expressions: Operators. (line 6) 24566* operators, permitted arguments: Infix Ops. (line 6) 24567* optimization, D10V: Overview. (line 504) 24568* optimization, D30V: Overview. (line 509) 24569* optimizations: Xtensa Optimizations. 24570 (line 6) 24571* option directive, ARC: ARC Directives. (line 159) 24572* option directive, TIC54X: TIC54X-Directives. (line 179) 24573* option summary: Overview. (line 6) 24574* options for AArch64 (none): AArch64 Options. (line 6) 24575* options for Alpha: Alpha Options. (line 6) 24576* options for ARC (none): ARC Options. (line 6) 24577* options for ARM (none): ARM Options. (line 6) 24578* options for AVR (none): AVR Options. (line 6) 24579* options for Blackfin (none): Blackfin Options. (line 6) 24580* options for i386: i386-Options. (line 6) 24581* options for IA-64: IA-64 Options. (line 6) 24582* options for LM32 (none): LM32 Options. (line 6) 24583* options for Meta: Meta Options. (line 6) 24584* options for MSP430 (none): MSP430 Options. (line 6) 24585* options for Nios II: Nios II Options. (line 6) 24586* options for PDP-11: PDP-11-Options. (line 6) 24587* options for PowerPC: PowerPC-Opts. (line 6) 24588* options for s390: s390 Options. (line 6) 24589* options for SCORE: SCORE-Opts. (line 6) 24590* options for SPARC: Sparc-Opts. (line 6) 24591* options for TIC6X: TIC6X Options. (line 6) 24592* options for V850 (none): V850 Options. (line 6) 24593* options for VAX/VMS: VAX-Opts. (line 42) 24594* options for x86-64: i386-Options. (line 6) 24595* options for Z80: Z80 Options. (line 6) 24596* options, all versions of assembler: Invoking. (line 6) 24597* options, command line: Command Line. (line 13) 24598* options, CRIS: CRIS-Opts. (line 6) 24599* options, D10V: D10V-Opts. (line 6) 24600* options, D30V: D30V-Opts. (line 6) 24601* options, Epiphany: Epiphany Options. (line 6) 24602* options, H8/300: H8/300 Options. (line 6) 24603* options, i960: Options-i960. (line 6) 24604* options, IP2K: IP2K-Opts. (line 6) 24605* options, M32C: M32C-Opts. (line 6) 24606* options, M32R: M32R-Opts. (line 6) 24607* options, M680x0: M68K-Opts. (line 6) 24608* options, M68HC11: M68HC11-Opts. (line 6) 24609* options, MMIX: MMIX-Opts. (line 6) 24610* options, PJ: PJ Options. (line 6) 24611* options, RL78: RL78-Opts. (line 6) 24612* options, RX: RX-Opts. (line 6) 24613* options, SH: SH Options. (line 6) 24614* options, SH64: SH64 Options. (line 6) 24615* options, TIC54X: TIC54X-Opts. (line 6) 24616* options, XGATE: XGATE-Opts. (line 6) 24617* options, Z8000: Z8000 Options. (line 6) 24618* org directive: Org. (line 6) 24619* other attribute, of a.out symbol: Symbol Other. (line 6) 24620* output file: Object. (line 6) 24621* p2align directive: P2align. (line 6) 24622* p2alignl directive: P2align. (line 28) 24623* p2alignw directive: P2align. (line 28) 24624* padding the location counter: Align. (line 6) 24625* padding the location counter given a power of two: P2align. (line 6) 24626* padding the location counter given number of bytes: Balign. (line 6) 24627* page, in listings: Eject. (line 6) 24628* paper size, for listings: Psize. (line 6) 24629* paths for .include: I. (line 6) 24630* patterns, writing in memory: Fill. (line 6) 24631* PDP-11 comments: PDP-11-Syntax. (line 16) 24632* PDP-11 floating-point register syntax: PDP-11-Syntax. (line 13) 24633* PDP-11 general-purpose register syntax: PDP-11-Syntax. (line 10) 24634* PDP-11 instruction naming: PDP-11-Mnemonics. (line 6) 24635* PDP-11 line separator: PDP-11-Syntax. (line 19) 24636* PDP-11 support: PDP-11-Dependent. (line 6) 24637* PDP-11 syntax: PDP-11-Syntax. (line 6) 24638* PIC code generation for ARM: ARM Options. (line 169) 24639* PIC code generation for M32R: M32R-Opts. (line 42) 24640* PIC selection, MIPS: MIPS Options. (line 21) 24641* PJ endianness: Overview. (line 644) 24642* PJ line comment character: PJ-Chars. (line 6) 24643* PJ line separator: PJ-Chars. (line 14) 24644* PJ options: PJ Options. (line 6) 24645* PJ support: PJ-Dependent. (line 6) 24646* plus, permitted arguments: Infix Ops. (line 44) 24647* popsection directive: PopSection. (line 6) 24648* Position-independent code, CRIS: CRIS-Opts. (line 27) 24649* Position-independent code, symbols in, CRIS: CRIS-Pic. (line 6) 24650* PowerPC architectures: PowerPC-Opts. (line 6) 24651* PowerPC directives: PowerPC-Pseudo. (line 6) 24652* PowerPC line comment character: PowerPC-Chars. (line 6) 24653* PowerPC line separator: PowerPC-Chars. (line 18) 24654* PowerPC options: PowerPC-Opts. (line 6) 24655* PowerPC support: PPC-Dependent. (line 6) 24656* precedence of operators: Infix Ops. (line 11) 24657* precision, floating point: Flonums. (line 6) 24658* prefix operators: Prefix Ops. (line 6) 24659* prefixes, i386: i386-Prefixes. (line 6) 24660* preprocessing: Preprocessing. (line 6) 24661* preprocessing, turning on and off: Preprocessing. (line 26) 24662* previous directive: Previous. (line 6) 24663* primary attributes, COFF symbols: COFF Symbols. (line 13) 24664* print directive: Print. (line 6) 24665* proc directive, SPARC: Sparc-Directives. (line 25) 24666* profiler directive, MSP 430: MSP430 Directives. (line 26) 24667* profiling capability for MSP 430: MSP430 Profiling Capability. 24668 (line 6) 24669* protected directive: Protected. (line 6) 24670* pseudo-op .arch, CRIS: CRIS-Pseudos. (line 45) 24671* pseudo-op .dword, CRIS: CRIS-Pseudos. (line 12) 24672* pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 17) 24673* pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 131) 24674* pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 97) 24675* pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 131) 24676* pseudo-op GREG, MMIX: MMIX-Pseudos. (line 50) 24677* pseudo-op IS, MMIX: MMIX-Pseudos. (line 42) 24678* pseudo-op LOC, MMIX: MMIX-Pseudos. (line 7) 24679* pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 28) 24680* pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 108) 24681* pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 120) 24682* pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 108) 24683* pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 108) 24684* pseudo-opcodes for XStormy16: XStormy16 Opcodes. (line 6) 24685* pseudo-opcodes, M680x0: M68K-Branch. (line 6) 24686* pseudo-opcodes, M68HC11: M68HC11-Branch. (line 6) 24687* pseudo-ops for branch, VAX: VAX-branch. (line 6) 24688* pseudo-ops, CRIS: CRIS-Pseudos. (line 6) 24689* pseudo-ops, machine independent: Pseudo Ops. (line 6) 24690* pseudo-ops, MMIX: MMIX-Pseudos. (line 6) 24691* psize directive: Psize. (line 6) 24692* PSR bits: IA-64-Bits. (line 6) 24693* pstring directive, TIC54X: TIC54X-Directives. (line 208) 24694* psw register, V850: V850-Regs. (line 116) 24695* purgem directive: Purgem. (line 6) 24696* purpose of GNU assembler: GNU Assembler. (line 12) 24697* pushsection directive: PushSection. (line 6) 24698* quad directive: Quad. (line 6) 24699* quad directive, i386: i386-Float. (line 21) 24700* quad directive, x86-64: i386-Float. (line 21) 24701* real-mode code, i386: i386-16bit. (line 6) 24702* ref directive, TIC54X: TIC54X-Directives. (line 103) 24703* register directive, SPARC: Sparc-Directives. (line 29) 24704* register names, AArch64: AArch64-Regs. (line 6) 24705* register names, Alpha: Alpha-Regs. (line 6) 24706* register names, ARC: ARC-Regs. (line 6) 24707* register names, ARM: ARM-Regs. (line 6) 24708* register names, AVR: AVR-Regs. (line 6) 24709* register names, CRIS: CRIS-Regs. (line 6) 24710* register names, H8/300: H8/300-Regs. (line 6) 24711* register names, IA-64: IA-64-Regs. (line 6) 24712* register names, LM32: LM32-Regs. (line 6) 24713* register names, MMIX: MMIX-Regs. (line 6) 24714* register names, MSP 430: MSP430-Regs. (line 6) 24715* register names, Sparc: Sparc-Regs. (line 6) 24716* register names, TILE-Gx: TILE-Gx Registers. (line 6) 24717* register names, TILEPro: TILEPro Registers. (line 6) 24718* register names, V850: V850-Regs. (line 6) 24719* register names, VAX: VAX-operands. (line 17) 24720* register names, Xtensa: Xtensa Registers. (line 6) 24721* register names, Z80: Z80-Regs. (line 6) 24722* register naming, s390: s390 Register. (line 6) 24723* register operands, i386: i386-Variations. (line 15) 24724* register operands, x86-64: i386-Variations. (line 15) 24725* registers, D10V: D10V-Regs. (line 6) 24726* registers, D30V: D30V-Regs. (line 6) 24727* registers, i386: i386-Regs. (line 6) 24728* registers, Meta: Meta-Regs. (line 6) 24729* registers, SH: SH-Regs. (line 6) 24730* registers, SH64: SH64-Regs. (line 6) 24731* registers, TIC54X memory-mapped: TIC54X-MMRegs. (line 6) 24732* registers, x86-64: i386-Regs. (line 6) 24733* registers, Z8000: Z8000-Regs. (line 6) 24734* relax-all command line option, Nios II: Nios II Options. (line 13) 24735* relax-section command line option, Nios II: Nios II Options. 24736 (line 6) 24737* relaxation: Xtensa Relaxation. (line 6) 24738* relaxation of ADDI instructions: Xtensa Immediate Relaxation. 24739 (line 43) 24740* relaxation of branch instructions: Xtensa Branch Relaxation. 24741 (line 6) 24742* relaxation of call instructions: Xtensa Call Relaxation. 24743 (line 6) 24744* relaxation of immediate fields: Xtensa Immediate Relaxation. 24745 (line 6) 24746* relaxation of L16SI instructions: Xtensa Immediate Relaxation. 24747 (line 23) 24748* relaxation of L16UI instructions: Xtensa Immediate Relaxation. 24749 (line 23) 24750* relaxation of L32I instructions: Xtensa Immediate Relaxation. 24751 (line 23) 24752* relaxation of L8UI instructions: Xtensa Immediate Relaxation. 24753 (line 23) 24754* relaxation of MOVI instructions: Xtensa Immediate Relaxation. 24755 (line 12) 24756* reloc directive: Reloc. (line 6) 24757* relocation: Sections. (line 6) 24758* relocation example: Ld Sections. (line 40) 24759* relocations, AArch64: AArch64-Relocations. (line 6) 24760* relocations, Alpha: Alpha-Relocs. (line 6) 24761* relocations, Sparc: Sparc-Relocs. (line 6) 24762* repeat prefixes, i386: i386-Prefixes. (line 44) 24763* reporting bugs in assembler: Reporting Bugs. (line 6) 24764* rept directive: Rept. (line 6) 24765* reserve directive, SPARC: Sparc-Directives. (line 39) 24766* return instructions, i386: i386-Variations. (line 41) 24767* return instructions, x86-64: i386-Variations. (line 41) 24768* REX prefixes, i386: i386-Prefixes. (line 46) 24769* RL78 assembler directives: RL78-Directives. (line 6) 24770* RL78 line comment character: RL78-Chars. (line 6) 24771* RL78 line separator: RL78-Chars. (line 14) 24772* RL78 modifiers: RL78-Modifiers. (line 6) 24773* RL78 options: RL78-Opts. (line 6) 24774* RL78 support: RL78-Dependent. (line 6) 24775* rsect: Z8000 Directives. (line 52) 24776* RX assembler directive .3byte: RX-Directives. (line 9) 24777* RX assembler directive .fetchalign: RX-Directives. (line 13) 24778* RX assembler directives: RX-Directives. (line 6) 24779* RX floating point: RX-Float. (line 6) 24780* RX line comment character: RX-Chars. (line 6) 24781* RX line separator: RX-Chars. (line 14) 24782* RX modifiers: RX-Modifiers. (line 6) 24783* RX options: RX-Opts. (line 6) 24784* RX support: RX-Dependent. (line 6) 24785* s390 floating point: s390 Floating Point. (line 6) 24786* s390 instruction aliases: s390 Aliases. (line 6) 24787* s390 instruction formats: s390 Formats. (line 6) 24788* s390 instruction marker: s390 Instruction Marker. 24789 (line 6) 24790* s390 instruction mnemonics: s390 Mnemonics. (line 6) 24791* s390 instruction operand modifier: s390 Operand Modifier. 24792 (line 6) 24793* s390 instruction operands: s390 Operands. (line 6) 24794* s390 instruction syntax: s390 Syntax. (line 6) 24795* s390 line comment character: s390 Characters. (line 6) 24796* s390 line separator: s390 Characters. (line 13) 24797* s390 literal pool entries: s390 Literal Pool Entries. 24798 (line 6) 24799* s390 options: s390 Options. (line 6) 24800* s390 register naming: s390 Register. (line 6) 24801* s390 support: S/390-Dependent. (line 6) 24802* sblock directive, TIC54X: TIC54X-Directives. (line 182) 24803* sbttl directive: Sbttl. (line 6) 24804* schedule directive: Schedule Directive. (line 6) 24805* scl directive: Scl. (line 6) 24806* SCORE architectures: SCORE-Opts. (line 6) 24807* SCORE directives: SCORE-Pseudo. (line 6) 24808* SCORE line comment character: SCORE-Chars. (line 6) 24809* SCORE line separator: SCORE-Chars. (line 14) 24810* SCORE options: SCORE-Opts. (line 6) 24811* SCORE processor: SCORE-Dependent. (line 6) 24812* sdaoff pseudo-op, V850: V850 Opcodes. (line 65) 24813* search path for .include: I. (line 6) 24814* sect directive, TIC54X: TIC54X-Directives. (line 188) 24815* section directive (COFF version): Section. (line 16) 24816* section directive (ELF version): Section. (line 76) 24817* section directive, V850: V850 Directives. (line 9) 24818* section override prefixes, i386: i386-Prefixes. (line 23) 24819* Section Stack <1>: SubSection. (line 6) 24820* Section Stack <2>: Section. (line 71) 24821* Section Stack <3>: PushSection. (line 6) 24822* Section Stack <4>: Previous. (line 6) 24823* Section Stack: PopSection. (line 6) 24824* section-relative addressing: Secs Background. (line 68) 24825* sections: Sections. (line 6) 24826* sections in messages, internal: As Sections. (line 6) 24827* sections, i386: i386-Variations. (line 47) 24828* sections, named: Ld Sections. (line 8) 24829* sections, x86-64: i386-Variations. (line 47) 24830* seg directive, SPARC: Sparc-Directives. (line 44) 24831* segm: Z8000 Directives. (line 10) 24832* set at directive, Nios II: Nios II Directives. (line 35) 24833* set break directive, Nios II: Nios II Directives. (line 43) 24834* set directive: Set. (line 6) 24835* set directive, Nios II: Nios II Directives. (line 57) 24836* set directive, TIC54X: TIC54X-Directives. (line 191) 24837* set noat directive, Nios II: Nios II Directives. (line 31) 24838* set nobreak directive, Nios II: Nios II Directives. (line 39) 24839* set norelax directive, Nios II: Nios II Directives. (line 46) 24840* set relaxall directive, Nios II: Nios II Directives. (line 53) 24841* set relaxsection directive, Nios II: Nios II Directives. (line 49) 24842* SH addressing modes: SH-Addressing. (line 6) 24843* SH floating point (IEEE): SH Floating Point. (line 6) 24844* SH line comment character: SH-Chars. (line 6) 24845* SH line separator: SH-Chars. (line 8) 24846* SH machine directives: SH Directives. (line 6) 24847* SH opcode summary: SH Opcodes. (line 6) 24848* SH options: SH Options. (line 6) 24849* SH registers: SH-Regs. (line 6) 24850* SH support: SH-Dependent. (line 6) 24851* SH64 ABI options: SH64 Options. (line 29) 24852* SH64 addressing modes: SH64-Addressing. (line 6) 24853* SH64 ISA options: SH64 Options. (line 6) 24854* SH64 line comment character: SH64-Chars. (line 6) 24855* SH64 line separator: SH64-Chars. (line 13) 24856* SH64 machine directives: SH64 Directives. (line 9) 24857* SH64 opcode summary: SH64 Opcodes. (line 6) 24858* SH64 options: SH64 Options. (line 6) 24859* SH64 registers: SH64-Regs. (line 6) 24860* SH64 support: SH64-Dependent. (line 6) 24861* shigh directive, M32R: M32R-Directives. (line 26) 24862* short directive: Short. (line 6) 24863* short directive, ARC: ARC Directives. (line 168) 24864* short directive, TIC54X: TIC54X-Directives. (line 111) 24865* SIMD, i386: i386-SIMD. (line 6) 24866* SIMD, x86-64: i386-SIMD. (line 6) 24867* single character constant: Chars. (line 6) 24868* single directive: Single. (line 6) 24869* single directive, i386: i386-Float. (line 14) 24870* single directive, x86-64: i386-Float. (line 14) 24871* single quote, Z80: Z80-Chars. (line 20) 24872* sixteen bit integers: hword. (line 6) 24873* sixteen byte integer: Octa. (line 6) 24874* size directive (COFF version): Size. (line 11) 24875* size directive (ELF version): Size. (line 19) 24876* size modifiers, D10V: D10V-Size. (line 6) 24877* size modifiers, D30V: D30V-Size. (line 6) 24878* size modifiers, M680x0: M68K-Syntax. (line 8) 24879* size prefixes, i386: i386-Prefixes. (line 27) 24880* size suffixes, H8/300: H8/300 Opcodes. (line 163) 24881* size, translations, Sparc: Sparc-Size-Translations. 24882 (line 6) 24883* sizes operands, i386: i386-Variations. (line 29) 24884* sizes operands, x86-64: i386-Variations. (line 29) 24885* skip directive: Skip. (line 6) 24886* skip directive, M680x0: M68K-Directives. (line 19) 24887* skip directive, SPARC: Sparc-Directives. (line 48) 24888* sleb128 directive: Sleb128. (line 6) 24889* small data, MIPS: MIPS Small Data. (line 6) 24890* SmartMIPS instruction generation override: MIPS ASE Instruction Generation Overrides. 24891 (line 11) 24892* SOM symbol attributes: SOM Symbols. (line 6) 24893* source program: Input Files. (line 6) 24894* source, destination operands; i386: i386-Variations. (line 22) 24895* source, destination operands; x86-64: i386-Variations. (line 22) 24896* sp register: Xtensa Registers. (line 6) 24897* sp register, V850: V850-Regs. (line 14) 24898* space directive: Space. (line 6) 24899* space directive, TIC54X: TIC54X-Directives. (line 196) 24900* space used, maximum for assembly: statistics. (line 6) 24901* SPARC architectures: Sparc-Opts. (line 6) 24902* Sparc constants: Sparc-Constants. (line 6) 24903* SPARC data alignment: Sparc-Aligned-Data. (line 6) 24904* SPARC floating point (IEEE): Sparc-Float. (line 6) 24905* Sparc line comment character: Sparc-Chars. (line 6) 24906* Sparc line separator: Sparc-Chars. (line 14) 24907* SPARC machine directives: Sparc-Directives. (line 6) 24908* SPARC options: Sparc-Opts. (line 6) 24909* Sparc registers: Sparc-Regs. (line 6) 24910* Sparc relocations: Sparc-Relocs. (line 6) 24911* Sparc size translations: Sparc-Size-Translations. 24912 (line 6) 24913* SPARC support: Sparc-Dependent. (line 6) 24914* SPARC syntax: Sparc-Aligned-Data. (line 21) 24915* special characters, M680x0: M68K-Chars. (line 6) 24916* special purpose registers, MSP 430: MSP430-Regs. (line 11) 24917* sslist directive, TIC54X: TIC54X-Directives. (line 203) 24918* ssnolist directive, TIC54X: TIC54X-Directives. (line 203) 24919* stabd directive: Stab. (line 38) 24920* stabn directive: Stab. (line 48) 24921* stabs directive: Stab. (line 51) 24922* stabX directives: Stab. (line 6) 24923* standard assembler sections: Secs Background. (line 27) 24924* standard input, as input file: Command Line. (line 10) 24925* statement separator character: Statements. (line 6) 24926* statement separator, AArch64: AArch64-Chars. (line 10) 24927* statement separator, Alpha: Alpha-Chars. (line 11) 24928* statement separator, ARC: ARC-Chars. (line 12) 24929* statement separator, ARM: ARM-Chars. (line 14) 24930* statement separator, AVR: AVR-Chars. (line 14) 24931* statement separator, CR16: CR16-Chars. (line 13) 24932* statement separator, Epiphany: Epiphany-Chars. (line 14) 24933* statement separator, H8/300: H8/300-Chars. (line 8) 24934* statement separator, i386: i386-Chars. (line 18) 24935* statement separator, i860: i860-Chars. (line 14) 24936* statement separator, i960: i960-Chars. (line 14) 24937* statement separator, IA-64: IA-64-Chars. (line 8) 24938* statement separator, IP2K: IP2K-Chars. (line 14) 24939* statement separator, LM32: LM32-Chars. (line 12) 24940* statement separator, M32C: M32C-Chars. (line 14) 24941* statement separator, M68HC11: M68HC11-Syntax. (line 27) 24942* statement separator, Meta: Meta-Chars. (line 8) 24943* statement separator, MicroBlaze: MicroBlaze-Chars. (line 14) 24944* statement separator, MIPS: MIPS-Chars. (line 14) 24945* statement separator, MSP 430: MSP430-Chars. (line 14) 24946* statement separator, NS32K: NS32K-Chars. (line 18) 24947* statement separator, PJ: PJ-Chars. (line 14) 24948* statement separator, PowerPC: PowerPC-Chars. (line 18) 24949* statement separator, RL78: RL78-Chars. (line 14) 24950* statement separator, RX: RX-Chars. (line 14) 24951* statement separator, s390: s390 Characters. (line 13) 24952* statement separator, SCORE: SCORE-Chars. (line 14) 24953* statement separator, SH: SH-Chars. (line 8) 24954* statement separator, SH64: SH64-Chars. (line 13) 24955* statement separator, Sparc: Sparc-Chars. (line 14) 24956* statement separator, TIC54X: TIC54X-Chars. (line 17) 24957* statement separator, TIC6X: TIC6X Syntax. (line 13) 24958* statement separator, V850: V850-Chars. (line 13) 24959* statement separator, VAX: VAX-Chars. (line 14) 24960* statement separator, XGATE: XGATE-Syntax. (line 26) 24961* statement separator, XStormy16: XStormy16-Chars. (line 14) 24962* statement separator, Z80: Z80-Chars. (line 13) 24963* statement separator, Z8000: Z8000-Chars. (line 13) 24964* statements, structure of: Statements. (line 6) 24965* statistics, about assembly: statistics. (line 6) 24966* stopping the assembly: Abort. (line 6) 24967* string constants: Strings. (line 6) 24968* string directive: String. (line 8) 24969* string directive on HPPA: HPPA Directives. (line 137) 24970* string directive, TIC54X: TIC54X-Directives. (line 208) 24971* string literals: Ascii. (line 6) 24972* string, copying to object file: String. (line 8) 24973* string16 directive: String. (line 8) 24974* string16, copying to object file: String. (line 8) 24975* string32 directive: String. (line 8) 24976* string32, copying to object file: String. (line 8) 24977* string64 directive: String. (line 8) 24978* string64, copying to object file: String. (line 8) 24979* string8 directive: String. (line 8) 24980* string8, copying to object file: String. (line 8) 24981* struct directive: Struct. (line 6) 24982* struct directive, TIC54X: TIC54X-Directives. (line 216) 24983* structure debugging, COFF: Tag. (line 6) 24984* sub-instruction ordering, D10V: D10V-Chars. (line 14) 24985* sub-instruction ordering, D30V: D30V-Chars. (line 14) 24986* sub-instructions, D10V: D10V-Subs. (line 6) 24987* sub-instructions, D30V: D30V-Subs. (line 6) 24988* subexpressions: Arguments. (line 24) 24989* subsection directive: SubSection. (line 6) 24990* subsym builtins, TIC54X: TIC54X-Macros. (line 16) 24991* subtitles for listings: Sbttl. (line 6) 24992* subtraction, permitted arguments: Infix Ops. (line 49) 24993* summary of options: Overview. (line 6) 24994* support: HPPA-Dependent. (line 6) 24995* supporting files, including: Include. (line 6) 24996* suppressing warnings: W. (line 11) 24997* sval: Z8000 Directives. (line 33) 24998* symbol attributes: Symbol Attributes. (line 6) 24999* symbol attributes, a.out: a.out Symbols. (line 6) 25000* symbol attributes, COFF: COFF Symbols. (line 6) 25001* symbol attributes, SOM: SOM Symbols. (line 6) 25002* symbol descriptor, COFF: Desc. (line 6) 25003* symbol modifiers <1>: M68HC11-Modifiers. (line 12) 25004* symbol modifiers <2>: M32C-Modifiers. (line 11) 25005* symbol modifiers <3>: LM32-Modifiers. (line 12) 25006* symbol modifiers: AVR-Modifiers. (line 12) 25007* symbol modifiers, TILE-Gx: TILE-Gx Modifiers. (line 6) 25008* symbol modifiers, TILEPro: TILEPro Modifiers. (line 6) 25009* symbol names: Symbol Names. (line 6) 25010* symbol names, $ in <1>: SH64-Chars. (line 15) 25011* symbol names, $ in <2>: SH-Chars. (line 15) 25012* symbol names, $ in <3>: Meta-Chars. (line 10) 25013* symbol names, $ in <4>: D30V-Chars. (line 70) 25014* symbol names, $ in: D10V-Chars. (line 53) 25015* symbol names, local: Symbol Names. (line 27) 25016* symbol names, temporary: Symbol Names. (line 40) 25017* symbol storage class (COFF): Scl. (line 6) 25018* symbol type: Symbol Type. (line 6) 25019* symbol type, COFF: Type. (line 11) 25020* symbol type, ELF: Type. (line 22) 25021* symbol value: Symbol Value. (line 6) 25022* symbol value, setting: Set. (line 6) 25023* symbol values, assigning: Setting Symbols. (line 6) 25024* symbol versioning: Symver. (line 6) 25025* symbol, common: Comm. (line 6) 25026* symbol, making visible to linker: Global. (line 6) 25027* symbolic debuggers, information for: Stab. (line 6) 25028* symbols: Symbols. (line 6) 25029* Symbols in position-independent code, CRIS: CRIS-Pic. (line 6) 25030* symbols with uppercase, VAX/VMS: VAX-Opts. (line 42) 25031* symbols, assigning values to: Equ. (line 6) 25032* Symbols, built-in, CRIS: CRIS-Symbols. (line 6) 25033* Symbols, CRIS, built-in: CRIS-Symbols. (line 6) 25034* symbols, local common: Lcomm. (line 6) 25035* symver directive: Symver. (line 6) 25036* syntax compatibility, i386: i386-Variations. (line 6) 25037* syntax compatibility, x86-64: i386-Variations. (line 6) 25038* syntax, AVR: AVR-Modifiers. (line 6) 25039* syntax, Blackfin: Blackfin Syntax. (line 6) 25040* syntax, D10V: D10V-Syntax. (line 6) 25041* syntax, D30V: D30V-Syntax. (line 6) 25042* syntax, LM32: LM32-Modifiers. (line 6) 25043* syntax, M680x0: M68K-Syntax. (line 8) 25044* syntax, M68HC11 <1>: M68HC11-Modifiers. (line 6) 25045* syntax, M68HC11: M68HC11-Syntax. (line 6) 25046* syntax, machine-independent: Syntax. (line 6) 25047* syntax, RL78: RL78-Modifiers. (line 6) 25048* syntax, RX: RX-Modifiers. (line 6) 25049* syntax, SPARC: Sparc-Aligned-Data. (line 21) 25050* syntax, TILE-Gx: TILE-Gx Syntax. (line 6) 25051* syntax, TILEPro: TILEPro Syntax. (line 6) 25052* syntax, XGATE: XGATE-Syntax. (line 6) 25053* syntax, Xtensa assembler: Xtensa Syntax. (line 6) 25054* sysproc directive, i960: Directives-i960. (line 37) 25055* tab (\t): Strings. (line 27) 25056* tab directive, TIC54X: TIC54X-Directives. (line 247) 25057* tag directive: Tag. (line 6) 25058* tag directive, TIC54X: TIC54X-Directives. (line 216) 25059* TBM, i386: i386-TBM. (line 6) 25060* TBM, x86-64: i386-TBM. (line 6) 25061* tdaoff pseudo-op, V850: V850 Opcodes. (line 81) 25062* temporary symbol names: Symbol Names. (line 40) 25063* text and data sections, joining: R. (line 6) 25064* text directive: Text. (line 6) 25065* text section: Ld Sections. (line 9) 25066* tfloat directive, i386: i386-Float. (line 14) 25067* tfloat directive, x86-64: i386-Float. (line 14) 25068* Thumb support <1>: ARM-Dependent. (line 6) 25069* Thumb support: AArch64-Dependent. (line 6) 25070* TIC54X builtin math functions: TIC54X-Builtins. (line 6) 25071* TIC54X line comment character: TIC54X-Chars. (line 6) 25072* TIC54X line separator: TIC54X-Chars. (line 17) 25073* TIC54X machine directives: TIC54X-Directives. (line 6) 25074* TIC54X memory-mapped registers: TIC54X-MMRegs. (line 6) 25075* TIC54X options: TIC54X-Opts. (line 6) 25076* TIC54X subsym builtins: TIC54X-Macros. (line 16) 25077* TIC54X support: TIC54X-Dependent. (line 6) 25078* TIC54X-specific macros: TIC54X-Macros. (line 6) 25079* TIC6X big-endian output: TIC6X Options. (line 46) 25080* TIC6X line comment character: TIC6X Syntax. (line 6) 25081* TIC6X line separator: TIC6X Syntax. (line 13) 25082* TIC6X little-endian output: TIC6X Options. (line 46) 25083* TIC6X machine directives: TIC6X Directives. (line 6) 25084* TIC6X options: TIC6X Options. (line 6) 25085* TIC6X support: TIC6X-Dependent. (line 6) 25086* TILE-Gx machine directives: TILE-Gx Directives. (line 6) 25087* TILE-Gx modifiers: TILE-Gx Modifiers. (line 6) 25088* TILE-Gx opcode names: TILE-Gx Opcodes. (line 6) 25089* TILE-Gx register names: TILE-Gx Registers. (line 6) 25090* TILE-Gx support: TILE-Gx-Dependent. (line 6) 25091* TILE-Gx syntax: TILE-Gx Syntax. (line 6) 25092* TILEPro machine directives: TILEPro Directives. (line 6) 25093* TILEPro modifiers: TILEPro Modifiers. (line 6) 25094* TILEPro opcode names: TILEPro Opcodes. (line 6) 25095* TILEPro register names: TILEPro Registers. (line 6) 25096* TILEPro support: TILEPro-Dependent. (line 6) 25097* TILEPro syntax: TILEPro Syntax. (line 6) 25098* time, total for assembly: statistics. (line 6) 25099* title directive: Title. (line 6) 25100* tls_gd directive, Nios II: Nios II Relocations. (line 38) 25101* tls_ie directive, Nios II: Nios II Relocations. (line 38) 25102* tls_ldm directive, Nios II: Nios II Relocations. (line 38) 25103* tls_ldo directive, Nios II: Nios II Relocations. (line 38) 25104* tls_le directive, Nios II: Nios II Relocations. (line 38) 25105* TMS320C6X support: TIC6X-Dependent. (line 6) 25106* tp register, V850: V850-Regs. (line 20) 25107* transform directive: Transform Directive. (line 6) 25108* trusted compiler: f. (line 6) 25109* turning preprocessing on and off: Preprocessing. (line 26) 25110* type directive (COFF version): Type. (line 11) 25111* type directive (ELF version): Type. (line 22) 25112* type of a symbol: Symbol Type. (line 6) 25113* ualong directive, SH: SH Directives. (line 6) 25114* uaquad directive, SH: SH Directives. (line 6) 25115* uaword directive, SH: SH Directives. (line 6) 25116* ubyte directive, TIC54X: TIC54X-Directives. (line 36) 25117* uchar directive, TIC54X: TIC54X-Directives. (line 36) 25118* uhalf directive, TIC54X: TIC54X-Directives. (line 111) 25119* uint directive, TIC54X: TIC54X-Directives. (line 111) 25120* uleb128 directive: Uleb128. (line 6) 25121* ulong directive, TIC54X: TIC54X-Directives. (line 135) 25122* undefined section: Ld Sections. (line 36) 25123* union directive, TIC54X: TIC54X-Directives. (line 250) 25124* unsegm: Z8000 Directives. (line 14) 25125* usect directive, TIC54X: TIC54X-Directives. (line 262) 25126* ushort directive, TIC54X: TIC54X-Directives. (line 111) 25127* uword directive, TIC54X: TIC54X-Directives. (line 111) 25128* V850 command line options: V850 Options. (line 9) 25129* V850 floating point (IEEE): V850 Floating Point. (line 6) 25130* V850 line comment character: V850-Chars. (line 6) 25131* V850 line separator: V850-Chars. (line 13) 25132* V850 machine directives: V850 Directives. (line 6) 25133* V850 opcodes: V850 Opcodes. (line 6) 25134* V850 options (none): V850 Options. (line 6) 25135* V850 register names: V850-Regs. (line 6) 25136* V850 support: V850-Dependent. (line 6) 25137* val directive: Val. (line 6) 25138* value attribute, COFF: Val. (line 6) 25139* value of a symbol: Symbol Value. (line 6) 25140* var directive, TIC54X: TIC54X-Directives. (line 272) 25141* VAX bitfields not supported: VAX-no. (line 6) 25142* VAX branch improvement: VAX-branch. (line 6) 25143* VAX command-line options ignored: VAX-Opts. (line 6) 25144* VAX displacement sizing character: VAX-operands. (line 12) 25145* VAX floating point: VAX-float. (line 6) 25146* VAX immediate character: VAX-operands. (line 6) 25147* VAX indirect character: VAX-operands. (line 9) 25148* VAX line comment character: VAX-Chars. (line 6) 25149* VAX line separator: VAX-Chars. (line 14) 25150* VAX machine directives: VAX-directives. (line 6) 25151* VAX opcode mnemonics: VAX-opcodes. (line 6) 25152* VAX operand notation: VAX-operands. (line 6) 25153* VAX register names: VAX-operands. (line 17) 25154* VAX support: Vax-Dependent. (line 6) 25155* Vax-11 C compatibility: VAX-Opts. (line 42) 25156* VAX/VMS options: VAX-Opts. (line 42) 25157* version directive: Version. (line 6) 25158* version directive, TIC54X: TIC54X-Directives. (line 276) 25159* version of assembler: v. (line 6) 25160* versions of symbols: Symver. (line 6) 25161* Virtualization instruction generation override: MIPS ASE Instruction Generation Overrides. 25162 (line 42) 25163* visibility <1>: Protected. (line 6) 25164* visibility <2>: Internal. (line 6) 25165* visibility: Hidden. (line 6) 25166* VMS (VAX) options: VAX-Opts. (line 42) 25167* vtable_entry directive: VTableEntry. (line 6) 25168* vtable_inherit directive: VTableInherit. (line 6) 25169* warning directive: Warning. (line 6) 25170* warning for altered difference tables: K. (line 6) 25171* warning messages: Errors. (line 6) 25172* warnings, causing error: W. (line 16) 25173* warnings, M32R: M32R-Warnings. (line 6) 25174* warnings, suppressing: W. (line 11) 25175* warnings, switching on: W. (line 19) 25176* weak directive: Weak. (line 6) 25177* weakref directive: Weakref. (line 6) 25178* whitespace: Whitespace. (line 6) 25179* whitespace, removed by preprocessor: Preprocessing. (line 7) 25180* wide floating point directives, VAX: VAX-directives. (line 10) 25181* width directive, TIC54X: TIC54X-Directives. (line 127) 25182* Width of continuation lines of disassembly output: listing. (line 21) 25183* Width of first line disassembly output: listing. (line 16) 25184* Width of source line output: listing. (line 28) 25185* wmsg directive, TIC54X: TIC54X-Directives. (line 77) 25186* word directive: Word. (line 6) 25187* word directive, ARC: ARC Directives. (line 171) 25188* word directive, H8/300: H8/300 Directives. (line 6) 25189* word directive, i386: i386-Float. (line 21) 25190* word directive, Nios II: Nios II Directives. (line 13) 25191* word directive, SPARC: Sparc-Directives. (line 51) 25192* word directive, TIC54X: TIC54X-Directives. (line 111) 25193* word directive, x86-64: i386-Float. (line 21) 25194* writing patterns in memory: Fill. (line 6) 25195* wval: Z8000 Directives. (line 24) 25196* x86 machine directives: i386-Directives. (line 6) 25197* x86-64 arch directive: i386-Arch. (line 6) 25198* x86-64 att_syntax pseudo op: i386-Variations. (line 6) 25199* x86-64 conversion instructions: i386-Mnemonics. (line 37) 25200* x86-64 floating point: i386-Float. (line 6) 25201* x86-64 immediate operands: i386-Variations. (line 15) 25202* x86-64 instruction naming: i386-Mnemonics. (line 6) 25203* x86-64 intel_syntax pseudo op: i386-Variations. (line 6) 25204* x86-64 jump optimization: i386-Jumps. (line 6) 25205* x86-64 jump, call, return: i386-Variations. (line 41) 25206* x86-64 jump/call operands: i386-Variations. (line 15) 25207* x86-64 memory references: i386-Memory. (line 6) 25208* x86-64 options: i386-Options. (line 6) 25209* x86-64 register operands: i386-Variations. (line 15) 25210* x86-64 registers: i386-Regs. (line 6) 25211* x86-64 sections: i386-Variations. (line 47) 25212* x86-64 size suffixes: i386-Variations. (line 29) 25213* x86-64 source, destination operands: i386-Variations. (line 22) 25214* x86-64 support: i386-Dependent. (line 6) 25215* x86-64 syntax compatibility: i386-Variations. (line 6) 25216* xfloat directive, TIC54X: TIC54X-Directives. (line 64) 25217* XGATE addressing modes: XGATE-Syntax. (line 29) 25218* XGATE assembler directives: XGATE-Directives. (line 6) 25219* XGATE floating point: XGATE-Float. (line 6) 25220* XGATE line comment character: XGATE-Syntax. (line 16) 25221* XGATE line separator: XGATE-Syntax. (line 26) 25222* XGATE opcodes: XGATE-opcodes. (line 6) 25223* XGATE options: XGATE-Opts. (line 6) 25224* XGATE support: XGATE-Dependent. (line 6) 25225* XGATE syntax: XGATE-Syntax. (line 6) 25226* xlong directive, TIC54X: TIC54X-Directives. (line 135) 25227* XStormy16 comment character: XStormy16-Chars. (line 11) 25228* XStormy16 line comment character: XStormy16-Chars. (line 6) 25229* XStormy16 line separator: XStormy16-Chars. (line 14) 25230* XStormy16 machine directives: XStormy16 Directives. 25231 (line 6) 25232* XStormy16 pseudo-opcodes: XStormy16 Opcodes. (line 6) 25233* XStormy16 support: XSTORMY16-Dependent. (line 6) 25234* Xtensa architecture: Xtensa-Dependent. (line 6) 25235* Xtensa assembler syntax: Xtensa Syntax. (line 6) 25236* Xtensa directives: Xtensa Directives. (line 6) 25237* Xtensa opcode names: Xtensa Opcodes. (line 6) 25238* Xtensa register names: Xtensa Registers. (line 6) 25239* xword directive, SPARC: Sparc-Directives. (line 55) 25240* Z80 $: Z80-Chars. (line 15) 25241* Z80 ': Z80-Chars. (line 20) 25242* Z80 floating point: Z80 Floating Point. (line 6) 25243* Z80 line comment character: Z80-Chars. (line 6) 25244* Z80 line separator: Z80-Chars. (line 13) 25245* Z80 options: Z80 Options. (line 6) 25246* Z80 registers: Z80-Regs. (line 6) 25247* Z80 support: Z80-Dependent. (line 6) 25248* Z80 Syntax: Z80 Options. (line 47) 25249* Z80, \: Z80-Chars. (line 18) 25250* Z80, case sensitivity: Z80-Case. (line 6) 25251* Z80-only directives: Z80 Directives. (line 9) 25252* Z800 addressing modes: Z8000-Addressing. (line 6) 25253* Z8000 directives: Z8000 Directives. (line 6) 25254* Z8000 line comment character: Z8000-Chars. (line 6) 25255* Z8000 line separator: Z8000-Chars. (line 13) 25256* Z8000 opcode summary: Z8000 Opcodes. (line 6) 25257* Z8000 options: Z8000 Options. (line 6) 25258* Z8000 registers: Z8000-Regs. (line 6) 25259* Z8000 support: Z8000-Dependent. (line 6) 25260* zdaoff pseudo-op, V850: V850 Opcodes. (line 99) 25261* zero register, V850: V850-Regs. (line 7) 25262* zero-terminated strings: Asciz. (line 6) 25263 25264 25265 25266Tag Table: 25267Node: Top839 25268Node: Overview1850 25269Node: Manual33933 25270Node: GNU Assembler34877 25271Node: Object Formats36048 25272Node: Command Line36500 25273Node: Input Files37587 25274Node: Object39568 25275Node: Errors40464 25276Node: Invoking41659 25277Node: a43614 25278Node: alternate45525 25279Node: D45697 25280Node: f45930 25281Node: I46438 25282Node: K46982 25283Node: L47286 25284Node: listing48025 25285Node: M49684 25286Node: MD54085 25287Node: o54511 25288Node: R54966 25289Node: statistics55996 25290Node: traditional-format56403 25291Node: v56876 25292Node: W57151 25293Node: Z58058 25294Node: Syntax58580 25295Node: Preprocessing59172 25296Node: Whitespace60735 25297Node: Comments61131 25298Node: Symbol Intro63142 25299Node: Statements63869 25300Node: Constants65858 25301Node: Characters66489 25302Node: Strings66991 25303Node: Chars69157 25304Node: Numbers69911 25305Node: Integers70451 25306Node: Bignums71107 25307Node: Flonums71463 25308Node: Sections73210 25309Node: Secs Background73588 25310Node: Ld Sections78627 25311Node: As Sections81011 25312Node: Sub-Sections81921 25313Node: bss85066 25314Node: Symbols86016 25315Node: Labels86664 25316Node: Setting Symbols87395 25317Node: Symbol Names87949 25318Node: Dot93240 25319Node: Symbol Attributes93687 25320Node: Symbol Value94424 25321Node: Symbol Type95469 25322Node: a.out Symbols95857 25323Node: Symbol Desc96119 25324Node: Symbol Other96414 25325Node: COFF Symbols96583 25326Node: SOM Symbols97256 25327Node: Expressions97698 25328Node: Empty Exprs98447 25329Node: Integer Exprs98794 25330Node: Arguments99189 25331Node: Operators100295 25332Node: Prefix Ops100630 25333Node: Infix Ops100958 25334Node: Pseudo Ops103348 25335Node: Abort108972 25336Node: ABORT (COFF)109384 25337Node: Align109592 25338Node: Altmacro111874 25339Node: Ascii113203 25340Node: Asciz113512 25341Node: Balign113757 25342Node: Bundle directives115633 25343Node: Byte118562 25344Node: CFI directives118823 25345Node: Comm126103 25346Ref: Comm-Footnote-1127704 25347Node: Data128066 25348Node: Def128383 25349Node: Desc128615 25350Node: Dim129115 25351Node: Double129372 25352Node: Eject129710 25353Node: Else129885 25354Node: Elseif130185 25355Node: End130479 25356Node: Endef130694 25357Node: Endfunc130871 25358Node: Endif131046 25359Node: Equ131307 25360Node: Equiv131821 25361Node: Eqv132377 25362Node: Err132741 25363Node: Error133052 25364Node: Exitm133497 25365Node: Extern133666 25366Node: Fail133927 25367Node: File134372 25368Node: Fill135701 25369Node: Float136665 25370Node: Func137007 25371Node: Global137597 25372Node: Gnu_attribute138354 25373Node: Hidden138579 25374Node: hword139165 25375Node: Ident139493 25376Node: If140067 25377Node: Incbin143126 25378Node: Include143821 25379Node: Int144372 25380Node: Internal144753 25381Node: Irp145401 25382Node: Irpc146280 25383Node: Lcomm147197 25384Node: Lflags147945 25385Node: Line148139 25386Node: Linkonce149052 25387Node: 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Type188344 25430Node: Uleb128190657 25431Node: Val190981 25432Node: Version191231 25433Node: VTableEntry191506 25434Node: VTableInherit191796 25435Node: Warning192246 25436Node: Weak192480 25437Node: Weakref193149 25438Node: Word194114 25439Node: Deprecated195960 25440Node: Object Attributes196195 25441Node: GNU Object Attributes197915 25442Node: Defining New Object Attributes200468 25443Node: Machine Dependencies201265 25444Node: AArch64-Dependent205094 25445Node: AArch64 Options205540 25446Node: AArch64 Syntax206172 25447Node: AArch64-Chars206469 25448Node: AArch64-Regs206955 25449Node: AArch64-Relocations207249 25450Node: AArch64 Floating Point208328 25451Node: AArch64 Directives208553 25452Node: AArch64 Opcodes210101 25453Node: AArch64 Mapping Symbols210780 25454Node: Alpha-Dependent211162 25455Node: Alpha Notes211602 25456Node: Alpha Options211883 25457Node: Alpha Syntax214358 25458Node: Alpha-Chars214827 25459Node: Alpha-Regs215239 25460Node: Alpha-Relocs215626 25461Node: Alpha Floating Point221884 25462Node: Alpha Directives222106 25463Node: Alpha Opcodes227629 25464Node: ARC-Dependent227924 25465Node: ARC Options228307 25466Node: ARC Syntax229376 25467Node: ARC-Chars229608 25468Node: ARC-Regs230089 25469Node: ARC Floating Point230213 25470Node: ARC Directives230524 25471Node: ARC Opcodes236489 25472Node: ARM-Dependent236715 25473Node: ARM Options237180 25474Node: ARM Syntax246014 25475Node: ARM-Instruction-Set246382 25476Node: ARM-Chars247602 25477Node: ARM-Regs248313 25478Node: ARM-Relocations248522 25479Node: ARM-Neon-Alignment249656 25480Node: ARM Floating Point250120 25481Node: ARM Directives250319 25482Ref: arm_pad251636 25483Ref: arm_fnend254973 25484Ref: arm_fnstart255297 25485Ref: arm_save258307 25486Ref: arm_setfp259008 25487Node: ARM Opcodes262300 25488Node: ARM Mapping Symbols264388 25489Node: ARM Unwinding Tutorial265198 25490Node: AVR-Dependent271398 25491Node: AVR Options271688 25492Node: AVR Syntax276576 25493Node: AVR-Chars276863 25494Node: AVR-Regs277422 25495Node: AVR-Modifiers278001 25496Node: AVR Opcodes280061 25497Node: Blackfin-Dependent285307 25498Node: Blackfin Options285619 25499Node: Blackfin Syntax286593 25500Node: Blackfin Directives292800 25501Node: CR16-Dependent293546 25502Node: CR16 Operand Qualifiers293846 25503Node: CR16 Syntax296575 25504Node: CR16-Chars296761 25505Node: CRIS-Dependent297298 25506Node: CRIS-Opts297644 25507Ref: march-option299330 25508Node: CRIS-Expand301147 25509Node: CRIS-Symbols302330 25510Node: CRIS-Syntax303499 25511Node: CRIS-Chars303835 25512Node: CRIS-Pic304386 25513Ref: crispic304582 25514Node: CRIS-Regs308122 25515Node: CRIS-Pseudos308539 25516Ref: crisnous309315 25517Node: D10V-Dependent310597 25518Node: D10V-Opts310948 25519Node: D10V-Syntax311910 25520Node: D10V-Size312439 25521Node: D10V-Subs313412 25522Node: D10V-Chars314447 25523Node: D10V-Regs316359 25524Node: D10V-Addressing317404 25525Node: D10V-Word318090 25526Node: D10V-Float318605 25527Node: D10V-Opcodes318916 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25848Node: V850 Syntax737305 25849Node: V850-Chars737545 25850Node: V850-Regs738089 25851Node: V850 Floating Point739657 25852Node: V850 Directives739863 25853Node: V850 Opcodes741930 25854Node: XGATE-Dependent747822 25855Node: XGATE-Opts748242 25856Node: XGATE-Syntax749233 25857Node: XGATE-Directives751312 25858Node: XGATE-Float751551 25859Node: XGATE-opcodes752048 25860Node: XSTORMY16-Dependent752160 25861Node: XStormy16 Syntax752506 25862Node: XStormy16-Chars752696 25863Node: XStormy16 Directives753309 25864Node: XStormy16 Opcodes753964 25865Node: Xtensa-Dependent755020 25866Node: Xtensa Options755754 25867Node: Xtensa Syntax758491 25868Node: Xtensa Opcodes760635 25869Node: Xtensa Registers762429 25870Node: Xtensa Optimizations763062 25871Node: Density Instructions763514 25872Node: Xtensa Automatic Alignment764616 25873Node: Xtensa Relaxation767063 25874Node: Xtensa Branch Relaxation767971 25875Node: Xtensa Call Relaxation769343 25876Node: Xtensa Immediate Relaxation771129 25877Node: Xtensa Directives773703 25878Node: Schedule Directive775412 25879Node: Longcalls Directive775752 25880Node: Transform Directive776296 25881Node: Literal Directive777038 25882Ref: Literal Directive-Footnote-1780577 25883Node: Literal Position Directive780719 25884Node: Literal Prefix Directive782418 25885Node: Absolute Literals Directive783316 25886Node: Reporting Bugs784623 25887Node: Bug Criteria785349 25888Node: Bug Reporting786116 25889Node: Acknowledgements792771 25890Ref: Acknowledgements-Footnote-1797736 25891Node: GNU Free Documentation License797762 25892Node: AS Index822931 25893 25894End Tag Table 25895