1<html><head><meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1"><title>5.5.�Supported Boards for ARM EABI</title><link rel="stylesheet" type="text/css" href="cs.css"><meta name="generator" content="DocBook XSL Stylesheets V1.78.0"><link rel="home" href="index.html" title="Sourcery CodeBench Lite"><link rel="up" href="chap-cs3.html" title="Chapter�5.�CS3™: The CodeSourcery Common Startup Code Sequence"><link rel="prev" href="sec-cs3-interrupts.html" title="5.4.�Interrupt Vectors and Handlers"><link rel="next" href="sec-cs3-vector-tables.html" title="5.6.�Interrupt Vector Tables"></head><body bgcolor="white" text="black" link="#0000FF" vlink="#840084" alink="#0000FF"><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">5.5.�Supported Boards for ARM EABI</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="sec-cs3-interrupts.html">Prev</a>�</td><th width="60%" align="center">Chapter�5.�CS3™: The CodeSourcery Common Startup Code Sequence</th><td width="20%" align="right">�<a accesskey="n" href="sec-cs3-vector-tables.html">Next</a></td></tr></table><hr></div><div class="section"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="sec-cs3-supported-boards"></a>5.5.�Supported Boards for ARM EABI</h2></div></div></div><p>CS3 provides support for the following boards on ARM EABI targets. </p><div class="informaltable"><table border="1" width="100%"><colgroup><col align="left" class="c1"><col align="left" class="c2"><col align="left" class="c3"></colgroup><thead><tr><th colspan="3" align="left">Altera Cyclone III Cortex-M1</th></tr></thead><tbody><tr><td align="left">Processor name:</td><td colspan="2" align="left">Cortex-M1</td></tr><tr><td align="left">Processor options:</td><td colspan="2" align="left"><code class="option">-mcpu=cortex-m1 -mthumb</code></td></tr><tr><td align="left">Memory regions:</td><td colspan="2" align="left"><code class="literal">itcm</code>,<br xmlns:fo="http://www.w3.org/1999/XSL/Format"><code class="literal">ram</code> (SRAM),<br xmlns:fo="http://www.w3.org/1999/XSL/Format"><code class="literal">rom</code> (Flash)</td></tr><tr><td align="left">Interrupt vector:</td><td colspan="2" align="left"><a class="link" href="sec-cs3-vector-tables.html#sec-vector-micro" title="5.6.2.�__cs3_interrupt_vector_micro"><code class="varname">__cs3_interrupt_vector_micro</code></a></td></tr><tr><td rowspan="4" align="left">Linker scripts:</td><td align="left">RAM Hosted</td><td align="left"><code class="filename">cycloneiii-cm1-ram-hosted.ld</code></td></tr><tr><td align="left">RAM Unhosted</td><td align="left"><code class="filename">cycloneiii-cm1-ram.ld</code></td></tr><tr><td align="left">ROM Hosted</td><td align="left"><code class="filename">cycloneiii-cm1-rom-hosted.ld</code></td></tr><tr><td align="left">ROM Unhosted</td><td align="left"><code class="filename">cycloneiii-cm1-rom.ld</code></td></tr></tbody></table></div><div class="informaltable"><table border="1" width="100%"><colgroup><col align="left" class="c1"><col align="left" class="c2"><col align="left" class="c3"></colgroup><thead><tr><th colspan="3" align="left">ARM M-profile Simulator</th></tr></thead><tbody><tr><td align="left">Processor name:</td><td colspan="2" align="left">Cortex-M3</td></tr><tr><td align="left">Processor options:</td><td colspan="2" align="left"><code class="option">-mcpu=cortex-m3 -mthumb</code></td></tr><tr><td align="left">Memory regions:</td><td colspan="2" align="left"><code class="literal">ram</code></td></tr><tr><td align="left">Interrupt vector:</td><td colspan="2" align="left"><a class="link" href="sec-cs3-vector-tables.html#sec-vector-micro" title="5.6.2.�__cs3_interrupt_vector_micro"><code class="varname">__cs3_interrupt_vector_micro</code></a></td></tr><tr><td rowspan="2" align="left">Linker scripts:</td><td align="left">Simulator Hosted</td><td align="left"><code class="filename">generic-m-hosted.ld</code></td></tr><tr><td align="left">Simulator Unhosted</td><td align="left"><code class="filename">generic-m.ld</code></td></tr></tbody></table></div><div class="informaltable"><table border="1" width="100%"><colgroup><col align="left" class="c1"><col align="left" class="c2"><col align="left" class="c3"></colgroup><thead><tr><th colspan="3" align="left">ARM Simulator</th></tr></thead><tbody><tr><td align="left">Processor name:</td><td colspan="2" align="left">unspecified</td></tr><tr><td align="left">Processor options:</td><td colspan="2" align="left">none</td></tr><tr><td align="left">Memory regions:</td><td colspan="2" align="left"><code class="literal">ram</code></td></tr><tr><td align="left">Interrupt vector:</td><td colspan="2" align="left"><a class="link" href="sec-cs3-vector-tables.html#sec-vector-arm" title="5.6.1.�__cs3_interrupt_vector_arm"><code class="varname">__cs3_interrupt_vector_arm</code></a></td></tr><tr><td rowspan="2" align="left">Linker scripts:</td><td align="left">Simulator Hosted</td><td align="left"><code class="filename">generic-hosted.ld</code></td></tr><tr><td align="left">Simulator Unhosted</td><td align="left"><code class="filename">generic.ld</code></td></tr></tbody></table></div><div class="informaltable"><table border="1" width="100%"><colgroup><col align="left" class="c1"><col align="left" class="c2"><col align="left" class="c3"></colgroup><thead><tr><th colspan="3" align="left">ARM Simulator (VFP)</th></tr></thead><tbody><tr><td align="left">Processor name:</td><td colspan="2" align="left">unspecified</td></tr><tr><td align="left">Processor options:</td><td colspan="2" align="left">none</td></tr><tr><td align="left">Memory regions:</td><td colspan="2" align="left"><code class="literal">ram</code></td></tr><tr><td align="left">Interrupt vector:</td><td colspan="2" align="left"><a class="link" href="sec-cs3-vector-tables.html#sec-vector-arm" title="5.6.1.�__cs3_interrupt_vector_arm"><code class="varname">__cs3_interrupt_vector_arm</code></a></td></tr><tr><td rowspan="2" align="left">Linker scripts:</td><td align="left">Simulator Hosted</td><td align="left"><code class="filename">generic-vfp-hosted.ld</code></td></tr><tr><td align="left">Simulator Unhosted</td><td align="left"><code class="filename">generic-vfp.ld</code></td></tr></tbody></table></div><div class="informaltable"><table border="1" width="100%"><colgroup><col align="left" class="c1"><col align="left" class="c2"><col align="left" class="c3"></colgroup><thead><tr><th colspan="3" align="left">ARMulator (RDI)</th></tr></thead><tbody><tr><td align="left">Processor name:</td><td colspan="2" align="left">unspecified</td></tr><tr><td align="left">Processor options:</td><td colspan="2" align="left">none</td></tr><tr><td align="left">Memory regions:</td><td colspan="2" align="left"><code class="literal">ram</code></td></tr><tr><td align="left">Interrupt vector:</td><td colspan="2" align="left"><a class="link" href="sec-cs3-vector-tables.html#sec-vector-arm" title="5.6.1.�__cs3_interrupt_vector_arm"><code class="varname">__cs3_interrupt_vector_arm</code></a></td></tr><tr><td rowspan="2" align="left">Linker scripts:</td><td align="left">RAM Hosted</td><td align="left"><code class="filename">armulator-ram-hosted.ld</code></td></tr><tr><td align="left">RAM Unhosted</td><td align="left"><code class="filename">armulator-ram.ld</code></td></tr></tbody></table></div><div class="informaltable"><table border="1" width="100%"><colgroup><col align="left" class="c1"><col align="left" class="c2"><col align="left" class="c3"></colgroup><thead><tr><th colspan="3" align="left">Xilinx Zynq-7000</th></tr></thead><tbody><tr><td align="left">Processor name:</td><td colspan="2" align="left">Cortex-A9</td></tr><tr><td align="left">Processor options:</td><td colspan="2" align="left"><code class="option">-mcpu=cortex-a9</code></td></tr><tr><td align="left">Memory regions:</td><td colspan="2" align="left"><code class="literal">ram</code> (1024MB DDR SDRAM),<br xmlns:fo="http://www.w3.org/1999/XSL/Format"><code class="literal">rom</code> (64MB NOR Flash Memory)</td></tr><tr><td align="left">Interrupt vector:</td><td colspan="2" align="left"><a class="link" href="sec-cs3-vector-tables.html#sec-vector-arm" title="5.6.1.�__cs3_interrupt_vector_arm"><code class="varname">__cs3_interrupt_vector_arm</code></a></td></tr><tr><td rowspan="4" align="left">Linker scripts:</td><td align="left">RAM Hosted</td><td align="left"><code class="filename">zynq7000-ram-hosted.ld</code></td></tr><tr><td align="left">RAM Unhosted</td><td align="left"><code class="filename">zynq7000-ram.ld</code></td></tr><tr><td align="left">ROM Hosted</td><td align="left"><code class="filename">zynq7000-rom-hosted.ld</code></td></tr><tr><td align="left">ROM Unhosted</td><td align="left"><code class="filename">zynq7000-rom.ld</code></td></tr></tbody></table></div></div><div class="navfooter"><hr><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="sec-cs3-interrupts.html">Prev</a>�</td><td width="20%" align="center"><a accesskey="u" href="chap-cs3.html">Up</a></td><td width="40%" align="right">�<a accesskey="n" href="sec-cs3-vector-tables.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">5.4.�Interrupt Vectors and Handlers�</td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top">�5.6.�Interrupt Vector Tables</td></tr></table></div></body></html> 2