1This is as.info, produced by makeinfo version 4.13 from 2/scratch/jwlemke/2011.09-arm-eabi-lite/obj/binutils-src-2011.09-69-arm-none-eabi-i686-pc-linux-gnu/gas/doc/as.texinfo. 3 4INFO-DIR-SECTION Software development 5START-INFO-DIR-ENTRY 6* As: (as). The GNU assembler. 7* Gas: (as). The GNU assembler. 8END-INFO-DIR-ENTRY 9 10 This file documents the GNU Assembler "as". 11 12 Copyright (C) 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 132000, 2001, 2002, 2006, 2007, 2008, 2009, 2010, 2011 Free Software 14Foundation, Inc. 15 16 Permission is granted to copy, distribute and/or modify this document 17under the terms of the GNU Free Documentation License, Version 1.3 or 18any later version published by the Free Software Foundation; with no 19Invariant Sections, with no Front-Cover Texts, and with no Back-Cover 20Texts. A copy of the license is included in the section entitled "GNU 21Free Documentation License". 22 23 24File: as.info, Node: Top, Next: Overview, Up: (dir) 25 26Using as 27******** 28 29This file is a user guide to the GNU assembler `as' (Sourcery CodeBench 30Lite 2011.09-69) version 2.21.53. 31 32 This document is distributed under the terms of the GNU Free 33Documentation License. A copy of the license is included in the 34section entitled "GNU Free Documentation License". 35 36* Menu: 37 38* Overview:: Overview 39* Invoking:: Command-Line Options 40* Syntax:: Syntax 41* Sections:: Sections and Relocation 42* Symbols:: Symbols 43* Expressions:: Expressions 44* Pseudo Ops:: Assembler Directives 45 46* Object Attributes:: Object Attributes 47* Machine Dependencies:: Machine Dependent Features 48* Reporting Bugs:: Reporting Bugs 49* Acknowledgements:: Who Did What 50* GNU Free Documentation License:: GNU Free Documentation License 51* AS Index:: AS Index 52 53 54File: as.info, Node: Overview, Next: Invoking, Prev: Top, Up: Top 55 561 Overview 57********** 58 59Here is a brief summary of how to invoke `as'. For details, see *note 60Command-Line Options: Invoking. 61 62 as [-a[cdghlns][=FILE]] [-alternate] [-D] 63 [-compress-debug-sections] [-nocompress-debug-sections] 64 [-debug-prefix-map OLD=NEW] 65 [-defsym SYM=VAL] [-f] [-g] [-gstabs] 66 [-gstabs+] [-gdwarf-2] [-help] [-I DIR] [-J] 67 [-K] [-L] [-listing-lhs-width=NUM] 68 [-listing-lhs-width2=NUM] [-listing-rhs-width=NUM] 69 [-listing-cont-lines=NUM] [-keep-locals] [-o 70 OBJFILE] [-R] [-reduce-memory-overheads] [-statistics] 71 [-v] [-version] [-version] [-W] [-warn] 72 [-fatal-warnings] [-w] [-x] [-Z] [@FILE] 73 [-size-check=[error|warning]] 74 [-target-help] [TARGET-OPTIONS] 75 [-|FILES ...] 76 77 _Target Alpha options:_ 78 [-mCPU] 79 [-mdebug | -no-mdebug] 80 [-replace | -noreplace] 81 [-relax] [-g] [-GSIZE] 82 [-F] [-32addr] 83 84 _Target ARC options:_ 85 [-marc[5|6|7|8]] 86 [-EB|-EL] 87 88 _Target ARM options:_ 89 [-mcpu=PROCESSOR[+EXTENSION...]] 90 [-march=ARCHITECTURE[+EXTENSION...]] 91 [-mfpu=FLOATING-POINT-FORMAT] 92 [-mfloat-abi=ABI] 93 [-meabi=VER] 94 [-mthumb] 95 [-EB|-EL] 96 [-mapcs-32|-mapcs-26|-mapcs-float| 97 -mapcs-reentrant] 98 [-mthumb-interwork] [-k] 99 100 _Target Blackfin options:_ 101 [-mcpu=PROCESSOR[-SIREVISION]] 102 [-mfdpic] 103 [-mno-fdpic] 104 [-mnopic] 105 106 _Target CRIS options:_ 107 [-underscore | -no-underscore] 108 [-pic] [-N] 109 [-emulation=criself | -emulation=crisaout] 110 [-march=v0_v10 | -march=v10 | -march=v32 | -march=common_v10_v32] 111 112 _Target D10V options:_ 113 [-O] 114 115 _Target D30V options:_ 116 [-O|-n|-N] 117 118 _Target H8/300 options:_ 119 [-h-tick-hex] 120 121 _Target i386 options:_ 122 [-32|-n32|-64] [-n] 123 [-march=CPU[+EXTENSION...]] [-mtune=CPU] 124 125 _Target i960 options:_ 126 [-ACA|-ACA_A|-ACB|-ACC|-AKA|-AKB| 127 -AKC|-AMC] 128 [-b] [-no-relax] 129 130 _Target IA-64 options:_ 131 [-mconstant-gp|-mauto-pic] 132 [-milp32|-milp64|-mlp64|-mp64] 133 [-mle|mbe] 134 [-mtune=itanium1|-mtune=itanium2] 135 [-munwind-check=warning|-munwind-check=error] 136 [-mhint.b=ok|-mhint.b=warning|-mhint.b=error] 137 [-x|-xexplicit] [-xauto] [-xdebug] 138 139 _Target IP2K options:_ 140 [-mip2022|-mip2022ext] 141 142 _Target M32C options:_ 143 [-m32c|-m16c] [-relax] [-h-tick-hex] 144 145 _Target M32R options:_ 146 [-m32rx|-[no-]warn-explicit-parallel-conflicts| 147 -W[n]p] 148 149 _Target M680X0 options:_ 150 [-l] [-m68000|-m68010|-m68020|...] 151 152 _Target M68HC11 options:_ 153 [-m68hc11|-m68hc12|-m68hcs12] 154 [-mshort|-mlong] 155 [-mshort-double|-mlong-double] 156 [-force-long-branches] [-short-branches] 157 [-strict-direct-mode] [-print-insn-syntax] 158 [-print-opcodes] [-generate-example] 159 160 _Target MCORE options:_ 161 [-jsri2bsr] [-sifilter] [-relax] 162 [-mcpu=[210|340]] 163 _Target MICROBLAZE options:_ 164 165 _Target MIPS options:_ 166 [-nocpp] [-EL] [-EB] [-O[OPTIMIZATION LEVEL]] 167 [-g[DEBUG LEVEL]] [-G NUM] [-KPIC] [-call_shared] 168 [-non_shared] [-xgot [-mvxworks-pic] 169 [-mabi=ABI] [-32] [-n32] [-64] [-mfp32] [-mgp32] 170 [-march=CPU] [-mtune=CPU] [-mips1] [-mips2] 171 [-mips3] [-mips4] [-mips5] [-mips32] [-mips32r2] 172 [-mips64] [-mips64r2] 173 [-construct-floats] [-no-construct-floats] 174 [-trap] [-no-break] [-break] [-no-trap] 175 [-mips16] [-no-mips16] 176 [-mmicromips] [-mno-micromips] 177 [-msmartmips] [-mno-smartmips] 178 [-mips3d] [-no-mips3d] 179 [-mdmx] [-no-mdmx] 180 [-mdsp] [-mno-dsp] 181 [-mdspr2] [-mno-dspr2] 182 [-mmt] [-mno-mt] 183 [-mmcu] [-mno-mcu] 184 [-minsn32] [-mno-insn32] 185 [-mfix7000] [-mno-fix7000] 186 [-mfix-vr4120] [-mno-fix-vr4120] 187 [-mfix-vr4130] [-mno-fix-vr4130] 188 [-mdebug] [-no-mdebug] 189 [-mpdr] [-mno-pdr] 190 191 _Target MMIX options:_ 192 [-fixed-special-register-names] [-globalize-symbols] 193 [-gnu-syntax] [-relax] [-no-predefined-symbols] 194 [-no-expand] [-no-merge-gregs] [-x] 195 [-linker-allocated-gregs] 196 197 _Target PDP11 options:_ 198 [-mpic|-mno-pic] [-mall] [-mno-extensions] 199 [-mEXTENSION|-mno-EXTENSION] 200 [-mCPU] [-mMACHINE] 201 202 _Target picoJava options:_ 203 [-mb|-me] 204 205 _Target PowerPC options:_ 206 [-a32|-a64] 207 [-mpwrx|-mpwr2|-mpwr|-m601|-mppc|-mppc32|-m603|-m604|-m403|-m405| 208 -m440|-m464|-m476|-m7400|-m7410|-m7450|-m7455|-m750cl|-mppc64| 209 -m620|-me500|-e500x2|-me500mc|-me500mc64|-mppc64bridge|-mbooke| 210 -mpower4|-mpr4|-mpower5|-mpwr5|-mpwr5x|-mpower6|-mpwr6| 211 -mpower7|-mpw7|-ma2|-mcell|-mspe|-mtitan|-me300|-mcom] 212 [-many] [-maltivec|-mvsx] 213 [-mregnames|-mno-regnames] 214 [-mrelocatable|-mrelocatable-lib|-K PIC] [-memb] 215 [-mlittle|-mlittle-endian|-le|-mbig|-mbig-endian|-be] 216 [-msolaris|-mno-solaris] 217 [-nops=COUNT] 218 219 _Target RX options:_ 220 [-mlittle-endian|-mbig-endian] 221 [-m32bit-ints|-m16bit-ints] 222 [-m32bit-doubles|-m64bit-doubles] 223 224 _Target s390 options:_ 225 [-m31|-m64] [-mesa|-mzarch] [-march=CPU] 226 [-mregnames|-mno-regnames] 227 [-mwarn-areg-zero] 228 229 _Target SCORE options:_ 230 [-EB][-EL][-FIXDD][-NWARN] 231 [-SCORE5][-SCORE5U][-SCORE7][-SCORE3] 232 [-march=score7][-march=score3] 233 [-USE_R1][-KPIC][-O0][-G NUM][-V] 234 235 _Target SPARC options:_ 236 [-Av6|-Av7|-Av8|-Asparclet|-Asparclite 237 -Av8plus|-Av8plusa|-Av9|-Av9a] 238 [-xarch=v8plus|-xarch=v8plusa] [-bump] 239 [-32|-64] 240 241 _Target TIC54X options:_ 242 [-mcpu=54[123589]|-mcpu=54[56]lp] [-mfar-mode|-mf] 243 [-merrors-to-file <FILENAME>|-me <FILENAME>] 244 245 246 _Target TIC6X options:_ 247 [-march=ARCH] [-mbig-endian|-mlittle-endian] 248 [-mdsbt|-mno-dsbt] [-mpid=no|-mpid=near|-mpid=far] 249 [-mpic|-mno-pic] 250 251 _Target TILE-Gx options:_ 252 [-m32|-m64] 253 254 255 _Target Xtensa options:_ 256 [-[no-]text-section-literals] [-[no-]absolute-literals] 257 [-[no-]target-align] [-[no-]longcalls] 258 [-[no-]transform] 259 [-rename-section OLDNAME=NEWNAME] 260 261 262 _Target Z80 options:_ 263 [-z80] [-r800] 264 [ -ignore-undocumented-instructions] [-Wnud] 265 [ -ignore-unportable-instructions] [-Wnup] 266 [ -warn-undocumented-instructions] [-Wud] 267 [ -warn-unportable-instructions] [-Wup] 268 [ -forbid-undocumented-instructions] [-Fud] 269 [ -forbid-unportable-instructions] [-Fup] 270 271`@FILE' 272 Read command-line options from FILE. The options read are 273 inserted in place of the original @FILE option. If FILE does not 274 exist, or cannot be read, then the option will be treated 275 literally, and not removed. 276 277 Options in FILE are separated by whitespace. A whitespace 278 character may be included in an option by surrounding the entire 279 option in either single or double quotes. Any character 280 (including a backslash) may be included by prefixing the character 281 to be included with a backslash. The FILE may itself contain 282 additional @FILE options; any such options will be processed 283 recursively. 284 285`-a[cdghlmns]' 286 Turn on listings, in any of a variety of ways: 287 288 `-ac' 289 omit false conditionals 290 291 `-ad' 292 omit debugging directives 293 294 `-ag' 295 include general information, like as version and options 296 passed 297 298 `-ah' 299 include high-level source 300 301 `-al' 302 include assembly 303 304 `-am' 305 include macro expansions 306 307 `-an' 308 omit forms processing 309 310 `-as' 311 include symbols 312 313 `=file' 314 set the name of the listing file 315 316 You may combine these options; for example, use `-aln' for assembly 317 listing without forms processing. The `=file' option, if used, 318 must be the last one. By itself, `-a' defaults to `-ahls'. 319 320`--alternate' 321 Begin in alternate macro mode. *Note `.altmacro': Altmacro. 322 323`--compress-debug-sections' 324 Compress DWARF debug sections using zlib. The debug sections are 325 renamed to begin with `.zdebug', and the resulting object file may 326 not be compatible with older linkers and object file utilities. 327 328`--nocompress-debug-sections' 329 Do not compress DWARF debug sections. This is the default. 330 331`-D' 332 Ignored. This option is accepted for script compatibility with 333 calls to other assemblers. 334 335`--debug-prefix-map OLD=NEW' 336 When assembling files in directory `OLD', record debugging 337 information describing them as in `NEW' instead. 338 339`--defsym SYM=VALUE' 340 Define the symbol SYM to be VALUE before assembling the input file. 341 VALUE must be an integer constant. As in C, a leading `0x' 342 indicates a hexadecimal value, and a leading `0' indicates an octal 343 value. The value of the symbol can be overridden inside a source 344 file via the use of a `.set' pseudo-op. 345 346`-f' 347 "fast"--skip whitespace and comment preprocessing (assume source is 348 compiler output). 349 350`-g' 351`--gen-debug' 352 Generate debugging information for each assembler source line 353 using whichever debug format is preferred by the target. This 354 currently means either STABS, ECOFF or DWARF2. 355 356`--gstabs' 357 Generate stabs debugging information for each assembler line. This 358 may help debugging assembler code, if the debugger can handle it. 359 360`--gstabs+' 361 Generate stabs debugging information for each assembler line, with 362 GNU extensions that probably only gdb can handle, and that could 363 make other debuggers crash or refuse to read your program. This 364 may help debugging assembler code. Currently the only GNU 365 extension is the location of the current working directory at 366 assembling time. 367 368`--gdwarf-2' 369 Generate DWARF2 debugging information for each assembler line. 370 This may help debugging assembler code, if the debugger can handle 371 it. Note--this option is only supported by some targets, not all 372 of them. 373 374`--size-check=error' 375`--size-check=warning' 376 Issue an error or warning for invalid ELF .size directive. 377 378`--help' 379 Print a summary of the command line options and exit. 380 381`--target-help' 382 Print a summary of all target specific options and exit. 383 384`-I DIR' 385 Add directory DIR to the search list for `.include' directives. 386 387`-J' 388 Don't warn about signed overflow. 389 390`-K' 391 Issue warnings when difference tables altered for long 392 displacements. 393 394`-L' 395`--keep-locals' 396 Keep (in the symbol table) local symbols. These symbols start with 397 system-specific local label prefixes, typically `.L' for ELF 398 systems or `L' for traditional a.out systems. *Note Symbol 399 Names::. 400 401`--listing-lhs-width=NUMBER' 402 Set the maximum width, in words, of the output data column for an 403 assembler listing to NUMBER. 404 405`--listing-lhs-width2=NUMBER' 406 Set the maximum width, in words, of the output data column for 407 continuation lines in an assembler listing to NUMBER. 408 409`--listing-rhs-width=NUMBER' 410 Set the maximum width of an input source line, as displayed in a 411 listing, to NUMBER bytes. 412 413`--listing-cont-lines=NUMBER' 414 Set the maximum number of lines printed in a listing for a single 415 line of input to NUMBER + 1. 416 417`-o OBJFILE' 418 Name the object-file output from `as' OBJFILE. 419 420`-R' 421 Fold the data section into the text section. 422 423 Set the default size of GAS's hash tables to a prime number close 424 to NUMBER. Increasing this value can reduce the length of time it 425 takes the assembler to perform its tasks, at the expense of 426 increasing the assembler's memory requirements. Similarly 427 reducing this value can reduce the memory requirements at the 428 expense of speed. 429 430`--reduce-memory-overheads' 431 This option reduces GAS's memory requirements, at the expense of 432 making the assembly processes slower. Currently this switch is a 433 synonym for `--hash-size=4051', but in the future it may have 434 other effects as well. 435 436`--statistics' 437 Print the maximum space (in bytes) and total time (in seconds) 438 used by assembly. 439 440`--strip-local-absolute' 441 Remove local absolute symbols from the outgoing symbol table. 442 443`-v' 444`-version' 445 Print the `as' version. 446 447`--version' 448 Print the `as' version and exit. 449 450`-W' 451`--no-warn' 452 Suppress warning messages. 453 454`--fatal-warnings' 455 Treat warnings as errors. 456 457`--warn' 458 Don't suppress warning messages or treat them as errors. 459 460`-w' 461 Ignored. 462 463`-x' 464 Ignored. 465 466`-Z' 467 Generate an object file even after errors. 468 469`-- | FILES ...' 470 Standard input, or source files to assemble. 471 472 473 *Note Alpha Options::, for the options available when as is 474configured for an Alpha processor. 475 476 The following options are available when as is configured for an ARC 477processor. 478 479`-marc[5|6|7|8]' 480 This option selects the core processor variant. 481 482`-EB | -EL' 483 Select either big-endian (-EB) or little-endian (-EL) output. 484 485 The following options are available when as is configured for the ARM 486processor family. 487 488`-mcpu=PROCESSOR[+EXTENSION...]' 489 Specify which ARM processor variant is the target. 490 491`-march=ARCHITECTURE[+EXTENSION...]' 492 Specify which ARM architecture variant is used by the target. 493 494`-mfpu=FLOATING-POINT-FORMAT' 495 Select which Floating Point architecture is the target. 496 497`-mfloat-abi=ABI' 498 Select which floating point ABI is in use. 499 500`-mthumb' 501 Enable Thumb only instruction decoding. 502 503`-mapcs-32 | -mapcs-26 | -mapcs-float | -mapcs-reentrant' 504 Select which procedure calling convention is in use. 505 506`-EB | -EL' 507 Select either big-endian (-EB) or little-endian (-EL) output. 508 509`-mthumb-interwork' 510 Specify that the code has been generated with interworking between 511 Thumb and ARM code in mind. 512 513`-k' 514 Specify that PIC code has been generated. 515 516 *Note Blackfin Options::, for the options available when as is 517configured for the Blackfin processor family. 518 519 See the info pages for documentation of the CRIS-specific options. 520 521 The following options are available when as is configured for a D10V 522processor. 523`-O' 524 Optimize output by parallelizing instructions. 525 526 The following options are available when as is configured for a D30V 527processor. 528`-O' 529 Optimize output by parallelizing instructions. 530 531`-n' 532 Warn when nops are generated. 533 534`-N' 535 Warn when a nop after a 32-bit multiply instruction is generated. 536 537 *Note i386-Options::, for the options available when as is 538configured for an i386 processor. 539 540 The following options are available when as is configured for the 541Intel 80960 processor. 542 543`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' 544 Specify which variant of the 960 architecture is the target. 545 546`-b' 547 Add code to collect statistics about branches taken. 548 549`-no-relax' 550 Do not alter compare-and-branch instructions for long 551 displacements; error if necessary. 552 553 554 The following options are available when as is configured for the 555Ubicom IP2K series. 556 557`-mip2022ext' 558 Specifies that the extended IP2022 instructions are allowed. 559 560`-mip2022' 561 Restores the default behaviour, which restricts the permitted 562 instructions to just the basic IP2022 ones. 563 564 565 The following options are available when as is configured for the 566Renesas M32C and M16C processors. 567 568`-m32c' 569 Assemble M32C instructions. 570 571`-m16c' 572 Assemble M16C instructions (the default). 573 574`-relax' 575 Enable support for link-time relaxations. 576 577`-h-tick-hex' 578 Support H'00 style hex constants in addition to 0x00 style. 579 580 581 The following options are available when as is configured for the 582Renesas M32R (formerly Mitsubishi M32R) series. 583 584`--m32rx' 585 Specify which processor in the M32R family is the target. The 586 default is normally the M32R, but this option changes it to the 587 M32RX. 588 589`--warn-explicit-parallel-conflicts or --Wp' 590 Produce warning messages when questionable parallel constructs are 591 encountered. 592 593`--no-warn-explicit-parallel-conflicts or --Wnp' 594 Do not produce warning messages when questionable parallel 595 constructs are encountered. 596 597 598 The following options are available when as is configured for the 599Motorola 68000 series. 600 601`-l' 602 Shorten references to undefined symbols, to one word instead of 603 two. 604 605`-m68000 | -m68008 | -m68010 | -m68020 | -m68030' 606`| -m68040 | -m68060 | -m68302 | -m68331 | -m68332' 607`| -m68333 | -m68340 | -mcpu32 | -m5200' 608 Specify what processor in the 68000 family is the target. The 609 default is normally the 68020, but this can be changed at 610 configuration time. 611 612`-m68881 | -m68882 | -mno-68881 | -mno-68882' 613 The target machine does (or does not) have a floating-point 614 coprocessor. The default is to assume a coprocessor for 68020, 615 68030, and cpu32. Although the basic 68000 is not compatible with 616 the 68881, a combination of the two can be specified, since it's 617 possible to do emulation of the coprocessor instructions with the 618 main processor. 619 620`-m68851 | -mno-68851' 621 The target machine does (or does not) have a memory-management 622 unit coprocessor. The default is to assume an MMU for 68020 and 623 up. 624 625 626 For details about the PDP-11 machine dependent features options, see 627*note PDP-11-Options::. 628 629`-mpic | -mno-pic' 630 Generate position-independent (or position-dependent) code. The 631 default is `-mpic'. 632 633`-mall' 634`-mall-extensions' 635 Enable all instruction set extensions. This is the default. 636 637`-mno-extensions' 638 Disable all instruction set extensions. 639 640`-mEXTENSION | -mno-EXTENSION' 641 Enable (or disable) a particular instruction set extension. 642 643`-mCPU' 644 Enable the instruction set extensions supported by a particular 645 CPU, and disable all other extensions. 646 647`-mMACHINE' 648 Enable the instruction set extensions supported by a particular 649 machine model, and disable all other extensions. 650 651 The following options are available when as is configured for a 652picoJava processor. 653 654`-mb' 655 Generate "big endian" format output. 656 657`-ml' 658 Generate "little endian" format output. 659 660 661 The following options are available when as is configured for the 662Motorola 68HC11 or 68HC12 series. 663 664`-m68hc11 | -m68hc12 | -m68hcs12' 665 Specify what processor is the target. The default is defined by 666 the configuration option when building the assembler. 667 668`-mshort' 669 Specify to use the 16-bit integer ABI. 670 671`-mlong' 672 Specify to use the 32-bit integer ABI. 673 674`-mshort-double' 675 Specify to use the 32-bit double ABI. 676 677`-mlong-double' 678 Specify to use the 64-bit double ABI. 679 680`--force-long-branches' 681 Relative branches are turned into absolute ones. This concerns 682 conditional branches, unconditional branches and branches to a sub 683 routine. 684 685`-S | --short-branches' 686 Do not turn relative branches into absolute ones when the offset 687 is out of range. 688 689`--strict-direct-mode' 690 Do not turn the direct addressing mode into extended addressing 691 mode when the instruction does not support direct addressing mode. 692 693`--print-insn-syntax' 694 Print the syntax of instruction in case of error. 695 696`--print-opcodes' 697 print the list of instructions with syntax and then exit. 698 699`--generate-example' 700 print an example of instruction for each possible instruction and 701 then exit. This option is only useful for testing `as'. 702 703 704 The following options are available when `as' is configured for the 705SPARC architecture: 706 707`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' 708`-Av8plus | -Av8plusa | -Av9 | -Av9a' 709 Explicitly select a variant of the SPARC architecture. 710 711 `-Av8plus' and `-Av8plusa' select a 32 bit environment. `-Av9' 712 and `-Av9a' select a 64 bit environment. 713 714 `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with 715 UltraSPARC extensions. 716 717`-xarch=v8plus | -xarch=v8plusa' 718 For compatibility with the Solaris v9 assembler. These options are 719 equivalent to -Av8plus and -Av8plusa, respectively. 720 721`-bump' 722 Warn when the assembler switches to another architecture. 723 724 The following options are available when as is configured for the 725'c54x architecture. 726 727`-mfar-mode' 728 Enable extended addressing mode. All addresses and relocations 729 will assume extended addressing (usually 23 bits). 730 731`-mcpu=CPU_VERSION' 732 Sets the CPU version being compiled for. 733 734`-merrors-to-file FILENAME' 735 Redirect error output to a file, for broken systems which don't 736 support such behaviour in the shell. 737 738 The following options are available when as is configured for a MIPS 739processor. 740 741`-G NUM' 742 This option sets the largest size of an object that can be 743 referenced implicitly with the `gp' register. It is only accepted 744 for targets that use ECOFF format, such as a DECstation running 745 Ultrix. The default value is 8. 746 747`-EB' 748 Generate "big endian" format output. 749 750`-EL' 751 Generate "little endian" format output. 752 753`-mips1' 754`-mips2' 755`-mips3' 756`-mips4' 757`-mips5' 758`-mips32' 759`-mips32r2' 760`-mips64' 761`-mips64r2' 762 Generate code for a particular MIPS Instruction Set Architecture 763 level. `-mips1' is an alias for `-march=r3000', `-mips2' is an 764 alias for `-march=r6000', `-mips3' is an alias for `-march=r4000' 765 and `-mips4' is an alias for `-march=r8000'. `-mips5', `-mips32', 766 `-mips32r2', `-mips64', and `-mips64r2' correspond to generic 767 `MIPS V', `MIPS32', `MIPS32 Release 2', `MIPS64', and `MIPS64 768 Release 2' ISA processors, respectively. 769 770`-march=CPU' 771 Generate code for a particular MIPS cpu. 772 773`-mtune=CPU' 774 Schedule and tune for a particular MIPS cpu. 775 776`-mfix7000' 777`-mno-fix7000' 778 Cause nops to be inserted if the read of the destination register 779 of an mfhi or mflo instruction occurs in the following two 780 instructions. 781 782`-mdebug' 783`-no-mdebug' 784 Cause stabs-style debugging output to go into an ECOFF-style 785 .mdebug section instead of the standard ELF .stabs sections. 786 787`-mpdr' 788`-mno-pdr' 789 Control generation of `.pdr' sections. 790 791`-mgp32' 792`-mfp32' 793 The register sizes are normally inferred from the ISA and ABI, but 794 these flags force a certain group of registers to be treated as 32 795 bits wide at all times. `-mgp32' controls the size of 796 general-purpose registers and `-mfp32' controls the size of 797 floating-point registers. 798 799`-mips16' 800`-no-mips16' 801 Generate code for the MIPS 16 processor. This is equivalent to 802 putting `.set mips16' at the start of the assembly file. 803 `-no-mips16' turns off this option. 804 805`-mmicromips' 806`-mno-micromips' 807 Generate code for the microMIPS processor. This is equivalent to 808 putting `.set micromips' at the start of the assembly file. 809 `-mno-micromips' turns off this option. This is equivalent to 810 putting `.set nomicromips' at the start of the assembly file. 811 812`-msmartmips' 813`-mno-smartmips' 814 Enables the SmartMIPS extension to the MIPS32 instruction set. 815 This is equivalent to putting `.set smartmips' at the start of the 816 assembly file. `-mno-smartmips' turns off this option. 817 818`-mips3d' 819`-no-mips3d' 820 Generate code for the MIPS-3D Application Specific Extension. 821 This tells the assembler to accept MIPS-3D instructions. 822 `-no-mips3d' turns off this option. 823 824`-mdmx' 825`-no-mdmx' 826 Generate code for the MDMX Application Specific Extension. This 827 tells the assembler to accept MDMX instructions. `-no-mdmx' turns 828 off this option. 829 830`-mdsp' 831`-mno-dsp' 832 Generate code for the DSP Release 1 Application Specific Extension. 833 This tells the assembler to accept DSP Release 1 instructions. 834 `-mno-dsp' turns off this option. 835 836`-mdspr2' 837`-mno-dspr2' 838 Generate code for the DSP Release 2 Application Specific Extension. 839 This option implies -mdsp. This tells the assembler to accept DSP 840 Release 2 instructions. `-mno-dspr2' turns off this option. 841 842`-mmt' 843`-mno-mt' 844 Generate code for the MT Application Specific Extension. This 845 tells the assembler to accept MT instructions. `-mno-mt' turns 846 off this option. 847 848`-mmcu' 849`-mno-mcu' 850 Generate code for the MCU Application Specific Extension. This 851 tells the assembler to accept MCU instructions. `-mno-mcu' turns 852 off this option. 853 854`-minsn32' 855`-mno-insn32' 856 Only use 32-bit instruction encodings when generating code for the 857 microMIPS processor. This option inhibits the use of any 16-bit 858 instructions. This is equivalent to putting `.set insn32' at the 859 start of the assembly file. `-mno-insn32' turns off this option. 860 This is equivalent to putting `.set noinsn32' at the start of the 861 assembly file. By default `-mno-insn32' is selected, allowing all 862 instructions to be used. 863 864`--construct-floats' 865`--no-construct-floats' 866 The `--no-construct-floats' option disables the construction of 867 double width floating point constants by loading the two halves of 868 the value into the two single width floating point registers that 869 make up the double width register. By default 870 `--construct-floats' is selected, allowing construction of these 871 floating point constants. 872 873`--emulation=NAME' 874 This option causes `as' to emulate `as' configured for some other 875 target, in all respects, including output format (choosing between 876 ELF and ECOFF only), handling of pseudo-opcodes which may generate 877 debugging information or store symbol table information, and 878 default endianness. The available configuration names are: 879 `mipsecoff', `mipself', `mipslecoff', `mipsbecoff', `mipslelf', 880 `mipsbelf'. The first two do not alter the default endianness 881 from that of the primary target for which the assembler was 882 configured; the others change the default to little- or big-endian 883 as indicated by the `b' or `l' in the name. Using `-EB' or `-EL' 884 will override the endianness selection in any case. 885 886 This option is currently supported only when the primary target 887 `as' is configured for is a MIPS ELF or ECOFF target. 888 Furthermore, the primary target or others specified with 889 `--enable-targets=...' at configuration time must include support 890 for the other format, if both are to be available. For example, 891 the Irix 5 configuration includes support for both. 892 893 Eventually, this option will support more configurations, with more 894 fine-grained control over the assembler's behavior, and will be 895 supported for more processors. 896 897`-nocpp' 898 `as' ignores this option. It is accepted for compatibility with 899 the native tools. 900 901`--trap' 902`--no-trap' 903`--break' 904`--no-break' 905 Control how to deal with multiplication overflow and division by 906 zero. `--trap' or `--no-break' (which are synonyms) take a trap 907 exception (and only work for Instruction Set Architecture level 2 908 and higher); `--break' or `--no-trap' (also synonyms, and the 909 default) take a break exception. 910 911`-n' 912 When this option is used, `as' will issue a warning every time it 913 generates a nop instruction from a macro. 914 915 The following options are available when as is configured for an 916MCore processor. 917 918`-jsri2bsr' 919`-nojsri2bsr' 920 Enable or disable the JSRI to BSR transformation. By default this 921 is enabled. The command line option `-nojsri2bsr' can be used to 922 disable it. 923 924`-sifilter' 925`-nosifilter' 926 Enable or disable the silicon filter behaviour. By default this 927 is disabled. The default can be overridden by the `-sifilter' 928 command line option. 929 930`-relax' 931 Alter jump instructions for long displacements. 932 933`-mcpu=[210|340]' 934 Select the cpu type on the target hardware. This controls which 935 instructions can be assembled. 936 937`-EB' 938 Assemble for a big endian target. 939 940`-EL' 941 Assemble for a little endian target. 942 943 944 See the info pages for documentation of the MMIX-specific options. 945 946 *Note PowerPC-Opts::, for the options available when as is configured 947for a PowerPC processor. 948 949 See the info pages for documentation of the RX-specific options. 950 951 The following options are available when as is configured for the 952s390 processor family. 953 954`-m31' 955`-m64' 956 Select the word size, either 31/32 bits or 64 bits. 957 958`-mesa' 959 960`-mzarch' 961 Select the architecture mode, either the Enterprise System 962 Architecture (esa) or the z/Architecture mode (zarch). 963 964`-march=PROCESSOR' 965 Specify which s390 processor variant is the target, `g6', `g6', 966 `z900', `z990', `z9-109', `z9-ec', or `z10'. 967 968`-mregnames' 969`-mno-regnames' 970 Allow or disallow symbolic names for registers. 971 972`-mwarn-areg-zero' 973 Warn whenever the operand for a base or index register has been 974 specified but evaluates to zero. 975 976 *Note TIC6X Options::, for the options available when as is 977configured for a TMS320C6000 processor. 978 979 *Note TILE-Gx Options::, for the options available when as is 980configured for a TILE-Gx processor. 981 982 *Note Xtensa Options::, for the options available when as is 983configured for an Xtensa processor. 984 985 The following options are available when as is configured for a Z80 986family processor. 987`-z80' 988 Assemble for Z80 processor. 989 990`-r800' 991 Assemble for R800 processor. 992 993`-ignore-undocumented-instructions' 994`-Wnud' 995 Assemble undocumented Z80 instructions that also work on R800 996 without warning. 997 998`-ignore-unportable-instructions' 999`-Wnup' 1000 Assemble all undocumented Z80 instructions without warning. 1001 1002`-warn-undocumented-instructions' 1003`-Wud' 1004 Issue a warning for undocumented Z80 instructions that also work 1005 on R800. 1006 1007`-warn-unportable-instructions' 1008`-Wup' 1009 Issue a warning for undocumented Z80 instructions that do not work 1010 on R800. 1011 1012`-forbid-undocumented-instructions' 1013`-Fud' 1014 Treat all undocumented instructions as errors. 1015 1016`-forbid-unportable-instructions' 1017`-Fup' 1018 Treat undocumented Z80 instructions that do not work on R800 as 1019 errors. 1020 1021* Menu: 1022 1023* Manual:: Structure of this Manual 1024* GNU Assembler:: The GNU Assembler 1025* Object Formats:: Object File Formats 1026* Command Line:: Command Line 1027* Input Files:: Input Files 1028* Object:: Output (Object) File 1029* Errors:: Error and Warning Messages 1030 1031 1032File: as.info, Node: Manual, Next: GNU Assembler, Up: Overview 1033 10341.1 Structure of this Manual 1035============================ 1036 1037This manual is intended to describe what you need to know to use GNU 1038`as'. We cover the syntax expected in source files, including notation 1039for symbols, constants, and expressions; the directives that `as' 1040understands; and of course how to invoke `as'. 1041 1042 This manual also describes some of the machine-dependent features of 1043various flavors of the assembler. 1044 1045 On the other hand, this manual is _not_ intended as an introduction 1046to programming in assembly language--let alone programming in general! 1047In a similar vein, we make no attempt to introduce the machine 1048architecture; we do _not_ describe the instruction set, standard 1049mnemonics, registers or addressing modes that are standard to a 1050particular architecture. You may want to consult the manufacturer's 1051machine architecture manual for this information. 1052 1053 1054File: as.info, Node: GNU Assembler, Next: Object Formats, Prev: Manual, Up: Overview 1055 10561.2 The GNU Assembler 1057===================== 1058 1059GNU `as' is really a family of assemblers. If you use (or have used) 1060the GNU assembler on one architecture, you should find a fairly similar 1061environment when you use it on another architecture. Each version has 1062much in common with the others, including object file formats, most 1063assembler directives (often called "pseudo-ops") and assembler syntax. 1064 1065 `as' is primarily intended to assemble the output of the GNU C 1066compiler `gcc' for use by the linker `ld'. Nevertheless, we've tried 1067to make `as' assemble correctly everything that other assemblers for 1068the same machine would assemble. Any exceptions are documented 1069explicitly (*note Machine Dependencies::). This doesn't mean `as' 1070always uses the same syntax as another assembler for the same 1071architecture; for example, we know of several incompatible versions of 1072680x0 assembly language syntax. 1073 1074 Unlike older assemblers, `as' is designed to assemble a source 1075program in one pass of the source file. This has a subtle impact on the 1076`.org' directive (*note `.org': Org.). 1077 1078 1079File: as.info, Node: Object Formats, Next: Command Line, Prev: GNU Assembler, Up: Overview 1080 10811.3 Object File Formats 1082======================= 1083 1084The GNU assembler can be configured to produce several alternative 1085object file formats. For the most part, this does not affect how you 1086write assembly language programs; but directives for debugging symbols 1087are typically different in different file formats. *Note Symbol 1088Attributes: Symbol Attributes. 1089 1090 1091File: as.info, Node: Command Line, Next: Input Files, Prev: Object Formats, Up: Overview 1092 10931.4 Command Line 1094================ 1095 1096After the program name `as', the command line may contain options and 1097file names. Options may appear in any order, and may be before, after, 1098or between file names. The order of file names is significant. 1099 1100 `--' (two hyphens) by itself names the standard input file 1101explicitly, as one of the files for `as' to assemble. 1102 1103 Except for `--' any command line argument that begins with a hyphen 1104(`-') is an option. Each option changes the behavior of `as'. No 1105option changes the way another option works. An option is a `-' 1106followed by one or more letters; the case of the letter is important. 1107All options are optional. 1108 1109 Some options expect exactly one file name to follow them. The file 1110name may either immediately follow the option's letter (compatible with 1111older assemblers) or it may be the next command argument (GNU 1112standard). These two command lines are equivalent: 1113 1114 as -o my-object-file.o mumble.s 1115 as -omy-object-file.o mumble.s 1116 1117 1118File: as.info, Node: Input Files, Next: Object, Prev: Command Line, Up: Overview 1119 11201.5 Input Files 1121=============== 1122 1123We use the phrase "source program", abbreviated "source", to describe 1124the program input to one run of `as'. The program may be in one or 1125more files; how the source is partitioned into files doesn't change the 1126meaning of the source. 1127 1128 The source program is a concatenation of the text in all the files, 1129in the order specified. 1130 1131 Each time you run `as' it assembles exactly one source program. The 1132source program is made up of one or more files. (The standard input is 1133also a file.) 1134 1135 You give `as' a command line that has zero or more input file names. 1136The input files are read (from left file name to right). A command 1137line argument (in any position) that has no special meaning is taken to 1138be an input file name. 1139 1140 If you give `as' no file names it attempts to read one input file 1141from the `as' standard input, which is normally your terminal. You may 1142have to type <ctl-D> to tell `as' there is no more program to assemble. 1143 1144 Use `--' if you need to explicitly name the standard input file in 1145your command line. 1146 1147 If the source is empty, `as' produces a small, empty object file. 1148 1149Filenames and Line-numbers 1150-------------------------- 1151 1152There are two ways of locating a line in the input file (or files) and 1153either may be used in reporting error messages. One way refers to a 1154line number in a physical file; the other refers to a line number in a 1155"logical" file. *Note Error and Warning Messages: Errors. 1156 1157 "Physical files" are those files named in the command line given to 1158`as'. 1159 1160 "Logical files" are simply names declared explicitly by assembler 1161directives; they bear no relation to physical files. Logical file 1162names help error messages reflect the original source file, when `as' 1163source is itself synthesized from other files. `as' understands the 1164`#' directives emitted by the `gcc' preprocessor. See also *note 1165`.file': File. 1166 1167 1168File: as.info, Node: Object, Next: Errors, Prev: Input Files, Up: Overview 1169 11701.6 Output (Object) File 1171======================== 1172 1173Every time you run `as' it produces an output file, which is your 1174assembly language program translated into numbers. This file is the 1175object file. Its default name is `a.out'. You can give it another 1176name by using the `-o' option. Conventionally, object file names end 1177with `.o'. The default name is used for historical reasons: older 1178assemblers were capable of assembling self-contained programs directly 1179into a runnable program. (For some formats, this isn't currently 1180possible, but it can be done for the `a.out' format.) 1181 1182 The object file is meant for input to the linker `ld'. It contains 1183assembled program code, information to help `ld' integrate the 1184assembled program into a runnable file, and (optionally) symbolic 1185information for the debugger. 1186 1187 1188File: as.info, Node: Errors, Prev: Object, Up: Overview 1189 11901.7 Error and Warning Messages 1191============================== 1192 1193`as' may write warnings and error messages to the standard error file 1194(usually your terminal). This should not happen when a compiler runs 1195`as' automatically. Warnings report an assumption made so that `as' 1196could keep assembling a flawed program; errors report a grave problem 1197that stops the assembly. 1198 1199 Warning messages have the format 1200 1201 file_name:NNN:Warning Message Text 1202 1203(where NNN is a line number). If a logical file name has been given 1204(*note `.file': File.) it is used for the filename, otherwise the name 1205of the current input file is used. If a logical line number was given 1206(*note `.line': Line.) then it is used to calculate the number printed, 1207otherwise the actual line in the current source file is printed. The 1208message text is intended to be self explanatory (in the grand Unix 1209tradition). 1210 1211 Error messages have the format 1212 file_name:NNN:FATAL:Error Message Text 1213 The file name and line number are derived as for warning messages. 1214The actual message text may be rather less explanatory because many of 1215them aren't supposed to happen. 1216 1217 1218File: as.info, Node: Invoking, Next: Syntax, Prev: Overview, Up: Top 1219 12202 Command-Line Options 1221********************** 1222 1223This chapter describes command-line options available in _all_ versions 1224of the GNU assembler; see *note Machine Dependencies::, for options 1225specific to particular machine architectures. 1226 1227 If you are invoking `as' via the GNU C compiler, you can use the 1228`-Wa' option to pass arguments through to the assembler. The assembler 1229arguments must be separated from each other (and the `-Wa') by commas. 1230For example: 1231 1232 gcc -c -g -O -Wa,-alh,-L file.c 1233 1234This passes two options to the assembler: `-alh' (emit a listing to 1235standard output with high-level and assembly source) and `-L' (retain 1236local symbols in the symbol table). 1237 1238 Usually you do not need to use this `-Wa' mechanism, since many 1239compiler command-line options are automatically passed to the assembler 1240by the compiler. (You can call the GNU compiler driver with the `-v' 1241option to see precisely what options it passes to each compilation 1242pass, including the assembler.) 1243 1244* Menu: 1245 1246* a:: -a[cdghlns] enable listings 1247* alternate:: --alternate enable alternate macro syntax 1248* D:: -D for compatibility 1249* f:: -f to work faster 1250* I:: -I for .include search path 1251 1252* K:: -K for difference tables 1253 1254* L:: -L to retain local symbols 1255* listing:: --listing-XXX to configure listing output 1256* M:: -M or --mri to assemble in MRI compatibility mode 1257* MD:: --MD for dependency tracking 1258* o:: -o to name the object file 1259* R:: -R to join data and text sections 1260* statistics:: --statistics to see statistics about assembly 1261* traditional-format:: --traditional-format for compatible output 1262* v:: -v to announce version 1263* W:: -W, --no-warn, --warn, --fatal-warnings to control warnings 1264* Z:: -Z to make object file even after errors 1265 1266 1267File: as.info, Node: a, Next: alternate, Up: Invoking 1268 12692.1 Enable Listings: `-a[cdghlns]' 1270================================== 1271 1272These options enable listing output from the assembler. By itself, 1273`-a' requests high-level, assembly, and symbols listing. You can use 1274other letters to select specific options for the list: `-ah' requests a 1275high-level language listing, `-al' requests an output-program assembly 1276listing, and `-as' requests a symbol table listing. High-level 1277listings require that a compiler debugging option like `-g' be used, 1278and that assembly listings (`-al') be requested also. 1279 1280 Use the `-ag' option to print a first section with general assembly 1281information, like as version, switches passed, or time stamp. 1282 1283 Use the `-ac' option to omit false conditionals from a listing. Any 1284lines which are not assembled because of a false `.if' (or `.ifdef', or 1285any other conditional), or a true `.if' followed by an `.else', will be 1286omitted from the listing. 1287 1288 Use the `-ad' option to omit debugging directives from the listing. 1289 1290 Once you have specified one of these options, you can further control 1291listing output and its appearance using the directives `.list', 1292`.nolist', `.psize', `.eject', `.title', and `.sbttl'. The `-an' 1293option turns off all forms processing. If you do not request listing 1294output with one of the `-a' options, the listing-control directives 1295have no effect. 1296 1297 The letters after `-a' may be combined into one option, _e.g._, 1298`-aln'. 1299 1300 Note if the assembler source is coming from the standard input (e.g., 1301because it is being created by `gcc' and the `-pipe' command line switch 1302is being used) then the listing will not contain any comments or 1303preprocessor directives. This is because the listing code buffers 1304input source lines from stdin only after they have been preprocessed by 1305the assembler. This reduces memory usage and makes the code more 1306efficient. 1307 1308 1309File: as.info, Node: alternate, Next: D, Prev: a, Up: Invoking 1310 13112.2 `--alternate' 1312================= 1313 1314Begin in alternate macro mode, see *note `.altmacro': Altmacro. 1315 1316 1317File: as.info, Node: D, Next: f, Prev: alternate, Up: Invoking 1318 13192.3 `-D' 1320======== 1321 1322This option has no effect whatsoever, but it is accepted to make it more 1323likely that scripts written for other assemblers also work with `as'. 1324 1325 1326File: as.info, Node: f, Next: I, Prev: D, Up: Invoking 1327 13282.4 Work Faster: `-f' 1329===================== 1330 1331`-f' should only be used when assembling programs written by a 1332(trusted) compiler. `-f' stops the assembler from doing whitespace and 1333comment preprocessing on the input file(s) before assembling them. 1334*Note Preprocessing: Preprocessing. 1335 1336 _Warning:_ if you use `-f' when the files actually need to be 1337 preprocessed (if they contain comments, for example), `as' does 1338 not work correctly. 1339 1340 1341File: as.info, Node: I, Next: K, Prev: f, Up: Invoking 1342 13432.5 `.include' Search Path: `-I' PATH 1344===================================== 1345 1346Use this option to add a PATH to the list of directories `as' searches 1347for files specified in `.include' directives (*note `.include': 1348Include.). You may use `-I' as many times as necessary to include a 1349variety of paths. The current working directory is always searched 1350first; after that, `as' searches any `-I' directories in the same order 1351as they were specified (left to right) on the command line. 1352 1353 1354File: as.info, Node: K, Next: L, Prev: I, Up: Invoking 1355 13562.6 Difference Tables: `-K' 1357=========================== 1358 1359`as' sometimes alters the code emitted for directives of the form 1360`.word SYM1-SYM2'. *Note `.word': Word. You can use the `-K' option 1361if you want a warning issued when this is done. 1362 1363 1364File: as.info, Node: L, Next: listing, Prev: K, Up: Invoking 1365 13662.7 Include Local Symbols: `-L' 1367=============================== 1368 1369Symbols beginning with system-specific local label prefixes, typically 1370`.L' for ELF systems or `L' for traditional a.out systems, are called 1371"local symbols". *Note Symbol Names::. Normally you do not see such 1372symbols when debugging, because they are intended for the use of 1373programs (like compilers) that compose assembler programs, not for your 1374notice. Normally both `as' and `ld' discard such symbols, so you do 1375not normally debug with them. 1376 1377 This option tells `as' to retain those local symbols in the object 1378file. Usually if you do this you also tell the linker `ld' to preserve 1379those symbols. 1380 1381 1382File: as.info, Node: listing, Next: M, Prev: L, Up: Invoking 1383 13842.8 Configuring listing output: `--listing' 1385=========================================== 1386 1387The listing feature of the assembler can be enabled via the command 1388line switch `-a' (*note a::). This feature combines the input source 1389file(s) with a hex dump of the corresponding locations in the output 1390object file, and displays them as a listing file. The format of this 1391listing can be controlled by directives inside the assembler source 1392(i.e., `.list' (*note List::), `.title' (*note Title::), `.sbttl' 1393(*note Sbttl::), `.psize' (*note Psize::), and `.eject' (*note Eject::) 1394and also by the following switches: 1395 1396`--listing-lhs-width=`number'' 1397 Sets the maximum width, in words, of the first line of the hex 1398 byte dump. This dump appears on the left hand side of the listing 1399 output. 1400 1401`--listing-lhs-width2=`number'' 1402 Sets the maximum width, in words, of any further lines of the hex 1403 byte dump for a given input source line. If this value is not 1404 specified, it defaults to being the same as the value specified 1405 for `--listing-lhs-width'. If neither switch is used the default 1406 is to one. 1407 1408`--listing-rhs-width=`number'' 1409 Sets the maximum width, in characters, of the source line that is 1410 displayed alongside the hex dump. The default value for this 1411 parameter is 100. The source line is displayed on the right hand 1412 side of the listing output. 1413 1414`--listing-cont-lines=`number'' 1415 Sets the maximum number of continuation lines of hex dump that 1416 will be displayed for a given single line of source input. The 1417 default value is 4. 1418 1419 1420File: as.info, Node: M, Next: MD, Prev: listing, Up: Invoking 1421 14222.9 Assemble in MRI Compatibility Mode: `-M' 1423============================================ 1424 1425The `-M' or `--mri' option selects MRI compatibility mode. This 1426changes the syntax and pseudo-op handling of `as' to make it compatible 1427with the `ASM68K' or the `ASM960' (depending upon the configured 1428target) assembler from Microtec Research. The exact nature of the MRI 1429syntax will not be documented here; see the MRI manuals for more 1430information. Note in particular that the handling of macros and macro 1431arguments is somewhat different. The purpose of this option is to 1432permit assembling existing MRI assembler code using `as'. 1433 1434 The MRI compatibility is not complete. Certain operations of the 1435MRI assembler depend upon its object file format, and can not be 1436supported using other object file formats. Supporting these would 1437require enhancing each object file format individually. These are: 1438 1439 * global symbols in common section 1440 1441 The m68k MRI assembler supports common sections which are merged 1442 by the linker. Other object file formats do not support this. 1443 `as' handles common sections by treating them as a single common 1444 symbol. It permits local symbols to be defined within a common 1445 section, but it can not support global symbols, since it has no 1446 way to describe them. 1447 1448 * complex relocations 1449 1450 The MRI assemblers support relocations against a negated section 1451 address, and relocations which combine the start addresses of two 1452 or more sections. These are not support by other object file 1453 formats. 1454 1455 * `END' pseudo-op specifying start address 1456 1457 The MRI `END' pseudo-op permits the specification of a start 1458 address. This is not supported by other object file formats. The 1459 start address may instead be specified using the `-e' option to 1460 the linker, or in a linker script. 1461 1462 * `IDNT', `.ident' and `NAME' pseudo-ops 1463 1464 The MRI `IDNT', `.ident' and `NAME' pseudo-ops assign a module 1465 name to the output file. This is not supported by other object 1466 file formats. 1467 1468 * `ORG' pseudo-op 1469 1470 The m68k MRI `ORG' pseudo-op begins an absolute section at a given 1471 address. This differs from the usual `as' `.org' pseudo-op, which 1472 changes the location within the current section. Absolute 1473 sections are not supported by other object file formats. The 1474 address of a section may be assigned within a linker script. 1475 1476 There are some other features of the MRI assembler which are not 1477supported by `as', typically either because they are difficult or 1478because they seem of little consequence. Some of these may be 1479supported in future releases. 1480 1481 * EBCDIC strings 1482 1483 EBCDIC strings are not supported. 1484 1485 * packed binary coded decimal 1486 1487 Packed binary coded decimal is not supported. This means that the 1488 `DC.P' and `DCB.P' pseudo-ops are not supported. 1489 1490 * `FEQU' pseudo-op 1491 1492 The m68k `FEQU' pseudo-op is not supported. 1493 1494 * `NOOBJ' pseudo-op 1495 1496 The m68k `NOOBJ' pseudo-op is not supported. 1497 1498 * `OPT' branch control options 1499 1500 The m68k `OPT' branch control options--`B', `BRS', `BRB', `BRL', 1501 and `BRW'--are ignored. `as' automatically relaxes all branches, 1502 whether forward or backward, to an appropriate size, so these 1503 options serve no purpose. 1504 1505 * `OPT' list control options 1506 1507 The following m68k `OPT' list control options are ignored: `C', 1508 `CEX', `CL', `CRE', `E', `G', `I', `M', `MEX', `MC', `MD', `X'. 1509 1510 * other `OPT' options 1511 1512 The following m68k `OPT' options are ignored: `NEST', `O', `OLD', 1513 `OP', `P', `PCO', `PCR', `PCS', `R'. 1514 1515 * `OPT' `D' option is default 1516 1517 The m68k `OPT' `D' option is the default, unlike the MRI assembler. 1518 `OPT NOD' may be used to turn it off. 1519 1520 * `XREF' pseudo-op. 1521 1522 The m68k `XREF' pseudo-op is ignored. 1523 1524 * `.debug' pseudo-op 1525 1526 The i960 `.debug' pseudo-op is not supported. 1527 1528 * `.extended' pseudo-op 1529 1530 The i960 `.extended' pseudo-op is not supported. 1531 1532 * `.list' pseudo-op. 1533 1534 The various options of the i960 `.list' pseudo-op are not 1535 supported. 1536 1537 * `.optimize' pseudo-op 1538 1539 The i960 `.optimize' pseudo-op is not supported. 1540 1541 * `.output' pseudo-op 1542 1543 The i960 `.output' pseudo-op is not supported. 1544 1545 * `.setreal' pseudo-op 1546 1547 The i960 `.setreal' pseudo-op is not supported. 1548 1549 1550 1551File: as.info, Node: MD, Next: o, Prev: M, Up: Invoking 1552 15532.10 Dependency Tracking: `--MD' 1554================================ 1555 1556`as' can generate a dependency file for the file it creates. This file 1557consists of a single rule suitable for `make' describing the 1558dependencies of the main source file. 1559 1560 The rule is written to the file named in its argument. 1561 1562 This feature is used in the automatic updating of makefiles. 1563 1564 1565File: as.info, Node: o, Next: R, Prev: MD, Up: Invoking 1566 15672.11 Name the Object File: `-o' 1568=============================== 1569 1570There is always one object file output when you run `as'. By default 1571it has the name `a.out' (or `b.out', for Intel 960 targets only). You 1572use this option (which takes exactly one filename) to give the object 1573file a different name. 1574 1575 Whatever the object file is called, `as' overwrites any existing 1576file of the same name. 1577 1578 1579File: as.info, Node: R, Next: statistics, Prev: o, Up: Invoking 1580 15812.12 Join Data and Text Sections: `-R' 1582====================================== 1583 1584`-R' tells `as' to write the object file as if all data-section data 1585lives in the text section. This is only done at the very last moment: 1586your binary data are the same, but data section parts are relocated 1587differently. The data section part of your object file is zero bytes 1588long because all its bytes are appended to the text section. (*Note 1589Sections and Relocation: Sections.) 1590 1591 When you specify `-R' it would be possible to generate shorter 1592address displacements (because we do not have to cross between text and 1593data section). We refrain from doing this simply for compatibility with 1594older versions of `as'. In future, `-R' may work this way. 1595 1596 When `as' is configured for COFF or ELF output, this option is only 1597useful if you use sections named `.text' and `.data'. 1598 1599 `-R' is not supported for any of the HPPA targets. Using `-R' 1600generates a warning from `as'. 1601 1602 1603File: as.info, Node: statistics, Next: traditional-format, Prev: R, Up: Invoking 1604 16052.13 Display Assembly Statistics: `--statistics' 1606================================================ 1607 1608Use `--statistics' to display two statistics about the resources used by 1609`as': the maximum amount of space allocated during the assembly (in 1610bytes), and the total execution time taken for the assembly (in CPU 1611seconds). 1612 1613 1614File: as.info, Node: traditional-format, Next: v, Prev: statistics, Up: Invoking 1615 16162.14 Compatible Output: `--traditional-format' 1617============================================== 1618 1619For some targets, the output of `as' is different in some ways from the 1620output of some existing assembler. This switch requests `as' to use 1621the traditional format instead. 1622 1623 For example, it disables the exception frame optimizations which 1624`as' normally does by default on `gcc' output. 1625 1626 1627File: as.info, Node: v, Next: W, Prev: traditional-format, Up: Invoking 1628 16292.15 Announce Version: `-v' 1630=========================== 1631 1632You can find out what version of as is running by including the option 1633`-v' (which you can also spell as `-version') on the command line. 1634 1635 1636File: as.info, Node: W, Next: Z, Prev: v, Up: Invoking 1637 16382.16 Control Warnings: `-W', `--warn', `--no-warn', `--fatal-warnings' 1639====================================================================== 1640 1641`as' should never give a warning or error message when assembling 1642compiler output. But programs written by people often cause `as' to 1643give a warning that a particular assumption was made. All such 1644warnings are directed to the standard error file. 1645 1646 If you use the `-W' and `--no-warn' options, no warnings are issued. 1647This only affects the warning messages: it does not change any 1648particular of how `as' assembles your file. Errors, which stop the 1649assembly, are still reported. 1650 1651 If you use the `--fatal-warnings' option, `as' considers files that 1652generate warnings to be in error. 1653 1654 You can switch these options off again by specifying `--warn', which 1655causes warnings to be output as usual. 1656 1657 1658File: as.info, Node: Z, Prev: W, Up: Invoking 1659 16602.17 Generate Object File in Spite of Errors: `-Z' 1661================================================== 1662 1663After an error message, `as' normally produces no output. If for some 1664reason you are interested in object file output even after `as' gives 1665an error message on your program, use the `-Z' option. If there are 1666any errors, `as' continues anyways, and writes an object file after a 1667final warning message of the form `N errors, M warnings, generating bad 1668object file.' 1669 1670 1671File: as.info, Node: Syntax, Next: Sections, Prev: Invoking, Up: Top 1672 16733 Syntax 1674******** 1675 1676This chapter describes the machine-independent syntax allowed in a 1677source file. `as' syntax is similar to what many other assemblers use; 1678it is inspired by the BSD 4.2 assembler, except that `as' does not 1679assemble Vax bit-fields. 1680 1681* Menu: 1682 1683* Preprocessing:: Preprocessing 1684* Whitespace:: Whitespace 1685* Comments:: Comments 1686* Symbol Intro:: Symbols 1687* Statements:: Statements 1688* Constants:: Constants 1689 1690 1691File: as.info, Node: Preprocessing, Next: Whitespace, Up: Syntax 1692 16933.1 Preprocessing 1694================= 1695 1696The `as' internal preprocessor: 1697 * adjusts and removes extra whitespace. It leaves one space or tab 1698 before the keywords on a line, and turns any other whitespace on 1699 the line into a single space. 1700 1701 * removes all comments, replacing them with a single space, or an 1702 appropriate number of newlines. 1703 1704 * converts character constants into the appropriate numeric values. 1705 1706 It does not do macro processing, include file handling, or anything 1707else you may get from your C compiler's preprocessor. You can do 1708include file processing with the `.include' directive (*note 1709`.include': Include.). You can use the GNU C compiler driver to get 1710other "CPP" style preprocessing by giving the input file a `.S' suffix. 1711*Note Options Controlling the Kind of Output: (gcc.info)Overall Options. 1712 1713 Excess whitespace, comments, and character constants cannot be used 1714in the portions of the input text that are not preprocessed. 1715 1716 If the first line of an input file is `#NO_APP' or if you use the 1717`-f' option, whitespace and comments are not removed from the input 1718file. Within an input file, you can ask for whitespace and comment 1719removal in specific portions of the by putting a line that says `#APP' 1720before the text that may contain whitespace or comments, and putting a 1721line that says `#NO_APP' after this text. This feature is mainly 1722intend to support `asm' statements in compilers whose output is 1723otherwise free of comments and whitespace. 1724 1725 1726File: as.info, Node: Whitespace, Next: Comments, Prev: Preprocessing, Up: Syntax 1727 17283.2 Whitespace 1729============== 1730 1731"Whitespace" is one or more blanks or tabs, in any order. Whitespace 1732is used to separate symbols, and to make programs neater for people to 1733read. Unless within character constants (*note Character Constants: 1734Characters.), any whitespace means the same as exactly one space. 1735 1736 1737File: as.info, Node: Comments, Next: Symbol Intro, Prev: Whitespace, Up: Syntax 1738 17393.3 Comments 1740============ 1741 1742There are two ways of rendering comments to `as'. In both cases the 1743comment is equivalent to one space. 1744 1745 Anything from `/*' through the next `*/' is a comment. This means 1746you may not nest these comments. 1747 1748 /* 1749 The only way to include a newline ('\n') in a comment 1750 is to use this sort of comment. 1751 */ 1752 1753 /* This sort of comment does not nest. */ 1754 1755 Anything from a "line comment" character up to the next newline is 1756considered a comment and is ignored. The line comment character is 1757target specific, and some targets multiple comment characters. Some 1758targets also have line comment characters that only work if they are 1759the first character on a line. Some targets use a sequence of two 1760characters to introduce a line comment. Some targets can also change 1761their line comment characters depending upon command line options that 1762have been used. For more details see the _Syntax_ section in the 1763documentation for individual targets. 1764 1765 If the line comment character is the hash sign (`#') then it still 1766has the special ability to enable and disable preprocessing (*note 1767Preprocessing::) and to specify logical line numbers: 1768 1769 To be compatible with past assemblers, lines that begin with `#' 1770have a special interpretation. Following the `#' should be an absolute 1771expression (*note Expressions::): the logical line number of the _next_ 1772line. Then a string (*note Strings: Strings.) is allowed: if present 1773it is a new logical file name. The rest of the line, if any, should be 1774whitespace. 1775 1776 If the first non-whitespace characters on the line are not numeric, 1777the line is ignored. (Just like a comment.) 1778 1779 # This is an ordinary comment. 1780 # 42-6 "new_file_name" # New logical file name 1781 # This is logical line # 36. 1782 This feature is deprecated, and may disappear from future versions 1783of `as'. 1784 1785 1786File: as.info, Node: Symbol Intro, Next: Statements, Prev: Comments, Up: Syntax 1787 17883.4 Symbols 1789=========== 1790 1791A "symbol" is one or more characters chosen from the set of all letters 1792(both upper and lower case), digits and the three characters `_.$'. On 1793most machines, you can also use `$' in symbol names; exceptions are 1794noted in *note Machine Dependencies::. No symbol may begin with a 1795digit. Case is significant. There is no length limit: all characters 1796are significant. Symbols are delimited by characters not in that set, 1797or by the beginning of a file (since the source program must end with a 1798newline, the end of a file is not a possible symbol delimiter). *Note 1799Symbols::. 1800 1801 1802File: as.info, Node: Statements, Next: Constants, Prev: Symbol Intro, Up: Syntax 1803 18043.5 Statements 1805============== 1806 1807A "statement" ends at a newline character (`\n') or a "line separator 1808character". The line separator character is target specific and 1809described in the _Syntax_ section of each target's documentation. Not 1810all targets support a line separator character. The newline or line 1811separator character is considered to be part of the preceding 1812statement. Newlines and separators within character constants are an 1813exception: they do not end statements. 1814 1815 It is an error to end any statement with end-of-file: the last 1816character of any input file should be a newline. 1817 1818 An empty statement is allowed, and may include whitespace. It is 1819ignored. 1820 1821 A statement begins with zero or more labels, optionally followed by a 1822key symbol which determines what kind of statement it is. The key 1823symbol determines the syntax of the rest of the statement. If the 1824symbol begins with a dot `.' then the statement is an assembler 1825directive: typically valid for any computer. If the symbol begins with 1826a letter the statement is an assembly language "instruction": it 1827assembles into a machine language instruction. Different versions of 1828`as' for different computers recognize different instructions. In 1829fact, the same symbol may represent a different instruction in a 1830different computer's assembly language. 1831 1832 A label is a symbol immediately followed by a colon (`:'). 1833Whitespace before a label or after a colon is permitted, but you may not 1834have whitespace between a label's symbol and its colon. *Note Labels::. 1835 1836 For HPPA targets, labels need not be immediately followed by a 1837colon, but the definition of a label must begin in column zero. This 1838also implies that only one label may be defined on each line. 1839 1840 label: .directive followed by something 1841 another_label: # This is an empty statement. 1842 instruction operand_1, operand_2, ... 1843 1844 1845File: as.info, Node: Constants, Prev: Statements, Up: Syntax 1846 18473.6 Constants 1848============= 1849 1850A constant is a number, written so that its value is known by 1851inspection, without knowing any context. Like this: 1852 .byte 74, 0112, 092, 0x4A, 0X4a, 'J, '\J # All the same value. 1853 .ascii "Ring the bell\7" # A string constant. 1854 .octa 0x123456789abcdef0123456789ABCDEF0 # A bignum. 1855 .float 0f-314159265358979323846264338327\ 1856 95028841971.693993751E-40 # - pi, a flonum. 1857 1858* Menu: 1859 1860* Characters:: Character Constants 1861* Numbers:: Number Constants 1862 1863 1864File: as.info, Node: Characters, Next: Numbers, Up: Constants 1865 18663.6.1 Character Constants 1867------------------------- 1868 1869There are two kinds of character constants. A "character" stands for 1870one character in one byte and its value may be used in numeric 1871expressions. String constants (properly called string _literals_) are 1872potentially many bytes and their values may not be used in arithmetic 1873expressions. 1874 1875* Menu: 1876 1877* Strings:: Strings 1878* Chars:: Characters 1879 1880 1881File: as.info, Node: Strings, Next: Chars, Up: Characters 1882 18833.6.1.1 Strings 1884............... 1885 1886A "string" is written between double-quotes. It may contain 1887double-quotes or null characters. The way to get special characters 1888into a string is to "escape" these characters: precede them with a 1889backslash `\' character. For example `\\' represents one backslash: 1890the first `\' is an escape which tells `as' to interpret the second 1891character literally as a backslash (which prevents `as' from 1892recognizing the second `\' as an escape character). The complete list 1893of escapes follows. 1894 1895`\b' 1896 Mnemonic for backspace; for ASCII this is octal code 010. 1897 1898`\f' 1899 Mnemonic for FormFeed; for ASCII this is octal code 014. 1900 1901`\n' 1902 Mnemonic for newline; for ASCII this is octal code 012. 1903 1904`\r' 1905 Mnemonic for carriage-Return; for ASCII this is octal code 015. 1906 1907`\t' 1908 Mnemonic for horizontal Tab; for ASCII this is octal code 011. 1909 1910`\ DIGIT DIGIT DIGIT' 1911 An octal character code. The numeric code is 3 octal digits. For 1912 compatibility with other Unix systems, 8 and 9 are accepted as 1913 digits: for example, `\008' has the value 010, and `\009' the 1914 value 011. 1915 1916`\`x' HEX-DIGITS...' 1917 A hex character code. All trailing hex digits are combined. 1918 Either upper or lower case `x' works. 1919 1920`\\' 1921 Represents one `\' character. 1922 1923`\"' 1924 Represents one `"' character. Needed in strings to represent this 1925 character, because an unescaped `"' would end the string. 1926 1927`\ ANYTHING-ELSE' 1928 Any other character when escaped by `\' gives a warning, but 1929 assembles as if the `\' was not present. The idea is that if you 1930 used an escape sequence you clearly didn't want the literal 1931 interpretation of the following character. However `as' has no 1932 other interpretation, so `as' knows it is giving you the wrong 1933 code and warns you of the fact. 1934 1935 Which characters are escapable, and what those escapes represent, 1936varies widely among assemblers. The current set is what we think the 1937BSD 4.2 assembler recognizes, and is a subset of what most C compilers 1938recognize. If you are in doubt, do not use an escape sequence. 1939 1940 1941File: as.info, Node: Chars, Prev: Strings, Up: Characters 1942 19433.6.1.2 Characters 1944.................. 1945 1946A single character may be written as a single quote immediately 1947followed by that character. The same escapes apply to characters as to 1948strings. So if you want to write the character backslash, you must 1949write `'\\' where the first `\' escapes the second `\'. As you can 1950see, the quote is an acute accent, not a grave accent. A newline 1951immediately following an acute accent is taken as a literal character 1952and does not count as the end of a statement. The value of a character 1953constant in a numeric expression is the machine's byte-wide code for 1954that character. `as' assumes your character code is ASCII: `'A' means 195565, `'B' means 66, and so on. 1956 1957 1958File: as.info, Node: Numbers, Prev: Characters, Up: Constants 1959 19603.6.2 Number Constants 1961---------------------- 1962 1963`as' distinguishes three kinds of numbers according to how they are 1964stored in the target machine. _Integers_ are numbers that would fit 1965into an `int' in the C language. _Bignums_ are integers, but they are 1966stored in more than 32 bits. _Flonums_ are floating point numbers, 1967described below. 1968 1969* Menu: 1970 1971* Integers:: Integers 1972* Bignums:: Bignums 1973* Flonums:: Flonums 1974 1975 1976File: as.info, Node: Integers, Next: Bignums, Up: Numbers 1977 19783.6.2.1 Integers 1979................ 1980 1981A binary integer is `0b' or `0B' followed by zero or more of the binary 1982digits `01'. 1983 1984 An octal integer is `0' followed by zero or more of the octal digits 1985(`01234567'). 1986 1987 A decimal integer starts with a non-zero digit followed by zero or 1988more digits (`0123456789'). 1989 1990 A hexadecimal integer is `0x' or `0X' followed by one or more 1991hexadecimal digits chosen from `0123456789abcdefABCDEF'. 1992 1993 Integers have the usual values. To denote a negative integer, use 1994the prefix operator `-' discussed under expressions (*note Prefix 1995Operators: Prefix Ops.). 1996 1997 1998File: as.info, Node: Bignums, Next: Flonums, Prev: Integers, Up: Numbers 1999 20003.6.2.2 Bignums 2001............... 2002 2003A "bignum" has the same syntax and semantics as an integer except that 2004the number (or its negative) takes more than 32 bits to represent in 2005binary. The distinction is made because in some places integers are 2006permitted while bignums are not. 2007 2008 2009File: as.info, Node: Flonums, Prev: Bignums, Up: Numbers 2010 20113.6.2.3 Flonums 2012............... 2013 2014A "flonum" represents a floating point number. The translation is 2015indirect: a decimal floating point number from the text is converted by 2016`as' to a generic binary floating point number of more than sufficient 2017precision. This generic floating point number is converted to a 2018particular computer's floating point format (or formats) by a portion 2019of `as' specialized to that computer. 2020 2021 A flonum is written by writing (in order) 2022 * The digit `0'. (`0' is optional on the HPPA.) 2023 2024 * A letter, to tell `as' the rest of the number is a flonum. `e' is 2025 recommended. Case is not important. 2026 2027 On the H8/300, Renesas / SuperH SH, and AMD 29K architectures, the 2028 letter must be one of the letters `DFPRSX' (in upper or lower 2029 case). 2030 2031 On the ARC, the letter must be one of the letters `DFRS' (in upper 2032 or lower case). 2033 2034 On the Intel 960 architecture, the letter must be one of the 2035 letters `DFT' (in upper or lower case). 2036 2037 On the HPPA architecture, the letter must be `E' (upper case only). 2038 2039 * An optional sign: either `+' or `-'. 2040 2041 * An optional "integer part": zero or more decimal digits. 2042 2043 * An optional "fractional part": `.' followed by zero or more 2044 decimal digits. 2045 2046 * An optional exponent, consisting of: 2047 2048 * An `E' or `e'. 2049 2050 * Optional sign: either `+' or `-'. 2051 2052 * One or more decimal digits. 2053 2054 2055 At least one of the integer part or the fractional part must be 2056present. The floating point number has the usual base-10 value. 2057 2058 `as' does all processing using integers. Flonums are computed 2059independently of any floating point hardware in the computer running 2060`as'. 2061 2062 2063File: as.info, Node: Sections, Next: Symbols, Prev: Syntax, Up: Top 2064 20654 Sections and Relocation 2066************************* 2067 2068* Menu: 2069 2070* Secs Background:: Background 2071* Ld Sections:: Linker Sections 2072* As Sections:: Assembler Internal Sections 2073* Sub-Sections:: Sub-Sections 2074* bss:: bss Section 2075 2076 2077File: as.info, Node: Secs Background, Next: Ld Sections, Up: Sections 2078 20794.1 Background 2080============== 2081 2082Roughly, a section is a range of addresses, with no gaps; all data "in" 2083those addresses is treated the same for some particular purpose. For 2084example there may be a "read only" section. 2085 2086 The linker `ld' reads many object files (partial programs) and 2087combines their contents to form a runnable program. When `as' emits an 2088object file, the partial program is assumed to start at address 0. 2089`ld' assigns the final addresses for the partial program, so that 2090different partial programs do not overlap. This is actually an 2091oversimplification, but it suffices to explain how `as' uses sections. 2092 2093 `ld' moves blocks of bytes of your program to their run-time 2094addresses. These blocks slide to their run-time addresses as rigid 2095units; their length does not change and neither does the order of bytes 2096within them. Such a rigid unit is called a _section_. Assigning 2097run-time addresses to sections is called "relocation". It includes the 2098task of adjusting mentions of object-file addresses so they refer to 2099the proper run-time addresses. For the H8/300, and for the Renesas / 2100SuperH SH, `as' pads sections if needed to ensure they end on a word 2101(sixteen bit) boundary. 2102 2103 An object file written by `as' has at least three sections, any of 2104which may be empty. These are named "text", "data" and "bss" sections. 2105 2106 When it generates COFF or ELF output, `as' can also generate 2107whatever other named sections you specify using the `.section' 2108directive (*note `.section': Section.). If you do not use any 2109directives that place output in the `.text' or `.data' sections, these 2110sections still exist, but are empty. 2111 2112 When `as' generates SOM or ELF output for the HPPA, `as' can also 2113generate whatever other named sections you specify using the `.space' 2114and `.subspace' directives. See `HP9000 Series 800 Assembly Language 2115Reference Manual' (HP 92432-90001) for details on the `.space' and 2116`.subspace' assembler directives. 2117 2118 Additionally, `as' uses different names for the standard text, data, 2119and bss sections when generating SOM output. Program text is placed 2120into the `$CODE$' section, data into `$DATA$', and BSS into `$BSS$'. 2121 2122 Within the object file, the text section starts at address `0', the 2123data section follows, and the bss section follows the data section. 2124 2125 When generating either SOM or ELF output files on the HPPA, the text 2126section starts at address `0', the data section at address `0x4000000', 2127and the bss section follows the data section. 2128 2129 To let `ld' know which data changes when the sections are relocated, 2130and how to change that data, `as' also writes to the object file 2131details of the relocation needed. To perform relocation `ld' must 2132know, each time an address in the object file is mentioned: 2133 * Where in the object file is the beginning of this reference to an 2134 address? 2135 2136 * How long (in bytes) is this reference? 2137 2138 * Which section does the address refer to? What is the numeric 2139 value of 2140 (ADDRESS) - (START-ADDRESS OF SECTION)? 2141 2142 * Is the reference to an address "Program-Counter relative"? 2143 2144 In fact, every address `as' ever uses is expressed as 2145 (SECTION) + (OFFSET INTO SECTION) 2146 Further, most expressions `as' computes have this section-relative 2147nature. (For some object formats, such as SOM for the HPPA, some 2148expressions are symbol-relative instead.) 2149 2150 In this manual we use the notation {SECNAME N} to mean "offset N 2151into section SECNAME." 2152 2153 Apart from text, data and bss sections you need to know about the 2154"absolute" section. When `ld' mixes partial programs, addresses in the 2155absolute section remain unchanged. For example, address `{absolute 0}' 2156is "relocated" to run-time address 0 by `ld'. Although the linker 2157never arranges two partial programs' data sections with overlapping 2158addresses after linking, _by definition_ their absolute sections must 2159overlap. Address `{absolute 239}' in one part of a program is always 2160the same address when the program is running as address `{absolute 2161239}' in any other part of the program. 2162 2163 The idea of sections is extended to the "undefined" section. Any 2164address whose section is unknown at assembly time is by definition 2165rendered {undefined U}--where U is filled in later. Since numbers are 2166always defined, the only way to generate an undefined address is to 2167mention an undefined symbol. A reference to a named common block would 2168be such a symbol: its value is unknown at assembly time so it has 2169section _undefined_. 2170 2171 By analogy the word _section_ is used to describe groups of sections 2172in the linked program. `ld' puts all partial programs' text sections 2173in contiguous addresses in the linked program. It is customary to 2174refer to the _text section_ of a program, meaning all the addresses of 2175all partial programs' text sections. Likewise for data and bss 2176sections. 2177 2178 Some sections are manipulated by `ld'; others are invented for use 2179of `as' and have no meaning except during assembly. 2180 2181 2182File: as.info, Node: Ld Sections, Next: As Sections, Prev: Secs Background, Up: Sections 2183 21844.2 Linker Sections 2185=================== 2186 2187`ld' deals with just four kinds of sections, summarized below. 2188 2189*named sections* 2190*text section* 2191*data section* 2192 These sections hold your program. `as' and `ld' treat them as 2193 separate but equal sections. Anything you can say of one section 2194 is true of another. When the program is running, however, it is 2195 customary for the text section to be unalterable. The text 2196 section is often shared among processes: it contains instructions, 2197 constants and the like. The data section of a running program is 2198 usually alterable: for example, C variables would be stored in the 2199 data section. 2200 2201*bss section* 2202 This section contains zeroed bytes when your program begins 2203 running. It is used to hold uninitialized variables or common 2204 storage. The length of each partial program's bss section is 2205 important, but because it starts out containing zeroed bytes there 2206 is no need to store explicit zero bytes in the object file. The 2207 bss section was invented to eliminate those explicit zeros from 2208 object files. 2209 2210*absolute section* 2211 Address 0 of this section is always "relocated" to runtime address 2212 0. This is useful if you want to refer to an address that `ld' 2213 must not change when relocating. In this sense we speak of 2214 absolute addresses being "unrelocatable": they do not change 2215 during relocation. 2216 2217*undefined section* 2218 This "section" is a catch-all for address references to objects 2219 not in the preceding sections. 2220 2221 An idealized example of three relocatable sections follows. The 2222example uses the traditional section names `.text' and `.data'. Memory 2223addresses are on the horizontal axis. 2224 2225 +-----+----+--+ 2226 partial program # 1: |ttttt|dddd|00| 2227 +-----+----+--+ 2228 2229 text data bss 2230 seg. seg. seg. 2231 2232 +---+---+---+ 2233 partial program # 2: |TTT|DDD|000| 2234 +---+---+---+ 2235 2236 +--+---+-----+--+----+---+-----+~~ 2237 linked program: | |TTT|ttttt| |dddd|DDD|00000| 2238 +--+---+-----+--+----+---+-----+~~ 2239 2240 addresses: 0 ... 2241 2242 2243File: as.info, Node: As Sections, Next: Sub-Sections, Prev: Ld Sections, Up: Sections 2244 22454.3 Assembler Internal Sections 2246=============================== 2247 2248These sections are meant only for the internal use of `as'. They have 2249no meaning at run-time. You do not really need to know about these 2250sections for most purposes; but they can be mentioned in `as' warning 2251messages, so it might be helpful to have an idea of their meanings to 2252`as'. These sections are used to permit the value of every expression 2253in your assembly language program to be a section-relative address. 2254 2255ASSEMBLER-INTERNAL-LOGIC-ERROR! 2256 An internal assembler logic error has been found. This means 2257 there is a bug in the assembler. 2258 2259expr section 2260 The assembler stores complex expression internally as combinations 2261 of symbols. When it needs to represent an expression as a symbol, 2262 it puts it in the expr section. 2263 2264 2265File: as.info, Node: Sub-Sections, Next: bss, Prev: As Sections, Up: Sections 2266 22674.4 Sub-Sections 2268================ 2269 2270Assembled bytes conventionally fall into two sections: text and data. 2271You may have separate groups of data in named sections that you want to 2272end up near to each other in the object file, even though they are not 2273contiguous in the assembler source. `as' allows you to use 2274"subsections" for this purpose. Within each section, there can be 2275numbered subsections with values from 0 to 8192. Objects assembled 2276into the same subsection go into the object file together with other 2277objects in the same subsection. For example, a compiler might want to 2278store constants in the text section, but might not want to have them 2279interspersed with the program being assembled. In this case, the 2280compiler could issue a `.text 0' before each section of code being 2281output, and a `.text 1' before each group of constants being output. 2282 2283Subsections are optional. If you do not use subsections, everything 2284goes in subsection number zero. 2285 2286 Each subsection is zero-padded up to a multiple of four bytes. 2287(Subsections may be padded a different amount on different flavors of 2288`as'.) 2289 2290 Subsections appear in your object file in numeric order, lowest 2291numbered to highest. (All this to be compatible with other people's 2292assemblers.) The object file contains no representation of 2293subsections; `ld' and other programs that manipulate object files see 2294no trace of them. They just see all your text subsections as a text 2295section, and all your data subsections as a data section. 2296 2297 To specify which subsection you want subsequent statements assembled 2298into, use a numeric argument to specify it, in a `.text EXPRESSION' or 2299a `.data EXPRESSION' statement. When generating COFF output, you can 2300also use an extra subsection argument with arbitrary named sections: 2301`.section NAME, EXPRESSION'. When generating ELF output, you can also 2302use the `.subsection' directive (*note SubSection::) to specify a 2303subsection: `.subsection EXPRESSION'. EXPRESSION should be an absolute 2304expression (*note Expressions::). If you just say `.text' then `.text 23050' is assumed. Likewise `.data' means `.data 0'. Assembly begins in 2306`text 0'. For instance: 2307 .text 0 # The default subsection is text 0 anyway. 2308 .ascii "This lives in the first text subsection. *" 2309 .text 1 2310 .ascii "But this lives in the second text subsection." 2311 .data 0 2312 .ascii "This lives in the data section," 2313 .ascii "in the first data subsection." 2314 .text 0 2315 .ascii "This lives in the first text section," 2316 .ascii "immediately following the asterisk (*)." 2317 2318 Each section has a "location counter" incremented by one for every 2319byte assembled into that section. Because subsections are merely a 2320convenience restricted to `as' there is no concept of a subsection 2321location counter. There is no way to directly manipulate a location 2322counter--but the `.align' directive changes it, and any label 2323definition captures its current value. The location counter of the 2324section where statements are being assembled is said to be the "active" 2325location counter. 2326 2327 2328File: as.info, Node: bss, Prev: Sub-Sections, Up: Sections 2329 23304.5 bss Section 2331=============== 2332 2333The bss section is used for local common variable storage. You may 2334allocate address space in the bss section, but you may not dictate data 2335to load into it before your program executes. When your program starts 2336running, all the contents of the bss section are zeroed bytes. 2337 2338 The `.lcomm' pseudo-op defines a symbol in the bss section; see 2339*note `.lcomm': Lcomm. 2340 2341 The `.comm' pseudo-op may be used to declare a common symbol, which 2342is another form of uninitialized symbol; see *note `.comm': Comm. 2343 2344 When assembling for a target which supports multiple sections, such 2345as ELF or COFF, you may switch into the `.bss' section and define 2346symbols as usual; see *note `.section': Section. You may only assemble 2347zero values into the section. Typically the section will only contain 2348symbol definitions and `.skip' directives (*note `.skip': Skip.). 2349 2350 2351File: as.info, Node: Symbols, Next: Expressions, Prev: Sections, Up: Top 2352 23535 Symbols 2354********* 2355 2356Symbols are a central concept: the programmer uses symbols to name 2357things, the linker uses symbols to link, and the debugger uses symbols 2358to debug. 2359 2360 _Warning:_ `as' does not place symbols in the object file in the 2361 same order they were declared. This may break some debuggers. 2362 2363* Menu: 2364 2365* Labels:: Labels 2366* Setting Symbols:: Giving Symbols Other Values 2367* Symbol Names:: Symbol Names 2368* Dot:: The Special Dot Symbol 2369* Symbol Attributes:: Symbol Attributes 2370 2371 2372File: as.info, Node: Labels, Next: Setting Symbols, Up: Symbols 2373 23745.1 Labels 2375========== 2376 2377A "label" is written as a symbol immediately followed by a colon `:'. 2378The symbol then represents the current value of the active location 2379counter, and is, for example, a suitable instruction operand. You are 2380warned if you use the same symbol to represent two different locations: 2381the first definition overrides any other definitions. 2382 2383 On the HPPA, the usual form for a label need not be immediately 2384followed by a colon, but instead must start in column zero. Only one 2385label may be defined on a single line. To work around this, the HPPA 2386version of `as' also provides a special directive `.label' for defining 2387labels more flexibly. 2388 2389 2390File: as.info, Node: Setting Symbols, Next: Symbol Names, Prev: Labels, Up: Symbols 2391 23925.2 Giving Symbols Other Values 2393=============================== 2394 2395A symbol can be given an arbitrary value by writing a symbol, followed 2396by an equals sign `=', followed by an expression (*note Expressions::). 2397This is equivalent to using the `.set' directive. *Note `.set': Set. 2398In the same way, using a double equals sign `='`=' here represents an 2399equivalent of the `.eqv' directive. *Note `.eqv': Eqv. 2400 2401 Blackfin does not support symbol assignment with `='. 2402 2403 2404File: as.info, Node: Symbol Names, Next: Dot, Prev: Setting Symbols, Up: Symbols 2405 24065.3 Symbol Names 2407================ 2408 2409Symbol names begin with a letter or with one of `._'. On most 2410machines, you can also use `$' in symbol names; exceptions are noted in 2411*note Machine Dependencies::. That character may be followed by any 2412string of digits, letters, dollar signs (unless otherwise noted for a 2413particular target machine), and underscores. 2414 2415Case of letters is significant: `foo' is a different symbol name than 2416`Foo'. 2417 2418 Each symbol has exactly one name. Each name in an assembly language 2419program refers to exactly one symbol. You may use that symbol name any 2420number of times in a program. 2421 2422Local Symbol Names 2423------------------ 2424 2425A local symbol is any symbol beginning with certain local label 2426prefixes. By default, the local label prefix is `.L' for ELF systems or 2427`L' for traditional a.out systems, but each target may have its own set 2428of local label prefixes. On the HPPA local symbols begin with `L$'. 2429 2430 Local symbols are defined and used within the assembler, but they are 2431normally not saved in object files. Thus, they are not visible when 2432debugging. You may use the `-L' option (*note Include Local Symbols: 2433`-L': L.) to retain the local symbols in the object files. 2434 2435Local Labels 2436------------ 2437 2438Local labels help compilers and programmers use names temporarily. 2439They create symbols which are guaranteed to be unique over the entire 2440scope of the input source code and which can be referred to by a simple 2441notation. To define a local label, write a label of the form `N:' 2442(where N represents any positive integer). To refer to the most recent 2443previous definition of that label write `Nb', using the same number as 2444when you defined the label. To refer to the next definition of a local 2445label, write `Nf'--the `b' stands for "backwards" and the `f' stands 2446for "forwards". 2447 2448 There is no restriction on how you can use these labels, and you can 2449reuse them too. So that it is possible to repeatedly define the same 2450local label (using the same number `N'), although you can only refer to 2451the most recently defined local label of that number (for a backwards 2452reference) or the next definition of a specific local label for a 2453forward reference. It is also worth noting that the first 10 local 2454labels (`0:'...`9:') are implemented in a slightly more efficient 2455manner than the others. 2456 2457 Here is an example: 2458 2459 1: branch 1f 2460 2: branch 1b 2461 1: branch 2f 2462 2: branch 1b 2463 2464 Which is the equivalent of: 2465 2466 label_1: branch label_3 2467 label_2: branch label_1 2468 label_3: branch label_4 2469 label_4: branch label_3 2470 2471 Local label names are only a notational device. They are immediately 2472transformed into more conventional symbol names before the assembler 2473uses them. The symbol names are stored in the symbol table, appear in 2474error messages, and are optionally emitted to the object file. The 2475names are constructed using these parts: 2476 2477`_local label prefix_' 2478 All local symbols begin with the system-specific local label 2479 prefix. Normally both `as' and `ld' forget symbols that start 2480 with the local label prefix. These labels are used for symbols 2481 you are never intended to see. If you use the `-L' option then 2482 `as' retains these symbols in the object file. If you also 2483 instruct `ld' to retain these symbols, you may use them in 2484 debugging. 2485 2486`NUMBER' 2487 This is the number that was used in the local label definition. 2488 So if the label is written `55:' then the number is `55'. 2489 2490`C-B' 2491 This unusual character is included so you do not accidentally 2492 invent a symbol of the same name. The character has ASCII value 2493 of `\002' (control-B). 2494 2495`_ordinal number_' 2496 This is a serial number to keep the labels distinct. The first 2497 definition of `0:' gets the number `1'. The 15th definition of 2498 `0:' gets the number `15', and so on. Likewise the first 2499 definition of `1:' gets the number `1' and its 15th definition 2500 gets `15' as well. 2501 2502 So for example, the first `1:' may be named `.L1C-B1', and the 44th 2503`3:' may be named `.L3C-B44'. 2504 2505Dollar Local Labels 2506------------------- 2507 2508`as' also supports an even more local form of local labels called 2509dollar labels. These labels go out of scope (i.e., they become 2510undefined) as soon as a non-local label is defined. Thus they remain 2511valid for only a small region of the input source code. Normal local 2512labels, by contrast, remain in scope for the entire file, or until they 2513are redefined by another occurrence of the same local label. 2514 2515 Dollar labels are defined in exactly the same way as ordinary local 2516labels, except that they have a dollar sign suffix to their numeric 2517value, e.g., `55$:'. 2518 2519 They can also be distinguished from ordinary local labels by their 2520transformed names which use ASCII character `\001' (control-A) as the 2521magic character to distinguish them from ordinary labels. For example, 2522the fifth definition of `6$' may be named `.L6C-A5'. 2523 2524 2525File: as.info, Node: Dot, Next: Symbol Attributes, Prev: Symbol Names, Up: Symbols 2526 25275.4 The Special Dot Symbol 2528========================== 2529 2530The special symbol `.' refers to the current address that `as' is 2531assembling into. Thus, the expression `melvin: .long .' defines 2532`melvin' to contain its own address. Assigning a value to `.' is 2533treated the same as a `.org' directive. Thus, the expression `.=.+4' 2534is the same as saying `.space 4'. 2535 2536 2537File: as.info, Node: Symbol Attributes, Prev: Dot, Up: Symbols 2538 25395.5 Symbol Attributes 2540===================== 2541 2542Every symbol has, as well as its name, the attributes "Value" and 2543"Type". Depending on output format, symbols can also have auxiliary 2544attributes. 2545 2546 If you use a symbol without defining it, `as' assumes zero for all 2547these attributes, and probably won't warn you. This makes the symbol 2548an externally defined symbol, which is generally what you would want. 2549 2550* Menu: 2551 2552* Symbol Value:: Value 2553* Symbol Type:: Type 2554 2555 2556* a.out Symbols:: Symbol Attributes: `a.out' 2557 2558* COFF Symbols:: Symbol Attributes for COFF 2559 2560* SOM Symbols:: Symbol Attributes for SOM 2561 2562 2563File: as.info, Node: Symbol Value, Next: Symbol Type, Up: Symbol Attributes 2564 25655.5.1 Value 2566----------- 2567 2568The value of a symbol is (usually) 32 bits. For a symbol which labels a 2569location in the text, data, bss or absolute sections the value is the 2570number of addresses from the start of that section to the label. 2571Naturally for text, data and bss sections the value of a symbol changes 2572as `ld' changes section base addresses during linking. Absolute 2573symbols' values do not change during linking: that is why they are 2574called absolute. 2575 2576 The value of an undefined symbol is treated in a special way. If it 2577is 0 then the symbol is not defined in this assembler source file, and 2578`ld' tries to determine its value from other files linked into the same 2579program. You make this kind of symbol simply by mentioning a symbol 2580name without defining it. A non-zero value represents a `.comm' common 2581declaration. The value is how much common storage to reserve, in bytes 2582(addresses). The symbol refers to the first address of the allocated 2583storage. 2584 2585 2586File: as.info, Node: Symbol Type, Next: a.out Symbols, Prev: Symbol Value, Up: Symbol Attributes 2587 25885.5.2 Type 2589---------- 2590 2591The type attribute of a symbol contains relocation (section) 2592information, any flag settings indicating that a symbol is external, and 2593(optionally), other information for linkers and debuggers. The exact 2594format depends on the object-code output format in use. 2595 2596 2597File: as.info, Node: a.out Symbols, Next: COFF Symbols, Prev: Symbol Type, Up: Symbol Attributes 2598 25995.5.3 Symbol Attributes: `a.out' 2600-------------------------------- 2601 2602* Menu: 2603 2604* Symbol Desc:: Descriptor 2605* Symbol Other:: Other 2606 2607 2608File: as.info, Node: Symbol Desc, Next: Symbol Other, Up: a.out Symbols 2609 26105.5.3.1 Descriptor 2611.................. 2612 2613This is an arbitrary 16-bit value. You may establish a symbol's 2614descriptor value by using a `.desc' statement (*note `.desc': Desc.). 2615A descriptor value means nothing to `as'. 2616 2617 2618File: as.info, Node: Symbol Other, Prev: Symbol Desc, Up: a.out Symbols 2619 26205.5.3.2 Other 2621............. 2622 2623This is an arbitrary 8-bit value. It means nothing to `as'. 2624 2625 2626File: as.info, Node: COFF Symbols, Next: SOM Symbols, Prev: a.out Symbols, Up: Symbol Attributes 2627 26285.5.4 Symbol Attributes for COFF 2629-------------------------------- 2630 2631The COFF format supports a multitude of auxiliary symbol attributes; 2632like the primary symbol attributes, they are set between `.def' and 2633`.endef' directives. 2634 26355.5.4.1 Primary Attributes 2636.......................... 2637 2638The symbol name is set with `.def'; the value and type, respectively, 2639with `.val' and `.type'. 2640 26415.5.4.2 Auxiliary Attributes 2642............................ 2643 2644The `as' directives `.dim', `.line', `.scl', `.size', `.tag', and 2645`.weak' can generate auxiliary symbol table information for COFF. 2646 2647 2648File: as.info, Node: SOM Symbols, Prev: COFF Symbols, Up: Symbol Attributes 2649 26505.5.5 Symbol Attributes for SOM 2651------------------------------- 2652 2653The SOM format for the HPPA supports a multitude of symbol attributes 2654set with the `.EXPORT' and `.IMPORT' directives. 2655 2656 The attributes are described in `HP9000 Series 800 Assembly Language 2657Reference Manual' (HP 92432-90001) under the `IMPORT' and `EXPORT' 2658assembler directive documentation. 2659 2660 2661File: as.info, Node: Expressions, Next: Pseudo Ops, Prev: Symbols, Up: Top 2662 26636 Expressions 2664************* 2665 2666An "expression" specifies an address or numeric value. Whitespace may 2667precede and/or follow an expression. 2668 2669 The result of an expression must be an absolute number, or else an 2670offset into a particular section. If an expression is not absolute, 2671and there is not enough information when `as' sees the expression to 2672know its section, a second pass over the source program might be 2673necessary to interpret the expression--but the second pass is currently 2674not implemented. `as' aborts with an error message in this situation. 2675 2676* Menu: 2677 2678* Empty Exprs:: Empty Expressions 2679* Integer Exprs:: Integer Expressions 2680 2681 2682File: as.info, Node: Empty Exprs, Next: Integer Exprs, Up: Expressions 2683 26846.1 Empty Expressions 2685===================== 2686 2687An empty expression has no value: it is just whitespace or null. 2688Wherever an absolute expression is required, you may omit the 2689expression, and `as' assumes a value of (absolute) 0. This is 2690compatible with other assemblers. 2691 2692 2693File: as.info, Node: Integer Exprs, Prev: Empty Exprs, Up: Expressions 2694 26956.2 Integer Expressions 2696======================= 2697 2698An "integer expression" is one or more _arguments_ delimited by 2699_operators_. 2700 2701* Menu: 2702 2703* Arguments:: Arguments 2704* Operators:: Operators 2705* Prefix Ops:: Prefix Operators 2706* Infix Ops:: Infix Operators 2707 2708 2709File: as.info, Node: Arguments, Next: Operators, Up: Integer Exprs 2710 27116.2.1 Arguments 2712--------------- 2713 2714"Arguments" are symbols, numbers or subexpressions. In other contexts 2715arguments are sometimes called "arithmetic operands". In this manual, 2716to avoid confusing them with the "instruction operands" of the machine 2717language, we use the term "argument" to refer to parts of expressions 2718only, reserving the word "operand" to refer only to machine instruction 2719operands. 2720 2721 Symbols are evaluated to yield {SECTION NNN} where SECTION is one of 2722text, data, bss, absolute, or undefined. NNN is a signed, 2's 2723complement 32 bit integer. 2724 2725 Numbers are usually integers. 2726 2727 A number can be a flonum or bignum. In this case, you are warned 2728that only the low order 32 bits are used, and `as' pretends these 32 2729bits are an integer. You may write integer-manipulating instructions 2730that act on exotic constants, compatible with other assemblers. 2731 2732 Subexpressions are a left parenthesis `(' followed by an integer 2733expression, followed by a right parenthesis `)'; or a prefix operator 2734followed by an argument. 2735 2736 2737File: as.info, Node: Operators, Next: Prefix Ops, Prev: Arguments, Up: Integer Exprs 2738 27396.2.2 Operators 2740--------------- 2741 2742"Operators" are arithmetic functions, like `+' or `%'. Prefix 2743operators are followed by an argument. Infix operators appear between 2744their arguments. Operators may be preceded and/or followed by 2745whitespace. 2746 2747 2748File: as.info, Node: Prefix Ops, Next: Infix Ops, Prev: Operators, Up: Integer Exprs 2749 27506.2.3 Prefix Operator 2751--------------------- 2752 2753`as' has the following "prefix operators". They each take one 2754argument, which must be absolute. 2755 2756`-' 2757 "Negation". Two's complement negation. 2758 2759`~' 2760 "Complementation". Bitwise not. 2761 2762 2763File: as.info, Node: Infix Ops, Prev: Prefix Ops, Up: Integer Exprs 2764 27656.2.4 Infix Operators 2766--------------------- 2767 2768"Infix operators" take two arguments, one on either side. Operators 2769have precedence, but operations with equal precedence are performed left 2770to right. Apart from `+' or `-', both arguments must be absolute, and 2771the result is absolute. 2772 2773 1. Highest Precedence 2774 2775 `*' 2776 "Multiplication". 2777 2778 `/' 2779 "Division". Truncation is the same as the C operator `/' 2780 2781 `%' 2782 "Remainder". 2783 2784 `<<' 2785 "Shift Left". Same as the C operator `<<'. 2786 2787 `>>' 2788 "Shift Right". Same as the C operator `>>'. 2789 2790 2. Intermediate precedence 2791 2792 `|' 2793 "Bitwise Inclusive Or". 2794 2795 `&' 2796 "Bitwise And". 2797 2798 `^' 2799 "Bitwise Exclusive Or". 2800 2801 `!' 2802 "Bitwise Or Not". 2803 2804 3. Low Precedence 2805 2806 `+' 2807 "Addition". If either argument is absolute, the result has 2808 the section of the other argument. You may not add together 2809 arguments from different sections. 2810 2811 `-' 2812 "Subtraction". If the right argument is absolute, the result 2813 has the section of the left argument. If both arguments are 2814 in the same section, the result is absolute. You may not 2815 subtract arguments from different sections. 2816 2817 `==' 2818 "Is Equal To" 2819 2820 `<>' 2821 `!=' 2822 "Is Not Equal To" 2823 2824 `<' 2825 "Is Less Than" 2826 2827 `>' 2828 "Is Greater Than" 2829 2830 `>=' 2831 "Is Greater Than Or Equal To" 2832 2833 `<=' 2834 "Is Less Than Or Equal To" 2835 2836 The comparison operators can be used as infix operators. A 2837 true results has a value of -1 whereas a false result has a 2838 value of 0. Note, these operators perform signed 2839 comparisons. 2840 2841 4. Lowest Precedence 2842 2843 `&&' 2844 "Logical And". 2845 2846 `||' 2847 "Logical Or". 2848 2849 These two logical operations can be used to combine the 2850 results of sub expressions. Note, unlike the comparison 2851 operators a true result returns a value of 1 but a false 2852 results does still return 0. Also note that the logical or 2853 operator has a slightly lower precedence than logical and. 2854 2855 2856 In short, it's only meaningful to add or subtract the _offsets_ in an 2857address; you can only have a defined section in one of the two 2858arguments. 2859 2860 2861File: as.info, Node: Pseudo Ops, Next: Object Attributes, Prev: Expressions, Up: Top 2862 28637 Assembler Directives 2864********************** 2865 2866All assembler directives have names that begin with a period (`.'). 2867The rest of the name is letters, usually in lower case. 2868 2869 This chapter discusses directives that are available regardless of 2870the target machine configuration for the GNU assembler. Some machine 2871configurations provide additional directives. *Note Machine 2872Dependencies::. 2873 2874* Menu: 2875 2876* Abort:: `.abort' 2877 2878* ABORT (COFF):: `.ABORT' 2879 2880* Align:: `.align ABS-EXPR , ABS-EXPR' 2881* Altmacro:: `.altmacro' 2882* Ascii:: `.ascii "STRING"'... 2883* Asciz:: `.asciz "STRING"'... 2884* Balign:: `.balign ABS-EXPR , ABS-EXPR' 2885* Byte:: `.byte EXPRESSIONS' 2886* CFI directives:: `.cfi_startproc [simple]', `.cfi_endproc', etc. 2887* Comm:: `.comm SYMBOL , LENGTH ' 2888* Data:: `.data SUBSECTION' 2889 2890* Def:: `.def NAME' 2891 2892* Desc:: `.desc SYMBOL, ABS-EXPRESSION' 2893 2894* Dim:: `.dim' 2895 2896* Double:: `.double FLONUMS' 2897* Eject:: `.eject' 2898* Else:: `.else' 2899* Elseif:: `.elseif' 2900* End:: `.end' 2901 2902* Endef:: `.endef' 2903 2904* Endfunc:: `.endfunc' 2905* Endif:: `.endif' 2906* Equ:: `.equ SYMBOL, EXPRESSION' 2907* Equiv:: `.equiv SYMBOL, EXPRESSION' 2908* Eqv:: `.eqv SYMBOL, EXPRESSION' 2909* Err:: `.err' 2910* Error:: `.error STRING' 2911* Exitm:: `.exitm' 2912* Extern:: `.extern' 2913* Fail:: `.fail' 2914* File:: `.file' 2915* Fill:: `.fill REPEAT , SIZE , VALUE' 2916* Float:: `.float FLONUMS' 2917* Func:: `.func' 2918* Global:: `.global SYMBOL', `.globl SYMBOL' 2919 2920* Gnu_attribute:: `.gnu_attribute TAG,VALUE' 2921* Hidden:: `.hidden NAMES' 2922 2923* hword:: `.hword EXPRESSIONS' 2924* Ident:: `.ident' 2925* If:: `.if ABSOLUTE EXPRESSION' 2926* Incbin:: `.incbin "FILE"[,SKIP[,COUNT]]' 2927* Include:: `.include "FILE"' 2928* Int:: `.int EXPRESSIONS' 2929 2930* Internal:: `.internal NAMES' 2931 2932* Irp:: `.irp SYMBOL,VALUES'... 2933* Irpc:: `.irpc SYMBOL,VALUES'... 2934* Lcomm:: `.lcomm SYMBOL , LENGTH' 2935* Lflags:: `.lflags' 2936 2937* Line:: `.line LINE-NUMBER' 2938 2939* Linkonce:: `.linkonce [TYPE]' 2940* List:: `.list' 2941* Ln:: `.ln LINE-NUMBER' 2942* Loc:: `.loc FILENO LINENO' 2943* Loc_mark_labels:: `.loc_mark_labels ENABLE' 2944 2945* Local:: `.local NAMES' 2946 2947* Long:: `.long EXPRESSIONS' 2948 2949* Macro:: `.macro NAME ARGS'... 2950* MRI:: `.mri VAL' 2951* Noaltmacro:: `.noaltmacro' 2952* Nolist:: `.nolist' 2953* Octa:: `.octa BIGNUMS' 2954* Offset:: `.offset LOC' 2955* Org:: `.org NEW-LC, FILL' 2956* P2align:: `.p2align ABS-EXPR, ABS-EXPR, ABS-EXPR' 2957 2958* PopSection:: `.popsection' 2959* Previous:: `.previous' 2960 2961* Print:: `.print STRING' 2962 2963* Protected:: `.protected NAMES' 2964 2965* Psize:: `.psize LINES, COLUMNS' 2966* Purgem:: `.purgem NAME' 2967 2968* PushSection:: `.pushsection NAME' 2969 2970* Quad:: `.quad BIGNUMS' 2971* Reloc:: `.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 2972* Rept:: `.rept COUNT' 2973* Sbttl:: `.sbttl "SUBHEADING"' 2974 2975* Scl:: `.scl CLASS' 2976 2977* Section:: `.section NAME[, FLAGS]' 2978 2979* Set:: `.set SYMBOL, EXPRESSION' 2980* Short:: `.short EXPRESSIONS' 2981* Single:: `.single FLONUMS' 2982 2983* Size:: `.size [NAME , EXPRESSION]' 2984 2985* Skip:: `.skip SIZE , FILL' 2986 2987* Sleb128:: `.sleb128 EXPRESSIONS' 2988 2989* Space:: `.space SIZE , FILL' 2990 2991* Stab:: `.stabd, .stabn, .stabs' 2992 2993* String:: `.string "STR"', `.string8 "STR"', `.string16 "STR"', `.string32 "STR"', `.string64 "STR"' 2994* Struct:: `.struct EXPRESSION' 2995 2996* SubSection:: `.subsection' 2997* Symver:: `.symver NAME,NAME2@NODENAME' 2998 2999 3000* Tag:: `.tag STRUCTNAME' 3001 3002* Text:: `.text SUBSECTION' 3003* Title:: `.title "HEADING"' 3004 3005* Type:: `.type <INT | NAME , TYPE DESCRIPTION>' 3006 3007* Uleb128:: `.uleb128 EXPRESSIONS' 3008 3009* Val:: `.val ADDR' 3010 3011 3012* Version:: `.version "STRING"' 3013* VTableEntry:: `.vtable_entry TABLE, OFFSET' 3014* VTableInherit:: `.vtable_inherit CHILD, PARENT' 3015 3016* Warning:: `.warning STRING' 3017* Weak:: `.weak NAMES' 3018* Weakref:: `.weakref ALIAS, SYMBOL' 3019* Word:: `.word EXPRESSIONS' 3020* Deprecated:: Deprecated Directives 3021 3022 3023File: as.info, Node: Abort, Next: ABORT (COFF), Up: Pseudo Ops 3024 30257.1 `.abort' 3026============ 3027 3028This directive stops the assembly immediately. It is for compatibility 3029with other assemblers. The original idea was that the assembly 3030language source would be piped into the assembler. If the sender of 3031the source quit, it could use this directive tells `as' to quit also. 3032One day `.abort' will not be supported. 3033 3034 3035File: as.info, Node: ABORT (COFF), Next: Align, Prev: Abort, Up: Pseudo Ops 3036 30377.2 `.ABORT' (COFF) 3038=================== 3039 3040When producing COFF output, `as' accepts this directive as a synonym 3041for `.abort'. 3042 3043 3044File: as.info, Node: Align, Next: Altmacro, Prev: ABORT (COFF), Up: Pseudo Ops 3045 30467.3 `.align ABS-EXPR, ABS-EXPR, ABS-EXPR' 3047========================================= 3048 3049Pad the location counter (in the current subsection) to a particular 3050storage boundary. The first expression (which must be absolute) is the 3051alignment required, as described below. 3052 3053 The second expression (also absolute) gives the fill value to be 3054stored in the padding bytes. It (and the comma) may be omitted. If it 3055is omitted, the padding bytes are normally zero. However, on some 3056systems, if the section is marked as containing code and the fill value 3057is omitted, the space is filled with no-op instructions. 3058 3059 The third expression is also absolute, and is also optional. If it 3060is present, it is the maximum number of bytes that should be skipped by 3061this alignment directive. If doing the alignment would require 3062skipping more bytes than the specified maximum, then the alignment is 3063not done at all. You can omit the fill value (the second argument) 3064entirely by simply using two commas after the required alignment; this 3065can be useful if you want the alignment to be filled with no-op 3066instructions when appropriate. 3067 3068 The way the required alignment is specified varies from system to 3069system. For the arc, hppa, i386 using ELF, i860, iq2000, m68k, or32, 3070s390, sparc, tic4x, tic80 and xtensa, the first expression is the 3071alignment request in bytes. For example `.align 8' advances the 3072location counter until it is a multiple of 8. If the location counter 3073is already a multiple of 8, no change is needed. For the tic54x, the 3074first expression is the alignment request in words. 3075 3076 For other systems, including ppc, i386 using a.out format, arm and 3077strongarm, it is the number of low-order zero bits the location counter 3078must have after advancement. For example `.align 3' advances the 3079location counter until it a multiple of 8. If the location counter is 3080already a multiple of 8, no change is needed. 3081 3082 This inconsistency is due to the different behaviors of the various 3083native assemblers for these systems which GAS must emulate. GAS also 3084provides `.balign' and `.p2align' directives, described later, which 3085have a consistent behavior across all architectures (but are specific 3086to GAS). 3087 3088 3089File: as.info, Node: Altmacro, Next: Ascii, Prev: Align, Up: Pseudo Ops 3090 30917.4 `.altmacro' 3092=============== 3093 3094Enable alternate macro mode, enabling: 3095 3096`LOCAL NAME [ , ... ]' 3097 One additional directive, `LOCAL', is available. It is used to 3098 generate a string replacement for each of the NAME arguments, and 3099 replace any instances of NAME in each macro expansion. The 3100 replacement string is unique in the assembly, and different for 3101 each separate macro expansion. `LOCAL' allows you to write macros 3102 that define symbols, without fear of conflict between separate 3103 macro expansions. 3104 3105`String delimiters' 3106 You can write strings delimited in these other ways besides 3107 `"STRING"': 3108 3109 `'STRING'' 3110 You can delimit strings with single-quote characters. 3111 3112 `<STRING>' 3113 You can delimit strings with matching angle brackets. 3114 3115`single-character string escape' 3116 To include any single character literally in a string (even if the 3117 character would otherwise have some special meaning), you can 3118 prefix the character with `!' (an exclamation mark). For example, 3119 you can write `<4.3 !> 5.4!!>' to get the literal text `4.3 > 3120 5.4!'. 3121 3122`Expression results as strings' 3123 You can write `%EXPR' to evaluate the expression EXPR and use the 3124 result as a string. 3125 3126 3127File: as.info, Node: Ascii, Next: Asciz, Prev: Altmacro, Up: Pseudo Ops 3128 31297.5 `.ascii "STRING"'... 3130======================== 3131 3132`.ascii' expects zero or more string literals (*note Strings::) 3133separated by commas. It assembles each string (with no automatic 3134trailing zero byte) into consecutive addresses. 3135 3136 3137File: as.info, Node: Asciz, Next: Balign, Prev: Ascii, Up: Pseudo Ops 3138 31397.6 `.asciz "STRING"'... 3140======================== 3141 3142`.asciz' is just like `.ascii', but each string is followed by a zero 3143byte. The "z" in `.asciz' stands for "zero". 3144 3145 3146File: as.info, Node: Balign, Next: Byte, Prev: Asciz, Up: Pseudo Ops 3147 31487.7 `.balign[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' 3149============================================== 3150 3151Pad the location counter (in the current subsection) to a particular 3152storage boundary. The first expression (which must be absolute) is the 3153alignment request in bytes. For example `.balign 8' advances the 3154location counter until it is a multiple of 8. If the location counter 3155is already a multiple of 8, no change is needed. 3156 3157 The second expression (also absolute) gives the fill value to be 3158stored in the padding bytes. It (and the comma) may be omitted. If it 3159is omitted, the padding bytes are normally zero. However, on some 3160systems, if the section is marked as containing code and the fill value 3161is omitted, the space is filled with no-op instructions. 3162 3163 The third expression is also absolute, and is also optional. If it 3164is present, it is the maximum number of bytes that should be skipped by 3165this alignment directive. If doing the alignment would require 3166skipping more bytes than the specified maximum, then the alignment is 3167not done at all. You can omit the fill value (the second argument) 3168entirely by simply using two commas after the required alignment; this 3169can be useful if you want the alignment to be filled with no-op 3170instructions when appropriate. 3171 3172 The `.balignw' and `.balignl' directives are variants of the 3173`.balign' directive. The `.balignw' directive treats the fill pattern 3174as a two byte word value. The `.balignl' directives treats the fill 3175pattern as a four byte longword value. For example, `.balignw 31764,0x368d' will align to a multiple of 4. If it skips two bytes, they 3177will be filled in with the value 0x368d (the exact placement of the 3178bytes depends upon the endianness of the processor). If it skips 1 or 31793 bytes, the fill value is undefined. 3180 3181 3182File: as.info, Node: Byte, Next: CFI directives, Prev: Balign, Up: Pseudo Ops 3183 31847.8 `.byte EXPRESSIONS' 3185======================= 3186 3187`.byte' expects zero or more expressions, separated by commas. Each 3188expression is assembled into the next byte. 3189 3190 3191File: as.info, Node: CFI directives, Next: Comm, Prev: Byte, Up: Pseudo Ops 3192 31937.9 `.cfi_sections SECTION_LIST' 3194================================ 3195 3196`.cfi_sections' may be used to specify whether CFI directives should 3197emit `.eh_frame' section and/or `.debug_frame' section. If 3198SECTION_LIST is `.eh_frame', `.eh_frame' is emitted, if SECTION_LIST is 3199`.debug_frame', `.debug_frame' is emitted. To emit both use 3200`.eh_frame, .debug_frame'. The default if this directive is not used 3201is `.cfi_sections .eh_frame'. 3202 32037.10 `.cfi_startproc [simple]' 3204============================== 3205 3206`.cfi_startproc' is used at the beginning of each function that should 3207have an entry in `.eh_frame'. It initializes some internal data 3208structures. Don't forget to close the function by `.cfi_endproc'. 3209 3210 Unless `.cfi_startproc' is used along with parameter `simple' it 3211also emits some architecture dependent initial CFI instructions. 3212 32137.11 `.cfi_endproc' 3214=================== 3215 3216`.cfi_endproc' is used at the end of a function where it closes its 3217unwind entry previously opened by `.cfi_startproc', and emits it to 3218`.eh_frame'. 3219 32207.12 `.cfi_personality ENCODING [, EXP]' 3221======================================== 3222 3223`.cfi_personality' defines personality routine and its encoding. 3224ENCODING must be a constant determining how the personality should be 3225encoded. If it is 255 (`DW_EH_PE_omit'), second argument is not 3226present, otherwise second argument should be a constant or a symbol 3227name. When using indirect encodings, the symbol provided should be the 3228location where personality can be loaded from, not the personality 3229routine itself. The default after `.cfi_startproc' is 3230`.cfi_personality 0xff', no personality routine. 3231 32327.13 `.cfi_lsda ENCODING [, EXP]' 3233================================= 3234 3235`.cfi_lsda' defines LSDA and its encoding. ENCODING must be a constant 3236determining how the LSDA should be encoded. If it is 255 3237(`DW_EH_PE_omit'), second argument is not present, otherwise second 3238argument should be a constant or a symbol name. The default after 3239`.cfi_startproc' is `.cfi_lsda 0xff', no LSDA. 3240 32417.14 `.cfi_def_cfa REGISTER, OFFSET' 3242==================================== 3243 3244`.cfi_def_cfa' defines a rule for computing CFA as: take address from 3245REGISTER and add OFFSET to it. 3246 32477.15 `.cfi_def_cfa_register REGISTER' 3248===================================== 3249 3250`.cfi_def_cfa_register' modifies a rule for computing CFA. From now on 3251REGISTER will be used instead of the old one. Offset remains the same. 3252 32537.16 `.cfi_def_cfa_offset OFFSET' 3254================================= 3255 3256`.cfi_def_cfa_offset' modifies a rule for computing CFA. Register 3257remains the same, but OFFSET is new. Note that it is the absolute 3258offset that will be added to a defined register to compute CFA address. 3259 32607.17 `.cfi_adjust_cfa_offset OFFSET' 3261==================================== 3262 3263Same as `.cfi_def_cfa_offset' but OFFSET is a relative value that is 3264added/substracted from the previous offset. 3265 32667.18 `.cfi_offset REGISTER, OFFSET' 3267=================================== 3268 3269Previous value of REGISTER is saved at offset OFFSET from CFA. 3270 32717.19 `.cfi_rel_offset REGISTER, OFFSET' 3272======================================= 3273 3274Previous value of REGISTER is saved at offset OFFSET from the current 3275CFA register. This is transformed to `.cfi_offset' using the known 3276displacement of the CFA register from the CFA. This is often easier to 3277use, because the number will match the code it's annotating. 3278 32797.20 `.cfi_register REGISTER1, REGISTER2' 3280========================================= 3281 3282Previous value of REGISTER1 is saved in register REGISTER2. 3283 32847.21 `.cfi_restore REGISTER' 3285============================ 3286 3287`.cfi_restore' says that the rule for REGISTER is now the same as it 3288was at the beginning of the function, after all initial instruction 3289added by `.cfi_startproc' were executed. 3290 32917.22 `.cfi_undefined REGISTER' 3292============================== 3293 3294From now on the previous value of REGISTER can't be restored anymore. 3295 32967.23 `.cfi_same_value REGISTER' 3297=============================== 3298 3299Current value of REGISTER is the same like in the previous frame, i.e. 3300no restoration needed. 3301 33027.24 `.cfi_remember_state', 3303=========================== 3304 3305First save all current rules for all registers by `.cfi_remember_state', 3306then totally screw them up by subsequent `.cfi_*' directives and when 3307everything is hopelessly bad, use `.cfi_restore_state' to restore the 3308previous saved state. 3309 33107.25 `.cfi_return_column REGISTER' 3311================================== 3312 3313Change return column REGISTER, i.e. the return address is either 3314directly in REGISTER or can be accessed by rules for REGISTER. 3315 33167.26 `.cfi_signal_frame' 3317======================== 3318 3319Mark current function as signal trampoline. 3320 33217.27 `.cfi_window_save' 3322======================= 3323 3324SPARC register window has been saved. 3325 33267.28 `.cfi_escape' EXPRESSION[, ...] 3327==================================== 3328 3329Allows the user to add arbitrary bytes to the unwind info. One might 3330use this to add OS-specific CFI opcodes, or generic CFI opcodes that 3331GAS does not yet support. 3332 33337.29 `.cfi_val_encoded_addr REGISTER, ENCODING, LABEL' 3334====================================================== 3335 3336The current value of REGISTER is LABEL. The value of LABEL will be 3337encoded in the output file according to ENCODING; see the description 3338of `.cfi_personality' for details on this encoding. 3339 3340 The usefulness of equating a register to a fixed label is probably 3341limited to the return address register. Here, it can be useful to mark 3342a code segment that has only one return address which is reached by a 3343direct branch and no copy of the return address exists in memory or 3344another register. 3345 3346 3347File: as.info, Node: Comm, Next: Data, Prev: CFI directives, Up: Pseudo Ops 3348 33497.30 `.comm SYMBOL , LENGTH ' 3350============================= 3351 3352`.comm' declares a common symbol named SYMBOL. When linking, a common 3353symbol in one object file may be merged with a defined or common symbol 3354of the same name in another object file. If `ld' does not see a 3355definition for the symbol-just one or more common symbols-then it will 3356allocate LENGTH bytes of uninitialized memory. LENGTH must be an 3357absolute expression. If `ld' sees multiple common symbols with the 3358same name, and they do not all have the same size, it will allocate 3359space using the largest size. 3360 3361 When using ELF or (as a GNU extension) PE, the `.comm' directive 3362takes an optional third argument. This is the desired alignment of the 3363symbol, specified for ELF as a byte boundary (for example, an alignment 3364of 16 means that the least significant 4 bits of the address should be 3365zero), and for PE as a power of two (for example, an alignment of 5 3366means aligned to a 32-byte boundary). The alignment must be an 3367absolute expression, and it must be a power of two. If `ld' allocates 3368uninitialized memory for the common symbol, it will use the alignment 3369when placing the symbol. If no alignment is specified, `as' will set 3370the alignment to the largest power of two less than or equal to the 3371size of the symbol, up to a maximum of 16 on ELF, or the default 3372section alignment of 4 on PE(1). 3373 3374 The syntax for `.comm' differs slightly on the HPPA. The syntax is 3375`SYMBOL .comm, LENGTH'; SYMBOL is optional. 3376 3377 ---------- Footnotes ---------- 3378 3379 (1) This is not the same as the executable image file alignment 3380controlled by `ld''s `--section-alignment' option; image file sections 3381in PE are aligned to multiples of 4096, which is far too large an 3382alignment for ordinary variables. It is rather the default alignment 3383for (non-debug) sections within object (`*.o') files, which are less 3384strictly aligned. 3385 3386 3387File: as.info, Node: Data, Next: Def, Prev: Comm, Up: Pseudo Ops 3388 33897.31 `.data SUBSECTION' 3390======================= 3391 3392`.data' tells `as' to assemble the following statements onto the end of 3393the data subsection numbered SUBSECTION (which is an absolute 3394expression). If SUBSECTION is omitted, it defaults to zero. 3395 3396 3397File: as.info, Node: Def, Next: Desc, Prev: Data, Up: Pseudo Ops 3398 33997.32 `.def NAME' 3400================ 3401 3402Begin defining debugging information for a symbol NAME; the definition 3403extends until the `.endef' directive is encountered. 3404 3405 3406File: as.info, Node: Desc, Next: Dim, Prev: Def, Up: Pseudo Ops 3407 34087.33 `.desc SYMBOL, ABS-EXPRESSION' 3409=================================== 3410 3411This directive sets the descriptor of the symbol (*note Symbol 3412Attributes::) to the low 16 bits of an absolute expression. 3413 3414 The `.desc' directive is not available when `as' is configured for 3415COFF output; it is only for `a.out' or `b.out' object format. For the 3416sake of compatibility, `as' accepts it, but produces no output, when 3417configured for COFF. 3418 3419 3420File: as.info, Node: Dim, Next: Double, Prev: Desc, Up: Pseudo Ops 3421 34227.34 `.dim' 3423=========== 3424 3425This directive is generated by compilers to include auxiliary debugging 3426information in the symbol table. It is only permitted inside 3427`.def'/`.endef' pairs. 3428 3429 3430File: as.info, Node: Double, Next: Eject, Prev: Dim, Up: Pseudo Ops 3431 34327.35 `.double FLONUMS' 3433====================== 3434 3435`.double' expects zero or more flonums, separated by commas. It 3436assembles floating point numbers. The exact kind of floating point 3437numbers emitted depends on how `as' is configured. *Note Machine 3438Dependencies::. 3439 3440 3441File: as.info, Node: Eject, Next: Else, Prev: Double, Up: Pseudo Ops 3442 34437.36 `.eject' 3444============= 3445 3446Force a page break at this point, when generating assembly listings. 3447 3448 3449File: as.info, Node: Else, Next: Elseif, Prev: Eject, Up: Pseudo Ops 3450 34517.37 `.else' 3452============ 3453 3454`.else' is part of the `as' support for conditional assembly; see *note 3455`.if': If. It marks the beginning of a section of code to be assembled 3456if the condition for the preceding `.if' was false. 3457 3458 3459File: as.info, Node: Elseif, Next: End, Prev: Else, Up: Pseudo Ops 3460 34617.38 `.elseif' 3462============== 3463 3464`.elseif' is part of the `as' support for conditional assembly; see 3465*note `.if': If. It is shorthand for beginning a new `.if' block that 3466would otherwise fill the entire `.else' section. 3467 3468 3469File: as.info, Node: End, Next: Endef, Prev: Elseif, Up: Pseudo Ops 3470 34717.39 `.end' 3472=========== 3473 3474`.end' marks the end of the assembly file. `as' does not process 3475anything in the file past the `.end' directive. 3476 3477 3478File: as.info, Node: Endef, Next: Endfunc, Prev: End, Up: Pseudo Ops 3479 34807.40 `.endef' 3481============= 3482 3483This directive flags the end of a symbol definition begun with `.def'. 3484 3485 3486File: as.info, Node: Endfunc, Next: Endif, Prev: Endef, Up: Pseudo Ops 3487 34887.41 `.endfunc' 3489=============== 3490 3491`.endfunc' marks the end of a function specified with `.func'. 3492 3493 3494File: as.info, Node: Endif, Next: Equ, Prev: Endfunc, Up: Pseudo Ops 3495 34967.42 `.endif' 3497============= 3498 3499`.endif' is part of the `as' support for conditional assembly; it marks 3500the end of a block of code that is only assembled conditionally. *Note 3501`.if': If. 3502 3503 3504File: as.info, Node: Equ, Next: Equiv, Prev: Endif, Up: Pseudo Ops 3505 35067.43 `.equ SYMBOL, EXPRESSION' 3507============================== 3508 3509This directive sets the value of SYMBOL to EXPRESSION. It is 3510synonymous with `.set'; see *note `.set': Set. 3511 3512 The syntax for `equ' on the HPPA is `SYMBOL .equ EXPRESSION'. 3513 3514 The syntax for `equ' on the Z80 is `SYMBOL equ EXPRESSION'. On the 3515Z80 it is an eror if SYMBOL is already defined, but the symbol is not 3516protected from later redefinition. Compare *note Equiv::. 3517 3518 3519File: as.info, Node: Equiv, Next: Eqv, Prev: Equ, Up: Pseudo Ops 3520 35217.44 `.equiv SYMBOL, EXPRESSION' 3522================================ 3523 3524The `.equiv' directive is like `.equ' and `.set', except that the 3525assembler will signal an error if SYMBOL is already defined. Note a 3526symbol which has been referenced but not actually defined is considered 3527to be undefined. 3528 3529 Except for the contents of the error message, this is roughly 3530equivalent to 3531 .ifdef SYM 3532 .err 3533 .endif 3534 .equ SYM,VAL 3535 plus it protects the symbol from later redefinition. 3536 3537 3538File: as.info, Node: Eqv, Next: Err, Prev: Equiv, Up: Pseudo Ops 3539 35407.45 `.eqv SYMBOL, EXPRESSION' 3541============================== 3542 3543The `.eqv' directive is like `.equiv', but no attempt is made to 3544evaluate the expression or any part of it immediately. Instead each 3545time the resulting symbol is used in an expression, a snapshot of its 3546current value is taken. 3547 3548 3549File: as.info, Node: Err, Next: Error, Prev: Eqv, Up: Pseudo Ops 3550 35517.46 `.err' 3552=========== 3553 3554If `as' assembles a `.err' directive, it will print an error message 3555and, unless the `-Z' option was used, it will not generate an object 3556file. This can be used to signal an error in conditionally compiled 3557code. 3558 3559 3560File: as.info, Node: Error, Next: Exitm, Prev: Err, Up: Pseudo Ops 3561 35627.47 `.error "STRING"' 3563====================== 3564 3565Similarly to `.err', this directive emits an error, but you can specify 3566a string that will be emitted as the error message. If you don't 3567specify the message, it defaults to `".error directive invoked in 3568source file"'. *Note Error and Warning Messages: Errors. 3569 3570 .error "This code has not been assembled and tested." 3571 3572 3573File: as.info, Node: Exitm, Next: Extern, Prev: Error, Up: Pseudo Ops 3574 35757.48 `.exitm' 3576============= 3577 3578Exit early from the current macro definition. *Note Macro::. 3579 3580 3581File: as.info, Node: Extern, Next: Fail, Prev: Exitm, Up: Pseudo Ops 3582 35837.49 `.extern' 3584============== 3585 3586`.extern' is accepted in the source program--for compatibility with 3587other assemblers--but it is ignored. `as' treats all undefined symbols 3588as external. 3589 3590 3591File: as.info, Node: Fail, Next: File, Prev: Extern, Up: Pseudo Ops 3592 35937.50 `.fail EXPRESSION' 3594======================= 3595 3596Generates an error or a warning. If the value of the EXPRESSION is 500 3597or more, `as' will print a warning message. If the value is less than 3598500, `as' will print an error message. The message will include the 3599value of EXPRESSION. This can occasionally be useful inside complex 3600nested macros or conditional assembly. 3601 3602 3603File: as.info, Node: File, Next: Fill, Prev: Fail, Up: Pseudo Ops 3604 36057.51 `.file' 3606============ 3607 3608There are two different versions of the `.file' directive. Targets 3609that support DWARF2 line number information use the DWARF2 version of 3610`.file'. Other targets use the default version. 3611 3612Default Version 3613--------------- 3614 3615This version of the `.file' directive tells `as' that we are about to 3616start a new logical file. The syntax is: 3617 3618 .file STRING 3619 3620 STRING is the new file name. In general, the filename is recognized 3621whether or not it is surrounded by quotes `"'; but if you wish to 3622specify an empty file name, you must give the quotes-`""'. This 3623statement may go away in future: it is only recognized to be compatible 3624with old `as' programs. 3625 3626DWARF2 Version 3627-------------- 3628 3629When emitting DWARF2 line number information, `.file' assigns filenames 3630to the `.debug_line' file name table. The syntax is: 3631 3632 .file FILENO FILENAME 3633 3634 The FILENO operand should be a unique positive integer to use as the 3635index of the entry in the table. The FILENAME operand is a C string 3636literal. 3637 3638 The detail of filename indices is exposed to the user because the 3639filename table is shared with the `.debug_info' section of the DWARF2 3640debugging information, and thus the user must know the exact indices 3641that table entries will have. 3642 3643 3644File: as.info, Node: Fill, Next: Float, Prev: File, Up: Pseudo Ops 3645 36467.52 `.fill REPEAT , SIZE , VALUE' 3647================================== 3648 3649REPEAT, SIZE and VALUE are absolute expressions. This emits REPEAT 3650copies of SIZE bytes. REPEAT may be zero or more. SIZE may be zero or 3651more, but if it is more than 8, then it is deemed to have the value 8, 3652compatible with other people's assemblers. The contents of each REPEAT 3653bytes is taken from an 8-byte number. The highest order 4 bytes are 3654zero. The lowest order 4 bytes are VALUE rendered in the byte-order of 3655an integer on the computer `as' is assembling for. Each SIZE bytes in 3656a repetition is taken from the lowest order SIZE bytes of this number. 3657Again, this bizarre behavior is compatible with other people's 3658assemblers. 3659 3660 SIZE and VALUE are optional. If the second comma and VALUE are 3661absent, VALUE is assumed zero. If the first comma and following tokens 3662are absent, SIZE is assumed to be 1. 3663 3664 3665File: as.info, Node: Float, Next: Func, Prev: Fill, Up: Pseudo Ops 3666 36677.53 `.float FLONUMS' 3668===================== 3669 3670This directive assembles zero or more flonums, separated by commas. It 3671has the same effect as `.single'. The exact kind of floating point 3672numbers emitted depends on how `as' is configured. *Note Machine 3673Dependencies::. 3674 3675 3676File: as.info, Node: Func, Next: Global, Prev: Float, Up: Pseudo Ops 3677 36787.54 `.func NAME[,LABEL]' 3679========================= 3680 3681`.func' emits debugging information to denote function NAME, and is 3682ignored unless the file is assembled with debugging enabled. Only 3683`--gstabs[+]' is currently supported. LABEL is the entry point of the 3684function and if omitted NAME prepended with the `leading char' is used. 3685`leading char' is usually `_' or nothing, depending on the target. All 3686functions are currently defined to have `void' return type. The 3687function must be terminated with `.endfunc'. 3688 3689 3690File: as.info, Node: Global, Next: Gnu_attribute, Prev: Func, Up: Pseudo Ops 3691 36927.55 `.global SYMBOL', `.globl SYMBOL' 3693====================================== 3694 3695`.global' makes the symbol visible to `ld'. If you define SYMBOL in 3696your partial program, its value is made available to other partial 3697programs that are linked with it. Otherwise, SYMBOL takes its 3698attributes from a symbol of the same name from another file linked into 3699the same program. 3700 3701 Both spellings (`.globl' and `.global') are accepted, for 3702compatibility with other assemblers. 3703 3704 On the HPPA, `.global' is not always enough to make it accessible to 3705other partial programs. You may need the HPPA-only `.EXPORT' directive 3706as well. *Note HPPA Assembler Directives: HPPA Directives. 3707 3708 3709File: as.info, Node: Gnu_attribute, Next: Hidden, Prev: Global, Up: Pseudo Ops 3710 37117.56 `.gnu_attribute TAG,VALUE' 3712=============================== 3713 3714Record a GNU object attribute for this file. *Note Object Attributes::. 3715 3716 3717File: as.info, Node: Hidden, Next: hword, Prev: Gnu_attribute, Up: Pseudo Ops 3718 37197.57 `.hidden NAMES' 3720==================== 3721 3722This is one of the ELF visibility directives. The other two are 3723`.internal' (*note `.internal': Internal.) and `.protected' (*note 3724`.protected': Protected.). 3725 3726 This directive overrides the named symbols default visibility (which 3727is set by their binding: local, global or weak). The directive sets 3728the visibility to `hidden' which means that the symbols are not visible 3729to other components. Such symbols are always considered to be 3730`protected' as well. 3731 3732 3733File: as.info, Node: hword, Next: Ident, Prev: Hidden, Up: Pseudo Ops 3734 37357.58 `.hword EXPRESSIONS' 3736========================= 3737 3738This expects zero or more EXPRESSIONS, and emits a 16 bit number for 3739each. 3740 3741 This directive is a synonym for `.short'; depending on the target 3742architecture, it may also be a synonym for `.word'. 3743 3744 3745File: as.info, Node: Ident, Next: If, Prev: hword, Up: Pseudo Ops 3746 37477.59 `.ident' 3748============= 3749 3750This directive is used by some assemblers to place tags in object 3751files. The behavior of this directive varies depending on the target. 3752When using the a.out object file format, `as' simply accepts the 3753directive for source-file compatibility with existing assemblers, but 3754does not emit anything for it. When using COFF, comments are emitted 3755to the `.comment' or `.rdata' section, depending on the target. When 3756using ELF, comments are emitted to the `.comment' section. 3757 3758 3759File: as.info, Node: If, Next: Incbin, Prev: Ident, Up: Pseudo Ops 3760 37617.60 `.if ABSOLUTE EXPRESSION' 3762============================== 3763 3764`.if' marks the beginning of a section of code which is only considered 3765part of the source program being assembled if the argument (which must 3766be an ABSOLUTE EXPRESSION) is non-zero. The end of the conditional 3767section of code must be marked by `.endif' (*note `.endif': Endif.); 3768optionally, you may include code for the alternative condition, flagged 3769by `.else' (*note `.else': Else.). If you have several conditions to 3770check, `.elseif' may be used to avoid nesting blocks if/else within 3771each subsequent `.else' block. 3772 3773 The following variants of `.if' are also supported: 3774`.ifdef SYMBOL' 3775 Assembles the following section of code if the specified SYMBOL 3776 has been defined. Note a symbol which has been referenced but not 3777 yet defined is considered to be undefined. 3778 3779`.ifb TEXT' 3780 Assembles the following section of code if the operand is blank 3781 (empty). 3782 3783`.ifc STRING1,STRING2' 3784 Assembles the following section of code if the two strings are the 3785 same. The strings may be optionally quoted with single quotes. 3786 If they are not quoted, the first string stops at the first comma, 3787 and the second string stops at the end of the line. Strings which 3788 contain whitespace should be quoted. The string comparison is 3789 case sensitive. 3790 3791`.ifeq ABSOLUTE EXPRESSION' 3792 Assembles the following section of code if the argument is zero. 3793 3794`.ifeqs STRING1,STRING2' 3795 Another form of `.ifc'. The strings must be quoted using double 3796 quotes. 3797 3798`.ifge ABSOLUTE EXPRESSION' 3799 Assembles the following section of code if the argument is greater 3800 than or equal to zero. 3801 3802`.ifgt ABSOLUTE EXPRESSION' 3803 Assembles the following section of code if the argument is greater 3804 than zero. 3805 3806`.ifle ABSOLUTE EXPRESSION' 3807 Assembles the following section of code if the argument is less 3808 than or equal to zero. 3809 3810`.iflt ABSOLUTE EXPRESSION' 3811 Assembles the following section of code if the argument is less 3812 than zero. 3813 3814`.ifnb TEXT' 3815 Like `.ifb', but the sense of the test is reversed: this assembles 3816 the following section of code if the operand is non-blank 3817 (non-empty). 3818 3819`.ifnc STRING1,STRING2.' 3820 Like `.ifc', but the sense of the test is reversed: this assembles 3821 the following section of code if the two strings are not the same. 3822 3823`.ifndef SYMBOL' 3824`.ifnotdef SYMBOL' 3825 Assembles the following section of code if the specified SYMBOL 3826 has not been defined. Both spelling variants are equivalent. 3827 Note a symbol which has been referenced but not yet defined is 3828 considered to be undefined. 3829 3830`.ifne ABSOLUTE EXPRESSION' 3831 Assembles the following section of code if the argument is not 3832 equal to zero (in other words, this is equivalent to `.if'). 3833 3834`.ifnes STRING1,STRING2' 3835 Like `.ifeqs', but the sense of the test is reversed: this 3836 assembles the following section of code if the two strings are not 3837 the same. 3838 3839 3840File: as.info, Node: Incbin, Next: Include, Prev: If, Up: Pseudo Ops 3841 38427.61 `.incbin "FILE"[,SKIP[,COUNT]]' 3843==================================== 3844 3845The `incbin' directive includes FILE verbatim at the current location. 3846You can control the search paths used with the `-I' command-line option 3847(*note Command-Line Options: Invoking.). Quotation marks are required 3848around FILE. 3849 3850 The SKIP argument skips a number of bytes from the start of the 3851FILE. The COUNT argument indicates the maximum number of bytes to 3852read. Note that the data is not aligned in any way, so it is the user's 3853responsibility to make sure that proper alignment is provided both 3854before and after the `incbin' directive. 3855 3856 3857File: as.info, Node: Include, Next: Int, Prev: Incbin, Up: Pseudo Ops 3858 38597.62 `.include "FILE"' 3860====================== 3861 3862This directive provides a way to include supporting files at specified 3863points in your source program. The code from FILE is assembled as if 3864it followed the point of the `.include'; when the end of the included 3865file is reached, assembly of the original file continues. You can 3866control the search paths used with the `-I' command-line option (*note 3867Command-Line Options: Invoking.). Quotation marks are required around 3868FILE. 3869 3870 3871File: as.info, Node: Int, Next: Internal, Prev: Include, Up: Pseudo Ops 3872 38737.63 `.int EXPRESSIONS' 3874======================= 3875 3876Expect zero or more EXPRESSIONS, of any section, separated by commas. 3877For each expression, emit a number that, at run time, is the value of 3878that expression. The byte order and bit size of the number depends on 3879what kind of target the assembly is for. 3880 3881 3882File: as.info, Node: Internal, Next: Irp, Prev: Int, Up: Pseudo Ops 3883 38847.64 `.internal NAMES' 3885====================== 3886 3887This is one of the ELF visibility directives. The other two are 3888`.hidden' (*note `.hidden': Hidden.) and `.protected' (*note 3889`.protected': Protected.). 3890 3891 This directive overrides the named symbols default visibility (which 3892is set by their binding: local, global or weak). The directive sets 3893the visibility to `internal' which means that the symbols are 3894considered to be `hidden' (i.e., not visible to other components), and 3895that some extra, processor specific processing must also be performed 3896upon the symbols as well. 3897 3898 3899File: as.info, Node: Irp, Next: Irpc, Prev: Internal, Up: Pseudo Ops 3900 39017.65 `.irp SYMBOL,VALUES'... 3902============================ 3903 3904Evaluate a sequence of statements assigning different values to SYMBOL. 3905The sequence of statements starts at the `.irp' directive, and is 3906terminated by an `.endr' directive. For each VALUE, SYMBOL is set to 3907VALUE, and the sequence of statements is assembled. If no VALUE is 3908listed, the sequence of statements is assembled once, with SYMBOL set 3909to the null string. To refer to SYMBOL within the sequence of 3910statements, use \SYMBOL. 3911 3912 For example, assembling 3913 3914 .irp param,1,2,3 3915 move d\param,sp@- 3916 .endr 3917 3918 is equivalent to assembling 3919 3920 move d1,sp@- 3921 move d2,sp@- 3922 move d3,sp@- 3923 3924 For some caveats with the spelling of SYMBOL, see also *note Macro::. 3925 3926 3927File: as.info, Node: Irpc, Next: Lcomm, Prev: Irp, Up: Pseudo Ops 3928 39297.66 `.irpc SYMBOL,VALUES'... 3930============================= 3931 3932Evaluate a sequence of statements assigning different values to SYMBOL. 3933The sequence of statements starts at the `.irpc' directive, and is 3934terminated by an `.endr' directive. For each character in VALUE, 3935SYMBOL is set to the character, and the sequence of statements is 3936assembled. If no VALUE is listed, the sequence of statements is 3937assembled once, with SYMBOL set to the null string. To refer to SYMBOL 3938within the sequence of statements, use \SYMBOL. 3939 3940 For example, assembling 3941 3942 .irpc param,123 3943 move d\param,sp@- 3944 .endr 3945 3946 is equivalent to assembling 3947 3948 move d1,sp@- 3949 move d2,sp@- 3950 move d3,sp@- 3951 3952 For some caveats with the spelling of SYMBOL, see also the discussion 3953at *Note Macro::. 3954 3955 3956File: as.info, Node: Lcomm, Next: Lflags, Prev: Irpc, Up: Pseudo Ops 3957 39587.67 `.lcomm SYMBOL , LENGTH' 3959============================= 3960 3961Reserve LENGTH (an absolute expression) bytes for a local common 3962denoted by SYMBOL. The section and value of SYMBOL are those of the 3963new local common. The addresses are allocated in the bss section, so 3964that at run-time the bytes start off zeroed. SYMBOL is not declared 3965global (*note `.global': Global.), so is normally not visible to `ld'. 3966 3967 Some targets permit a third argument to be used with `.lcomm'. This 3968argument specifies the desired alignment of the symbol in the bss 3969section. 3970 3971 The syntax for `.lcomm' differs slightly on the HPPA. The syntax is 3972`SYMBOL .lcomm, LENGTH'; SYMBOL is optional. 3973 3974 3975File: as.info, Node: Lflags, Next: Line, Prev: Lcomm, Up: Pseudo Ops 3976 39777.68 `.lflags' 3978============== 3979 3980`as' accepts this directive, for compatibility with other assemblers, 3981but ignores it. 3982 3983 3984File: as.info, Node: Line, Next: Linkonce, Prev: Lflags, Up: Pseudo Ops 3985 39867.69 `.line LINE-NUMBER' 3987======================== 3988 3989Change the logical line number. LINE-NUMBER must be an absolute 3990expression. The next line has that logical line number. Therefore any 3991other statements on the current line (after a statement separator 3992character) are reported as on logical line number LINE-NUMBER - 1. One 3993day `as' will no longer support this directive: it is recognized only 3994for compatibility with existing assembler programs. 3995 3996Even though this is a directive associated with the `a.out' or `b.out' 3997object-code formats, `as' still recognizes it when producing COFF 3998output, and treats `.line' as though it were the COFF `.ln' _if_ it is 3999found outside a `.def'/`.endef' pair. 4000 4001 Inside a `.def', `.line' is, instead, one of the directives used by 4002compilers to generate auxiliary symbol information for debugging. 4003 4004 4005File: as.info, Node: Linkonce, Next: List, Prev: Line, Up: Pseudo Ops 4006 40077.70 `.linkonce [TYPE]' 4008======================= 4009 4010Mark the current section so that the linker only includes a single copy 4011of it. This may be used to include the same section in several 4012different object files, but ensure that the linker will only include it 4013once in the final output file. The `.linkonce' pseudo-op must be used 4014for each instance of the section. Duplicate sections are detected 4015based on the section name, so it should be unique. 4016 4017 This directive is only supported by a few object file formats; as of 4018this writing, the only object file format which supports it is the 4019Portable Executable format used on Windows NT. 4020 4021 The TYPE argument is optional. If specified, it must be one of the 4022following strings. For example: 4023 .linkonce same_size 4024 Not all types may be supported on all object file formats. 4025 4026`discard' 4027 Silently discard duplicate sections. This is the default. 4028 4029`one_only' 4030 Warn if there are duplicate sections, but still keep only one copy. 4031 4032`same_size' 4033 Warn if any of the duplicates have different sizes. 4034 4035`same_contents' 4036 Warn if any of the duplicates do not have exactly the same 4037 contents. 4038 4039 4040File: as.info, Node: List, Next: Ln, Prev: Linkonce, Up: Pseudo Ops 4041 40427.71 `.list' 4043============ 4044 4045Control (in conjunction with the `.nolist' directive) whether or not 4046assembly listings are generated. These two directives maintain an 4047internal counter (which is zero initially). `.list' increments the 4048counter, and `.nolist' decrements it. Assembly listings are generated 4049whenever the counter is greater than zero. 4050 4051 By default, listings are disabled. When you enable them (with the 4052`-a' command line option; *note Command-Line Options: Invoking.), the 4053initial value of the listing counter is one. 4054 4055 4056File: as.info, Node: Ln, Next: Loc, Prev: List, Up: Pseudo Ops 4057 40587.72 `.ln LINE-NUMBER' 4059====================== 4060 4061`.ln' is a synonym for `.line'. 4062 4063 4064File: as.info, Node: Loc, Next: Loc_mark_labels, Prev: Ln, Up: Pseudo Ops 4065 40667.73 `.loc FILENO LINENO [COLUMN] [OPTIONS]' 4067============================================ 4068 4069When emitting DWARF2 line number information, the `.loc' directive will 4070add a row to the `.debug_line' line number matrix corresponding to the 4071immediately following assembly instruction. The FILENO, LINENO, and 4072optional COLUMN arguments will be applied to the `.debug_line' state 4073machine before the row is added. 4074 4075 The OPTIONS are a sequence of the following tokens in any order: 4076 4077`basic_block' 4078 This option will set the `basic_block' register in the 4079 `.debug_line' state machine to `true'. 4080 4081`prologue_end' 4082 This option will set the `prologue_end' register in the 4083 `.debug_line' state machine to `true'. 4084 4085`epilogue_begin' 4086 This option will set the `epilogue_begin' register in the 4087 `.debug_line' state machine to `true'. 4088 4089`is_stmt VALUE' 4090 This option will set the `is_stmt' register in the `.debug_line' 4091 state machine to `value', which must be either 0 or 1. 4092 4093`isa VALUE' 4094 This directive will set the `isa' register in the `.debug_line' 4095 state machine to VALUE, which must be an unsigned integer. 4096 4097`discriminator VALUE' 4098 This directive will set the `discriminator' register in the 4099 `.debug_line' state machine to VALUE, which must be an unsigned 4100 integer. 4101 4102 4103 4104File: as.info, Node: Loc_mark_labels, Next: Local, Prev: Loc, Up: Pseudo Ops 4105 41067.74 `.loc_mark_labels ENABLE' 4107============================== 4108 4109When emitting DWARF2 line number information, the `.loc_mark_labels' 4110directive makes the assembler emit an entry to the `.debug_line' line 4111number matrix with the `basic_block' register in the state machine set 4112whenever a code label is seen. The ENABLE argument should be either 1 4113or 0, to enable or disable this function respectively. 4114 4115 4116File: as.info, Node: Local, Next: Long, Prev: Loc_mark_labels, Up: Pseudo Ops 4117 41187.75 `.local NAMES' 4119=================== 4120 4121This directive, which is available for ELF targets, marks each symbol in 4122the comma-separated list of `names' as a local symbol so that it will 4123not be externally visible. If the symbols do not already exist, they 4124will be created. 4125 4126 For targets where the `.lcomm' directive (*note Lcomm::) does not 4127accept an alignment argument, which is the case for most ELF targets, 4128the `.local' directive can be used in combination with `.comm' (*note 4129Comm::) to define aligned local common data. 4130 4131 4132File: as.info, Node: Long, Next: Macro, Prev: Local, Up: Pseudo Ops 4133 41347.76 `.long EXPRESSIONS' 4135======================== 4136 4137`.long' is the same as `.int'. *Note `.int': Int. 4138 4139 4140File: as.info, Node: Macro, Next: MRI, Prev: Long, Up: Pseudo Ops 4141 41427.77 `.macro' 4143============= 4144 4145The commands `.macro' and `.endm' allow you to define macros that 4146generate assembly output. For example, this definition specifies a 4147macro `sum' that puts a sequence of numbers into memory: 4148 4149 .macro sum from=0, to=5 4150 .long \from 4151 .if \to-\from 4152 sum "(\from+1)",\to 4153 .endif 4154 .endm 4155 4156With that definition, `SUM 0,5' is equivalent to this assembly input: 4157 4158 .long 0 4159 .long 1 4160 .long 2 4161 .long 3 4162 .long 4 4163 .long 5 4164 4165`.macro MACNAME' 4166`.macro MACNAME MACARGS ...' 4167 Begin the definition of a macro called MACNAME. If your macro 4168 definition requires arguments, specify their names after the macro 4169 name, separated by commas or spaces. You can qualify the macro 4170 argument to indicate whether all invocations must specify a 4171 non-blank value (through `:`req''), or whether it takes all of the 4172 remaining arguments (through `:`vararg''). You can supply a 4173 default value for any macro argument by following the name with 4174 `=DEFLT'. You cannot define two macros with the same MACNAME 4175 unless it has been subject to the `.purgem' directive (*note 4176 Purgem::) between the two definitions. For example, these are all 4177 valid `.macro' statements: 4178 4179 `.macro comm' 4180 Begin the definition of a macro called `comm', which takes no 4181 arguments. 4182 4183 `.macro plus1 p, p1' 4184 `.macro plus1 p p1' 4185 Either statement begins the definition of a macro called 4186 `plus1', which takes two arguments; within the macro 4187 definition, write `\p' or `\p1' to evaluate the arguments. 4188 4189 `.macro reserve_str p1=0 p2' 4190 Begin the definition of a macro called `reserve_str', with two 4191 arguments. The first argument has a default value, but not 4192 the second. After the definition is complete, you can call 4193 the macro either as `reserve_str A,B' (with `\p1' evaluating 4194 to A and `\p2' evaluating to B), or as `reserve_str ,B' (with 4195 `\p1' evaluating as the default, in this case `0', and `\p2' 4196 evaluating to B). 4197 4198 `.macro m p1:req, p2=0, p3:vararg' 4199 Begin the definition of a macro called `m', with at least 4200 three arguments. The first argument must always have a value 4201 specified, but not the second, which instead has a default 4202 value. The third formal will get assigned all remaining 4203 arguments specified at invocation time. 4204 4205 When you call a macro, you can specify the argument values 4206 either by position, or by keyword. For example, `sum 9,17' 4207 is equivalent to `sum to=17, from=9'. 4208 4209 4210 Note that since each of the MACARGS can be an identifier exactly 4211 as any other one permitted by the target architecture, there may be 4212 occasional problems if the target hand-crafts special meanings to 4213 certain characters when they occur in a special position. For 4214 example, if the colon (`:') is generally permitted to be part of a 4215 symbol name, but the architecture specific code special-cases it 4216 when occurring as the final character of a symbol (to denote a 4217 label), then the macro parameter replacement code will have no way 4218 of knowing that and consider the whole construct (including the 4219 colon) an identifier, and check only this identifier for being the 4220 subject to parameter substitution. So for example this macro 4221 definition: 4222 4223 .macro label l 4224 \l: 4225 .endm 4226 4227 might not work as expected. Invoking `label foo' might not create 4228 a label called `foo' but instead just insert the text `\l:' into 4229 the assembler source, probably generating an error about an 4230 unrecognised identifier. 4231 4232 Similarly problems might occur with the period character (`.') 4233 which is often allowed inside opcode names (and hence identifier 4234 names). So for example constructing a macro to build an opcode 4235 from a base name and a length specifier like this: 4236 4237 .macro opcode base length 4238 \base.\length 4239 .endm 4240 4241 and invoking it as `opcode store l' will not create a `store.l' 4242 instruction but instead generate some kind of error as the 4243 assembler tries to interpret the text `\base.\length'. 4244 4245 There are several possible ways around this problem: 4246 4247 `Insert white space' 4248 If it is possible to use white space characters then this is 4249 the simplest solution. eg: 4250 4251 .macro label l 4252 \l : 4253 .endm 4254 4255 `Use `\()'' 4256 The string `\()' can be used to separate the end of a macro 4257 argument from the following text. eg: 4258 4259 .macro opcode base length 4260 \base\().\length 4261 .endm 4262 4263 `Use the alternate macro syntax mode' 4264 In the alternative macro syntax mode the ampersand character 4265 (`&') can be used as a separator. eg: 4266 4267 .altmacro 4268 .macro label l 4269 l&: 4270 .endm 4271 4272 Note: this problem of correctly identifying string parameters to 4273 pseudo ops also applies to the identifiers used in `.irp' (*note 4274 Irp::) and `.irpc' (*note Irpc::) as well. 4275 4276`.endm' 4277 Mark the end of a macro definition. 4278 4279`.exitm' 4280 Exit early from the current macro definition. 4281 4282`\@' 4283 `as' maintains a counter of how many macros it has executed in 4284 this pseudo-variable; you can copy that number to your output with 4285 `\@', but _only within a macro definition_. 4286 4287`LOCAL NAME [ , ... ]' 4288 _Warning: `LOCAL' is only available if you select "alternate macro 4289 syntax" with `--alternate' or `.altmacro'._ *Note `.altmacro': 4290 Altmacro. 4291 4292 4293File: as.info, Node: MRI, Next: Noaltmacro, Prev: Macro, Up: Pseudo Ops 4294 42957.78 `.mri VAL' 4296=============== 4297 4298If VAL is non-zero, this tells `as' to enter MRI mode. If VAL is zero, 4299this tells `as' to exit MRI mode. This change affects code assembled 4300until the next `.mri' directive, or until the end of the file. *Note 4301MRI mode: M. 4302 4303 4304File: as.info, Node: Noaltmacro, Next: Nolist, Prev: MRI, Up: Pseudo Ops 4305 43067.79 `.noaltmacro' 4307================== 4308 4309Disable alternate macro mode. *Note Altmacro::. 4310 4311 4312File: as.info, Node: Nolist, Next: Octa, Prev: Noaltmacro, Up: Pseudo Ops 4313 43147.80 `.nolist' 4315============== 4316 4317Control (in conjunction with the `.list' directive) whether or not 4318assembly listings are generated. These two directives maintain an 4319internal counter (which is zero initially). `.list' increments the 4320counter, and `.nolist' decrements it. Assembly listings are generated 4321whenever the counter is greater than zero. 4322 4323 4324File: as.info, Node: Octa, Next: Offset, Prev: Nolist, Up: Pseudo Ops 4325 43267.81 `.octa BIGNUMS' 4327==================== 4328 4329This directive expects zero or more bignums, separated by commas. For 4330each bignum, it emits a 16-byte integer. 4331 4332 The term "octa" comes from contexts in which a "word" is two bytes; 4333hence _octa_-word for 16 bytes. 4334 4335 4336File: as.info, Node: Offset, Next: Org, Prev: Octa, Up: Pseudo Ops 4337 43387.82 `.offset LOC' 4339================== 4340 4341Set the location counter to LOC in the absolute section. LOC must be 4342an absolute expression. This directive may be useful for defining 4343symbols with absolute values. Do not confuse it with the `.org' 4344directive. 4345 4346 4347File: as.info, Node: Org, Next: P2align, Prev: Offset, Up: Pseudo Ops 4348 43497.83 `.org NEW-LC , FILL' 4350========================= 4351 4352Advance the location counter of the current section to NEW-LC. NEW-LC 4353is either an absolute expression or an expression with the same section 4354as the current subsection. That is, you can't use `.org' to cross 4355sections: if NEW-LC has the wrong section, the `.org' directive is 4356ignored. To be compatible with former assemblers, if the section of 4357NEW-LC is absolute, `as' issues a warning, then pretends the section of 4358NEW-LC is the same as the current subsection. 4359 4360 `.org' may only increase the location counter, or leave it 4361unchanged; you cannot use `.org' to move the location counter backwards. 4362 4363 Because `as' tries to assemble programs in one pass, NEW-LC may not 4364be undefined. If you really detest this restriction we eagerly await a 4365chance to share your improved assembler. 4366 4367 Beware that the origin is relative to the start of the section, not 4368to the start of the subsection. This is compatible with other people's 4369assemblers. 4370 4371 When the location counter (of the current subsection) is advanced, 4372the intervening bytes are filled with FILL which should be an absolute 4373expression. If the comma and FILL are omitted, FILL defaults to zero. 4374 4375 4376File: as.info, Node: P2align, Next: PopSection, Prev: Org, Up: Pseudo Ops 4377 43787.84 `.p2align[wl] ABS-EXPR, ABS-EXPR, ABS-EXPR' 4379================================================ 4380 4381Pad the location counter (in the current subsection) to a particular 4382storage boundary. The first expression (which must be absolute) is the 4383number of low-order zero bits the location counter must have after 4384advancement. For example `.p2align 3' advances the location counter 4385until it a multiple of 8. If the location counter is already a 4386multiple of 8, no change is needed. 4387 4388 The second expression (also absolute) gives the fill value to be 4389stored in the padding bytes. It (and the comma) may be omitted. If it 4390is omitted, the padding bytes are normally zero. However, on some 4391systems, if the section is marked as containing code and the fill value 4392is omitted, the space is filled with no-op instructions. 4393 4394 The third expression is also absolute, and is also optional. If it 4395is present, it is the maximum number of bytes that should be skipped by 4396this alignment directive. If doing the alignment would require 4397skipping more bytes than the specified maximum, then the alignment is 4398not done at all. You can omit the fill value (the second argument) 4399entirely by simply using two commas after the required alignment; this 4400can be useful if you want the alignment to be filled with no-op 4401instructions when appropriate. 4402 4403 The `.p2alignw' and `.p2alignl' directives are variants of the 4404`.p2align' directive. The `.p2alignw' directive treats the fill 4405pattern as a two byte word value. The `.p2alignl' directives treats the 4406fill pattern as a four byte longword value. For example, `.p2alignw 44072,0x368d' will align to a multiple of 4. If it skips two bytes, they 4408will be filled in with the value 0x368d (the exact placement of the 4409bytes depends upon the endianness of the processor). If it skips 1 or 44103 bytes, the fill value is undefined. 4411 4412 4413File: as.info, Node: PopSection, Next: Previous, Prev: P2align, Up: Pseudo Ops 4414 44157.85 `.popsection' 4416================== 4417 4418This is one of the ELF section stack manipulation directives. The 4419others are `.section' (*note Section::), `.subsection' (*note 4420SubSection::), `.pushsection' (*note PushSection::), and `.previous' 4421(*note Previous::). 4422 4423 This directive replaces the current section (and subsection) with 4424the top section (and subsection) on the section stack. This section is 4425popped off the stack. 4426 4427 4428File: as.info, Node: Previous, Next: Print, Prev: PopSection, Up: Pseudo Ops 4429 44307.86 `.previous' 4431================ 4432 4433This is one of the ELF section stack manipulation directives. The 4434others are `.section' (*note Section::), `.subsection' (*note 4435SubSection::), `.pushsection' (*note PushSection::), and `.popsection' 4436(*note PopSection::). 4437 4438 This directive swaps the current section (and subsection) with most 4439recently referenced section/subsection pair prior to this one. Multiple 4440`.previous' directives in a row will flip between two sections (and 4441their subsections). For example: 4442 4443 .section A 4444 .subsection 1 4445 .word 0x1234 4446 .subsection 2 4447 .word 0x5678 4448 .previous 4449 .word 0x9abc 4450 4451 Will place 0x1234 and 0x9abc into subsection 1 and 0x5678 into 4452subsection 2 of section A. Whilst: 4453 4454 .section A 4455 .subsection 1 4456 # Now in section A subsection 1 4457 .word 0x1234 4458 .section B 4459 .subsection 0 4460 # Now in section B subsection 0 4461 .word 0x5678 4462 .subsection 1 4463 # Now in section B subsection 1 4464 .word 0x9abc 4465 .previous 4466 # Now in section B subsection 0 4467 .word 0xdef0 4468 4469 Will place 0x1234 into section A, 0x5678 and 0xdef0 into subsection 44700 of section B and 0x9abc into subsection 1 of section B. 4471 4472 In terms of the section stack, this directive swaps the current 4473section with the top section on the section stack. 4474 4475 4476File: as.info, Node: Print, Next: Protected, Prev: Previous, Up: Pseudo Ops 4477 44787.87 `.print STRING' 4479==================== 4480 4481`as' will print STRING on the standard output during assembly. You 4482must put STRING in double quotes. 4483 4484 4485File: as.info, Node: Protected, Next: Psize, Prev: Print, Up: Pseudo Ops 4486 44877.88 `.protected NAMES' 4488======================= 4489 4490This is one of the ELF visibility directives. The other two are 4491`.hidden' (*note Hidden::) and `.internal' (*note Internal::). 4492 4493 This directive overrides the named symbols default visibility (which 4494is set by their binding: local, global or weak). The directive sets 4495the visibility to `protected' which means that any references to the 4496symbols from within the components that defines them must be resolved 4497to the definition in that component, even if a definition in another 4498component would normally preempt this. 4499 4500 4501File: as.info, Node: Psize, Next: Purgem, Prev: Protected, Up: Pseudo Ops 4502 45037.89 `.psize LINES , COLUMNS' 4504============================= 4505 4506Use this directive to declare the number of lines--and, optionally, the 4507number of columns--to use for each page, when generating listings. 4508 4509 If you do not use `.psize', listings use a default line-count of 60. 4510You may omit the comma and COLUMNS specification; the default width is 4511200 columns. 4512 4513 `as' generates formfeeds whenever the specified number of lines is 4514exceeded (or whenever you explicitly request one, using `.eject'). 4515 4516 If you specify LINES as `0', no formfeeds are generated save those 4517explicitly specified with `.eject'. 4518 4519 4520File: as.info, Node: Purgem, Next: PushSection, Prev: Psize, Up: Pseudo Ops 4521 45227.90 `.purgem NAME' 4523=================== 4524 4525Undefine the macro NAME, so that later uses of the string will not be 4526expanded. *Note Macro::. 4527 4528 4529File: as.info, Node: PushSection, Next: Quad, Prev: Purgem, Up: Pseudo Ops 4530 45317.91 `.pushsection NAME [, SUBSECTION] [, "FLAGS"[, @TYPE[,ARGUMENTS]]]' 4532======================================================================== 4533 4534This is one of the ELF section stack manipulation directives. The 4535others are `.section' (*note Section::), `.subsection' (*note 4536SubSection::), `.popsection' (*note PopSection::), and `.previous' 4537(*note Previous::). 4538 4539 This directive pushes the current section (and subsection) onto the 4540top of the section stack, and then replaces the current section and 4541subsection with `name' and `subsection'. The optional `flags', `type' 4542and `arguments' are treated the same as in the `.section' (*note 4543Section::) directive. 4544 4545 4546File: as.info, Node: Quad, Next: Reloc, Prev: PushSection, Up: Pseudo Ops 4547 45487.92 `.quad BIGNUMS' 4549==================== 4550 4551`.quad' expects zero or more bignums, separated by commas. For each 4552bignum, it emits an 8-byte integer. If the bignum won't fit in 8 4553bytes, it prints a warning message; and just takes the lowest order 8 4554bytes of the bignum. 4555 4556 The term "quad" comes from contexts in which a "word" is two bytes; 4557hence _quad_-word for 8 bytes. 4558 4559 4560File: as.info, Node: Reloc, Next: Rept, Prev: Quad, Up: Pseudo Ops 4561 45627.93 `.reloc OFFSET, RELOC_NAME[, EXPRESSION]' 4563============================================== 4564 4565Generate a relocation at OFFSET of type RELOC_NAME with value 4566EXPRESSION. If OFFSET is a number, the relocation is generated in the 4567current section. If OFFSET is an expression that resolves to a symbol 4568plus offset, the relocation is generated in the given symbol's section. 4569EXPRESSION, if present, must resolve to a symbol plus addend or to an 4570absolute value, but note that not all targets support an addend. e.g. 4571ELF REL targets such as i386 store an addend in the section contents 4572rather than in the relocation. This low level interface does not 4573support addends stored in the section. 4574 4575 4576File: as.info, Node: Rept, Next: Sbttl, Prev: Reloc, Up: Pseudo Ops 4577 45787.94 `.rept COUNT' 4579================== 4580 4581Repeat the sequence of lines between the `.rept' directive and the next 4582`.endr' directive COUNT times. 4583 4584 For example, assembling 4585 4586 .rept 3 4587 .long 0 4588 .endr 4589 4590 is equivalent to assembling 4591 4592 .long 0 4593 .long 0 4594 .long 0 4595 4596 4597File: as.info, Node: Sbttl, Next: Scl, Prev: Rept, Up: Pseudo Ops 4598 45997.95 `.sbttl "SUBHEADING"' 4600========================== 4601 4602Use SUBHEADING as the title (third line, immediately after the title 4603line) when generating assembly listings. 4604 4605 This directive affects subsequent pages, as well as the current page 4606if it appears within ten lines of the top of a page. 4607 4608 4609File: as.info, Node: Scl, Next: Section, Prev: Sbttl, Up: Pseudo Ops 4610 46117.96 `.scl CLASS' 4612================= 4613 4614Set the storage-class value for a symbol. This directive may only be 4615used inside a `.def'/`.endef' pair. Storage class may flag whether a 4616symbol is static or external, or it may record further symbolic 4617debugging information. 4618 4619 4620File: as.info, Node: Section, Next: Set, Prev: Scl, Up: Pseudo Ops 4621 46227.97 `.section NAME' 4623==================== 4624 4625Use the `.section' directive to assemble the following code into a 4626section named NAME. 4627 4628 This directive is only supported for targets that actually support 4629arbitrarily named sections; on `a.out' targets, for example, it is not 4630accepted, even with a standard `a.out' section name. 4631 4632COFF Version 4633------------ 4634 4635 For COFF targets, the `.section' directive is used in one of the 4636following ways: 4637 4638 .section NAME[, "FLAGS"] 4639 .section NAME[, SUBSECTION] 4640 4641 If the optional argument is quoted, it is taken as flags to use for 4642the section. Each flag is a single character. The following flags are 4643recognized: 4644`b' 4645 bss section (uninitialized data) 4646 4647`n' 4648 section is not loaded 4649 4650`w' 4651 writable section 4652 4653`d' 4654 data section 4655 4656`r' 4657 read-only section 4658 4659`x' 4660 executable section 4661 4662`s' 4663 shared section (meaningful for PE targets) 4664 4665`a' 4666 ignored. (For compatibility with the ELF version) 4667 4668`y' 4669 section is not readable (meaningful for PE targets) 4670 4671`0-9' 4672 single-digit power-of-two section alignment (GNU extension) 4673 4674 If no flags are specified, the default flags depend upon the section 4675name. If the section name is not recognized, the default will be for 4676the section to be loaded and writable. Note the `n' and `w' flags 4677remove attributes from the section, rather than adding them, so if they 4678are used on their own it will be as if no flags had been specified at 4679all. 4680 4681 If the optional argument to the `.section' directive is not quoted, 4682it is taken as a subsection number (*note Sub-Sections::). 4683 4684ELF Version 4685----------- 4686 4687 This is one of the ELF section stack manipulation directives. The 4688others are `.subsection' (*note SubSection::), `.pushsection' (*note 4689PushSection::), `.popsection' (*note PopSection::), and `.previous' 4690(*note Previous::). 4691 4692 For ELF targets, the `.section' directive is used like this: 4693 4694 .section NAME [, "FLAGS"[, @TYPE[,FLAG_SPECIFIC_ARGUMENTS]]] 4695 4696 The optional FLAGS argument is a quoted string which may contain any 4697combination of the following characters: 4698`a' 4699 section is allocatable 4700 4701`e' 4702 section is excluded from executable and shared library. 4703 4704`w' 4705 section is writable 4706 4707`x' 4708 section is executable 4709 4710`M' 4711 section is mergeable 4712 4713`S' 4714 section contains zero terminated strings 4715 4716`G' 4717 section is a member of a section group 4718 4719`T' 4720 section is used for thread-local-storage 4721 4722`?' 4723 section is a member of the previously-current section's group, if 4724 any 4725 4726 The optional TYPE argument may contain one of the following 4727constants: 4728`@progbits' 4729 section contains data 4730 4731`@nobits' 4732 section does not contain data (i.e., section only occupies space) 4733 4734`@note' 4735 section contains data which is used by things other than the 4736 program 4737 4738`@init_array' 4739 section contains an array of pointers to init functions 4740 4741`@fini_array' 4742 section contains an array of pointers to finish functions 4743 4744`@preinit_array' 4745 section contains an array of pointers to pre-init functions 4746 4747 Many targets only support the first three section types. 4748 4749 Note on targets where the `@' character is the start of a comment (eg 4750ARM) then another character is used instead. For example the ARM port 4751uses the `%' character. 4752 4753 If FLAGS contains the `M' symbol then the TYPE argument must be 4754specified as well as an extra argument--ENTSIZE--like this: 4755 4756 .section NAME , "FLAGS"M, @TYPE, ENTSIZE 4757 4758 Sections with the `M' flag but not `S' flag must contain fixed size 4759constants, each ENTSIZE octets long. Sections with both `M' and `S' 4760must contain zero terminated strings where each character is ENTSIZE 4761bytes long. The linker may remove duplicates within sections with the 4762same name, same entity size and same flags. ENTSIZE must be an 4763absolute expression. For sections with both `M' and `S', a string 4764which is a suffix of a larger string is considered a duplicate. Thus 4765`"def"' will be merged with `"abcdef"'; A reference to the first 4766`"def"' will be changed to a reference to `"abcdef"+3'. 4767 4768 If FLAGS contains the `G' symbol then the TYPE argument must be 4769present along with an additional field like this: 4770 4771 .section NAME , "FLAGS"G, @TYPE, GROUPNAME[, LINKAGE] 4772 4773 The GROUPNAME field specifies the name of the section group to which 4774this particular section belongs. The optional linkage field can 4775contain: 4776`comdat' 4777 indicates that only one copy of this section should be retained 4778 4779`.gnu.linkonce' 4780 an alias for comdat 4781 4782 Note: if both the M and G flags are present then the fields for the 4783Merge flag should come first, like this: 4784 4785 .section NAME , "FLAGS"MG, @TYPE, ENTSIZE, GROUPNAME[, LINKAGE] 4786 4787 If FLAGS contains the `?' symbol then it may not also contain the 4788`G' symbol and the GROUPNAME or LINKAGE fields should not be present. 4789Instead, `?' says to consider the section that's current before this 4790directive. If that section used `G', then the new section will use `G' 4791with those same GROUPNAME and LINKAGE fields implicitly. If not, then 4792the `?' symbol has no effect. 4793 4794 If no flags are specified, the default flags depend upon the section 4795name. If the section name is not recognized, the default will be for 4796the section to have none of the above flags: it will not be allocated 4797in memory, nor writable, nor executable. The section will contain data. 4798 4799 For ELF targets, the assembler supports another type of `.section' 4800directive for compatibility with the Solaris assembler: 4801 4802 .section "NAME"[, FLAGS...] 4803 4804 Note that the section name is quoted. There may be a sequence of 4805comma separated flags: 4806`#alloc' 4807 section is allocatable 4808 4809`#write' 4810 section is writable 4811 4812`#execinstr' 4813 section is executable 4814 4815`#exclude' 4816 section is excluded from executable and shared library. 4817 4818`#tls' 4819 section is used for thread local storage 4820 4821 This directive replaces the current section and subsection. See the 4822contents of the gas testsuite directory `gas/testsuite/gas/elf' for 4823some examples of how this directive and the other section stack 4824directives work. 4825 4826 4827File: as.info, Node: Set, Next: Short, Prev: Section, Up: Pseudo Ops 4828 48297.98 `.set SYMBOL, EXPRESSION' 4830============================== 4831 4832Set the value of SYMBOL to EXPRESSION. This changes SYMBOL's value and 4833type to conform to EXPRESSION. If SYMBOL was flagged as external, it 4834remains flagged (*note Symbol Attributes::). 4835 4836 You may `.set' a symbol many times in the same assembly. 4837 4838 If you `.set' a global symbol, the value stored in the object file 4839is the last value stored into it. 4840 4841 On Z80 `set' is a real instruction, use `SYMBOL defl EXPRESSION' 4842instead. 4843 4844 4845File: as.info, Node: Short, Next: Single, Prev: Set, Up: Pseudo Ops 4846 48477.99 `.short EXPRESSIONS' 4848========================= 4849 4850`.short' is normally the same as `.word'. *Note `.word': Word. 4851 4852 In some configurations, however, `.short' and `.word' generate 4853numbers of different lengths. *Note Machine Dependencies::. 4854 4855 4856File: as.info, Node: Single, Next: Size, Prev: Short, Up: Pseudo Ops 4857 48587.100 `.single FLONUMS' 4859======================= 4860 4861This directive assembles zero or more flonums, separated by commas. It 4862has the same effect as `.float'. The exact kind of floating point 4863numbers emitted depends on how `as' is configured. *Note Machine 4864Dependencies::. 4865 4866 4867File: as.info, Node: Size, Next: Skip, Prev: Single, Up: Pseudo Ops 4868 48697.101 `.size' 4870============= 4871 4872This directive is used to set the size associated with a symbol. 4873 4874COFF Version 4875------------ 4876 4877 For COFF targets, the `.size' directive is only permitted inside 4878`.def'/`.endef' pairs. It is used like this: 4879 4880 .size EXPRESSION 4881 4882ELF Version 4883----------- 4884 4885 For ELF targets, the `.size' directive is used like this: 4886 4887 .size NAME , EXPRESSION 4888 4889 This directive sets the size associated with a symbol NAME. The 4890size in bytes is computed from EXPRESSION which can make use of label 4891arithmetic. This directive is typically used to set the size of 4892function symbols. 4893 4894 4895File: as.info, Node: Skip, Next: Sleb128, Prev: Size, Up: Pseudo Ops 4896 48977.102 `.skip SIZE , FILL' 4898========================= 4899 4900This directive emits SIZE bytes, each of value FILL. Both SIZE and 4901FILL are absolute expressions. If the comma and FILL are omitted, FILL 4902is assumed to be zero. This is the same as `.space'. 4903 4904 4905File: as.info, Node: Sleb128, Next: Space, Prev: Skip, Up: Pseudo Ops 4906 49077.103 `.sleb128 EXPRESSIONS' 4908============================ 4909 4910SLEB128 stands for "signed little endian base 128." This is a compact, 4911variable length representation of numbers used by the DWARF symbolic 4912debugging format. *Note `.uleb128': Uleb128. 4913 4914 4915File: as.info, Node: Space, Next: Stab, Prev: Sleb128, Up: Pseudo Ops 4916 49177.104 `.space SIZE , FILL' 4918========================== 4919 4920This directive emits SIZE bytes, each of value FILL. Both SIZE and 4921FILL are absolute expressions. If the comma and FILL are omitted, FILL 4922is assumed to be zero. This is the same as `.skip'. 4923 4924 _Warning:_ `.space' has a completely different meaning for HPPA 4925 targets; use `.block' as a substitute. See `HP9000 Series 800 4926 Assembly Language Reference Manual' (HP 92432-90001) for the 4927 meaning of the `.space' directive. *Note HPPA Assembler 4928 Directives: HPPA Directives, for a summary. 4929 4930 4931File: as.info, Node: Stab, Next: String, Prev: Space, Up: Pseudo Ops 4932 49337.105 `.stabd, .stabn, .stabs' 4934============================== 4935 4936There are three directives that begin `.stab'. All emit symbols (*note 4937Symbols::), for use by symbolic debuggers. The symbols are not entered 4938in the `as' hash table: they cannot be referenced elsewhere in the 4939source file. Up to five fields are required: 4940 4941STRING 4942 This is the symbol's name. It may contain any character except 4943 `\000', so is more general than ordinary symbol names. Some 4944 debuggers used to code arbitrarily complex structures into symbol 4945 names using this field. 4946 4947TYPE 4948 An absolute expression. The symbol's type is set to the low 8 4949 bits of this expression. Any bit pattern is permitted, but `ld' 4950 and debuggers choke on silly bit patterns. 4951 4952OTHER 4953 An absolute expression. The symbol's "other" attribute is set to 4954 the low 8 bits of this expression. 4955 4956DESC 4957 An absolute expression. The symbol's descriptor is set to the low 4958 16 bits of this expression. 4959 4960VALUE 4961 An absolute expression which becomes the symbol's value. 4962 4963 If a warning is detected while reading a `.stabd', `.stabn', or 4964`.stabs' statement, the symbol has probably already been created; you 4965get a half-formed symbol in your object file. This is compatible with 4966earlier assemblers! 4967 4968`.stabd TYPE , OTHER , DESC' 4969 The "name" of the symbol generated is not even an empty string. 4970 It is a null pointer, for compatibility. Older assemblers used a 4971 null pointer so they didn't waste space in object files with empty 4972 strings. 4973 4974 The symbol's value is set to the location counter, relocatably. 4975 When your program is linked, the value of this symbol is the 4976 address of the location counter when the `.stabd' was assembled. 4977 4978`.stabn TYPE , OTHER , DESC , VALUE' 4979 The name of the symbol is set to the empty string `""'. 4980 4981`.stabs STRING , TYPE , OTHER , DESC , VALUE' 4982 All five fields are specified. 4983 4984 4985File: as.info, Node: String, Next: Struct, Prev: Stab, Up: Pseudo Ops 4986 49877.106 `.string' "STR", `.string8' "STR", `.string16' 4988==================================================== 4989 4990"STR", `.string32' "STR", `.string64' "STR" 4991 4992 Copy the characters in STR to the object file. You may specify more 4993than one string to copy, separated by commas. Unless otherwise 4994specified for a particular machine, the assembler marks the end of each 4995string with a 0 byte. You can use any of the escape sequences 4996described in *note Strings: Strings. 4997 4998 The variants `string16', `string32' and `string64' differ from the 4999`string' pseudo opcode in that each 8-bit character from STR is copied 5000and expanded to 16, 32 or 64 bits respectively. The expanded characters 5001are stored in target endianness byte order. 5002 5003 Example: 5004 .string32 "BYE" 5005 expands to: 5006 .string "B\0\0\0Y\0\0\0E\0\0\0" /* On little endian targets. */ 5007 .string "\0\0\0B\0\0\0Y\0\0\0E" /* On big endian targets. */ 5008 5009 5010File: as.info, Node: Struct, Next: SubSection, Prev: String, Up: Pseudo Ops 5011 50127.107 `.struct EXPRESSION' 5013========================== 5014 5015Switch to the absolute section, and set the section offset to 5016EXPRESSION, which must be an absolute expression. You might use this 5017as follows: 5018 .struct 0 5019 field1: 5020 .struct field1 + 4 5021 field2: 5022 .struct field2 + 4 5023 field3: 5024 This would define the symbol `field1' to have the value 0, the symbol 5025`field2' to have the value 4, and the symbol `field3' to have the value 50268. Assembly would be left in the absolute section, and you would need 5027to use a `.section' directive of some sort to change to some other 5028section before further assembly. 5029 5030 5031File: as.info, Node: SubSection, Next: Symver, Prev: Struct, Up: Pseudo Ops 5032 50337.108 `.subsection NAME' 5034======================== 5035 5036This is one of the ELF section stack manipulation directives. The 5037others are `.section' (*note Section::), `.pushsection' (*note 5038PushSection::), `.popsection' (*note PopSection::), and `.previous' 5039(*note Previous::). 5040 5041 This directive replaces the current subsection with `name'. The 5042current section is not changed. The replaced subsection is put onto 5043the section stack in place of the then current top of stack subsection. 5044 5045 5046File: as.info, Node: Symver, Next: Tag, Prev: SubSection, Up: Pseudo Ops 5047 50487.109 `.symver' 5049=============== 5050 5051Use the `.symver' directive to bind symbols to specific version nodes 5052within a source file. This is only supported on ELF platforms, and is 5053typically used when assembling files to be linked into a shared library. 5054There are cases where it may make sense to use this in objects to be 5055bound into an application itself so as to override a versioned symbol 5056from a shared library. 5057 5058 For ELF targets, the `.symver' directive can be used like this: 5059 .symver NAME, NAME2@NODENAME 5060 If the symbol NAME is defined within the file being assembled, the 5061`.symver' directive effectively creates a symbol alias with the name 5062NAME2@NODENAME, and in fact the main reason that we just don't try and 5063create a regular alias is that the @ character isn't permitted in 5064symbol names. The NAME2 part of the name is the actual name of the 5065symbol by which it will be externally referenced. The name NAME itself 5066is merely a name of convenience that is used so that it is possible to 5067have definitions for multiple versions of a function within a single 5068source file, and so that the compiler can unambiguously know which 5069version of a function is being mentioned. The NODENAME portion of the 5070alias should be the name of a node specified in the version script 5071supplied to the linker when building a shared library. If you are 5072attempting to override a versioned symbol from a shared library, then 5073NODENAME should correspond to the nodename of the symbol you are trying 5074to override. 5075 5076 If the symbol NAME is not defined within the file being assembled, 5077all references to NAME will be changed to NAME2@NODENAME. If no 5078reference to NAME is made, NAME2@NODENAME will be removed from the 5079symbol table. 5080 5081 Another usage of the `.symver' directive is: 5082 .symver NAME, NAME2@@NODENAME 5083 In this case, the symbol NAME must exist and be defined within the 5084file being assembled. It is similar to NAME2@NODENAME. The difference 5085is NAME2@@NODENAME will also be used to resolve references to NAME2 by 5086the linker. 5087 5088 The third usage of the `.symver' directive is: 5089 .symver NAME, NAME2@@@NODENAME 5090 When NAME is not defined within the file being assembled, it is 5091treated as NAME2@NODENAME. When NAME is defined within the file being 5092assembled, the symbol name, NAME, will be changed to NAME2@@NODENAME. 5093 5094 5095File: as.info, Node: Tag, Next: Text, Prev: Symver, Up: Pseudo Ops 5096 50977.110 `.tag STRUCTNAME' 5098======================= 5099 5100This directive is generated by compilers to include auxiliary debugging 5101information in the symbol table. It is only permitted inside 5102`.def'/`.endef' pairs. Tags are used to link structure definitions in 5103the symbol table with instances of those structures. 5104 5105 5106File: as.info, Node: Text, Next: Title, Prev: Tag, Up: Pseudo Ops 5107 51087.111 `.text SUBSECTION' 5109======================== 5110 5111Tells `as' to assemble the following statements onto the end of the 5112text subsection numbered SUBSECTION, which is an absolute expression. 5113If SUBSECTION is omitted, subsection number zero is used. 5114 5115 5116File: as.info, Node: Title, Next: Type, Prev: Text, Up: Pseudo Ops 5117 51187.112 `.title "HEADING"' 5119======================== 5120 5121Use HEADING as the title (second line, immediately after the source 5122file name and pagenumber) when generating assembly listings. 5123 5124 This directive affects subsequent pages, as well as the current page 5125if it appears within ten lines of the top of a page. 5126 5127 5128File: as.info, Node: Type, Next: Uleb128, Prev: Title, Up: Pseudo Ops 5129 51307.113 `.type' 5131============= 5132 5133This directive is used to set the type of a symbol. 5134 5135COFF Version 5136------------ 5137 5138 For COFF targets, this directive is permitted only within 5139`.def'/`.endef' pairs. It is used like this: 5140 5141 .type INT 5142 5143 This records the integer INT as the type attribute of a symbol table 5144entry. 5145 5146ELF Version 5147----------- 5148 5149 For ELF targets, the `.type' directive is used like this: 5150 5151 .type NAME , TYPE DESCRIPTION 5152 5153 This sets the type of symbol NAME to be either a function symbol or 5154an object symbol. There are five different syntaxes supported for the 5155TYPE DESCRIPTION field, in order to provide compatibility with various 5156other assemblers. 5157 5158 Because some of the characters used in these syntaxes (such as `@' 5159and `#') are comment characters for some architectures, some of the 5160syntaxes below do not work on all architectures. The first variant 5161will be accepted by the GNU assembler on all architectures so that 5162variant should be used for maximum portability, if you do not need to 5163assemble your code with other assemblers. 5164 5165 The syntaxes supported are: 5166 5167 .type <name> STT_<TYPE_IN_UPPER_CASE> 5168 .type <name>,#<type> 5169 .type <name>,@<type> 5170 .type <name>,%<type> 5171 .type <name>,"<type>" 5172 5173 The types supported are: 5174 5175`STT_FUNC' 5176`function' 5177 Mark the symbol as being a function name. 5178 5179`STT_GNU_IFUNC' 5180`gnu_indirect_function' 5181 Mark the symbol as an indirect function when evaluated during reloc 5182 processing. (This is only supported on assemblers targeting GNU 5183 systems). 5184 5185`STT_OBJECT' 5186`object' 5187 Mark the symbol as being a data object. 5188 5189`STT_TLS' 5190`tls_object' 5191 Mark the symbol as being a thead-local data object. 5192 5193`STT_COMMON' 5194`common' 5195 Mark the symbol as being a common data object. 5196 5197`STT_NOTYPE' 5198`notype' 5199 Does not mark the symbol in any way. It is supported just for 5200 completeness. 5201 5202`gnu_unique_object' 5203 Marks the symbol as being a globally unique data object. The 5204 dynamic linker will make sure that in the entire process there is 5205 just one symbol with this name and type in use. (This is only 5206 supported on assemblers targeting GNU systems). 5207 5208 5209 Note: Some targets support extra types in addition to those listed 5210above. 5211 5212 5213File: as.info, Node: Uleb128, Next: Val, Prev: Type, Up: Pseudo Ops 5214 52157.114 `.uleb128 EXPRESSIONS' 5216============================ 5217 5218ULEB128 stands for "unsigned little endian base 128." This is a 5219compact, variable length representation of numbers used by the DWARF 5220symbolic debugging format. *Note `.sleb128': Sleb128. 5221 5222 5223File: as.info, Node: Val, Next: Version, Prev: Uleb128, Up: Pseudo Ops 5224 52257.115 `.val ADDR' 5226================= 5227 5228This directive, permitted only within `.def'/`.endef' pairs, records 5229the address ADDR as the value attribute of a symbol table entry. 5230 5231 5232File: as.info, Node: Version, Next: VTableEntry, Prev: Val, Up: Pseudo Ops 5233 52347.116 `.version "STRING"' 5235========================= 5236 5237This directive creates a `.note' section and places into it an ELF 5238formatted note of type NT_VERSION. The note's name is set to `string'. 5239 5240 5241File: as.info, Node: VTableEntry, Next: VTableInherit, Prev: Version, Up: Pseudo Ops 5242 52437.117 `.vtable_entry TABLE, OFFSET' 5244=================================== 5245 5246This directive finds or creates a symbol `table' and creates a 5247`VTABLE_ENTRY' relocation for it with an addend of `offset'. 5248 5249 5250File: as.info, Node: VTableInherit, Next: Warning, Prev: VTableEntry, Up: Pseudo Ops 5251 52527.118 `.vtable_inherit CHILD, PARENT' 5253===================================== 5254 5255This directive finds the symbol `child' and finds or creates the symbol 5256`parent' and then creates a `VTABLE_INHERIT' relocation for the parent 5257whose addend is the value of the child symbol. As a special case the 5258parent name of `0' is treated as referring to the `*ABS*' section. 5259 5260 5261File: as.info, Node: Warning, Next: Weak, Prev: VTableInherit, Up: Pseudo Ops 5262 52637.119 `.warning "STRING"' 5264========================= 5265 5266Similar to the directive `.error' (*note `.error "STRING"': Error.), 5267but just emits a warning. 5268 5269 5270File: as.info, Node: Weak, Next: Weakref, Prev: Warning, Up: Pseudo Ops 5271 52727.120 `.weak NAMES' 5273=================== 5274 5275This directive sets the weak attribute on the comma separated list of 5276symbol `names'. If the symbols do not already exist, they will be 5277created. 5278 5279 On COFF targets other than PE, weak symbols are a GNU extension. 5280This directive sets the weak attribute on the comma separated list of 5281symbol `names'. If the symbols do not already exist, they will be 5282created. 5283 5284 On the PE target, weak symbols are supported natively as weak 5285aliases. When a weak symbol is created that is not an alias, GAS 5286creates an alternate symbol to hold the default value. 5287 5288 5289File: as.info, Node: Weakref, Next: Word, Prev: Weak, Up: Pseudo Ops 5290 52917.121 `.weakref ALIAS, TARGET' 5292============================== 5293 5294This directive creates an alias to the target symbol that enables the 5295symbol to be referenced with weak-symbol semantics, but without 5296actually making it weak. If direct references or definitions of the 5297symbol are present, then the symbol will not be weak, but if all 5298references to it are through weak references, the symbol will be marked 5299as weak in the symbol table. 5300 5301 The effect is equivalent to moving all references to the alias to a 5302separate assembly source file, renaming the alias to the symbol in it, 5303declaring the symbol as weak there, and running a reloadable link to 5304merge the object files resulting from the assembly of the new source 5305file and the old source file that had the references to the alias 5306removed. 5307 5308 The alias itself never makes to the symbol table, and is entirely 5309handled within the assembler. 5310 5311 5312File: as.info, Node: Word, Next: Deprecated, Prev: Weakref, Up: Pseudo Ops 5313 53147.122 `.word EXPRESSIONS' 5315========================= 5316 5317This directive expects zero or more EXPRESSIONS, of any section, 5318separated by commas. 5319 5320 The size of the number emitted, and its byte order, depend on what 5321target computer the assembly is for. 5322 5323 _Warning: Special Treatment to support Compilers_ 5324 5325 Machines with a 32-bit address space, but that do less than 32-bit 5326addressing, require the following special treatment. If the machine of 5327interest to you does 32-bit addressing (or doesn't require it; *note 5328Machine Dependencies::), you can ignore this issue. 5329 5330 In order to assemble compiler output into something that works, `as' 5331occasionally does strange things to `.word' directives. Directives of 5332the form `.word sym1-sym2' are often emitted by compilers as part of 5333jump tables. Therefore, when `as' assembles a directive of the form 5334`.word sym1-sym2', and the difference between `sym1' and `sym2' does 5335not fit in 16 bits, `as' creates a "secondary jump table", immediately 5336before the next label. This secondary jump table is preceded by a 5337short-jump to the first byte after the secondary table. This 5338short-jump prevents the flow of control from accidentally falling into 5339the new table. Inside the table is a long-jump to `sym2'. The 5340original `.word' contains `sym1' minus the address of the long-jump to 5341`sym2'. 5342 5343 If there were several occurrences of `.word sym1-sym2' before the 5344secondary jump table, all of them are adjusted. If there was a `.word 5345sym3-sym4', that also did not fit in sixteen bits, a long-jump to 5346`sym4' is included in the secondary jump table, and the `.word' 5347directives are adjusted to contain `sym3' minus the address of the 5348long-jump to `sym4'; and so on, for as many entries in the original 5349jump table as necessary. 5350 5351 5352File: as.info, Node: Deprecated, Prev: Word, Up: Pseudo Ops 5353 53547.123 Deprecated Directives 5355=========================== 5356 5357One day these directives won't work. They are included for 5358compatibility with older assemblers. 5359.abort 5360 5361.line 5362 5363 5364File: as.info, Node: Object Attributes, Next: Machine Dependencies, Prev: Pseudo Ops, Up: Top 5365 53668 Object Attributes 5367******************* 5368 5369`as' assembles source files written for a specific architecture into 5370object files for that architecture. But not all object files are alike. 5371Many architectures support incompatible variations. For instance, 5372floating point arguments might be passed in floating point registers if 5373the object file requires hardware floating point support--or floating 5374point arguments might be passed in integer registers if the object file 5375supports processors with no hardware floating point unit. Or, if two 5376objects are built for different generations of the same architecture, 5377the combination may require the newer generation at run-time. 5378 5379 This information is useful during and after linking. At link time, 5380`ld' can warn about incompatible object files. After link time, tools 5381like `gdb' can use it to process the linked file correctly. 5382 5383 Compatibility information is recorded as a series of object 5384attributes. Each attribute has a "vendor", "tag", and "value". The 5385vendor is a string, and indicates who sets the meaning of the tag. The 5386tag is an integer, and indicates what property the attribute describes. 5387The value may be a string or an integer, and indicates how the property 5388affects this object. Missing attributes are the same as attributes 5389with a zero value or empty string value. 5390 5391 Object attributes were developed as part of the ABI for the ARM 5392Architecture. The file format is documented in `ELF for the ARM 5393Architecture'. 5394 5395* Menu: 5396 5397* GNU Object Attributes:: GNU Object Attributes 5398* Defining New Object Attributes:: Defining New Object Attributes 5399 5400 5401File: as.info, Node: GNU Object Attributes, Next: Defining New Object Attributes, Up: Object Attributes 5402 54038.1 GNU Object Attributes 5404========================= 5405 5406The `.gnu_attribute' directive records an object attribute with vendor 5407`gnu'. 5408 5409 Except for `Tag_compatibility', which has both an integer and a 5410string for its value, GNU attributes have a string value if the tag 5411number is odd and an integer value if the tag number is even. The 5412second bit (`TAG & 2' is set for architecture-independent attributes 5413and clear for architecture-dependent ones. 5414 54158.1.1 Common GNU attributes 5416--------------------------- 5417 5418These attributes are valid on all architectures. 5419 5420Tag_compatibility (32) 5421 The compatibility attribute takes an integer flag value and a 5422 vendor name. If the flag value is 0, the file is compatible with 5423 other toolchains. If it is 1, then the file is only compatible 5424 with the named toolchain. If it is greater than 1, the file can 5425 only be processed by other toolchains under some private 5426 arrangement indicated by the flag value and the vendor name. 5427 54288.1.2 MIPS Attributes 5429--------------------- 5430 5431Tag_GNU_MIPS_ABI_FP (4) 5432 The floating-point ABI used by this object file. The value will 5433 be: 5434 5435 * 0 for files not affected by the floating-point ABI. 5436 5437 * 1 for files using the hardware floating-point with a standard 5438 double-precision FPU. 5439 5440 * 2 for files using the hardware floating-point ABI with a 5441 single-precision FPU. 5442 5443 * 3 for files using the software floating-point ABI. 5444 5445 * 4 for files using the hardware floating-point ABI with 64-bit 5446 wide double-precision floating-point registers and 32-bit 5447 wide general purpose registers. 5448 54498.1.3 PowerPC Attributes 5450------------------------ 5451 5452Tag_GNU_Power_ABI_FP (4) 5453 The floating-point ABI used by this object file. The value will 5454 be: 5455 5456 * 0 for files not affected by the floating-point ABI. 5457 5458 * 1 for files using double-precision hardware floating-point 5459 ABI. 5460 5461 * 2 for files using the software floating-point ABI. 5462 5463 * 3 for files using single-precision hardware floating-point 5464 ABI. 5465 5466Tag_GNU_Power_ABI_Vector (8) 5467 The vector ABI used by this object file. The value will be: 5468 5469 * 0 for files not affected by the vector ABI. 5470 5471 * 1 for files using general purpose registers to pass vectors. 5472 5473 * 2 for files using AltiVec registers to pass vectors. 5474 5475 * 3 for files using SPE registers to pass vectors. 5476 5477 5478File: as.info, Node: Defining New Object Attributes, Prev: GNU Object Attributes, Up: Object Attributes 5479 54808.2 Defining New Object Attributes 5481================================== 5482 5483If you want to define a new GNU object attribute, here are the places 5484you will need to modify. New attributes should be discussed on the 5485`binutils' mailing list. 5486 5487 * This manual, which is the official register of attributes. 5488 5489 * The header for your architecture `include/elf', to define the tag. 5490 5491 * The `bfd' support file for your architecture, to merge the 5492 attribute and issue any appropriate link warnings. 5493 5494 * Test cases in `ld/testsuite' for merging and link warnings. 5495 5496 * `binutils/readelf.c' to display your attribute. 5497 5498 * GCC, if you want the compiler to mark the attribute automatically. 5499 5500 5501File: as.info, Node: Machine Dependencies, Next: Reporting Bugs, Prev: Object Attributes, Up: Top 5502 55039 Machine Dependent Features 5504**************************** 5505 5506The machine instruction sets are (almost by definition) different on 5507each machine where `as' runs. Floating point representations vary as 5508well, and `as' often supports a few additional directives or 5509command-line options for compatibility with other assemblers on a 5510particular platform. Finally, some versions of `as' support special 5511pseudo-instructions for branch optimization. 5512 5513 This chapter discusses most of these differences, though it does not 5514include details on any machine's instruction set. For details on that 5515subject, see the hardware manufacturer's manual. 5516 5517* Menu: 5518 5519 5520* Alpha-Dependent:: Alpha Dependent Features 5521 5522* ARC-Dependent:: ARC Dependent Features 5523 5524* ARM-Dependent:: ARM Dependent Features 5525 5526* AVR-Dependent:: AVR Dependent Features 5527 5528* Blackfin-Dependent:: Blackfin Dependent Features 5529 5530* CR16-Dependent:: CR16 Dependent Features 5531 5532* CRIS-Dependent:: CRIS Dependent Features 5533 5534* D10V-Dependent:: D10V Dependent Features 5535 5536* D30V-Dependent:: D30V Dependent Features 5537 5538* H8/300-Dependent:: Renesas H8/300 Dependent Features 5539 5540* HPPA-Dependent:: HPPA Dependent Features 5541 5542* ESA/390-Dependent:: IBM ESA/390 Dependent Features 5543 5544* i386-Dependent:: Intel 80386 and AMD x86-64 Dependent Features 5545 5546* i860-Dependent:: Intel 80860 Dependent Features 5547 5548* i960-Dependent:: Intel 80960 Dependent Features 5549 5550* IA-64-Dependent:: Intel IA-64 Dependent Features 5551 5552* IP2K-Dependent:: IP2K Dependent Features 5553 5554* LM32-Dependent:: LM32 Dependent Features 5555 5556* M32C-Dependent:: M32C Dependent Features 5557 5558* M32R-Dependent:: M32R Dependent Features 5559 5560* M68K-Dependent:: M680x0 Dependent Features 5561 5562* M68HC11-Dependent:: M68HC11 and 68HC12 Dependent Features 5563 5564* MicroBlaze-Dependent:: MICROBLAZE Dependent Features 5565 5566* MIPS-Dependent:: MIPS Dependent Features 5567 5568* MMIX-Dependent:: MMIX Dependent Features 5569 5570* MSP430-Dependent:: MSP430 Dependent Features 5571 5572* NS32K-Dependent:: NS32K Dependent Features 5573 5574* SH-Dependent:: Renesas / SuperH SH Dependent Features 5575* SH64-Dependent:: SuperH SH64 Dependent Features 5576 5577* PDP-11-Dependent:: PDP-11 Dependent Features 5578 5579* PJ-Dependent:: picoJava Dependent Features 5580 5581* PPC-Dependent:: PowerPC Dependent Features 5582 5583* RX-Dependent:: RX Dependent Features 5584 5585* S/390-Dependent:: IBM S/390 Dependent Features 5586 5587* SCORE-Dependent:: SCORE Dependent Features 5588 5589* Sparc-Dependent:: SPARC Dependent Features 5590 5591* TIC54X-Dependent:: TI TMS320C54x Dependent Features 5592 5593* TIC6X-Dependent :: TI TMS320C6x Dependent Features 5594 5595* TILE-Gx-Dependent :: Tilera TILE-Gx Dependent Features 5596 5597* TILEPro-Dependent :: Tilera TILEPro Dependent Features 5598 5599* V850-Dependent:: V850 Dependent Features 5600 5601* XSTORMY16-Dependent:: XStormy16 Dependent Features 5602 5603* Xtensa-Dependent:: Xtensa Dependent Features 5604 5605* Z80-Dependent:: Z80 Dependent Features 5606 5607* Z8000-Dependent:: Z8000 Dependent Features 5608 5609* Vax-Dependent:: VAX Dependent Features 5610 5611 5612File: as.info, Node: Alpha-Dependent, Next: ARC-Dependent, Up: Machine Dependencies 5613 56149.1 Alpha Dependent Features 5615============================ 5616 5617* Menu: 5618 5619* Alpha Notes:: Notes 5620* Alpha Options:: Options 5621* Alpha Syntax:: Syntax 5622* Alpha Floating Point:: Floating Point 5623* Alpha Directives:: Alpha Machine Directives 5624* Alpha Opcodes:: Opcodes 5625 5626 5627File: as.info, Node: Alpha Notes, Next: Alpha Options, Up: Alpha-Dependent 5628 56299.1.1 Notes 5630----------- 5631 5632The documentation here is primarily for the ELF object format. `as' 5633also supports the ECOFF and EVAX formats, but features specific to 5634these formats are not yet documented. 5635 5636 5637File: as.info, Node: Alpha Options, Next: Alpha Syntax, Prev: Alpha Notes, Up: Alpha-Dependent 5638 56399.1.2 Options 5640------------- 5641 5642`-mCPU' 5643 This option specifies the target processor. If an attempt is made 5644 to assemble an instruction which will not execute on the target 5645 processor, the assembler may either expand the instruction as a 5646 macro or issue an error message. This option is equivalent to the 5647 `.arch' directive. 5648 5649 The following processor names are recognized: `21064', `21064a', 5650 `21066', `21068', `21164', `21164a', `21164pc', `21264', `21264a', 5651 `21264b', `ev4', `ev5', `lca45', `ev5', `ev56', `pca56', `ev6', 5652 `ev67', `ev68'. The special name `all' may be used to allow the 5653 assembler to accept instructions valid for any Alpha processor. 5654 5655 In order to support existing practice in OSF/1 with respect to 5656 `.arch', and existing practice within `MILO' (the Linux ARC 5657 bootloader), the numbered processor names (e.g. 21064) enable the 5658 processor-specific PALcode instructions, while the 5659 "electro-vlasic" names (e.g. `ev4') do not. 5660 5661`-mdebug' 5662`-no-mdebug' 5663 Enables or disables the generation of `.mdebug' encapsulation for 5664 stabs directives and procedure descriptors. The default is to 5665 automatically enable `.mdebug' when the first stabs directive is 5666 seen. 5667 5668`-relax' 5669 This option forces all relocations to be put into the object file, 5670 instead of saving space and resolving some relocations at assembly 5671 time. Note that this option does not propagate all symbol 5672 arithmetic into the object file, because not all symbol arithmetic 5673 can be represented. However, the option can still be useful in 5674 specific applications. 5675 5676`-replace' 5677`-noreplace' 5678 Enables or disables the optimization of procedure calls, both at 5679 assemblage and at link time. These options are only available for 5680 VMS targets and `-replace' is the default. See section 1.4.1 of 5681 the OpenVMS Linker Utility Manual. 5682 5683`-g' 5684 This option is used when the compiler generates debug information. 5685 When `gcc' is using `mips-tfile' to generate debug information for 5686 ECOFF, local labels must be passed through to the object file. 5687 Otherwise this option has no effect. 5688 5689`-GSIZE' 5690 A local common symbol larger than SIZE is placed in `.bss', while 5691 smaller symbols are placed in `.sbss'. 5692 5693`-F' 5694`-32addr' 5695 These options are ignored for backward compatibility. 5696 5697 5698File: as.info, Node: Alpha Syntax, Next: Alpha Floating Point, Prev: Alpha Options, Up: Alpha-Dependent 5699 57009.1.3 Syntax 5701------------ 5702 5703The assembler syntax closely follow the Alpha Reference Manual; 5704assembler directives and general syntax closely follow the OSF/1 and 5705OpenVMS syntax, with a few differences for ELF. 5706 5707* Menu: 5708 5709* Alpha-Chars:: Special Characters 5710* Alpha-Regs:: Register Names 5711* Alpha-Relocs:: Relocations 5712 5713 5714File: as.info, Node: Alpha-Chars, Next: Alpha-Regs, Up: Alpha Syntax 5715 57169.1.3.1 Special Characters 5717.......................... 5718 5719`#' is the line comment character. Note that if `#' is the first 5720character on a line then it can also be a logical line number directive 5721(*note Comments::) or a preprocessor control command (*note 5722Preprocessing::). 5723 5724 `;' can be used instead of a newline to separate statements. 5725 5726 5727File: as.info, Node: Alpha-Regs, Next: Alpha-Relocs, Prev: Alpha-Chars, Up: Alpha Syntax 5728 57299.1.3.2 Register Names 5730...................... 5731 5732The 32 integer registers are referred to as `$N' or `$rN'. In 5733addition, registers 15, 28, 29, and 30 may be referred to by the 5734symbols `$fp', `$at', `$gp', and `$sp' respectively. 5735 5736 The 32 floating-point registers are referred to as `$fN'. 5737 5738 5739File: as.info, Node: Alpha-Relocs, Prev: Alpha-Regs, Up: Alpha Syntax 5740 57419.1.3.3 Relocations 5742................... 5743 5744Some of these relocations are available for ECOFF, but mostly only for 5745ELF. They are modeled after the relocation format introduced in 5746Digital Unix 4.0, but there are additions. 5747 5748 The format is `!TAG' or `!TAG!NUMBER' where TAG is the name of the 5749relocation. In some cases NUMBER is used to relate specific 5750instructions. 5751 5752 The relocation is placed at the end of the instruction like so: 5753 5754 ldah $0,a($29) !gprelhigh 5755 lda $0,a($0) !gprellow 5756 ldq $1,b($29) !literal!100 5757 ldl $2,0($1) !lituse_base!100 5758 5759`!literal' 5760`!literal!N' 5761 Used with an `ldq' instruction to load the address of a symbol 5762 from the GOT. 5763 5764 A sequence number N is optional, and if present is used to pair 5765 `lituse' relocations with this `literal' relocation. The `lituse' 5766 relocations are used by the linker to optimize the code based on 5767 the final location of the symbol. 5768 5769 Note that these optimizations are dependent on the data flow of the 5770 program. Therefore, if _any_ `lituse' is paired with a `literal' 5771 relocation, then _all_ uses of the register set by the `literal' 5772 instruction must also be marked with `lituse' relocations. This 5773 is because the original `literal' instruction may be deleted or 5774 transformed into another instruction. 5775 5776 Also note that there may be a one-to-many relationship between 5777 `literal' and `lituse', but not a many-to-one. That is, if there 5778 are two code paths that load up the same address and feed the 5779 value to a single use, then the use may not use a `lituse' 5780 relocation. 5781 5782`!lituse_base!N' 5783 Used with any memory format instruction (e.g. `ldl') to indicate 5784 that the literal is used for an address load. The offset field of 5785 the instruction must be zero. During relaxation, the code may be 5786 altered to use a gp-relative load. 5787 5788`!lituse_jsr!N' 5789 Used with a register branch format instruction (e.g. `jsr') to 5790 indicate that the literal is used for a call. During relaxation, 5791 the code may be altered to use a direct branch (e.g. `bsr'). 5792 5793`!lituse_jsrdirect!N' 5794 Similar to `lituse_jsr', but also that this call cannot be vectored 5795 through a PLT entry. This is useful for functions with special 5796 calling conventions which do not allow the normal call-clobbered 5797 registers to be clobbered. 5798 5799`!lituse_bytoff!N' 5800 Used with a byte mask instruction (e.g. `extbl') to indicate that 5801 only the low 3 bits of the address are relevant. During 5802 relaxation, the code may be altered to use an immediate instead of 5803 a register shift. 5804 5805`!lituse_addr!N' 5806 Used with any other instruction to indicate that the original 5807 address is in fact used, and the original `ldq' instruction may 5808 not be altered or deleted. This is useful in conjunction with 5809 `lituse_jsr' to test whether a weak symbol is defined. 5810 5811 ldq $27,foo($29) !literal!1 5812 beq $27,is_undef !lituse_addr!1 5813 jsr $26,($27),foo !lituse_jsr!1 5814 5815`!lituse_tlsgd!N' 5816 Used with a register branch format instruction to indicate that the 5817 literal is the call to `__tls_get_addr' used to compute the 5818 address of the thread-local storage variable whose descriptor was 5819 loaded with `!tlsgd!N'. 5820 5821`!lituse_tlsldm!N' 5822 Used with a register branch format instruction to indicate that the 5823 literal is the call to `__tls_get_addr' used to compute the 5824 address of the base of the thread-local storage block for the 5825 current module. The descriptor for the module must have been 5826 loaded with `!tlsldm!N'. 5827 5828`!gpdisp!N' 5829 Used with `ldah' and `lda' to load the GP from the current 5830 address, a-la the `ldgp' macro. The source register for the 5831 `ldah' instruction must contain the address of the `ldah' 5832 instruction. There must be exactly one `lda' instruction paired 5833 with the `ldah' instruction, though it may appear anywhere in the 5834 instruction stream. The immediate operands must be zero. 5835 5836 bsr $26,foo 5837 ldah $29,0($26) !gpdisp!1 5838 lda $29,0($29) !gpdisp!1 5839 5840`!gprelhigh' 5841 Used with an `ldah' instruction to add the high 16 bits of a 5842 32-bit displacement from the GP. 5843 5844`!gprellow' 5845 Used with any memory format instruction to add the low 16 bits of a 5846 32-bit displacement from the GP. 5847 5848`!gprel' 5849 Used with any memory format instruction to add a 16-bit 5850 displacement from the GP. 5851 5852`!samegp' 5853 Used with any branch format instruction to skip the GP load at the 5854 target address. The referenced symbol must have the same GP as the 5855 source object file, and it must be declared to either not use `$27' 5856 or perform a standard GP load in the first two instructions via the 5857 `.prologue' directive. 5858 5859`!tlsgd' 5860`!tlsgd!N' 5861 Used with an `lda' instruction to load the address of a TLS 5862 descriptor for a symbol in the GOT. 5863 5864 The sequence number N is optional, and if present it used to pair 5865 the descriptor load with both the `literal' loading the address of 5866 the `__tls_get_addr' function and the `lituse_tlsgd' marking the 5867 call to that function. 5868 5869 For proper relaxation, both the `tlsgd', `literal' and `lituse' 5870 relocations must be in the same extended basic block. That is, 5871 the relocation with the lowest address must be executed first at 5872 runtime. 5873 5874`!tlsldm' 5875`!tlsldm!N' 5876 Used with an `lda' instruction to load the address of a TLS 5877 descriptor for the current module in the GOT. 5878 5879 Similar in other respects to `tlsgd'. 5880 5881`!gotdtprel' 5882 Used with an `ldq' instruction to load the offset of the TLS 5883 symbol within its module's thread-local storage block. Also known 5884 as the dynamic thread pointer offset or dtp-relative offset. 5885 5886`!dtprelhi' 5887`!dtprello' 5888`!dtprel' 5889 Like `gprel' relocations except they compute dtp-relative offsets. 5890 5891`!gottprel' 5892 Used with an `ldq' instruction to load the offset of the TLS 5893 symbol from the thread pointer. Also known as the tp-relative 5894 offset. 5895 5896`!tprelhi' 5897`!tprello' 5898`!tprel' 5899 Like `gprel' relocations except they compute tp-relative offsets. 5900 5901 5902File: as.info, Node: Alpha Floating Point, Next: Alpha Directives, Prev: Alpha Syntax, Up: Alpha-Dependent 5903 59049.1.4 Floating Point 5905-------------------- 5906 5907The Alpha family uses both IEEE and VAX floating-point numbers. 5908 5909 5910File: as.info, Node: Alpha Directives, Next: Alpha Opcodes, Prev: Alpha Floating Point, Up: Alpha-Dependent 5911 59129.1.5 Alpha Assembler Directives 5913-------------------------------- 5914 5915`as' for the Alpha supports many additional directives for 5916compatibility with the native assembler. This section describes them 5917only briefly. 5918 5919 These are the additional directives in `as' for the Alpha: 5920 5921`.arch CPU' 5922 Specifies the target processor. This is equivalent to the `-mCPU' 5923 command-line option. *Note Options: Alpha Options, for a list of 5924 values for CPU. 5925 5926`.ent FUNCTION[, N]' 5927 Mark the beginning of FUNCTION. An optional number may follow for 5928 compatibility with the OSF/1 assembler, but is ignored. When 5929 generating `.mdebug' information, this will create a procedure 5930 descriptor for the function. In ELF, it will mark the symbol as a 5931 function a-la the generic `.type' directive. 5932 5933`.end FUNCTION' 5934 Mark the end of FUNCTION. In ELF, it will set the size of the 5935 symbol a-la the generic `.size' directive. 5936 5937`.mask MASK, OFFSET' 5938 Indicate which of the integer registers are saved in the current 5939 function's stack frame. MASK is interpreted a bit mask in which 5940 bit N set indicates that register N is saved. The registers are 5941 saved in a block located OFFSET bytes from the "canonical frame 5942 address" (CFA) which is the value of the stack pointer on entry to 5943 the function. The registers are saved sequentially, except that 5944 the return address register (normally `$26') is saved first. 5945 5946 This and the other directives that describe the stack frame are 5947 currently only used when generating `.mdebug' information. They 5948 may in the future be used to generate DWARF2 `.debug_frame' unwind 5949 information for hand written assembly. 5950 5951`.fmask MASK, OFFSET' 5952 Indicate which of the floating-point registers are saved in the 5953 current stack frame. The MASK and OFFSET parameters are 5954 interpreted as with `.mask'. 5955 5956`.frame FRAMEREG, FRAMEOFFSET, RETREG[, ARGOFFSET]' 5957 Describes the shape of the stack frame. The frame pointer in use 5958 is FRAMEREG; normally this is either `$fp' or `$sp'. The frame 5959 pointer is FRAMEOFFSET bytes below the CFA. The return address is 5960 initially located in RETREG until it is saved as indicated in 5961 `.mask'. For compatibility with OSF/1 an optional ARGOFFSET 5962 parameter is accepted and ignored. It is believed to indicate the 5963 offset from the CFA to the saved argument registers. 5964 5965`.prologue N' 5966 Indicate that the stack frame is set up and all registers have been 5967 spilled. The argument N indicates whether and how the function 5968 uses the incoming "procedure vector" (the address of the called 5969 function) in `$27'. 0 indicates that `$27' is not used; 1 5970 indicates that the first two instructions of the function use `$27' 5971 to perform a load of the GP register; 2 indicates that `$27' is 5972 used in some non-standard way and so the linker cannot elide the 5973 load of the procedure vector during relaxation. 5974 5975`.usepv FUNCTION, WHICH' 5976 Used to indicate the use of the `$27' register, similar to 5977 `.prologue', but without the other semantics of needing to be 5978 inside an open `.ent'/`.end' block. 5979 5980 The WHICH argument should be either `no', indicating that `$27' is 5981 not used, or `std', indicating that the first two instructions of 5982 the function perform a GP load. 5983 5984 One might use this directive instead of `.prologue' if you are 5985 also using dwarf2 CFI directives. 5986 5987`.gprel32 EXPRESSION' 5988 Computes the difference between the address in EXPRESSION and the 5989 GP for the current object file, and stores it in 4 bytes. In 5990 addition to being smaller than a full 8 byte address, this also 5991 does not require a dynamic relocation when used in a shared 5992 library. 5993 5994`.t_floating EXPRESSION' 5995 Stores EXPRESSION as an IEEE double precision value. 5996 5997`.s_floating EXPRESSION' 5998 Stores EXPRESSION as an IEEE single precision value. 5999 6000`.f_floating EXPRESSION' 6001 Stores EXPRESSION as a VAX F format value. 6002 6003`.g_floating EXPRESSION' 6004 Stores EXPRESSION as a VAX G format value. 6005 6006`.d_floating EXPRESSION' 6007 Stores EXPRESSION as a VAX D format value. 6008 6009`.set FEATURE' 6010 Enables or disables various assembler features. Using the positive 6011 name of the feature enables while using `noFEATURE' disables. 6012 6013 `at' 6014 Indicates that macro expansions may clobber the "assembler 6015 temporary" (`$at' or `$28') register. Some macros may not be 6016 expanded without this and will generate an error message if 6017 `noat' is in effect. When `at' is in effect, a warning will 6018 be generated if `$at' is used by the programmer. 6019 6020 `macro' 6021 Enables the expansion of macro instructions. Note that 6022 variants of real instructions, such as `br label' vs `br 6023 $31,label' are considered alternate forms and not macros. 6024 6025 `move' 6026 `reorder' 6027 `volatile' 6028 These control whether and how the assembler may re-order 6029 instructions. Accepted for compatibility with the OSF/1 6030 assembler, but `as' does not do instruction scheduling, so 6031 these features are ignored. 6032 6033 The following directives are recognized for compatibility with the 6034OSF/1 assembler but are ignored. 6035 6036 .proc .aproc 6037 .reguse .livereg 6038 .option .aent 6039 .ugen .eflag 6040 .alias .noalias 6041 6042 6043File: as.info, Node: Alpha Opcodes, Prev: Alpha Directives, Up: Alpha-Dependent 6044 60459.1.6 Opcodes 6046------------- 6047 6048For detailed information on the Alpha machine instruction set, see the 6049Alpha Architecture Handbook 6050(ftp://ftp.digital.com/pub/Digital/info/semiconductor/literature/alphaahb.pdf). 6051 6052 6053File: as.info, Node: ARC-Dependent, Next: ARM-Dependent, Prev: Alpha-Dependent, Up: Machine Dependencies 6054 60559.2 ARC Dependent Features 6056========================== 6057 6058* Menu: 6059 6060* ARC Options:: Options 6061* ARC Syntax:: Syntax 6062* ARC Floating Point:: Floating Point 6063* ARC Directives:: ARC Machine Directives 6064* ARC Opcodes:: Opcodes 6065 6066 6067File: as.info, Node: ARC Options, Next: ARC Syntax, Up: ARC-Dependent 6068 60699.2.1 Options 6070------------- 6071 6072`-marc[5|6|7|8]' 6073 This option selects the core processor variant. Using `-marc' is 6074 the same as `-marc6', which is also the default. 6075 6076 `arc5' 6077 Base instruction set. 6078 6079 `arc6' 6080 Jump-and-link (jl) instruction. No requirement of an 6081 instruction between setting flags and conditional jump. For 6082 example: 6083 6084 mov.f r0,r1 6085 beq foo 6086 6087 `arc7' 6088 Break (brk) and sleep (sleep) instructions. 6089 6090 `arc8' 6091 Software interrupt (swi) instruction. 6092 6093 6094 Note: the `.option' directive can to be used to select a core 6095 variant from within assembly code. 6096 6097`-EB' 6098 This option specifies that the output generated by the assembler 6099 should be marked as being encoded for a big-endian processor. 6100 6101`-EL' 6102 This option specifies that the output generated by the assembler 6103 should be marked as being encoded for a little-endian processor - 6104 this is the default. 6105 6106 6107 6108File: as.info, Node: ARC Syntax, Next: ARC Floating Point, Prev: ARC Options, Up: ARC-Dependent 6109 61109.2.2 Syntax 6111------------ 6112 6113* Menu: 6114 6115* ARC-Chars:: Special Characters 6116* ARC-Regs:: Register Names 6117 6118 6119File: as.info, Node: ARC-Chars, Next: ARC-Regs, Up: ARC Syntax 6120 61219.2.2.1 Special Characters 6122.......................... 6123 6124The presence of a `#' on a line indicates the start of a comment that 6125extends to the end of the current line. Note that if a line starts 6126with a `#' character then it can also be a logical line number 6127directive (*note Comments::) or a preprocessor control command (*note 6128Preprocessing::). 6129 6130 The ARC assembler does not support a line separator character. 6131 6132 6133File: as.info, Node: ARC-Regs, Prev: ARC-Chars, Up: ARC Syntax 6134 61359.2.2.2 Register Names 6136...................... 6137 6138*TODO* 6139 6140 6141File: as.info, Node: ARC Floating Point, Next: ARC Directives, Prev: ARC Syntax, Up: ARC-Dependent 6142 61439.2.3 Floating Point 6144-------------------- 6145 6146The ARC core does not currently have hardware floating point support. 6147Software floating point support is provided by `GCC' and uses IEEE 6148floating-point numbers. 6149 6150 6151File: as.info, Node: ARC Directives, Next: ARC Opcodes, Prev: ARC Floating Point, Up: ARC-Dependent 6152 61539.2.4 ARC Machine Directives 6154---------------------------- 6155 6156The ARC version of `as' supports the following additional machine 6157directives: 6158 6159`.2byte EXPRESSIONS' 6160 *TODO* 6161 6162`.3byte EXPRESSIONS' 6163 *TODO* 6164 6165`.4byte EXPRESSIONS' 6166 *TODO* 6167 6168`.extAuxRegister NAME,ADDRESS,MODE' 6169 The ARCtangent A4 has extensible auxiliary register space. The 6170 auxiliary registers can be defined in the assembler source code by 6171 using this directive. The first parameter is the NAME of the new 6172 auxiallry register. The second parameter is the ADDRESS of the 6173 register in the auxiliary register memory map for the variant of 6174 the ARC. The third parameter specifies the MODE in which the 6175 register can be operated is and it can be one of: 6176 6177 `r (readonly)' 6178 6179 `w (write only)' 6180 6181 `r|w (read or write)' 6182 6183 For example: 6184 6185 .extAuxRegister mulhi,0x12,w 6186 6187 This specifies an extension auxiliary register called _mulhi_ 6188 which is at address 0x12 in the memory space and which is only 6189 writable. 6190 6191`.extCondCode SUFFIX,VALUE' 6192 The condition codes on the ARCtangent A4 are extensible and can be 6193 specified by means of this assembler directive. They are specified 6194 by the suffix and the value for the condition code. They can be 6195 used to specify extra condition codes with any values. For 6196 example: 6197 6198 .extCondCode is_busy,0x14 6199 6200 add.is_busy r1,r2,r3 6201 bis_busy _main 6202 6203`.extCoreRegister NAME,REGNUM,MODE,SHORTCUT' 6204 Specifies an extension core register NAME for the application. 6205 This allows a register NAME with a valid REGNUM between 0 and 60, 6206 with the following as valid values for MODE 6207 6208 `_r_ (readonly)' 6209 6210 `_w_ (write only)' 6211 6212 `_r|w_ (read or write)' 6213 6214 The other parameter gives a description of the register having a 6215 SHORTCUT in the pipeline. The valid values are: 6216 6217 `can_shortcut' 6218 6219 `cannot_shortcut' 6220 6221 For example: 6222 6223 .extCoreRegister mlo,57,r,can_shortcut 6224 6225 This defines an extension core register mlo with the value 57 which 6226 can shortcut the pipeline. 6227 6228`.extInstruction NAME,OPCODE,SUBOPCODE,SUFFIXCLASS,SYNTAXCLASS' 6229 The ARCtangent A4 allows the user to specify extension 6230 instructions. The extension instructions are not macros. The 6231 assembler creates encodings for use of these instructions 6232 according to the specification by the user. The parameters are: 6233 6234 *NAME 6235 Name of the extension instruction 6236 6237 *OPCODE 6238 Opcode to be used. (Bits 27:31 in the encoding). Valid values 6239 0x10-0x1f or 0x03 6240 6241 *SUBOPCODE 6242 Subopcode to be used. Valid values are from 0x09-0x3f. 6243 However the correct value also depends on SYNTAXCLASS 6244 6245 *SUFFIXCLASS 6246 Determines the kinds of suffixes to be allowed. Valid values 6247 are `SUFFIX_NONE', `SUFFIX_COND', `SUFFIX_FLAG' which 6248 indicates the absence or presence of conditional suffixes and 6249 flag setting by the extension instruction. It is also 6250 possible to specify that an instruction sets the flags and is 6251 conditional by using `SUFFIX_CODE' | `SUFFIX_FLAG'. 6252 6253 *SYNTAXCLASS 6254 Determines the syntax class for the instruction. It can have 6255 the following values: 6256 6257 ``SYNTAX_2OP':' 6258 2 Operand Instruction 6259 6260 ``SYNTAX_3OP':' 6261 3 Operand Instruction 6262 6263 In addition there could be modifiers for the syntax class as 6264 described below: 6265 6266 Syntax Class Modifiers are: 6267 6268 - `OP1_MUST_BE_IMM': Modifies syntax class SYNTAX_3OP, 6269 specifying that the first operand of a three-operand 6270 instruction must be an immediate (i.e., the result is 6271 discarded). OP1_MUST_BE_IMM is used by bitwise ORing it 6272 with SYNTAX_3OP as given in the example below. This 6273 could usually be used to set the flags using specific 6274 instructions and not retain results. 6275 6276 - `OP1_IMM_IMPLIED': Modifies syntax class SYNTAX_20P, it 6277 specifies that there is an implied immediate destination 6278 operand which does not appear in the syntax. For 6279 example, if the source code contains an instruction like: 6280 6281 inst r1,r2 6282 6283 it really means that the first argument is an implied 6284 immediate (that is, the result is discarded). This is 6285 the same as though the source code were: inst 0,r1,r2. 6286 You use OP1_IMM_IMPLIED by bitwise ORing it with 6287 SYNTAX_20P. 6288 6289 6290 For example, defining 64-bit multiplier with immediate operands: 6291 6292 .extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG , 6293 SYNTAX_3OP|OP1_MUST_BE_IMM 6294 6295 The above specifies an extension instruction called mp64 which has 6296 3 operands, sets the flags, can be used with a condition code, for 6297 which the first operand is an immediate. (Equivalent to 6298 discarding the result of the operation). 6299 6300 .extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED 6301 6302 This describes a 2 operand instruction with an implicit first 6303 immediate operand. The result of this operation would be 6304 discarded. 6305 6306`.half EXPRESSIONS' 6307 *TODO* 6308 6309`.long EXPRESSIONS' 6310 *TODO* 6311 6312`.option ARC|ARC5|ARC6|ARC7|ARC8' 6313 The `.option' directive must be followed by the desired core 6314 version. Again `arc' is an alias for `arc6'. 6315 6316 Note: the `.option' directive overrides the command line option 6317 `-marc'; a warning is emitted when the version is not consistent 6318 between the two - even for the implicit default core version 6319 (arc6). 6320 6321`.short EXPRESSIONS' 6322 *TODO* 6323 6324`.word EXPRESSIONS' 6325 *TODO* 6326 6327 6328 6329File: as.info, Node: ARC Opcodes, Prev: ARC Directives, Up: ARC-Dependent 6330 63319.2.5 Opcodes 6332------------- 6333 6334For information on the ARC instruction set, see `ARC Programmers 6335Reference Manual', ARC International (www.arc.com) 6336 6337 6338File: as.info, Node: ARM-Dependent, Next: AVR-Dependent, Prev: ARC-Dependent, Up: Machine Dependencies 6339 63409.3 ARM Dependent Features 6341========================== 6342 6343* Menu: 6344 6345* ARM Options:: Options 6346* ARM Syntax:: Syntax 6347* ARM Floating Point:: Floating Point 6348* ARM Directives:: ARM Machine Directives 6349* ARM Opcodes:: Opcodes 6350* ARM Mapping Symbols:: Mapping Symbols 6351* ARM Unwinding Tutorial:: Unwinding 6352 6353 6354File: as.info, Node: ARM Options, Next: ARM Syntax, Up: ARM-Dependent 6355 63569.3.1 Options 6357------------- 6358 6359`-mcpu=PROCESSOR[+EXTENSION...]' 6360 This option specifies the target processor. The assembler will 6361 issue an error message if an attempt is made to assemble an 6362 instruction which will not execute on the target processor. The 6363 following processor names are recognized: `arm1', `arm2', `arm250', 6364 `arm3', `arm6', `arm60', `arm600', `arm610', `arm620', `arm7', 6365 `arm7m', `arm7d', `arm7dm', `arm7di', `arm7dmi', `arm70', `arm700', 6366 `arm700i', `arm710', `arm710t', `arm720', `arm720t', `arm740t', 6367 `arm710c', `arm7100', `arm7500', `arm7500fe', `arm7t', `arm7tdmi', 6368 `arm7tdmi-s', `arm8', `arm810', `strongarm', `strongarm1', 6369 `strongarm110', `strongarm1100', `strongarm1110', `arm9', `arm920', 6370 `arm920t', `arm922t', `arm940t', `arm9tdmi', `fa526' (Faraday 6371 FA526 processor), `fa626' (Faraday FA626 processor), `arm9e', 6372 `arm926e', `arm926ej-s', `arm946e-r0', `arm946e', `arm946e-s', 6373 `arm966e-r0', `arm966e', `arm966e-s', `arm968e-s', `arm10t', 6374 `arm10tdmi', `arm10e', `arm1020', `arm1020t', `arm1020e', 6375 `arm1022e', `arm1026ej-s', `fa606te' (Faraday FA606TE processor), 6376 `fa616te' (Faraday FA616TE processor), `fa626te' (Faraday FA626TE 6377 processor), `fmp626' (Faraday FMP626 processor), `fa726te' 6378 (Faraday FA726TE processor), `arm1136j-s', `arm1136jf-s', 6379 `arm1156t2-s', `arm1156t2f-s', `arm1176jz-s', `arm1176jzf-s', 6380 `mpcore', `mpcorenovfp', `cortex-a5', `cortex-a8', `cortex-a9', 6381 `cortex-a15', `cortex-r4', `cortex-r4f', `cortex-m4', `cortex-m3', 6382 `cortex-m1', `cortex-m0', `ep9312' (ARM920 with Cirrus Maverick 6383 coprocessor), `i80200' (Intel XScale processor) `iwmmxt' (Intel(r) 6384 XScale processor with Wireless MMX(tm) technology coprocessor) and 6385 `xscale'. The special name `all' may be used to allow the 6386 assembler to accept instructions valid for any ARM processor. 6387 6388 In addition to the basic instruction set, the assembler can be 6389 told to accept various extension mnemonics that extend the 6390 processor using the co-processor instruction space. For example, 6391 `-mcpu=arm920+maverick' is equivalent to specifying `-mcpu=ep9312'. 6392 6393 Multiple extensions may be specified, separated by a `+'. The 6394 extensions should be specified in ascending alphabetical order. 6395 6396 Some extensions may be restricted to particular architectures; 6397 this is documented in the list of extensions below. 6398 6399 Extension mnemonics may also be removed from those the assembler 6400 accepts. This is done be prepending `no' to the option that adds 6401 the extension. Extensions that are removed should be listed after 6402 all extensions which have been added, again in ascending 6403 alphabetical order. For example, `-mcpu=ep9312+nomaverick' is 6404 equivalent to specifying `-mcpu=arm920'. 6405 6406 The following extensions are currently supported: `idiv', (Integer 6407 Divide Extensions for v7-A and v7-R architectures), `iwmmxt', 6408 `iwmmxt2', `maverick', `mp' (Multiprocessing Extensions for v7-A 6409 and v7-R architectures), `os' (Operating System for v6M 6410 architecture), `sec' (Security Extensions for v6K and v7-A 6411 architectures), `virt' (Virtualization Extensions for v7-A 6412 architecture, implies `idiv'), and `xscale'. 6413 6414`-march=ARCHITECTURE[+EXTENSION...]' 6415 This option specifies the target architecture. The assembler will 6416 issue an error message if an attempt is made to assemble an 6417 instruction which will not execute on the target architecture. 6418 The following architecture names are recognized: `armv1', `armv2', 6419 `armv2a', `armv2s', `armv3', `armv3m', `armv4', `armv4xm', 6420 `armv4t', `armv4txm', `armv5', `armv5t', `armv5txm', `armv5te', 6421 `armv5texp', `armv6', `armv6j', `armv6k', `armv6z', `armv6zk', 6422 `armv6-m', `armv6s-m', `armv7', `armv7-a', `armv7-r', `armv7-m', 6423 `armv7e-m', `iwmmxt' and `xscale'. If both `-mcpu' and `-march' 6424 are specified, the assembler will use the setting for `-mcpu'. 6425 6426 The architecture option can be extended with the same instruction 6427 set extension options as the `-mcpu' option. 6428 6429`-mfpu=FLOATING-POINT-FORMAT' 6430 This option specifies the floating point format to assemble for. 6431 The assembler will issue an error message if an attempt is made to 6432 assemble an instruction which will not execute on the target 6433 floating point unit. The following format options are recognized: 6434 `softfpa', `fpe', `fpe2', `fpe3', `fpa', `fpa10', `fpa11', 6435 `arm7500fe', `softvfp', `softvfp+vfp', `vfp', `vfp10', `vfp10-r0', 6436 `vfp9', `vfpxd', `vfpv2', `vfpv3', `vfpv3-fp16', `vfpv3-d16', 6437 `vfpv3-d16-fp16', `vfpv3xd', `vfpv3xd-d16', `vfpv4', `vfpv4-d16', 6438 `fpv4-sp-d16', `arm1020t', `arm1020e', `arm1136jf-s', `maverick', 6439 `neon', and `neon-vfpv4'. 6440 6441 In addition to determining which instructions are assembled, this 6442 option also affects the way in which the `.double' assembler 6443 directive behaves when assembling little-endian code. 6444 6445 The default is dependent on the processor selected. For 6446 Architecture 5 or later, the default is to assembler for VFP 6447 instructions; for earlier architectures the default is to assemble 6448 for FPA instructions. 6449 6450`-mthumb' 6451 This option specifies that the assembler should start assembling 6452 Thumb instructions; that is, it should behave as though the file 6453 starts with a `.code 16' directive. 6454 6455`-mthumb-interwork' 6456 This option specifies that the output generated by the assembler 6457 should be marked as supporting interworking. 6458 6459`-mimplicit-it=never' 6460`-mimplicit-it=always' 6461`-mimplicit-it=arm' 6462`-mimplicit-it=thumb' 6463 The `-mimplicit-it' option controls the behavior of the assembler 6464 when conditional instructions are not enclosed in IT blocks. 6465 There are four possible behaviors. If `never' is specified, such 6466 constructs cause a warning in ARM code and an error in Thumb-2 6467 code. If `always' is specified, such constructs are accepted in 6468 both ARM and Thumb-2 code, where the IT instruction is added 6469 implicitly. If `arm' is specified, such constructs are accepted 6470 in ARM code and cause an error in Thumb-2 code. If `thumb' is 6471 specified, such constructs cause a warning in ARM code and are 6472 accepted in Thumb-2 code. If you omit this option, the behavior 6473 is equivalent to `-mimplicit-it=arm'. 6474 6475`-mapcs-26' 6476`-mapcs-32' 6477 These options specify that the output generated by the assembler 6478 should be marked as supporting the indicated version of the Arm 6479 Procedure. Calling Standard. 6480 6481`-matpcs' 6482 This option specifies that the output generated by the assembler 6483 should be marked as supporting the Arm/Thumb Procedure Calling 6484 Standard. If enabled this option will cause the assembler to 6485 create an empty debugging section in the object file called 6486 .arm.atpcs. Debuggers can use this to determine the ABI being 6487 used by. 6488 6489`-mapcs-float' 6490 This indicates the floating point variant of the APCS should be 6491 used. In this variant floating point arguments are passed in FP 6492 registers rather than integer registers. 6493 6494`-mapcs-reentrant' 6495 This indicates that the reentrant variant of the APCS should be 6496 used. This variant supports position independent code. 6497 6498`-mfloat-abi=ABI' 6499 This option specifies that the output generated by the assembler 6500 should be marked as using specified floating point ABI. The 6501 following values are recognized: `soft', `softfp' and `hard'. 6502 6503`-meabi=VER' 6504 This option specifies which EABI version the produced object files 6505 should conform to. The following values are recognized: `gnu', `4' 6506 and `5'. 6507 6508`-EB' 6509 This option specifies that the output generated by the assembler 6510 should be marked as being encoded for a big-endian processor. 6511 6512`-EL' 6513 This option specifies that the output generated by the assembler 6514 should be marked as being encoded for a little-endian processor. 6515 6516`-k' 6517 This option specifies that the output of the assembler should be 6518 marked as position-independent code (PIC). 6519 6520`--fix-v4bx' 6521 Allow `BX' instructions in ARMv4 code. This is intended for use 6522 with the linker option of the same name. 6523 6524`-mwarn-deprecated' 6525`-mno-warn-deprecated' 6526 Enable or disable warnings about using deprecated options or 6527 features. The default is to warn. 6528 6529 6530 6531File: as.info, Node: ARM Syntax, Next: ARM Floating Point, Prev: ARM Options, Up: ARM-Dependent 6532 65339.3.2 Syntax 6534------------ 6535 6536* Menu: 6537 6538* ARM-Instruction-Set:: Instruction Set 6539* ARM-Chars:: Special Characters 6540* ARM-Regs:: Register Names 6541* ARM-Relocations:: Relocations 6542* ARM-Neon-Alignment:: NEON Alignment Specifiers 6543 6544 6545File: as.info, Node: ARM-Instruction-Set, Next: ARM-Chars, Up: ARM Syntax 6546 65479.3.2.1 Instruction Set Syntax 6548.............................. 6549 6550Two slightly different syntaxes are support for ARM and THUMB 6551instructions. The default, `divided', uses the old style where ARM and 6552THUMB instructions had their own, separate syntaxes. The new, 6553`unified' syntax, which can be selected via the `.syntax' directive, 6554and has the following main features: 6555 6556* 6557 Immediate operands do not require a `#' prefix. 6558 6559* 6560 The `IT' instruction may appear, and if it does it is validated 6561 against subsequent conditional affixes. In ARM mode it does not 6562 generate machine code, in THUMB mode it does. 6563 6564* 6565 For ARM instructions the conditional affixes always appear at the 6566 end of the instruction. For THUMB instructions conditional 6567 affixes can be used, but only inside the scope of an `IT' 6568 instruction. 6569 6570* 6571 All of the instructions new to the V6T2 architecture (and later) 6572 are available. (Only a few such instructions can be written in the 6573 `divided' syntax). 6574 6575* 6576 The `.N' and `.W' suffixes are recognized and honored. 6577 6578* 6579 All instructions set the flags if and only if they have an `s' 6580 affix. 6581 6582 6583File: as.info, Node: ARM-Chars, Next: ARM-Regs, Prev: ARM-Instruction-Set, Up: ARM Syntax 6584 65859.3.2.2 Special Characters 6586.......................... 6587 6588The presence of a `@' anywhere on a line indicates the start of a 6589comment that extends to the end of that line. 6590 6591 If a `#' appears as the first character of a line then the whole 6592line is treated as a comment, but in this case the line could also be a 6593logical line number directive (*note Comments::) or a preprocessor 6594control command (*note Preprocessing::). 6595 6596 The `;' character can be used instead of a newline to separate 6597statements. 6598 6599 Either `#' or `$' can be used to indicate immediate operands. 6600 6601 *TODO* Explain about /data modifier on symbols. 6602 6603 6604File: as.info, Node: ARM-Regs, Next: ARM-Relocations, Prev: ARM-Chars, Up: ARM Syntax 6605 66069.3.2.3 Register Names 6607...................... 6608 6609*TODO* Explain about ARM register naming, and the predefined names. 6610 6611 6612File: as.info, Node: ARM-Neon-Alignment, Prev: ARM-Relocations, Up: ARM Syntax 6613 66149.3.2.4 NEON Alignment Specifiers 6615................................. 6616 6617Some NEON load/store instructions allow an optional address alignment 6618qualifier. The ARM documentation specifies that this is indicated by 6619`@ ALIGN'. However GAS already interprets the `@' character as a "line 6620comment" start, so `: ALIGN' is used instead. For example: 6621 6622 vld1.8 {q0}, [r0, :128] 6623 6624 6625File: as.info, Node: ARM Floating Point, Next: ARM Directives, Prev: ARM Syntax, Up: ARM-Dependent 6626 66279.3.3 Floating Point 6628-------------------- 6629 6630The ARM family uses IEEE floating-point numbers. 6631 6632 6633File: as.info, Node: ARM-Relocations, Next: ARM-Neon-Alignment, Prev: ARM-Regs, Up: ARM Syntax 6634 66359.3.3.1 ARM relocation generation 6636................................. 6637 6638Specific data relocations can be generated by putting the relocation 6639name in parentheses after the symbol name. For example: 6640 6641 .word foo(TARGET1) 6642 6643 This will generate an `R_ARM_TARGET1' relocation against the symbol 6644FOO. The following relocations are supported: `GOT', `GOTOFF', 6645`TARGET1', `TARGET2', `SBREL', `TLSGD', `TLSLDM', `TLSLDO', `TLSDESC', 6646`TLSCALL', `GOTTPOFF', `GOT_PREL' and `TPOFF'. 6647 6648 For compatibility with older toolchains the assembler also accepts 6649`(PLT)' after branch targets. This will generate the deprecated 6650`R_ARM_PLT32' relocation. 6651 6652 Relocations for `MOVW' and `MOVT' instructions can be generated by 6653prefixing the value with `#:lower16:' and `#:upper16' respectively. 6654For example to load the 32-bit address of foo into r0: 6655 6656 MOVW r0, #:lower16:foo 6657 MOVT r0, #:upper16:foo 6658 6659 6660File: as.info, Node: ARM Directives, Next: ARM Opcodes, Prev: ARM Floating Point, Up: ARM-Dependent 6661 66629.3.4 ARM Machine Directives 6663---------------------------- 6664 6665`.2byte EXPRESSION [, EXPRESSION]*' 6666`.4byte EXPRESSION [, EXPRESSION]*' 6667`.8byte EXPRESSION [, EXPRESSION]*' 6668 These directives write 2, 4 or 8 byte values to the output section. 6669 6670`.align EXPRESSION [, EXPRESSION]' 6671 This is the generic .ALIGN directive. For the ARM however if the 6672 first argument is zero (ie no alignment is needed) the assembler 6673 will behave as if the argument had been 2 (ie pad to the next four 6674 byte boundary). This is for compatibility with ARM's own 6675 assembler. 6676 6677`.arch NAME' 6678 Select the target architecture. Valid values for NAME are the 6679 same as for the `-march' commandline option. 6680 6681 Specifying `.arch' clears any previously selected architecture 6682 extensions. 6683 6684`.arch_extension NAME' 6685 Add or remove an architecture extension to the target 6686 architecture. Valid values for NAME are the same as those 6687 accepted as architectural extensions by the `-mcpu' commandline 6688 option. 6689 6690 `.arch_extension' may be used multiple times to add or remove 6691 extensions incrementally to the architecture being compiled for. 6692 6693`.arm' 6694 This performs the same action as .CODE 32. 6695 6696`.pad #COUNT' 6697 Generate unwinder annotations for a stack adjustment of COUNT 6698 bytes. A positive value indicates the function prologue allocated 6699 stack space by decrementing the stack pointer. 6700 6701`.bss' 6702 This directive switches to the `.bss' section. 6703 6704`.cantunwind' 6705 Prevents unwinding through the current function. No personality 6706 routine or exception table data is required or permitted. 6707 6708`.code `[16|32]'' 6709 This directive selects the instruction set being generated. The 6710 value 16 selects Thumb, with the value 32 selecting ARM. 6711 6712`.cpu NAME' 6713 Select the target processor. Valid values for NAME are the same as 6714 for the `-mcpu' commandline option. 6715 6716 Specifying `.cpu' clears any previously selected architecture 6717 extensions. 6718 6719`NAME .dn REGISTER NAME [.TYPE] [[INDEX]]' 6720`NAME .qn REGISTER NAME [.TYPE] [[INDEX]]' 6721 The `dn' and `qn' directives are used to create typed and/or 6722 indexed register aliases for use in Advanced SIMD Extension (Neon) 6723 instructions. The former should be used to create aliases of 6724 double-precision registers, and the latter to create aliases of 6725 quad-precision registers. 6726 6727 If these directives are used to create typed aliases, those 6728 aliases can be used in Neon instructions instead of writing types 6729 after the mnemonic or after each operand. For example: 6730 6731 x .dn d2.f32 6732 y .dn d3.f32 6733 z .dn d4.f32[1] 6734 vmul x,y,z 6735 6736 This is equivalent to writing the following: 6737 6738 vmul.f32 d2,d3,d4[1] 6739 6740 Aliases created using `dn' or `qn' can be destroyed using `unreq'. 6741 6742`.eabi_attribute TAG, VALUE' 6743 Set the EABI object attribute TAG to VALUE. 6744 6745 The TAG is either an attribute number, or one of the following: 6746 `Tag_CPU_raw_name', `Tag_CPU_name', `Tag_CPU_arch', 6747 `Tag_CPU_arch_profile', `Tag_ARM_ISA_use', `Tag_THUMB_ISA_use', 6748 `Tag_FP_arch', `Tag_WMMX_arch', `Tag_Advanced_SIMD_arch', 6749 `Tag_PCS_config', `Tag_ABI_PCS_R9_use', `Tag_ABI_PCS_RW_data', 6750 `Tag_ABI_PCS_RO_data', `Tag_ABI_PCS_GOT_use', 6751 `Tag_ABI_PCS_wchar_t', `Tag_ABI_FP_rounding', 6752 `Tag_ABI_FP_denormal', `Tag_ABI_FP_exceptions', 6753 `Tag_ABI_FP_user_exceptions', `Tag_ABI_FP_number_model', 6754 `Tag_ABI_align_needed', `Tag_ABI_align_preserved', 6755 `Tag_ABI_enum_size', `Tag_ABI_HardFP_use', `Tag_ABI_VFP_args', 6756 `Tag_ABI_WMMX_args', `Tag_ABI_optimization_goals', 6757 `Tag_ABI_FP_optimization_goals', `Tag_compatibility', 6758 `Tag_CPU_unaligned_access', `Tag_FP_HP_extension', 6759 `Tag_ABI_FP_16bit_format', `Tag_MPextension_use', `Tag_DIV_use', 6760 `Tag_nodefaults', `Tag_also_compatible_with', `Tag_conformance', 6761 `Tag_T2EE_use', `Tag_Virtualization_use' 6762 6763 The VALUE is either a `number', `"string"', or `number, "string"' 6764 depending on the tag. 6765 6766 Note - the following legacy values are also accepted by TAG: 6767 `Tag_VFP_arch', `Tag_ABI_align8_needed', 6768 `Tag_ABI_align8_preserved', `Tag_VFP_HP_extension', 6769 6770`.even' 6771 This directive aligns to an even-numbered address. 6772 6773`.extend EXPRESSION [, EXPRESSION]*' 6774`.ldouble EXPRESSION [, EXPRESSION]*' 6775 These directives write 12byte long double floating-point values to 6776 the output section. These are not compatible with current ARM 6777 processors or ABIs. 6778 6779`.fnend' 6780 Marks the end of a function with an unwind table entry. The 6781 unwind index table entry is created when this directive is 6782 processed. 6783 6784 If no personality routine has been specified then standard 6785 personality routine 0 or 1 will be used, depending on the number 6786 of unwind opcodes required. 6787 6788`.fnstart' 6789 Marks the start of a function with an unwind table entry. 6790 6791`.force_thumb' 6792 This directive forces the selection of Thumb instructions, even if 6793 the target processor does not support those instructions 6794 6795`.fpu NAME' 6796 Select the floating-point unit to assemble for. Valid values for 6797 NAME are the same as for the `-mfpu' commandline option. 6798 6799`.handlerdata' 6800 Marks the end of the current function, and the start of the 6801 exception table entry for that function. Anything between this 6802 directive and the `.fnend' directive will be added to the 6803 exception table entry. 6804 6805 Must be preceded by a `.personality' or `.personalityindex' 6806 directive. 6807 6808`.inst OPCODE [ , ... ]' 6809`.inst.n OPCODE [ , ... ]' 6810`.inst.w OPCODE [ , ... ]' 6811 Generates the instruction corresponding to the numerical value 6812 OPCODE. `.inst.n' and `.inst.w' allow the Thumb instruction size 6813 to be specified explicitly, overriding the normal encoding rules. 6814 6815`.ldouble EXPRESSION [, EXPRESSION]*' 6816 See `.extend'. 6817 6818`.ltorg' 6819 This directive causes the current contents of the literal pool to 6820 be dumped into the current section (which is assumed to be the 6821 .text section) at the current location (aligned to a word 6822 boundary). `GAS' maintains a separate literal pool for each 6823 section and each sub-section. The `.ltorg' directive will only 6824 affect the literal pool of the current section and sub-section. 6825 At the end of assembly all remaining, un-empty literal pools will 6826 automatically be dumped. 6827 6828 Note - older versions of `GAS' would dump the current literal pool 6829 any time a section change occurred. This is no longer done, since 6830 it prevents accurate control of the placement of literal pools. 6831 6832`.movsp REG [, #OFFSET]' 6833 Tell the unwinder that REG contains an offset from the current 6834 stack pointer. If OFFSET is not specified then it is assumed to be 6835 zero. 6836 6837`.object_arch NAME' 6838 Override the architecture recorded in the EABI object attribute 6839 section. Valid values for NAME are the same as for the `.arch' 6840 directive. Typically this is useful when code uses runtime 6841 detection of CPU features. 6842 6843`.packed EXPRESSION [, EXPRESSION]*' 6844 This directive writes 12-byte packed floating-point values to the 6845 output section. These are not compatible with current ARM 6846 processors or ABIs. 6847 6848`.pad #COUNT' 6849 Generate unwinder annotations for a stack adjustment of COUNT 6850 bytes. A positive value indicates the function prologue allocated 6851 stack space by decrementing the stack pointer. 6852 6853`.personality NAME' 6854 Sets the personality routine for the current function to NAME. 6855 6856`.personalityindex INDEX' 6857 Sets the personality routine for the current function to the EABI 6858 standard routine number INDEX 6859 6860`.pool' 6861 This is a synonym for .ltorg. 6862 6863`NAME .req REGISTER NAME' 6864 This creates an alias for REGISTER NAME called NAME. For example: 6865 6866 foo .req r0 6867 6868`.save REGLIST' 6869 Generate unwinder annotations to restore the registers in REGLIST. 6870 The format of REGLIST is the same as the corresponding 6871 store-multiple instruction. 6872 6873 _core registers_ 6874 .save {r4, r5, r6, lr} 6875 stmfd sp!, {r4, r5, r6, lr} 6876 _FPA registers_ 6877 .save f4, 2 6878 sfmfd f4, 2, [sp]! 6879 _VFP registers_ 6880 .save {d8, d9, d10} 6881 fstmdx sp!, {d8, d9, d10} 6882 _iWMMXt registers_ 6883 .save {wr10, wr11} 6884 wstrd wr11, [sp, #-8]! 6885 wstrd wr10, [sp, #-8]! 6886 or 6887 .save wr11 6888 wstrd wr11, [sp, #-8]! 6889 .save wr10 6890 wstrd wr10, [sp, #-8]! 6891 6892`.setfp FPREG, SPREG [, #OFFSET]' 6893 Make all unwinder annotations relative to a frame pointer. 6894 Without this the unwinder will use offsets from the stack pointer. 6895 6896 The syntax of this directive is the same as the `add' or `mov' 6897 instruction used to set the frame pointer. SPREG must be either 6898 `sp' or mentioned in a previous `.movsp' directive. 6899 6900 .movsp ip 6901 mov ip, sp 6902 ... 6903 .setfp fp, ip, #4 6904 add fp, ip, #4 6905 6906`.secrel32 EXPRESSION [, EXPRESSION]*' 6907 This directive emits relocations that evaluate to the 6908 section-relative offset of each expression's symbol. This 6909 directive is only supported for PE targets. 6910 6911`.syntax [`unified' | `divided']' 6912 This directive sets the Instruction Set Syntax as described in the 6913 *note ARM-Instruction-Set:: section. 6914 6915`.thumb' 6916 This performs the same action as .CODE 16. 6917 6918`.thumb_func' 6919 This directive specifies that the following symbol is the name of a 6920 Thumb encoded function. This information is necessary in order to 6921 allow the assembler and linker to generate correct code for 6922 interworking between Arm and Thumb instructions and should be used 6923 even if interworking is not going to be performed. The presence 6924 of this directive also implies `.thumb' 6925 6926 This directive is not neccessary when generating EABI objects. On 6927 these targets the encoding is implicit when generating Thumb code. 6928 6929`.thumb_set' 6930 This performs the equivalent of a `.set' directive in that it 6931 creates a symbol which is an alias for another symbol (possibly 6932 not yet defined). This directive also has the added property in 6933 that it marks the aliased symbol as being a thumb function entry 6934 point, in the same way that the `.thumb_func' directive does. 6935 6936`.tlsdescseq TLS-VARIABLE' 6937 This directive is used to annotate parts of an inlined TLS 6938 descriptor trampoline. Normally the trampoline is provided by the 6939 linker, and this directive is not needed. 6940 6941`.unreq ALIAS-NAME' 6942 This undefines a register alias which was previously defined using 6943 the `req', `dn' or `qn' directives. For example: 6944 6945 foo .req r0 6946 .unreq foo 6947 6948 An error occurs if the name is undefined. Note - this pseudo op 6949 can be used to delete builtin in register name aliases (eg 'r0'). 6950 This should only be done if it is really necessary. 6951 6952`.unwind_raw OFFSET, BYTE1, ...' 6953 Insert one of more arbitary unwind opcode bytes, which are known 6954 to adjust the stack pointer by OFFSET bytes. 6955 6956 For example `.unwind_raw 4, 0xb1, 0x01' is equivalent to `.save 6957 {r0}' 6958 6959`.vsave VFP-REGLIST' 6960 Generate unwinder annotations to restore the VFP registers in 6961 VFP-REGLIST using FLDMD. Also works for VFPv3 registers that are 6962 to be restored using VLDM. The format of VFP-REGLIST is the same 6963 as the corresponding store-multiple instruction. 6964 6965 _VFP registers_ 6966 .vsave {d8, d9, d10} 6967 fstmdd sp!, {d8, d9, d10} 6968 _VFPv3 registers_ 6969 .vsave {d15, d16, d17} 6970 vstm sp!, {d15, d16, d17} 6971 6972 Since FLDMX and FSTMX are now deprecated, this directive should be 6973 used in favour of `.save' for saving VFP registers for ARMv6 and 6974 above. 6975 6976 6977 6978File: as.info, Node: ARM Opcodes, Next: ARM Mapping Symbols, Prev: ARM Directives, Up: ARM-Dependent 6979 69809.3.5 Opcodes 6981------------- 6982 6983`as' implements all the standard ARM opcodes. It also implements 6984several pseudo opcodes, including several synthetic load instructions. 6985 6986`NOP' 6987 nop 6988 6989 This pseudo op will always evaluate to a legal ARM instruction 6990 that does nothing. Currently it will evaluate to MOV r0, r0. 6991 6992`LDR' 6993 ldr <register> , = <expression> 6994 6995 If expression evaluates to a numeric constant then a MOV or MVN 6996 instruction will be used in place of the LDR instruction, if the 6997 constant can be generated by either of these instructions. 6998 Otherwise the constant will be placed into the nearest literal 6999 pool (if it not already there) and a PC relative LDR instruction 7000 will be generated. 7001 7002`ADR' 7003 adr <register> <label> 7004 7005 This instruction will load the address of LABEL into the indicated 7006 register. The instruction will evaluate to a PC relative ADD or 7007 SUB instruction depending upon where the label is located. If the 7008 label is out of range, or if it is not defined in the same file 7009 (and section) as the ADR instruction, then an error will be 7010 generated. This instruction will not make use of the literal pool. 7011 7012`ADRL' 7013 adrl <register> <label> 7014 7015 This instruction will load the address of LABEL into the indicated 7016 register. The instruction will evaluate to one or two PC relative 7017 ADD or SUB instructions depending upon where the label is located. 7018 If a second instruction is not needed a NOP instruction will be 7019 generated in its place, so that this instruction is always 8 bytes 7020 long. 7021 7022 If the label is out of range, or if it is not defined in the same 7023 file (and section) as the ADRL instruction, then an error will be 7024 generated. This instruction will not make use of the literal pool. 7025 7026 7027 For information on the ARM or Thumb instruction sets, see `ARM 7028Software Development Toolkit Reference Manual', Advanced RISC Machines 7029Ltd. 7030 7031 7032File: as.info, Node: ARM Mapping Symbols, Next: ARM Unwinding Tutorial, Prev: ARM Opcodes, Up: ARM-Dependent 7033 70349.3.6 Mapping Symbols 7035--------------------- 7036 7037The ARM ELF specification requires that special symbols be inserted 7038into object files to mark certain features: 7039 7040`$a' 7041 At the start of a region of code containing ARM instructions. 7042 7043`$t' 7044 At the start of a region of code containing THUMB instructions. 7045 7046`$d' 7047 At the start of a region of data. 7048 7049 7050 The assembler will automatically insert these symbols for you - there 7051is no need to code them yourself. Support for tagging symbols ($b, $f, 7052$p and $m) which is also mentioned in the current ARM ELF specification 7053is not implemented. This is because they have been dropped from the 7054new EABI and so tools cannot rely upon their presence. 7055 7056 7057File: as.info, Node: ARM Unwinding Tutorial, Prev: ARM Mapping Symbols, Up: ARM-Dependent 7058 70599.3.7 Unwinding 7060--------------- 7061 7062The ABI for the ARM Architecture specifies a standard format for 7063exception unwind information. This information is used when an 7064exception is thrown to determine where control should be transferred. 7065In particular, the unwind information is used to determine which 7066function called the function that threw the exception, and which 7067function called that one, and so forth. This information is also used 7068to restore the values of callee-saved registers in the function 7069catching the exception. 7070 7071 If you are writing functions in assembly code, and those functions 7072call other functions that throw exceptions, you must use assembly 7073pseudo ops to ensure that appropriate exception unwind information is 7074generated. Otherwise, if one of the functions called by your assembly 7075code throws an exception, the run-time library will be unable to unwind 7076the stack through your assembly code and your program will not behave 7077correctly. 7078 7079 To illustrate the use of these pseudo ops, we will examine the code 7080that G++ generates for the following C++ input: 7081 7082void callee (int *); 7083 7084int 7085caller () 7086{ 7087 int i; 7088 callee (&i); 7089 return i; 7090} 7091 7092 This example does not show how to throw or catch an exception from 7093assembly code. That is a much more complex operation and should always 7094be done in a high-level language, such as C++, that directly supports 7095exceptions. 7096 7097 The code generated by one particular version of G++ when compiling 7098the example above is: 7099 7100_Z6callerv: 7101 .fnstart 7102.LFB2: 7103 @ Function supports interworking. 7104 @ args = 0, pretend = 0, frame = 8 7105 @ frame_needed = 1, uses_anonymous_args = 0 7106 stmfd sp!, {fp, lr} 7107 .save {fp, lr} 7108.LCFI0: 7109 .setfp fp, sp, #4 7110 add fp, sp, #4 7111.LCFI1: 7112 .pad #8 7113 sub sp, sp, #8 7114.LCFI2: 7115 sub r3, fp, #8 7116 mov r0, r3 7117 bl _Z6calleePi 7118 ldr r3, [fp, #-8] 7119 mov r0, r3 7120 sub sp, fp, #4 7121 ldmfd sp!, {fp, lr} 7122 bx lr 7123.LFE2: 7124 .fnend 7125 7126 Of course, the sequence of instructions varies based on the options 7127you pass to GCC and on the version of GCC in use. The exact 7128instructions are not important since we are focusing on the pseudo ops 7129that are used to generate unwind information. 7130 7131 An important assumption made by the unwinder is that the stack frame 7132does not change during the body of the function. In particular, since 7133we assume that the assembly code does not itself throw an exception, 7134the only point where an exception can be thrown is from a call, such as 7135the `bl' instruction above. At each call site, the same saved 7136registers (including `lr', which indicates the return address) must be 7137located in the same locations relative to the frame pointer. 7138 7139 The `.fnstart' (*note .fnstart pseudo op: arm_fnstart.) pseudo op 7140appears immediately before the first instruction of the function while 7141the `.fnend' (*note .fnend pseudo op: arm_fnend.) pseudo op appears 7142immediately after the last instruction of the function. These pseudo 7143ops specify the range of the function. 7144 7145 Only the order of the other pseudos ops (e.g., `.setfp' or `.pad') 7146matters; their exact locations are irrelevant. In the example above, 7147the compiler emits the pseudo ops with particular instructions. That 7148makes it easier to understand the code, but it is not required for 7149correctness. It would work just as well to emit all of the pseudo ops 7150other than `.fnend' in the same order, but immediately after `.fnstart'. 7151 7152 The `.save' (*note .save pseudo op: arm_save.) pseudo op indicates 7153registers that have been saved to the stack so that they can be 7154restored before the function returns. The argument to the `.save' 7155pseudo op is a list of registers to save. If a register is 7156"callee-saved" (as specified by the ABI) and is modified by the 7157function you are writing, then your code must save the value before it 7158is modified and restore the original value before the function returns. 7159If an exception is thrown, the run-time library restores the values of 7160these registers from their locations on the stack before returning 7161control to the exception handler. (Of course, if an exception is not 7162thrown, the function that contains the `.save' pseudo op restores these 7163registers in the function epilogue, as is done with the `ldmfd' 7164instruction above.) 7165 7166 You do not have to save callee-saved registers at the very beginning 7167of the function and you do not need to use the `.save' pseudo op 7168immediately following the point at which the registers are saved. 7169However, if you modify a callee-saved register, you must save it on the 7170stack before modifying it and before calling any functions which might 7171throw an exception. And, you must use the `.save' pseudo op to 7172indicate that you have done so. 7173 7174 The `.pad' (*note .pad: arm_pad.) pseudo op indicates a modification 7175of the stack pointer that does not save any registers. The argument is 7176the number of bytes (in decimal) that are subtracted from the stack 7177pointer. (On ARM CPUs, the stack grows downwards, so subtracting from 7178the stack pointer increases the size of the stack.) 7179 7180 The `.setfp' (*note .setfp pseudo op: arm_setfp.) pseudo op 7181indicates the register that contains the frame pointer. The first 7182argument is the register that is set, which is typically `fp'. The 7183second argument indicates the register from which the frame pointer 7184takes its value. The third argument, if present, is the value (in 7185decimal) added to the register specified by the second argument to 7186compute the value of the frame pointer. You should not modify the 7187frame pointer in the body of the function. 7188 7189 If you do not use a frame pointer, then you should not use the 7190`.setfp' pseudo op. If you do not use a frame pointer, then you should 7191avoid modifying the stack pointer outside of the function prologue. 7192Otherwise, the run-time library will be unable to find saved registers 7193when it is unwinding the stack. 7194 7195 The pseudo ops described above are sufficient for writing assembly 7196code that calls functions which may throw exceptions. If you need to 7197know more about the object-file format used to represent unwind 7198information, you may consult the `Exception Handling ABI for the ARM 7199Architecture' available from `http://infocenter.arm.com'. 7200 7201 7202File: as.info, Node: AVR-Dependent, Next: Blackfin-Dependent, Prev: ARM-Dependent, Up: Machine Dependencies 7203 72049.4 AVR Dependent Features 7205========================== 7206 7207* Menu: 7208 7209* AVR Options:: Options 7210* AVR Syntax:: Syntax 7211* AVR Opcodes:: Opcodes 7212 7213 7214File: as.info, Node: AVR Options, Next: AVR Syntax, Up: AVR-Dependent 7215 72169.4.1 Options 7217------------- 7218 7219`-mmcu=MCU' 7220 Specify ATMEL AVR instruction set or MCU type. 7221 7222 Instruction set avr1 is for the minimal AVR core, not supported by 7223 the C compiler, only for assembler programs (MCU types: at90s1200, 7224 attiny11, attiny12, attiny15, attiny28). 7225 7226 Instruction set avr2 (default) is for the classic AVR core with up 7227 to 8K program memory space (MCU types: at90s2313, at90s2323, 7228 at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433, 7229 at90s4434, at90s8515, at90c8534, at90s8535). 7230 7231 Instruction set avr25 is for the classic AVR core with up to 8K 7232 program memory space plus the MOVW instruction (MCU types: 7233 attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, 7234 attiny4313, attiny44, attiny44a, attiny84, attiny84a, attiny25, 7235 attiny45, attiny85, attiny261, attiny261a, attiny461, attiny461a, 7236 attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, 7237 at86rf401, ata6289). 7238 7239 Instruction set avr3 is for the classic AVR core with up to 128K 7240 program memory space (MCU types: at43usb355, at76c711). 7241 7242 Instruction set avr31 is for the classic AVR core with exactly 7243 128K program memory space (MCU types: atmega103, at43usb320). 7244 7245 Instruction set avr35 is for classic AVR core plus MOVW, CALL, and 7246 JMP instructions (MCU types: attiny167, at90usb82, at90usb162, 7247 atmega8u2, atmega16u2, atmega32u2). 7248 7249 Instruction set avr4 is for the enhanced AVR core with up to 8K 7250 program memory space (MCU types: atmega48, atmega48a, atmega48p, 7251 atmega8, atmega88, atmega88a, atmega88p, atmega88pa, atmega8515, 7252 atmega8535, atmega8hva, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, 7253 at90pwm3b, at90pwm81). 7254 7255 Instruction set avr5 is for the enhanced AVR core with up to 128K 7256 program memory space (MCU types: atmega16, atmega16a, atmega161, 7257 atmega162, atmega163, atmega164a, atmega164p, atmega165, 7258 atmega165a, atmega165p, atmega168, atmega168a, atmega168p, 7259 atmega169, atmega169a, atmega169p, atmega169pa, atmega32, 7260 atmega323, atmega324a, atmega324p, atmega325, atmega325a, 7261 atmega325p, atmega325pa, atmega3250, atmega3250a, atmega3250p, 7262 atmega3250pa, atmega328, atmega328p, atmega329, atmega329a, 7263 atmega329p, atmega329pa, atmega3290, atmega3290a, atmega3290p, 7264 atmega3290pa, atmega406, atmega64, atmega640, atmega644, 7265 atmega644a, atmega644p, atmega644pa, atmega645, atmega645a, 7266 atmega645p, atmega6450, atmega6450a, atmega6450p, atmega649, 7267 atmega649a, atmega649p, atmega6490, atmega6490a, atmega6490p, 7268 atmega16hva, atmega16hva2, atmega16hvb, atmega16hvbrevb, 7269 atmega32hvb, atmega32hvbrevb, atmega64hve, at90can32, at90can64, 7270 at90pwm161, at90pwm216, at90pwm316, atmega32c1, atmega64c1, 7271 atmega16m1, atmega32m1, atmega64m1, atmega16u4, atmega32u4, 7272 atmega32u6, at90usb646, at90usb647, at94k, at90scr100). 7273 7274 Instruction set avr51 is for the enhanced AVR core with exactly 7275 128K program memory space (MCU types: atmega128, atmega1280, 7276 atmega1281, atmega1284p, atmega128rfa1, at90can128, at90usb1286, 7277 at90usb1287, m3000). 7278 7279 Instruction set avr6 is for the enhanced AVR core with a 3-byte PC 7280 (MCU types: atmega2560, atmega2561). 7281 7282 Instruction set avrxmega2 is for the XMEGA AVR core with 8K to 64K 7283 program memory space and less than 64K data space (MCU types: 7284 atxmega16a4, atxmega16d4, atxmega16x1, atxmega32a4, atxmega32d4, 7285 atxmega32x1). 7286 7287 Instruction set avrxmega3 is for the XMEGA AVR core with 8K to 64K 7288 program memory space and greater than 64K data space (MCU types: 7289 none). 7290 7291 Instruction set avrxmega4 is for the XMEGA AVR core with up to 64K 7292 program memory space and less than 64K data space (MCU types: 7293 atxmega64a3, atxmega64d3). 7294 7295 Instruction set avrxmega5 is for the XMEGA AVR core with up to 64K 7296 program memory space and greater than 64K data space (MCU types: 7297 atxmega64a1, atxmega64a1u). 7298 7299 Instruction set avrxmega6 is for the XMEGA AVR core with up to 7300 256K program memory space and less than 64K data space (MCU types: 7301 atxmega128a3, atxmega128d3, atxmega192a3, atxmega128b1, 7302 atxmega192d3, atxmega256a3, atxmega256a3b, atxmega256a3bu, 7303 atxmega192d3). 7304 7305 Instruction set avrxmega7 is for the XMEGA AVR core with up to 7306 256K program memory space and greater than 64K data space (MCU 7307 types: atxmega128a1, atxmega128a1u). 7308 7309`-mall-opcodes' 7310 Accept all AVR opcodes, even if not supported by `-mmcu'. 7311 7312`-mno-skip-bug' 7313 This option disable warnings for skipping two-word instructions. 7314 7315`-mno-wrap' 7316 This option reject `rjmp/rcall' instructions with 8K wrap-around. 7317 7318 7319 7320File: as.info, Node: AVR Syntax, Next: AVR Opcodes, Prev: AVR Options, Up: AVR-Dependent 7321 73229.4.2 Syntax 7323------------ 7324 7325* Menu: 7326 7327* AVR-Chars:: Special Characters 7328* AVR-Regs:: Register Names 7329* AVR-Modifiers:: Relocatable Expression Modifiers 7330 7331 7332File: as.info, Node: AVR-Chars, Next: AVR-Regs, Up: AVR Syntax 7333 73349.4.2.1 Special Characters 7335.......................... 7336 7337The presence of a `;' anywhere on a line indicates the start of a 7338comment that extends to the end of that line. 7339 7340 If a `#' appears as the first character of a line, the whole line is 7341treated as a comment, but in this case the line can also be a logical 7342line number directive (*note Comments::) or a preprocessor control 7343command (*note Preprocessing::). 7344 7345 The `$' character can be used instead of a newline to separate 7346statements. 7347 7348 7349File: as.info, Node: AVR-Regs, Next: AVR-Modifiers, Prev: AVR-Chars, Up: AVR Syntax 7350 73519.4.2.2 Register Names 7352...................... 7353 7354The AVR has 32 x 8-bit general purpose working registers `r0', `r1', 7355... `r31'. Six of the 32 registers can be used as three 16-bit 7356indirect address register pointers for Data Space addressing. One of 7357the these address pointers can also be used as an address pointer for 7358look up tables in Flash program memory. These added function registers 7359are the 16-bit `X', `Y' and `Z' - registers. 7360 7361 X = r26:r27 7362 Y = r28:r29 7363 Z = r30:r31 7364 7365 7366File: as.info, Node: AVR-Modifiers, Prev: AVR-Regs, Up: AVR Syntax 7367 73689.4.2.3 Relocatable Expression Modifiers 7369........................................ 7370 7371The assembler supports several modifiers when using relocatable 7372addresses in AVR instruction operands. The general syntax is the 7373following: 7374 7375 modifier(relocatable-expression) 7376 7377`lo8' 7378 This modifier allows you to use bits 0 through 7 of an address 7379 expression as 8 bit relocatable expression. 7380 7381`hi8' 7382 This modifier allows you to use bits 7 through 15 of an address 7383 expression as 8 bit relocatable expression. This is useful with, 7384 for example, the AVR `ldi' instruction and `lo8' modifier. 7385 7386 For example 7387 7388 ldi r26, lo8(sym+10) 7389 ldi r27, hi8(sym+10) 7390 7391`hh8' 7392 This modifier allows you to use bits 16 through 23 of an address 7393 expression as 8 bit relocatable expression. Also, can be useful 7394 for loading 32 bit constants. 7395 7396`hlo8' 7397 Synonym of `hh8'. 7398 7399`hhi8' 7400 This modifier allows you to use bits 24 through 31 of an 7401 expression as 8 bit expression. This is useful with, for example, 7402 the AVR `ldi' instruction and `lo8', `hi8', `hlo8', `hhi8', 7403 modifier. 7404 7405 For example 7406 7407 ldi r26, lo8(285774925) 7408 ldi r27, hi8(285774925) 7409 ldi r28, hlo8(285774925) 7410 ldi r29, hhi8(285774925) 7411 ; r29,r28,r27,r26 = 285774925 7412 7413`pm_lo8' 7414 This modifier allows you to use bits 0 through 7 of an address 7415 expression as 8 bit relocatable expression. This modifier useful 7416 for addressing data or code from Flash/Program memory. The using 7417 of `pm_lo8' similar to `lo8'. 7418 7419`pm_hi8' 7420 This modifier allows you to use bits 8 through 15 of an address 7421 expression as 8 bit relocatable expression. This modifier useful 7422 for addressing data or code from Flash/Program memory. 7423 7424`pm_hh8' 7425 This modifier allows you to use bits 15 through 23 of an address 7426 expression as 8 bit relocatable expression. This modifier useful 7427 for addressing data or code from Flash/Program memory. 7428 7429 7430 7431File: as.info, Node: AVR Opcodes, Prev: AVR Syntax, Up: AVR-Dependent 7432 74339.4.3 Opcodes 7434------------- 7435 7436For detailed information on the AVR machine instruction set, see 7437`www.atmel.com/products/AVR'. 7438 7439 `as' implements all the standard AVR opcodes. The following table 7440summarizes the AVR opcodes, and their arguments. 7441 7442 Legend: 7443 r any register 7444 d `ldi' register (r16-r31) 7445 v `movw' even register (r0, r2, ..., r28, r30) 7446 a `fmul' register (r16-r23) 7447 w `adiw' register (r24,r26,r28,r30) 7448 e pointer registers (X,Y,Z) 7449 b base pointer register and displacement ([YZ]+disp) 7450 z Z pointer register (for [e]lpm Rd,Z[+]) 7451 M immediate value from 0 to 255 7452 n immediate value from 0 to 255 ( n = ~M ). Relocation impossible 7453 s immediate value from 0 to 7 7454 P Port address value from 0 to 63. (in, out) 7455 p Port address value from 0 to 31. (cbi, sbi, sbic, sbis) 7456 K immediate value from 0 to 63 (used in `adiw', `sbiw') 7457 i immediate value 7458 l signed pc relative offset from -64 to 63 7459 L signed pc relative offset from -2048 to 2047 7460 h absolute code address (call, jmp) 7461 S immediate value from 0 to 7 (S = s << 4) 7462 ? use this opcode entry if no parameters, else use next opcode entry 7463 7464 1001010010001000 clc 7465 1001010011011000 clh 7466 1001010011111000 cli 7467 1001010010101000 cln 7468 1001010011001000 cls 7469 1001010011101000 clt 7470 1001010010111000 clv 7471 1001010010011000 clz 7472 1001010000001000 sec 7473 1001010001011000 seh 7474 1001010001111000 sei 7475 1001010000101000 sen 7476 1001010001001000 ses 7477 1001010001101000 set 7478 1001010000111000 sev 7479 1001010000011000 sez 7480 100101001SSS1000 bclr S 7481 100101000SSS1000 bset S 7482 1001010100001001 icall 7483 1001010000001001 ijmp 7484 1001010111001000 lpm ? 7485 1001000ddddd010+ lpm r,z 7486 1001010111011000 elpm ? 7487 1001000ddddd011+ elpm r,z 7488 0000000000000000 nop 7489 1001010100001000 ret 7490 1001010100011000 reti 7491 1001010110001000 sleep 7492 1001010110011000 break 7493 1001010110101000 wdr 7494 1001010111101000 spm 7495 000111rdddddrrrr adc r,r 7496 000011rdddddrrrr add r,r 7497 001000rdddddrrrr and r,r 7498 000101rdddddrrrr cp r,r 7499 000001rdddddrrrr cpc r,r 7500 000100rdddddrrrr cpse r,r 7501 001001rdddddrrrr eor r,r 7502 001011rdddddrrrr mov r,r 7503 100111rdddddrrrr mul r,r 7504 001010rdddddrrrr or r,r 7505 000010rdddddrrrr sbc r,r 7506 000110rdddddrrrr sub r,r 7507 001001rdddddrrrr clr r 7508 000011rdddddrrrr lsl r 7509 000111rdddddrrrr rol r 7510 001000rdddddrrrr tst r 7511 0111KKKKddddKKKK andi d,M 7512 0111KKKKddddKKKK cbr d,n 7513 1110KKKKddddKKKK ldi d,M 7514 11101111dddd1111 ser d 7515 0110KKKKddddKKKK ori d,M 7516 0110KKKKddddKKKK sbr d,M 7517 0011KKKKddddKKKK cpi d,M 7518 0100KKKKddddKKKK sbci d,M 7519 0101KKKKddddKKKK subi d,M 7520 1111110rrrrr0sss sbrc r,s 7521 1111111rrrrr0sss sbrs r,s 7522 1111100ddddd0sss bld r,s 7523 1111101ddddd0sss bst r,s 7524 10110PPdddddPPPP in r,P 7525 10111PPrrrrrPPPP out P,r 7526 10010110KKddKKKK adiw w,K 7527 10010111KKddKKKK sbiw w,K 7528 10011000pppppsss cbi p,s 7529 10011010pppppsss sbi p,s 7530 10011001pppppsss sbic p,s 7531 10011011pppppsss sbis p,s 7532 111101lllllll000 brcc l 7533 111100lllllll000 brcs l 7534 111100lllllll001 breq l 7535 111101lllllll100 brge l 7536 111101lllllll101 brhc l 7537 111100lllllll101 brhs l 7538 111101lllllll111 brid l 7539 111100lllllll111 brie l 7540 111100lllllll000 brlo l 7541 111100lllllll100 brlt l 7542 111100lllllll010 brmi l 7543 111101lllllll001 brne l 7544 111101lllllll010 brpl l 7545 111101lllllll000 brsh l 7546 111101lllllll110 brtc l 7547 111100lllllll110 brts l 7548 111101lllllll011 brvc l 7549 111100lllllll011 brvs l 7550 111101lllllllsss brbc s,l 7551 111100lllllllsss brbs s,l 7552 1101LLLLLLLLLLLL rcall L 7553 1100LLLLLLLLLLLL rjmp L 7554 1001010hhhhh111h call h 7555 1001010hhhhh110h jmp h 7556 1001010rrrrr0101 asr r 7557 1001010rrrrr0000 com r 7558 1001010rrrrr1010 dec r 7559 1001010rrrrr0011 inc r 7560 1001010rrrrr0110 lsr r 7561 1001010rrrrr0001 neg r 7562 1001000rrrrr1111 pop r 7563 1001001rrrrr1111 push r 7564 1001010rrrrr0111 ror r 7565 1001010rrrrr0010 swap r 7566 00000001ddddrrrr movw v,v 7567 00000010ddddrrrr muls d,d 7568 000000110ddd0rrr mulsu a,a 7569 000000110ddd1rrr fmul a,a 7570 000000111ddd0rrr fmuls a,a 7571 000000111ddd1rrr fmulsu a,a 7572 1001001ddddd0000 sts i,r 7573 1001000ddddd0000 lds r,i 7574 10o0oo0dddddbooo ldd r,b 7575 100!000dddddee-+ ld r,e 7576 10o0oo1rrrrrbooo std b,r 7577 100!001rrrrree-+ st e,r 7578 1001010100011001 eicall 7579 1001010000011001 eijmp 7580 7581 7582File: as.info, Node: Blackfin-Dependent, Next: CR16-Dependent, Prev: AVR-Dependent, Up: Machine Dependencies 7583 75849.5 Blackfin Dependent Features 7585=============================== 7586 7587* Menu: 7588 7589* Blackfin Options:: Blackfin Options 7590* Blackfin Syntax:: Blackfin Syntax 7591* Blackfin Directives:: Blackfin Directives 7592 7593 7594File: as.info, Node: Blackfin Options, Next: Blackfin Syntax, Up: Blackfin-Dependent 7595 75969.5.1 Options 7597------------- 7598 7599`-mcpu=PROCESSOR[-SIREVISION]' 7600 This option specifies the target processor. The optional 7601 SIREVISION is not used in assembler. It's here such that GCC can 7602 easily pass down its `-mcpu=' option. The assembler will issue an 7603 error message if an attempt is made to assemble an instruction 7604 which will not execute on the target processor. The following 7605 processor names are recognized: `bf504', `bf506', `bf512', `bf514', 7606 `bf516', `bf518', `bf522', `bf523', `bf524', `bf525', `bf526', 7607 `bf527', `bf531', `bf532', `bf533', `bf534', `bf535' (not 7608 implemented yet), `bf536', `bf537', `bf538', `bf539', `bf542', 7609 `bf542m', `bf544', `bf544m', `bf547', `bf547m', `bf548', `bf548m', 7610 `bf549', `bf549m', `bf561', and `bf592'. 7611 7612`-mfdpic' 7613 Assemble for the FDPIC ABI. 7614 7615`-mno-fdpic' 7616`-mnopic' 7617 Disable -mfdpic. 7618 7619 7620File: as.info, Node: Blackfin Syntax, Next: Blackfin Directives, Prev: Blackfin Options, Up: Blackfin-Dependent 7621 76229.5.2 Syntax 7623------------ 7624 7625`Special Characters' 7626 Assembler input is free format and may appear anywhere on the line. 7627 One instruction may extend across multiple lines or more than one 7628 instruction may appear on the same line. White space (space, tab, 7629 comments or newline) may appear anywhere between tokens. A token 7630 must not have embedded spaces. Tokens include numbers, register 7631 names, keywords, user identifiers, and also some multicharacter 7632 special symbols like "+=", "/*" or "||". 7633 7634 Comments are introduced by the `#' character and extend to the end 7635 of the current line. If the `#' appears as the first character of 7636 a line, the whole line is treated as a comment, but in this case 7637 the line can also be a logical line number directive (*note 7638 Comments::) or a preprocessor control command (*note 7639 Preprocessing::). 7640 7641`Instruction Delimiting' 7642 A semicolon must terminate every instruction. Sometimes a complete 7643 instruction will consist of more than one operation. There are two 7644 cases where this occurs. The first is when two general operations 7645 are combined. Normally a comma separates the different parts, as 7646 in 7647 7648 a0= r3.h * r2.l, a1 = r3.l * r2.h ; 7649 7650 The second case occurs when a general instruction is combined with 7651 one or two memory references for joint issue. The latter portions 7652 are set off by a "||" token. 7653 7654 a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++]; 7655 7656 Multiple instructions can occur on the same line. Each must be 7657 terminated by a semicolon character. 7658 7659`Register Names' 7660 The assembler treats register names and instruction keywords in a 7661 case insensitive manner. User identifiers are case sensitive. 7662 Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the 7663 assembler. 7664 7665 Register names are reserved and may not be used as program 7666 identifiers. 7667 7668 Some operations (such as "Move Register") require a register pair. 7669 Register pairs are always data registers and are denoted using a 7670 colon, eg., R3:2. The larger number must be written firsts. Note 7671 that the hardware only supports odd-even pairs, eg., R7:6, R5:4, 7672 R3:2, and R1:0. 7673 7674 Some instructions (such as -SP (Push Multiple)) require a group of 7675 adjacent registers. Adjacent registers are denoted in the syntax 7676 by the range enclosed in parentheses and separated by a colon, 7677 eg., (R7:3). Again, the larger number appears first. 7678 7679 Portions of a particular register may be individually specified. 7680 This is written with a dot (".") following the register name and 7681 then a letter denoting the desired portion. For 32-bit registers, 7682 ".H" denotes the most significant ("High") portion. ".L" denotes 7683 the least-significant portion. The subdivisions of the 40-bit 7684 registers are described later. 7685 7686`Accumulators' 7687 The set of 40-bit registers A1 and A0 that normally contain data 7688 that is being manipulated. Each accumulator can be accessed in 7689 four ways. 7690 7691 `one 40-bit register' 7692 The register will be referred to as A1 or A0. 7693 7694 `one 32-bit register' 7695 The registers are designated as A1.W or A0.W. 7696 7697 `two 16-bit registers' 7698 The registers are designated as A1.H, A1.L, A0.H or A0.L. 7699 7700 `one 8-bit register' 7701 The registers are designated as A1.X or A0.X for the bits that 7702 extend beyond bit 31. 7703 7704`Data Registers' 7705 The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) 7706 that normally contain data for manipulation. These are 7707 abbreviated as D-register or Dreg. Data registers can be accessed 7708 as 32-bit registers or as two independent 16-bit registers. The 7709 least significant 16 bits of each register is called the "low" 7710 half and is designated with ".L" following the register name. The 7711 most significant 16 bits are called the "high" half and is 7712 designated with ".H" following the name. 7713 7714 R7.L, r2.h, r4.L, R0.H 7715 7716`Pointer Registers' 7717 The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) 7718 that normally contain byte addresses of data structures. These are 7719 abbreviated as P-register or Preg. 7720 7721 p2, p5, fp, sp 7722 7723`Stack Pointer SP' 7724 The stack pointer contains the 32-bit address of the last occupied 7725 byte location in the stack. The stack grows by decrementing the 7726 stack pointer. 7727 7728`Frame Pointer FP' 7729 The frame pointer contains the 32-bit address of the previous frame 7730 pointer in the stack. It is located at the top of a frame. 7731 7732`Loop Top' 7733 LT0 and LT1. These registers contain the 32-bit address of the 7734 top of a zero overhead loop. 7735 7736`Loop Count' 7737 LC0 and LC1. These registers contain the 32-bit counter of the 7738 zero overhead loop executions. 7739 7740`Loop Bottom' 7741 LB0 and LB1. These registers contain the 32-bit address of the 7742 bottom of a zero overhead loop. 7743 7744`Index Registers' 7745 The set of 32-bit registers (I0, I1, I2, I3) that normally contain 7746 byte addresses of data structures. Abbreviated I-register or Ireg. 7747 7748`Modify Registers' 7749 The set of 32-bit registers (M0, M1, M2, M3) that normally contain 7750 offset values that are added and subtracted to one of the index 7751 registers. Abbreviated as Mreg. 7752 7753`Length Registers' 7754 The set of 32-bit registers (L0, L1, L2, L3) that normally contain 7755 the length in bytes of the circular buffer. Abbreviated as Lreg. 7756 Clear the Lreg to disable circular addressing for the 7757 corresponding Ireg. 7758 7759`Base Registers' 7760 The set of 32-bit registers (B0, B1, B2, B3) that normally contain 7761 the base address in bytes of the circular buffer. Abbreviated as 7762 Breg. 7763 7764`Floating Point' 7765 The Blackfin family has no hardware floating point but the .float 7766 directive generates ieee floating point numbers for use with 7767 software floating point libraries. 7768 7769`Blackfin Opcodes' 7770 For detailed information on the Blackfin machine instruction set, 7771 see the Blackfin(r) Processor Instruction Set Reference. 7772 7773 7774 7775File: as.info, Node: Blackfin Directives, Prev: Blackfin Syntax, Up: Blackfin-Dependent 7776 77779.5.3 Directives 7778---------------- 7779 7780The following directives are provided for compatibility with the VDSP 7781assembler. 7782 7783`.byte2' 7784 Initializes a two byte data object. 7785 7786 This maps to the `.short' directive. 7787 7788`.byte4' 7789 Initializes a four byte data object. 7790 7791 This maps to the `.int' directive. 7792 7793`.db' 7794 Initializes a single byte data object. 7795 7796 This directive is a synonym for `.byte'. 7797 7798`.dw' 7799 Initializes a two byte data object. 7800 7801 This directive is a synonym for `.byte2'. 7802 7803`.dd' 7804 Initializes a four byte data object. 7805 7806 This directive is a synonym for `.byte4'. 7807 7808`.var' 7809 Define and initialize a 32 bit data object. 7810 7811 7812File: as.info, Node: CR16-Dependent, Next: CRIS-Dependent, Prev: Blackfin-Dependent, Up: Machine Dependencies 7813 78149.6 CR16 Dependent Features 7815=========================== 7816 7817* Menu: 7818 7819* CR16 Operand Qualifiers:: CR16 Machine Operand Qualifiers 7820* CR16 Syntax:: Syntax for the CR16 7821 7822 7823File: as.info, Node: CR16 Operand Qualifiers, Next: CR16 Syntax, Up: CR16-Dependent 7824 78259.6.1 CR16 Operand Qualifiers 7826----------------------------- 7827 7828The National Semiconductor CR16 target of `as' has a few machine 7829dependent operand qualifiers. 7830 7831 Operand expression type qualifier is an optional field in the 7832instruction operand, to determines the type of the expression field of 7833an operand. The `@' is required. CR16 architecture uses one of the 7834following expression qualifiers: 7835 7836`s' 7837 - `Specifies expression operand type as small' 7838 7839`m' 7840 - `Specifies expression operand type as medium' 7841 7842`l' 7843 - `Specifies expression operand type as large' 7844 7845`c' 7846 - `Specifies the CR16 Assembler generates a relocation entry for 7847 the operand, where pc has implied bit, the expression is adjusted 7848 accordingly. The linker uses the relocation entry to update the 7849 operand address at link time.' 7850 7851`got/GOT' 7852 - `Specifies the CR16 Assembler generates a relocation entry for 7853 the operand, offset from Global Offset Table. The linker uses this 7854 relocation entry to update the operand address at link time' 7855 7856`cgot/cGOT' 7857 - `Specifies the CompactRISC Assembler generates a relocation 7858 entry for the operand, where pc has implied bit, the expression is 7859 adjusted accordingly. The linker uses the relocation entry to 7860 update the operand address at link time.' 7861 7862 CR16 target operand qualifiers and its size (in bits): 7863 7864`Immediate Operand' 7865 - s --- 4 bits 7866 7867`' 7868 - m --- 16 bits, for movb and movw instructions. 7869 7870`' 7871 - m --- 20 bits, movd instructions. 7872 7873`' 7874 - l --- 32 bits 7875 7876`Absolute Operand' 7877 - s --- Illegal specifier for this operand. 7878 7879`' 7880 - m --- 20 bits, movd instructions. 7881 7882`Displacement Operand' 7883 - s --- 8 bits 7884 7885`' 7886 - m --- 16 bits 7887 7888`' 7889 - l --- 24 bits 7890 7891 For example: 7892 1 `movw $_myfun@c,r1' 7893 7894 This loads the address of _myfun, shifted right by 1, into r1. 7895 7896 2 `movd $_myfun@c,(r2,r1)' 7897 7898 This loads the address of _myfun, shifted right by 1, into register-pair r2-r1. 7899 7900 3 `_myfun_ptr:' 7901 `.long _myfun@c' 7902 `loadd _myfun_ptr, (r1,r0)' 7903 `jal (r1,r0)' 7904 7905 This .long directive, the address of _myfunc, shifted right by 1 at link time. 7906 7907 4 `loadd _data1@GOT(r12), (r1,r0)' 7908 7909 This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1. 7910 7911 5 `loadd _myfunc@cGOT(r12), (r1,r0)' 7912 7913 This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0. 7914 7915 7916File: as.info, Node: CR16 Syntax, Prev: CR16 Operand Qualifiers, Up: CR16-Dependent 7917 79189.6.2 CR16 Syntax 7919----------------- 7920 7921* Menu: 7922 7923* CR16-Chars:: Special Characters 7924 7925 7926File: as.info, Node: CR16-Chars, Up: CR16 Syntax 7927 79289.6.2.1 Special Characters 7929.......................... 7930 7931The presence of a `#' on a line indicates the start of a comment that 7932extends to the end of the current line. If the `#' appears as the 7933first character of a line, the whole line is treated as a comment, but 7934in this case the line can also be a logical line number directive 7935(*note Comments::) or a preprocessor control command (*note 7936Preprocessing::). 7937 7938 The `;' character can be used to separate statements on the same 7939line. 7940 7941 7942File: as.info, Node: CRIS-Dependent, Next: D10V-Dependent, Prev: CR16-Dependent, Up: Machine Dependencies 7943 79449.7 CRIS Dependent Features 7945=========================== 7946 7947* Menu: 7948 7949* CRIS-Opts:: Command-line Options 7950* CRIS-Expand:: Instruction expansion 7951* CRIS-Symbols:: Symbols 7952* CRIS-Syntax:: Syntax 7953 7954 7955File: as.info, Node: CRIS-Opts, Next: CRIS-Expand, Up: CRIS-Dependent 7956 79579.7.1 Command-line Options 7958-------------------------- 7959 7960The CRIS version of `as' has these machine-dependent command-line 7961options. 7962 7963 The format of the generated object files can be either ELF or a.out, 7964specified by the command-line options `--emulation=crisaout' and 7965`--emulation=criself'. The default is ELF (criself), unless `as' has 7966been configured specifically for a.out by using the configuration name 7967`cris-axis-aout'. 7968 7969 There are two different link-incompatible ELF object file variants 7970for CRIS, for use in environments where symbols are expected to be 7971prefixed by a leading `_' character and for environments without such a 7972symbol prefix. The variant used for GNU/Linux port has no symbol 7973prefix. Which variant to produce is specified by either of the options 7974`--underscore' and `--no-underscore'. The default is `--underscore'. 7975Since symbols in CRIS a.out objects are expected to have a `_' prefix, 7976specifying `--no-underscore' when generating a.out objects is an error. 7977Besides the object format difference, the effect of this option is to 7978parse register names differently (*note crisnous::). The 7979`--no-underscore' option makes a `$' register prefix mandatory. 7980 7981 The option `--pic' must be passed to `as' in order to recognize the 7982symbol syntax used for ELF (SVR4 PIC) position-independent-code (*note 7983crispic::). This will also affect expansion of instructions. The 7984expansion with `--pic' will use PC-relative rather than (slightly 7985faster) absolute addresses in those expansions. This option is only 7986valid when generating ELF format object files. 7987 7988 The option `--march=ARCHITECTURE' specifies the recognized 7989instruction set and recognized register names. It also controls the 7990architecture type of the object file. Valid values for ARCHITECTURE 7991are: 7992`v0_v10' 7993 All instructions and register names for any architecture variant 7994 in the set v0...v10 are recognized. This is the default if the 7995 target is configured as cris-*. 7996 7997`v10' 7998 Only instructions and register names for CRIS v10 (as found in 7999 ETRAX 100 LX) are recognized. This is the default if the target 8000 is configured as crisv10-*. 8001 8002`v32' 8003 Only instructions and register names for CRIS v32 (code name 8004 Guinness) are recognized. This is the default if the target is 8005 configured as crisv32-*. This value implies `--no-mul-bug-abort'. 8006 (A subsequent `--mul-bug-abort' will turn it back on.) 8007 8008`common_v10_v32' 8009 Only instructions with register names and addressing modes with 8010 opcodes common to the v10 and v32 are recognized. 8011 8012 When `-N' is specified, `as' will emit a warning when a 16-bit 8013branch instruction is expanded into a 32-bit multiple-instruction 8014construct (*note CRIS-Expand::). 8015 8016 Some versions of the CRIS v10, for example in the Etrax 100 LX, 8017contain a bug that causes destabilizing memory accesses when a multiply 8018instruction is executed with certain values in the first operand just 8019before a cache-miss. When the `--mul-bug-abort' command line option is 8020active (the default value), `as' will refuse to assemble a file 8021containing a multiply instruction at a dangerous offset, one that could 8022be the last on a cache-line, or is in a section with insufficient 8023alignment. This placement checking does not catch any case where the 8024multiply instruction is dangerously placed because it is located in a 8025delay-slot. The `--mul-bug-abort' command line option turns off the 8026checking. 8027 8028 8029File: as.info, Node: CRIS-Expand, Next: CRIS-Symbols, Prev: CRIS-Opts, Up: CRIS-Dependent 8030 80319.7.2 Instruction expansion 8032--------------------------- 8033 8034`as' will silently choose an instruction that fits the operand size for 8035`[register+constant]' operands. For example, the offset `127' in 8036`move.d [r3+127],r4' fits in an instruction using a signed-byte offset. 8037Similarly, `move.d [r2+32767],r1' will generate an instruction using a 803816-bit offset. For symbolic expressions and constants that do not fit 8039in 16 bits including the sign bit, a 32-bit offset is generated. 8040 8041 For branches, `as' will expand from a 16-bit branch instruction into 8042a sequence of instructions that can reach a full 32-bit address. Since 8043this does not correspond to a single instruction, such expansions can 8044optionally be warned about. *Note CRIS-Opts::. 8045 8046 If the operand is found to fit the range, a `lapc' mnemonic will 8047translate to a `lapcq' instruction. Use `lapc.d' to force the 32-bit 8048`lapc' instruction. 8049 8050 Similarly, the `addo' mnemonic will translate to the shortest 8051fitting instruction of `addoq', `addo.w' and `addo.d', when used with a 8052operand that is a constant known at assembly time. 8053 8054 8055File: as.info, Node: CRIS-Symbols, Next: CRIS-Syntax, Prev: CRIS-Expand, Up: CRIS-Dependent 8056 80579.7.3 Symbols 8058------------- 8059 8060Some symbols are defined by the assembler. They're intended to be used 8061in conditional assembly, for example: 8062 .if ..asm.arch.cris.v32 8063 CODE FOR CRIS V32 8064 .elseif ..asm.arch.cris.common_v10_v32 8065 CODE COMMON TO CRIS V32 AND CRIS V10 8066 .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10 8067 CODE FOR V10 8068 .else 8069 .error "Code needs to be added here." 8070 .endif 8071 8072 These symbols are defined in the assembler, reflecting command-line 8073options, either when specified or the default. They are always 8074defined, to 0 or 1. 8075`..asm.arch.cris.any_v0_v10' 8076 This symbol is non-zero when `--march=v0_v10' is specified or the 8077 default. 8078 8079`..asm.arch.cris.common_v10_v32' 8080 Set according to the option `--march=common_v10_v32'. 8081 8082`..asm.arch.cris.v10' 8083 Reflects the option `--march=v10'. 8084 8085`..asm.arch.cris.v32' 8086 Corresponds to `--march=v10'. 8087 8088 Speaking of symbols, when a symbol is used in code, it can have a 8089suffix modifying its value for use in position-independent code. *Note 8090CRIS-Pic::. 8091 8092 8093File: as.info, Node: CRIS-Syntax, Prev: CRIS-Symbols, Up: CRIS-Dependent 8094 80959.7.4 Syntax 8096------------ 8097 8098There are different aspects of the CRIS assembly syntax. 8099 8100* Menu: 8101 8102* CRIS-Chars:: Special Characters 8103* CRIS-Pic:: Position-Independent Code Symbols 8104* CRIS-Regs:: Register Names 8105* CRIS-Pseudos:: Assembler Directives 8106 8107 8108File: as.info, Node: CRIS-Chars, Next: CRIS-Pic, Up: CRIS-Syntax 8109 81109.7.4.1 Special Characters 8111.......................... 8112 8113The character `#' is a line comment character. It starts a comment if 8114and only if it is placed at the beginning of a line. 8115 8116 A `;' character starts a comment anywhere on the line, causing all 8117characters up to the end of the line to be ignored. 8118 8119 A `@' character is handled as a line separator equivalent to a 8120logical new-line character (except in a comment), so separate 8121instructions can be specified on a single line. 8122 8123 8124File: as.info, Node: CRIS-Pic, Next: CRIS-Regs, Prev: CRIS-Chars, Up: CRIS-Syntax 8125 81269.7.4.2 Symbols in position-independent code 8127............................................ 8128 8129When generating position-independent code (SVR4 PIC) for use in 8130cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol 8131suffixes are used to specify what kind of run-time symbol lookup will 8132be used, expressed in the object as different _relocation types_. 8133Usually, all absolute symbol values must be located in a table, the 8134_global offset table_, leaving the code position-independent; 8135independent of values of global symbols and independent of the address 8136of the code. The suffix modifies the value of the symbol, into for 8137example an index into the global offset table where the real symbol 8138value is entered, or a PC-relative value, or a value relative to the 8139start of the global offset table. All symbol suffixes start with the 8140character `:' (omitted in the list below). Every symbol use in code or 8141a read-only section must therefore have a PIC suffix to enable a useful 8142shared library to be created. Usually, these constructs must not be 8143used with an additive constant offset as is usually allowed, i.e. no 4 8144as in `symbol + 4' is allowed. This restriction is checked at 8145link-time, not at assembly-time. 8146 8147`GOT' 8148 Attaching this suffix to a symbol in an instruction causes the 8149 symbol to be entered into the global offset table. The value is a 8150 32-bit index for that symbol into the global offset table. The 8151 name of the corresponding relocation is `R_CRIS_32_GOT'. Example: 8152 `move.d [$r0+extsym:GOT],$r9' 8153 8154`GOT16' 8155 Same as for `GOT', but the value is a 16-bit index into the global 8156 offset table. The corresponding relocation is `R_CRIS_16_GOT'. 8157 Example: `move.d [$r0+asymbol:GOT16],$r10' 8158 8159`PLT' 8160 This suffix is used for function symbols. It causes a _procedure 8161 linkage table_, an array of code stubs, to be created at the time 8162 the shared object is created or linked against, together with a 8163 global offset table entry. The value is a pc-relative offset to 8164 the corresponding stub code in the procedure linkage table. This 8165 arrangement causes the run-time symbol resolver to be called to 8166 look up and set the value of the symbol the first time the 8167 function is called (at latest; depending environment variables). 8168 It is only safe to leave the symbol unresolved this way if all 8169 references are function calls. The name of the relocation is 8170 `R_CRIS_32_PLT_PCREL'. Example: `add.d fnname:PLT,$pc' 8171 8172`PLTG' 8173 Like PLT, but the value is relative to the beginning of the global 8174 offset table. The relocation is `R_CRIS_32_PLT_GOTREL'. Example: 8175 `move.d fnname:PLTG,$r3' 8176 8177`GOTPLT' 8178 Similar to `PLT', but the value of the symbol is a 32-bit index 8179 into the global offset table. This is somewhat of a mix between 8180 the effect of the `GOT' and the `PLT' suffix; the difference to 8181 `GOT' is that there will be a procedure linkage table entry 8182 created, and that the symbol is assumed to be a function entry and 8183 will be resolved by the run-time resolver as with `PLT'. The 8184 relocation is `R_CRIS_32_GOTPLT'. Example: `jsr 8185 [$r0+fnname:GOTPLT]' 8186 8187`GOTPLT16' 8188 A variant of `GOTPLT' giving a 16-bit value. Its relocation name 8189 is `R_CRIS_16_GOTPLT'. Example: `jsr [$r0+fnname:GOTPLT16]' 8190 8191`GOTOFF' 8192 This suffix must only be attached to a local symbol, but may be 8193 used in an expression adding an offset. The value is the address 8194 of the symbol relative to the start of the global offset table. 8195 The relocation name is `R_CRIS_32_GOTREL'. Example: `move.d 8196 [$r0+localsym:GOTOFF],r3' 8197 8198 8199File: as.info, Node: CRIS-Regs, Next: CRIS-Pseudos, Prev: CRIS-Pic, Up: CRIS-Syntax 8200 82019.7.4.3 Register names 8202...................... 8203 8204A `$' character may always prefix a general or special register name in 8205an instruction operand but is mandatory when the option 8206`--no-underscore' is specified or when the `.syntax register_prefix' 8207directive is in effect (*note crisnous::). Register names are 8208case-insensitive. 8209 8210 8211File: as.info, Node: CRIS-Pseudos, Prev: CRIS-Regs, Up: CRIS-Syntax 8212 82139.7.4.4 Assembler Directives 8214............................ 8215 8216There are a few CRIS-specific pseudo-directives in addition to the 8217generic ones. *Note Pseudo Ops::. Constants emitted by 8218pseudo-directives are in little-endian order for CRIS. There is no 8219support for floating-point-specific directives for CRIS. 8220 8221`.dword EXPRESSIONS' 8222 The `.dword' directive is a synonym for `.int', expecting zero or 8223 more EXPRESSIONS, separated by commas. For each expression, a 8224 32-bit little-endian constant is emitted. 8225 8226`.syntax ARGUMENT' 8227 The `.syntax' directive takes as ARGUMENT one of the following 8228 case-sensitive choices. 8229 8230 `no_register_prefix' 8231 The `.syntax no_register_prefix' directive makes a `$' 8232 character prefix on all registers optional. It overrides a 8233 previous setting, including the corresponding effect of the 8234 option `--no-underscore'. If this directive is used when 8235 ordinary symbols do not have a `_' character prefix, care 8236 must be taken to avoid ambiguities whether an operand is a 8237 register or a symbol; using symbols with names the same as 8238 general or special registers then invoke undefined behavior. 8239 8240 `register_prefix' 8241 This directive makes a `$' character prefix on all registers 8242 mandatory. It overrides a previous setting, including the 8243 corresponding effect of the option `--underscore'. 8244 8245 `leading_underscore' 8246 This is an assertion directive, emitting an error if the 8247 `--no-underscore' option is in effect. 8248 8249 `no_leading_underscore' 8250 This is the opposite of the `.syntax leading_underscore' 8251 directive and emits an error if the option `--underscore' is 8252 in effect. 8253 8254`.arch ARGUMENT' 8255 This is an assertion directive, giving an error if the specified 8256 ARGUMENT is not the same as the specified or default value for the 8257 `--march=ARCHITECTURE' option (*note march-option::). 8258 8259 8260 8261File: as.info, Node: D10V-Dependent, Next: D30V-Dependent, Prev: CRIS-Dependent, Up: Machine Dependencies 8262 82639.8 D10V Dependent Features 8264=========================== 8265 8266* Menu: 8267 8268* D10V-Opts:: D10V Options 8269* D10V-Syntax:: Syntax 8270* D10V-Float:: Floating Point 8271* D10V-Opcodes:: Opcodes 8272 8273 8274File: as.info, Node: D10V-Opts, Next: D10V-Syntax, Up: D10V-Dependent 8275 82769.8.1 D10V Options 8277------------------ 8278 8279The Mitsubishi D10V version of `as' has a few machine dependent options. 8280 8281`-O' 8282 The D10V can often execute two sub-instructions in parallel. When 8283 this option is used, `as' will attempt to optimize its output by 8284 detecting when instructions can be executed in parallel. 8285 8286`--nowarnswap' 8287 To optimize execution performance, `as' will sometimes swap the 8288 order of instructions. Normally this generates a warning. When 8289 this option is used, no warning will be generated when 8290 instructions are swapped. 8291 8292`--gstabs-packing' 8293`--no-gstabs-packing' 8294 `as' packs adjacent short instructions into a single packed 8295 instruction. `--no-gstabs-packing' turns instruction packing off if 8296 `--gstabs' is specified as well; `--gstabs-packing' (the default) 8297 turns instruction packing on even when `--gstabs' is specified. 8298 8299 8300File: as.info, Node: D10V-Syntax, Next: D10V-Float, Prev: D10V-Opts, Up: D10V-Dependent 8301 83029.8.2 Syntax 8303------------ 8304 8305The D10V syntax is based on the syntax in Mitsubishi's D10V 8306architecture manual. The differences are detailed below. 8307 8308* Menu: 8309 8310* D10V-Size:: Size Modifiers 8311* D10V-Subs:: Sub-Instructions 8312* D10V-Chars:: Special Characters 8313* D10V-Regs:: Register Names 8314* D10V-Addressing:: Addressing Modes 8315* D10V-Word:: @WORD Modifier 8316 8317 8318File: as.info, Node: D10V-Size, Next: D10V-Subs, Up: D10V-Syntax 8319 83209.8.2.1 Size Modifiers 8321...................... 8322 8323The D10V version of `as' uses the instruction names in the D10V 8324Architecture Manual. However, the names in the manual are sometimes 8325ambiguous. There are instruction names that can assemble to a short or 8326long form opcode. How does the assembler pick the correct form? `as' 8327will always pick the smallest form if it can. When dealing with a 8328symbol that is not defined yet when a line is being assembled, it will 8329always use the long form. If you need to force the assembler to use 8330either the short or long form of the instruction, you can append either 8331`.s' (short) or `.l' (long) to it. For example, if you are writing an 8332assembly program and you want to do a branch to a symbol that is 8333defined later in your program, you can write `bra.s foo'. Objdump 8334and GDB will always append `.s' or `.l' to instructions which have both 8335short and long forms. 8336 8337 8338File: as.info, Node: D10V-Subs, Next: D10V-Chars, Prev: D10V-Size, Up: D10V-Syntax 8339 83409.8.2.2 Sub-Instructions 8341........................ 8342 8343The D10V assembler takes as input a series of instructions, either 8344one-per-line, or in the special two-per-line format described in the 8345next section. Some of these instructions will be short-form or 8346sub-instructions. These sub-instructions can be packed into a single 8347instruction. The assembler will do this automatically. It will also 8348detect when it should not pack instructions. For example, when a label 8349is defined, the next instruction will never be packaged with the 8350previous one. Whenever a branch and link instruction is called, it 8351will not be packaged with the next instruction so the return address 8352will be valid. Nops are automatically inserted when necessary. 8353 8354 If you do not want the assembler automatically making these 8355decisions, you can control the packaging and execution type (parallel 8356or sequential) with the special execution symbols described in the next 8357section. 8358 8359 8360File: as.info, Node: D10V-Chars, Next: D10V-Regs, Prev: D10V-Subs, Up: D10V-Syntax 8361 83629.8.2.3 Special Characters 8363.......................... 8364 8365A semicolon (`;') can be used anywhere on a line to start a comment 8366that extends to the end of the line. 8367 8368 If a `#' appears as the first character of a line, the whole line is 8369treated as a comment, but in this case the line could also be a logical 8370line number directive (*note Comments::) or a preprocessor control 8371command (*note Preprocessing::). 8372 8373 Sub-instructions may be executed in order, in reverse-order, or in 8374parallel. Instructions listed in the standard one-per-line format will 8375be executed sequentially. To specify the executing order, use the 8376following symbols: 8377`->' 8378 Sequential with instruction on the left first. 8379 8380`<-' 8381 Sequential with instruction on the right first. 8382 8383`||' 8384 Parallel 8385 The D10V syntax allows either one instruction per line, one 8386instruction per line with the execution symbol, or two instructions per 8387line. For example 8388`abs a1 -> abs r0' 8389 Execute these sequentially. The instruction on the right is in 8390 the right container and is executed second. 8391 8392`abs r0 <- abs a1' 8393 Execute these reverse-sequentially. The instruction on the right 8394 is in the right container, and is executed first. 8395 8396`ld2w r2,@r8+ || mac a0,r0,r7' 8397 Execute these in parallel. 8398 8399`ld2w r2,@r8+ ||' 8400`mac a0,r0,r7' 8401 Two-line format. Execute these in parallel. 8402 8403`ld2w r2,@r8+' 8404`mac a0,r0,r7' 8405 Two-line format. Execute these sequentially. Assembler will put 8406 them in the proper containers. 8407 8408`ld2w r2,@r8+ ->' 8409`mac a0,r0,r7' 8410 Two-line format. Execute these sequentially. Same as above but 8411 second instruction will always go into right container. 8412 Since `$' has no special meaning, you may use it in symbol names. 8413 8414 8415File: as.info, Node: D10V-Regs, Next: D10V-Addressing, Prev: D10V-Chars, Up: D10V-Syntax 8416 84179.8.2.4 Register Names 8418...................... 8419 8420You can use the predefined symbols `r0' through `r15' to refer to the 8421D10V registers. You can also use `sp' as an alias for `r15'. The 8422accumulators are `a0' and `a1'. There are special register-pair names 8423that may optionally be used in opcodes that require even-numbered 8424registers. Register names are not case sensitive. 8425 8426 Register Pairs 8427`r0-r1' 8428 8429`r2-r3' 8430 8431`r4-r5' 8432 8433`r6-r7' 8434 8435`r8-r9' 8436 8437`r10-r11' 8438 8439`r12-r13' 8440 8441`r14-r15' 8442 8443 The D10V also has predefined symbols for these control registers and 8444status bits: 8445`psw' 8446 Processor Status Word 8447 8448`bpsw' 8449 Backup Processor Status Word 8450 8451`pc' 8452 Program Counter 8453 8454`bpc' 8455 Backup Program Counter 8456 8457`rpt_c' 8458 Repeat Count 8459 8460`rpt_s' 8461 Repeat Start address 8462 8463`rpt_e' 8464 Repeat End address 8465 8466`mod_s' 8467 Modulo Start address 8468 8469`mod_e' 8470 Modulo End address 8471 8472`iba' 8473 Instruction Break Address 8474 8475`f0' 8476 Flag 0 8477 8478`f1' 8479 Flag 1 8480 8481`c' 8482 Carry flag 8483 8484 8485File: as.info, Node: D10V-Addressing, Next: D10V-Word, Prev: D10V-Regs, Up: D10V-Syntax 8486 84879.8.2.5 Addressing Modes 8488........................ 8489 8490`as' understands the following addressing modes for the D10V. `RN' in 8491the following refers to any of the numbered registers, but _not_ the 8492control registers. 8493`RN' 8494 Register direct 8495 8496`@RN' 8497 Register indirect 8498 8499`@RN+' 8500 Register indirect with post-increment 8501 8502`@RN-' 8503 Register indirect with post-decrement 8504 8505`@-SP' 8506 Register indirect with pre-decrement 8507 8508`@(DISP, RN)' 8509 Register indirect with displacement 8510 8511`ADDR' 8512 PC relative address (for branch or rep). 8513 8514`#IMM' 8515 Immediate data (the `#' is optional and ignored) 8516 8517 8518File: as.info, Node: D10V-Word, Prev: D10V-Addressing, Up: D10V-Syntax 8519 85209.8.2.6 @WORD Modifier 8521...................... 8522 8523Any symbol followed by `@word' will be replaced by the symbol's value 8524shifted right by 2. This is used in situations such as loading a 8525register with the address of a function (or any other code fragment). 8526For example, if you want to load a register with the location of the 8527function `main' then jump to that function, you could do it as follows: 8528 ldi r2, main@word 8529 jmp r2 8530 8531 8532File: as.info, Node: D10V-Float, Next: D10V-Opcodes, Prev: D10V-Syntax, Up: D10V-Dependent 8533 85349.8.3 Floating Point 8535-------------------- 8536 8537The D10V has no hardware floating point, but the `.float' and `.double' 8538directives generates IEEE floating-point numbers for compatibility with 8539other development tools. 8540 8541 8542File: as.info, Node: D10V-Opcodes, Prev: D10V-Float, Up: D10V-Dependent 8543 85449.8.4 Opcodes 8545------------- 8546 8547For detailed information on the D10V machine instruction set, see `D10V 8548Architecture: A VLIW Microprocessor for Multimedia Applications' 8549(Mitsubishi Electric Corp.). `as' implements all the standard D10V 8550opcodes. The only changes are those described in the section on size 8551modifiers 8552 8553 8554File: as.info, Node: D30V-Dependent, Next: H8/300-Dependent, Prev: D10V-Dependent, Up: Machine Dependencies 8555 85569.9 D30V Dependent Features 8557=========================== 8558 8559* Menu: 8560 8561* D30V-Opts:: D30V Options 8562* D30V-Syntax:: Syntax 8563* D30V-Float:: Floating Point 8564* D30V-Opcodes:: Opcodes 8565 8566 8567File: as.info, Node: D30V-Opts, Next: D30V-Syntax, Up: D30V-Dependent 8568 85699.9.1 D30V Options 8570------------------ 8571 8572The Mitsubishi D30V version of `as' has a few machine dependent options. 8573 8574`-O' 8575 The D30V can often execute two sub-instructions in parallel. When 8576 this option is used, `as' will attempt to optimize its output by 8577 detecting when instructions can be executed in parallel. 8578 8579`-n' 8580 When this option is used, `as' will issue a warning every time it 8581 adds a nop instruction. 8582 8583`-N' 8584 When this option is used, `as' will issue a warning if it needs to 8585 insert a nop after a 32-bit multiply before a load or 16-bit 8586 multiply instruction. 8587 8588 8589File: as.info, Node: D30V-Syntax, Next: D30V-Float, Prev: D30V-Opts, Up: D30V-Dependent 8590 85919.9.2 Syntax 8592------------ 8593 8594The D30V syntax is based on the syntax in Mitsubishi's D30V 8595architecture manual. The differences are detailed below. 8596 8597* Menu: 8598 8599* D30V-Size:: Size Modifiers 8600* D30V-Subs:: Sub-Instructions 8601* D30V-Chars:: Special Characters 8602* D30V-Guarded:: Guarded Execution 8603* D30V-Regs:: Register Names 8604* D30V-Addressing:: Addressing Modes 8605 8606 8607File: as.info, Node: D30V-Size, Next: D30V-Subs, Up: D30V-Syntax 8608 86099.9.2.1 Size Modifiers 8610...................... 8611 8612The D30V version of `as' uses the instruction names in the D30V 8613Architecture Manual. However, the names in the manual are sometimes 8614ambiguous. There are instruction names that can assemble to a short or 8615long form opcode. How does the assembler pick the correct form? `as' 8616will always pick the smallest form if it can. When dealing with a 8617symbol that is not defined yet when a line is being assembled, it will 8618always use the long form. If you need to force the assembler to use 8619either the short or long form of the instruction, you can append either 8620`.s' (short) or `.l' (long) to it. For example, if you are writing an 8621assembly program and you want to do a branch to a symbol that is 8622defined later in your program, you can write `bra.s foo'. Objdump and 8623GDB will always append `.s' or `.l' to instructions which have both 8624short and long forms. 8625 8626 8627File: as.info, Node: D30V-Subs, Next: D30V-Chars, Prev: D30V-Size, Up: D30V-Syntax 8628 86299.9.2.2 Sub-Instructions 8630........................ 8631 8632The D30V assembler takes as input a series of instructions, either 8633one-per-line, or in the special two-per-line format described in the 8634next section. Some of these instructions will be short-form or 8635sub-instructions. These sub-instructions can be packed into a single 8636instruction. The assembler will do this automatically. It will also 8637detect when it should not pack instructions. For example, when a label 8638is defined, the next instruction will never be packaged with the 8639previous one. Whenever a branch and link instruction is called, it 8640will not be packaged with the next instruction so the return address 8641will be valid. Nops are automatically inserted when necessary. 8642 8643 If you do not want the assembler automatically making these 8644decisions, you can control the packaging and execution type (parallel 8645or sequential) with the special execution symbols described in the next 8646section. 8647 8648 8649File: as.info, Node: D30V-Chars, Next: D30V-Guarded, Prev: D30V-Subs, Up: D30V-Syntax 8650 86519.9.2.3 Special Characters 8652.......................... 8653 8654A semicolon (`;') can be used anywhere on a line to start a comment 8655that extends to the end of the line. 8656 8657 If a `#' appears as the first character of a line, the whole line is 8658treated as a comment, but in this case the line could also be a logical 8659line number directive (*note Comments::) or a preprocessor control 8660command (*note Preprocessing::). 8661 8662 Sub-instructions may be executed in order, in reverse-order, or in 8663parallel. Instructions listed in the standard one-per-line format will 8664be executed sequentially unless you use the `-O' option. 8665 8666 To specify the executing order, use the following symbols: 8667`->' 8668 Sequential with instruction on the left first. 8669 8670`<-' 8671 Sequential with instruction on the right first. 8672 8673`||' 8674 Parallel 8675 8676 The D30V syntax allows either one instruction per line, one 8677instruction per line with the execution symbol, or two instructions per 8678line. For example 8679`abs r2,r3 -> abs r4,r5' 8680 Execute these sequentially. The instruction on the right is in 8681 the right container and is executed second. 8682 8683`abs r2,r3 <- abs r4,r5' 8684 Execute these reverse-sequentially. The instruction on the right 8685 is in the right container, and is executed first. 8686 8687`abs r2,r3 || abs r4,r5' 8688 Execute these in parallel. 8689 8690`ldw r2,@(r3,r4) ||' 8691`mulx r6,r8,r9' 8692 Two-line format. Execute these in parallel. 8693 8694`mulx a0,r8,r9' 8695`stw r2,@(r3,r4)' 8696 Two-line format. Execute these sequentially unless `-O' option is 8697 used. If the `-O' option is used, the assembler will determine if 8698 the instructions could be done in parallel (the above two 8699 instructions can be done in parallel), and if so, emit them as 8700 parallel instructions. The assembler will put them in the proper 8701 containers. In the above example, the assembler will put the 8702 `stw' instruction in left container and the `mulx' instruction in 8703 the right container. 8704 8705`stw r2,@(r3,r4) ->' 8706`mulx a0,r8,r9' 8707 Two-line format. Execute the `stw' instruction followed by the 8708 `mulx' instruction sequentially. The first instruction goes in the 8709 left container and the second instruction goes into right 8710 container. The assembler will give an error if the machine 8711 ordering constraints are violated. 8712 8713`stw r2,@(r3,r4) <-' 8714`mulx a0,r8,r9' 8715 Same as previous example, except that the `mulx' instruction is 8716 executed before the `stw' instruction. 8717 8718 Since `$' has no special meaning, you may use it in symbol names. 8719 8720 8721File: as.info, Node: D30V-Guarded, Next: D30V-Regs, Prev: D30V-Chars, Up: D30V-Syntax 8722 87239.9.2.4 Guarded Execution 8724......................... 8725 8726`as' supports the full range of guarded execution directives for each 8727instruction. Just append the directive after the instruction proper. 8728The directives are: 8729 8730`/tx' 8731 Execute the instruction if flag f0 is true. 8732 8733`/fx' 8734 Execute the instruction if flag f0 is false. 8735 8736`/xt' 8737 Execute the instruction if flag f1 is true. 8738 8739`/xf' 8740 Execute the instruction if flag f1 is false. 8741 8742`/tt' 8743 Execute the instruction if both flags f0 and f1 are true. 8744 8745`/tf' 8746 Execute the instruction if flag f0 is true and flag f1 is false. 8747 8748 8749File: as.info, Node: D30V-Regs, Next: D30V-Addressing, Prev: D30V-Guarded, Up: D30V-Syntax 8750 87519.9.2.5 Register Names 8752...................... 8753 8754You can use the predefined symbols `r0' through `r63' to refer to the 8755D30V registers. You can also use `sp' as an alias for `r63' and `link' 8756as an alias for `r62'. The accumulators are `a0' and `a1'. 8757 8758 The D30V also has predefined symbols for these control registers and 8759status bits: 8760`psw' 8761 Processor Status Word 8762 8763`bpsw' 8764 Backup Processor Status Word 8765 8766`pc' 8767 Program Counter 8768 8769`bpc' 8770 Backup Program Counter 8771 8772`rpt_c' 8773 Repeat Count 8774 8775`rpt_s' 8776 Repeat Start address 8777 8778`rpt_e' 8779 Repeat End address 8780 8781`mod_s' 8782 Modulo Start address 8783 8784`mod_e' 8785 Modulo End address 8786 8787`iba' 8788 Instruction Break Address 8789 8790`f0' 8791 Flag 0 8792 8793`f1' 8794 Flag 1 8795 8796`f2' 8797 Flag 2 8798 8799`f3' 8800 Flag 3 8801 8802`f4' 8803 Flag 4 8804 8805`f5' 8806 Flag 5 8807 8808`f6' 8809 Flag 6 8810 8811`f7' 8812 Flag 7 8813 8814`s' 8815 Same as flag 4 (saturation flag) 8816 8817`v' 8818 Same as flag 5 (overflow flag) 8819 8820`va' 8821 Same as flag 6 (sticky overflow flag) 8822 8823`c' 8824 Same as flag 7 (carry/borrow flag) 8825 8826`b' 8827 Same as flag 7 (carry/borrow flag) 8828 8829 8830File: as.info, Node: D30V-Addressing, Prev: D30V-Regs, Up: D30V-Syntax 8831 88329.9.2.6 Addressing Modes 8833........................ 8834 8835`as' understands the following addressing modes for the D30V. `RN' in 8836the following refers to any of the numbered registers, but _not_ the 8837control registers. 8838`RN' 8839 Register direct 8840 8841`@RN' 8842 Register indirect 8843 8844`@RN+' 8845 Register indirect with post-increment 8846 8847`@RN-' 8848 Register indirect with post-decrement 8849 8850`@-SP' 8851 Register indirect with pre-decrement 8852 8853`@(DISP, RN)' 8854 Register indirect with displacement 8855 8856`ADDR' 8857 PC relative address (for branch or rep). 8858 8859`#IMM' 8860 Immediate data (the `#' is optional and ignored) 8861 8862 8863File: as.info, Node: D30V-Float, Next: D30V-Opcodes, Prev: D30V-Syntax, Up: D30V-Dependent 8864 88659.9.3 Floating Point 8866-------------------- 8867 8868The D30V has no hardware floating point, but the `.float' and `.double' 8869directives generates IEEE floating-point numbers for compatibility with 8870other development tools. 8871 8872 8873File: as.info, Node: D30V-Opcodes, Prev: D30V-Float, Up: D30V-Dependent 8874 88759.9.4 Opcodes 8876------------- 8877 8878For detailed information on the D30V machine instruction set, see `D30V 8879Architecture: A VLIW Microprocessor for Multimedia Applications' 8880(Mitsubishi Electric Corp.). `as' implements all the standard D30V 8881opcodes. The only changes are those described in the section on size 8882modifiers 8883 8884 8885File: as.info, Node: H8/300-Dependent, Next: HPPA-Dependent, Prev: D30V-Dependent, Up: Machine Dependencies 8886 88879.10 H8/300 Dependent Features 8888============================== 8889 8890* Menu: 8891 8892* H8/300 Options:: Options 8893* H8/300 Syntax:: Syntax 8894* H8/300 Floating Point:: Floating Point 8895* H8/300 Directives:: H8/300 Machine Directives 8896* H8/300 Opcodes:: Opcodes 8897 8898 8899File: as.info, Node: H8/300 Options, Next: H8/300 Syntax, Up: H8/300-Dependent 8900 89019.10.1 Options 8902-------------- 8903 8904The Renesas H8/300 version of `as' has one machine-dependent option: 8905 8906`-h-tick-hex' 8907 Support H'00 style hex constants in addition to 0x00 style. 8908 8909 8910 8911File: as.info, Node: H8/300 Syntax, Next: H8/300 Floating Point, Prev: H8/300 Options, Up: H8/300-Dependent 8912 89139.10.2 Syntax 8914------------- 8915 8916* Menu: 8917 8918* H8/300-Chars:: Special Characters 8919* H8/300-Regs:: Register Names 8920* H8/300-Addressing:: Addressing Modes 8921 8922 8923File: as.info, Node: H8/300-Chars, Next: H8/300-Regs, Up: H8/300 Syntax 8924 89259.10.2.1 Special Characters 8926........................... 8927 8928`;' is the line comment character. 8929 8930 `$' can be used instead of a newline to separate statements. 8931Therefore _you may not use `$' in symbol names_ on the H8/300. 8932 8933 8934File: as.info, Node: H8/300-Regs, Next: H8/300-Addressing, Prev: H8/300-Chars, Up: H8/300 Syntax 8935 89369.10.2.2 Register Names 8937....................... 8938 8939You can use predefined symbols of the form `rNh' and `rNl' to refer to 8940the H8/300 registers as sixteen 8-bit general-purpose registers. N is 8941a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid 8942register names. 8943 8944 You can also use the eight predefined symbols `rN' to refer to the 8945H8/300 registers as 16-bit registers (you must use this form for 8946addressing). 8947 8948 On the H8/300H, you can also use the eight predefined symbols `erN' 8949(`er0' ... `er7') to refer to the 32-bit general purpose registers. 8950 8951 The two control registers are called `pc' (program counter; a 16-bit 8952register, except on the H8/300H where it is 24 bits) and `ccr' 8953(condition code register; an 8-bit register). `r7' is used as the 8954stack pointer, and can also be called `sp'. 8955 8956 8957File: as.info, Node: H8/300-Addressing, Prev: H8/300-Regs, Up: H8/300 Syntax 8958 89599.10.2.3 Addressing Modes 8960......................... 8961 8962as understands the following addressing modes for the H8/300: 8963`rN' 8964 Register direct 8965 8966`@rN' 8967 Register indirect 8968 8969`@(D, rN)' 8970`@(D:16, rN)' 8971`@(D:24, rN)' 8972 Register indirect: 16-bit or 24-bit displacement D from register 8973 N. (24-bit displacements are only meaningful on the H8/300H.) 8974 8975`@rN+' 8976 Register indirect with post-increment 8977 8978`@-rN' 8979 Register indirect with pre-decrement 8980 8981``@'AA' 8982``@'AA:8' 8983``@'AA:16' 8984``@'AA:24' 8985 Absolute address `aa'. (The address size `:24' only makes sense 8986 on the H8/300H.) 8987 8988`#XX' 8989`#XX:8' 8990`#XX:16' 8991`#XX:32' 8992 Immediate data XX. You may specify the `:8', `:16', or `:32' for 8993 clarity, if you wish; but `as' neither requires this nor uses 8994 it--the data size required is taken from context. 8995 8996``@'`@'AA' 8997``@'`@'AA:8' 8998 Memory indirect. You may specify the `:8' for clarity, if you 8999 wish; but `as' neither requires this nor uses it. 9000 9001 9002File: as.info, Node: H8/300 Floating Point, Next: H8/300 Directives, Prev: H8/300 Syntax, Up: H8/300-Dependent 9003 90049.10.3 Floating Point 9005--------------------- 9006 9007The H8/300 family has no hardware floating point, but the `.float' 9008directive generates IEEE floating-point numbers for compatibility with 9009other development tools. 9010 9011 9012File: as.info, Node: H8/300 Directives, Next: H8/300 Opcodes, Prev: H8/300 Floating Point, Up: H8/300-Dependent 9013 90149.10.4 H8/300 Machine Directives 9015-------------------------------- 9016 9017`as' has the following machine-dependent directives for the H8/300: 9018 9019`.h8300h' 9020 Recognize and emit additional instructions for the H8/300H 9021 variant, and also make `.int' emit 32-bit numbers rather than the 9022 usual (16-bit) for the H8/300 family. 9023 9024`.h8300s' 9025 Recognize and emit additional instructions for the H8S variant, and 9026 also make `.int' emit 32-bit numbers rather than the usual (16-bit) 9027 for the H8/300 family. 9028 9029`.h8300hn' 9030 Recognize and emit additional instructions for the H8/300H variant 9031 in normal mode, and also make `.int' emit 32-bit numbers rather 9032 than the usual (16-bit) for the H8/300 family. 9033 9034`.h8300sn' 9035 Recognize and emit additional instructions for the H8S variant in 9036 normal mode, and also make `.int' emit 32-bit numbers rather than 9037 the usual (16-bit) for the H8/300 family. 9038 9039 On the H8/300 family (including the H8/300H) `.word' directives 9040generate 16-bit numbers. 9041 9042 9043File: as.info, Node: H8/300 Opcodes, Prev: H8/300 Directives, Up: H8/300-Dependent 9044 90459.10.5 Opcodes 9046-------------- 9047 9048For detailed information on the H8/300 machine instruction set, see 9049`H8/300 Series Programming Manual'. For information specific to the 9050H8/300H, see `H8/300H Series Programming Manual' (Renesas). 9051 9052 `as' implements all the standard H8/300 opcodes. No additional 9053pseudo-instructions are needed on this family. 9054 9055 The following table summarizes the H8/300 opcodes, and their 9056arguments. Entries marked `*' are opcodes used only on the H8/300H. 9057 9058 Legend: 9059 Rs source register 9060 Rd destination register 9061 abs absolute address 9062 imm immediate data 9063 disp:N N-bit displacement from a register 9064 pcrel:N N-bit displacement relative to program counter 9065 9066 add.b #imm,rd * andc #imm,ccr 9067 add.b rs,rd band #imm,rd 9068 add.w rs,rd band #imm,@rd 9069 * add.w #imm,rd band #imm,@abs:8 9070 * add.l rs,rd bra pcrel:8 9071 * add.l #imm,rd * bra pcrel:16 9072 adds #imm,rd bt pcrel:8 9073 addx #imm,rd * bt pcrel:16 9074 addx rs,rd brn pcrel:8 9075 and.b #imm,rd * brn pcrel:16 9076 and.b rs,rd bf pcrel:8 9077 * and.w rs,rd * bf pcrel:16 9078 * and.w #imm,rd bhi pcrel:8 9079 * and.l #imm,rd * bhi pcrel:16 9080 * and.l rs,rd bls pcrel:8 9081 9082 * bls pcrel:16 bld #imm,rd 9083 bcc pcrel:8 bld #imm,@rd 9084 * bcc pcrel:16 bld #imm,@abs:8 9085 bhs pcrel:8 bnot #imm,rd 9086 * bhs pcrel:16 bnot #imm,@rd 9087 bcs pcrel:8 bnot #imm,@abs:8 9088 * bcs pcrel:16 bnot rs,rd 9089 blo pcrel:8 bnot rs,@rd 9090 * blo pcrel:16 bnot rs,@abs:8 9091 bne pcrel:8 bor #imm,rd 9092 * bne pcrel:16 bor #imm,@rd 9093 beq pcrel:8 bor #imm,@abs:8 9094 * beq pcrel:16 bset #imm,rd 9095 bvc pcrel:8 bset #imm,@rd 9096 * bvc pcrel:16 bset #imm,@abs:8 9097 bvs pcrel:8 bset rs,rd 9098 * bvs pcrel:16 bset rs,@rd 9099 bpl pcrel:8 bset rs,@abs:8 9100 * bpl pcrel:16 bsr pcrel:8 9101 bmi pcrel:8 bsr pcrel:16 9102 * bmi pcrel:16 bst #imm,rd 9103 bge pcrel:8 bst #imm,@rd 9104 * bge pcrel:16 bst #imm,@abs:8 9105 blt pcrel:8 btst #imm,rd 9106 * blt pcrel:16 btst #imm,@rd 9107 bgt pcrel:8 btst #imm,@abs:8 9108 * bgt pcrel:16 btst rs,rd 9109 ble pcrel:8 btst rs,@rd 9110 * ble pcrel:16 btst rs,@abs:8 9111 bclr #imm,rd bxor #imm,rd 9112 bclr #imm,@rd bxor #imm,@rd 9113 bclr #imm,@abs:8 bxor #imm,@abs:8 9114 bclr rs,rd cmp.b #imm,rd 9115 bclr rs,@rd cmp.b rs,rd 9116 bclr rs,@abs:8 cmp.w rs,rd 9117 biand #imm,rd cmp.w rs,rd 9118 biand #imm,@rd * cmp.w #imm,rd 9119 biand #imm,@abs:8 * cmp.l #imm,rd 9120 bild #imm,rd * cmp.l rs,rd 9121 bild #imm,@rd daa rs 9122 bild #imm,@abs:8 das rs 9123 bior #imm,rd dec.b rs 9124 bior #imm,@rd * dec.w #imm,rd 9125 bior #imm,@abs:8 * dec.l #imm,rd 9126 bist #imm,rd divxu.b rs,rd 9127 bist #imm,@rd * divxu.w rs,rd 9128 bist #imm,@abs:8 * divxs.b rs,rd 9129 bixor #imm,rd * divxs.w rs,rd 9130 bixor #imm,@rd eepmov 9131 bixor #imm,@abs:8 * eepmovw 9132 9133 * exts.w rd mov.w rs,@abs:16 9134 * exts.l rd * mov.l #imm,rd 9135 * extu.w rd * mov.l rs,rd 9136 * extu.l rd * mov.l @rs,rd 9137 inc rs * mov.l @(disp:16,rs),rd 9138 * inc.w #imm,rd * mov.l @(disp:24,rs),rd 9139 * inc.l #imm,rd * mov.l @rs+,rd 9140 jmp @rs * mov.l @abs:16,rd 9141 jmp abs * mov.l @abs:24,rd 9142 jmp @@abs:8 * mov.l rs,@rd 9143 jsr @rs * mov.l rs,@(disp:16,rd) 9144 jsr abs * mov.l rs,@(disp:24,rd) 9145 jsr @@abs:8 * mov.l rs,@-rd 9146 ldc #imm,ccr * mov.l rs,@abs:16 9147 ldc rs,ccr * mov.l rs,@abs:24 9148 * ldc @abs:16,ccr movfpe @abs:16,rd 9149 * ldc @abs:24,ccr movtpe rs,@abs:16 9150 * ldc @(disp:16,rs),ccr mulxu.b rs,rd 9151 * ldc @(disp:24,rs),ccr * mulxu.w rs,rd 9152 * ldc @rs+,ccr * mulxs.b rs,rd 9153 * ldc @rs,ccr * mulxs.w rs,rd 9154 * mov.b @(disp:24,rs),rd neg.b rs 9155 * mov.b rs,@(disp:24,rd) * neg.w rs 9156 mov.b @abs:16,rd * neg.l rs 9157 mov.b rs,rd nop 9158 mov.b @abs:8,rd not.b rs 9159 mov.b rs,@abs:8 * not.w rs 9160 mov.b rs,rd * not.l rs 9161 mov.b #imm,rd or.b #imm,rd 9162 mov.b @rs,rd or.b rs,rd 9163 mov.b @(disp:16,rs),rd * or.w #imm,rd 9164 mov.b @rs+,rd * or.w rs,rd 9165 mov.b @abs:8,rd * or.l #imm,rd 9166 mov.b rs,@rd * or.l rs,rd 9167 mov.b rs,@(disp:16,rd) orc #imm,ccr 9168 mov.b rs,@-rd pop.w rs 9169 mov.b rs,@abs:8 * pop.l rs 9170 mov.w rs,@rd push.w rs 9171 * mov.w @(disp:24,rs),rd * push.l rs 9172 * mov.w rs,@(disp:24,rd) rotl.b rs 9173 * mov.w @abs:24,rd * rotl.w rs 9174 * mov.w rs,@abs:24 * rotl.l rs 9175 mov.w rs,rd rotr.b rs 9176 mov.w #imm,rd * rotr.w rs 9177 mov.w @rs,rd * rotr.l rs 9178 mov.w @(disp:16,rs),rd rotxl.b rs 9179 mov.w @rs+,rd * rotxl.w rs 9180 mov.w @abs:16,rd * rotxl.l rs 9181 mov.w rs,@(disp:16,rd) rotxr.b rs 9182 mov.w rs,@-rd * rotxr.w rs 9183 9184 * rotxr.l rs * stc ccr,@(disp:24,rd) 9185 bpt * stc ccr,@-rd 9186 rte * stc ccr,@abs:16 9187 rts * stc ccr,@abs:24 9188 shal.b rs sub.b rs,rd 9189 * shal.w rs sub.w rs,rd 9190 * shal.l rs * sub.w #imm,rd 9191 shar.b rs * sub.l rs,rd 9192 * shar.w rs * sub.l #imm,rd 9193 * shar.l rs subs #imm,rd 9194 shll.b rs subx #imm,rd 9195 * shll.w rs subx rs,rd 9196 * shll.l rs * trapa #imm 9197 shlr.b rs xor #imm,rd 9198 * shlr.w rs xor rs,rd 9199 * shlr.l rs * xor.w #imm,rd 9200 sleep * xor.w rs,rd 9201 stc ccr,rd * xor.l #imm,rd 9202 * stc ccr,@rs * xor.l rs,rd 9203 * stc ccr,@(disp:16,rd) xorc #imm,ccr 9204 9205 Four H8/300 instructions (`add', `cmp', `mov', `sub') are defined 9206with variants using the suffixes `.b', `.w', and `.l' to specify the 9207size of a memory operand. `as' supports these suffixes, but does not 9208require them; since one of the operands is always a register, `as' can 9209deduce the correct size. 9210 9211 For example, since `r0' refers to a 16-bit register, 9212 mov r0,@foo 9213is equivalent to 9214 mov.w r0,@foo 9215 9216 If you use the size suffixes, `as' issues a warning when the suffix 9217and the register size do not match. 9218 9219 9220File: as.info, Node: HPPA-Dependent, Next: ESA/390-Dependent, Prev: H8/300-Dependent, Up: Machine Dependencies 9221 92229.11 HPPA Dependent Features 9223============================ 9224 9225* Menu: 9226 9227* HPPA Notes:: Notes 9228* HPPA Options:: Options 9229* HPPA Syntax:: Syntax 9230* HPPA Floating Point:: Floating Point 9231* HPPA Directives:: HPPA Machine Directives 9232* HPPA Opcodes:: Opcodes 9233 9234 9235File: as.info, Node: HPPA Notes, Next: HPPA Options, Up: HPPA-Dependent 9236 92379.11.1 Notes 9238------------ 9239 9240As a back end for GNU CC `as' has been throughly tested and should work 9241extremely well. We have tested it only minimally on hand written 9242assembly code and no one has tested it much on the assembly output from 9243the HP compilers. 9244 9245 The format of the debugging sections has changed since the original 9246`as' port (version 1.3X) was released; therefore, you must rebuild all 9247HPPA objects and libraries with the new assembler so that you can debug 9248the final executable. 9249 9250 The HPPA `as' port generates a small subset of the relocations 9251available in the SOM and ELF object file formats. Additional relocation 9252support will be added as it becomes necessary. 9253 9254 9255File: as.info, Node: HPPA Options, Next: HPPA Syntax, Prev: HPPA Notes, Up: HPPA-Dependent 9256 92579.11.2 Options 9258-------------- 9259 9260`as' has no machine-dependent command-line options for the HPPA. 9261 9262 9263File: as.info, Node: HPPA Syntax, Next: HPPA Floating Point, Prev: HPPA Options, Up: HPPA-Dependent 9264 92659.11.3 Syntax 9266------------- 9267 9268The assembler syntax closely follows the HPPA instruction set reference 9269manual; assembler directives and general syntax closely follow the HPPA 9270assembly language reference manual, with a few noteworthy differences. 9271 9272 First, a colon may immediately follow a label definition. This is 9273simply for compatibility with how most assembly language programmers 9274write code. 9275 9276 Some obscure expression parsing problems may affect hand written 9277code which uses the `spop' instructions, or code which makes significant 9278use of the `!' line separator. 9279 9280 `as' is much less forgiving about missing arguments and other 9281similar oversights than the HP assembler. `as' notifies you of missing 9282arguments as syntax errors; this is regarded as a feature, not a bug. 9283 9284 Finally, `as' allows you to use an external symbol without 9285explicitly importing the symbol. _Warning:_ in the future this will be 9286an error for HPPA targets. 9287 9288 Special characters for HPPA targets include: 9289 9290 `;' is the line comment character. 9291 9292 `!' can be used instead of a newline to separate statements. 9293 9294 Since `$' has no special meaning, you may use it in symbol names. 9295 9296 9297File: as.info, Node: HPPA Floating Point, Next: HPPA Directives, Prev: HPPA Syntax, Up: HPPA-Dependent 9298 92999.11.4 Floating Point 9300--------------------- 9301 9302The HPPA family uses IEEE floating-point numbers. 9303 9304 9305File: as.info, Node: HPPA Directives, Next: HPPA Opcodes, Prev: HPPA Floating Point, Up: HPPA-Dependent 9306 93079.11.5 HPPA Assembler Directives 9308-------------------------------- 9309 9310`as' for the HPPA supports many additional directives for compatibility 9311with the native assembler. This section describes them only briefly. 9312For detailed information on HPPA-specific assembler directives, see 9313`HP9000 Series 800 Assembly Language Reference Manual' (HP 92432-90001). 9314 9315 `as' does _not_ support the following assembler directives described 9316in the HP manual: 9317 9318 .endm .liston 9319 .enter .locct 9320 .leave .macro 9321 .listoff 9322 9323 Beyond those implemented for compatibility, `as' supports one 9324additional assembler directive for the HPPA: `.param'. It conveys 9325register argument locations for static functions. Its syntax closely 9326follows the `.export' directive. 9327 9328 These are the additional directives in `as' for the HPPA: 9329 9330`.block N' 9331`.blockz N' 9332 Reserve N bytes of storage, and initialize them to zero. 9333 9334`.call' 9335 Mark the beginning of a procedure call. Only the special case 9336 with _no arguments_ is allowed. 9337 9338`.callinfo [ PARAM=VALUE, ... ] [ FLAG, ... ]' 9339 Specify a number of parameters and flags that define the 9340 environment for a procedure. 9341 9342 PARAM may be any of `frame' (frame size), `entry_gr' (end of 9343 general register range), `entry_fr' (end of float register range), 9344 `entry_sr' (end of space register range). 9345 9346 The values for FLAG are `calls' or `caller' (proc has 9347 subroutines), `no_calls' (proc does not call subroutines), 9348 `save_rp' (preserve return pointer), `save_sp' (proc preserves 9349 stack pointer), `no_unwind' (do not unwind this proc), `hpux_int' 9350 (proc is interrupt routine). 9351 9352`.code' 9353 Assemble into the standard section called `$TEXT$', subsection 9354 `$CODE$'. 9355 9356`.copyright "STRING"' 9357 In the SOM object format, insert STRING into the object code, 9358 marked as a copyright string. 9359 9360`.copyright "STRING"' 9361 In the ELF object format, insert STRING into the object code, 9362 marked as a version string. 9363 9364`.enter' 9365 Not yet supported; the assembler rejects programs containing this 9366 directive. 9367 9368`.entry' 9369 Mark the beginning of a procedure. 9370 9371`.exit' 9372 Mark the end of a procedure. 9373 9374`.export NAME [ ,TYP ] [ ,PARAM=R ]' 9375 Make a procedure NAME available to callers. TYP, if present, must 9376 be one of `absolute', `code' (ELF only, not SOM), `data', `entry', 9377 `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'. 9378 9379 PARAM, if present, provides either relocation information for the 9380 procedure arguments and result, or a privilege level. PARAM may be 9381 `argwN' (where N ranges from `0' to `3', and indicates one of four 9382 one-word arguments); `rtnval' (the procedure's result); or 9383 `priv_lev' (privilege level). For arguments or the result, R 9384 specifies how to relocate, and must be one of `no' (not 9385 relocatable), `gr' (argument is in general register), `fr' (in 9386 floating point register), or `fu' (upper half of float register). 9387 For `priv_lev', R is an integer. 9388 9389`.half N' 9390 Define a two-byte integer constant N; synonym for the portable 9391 `as' directive `.short'. 9392 9393`.import NAME [ ,TYP ]' 9394 Converse of `.export'; make a procedure available to call. The 9395 arguments use the same conventions as the first two arguments for 9396 `.export'. 9397 9398`.label NAME' 9399 Define NAME as a label for the current assembly location. 9400 9401`.leave' 9402 Not yet supported; the assembler rejects programs containing this 9403 directive. 9404 9405`.origin LC' 9406 Advance location counter to LC. Synonym for the `as' portable 9407 directive `.org'. 9408 9409`.param NAME [ ,TYP ] [ ,PARAM=R ]' 9410 Similar to `.export', but used for static procedures. 9411 9412`.proc' 9413 Use preceding the first statement of a procedure. 9414 9415`.procend' 9416 Use following the last statement of a procedure. 9417 9418`LABEL .reg EXPR' 9419 Synonym for `.equ'; define LABEL with the absolute expression EXPR 9420 as its value. 9421 9422`.space SECNAME [ ,PARAMS ]' 9423 Switch to section SECNAME, creating a new section by that name if 9424 necessary. You may only use PARAMS when creating a new section, 9425 not when switching to an existing one. SECNAME may identify a 9426 section by number rather than by name. 9427 9428 If specified, the list PARAMS declares attributes of the section, 9429 identified by keywords. The keywords recognized are `spnum=EXP' 9430 (identify this section by the number EXP, an absolute expression), 9431 `sort=EXP' (order sections according to this sort key when linking; 9432 EXP is an absolute expression), `unloadable' (section contains no 9433 loadable data), `notdefined' (this section defined elsewhere), and 9434 `private' (data in this section not available to other programs). 9435 9436`.spnum SECNAM' 9437 Allocate four bytes of storage, and initialize them with the 9438 section number of the section named SECNAM. (You can define the 9439 section number with the HPPA `.space' directive.) 9440 9441`.string "STR"' 9442 Copy the characters in the string STR to the object file. *Note 9443 Strings: Strings, for information on escape sequences you can use 9444 in `as' strings. 9445 9446 _Warning!_ The HPPA version of `.string' differs from the usual 9447 `as' definition: it does _not_ write a zero byte after copying STR. 9448 9449`.stringz "STR"' 9450 Like `.string', but appends a zero byte after copying STR to object 9451 file. 9452 9453`.subspa NAME [ ,PARAMS ]' 9454`.nsubspa NAME [ ,PARAMS ]' 9455 Similar to `.space', but selects a subsection NAME within the 9456 current section. You may only specify PARAMS when you create a 9457 subsection (in the first instance of `.subspa' for this NAME). 9458 9459 If specified, the list PARAMS declares attributes of the 9460 subsection, identified by keywords. The keywords recognized are 9461 `quad=EXPR' ("quadrant" for this subsection), `align=EXPR' 9462 (alignment for beginning of this subsection; a power of two), 9463 `access=EXPR' (value for "access rights" field), `sort=EXPR' 9464 (sorting order for this subspace in link), `code_only' (subsection 9465 contains only code), `unloadable' (subsection cannot be loaded 9466 into memory), `comdat' (subsection is comdat), `common' 9467 (subsection is common block), `dup_comm' (subsection may have 9468 duplicate names), or `zero' (subsection is all zeros, do not write 9469 in object file). 9470 9471 `.nsubspa' always creates a new subspace with the given name, even 9472 if one with the same name already exists. 9473 9474 `comdat', `common' and `dup_comm' can be used to implement various 9475 flavors of one-only support when using the SOM linker. The SOM 9476 linker only supports specific combinations of these flags. The 9477 details are not documented. A brief description is provided here. 9478 9479 `comdat' provides a form of linkonce support. It is useful for 9480 both code and data subspaces. A `comdat' subspace has a key symbol 9481 marked by the `is_comdat' flag or `ST_COMDAT'. Only the first 9482 subspace for any given key is selected. The key symbol becomes 9483 universal in shared links. This is similar to the behavior of 9484 `secondary_def' symbols. 9485 9486 `common' provides Fortran named common support. It is only useful 9487 for data subspaces. Symbols with the flag `is_common' retain this 9488 flag in shared links. Referencing a `is_common' symbol in a shared 9489 library from outside the library doesn't work. Thus, `is_common' 9490 symbols must be output whenever they are needed. 9491 9492 `common' and `dup_comm' together provide Cobol common support. 9493 The subspaces in this case must all be the same length. 9494 Otherwise, this support is similar to the Fortran common support. 9495 9496 `dup_comm' by itself provides a type of one-only support for code. 9497 Only the first `dup_comm' subspace is selected. There is a rather 9498 complex algorithm to compare subspaces. Code symbols marked with 9499 the `dup_common' flag are hidden. This support was intended for 9500 "C++ duplicate inlines". 9501 9502 A simplified technique is used to mark the flags of symbols based 9503 on the flags of their subspace. A symbol with the scope 9504 SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with 9505 the corresponding settings of `comdat', `common' and `dup_comm' 9506 from the subspace, respectively. This avoids having to introduce 9507 additional directives to mark these symbols. The HP assembler 9508 sets `is_common' from `common'. However, it doesn't set the 9509 `dup_common' from `dup_comm'. It doesn't have `comdat' support. 9510 9511`.version "STR"' 9512 Write STR as version identifier in object code. 9513 9514 9515File: as.info, Node: HPPA Opcodes, Prev: HPPA Directives, Up: HPPA-Dependent 9516 95179.11.6 Opcodes 9518-------------- 9519 9520For detailed information on the HPPA machine instruction set, see 9521`PA-RISC Architecture and Instruction Set Reference Manual' (HP 952209740-90039). 9523 9524 9525File: as.info, Node: ESA/390-Dependent, Next: i386-Dependent, Prev: HPPA-Dependent, Up: Machine Dependencies 9526 95279.12 ESA/390 Dependent Features 9528=============================== 9529 9530* Menu: 9531 9532* ESA/390 Notes:: Notes 9533* ESA/390 Options:: Options 9534* ESA/390 Syntax:: Syntax 9535* ESA/390 Floating Point:: Floating Point 9536* ESA/390 Directives:: ESA/390 Machine Directives 9537* ESA/390 Opcodes:: Opcodes 9538 9539 9540File: as.info, Node: ESA/390 Notes, Next: ESA/390 Options, Up: ESA/390-Dependent 9541 95429.12.1 Notes 9543------------ 9544 9545The ESA/390 `as' port is currently intended to be a back-end for the 9546GNU CC compiler. It is not HLASM compatible, although it does support 9547a subset of some of the HLASM directives. The only supported binary 9548file format is ELF; none of the usual MVS/VM/OE/USS object file 9549formats, such as ESD or XSD, are supported. 9550 9551 When used with the GNU CC compiler, the ESA/390 `as' will produce 9552correct, fully relocated, functional binaries, and has been used to 9553compile and execute large projects. However, many aspects should still 9554be considered experimental; these include shared library support, 9555dynamically loadable objects, and any relocation other than the 31-bit 9556relocation. 9557 9558 9559File: as.info, Node: ESA/390 Options, Next: ESA/390 Syntax, Prev: ESA/390 Notes, Up: ESA/390-Dependent 9560 95619.12.2 Options 9562-------------- 9563 9564`as' has no machine-dependent command-line options for the ESA/390. 9565 9566 9567File: as.info, Node: ESA/390 Syntax, Next: ESA/390 Floating Point, Prev: ESA/390 Options, Up: ESA/390-Dependent 9568 95699.12.3 Syntax 9570------------- 9571 9572The opcode/operand syntax follows the ESA/390 Principles of Operation 9573manual; assembler directives and general syntax are loosely based on the 9574prevailing AT&T/SVR4/ELF/Solaris style notation. HLASM-style directives 9575are _not_ supported for the most part, with the exception of those 9576described herein. 9577 9578 A leading dot in front of directives is optional, and the case of 9579directives is ignored; thus for example, .using and USING have the same 9580effect. 9581 9582 A colon may immediately follow a label definition. This is simply 9583for compatibility with how most assembly language programmers write 9584code. 9585 9586 `#' is the line comment character. 9587 9588 `;' can be used instead of a newline to separate statements. 9589 9590 Since `$' has no special meaning, you may use it in symbol names. 9591 9592 Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, 9593fp6. By using thesse symbolic names, `as' can detect simple syntax 9594errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for 9595r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base 9596for r3 and rpgt or r.pgt for r4. 9597 9598 `*' is the current location counter. Unlike `.' it is always 9599relative to the last USING directive. Note that this means that 9600expressions cannot use multiplication, as any occurrence of `*' will be 9601interpreted as a location counter. 9602 9603 All labels are relative to the last USING. Thus, branches to a label 9604always imply the use of base+displacement. 9605 9606 Many of the usual forms of address constants / address literals are 9607supported. Thus, 9608 .using *,r3 9609 L r15,=A(some_routine) 9610 LM r6,r7,=V(some_longlong_extern) 9611 A r1,=F'12' 9612 AH r0,=H'42' 9613 ME r6,=E'3.1416' 9614 MD r6,=D'3.14159265358979' 9615 O r6,=XL4'cacad0d0' 9616 .ltorg 9617 should all behave as expected: that is, an entry in the literal pool 9618will be created (or reused if it already exists), and the instruction 9619operands will be the displacement into the literal pool using the 9620current base register (as last declared with the `.using' directive). 9621 9622 9623File: as.info, Node: ESA/390 Floating Point, Next: ESA/390 Directives, Prev: ESA/390 Syntax, Up: ESA/390-Dependent 9624 96259.12.4 Floating Point 9626--------------------- 9627 9628The assembler generates only IEEE floating-point numbers. The older 9629floating point formats are not supported. 9630 9631 9632File: as.info, Node: ESA/390 Directives, Next: ESA/390 Opcodes, Prev: ESA/390 Floating Point, Up: ESA/390-Dependent 9633 96349.12.5 ESA/390 Assembler Directives 9635----------------------------------- 9636 9637`as' for the ESA/390 supports all of the standard ELF/SVR4 assembler 9638directives that are documented in the main part of this documentation. 9639Several additional directives are supported in order to implement the 9640ESA/390 addressing model. The most important of these are `.using' and 9641`.ltorg' 9642 9643 These are the additional directives in `as' for the ESA/390: 9644 9645`.dc' 9646 A small subset of the usual DC directive is supported. 9647 9648`.drop REGNO' 9649 Stop using REGNO as the base register. The REGNO must have been 9650 previously declared with a `.using' directive in the same section 9651 as the current section. 9652 9653`.ebcdic STRING' 9654 Emit the EBCDIC equivalent of the indicated string. The emitted 9655 string will be null terminated. Note that the directives 9656 `.string' etc. emit ascii strings by default. 9657 9658`EQU' 9659 The standard HLASM-style EQU directive is not supported; however, 9660 the standard `as' directive .equ can be used to the same effect. 9661 9662`.ltorg' 9663 Dump the literal pool accumulated so far; begin a new literal pool. 9664 The literal pool will be written in the current section; in order 9665 to generate correct assembly, a `.using' must have been previously 9666 specified in the same section. 9667 9668`.using EXPR,REGNO' 9669 Use REGNO as the base register for all subsequent RX, RS, and SS 9670 form instructions. The EXPR will be evaluated to obtain the base 9671 address; usually, EXPR will merely be `*'. 9672 9673 This assembler allows two `.using' directives to be simultaneously 9674 outstanding, one in the `.text' section, and one in another section 9675 (typically, the `.data' section). This feature allows dynamically 9676 loaded objects to be implemented in a relatively straightforward 9677 way. A `.using' directive must always be specified in the `.text' 9678 section; this will specify the base register that will be used for 9679 branches in the `.text' section. A second `.using' may be 9680 specified in another section; this will specify the base register 9681 that is used for non-label address literals. When a second 9682 `.using' is specified, then the subsequent `.ltorg' must be put in 9683 the same section; otherwise an error will result. 9684 9685 Thus, for example, the following code uses `r3' to address branch 9686 targets and `r4' to address the literal pool, which has been 9687 written to the `.data' section. The is, the constants 9688 `=A(some_routine)', `=H'42'' and `=E'3.1416'' will all appear in 9689 the `.data' section. 9690 9691 .data 9692 .using LITPOOL,r4 9693 .text 9694 BASR r3,0 9695 .using *,r3 9696 B START 9697 .long LITPOOL 9698 START: 9699 L r4,4(,r3) 9700 L r15,=A(some_routine) 9701 LTR r15,r15 9702 BNE LABEL 9703 AH r0,=H'42' 9704 LABEL: 9705 ME r6,=E'3.1416' 9706 .data 9707 LITPOOL: 9708 .ltorg 9709 9710 Note that this dual-`.using' directive semantics extends and is 9711 not compatible with HLASM semantics. Note that this assembler 9712 directive does not support the full range of HLASM semantics. 9713 9714 9715 9716File: as.info, Node: ESA/390 Opcodes, Prev: ESA/390 Directives, Up: ESA/390-Dependent 9717 97189.12.6 Opcodes 9719-------------- 9720 9721For detailed information on the ESA/390 machine instruction set, see 9722`ESA/390 Principles of Operation' (IBM Publication Number DZ9AR004). 9723 9724 9725File: as.info, Node: i386-Dependent, Next: i860-Dependent, Prev: ESA/390-Dependent, Up: Machine Dependencies 9726 97279.13 80386 Dependent Features 9728============================= 9729 9730 The i386 version `as' supports both the original Intel 386 9731architecture in both 16 and 32-bit mode as well as AMD x86-64 9732architecture extending the Intel architecture to 64-bits. 9733 9734* Menu: 9735 9736* i386-Options:: Options 9737* i386-Directives:: X86 specific directives 9738* i386-Syntax:: Syntactical considerations 9739* i386-Mnemonics:: Instruction Naming 9740* i386-Regs:: Register Naming 9741* i386-Prefixes:: Instruction Prefixes 9742* i386-Memory:: Memory References 9743* i386-Jumps:: Handling of Jump Instructions 9744* i386-Float:: Floating Point 9745* i386-SIMD:: Intel's MMX and AMD's 3DNow! SIMD Operations 9746* i386-LWP:: AMD's Lightweight Profiling Instructions 9747* i386-BMI:: Bit Manipulation Instruction 9748* i386-TBM:: AMD's Trailing Bit Manipulation Instructions 9749* i386-16bit:: Writing 16-bit Code 9750* i386-Arch:: Specifying an x86 CPU architecture 9751* i386-Bugs:: AT&T Syntax bugs 9752* i386-Notes:: Notes 9753 9754 9755File: as.info, Node: i386-Options, Next: i386-Directives, Up: i386-Dependent 9756 97579.13.1 Options 9758-------------- 9759 9760The i386 version of `as' has a few machine dependent options: 9761 9762`--32 | --x32 | --64' 9763 Select the word size, either 32 bits or 64 bits. `--32' implies 9764 Intel i386 architecture, while `--x32' and `--64' imply AMD x86-64 9765 architecture with 32-bit or 64-bit word-size respectively. 9766 9767 These options are only available with the ELF object file format, 9768 and require that the necessary BFD support has been included (on a 9769 32-bit platform you have to add -enable-64-bit-bfd to configure 9770 enable 64-bit usage and use x86-64 as target platform). 9771 9772`-n' 9773 By default, x86 GAS replaces multiple nop instructions used for 9774 alignment within code sections with multi-byte nop instructions 9775 such as leal 0(%esi,1),%esi. This switch disables the 9776 optimization. 9777 9778`--divide' 9779 On SVR4-derived platforms, the character `/' is treated as a 9780 comment character, which means that it cannot be used in 9781 expressions. The `--divide' option turns `/' into a normal 9782 character. This does not disable `/' at the beginning of a line 9783 starting a comment, or affect using `#' for starting a comment. 9784 9785`-march=CPU[+EXTENSION...]' 9786 This option specifies the target processor. The assembler will 9787 issue an error message if an attempt is made to assemble an 9788 instruction which will not execute on the target processor. The 9789 following processor names are recognized: `i8086', `i186', `i286', 9790 `i386', `i486', `i586', `i686', `pentium', `pentiumpro', 9791 `pentiumii', `pentiumiii', `pentium4', `prescott', `nocona', 9792 `core', `core2', `corei7', `l1om', `k1om', `k6', `k6_2', `athlon', 9793 `opteron', `k8', `amdfam10', `bdver1', `bdver2', `generic32' and 9794 `generic64'. 9795 9796 In addition to the basic instruction set, the assembler can be 9797 told to accept various extension mnemonics. For example, 9798 `-march=i686+sse4+vmx' extends I686 with SSE4 and VMX. The 9799 following extensions are currently supported: `8087', `287', `387', 9800 `no87', `mmx', `nommx', `sse', `sse2', `sse3', `ssse3', `sse4.1', 9801 `sse4.2', `sse4', `nosse', `avx', `avx2', `noavx', `vmx', `smx', 9802 `xsave', `xsaveopt', `aes', `pclmul', `fsgsbase', `rdrnd', `f16c', 9803 `bmi2', `fma', `movbe', `ept', `lzcnt', `invpcid', `clflush', 9804 `lwp', `fma4', `xop', `syscall', `rdtscp', `3dnow', `3dnowa', 9805 `sse4a', `sse5', `svme', `abm' and `padlock'. Note that rather 9806 than extending a basic instruction set, the extension mnemonics 9807 starting with `no' revoke the respective functionality. 9808 9809 When the `.arch' directive is used with `-march', the `.arch' 9810 directive will take precedent. 9811 9812`-mtune=CPU' 9813 This option specifies a processor to optimize for. When used in 9814 conjunction with the `-march' option, only instructions of the 9815 processor specified by the `-march' option will be generated. 9816 9817 Valid CPU values are identical to the processor list of 9818 `-march=CPU'. 9819 9820`-msse2avx' 9821 This option specifies that the assembler should encode SSE 9822 instructions with VEX prefix. 9823 9824`-msse-check=NONE' 9825`-msse-check=WARNING' 9826`-msse-check=ERROR' 9827 These options control if the assembler should check SSE 9828 intructions. `-msse-check=NONE' will make the assembler not to 9829 check SSE instructions, which is the default. 9830 `-msse-check=WARNING' will make the assembler issue a warning for 9831 any SSE intruction. `-msse-check=ERROR' will make the assembler 9832 issue an error for any SSE intruction. 9833 9834`-mavxscalar=128' 9835`-mavxscalar=256' 9836 These options control how the assembler should encode scalar AVX 9837 instructions. `-mavxscalar=128' will encode scalar AVX 9838 instructions with 128bit vector length, which is the default. 9839 `-mavxscalar=256' will encode scalar AVX instructions with 256bit 9840 vector length. 9841 9842`-mmnemonic=ATT' 9843`-mmnemonic=INTEL' 9844 This option specifies instruction mnemonic for matching 9845 instructions. The `.att_mnemonic' and `.intel_mnemonic' 9846 directives will take precedent. 9847 9848`-msyntax=ATT' 9849`-msyntax=INTEL' 9850 This option specifies instruction syntax when processing 9851 instructions. The `.att_syntax' and `.intel_syntax' directives 9852 will take precedent. 9853 9854`-mnaked-reg' 9855 This opetion specifies that registers don't require a `%' prefix. 9856 The `.att_syntax' and `.intel_syntax' directives will take 9857 precedent. 9858 9859 9860 9861File: as.info, Node: i386-Directives, Next: i386-Syntax, Prev: i386-Options, Up: i386-Dependent 9862 98639.13.2 x86 specific Directives 9864------------------------------ 9865 9866`.lcomm SYMBOL , LENGTH[, ALIGNMENT]' 9867 Reserve LENGTH (an absolute expression) bytes for a local common 9868 denoted by SYMBOL. The section and value of SYMBOL are those of 9869 the new local common. The addresses are allocated in the bss 9870 section, so that at run-time the bytes start off zeroed. Since 9871 SYMBOL is not declared global, it is normally not visible to `ld'. 9872 The optional third parameter, ALIGNMENT, specifies the desired 9873 alignment of the symbol in the bss section. 9874 9875 This directive is only available for COFF based x86 targets. 9876 9877 9878 9879File: as.info, Node: i386-Syntax, Next: i386-Mnemonics, Prev: i386-Directives, Up: i386-Dependent 9880 98819.13.3 i386 Syntactical Considerations 9882-------------------------------------- 9883 9884* Menu: 9885 9886* i386-Variations:: AT&T Syntax versus Intel Syntax 9887* i386-Chars:: Special Characters 9888 9889 9890File: as.info, Node: i386-Variations, Next: i386-Chars, Up: i386-Syntax 9891 98929.13.3.1 AT&T Syntax versus Intel Syntax 9893........................................ 9894 9895`as' now supports assembly using Intel assembler syntax. 9896`.intel_syntax' selects Intel mode, and `.att_syntax' switches back to 9897the usual AT&T mode for compatibility with the output of `gcc'. Either 9898of these directives may have an optional argument, `prefix', or 9899`noprefix' specifying whether registers require a `%' prefix. AT&T 9900System V/386 assembler syntax is quite different from Intel syntax. We 9901mention these differences because almost all 80386 documents use Intel 9902syntax. Notable differences between the two syntaxes are: 9903 9904 * AT&T immediate operands are preceded by `$'; Intel immediate 9905 operands are undelimited (Intel `push 4' is AT&T `pushl $4'). 9906 AT&T register operands are preceded by `%'; Intel register operands 9907 are undelimited. AT&T absolute (as opposed to PC relative) 9908 jump/call operands are prefixed by `*'; they are undelimited in 9909 Intel syntax. 9910 9911 * AT&T and Intel syntax use the opposite order for source and 9912 destination operands. Intel `add eax, 4' is `addl $4, %eax'. The 9913 `source, dest' convention is maintained for compatibility with 9914 previous Unix assemblers. Note that `bound', `invlpga', and 9915 instructions with 2 immediate operands, such as the `enter' 9916 instruction, do _not_ have reversed order. *note i386-Bugs::. 9917 9918 * In AT&T syntax the size of memory operands is determined from the 9919 last character of the instruction mnemonic. Mnemonic suffixes of 9920 `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long 9921 (32-bit) and quadruple word (64-bit) memory references. Intel 9922 syntax accomplishes this by prefixing memory operands (_not_ the 9923 instruction mnemonics) with `byte ptr', `word ptr', `dword ptr' 9924 and `qword ptr'. Thus, Intel `mov al, byte ptr FOO' is `movb FOO, 9925 %al' in AT&T syntax. 9926 9927 In 64-bit code, `movabs' can be used to encode the `mov' 9928 instruction with the 64-bit displacement or immediate operand. 9929 9930 * Immediate form long jumps and calls are `lcall/ljmp $SECTION, 9931 $OFFSET' in AT&T syntax; the Intel syntax is `call/jmp far 9932 SECTION:OFFSET'. Also, the far return instruction is `lret 9933 $STACK-ADJUST' in AT&T syntax; Intel syntax is `ret far 9934 STACK-ADJUST'. 9935 9936 * The AT&T assembler does not provide support for multiple section 9937 programs. Unix style systems expect all programs to be single 9938 sections. 9939 9940 9941File: as.info, Node: i386-Chars, Prev: i386-Variations, Up: i386-Syntax 9942 99439.13.3.2 Special Characters 9944........................... 9945 9946The presence of a `#' appearing anywhere on a line indicates the start 9947of a comment that extends to the end of that line. 9948 9949 If a `#' appears as the first character of a line then the whole 9950line is treated as a comment, but in this case the line can also be a 9951logical line number directive (*note Comments::) or a preprocessor 9952control command (*note Preprocessing::). 9953 9954 If the `--divide' command line option has not been specified then 9955the `/' character appearing anywhere on a line also introduces a line 9956comment. 9957 9958 The `;' character can be used to separate statements on the same 9959line. 9960 9961 9962File: as.info, Node: i386-Mnemonics, Next: i386-Regs, Prev: i386-Syntax, Up: i386-Dependent 9963 99649.13.4 Instruction Naming 9965------------------------- 9966 9967Instruction mnemonics are suffixed with one character modifiers which 9968specify the size of operands. The letters `b', `w', `l' and `q' 9969specify byte, word, long and quadruple word operands. If no suffix is 9970specified by an instruction then `as' tries to fill in the missing 9971suffix based on the destination register operand (the last one by 9972convention). Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx'; 9973also, `mov $1, %bx' is equivalent to `movw $1, bx'. Note that this is 9974incompatible with the AT&T Unix assembler which assumes that a missing 9975mnemonic suffix implies long operand size. (This incompatibility does 9976not affect compiler output since compilers always explicitly specify 9977the mnemonic suffix.) 9978 9979 Almost all instructions have the same names in AT&T and Intel format. 9980There are a few exceptions. The sign extend and zero extend 9981instructions need two sizes to specify them. They need a size to 9982sign/zero extend _from_ and a size to zero extend _to_. This is 9983accomplished by using two instruction mnemonic suffixes in AT&T syntax. 9984Base names for sign extend and zero extend are `movs...' and `movz...' 9985in AT&T syntax (`movsx' and `movzx' in Intel syntax). The instruction 9986mnemonic suffixes are tacked on to this base name, the _from_ suffix 9987before the _to_ suffix. Thus, `movsbl %al, %edx' is AT&T syntax for 9988"move sign extend _from_ %al _to_ %edx." Possible suffixes, thus, are 9989`bl' (from byte to long), `bw' (from byte to word), `wl' (from word to 9990long), `bq' (from byte to quadruple word), `wq' (from word to quadruple 9991word), and `lq' (from long to quadruple word). 9992 9993 Different encoding options can be specified via optional mnemonic 9994suffix. `.s' suffix swaps 2 register operands in encoding when moving 9995from one register to another. `.d32' suffix forces 32bit displacement 9996in encoding. 9997 9998 The Intel-syntax conversion instructions 9999 10000 * `cbw' -- sign-extend byte in `%al' to word in `%ax', 10001 10002 * `cwde' -- sign-extend word in `%ax' to long in `%eax', 10003 10004 * `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax', 10005 10006 * `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax', 10007 10008 * `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64 10009 only), 10010 10011 * `cqo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax' 10012 (x86-64 only), 10013 10014are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T 10015naming. `as' accepts either naming for these instructions. 10016 10017 Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax, 10018but are `call far' and `jump far' in Intel convention. 10019 100209.13.5 AT&T Mnemonic versus Intel Mnemonic 10021------------------------------------------ 10022 10023`as' supports assembly using Intel mnemonic. `.intel_mnemonic' selects 10024Intel mnemonic with Intel syntax, and `.att_mnemonic' switches back to 10025the usual AT&T mnemonic with AT&T syntax for compatibility with the 10026output of `gcc'. Several x87 instructions, `fadd', `fdiv', `fdivp', 10027`fdivr', `fdivrp', `fmul', `fsub', `fsubp', `fsubr' and `fsubrp', are 10028implemented in AT&T System V/386 assembler with different mnemonics 10029from those in Intel IA32 specification. `gcc' generates those 10030instructions with AT&T mnemonic. 10031 10032 10033File: as.info, Node: i386-Regs, Next: i386-Prefixes, Prev: i386-Mnemonics, Up: i386-Dependent 10034 100359.13.6 Register Naming 10036---------------------- 10037 10038Register operands are always prefixed with `%'. The 80386 registers 10039consist of 10040 10041 * the 8 32-bit registers `%eax' (the accumulator), `%ebx', `%ecx', 10042 `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp' 10043 (the stack pointer). 10044 10045 * the 8 16-bit low-ends of these: `%ax', `%bx', `%cx', `%dx', `%di', 10046 `%si', `%bp', and `%sp'. 10047 10048 * the 8 8-bit registers: `%ah', `%al', `%bh', `%bl', `%ch', `%cl', 10049 `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax', 10050 `%bx', `%cx', and `%dx') 10051 10052 * the 6 section registers `%cs' (code section), `%ds' (data 10053 section), `%ss' (stack section), `%es', `%fs', and `%gs'. 10054 10055 * the 3 processor control registers `%cr0', `%cr2', and `%cr3'. 10056 10057 * the 6 debug registers `%db0', `%db1', `%db2', `%db3', `%db6', and 10058 `%db7'. 10059 10060 * the 2 test registers `%tr6' and `%tr7'. 10061 10062 * the 8 floating point register stack `%st' or equivalently 10063 `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)', 10064 `%st(6)', and `%st(7)'. These registers are overloaded by 8 MMX 10065 registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6' 10066 and `%mm7'. 10067 10068 * the 8 SSE registers registers `%xmm0', `%xmm1', `%xmm2', `%xmm3', 10069 `%xmm4', `%xmm5', `%xmm6' and `%xmm7'. 10070 10071 The AMD x86-64 architecture extends the register set by: 10072 10073 * enhancing the 8 32-bit registers to 64-bit: `%rax' (the 10074 accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the 10075 frame pointer), `%rsp' (the stack pointer) 10076 10077 * the 8 extended registers `%r8'-`%r15'. 10078 10079 * the 8 32-bit low ends of the extended registers: `%r8d'-`%r15d' 10080 10081 * the 8 16-bit low ends of the extended registers: `%r8w'-`%r15w' 10082 10083 * the 8 8-bit low ends of the extended registers: `%r8b'-`%r15b' 10084 10085 * the 4 8-bit registers: `%sil', `%dil', `%bpl', `%spl'. 10086 10087 * the 8 debug registers: `%db8'-`%db15'. 10088 10089 * the 8 SSE registers: `%xmm8'-`%xmm15'. 10090 10091 10092File: as.info, Node: i386-Prefixes, Next: i386-Memory, Prev: i386-Regs, Up: i386-Dependent 10093 100949.13.7 Instruction Prefixes 10095--------------------------- 10096 10097Instruction prefixes are used to modify the following instruction. They 10098are used to repeat string instructions, to provide section overrides, to 10099perform bus lock operations, and to change operand and address sizes. 10100(Most instructions that normally operate on 32-bit operands will use 1010116-bit operands if the instruction has an "operand size" prefix.) 10102Instruction prefixes are best written on the same line as the 10103instruction they act upon. For example, the `scas' (scan string) 10104instruction is repeated with: 10105 10106 repne scas %es:(%edi),%al 10107 10108 You may also place prefixes on the lines immediately preceding the 10109instruction, but this circumvents checks that `as' does with prefixes, 10110and will not work with all prefixes. 10111 10112 Here is a list of instruction prefixes: 10113 10114 * Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'. 10115 These are automatically added by specifying using the 10116 SECTION:MEMORY-OPERAND form for memory references. 10117 10118 * Operand/Address size prefixes `data16' and `addr16' change 32-bit 10119 operands/addresses into 16-bit operands/addresses, while `data32' 10120 and `addr32' change 16-bit ones (in a `.code16' section) into 10121 32-bit operands/addresses. These prefixes _must_ appear on the 10122 same line of code as the instruction they modify. For example, in 10123 a 16-bit `.code16' section, you might write: 10124 10125 addr32 jmpl *(%ebx) 10126 10127 * The bus lock prefix `lock' inhibits interrupts during execution of 10128 the instruction it precedes. (This is only valid with certain 10129 instructions; see a 80386 manual for details). 10130 10131 * The wait for coprocessor prefix `wait' waits for the coprocessor to 10132 complete the current instruction. This should never be needed for 10133 the 80386/80387 combination. 10134 10135 * The `rep', `repe', and `repne' prefixes are added to string 10136 instructions to make them repeat `%ecx' times (`%cx' times if the 10137 current address size is 16-bits). 10138 10139 * The `rex' family of prefixes is used by x86-64 to encode 10140 extensions to i386 instruction set. The `rex' prefix has four 10141 bits -- an operand size overwrite (`64') used to change operand 10142 size from 32-bit to 64-bit and X, Y and Z extensions bits used to 10143 extend the register set. 10144 10145 You may write the `rex' prefixes directly. The `rex64xyz' 10146 instruction emits `rex' prefix with all the bits set. By omitting 10147 the `64', `x', `y' or `z' you may write other prefixes as well. 10148 Normally, there is no need to write the prefixes explicitly, since 10149 gas will automatically generate them based on the instruction 10150 operands. 10151 10152 10153File: as.info, Node: i386-Memory, Next: i386-Jumps, Prev: i386-Prefixes, Up: i386-Dependent 10154 101559.13.8 Memory References 10156------------------------ 10157 10158An Intel syntax indirect memory reference of the form 10159 10160 SECTION:[BASE + INDEX*SCALE + DISP] 10161 10162is translated into the AT&T syntax 10163 10164 SECTION:DISP(BASE, INDEX, SCALE) 10165 10166where BASE and INDEX are the optional 32-bit base and index registers, 10167DISP is the optional displacement, and SCALE, taking the values 1, 2, 101684, and 8, multiplies INDEX to calculate the address of the operand. If 10169no SCALE is specified, SCALE is taken to be 1. SECTION specifies the 10170optional section register for the memory operand, and may override the 10171default section register (see a 80386 manual for section register 10172defaults). Note that section overrides in AT&T syntax _must_ be 10173preceded by a `%'. If you specify a section override which coincides 10174with the default section register, `as' does _not_ output any section 10175register override prefixes to assemble the given instruction. Thus, 10176section overrides can be specified to emphasize which section register 10177is used for a given memory operand. 10178 10179 Here are some examples of Intel and AT&T style memory references: 10180 10181AT&T: `-4(%ebp)', Intel: `[ebp - 4]' 10182 BASE is `%ebp'; DISP is `-4'. SECTION is missing, and the default 10183 section is used (`%ss' for addressing with `%ebp' as the base 10184 register). INDEX, SCALE are both missing. 10185 10186AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]' 10187 INDEX is `%eax' (scaled by a SCALE 4); DISP is `foo'. All other 10188 fields are missing. The section register here defaults to `%ds'. 10189 10190AT&T: `foo(,1)'; Intel `[foo]' 10191 This uses the value pointed to by `foo' as a memory operand. Note 10192 that BASE and INDEX are both missing, but there is only _one_ `,'. 10193 This is a syntactic exception. 10194 10195AT&T: `%gs:foo'; Intel `gs:foo' 10196 This selects the contents of the variable `foo' with section 10197 register SECTION being `%gs'. 10198 10199 Absolute (as opposed to PC relative) call and jump operands must be 10200prefixed with `*'. If no `*' is specified, `as' always chooses PC 10201relative addressing for jump/call labels. 10202 10203 Any instruction that has a memory operand, but no register operand, 10204_must_ specify its size (byte, word, long, or quadruple) with an 10205instruction mnemonic suffix (`b', `w', `l' or `q', respectively). 10206 10207 The x86-64 architecture adds an RIP (instruction pointer relative) 10208addressing. This addressing mode is specified by using `rip' as a base 10209register. Only constant offsets are valid. For example: 10210 10211AT&T: `1234(%rip)', Intel: `[rip + 1234]' 10212 Points to the address 1234 bytes past the end of the current 10213 instruction. 10214 10215AT&T: `symbol(%rip)', Intel: `[rip + symbol]' 10216 Points to the `symbol' in RIP relative way, this is shorter than 10217 the default absolute addressing. 10218 10219 Other addressing modes remain unchanged in x86-64 architecture, 10220except registers used are 64-bit instead of 32-bit. 10221 10222 10223File: as.info, Node: i386-Jumps, Next: i386-Float, Prev: i386-Memory, Up: i386-Dependent 10224 102259.13.9 Handling of Jump Instructions 10226------------------------------------ 10227 10228Jump instructions are always optimized to use the smallest possible 10229displacements. This is accomplished by using byte (8-bit) displacement 10230jumps whenever the target is sufficiently close. If a byte displacement 10231is insufficient a long displacement is used. We do not support word 10232(16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump 10233instruction with the `data16' instruction prefix), since the 80386 10234insists upon masking `%eip' to 16 bits after the word displacement is 10235added. (See also *note i386-Arch::) 10236 10237 Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz' 10238and `loopne' instructions only come in byte displacements, so that if 10239you use these instructions (`gcc' does not use them) you may get an 10240error message (and incorrect code). The AT&T 80386 assembler tries to 10241get around this problem by expanding `jcxz foo' to 10242 10243 jcxz cx_zero 10244 jmp cx_nonzero 10245 cx_zero: jmp foo 10246 cx_nonzero: 10247 10248 10249File: as.info, Node: i386-Float, Next: i386-SIMD, Prev: i386-Jumps, Up: i386-Dependent 10250 102519.13.10 Floating Point 10252---------------------- 10253 10254All 80387 floating point types except packed BCD are supported. (BCD 10255support may be added without much difficulty). These data types are 1025616-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), 10257and extended (80-bit) precision floating point. Each supported type 10258has an instruction mnemonic suffix and a constructor associated with 10259it. Instruction mnemonic suffixes specify the operand's data type. 10260Constructors build these data types into memory. 10261 10262 * Floating point constructors are `.float' or `.single', `.double', 10263 and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond 10264 to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for 10265 80-bit (ten byte) real. The 80387 only supports this format via 10266 the `fldt' (load 80-bit real to stack top) and `fstpt' (store 10267 80-bit real and pop stack) instructions. 10268 10269 * Integer constructors are `.word', `.long' or `.int', and `.quad' 10270 for the 16-, 32-, and 64-bit integer formats. The corresponding 10271 instruction mnemonic suffixes are `s' (single), `l' (long), and 10272 `q' (quad). As with the 80-bit real format, the 64-bit `q' format 10273 is only present in the `fildq' (load quad integer to stack top) 10274 and `fistpq' (store quad integer and pop stack) instructions. 10275 10276 Register to register operations should not use instruction mnemonic 10277suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as 10278if you wrote `fst %st, %st(1)', since all register to register 10279operations use 80-bit floating point operands. (Contrast this with 10280`fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating 10281point format, then stores the result in the 4 byte location `mem') 10282 10283 10284File: as.info, Node: i386-SIMD, Next: i386-LWP, Prev: i386-Float, Up: i386-Dependent 10285 102869.13.11 Intel's MMX and AMD's 3DNow! SIMD Operations 10287---------------------------------------------------- 10288 10289`as' supports Intel's MMX instruction set (SIMD instructions for 10290integer data), available on Intel's Pentium MMX processors and Pentium 10291II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and 10292probably others. It also supports AMD's 3DNow! instruction set (SIMD 10293instructions for 32-bit floating point data) available on AMD's K6-2 10294processor and possibly others in the future. 10295 10296 Currently, `as' does not support Intel's floating point SIMD, Katmai 10297(KNI). 10298 10299 The eight 64-bit MMX operands, also used by 3DNow!, are called 10300`%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four 1030116-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit 10302floating point values. The MMX registers cannot be used at the same 10303time as the floating point stack. 10304 10305 See Intel and AMD documentation, keeping in mind that the operand 10306order in instructions is reversed from the Intel syntax. 10307 10308 10309File: as.info, Node: i386-LWP, Next: i386-BMI, Prev: i386-SIMD, Up: i386-Dependent 10310 103119.13.12 AMD's Lightweight Profiling Instructions 10312------------------------------------------------ 10313 10314`as' supports AMD's Lightweight Profiling (LWP) instruction set, 10315available on AMD's Family 15h (Orochi) processors. 10316 10317 LWP enables applications to collect and manage performance data, and 10318react to performance events. The collection of performance data 10319requires no context switches. LWP runs in the context of a thread and 10320so several counters can be used independently across multiple threads. 10321LWP can be used in both 64-bit and legacy 32-bit modes. 10322 10323 For detailed information on the LWP instruction set, see the `AMD 10324Lightweight Profiling Specification' available at Lightweight Profiling 10325Specification (http://developer.amd.com/cpu/LWP). 10326 10327 10328File: as.info, Node: i386-BMI, Next: i386-TBM, Prev: i386-LWP, Up: i386-Dependent 10329 103309.13.13 Bit Manipulation Instructions 10331------------------------------------- 10332 10333`as' supports the Bit Manipulation (BMI) instruction set. 10334 10335 BMI instructions provide several instructions implementing individual 10336bit manipulation operations such as isolation, masking, setting, or 10337resetting. 10338 10339 10340File: as.info, Node: i386-TBM, Next: i386-16bit, Prev: i386-BMI, Up: i386-Dependent 10341 103429.13.14 AMD's Trailing Bit Manipulation Instructions 10343---------------------------------------------------- 10344 10345`as' supports AMD's Trailing Bit Manipulation (TBM) instruction set, 10346available on AMD's BDVER2 processors (Trinity and Viperfish). 10347 10348 TBM instructions provide instructions implementing individual bit 10349manipulation operations such as isolating, masking, setting, resetting, 10350complementing, and operations on trailing zeros and ones. 10351 10352 10353File: as.info, Node: i386-16bit, Next: i386-Arch, Prev: i386-TBM, Up: i386-Dependent 10354 103559.13.15 Writing 16-bit Code 10356--------------------------- 10357 10358While `as' normally writes only "pure" 32-bit i386 code or 64-bit 10359x86-64 code depending on the default configuration, it also supports 10360writing code to run in real mode or in 16-bit protected mode code 10361segments. To do this, put a `.code16' or `.code16gcc' directive before 10362the assembly language instructions to be run in 16-bit mode. You can 10363switch `as' to writing 32-bit code with the `.code32' directive or 1036464-bit code with the `.code64' directive. 10365 10366 `.code16gcc' provides experimental support for generating 16-bit 10367code from gcc, and differs from `.code16' in that `call', `ret', 10368`enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf' 10369instructions default to 32-bit size. This is so that the stack pointer 10370is manipulated in the same way over function calls, allowing access to 10371function parameters at the same stack offsets as in 32-bit mode. 10372`.code16gcc' also automatically adds address size prefixes where 10373necessary to use the 32-bit addressing modes that gcc generates. 10374 10375 The code which `as' generates in 16-bit mode will not necessarily 10376run on a 16-bit pre-80386 processor. To write code that runs on such a 10377processor, you must refrain from using _any_ 32-bit constructs which 10378require `as' to output address or operand size prefixes. 10379 10380 Note that writing 16-bit code instructions by explicitly specifying a 10381prefix or an instruction mnemonic suffix within a 32-bit code section 10382generates different machine instructions than those generated for a 1038316-bit code segment. In a 32-bit code section, the following code 10384generates the machine opcode bytes `66 6a 04', which pushes the value 10385`4' onto the stack, decrementing `%esp' by 2. 10386 10387 pushw $4 10388 10389 The same code in a 16-bit code section would generate the machine 10390opcode bytes `6a 04' (i.e., without the operand size prefix), which is 10391correct since the processor default operand size is assumed to be 16 10392bits in a 16-bit code section. 10393 10394 10395File: as.info, Node: i386-Bugs, Next: i386-Notes, Prev: i386-Arch, Up: i386-Dependent 10396 103979.13.16 AT&T Syntax bugs 10398------------------------ 10399 10400The UnixWare assembler, and probably other AT&T derived ix86 Unix 10401assemblers, generate floating point instructions with reversed source 10402and destination registers in certain cases. Unfortunately, gcc and 10403possibly many other programs use this reversed syntax, so we're stuck 10404with it. 10405 10406 For example 10407 10408 fsub %st,%st(3) 10409 results in `%st(3)' being updated to `%st - %st(3)' rather than the 10410expected `%st(3) - %st'. This happens with all the non-commutative 10411arithmetic floating point operations with two register operands where 10412the source register is `%st' and the destination register is `%st(i)'. 10413 10414 10415File: as.info, Node: i386-Arch, Next: i386-Bugs, Prev: i386-16bit, Up: i386-Dependent 10416 104179.13.17 Specifying CPU Architecture 10418----------------------------------- 10419 10420`as' may be told to assemble for a particular CPU (sub-)architecture 10421with the `.arch CPU_TYPE' directive. This directive enables a warning 10422when gas detects an instruction that is not supported on the CPU 10423specified. The choices for CPU_TYPE are: 10424 10425`i8086' `i186' `i286' `i386' 10426`i486' `i586' `i686' `pentium' 10427`pentiumpro' `pentiumii' `pentiumiii' `pentium4' 10428`prescott' `nocona' `core' `core2' 10429`corei7' `l1om' `k1om' 10430`k6' `k6_2' `athlon' `k8' 10431`amdfam10' `bdver1' `bdver2' 10432`generic32' `generic64' 10433`.mmx' `.sse' `.sse2' `.sse3' 10434`.ssse3' `.sse4.1' `.sse4.2' `.sse4' 10435`.avx' `.vmx' `.smx' `.ept' 10436`.clflush' `.movbe' `.xsave' `.xsaveopt' 10437`.aes' `.pclmul' `.fma' `.fsgsbase' 10438`.rdrnd' `.f16c' `.avx2' `.bmi2' 10439`.lzcnt' `.invpcid' 10440`.3dnow' `.3dnowa' `.sse4a' `.sse5' 10441`.syscall' `.rdtscp' `.svme' `.abm' 10442`.lwp' `.fma4' `.xop' 10443`.padlock' 10444 10445 Apart from the warning, there are only two other effects on `as' 10446operation; Firstly, if you specify a CPU other than `i486', then shift 10447by one instructions such as `sarl $1, %eax' will automatically use a 10448two byte opcode sequence. The larger three byte opcode sequence is 10449used on the 486 (and when no architecture is specified) because it 10450executes faster on the 486. Note that you can explicitly request the 10451two byte opcode by writing `sarl %eax'. Secondly, if you specify 10452`i8086', `i186', or `i286', _and_ `.code16' or `.code16gcc' then byte 10453offset conditional jumps will be promoted when necessary to a two 10454instruction sequence consisting of a conditional jump of the opposite 10455sense around an unconditional jump to the target. 10456 10457 Following the CPU architecture (but not a sub-architecture, which 10458are those starting with a dot), you may specify `jumps' or `nojumps' to 10459control automatic promotion of conditional jumps. `jumps' is the 10460default, and enables jump promotion; All external jumps will be of the 10461long variety, and file-local jumps will be promoted as necessary. 10462(*note i386-Jumps::) `nojumps' leaves external conditional jumps as 10463byte offset jumps, and warns about file-local conditional jumps that 10464`as' promotes. Unconditional jumps are treated as for `jumps'. 10465 10466 For example 10467 10468 .arch i8086,nojumps 10469 10470 10471File: as.info, Node: i386-Notes, Prev: i386-Bugs, Up: i386-Dependent 10472 104739.13.18 Notes 10474------------- 10475 10476There is some trickery concerning the `mul' and `imul' instructions 10477that deserves mention. The 16-, 32-, 64- and 128-bit expanding 10478multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul') 10479can be output only in the one operand form. Thus, `imul %ebx, %eax' 10480does _not_ select the expanding multiply; the expanding multiply would 10481clobber the `%edx' register, and this would confuse `gcc' output. Use 10482`imul %ebx' to get the 64-bit product in `%edx:%eax'. 10483 10484 We have added a two operand form of `imul' when the first operand is 10485an immediate mode expression and the second operand is a register. 10486This is just a shorthand, so that, multiplying `%eax' by 69, for 10487example, can be done with `imul $69, %eax' rather than `imul $69, %eax, 10488%eax'. 10489 10490 10491File: as.info, Node: i860-Dependent, Next: i960-Dependent, Prev: i386-Dependent, Up: Machine Dependencies 10492 104939.14 Intel i860 Dependent Features 10494================================== 10495 10496* Menu: 10497 10498* Notes-i860:: i860 Notes 10499* Options-i860:: i860 Command-line Options 10500* Directives-i860:: i860 Machine Directives 10501* Opcodes for i860:: i860 Opcodes 10502* Syntax of i860:: i860 Syntax 10503 10504 10505File: as.info, Node: Notes-i860, Next: Options-i860, Up: i860-Dependent 10506 105079.14.1 i860 Notes 10508----------------- 10509 10510This is a fairly complete i860 assembler which is compatible with the 10511UNIX System V/860 Release 4 assembler. However, it does not currently 10512support SVR4 PIC (i.e., `@GOT, @GOTOFF, @PLT'). 10513 10514 Like the SVR4/860 assembler, the output object format is ELF32. 10515Currently, this is the only supported object format. If there is 10516sufficient interest, other formats such as COFF may be implemented. 10517 10518 Both the Intel and AT&T/SVR4 syntaxes are supported, with the latter 10519being the default. One difference is that AT&T syntax requires the '%' 10520prefix on register names while Intel syntax does not. Another 10521difference is in the specification of relocatable expressions. The 10522Intel syntax is `ha%expression' whereas the SVR4 syntax is 10523`[expression]@ha' (and similarly for the "l" and "h" selectors). 10524 10525 10526File: as.info, Node: Options-i860, Next: Directives-i860, Prev: Notes-i860, Up: i860-Dependent 10527 105289.14.2 i860 Command-line Options 10529-------------------------------- 10530 105319.14.2.1 SVR4 compatibility options 10532................................... 10533 10534`-V' 10535 Print assembler version. 10536 10537`-Qy' 10538 Ignored. 10539 10540`-Qn' 10541 Ignored. 10542 105439.14.2.2 Other options 10544...................... 10545 10546`-EL' 10547 Select little endian output (this is the default). 10548 10549`-EB' 10550 Select big endian output. Note that the i860 always reads 10551 instructions as little endian data, so this option only effects 10552 data and not instructions. 10553 10554`-mwarn-expand' 10555 Emit a warning message if any pseudo-instruction expansions 10556 occurred. For example, a `or' instruction with an immediate 10557 larger than 16-bits will be expanded into two instructions. This 10558 is a very undesirable feature to rely on, so this flag can help 10559 detect any code where it happens. One use of it, for instance, has 10560 been to find and eliminate any place where `gcc' may emit these 10561 pseudo-instructions. 10562 10563`-mxp' 10564 Enable support for the i860XP instructions and control registers. 10565 By default, this option is disabled so that only the base 10566 instruction set (i.e., i860XR) is supported. 10567 10568`-mintel-syntax' 10569 The i860 assembler defaults to AT&T/SVR4 syntax. This option 10570 enables the Intel syntax. 10571 10572 10573File: as.info, Node: Directives-i860, Next: Opcodes for i860, Prev: Options-i860, Up: i860-Dependent 10574 105759.14.3 i860 Machine Directives 10576------------------------------ 10577 10578`.dual' 10579 Enter dual instruction mode. While this directive is supported, the 10580 preferred way to use dual instruction mode is to explicitly code 10581 the dual bit with the `d.' prefix. 10582 10583`.enddual' 10584 Exit dual instruction mode. While this directive is supported, the 10585 preferred way to use dual instruction mode is to explicitly code 10586 the dual bit with the `d.' prefix. 10587 10588`.atmp' 10589 Change the temporary register used when expanding pseudo 10590 operations. The default register is `r31'. 10591 10592 The `.dual', `.enddual', and `.atmp' directives are available only 10593in the Intel syntax mode. 10594 10595 Both syntaxes allow for the standard `.align' directive. However, 10596the Intel syntax additionally allows keywords for the alignment 10597parameter: "`.align type'", where `type' is one of `.short', `.long', 10598`.quad', `.single', `.double' representing alignments of 2, 4, 16, 4, 10599and 8, respectively. 10600 10601 10602File: as.info, Node: Opcodes for i860, Next: Syntax of i860, Prev: Directives-i860, Up: i860-Dependent 10603 106049.14.4 i860 Opcodes 10605------------------- 10606 10607All of the Intel i860XR and i860XP machine instructions are supported. 10608Please see either _i860 Microprocessor Programmer's Reference Manual_ 10609or _i860 Microprocessor Architecture_ for more information. 10610 106119.14.4.1 Other instruction support (pseudo-instructions) 10612........................................................ 10613 10614For compatibility with some other i860 assemblers, a number of 10615pseudo-instructions are supported. While these are supported, they are 10616a very undesirable feature that should be avoided - in particular, when 10617they result in an expansion to multiple actual i860 instructions. Below 10618are the pseudo-instructions that result in expansions. 10619 * Load large immediate into general register: 10620 10621 The pseudo-instruction `mov imm,%rn' (where the immediate does not 10622 fit within a signed 16-bit field) will be expanded into: 10623 orh large_imm@h,%r0,%rn 10624 or large_imm@l,%rn,%rn 10625 10626 * Load/store with relocatable address expression: 10627 10628 For example, the pseudo-instruction `ld.b addr_exp(%rx),%rn' will 10629 be expanded into: 10630 orh addr_exp@ha,%rx,%r31 10631 ld.l addr_exp@l(%r31),%rn 10632 10633 The analogous expansions apply to `ld.x, st.x, fld.x, pfld.x, 10634 fst.x', and `pst.x' as well. 10635 10636 * Signed large immediate with add/subtract: 10637 10638 If any of the arithmetic operations `adds, addu, subs, subu' are 10639 used with an immediate larger than 16-bits (signed), then they 10640 will be expanded. For instance, the pseudo-instruction `adds 10641 large_imm,%rx,%rn' expands to: 10642 orh large_imm@h,%r0,%r31 10643 or large_imm@l,%r31,%r31 10644 adds %r31,%rx,%rn 10645 10646 * Unsigned large immediate with logical operations: 10647 10648 Logical operations (`or, andnot, or, xor') also result in 10649 expansions. The pseudo-instruction `or large_imm,%rx,%rn' results 10650 in: 10651 orh large_imm@h,%rx,%r31 10652 or large_imm@l,%r31,%rn 10653 10654 Similarly for the others, except for `and' which expands to: 10655 andnot (-1 - large_imm)@h,%rx,%r31 10656 andnot (-1 - large_imm)@l,%r31,%rn 10657 10658 10659File: as.info, Node: Syntax of i860, Prev: Opcodes for i860, Up: i860-Dependent 10660 106619.14.5 i860 Syntax 10662------------------ 10663 10664* Menu: 10665 10666* i860-Chars:: Special Characters 10667 10668 10669File: as.info, Node: i860-Chars, Up: Syntax of i860 10670 106719.14.5.1 Special Characters 10672........................... 10673 10674The presence of a `#' appearing anywhere on a line indicates the start 10675of a comment that extends to the end of that line. 10676 10677 If a `#' appears as the first character of a line then the whole 10678line is treated as a comment, but in this case the line can also be a 10679logical line number directive (*note Comments::) or a preprocessor 10680control command (*note Preprocessing::). 10681 10682 The `;' character can be used to separate statements on the same 10683line. 10684 10685 10686File: as.info, Node: i960-Dependent, Next: IA-64-Dependent, Prev: i860-Dependent, Up: Machine Dependencies 10687 106889.15 Intel 80960 Dependent Features 10689=================================== 10690 10691* Menu: 10692 10693* Options-i960:: i960 Command-line Options 10694* Floating Point-i960:: Floating Point 10695* Directives-i960:: i960 Machine Directives 10696* Opcodes for i960:: i960 Opcodes 10697* Syntax of i960:: i960 Syntax 10698 10699 10700File: as.info, Node: Options-i960, Next: Floating Point-i960, Up: i960-Dependent 10701 107029.15.1 i960 Command-line Options 10703-------------------------------- 10704 10705`-ACA | -ACA_A | -ACB | -ACC | -AKA | -AKB | -AKC | -AMC' 10706 Select the 80960 architecture. Instructions or features not 10707 supported by the selected architecture cause fatal errors. 10708 10709 `-ACA' is equivalent to `-ACA_A'; `-AKC' is equivalent to `-AMC'. 10710 Synonyms are provided for compatibility with other tools. 10711 10712 If you do not specify any of these options, `as' generates code 10713 for any instruction or feature that is supported by _some_ version 10714 of the 960 (even if this means mixing architectures!). In 10715 principle, `as' attempts to deduce the minimal sufficient 10716 processor type if none is specified; depending on the object code 10717 format, the processor type may be recorded in the object file. If 10718 it is critical that the `as' output match a specific architecture, 10719 specify that architecture explicitly. 10720 10721`-b' 10722 Add code to collect information about conditional branches taken, 10723 for later optimization using branch prediction bits. (The 10724 conditional branch instructions have branch prediction bits in the 10725 CA, CB, and CC architectures.) If BR represents a conditional 10726 branch instruction, the following represents the code generated by 10727 the assembler when `-b' is specified: 10728 10729 call INCREMENT ROUTINE 10730 .word 0 # pre-counter 10731 Label: BR 10732 call INCREMENT ROUTINE 10733 .word 0 # post-counter 10734 10735 The counter following a branch records the number of times that 10736 branch was _not_ taken; the difference between the two counters is 10737 the number of times the branch _was_ taken. 10738 10739 A table of every such `Label' is also generated, so that the 10740 external postprocessor `gbr960' (supplied by Intel) can locate all 10741 the counters. This table is always labeled `__BRANCH_TABLE__'; 10742 this is a local symbol to permit collecting statistics for many 10743 separate object files. The table is word aligned, and begins with 10744 a two-word header. The first word, initialized to 0, is used in 10745 maintaining linked lists of branch tables. The second word is a 10746 count of the number of entries in the table, which follow 10747 immediately: each is a word, pointing to one of the labels 10748 illustrated above. 10749 10750 +------------+------------+------------+ ... +------------+ 10751 | | | | | | 10752 | *NEXT | COUNT: N | *BRLAB 1 | | *BRLAB N | 10753 | | | | | | 10754 +------------+------------+------------+ ... +------------+ 10755 10756 __BRANCH_TABLE__ layout 10757 10758 The first word of the header is used to locate multiple branch 10759 tables, since each object file may contain one. Normally the links 10760 are maintained with a call to an initialization routine, placed at 10761 the beginning of each function in the file. The GNU C compiler 10762 generates these calls automatically when you give it a `-b' option. 10763 For further details, see the documentation of `gbr960'. 10764 10765`-no-relax' 10766 Normally, Compare-and-Branch instructions with targets that require 10767 displacements greater than 13 bits (or that have external targets) 10768 are replaced with the corresponding compare (or `chkbit') and 10769 branch instructions. You can use the `-no-relax' option to 10770 specify that `as' should generate errors instead, if the target 10771 displacement is larger than 13 bits. 10772 10773 This option does not affect the Compare-and-Jump instructions; the 10774 code emitted for them is _always_ adjusted when necessary 10775 (depending on displacement size), regardless of whether you use 10776 `-no-relax'. 10777 10778 10779File: as.info, Node: Floating Point-i960, Next: Directives-i960, Prev: Options-i960, Up: i960-Dependent 10780 107819.15.2 Floating Point 10782--------------------- 10783 10784`as' generates IEEE floating-point numbers for the directives `.float', 10785`.double', `.extended', and `.single'. 10786 10787 10788File: as.info, Node: Directives-i960, Next: Opcodes for i960, Prev: Floating Point-i960, Up: i960-Dependent 10789 107909.15.3 i960 Machine Directives 10791------------------------------ 10792 10793`.bss SYMBOL, LENGTH, ALIGN' 10794 Reserve LENGTH bytes in the bss section for a local SYMBOL, 10795 aligned to the power of two specified by ALIGN. LENGTH and ALIGN 10796 must be positive absolute expressions. This directive differs 10797 from `.lcomm' only in that it permits you to specify an alignment. 10798 *Note `.lcomm': Lcomm. 10799 10800`.extended FLONUMS' 10801 `.extended' expects zero or more flonums, separated by commas; for 10802 each flonum, `.extended' emits an IEEE extended-format (80-bit) 10803 floating-point number. 10804 10805`.leafproc CALL-LAB, BAL-LAB' 10806 You can use the `.leafproc' directive in conjunction with the 10807 optimized `callj' instruction to enable faster calls of leaf 10808 procedures. If a procedure is known to call no other procedures, 10809 you may define an entry point that skips procedure prolog code 10810 (and that does not depend on system-supplied saved context), and 10811 declare it as the BAL-LAB using `.leafproc'. If the procedure 10812 also has an entry point that goes through the normal prolog, you 10813 can specify that entry point as CALL-LAB. 10814 10815 A `.leafproc' declaration is meant for use in conjunction with the 10816 optimized call instruction `callj'; the directive records the data 10817 needed later to choose between converting the `callj' into a `bal' 10818 or a `call'. 10819 10820 CALL-LAB is optional; if only one argument is present, or if the 10821 two arguments are identical, the single argument is assumed to be 10822 the `bal' entry point. 10823 10824`.sysproc NAME, INDEX' 10825 The `.sysproc' directive defines a name for a system procedure. 10826 After you define it using `.sysproc', you can use NAME to refer to 10827 the system procedure identified by INDEX when calling procedures 10828 with the optimized call instruction `callj'. 10829 10830 Both arguments are required; INDEX must be between 0 and 31 10831 (inclusive). 10832 10833 10834File: as.info, Node: Opcodes for i960, Next: Syntax of i960, Prev: Directives-i960, Up: i960-Dependent 10835 108369.15.4 i960 Opcodes 10837------------------- 10838 10839All Intel 960 machine instructions are supported; *note i960 10840Command-line Options: Options-i960. for a discussion of selecting the 10841instruction subset for a particular 960 architecture. 10842 10843 Some opcodes are processed beyond simply emitting a single 10844corresponding instruction: `callj', and Compare-and-Branch or 10845Compare-and-Jump instructions with target displacements larger than 13 10846bits. 10847 10848* Menu: 10849 10850* callj-i960:: `callj' 10851* Compare-and-branch-i960:: Compare-and-Branch 10852 10853 10854File: as.info, Node: callj-i960, Next: Compare-and-branch-i960, Up: Opcodes for i960 10855 108569.15.4.1 `callj' 10857................ 10858 10859You can write `callj' to have the assembler or the linker determine the 10860most appropriate form of subroutine call: `call', `bal', or `calls'. 10861If the assembly source contains enough information--a `.leafproc' or 10862`.sysproc' directive defining the operand--then `as' translates the 10863`callj'; if not, it simply emits the `callj', leaving it for the linker 10864to resolve. 10865 10866 10867File: as.info, Node: Compare-and-branch-i960, Prev: callj-i960, Up: Opcodes for i960 10868 108699.15.4.2 Compare-and-Branch 10870........................... 10871 10872The 960 architectures provide combined Compare-and-Branch instructions 10873that permit you to store the branch target in the lower 13 bits of the 10874instruction word itself. However, if you specify a branch target far 10875enough away that its address won't fit in 13 bits, the assembler can 10876either issue an error, or convert your Compare-and-Branch instruction 10877into separate instructions to do the compare and the branch. 10878 10879 Whether `as' gives an error or expands the instruction depends on 10880two choices you can make: whether you use the `-no-relax' option, and 10881whether you use a "Compare and Branch" instruction or a "Compare and 10882Jump" instruction. The "Jump" instructions are _always_ expanded if 10883necessary; the "Branch" instructions are expanded when necessary 10884_unless_ you specify `-no-relax'--in which case `as' gives an error 10885instead. 10886 10887 These are the Compare-and-Branch instructions, their "Jump" variants, 10888and the instruction pairs they may expand into: 10889 10890 Compare and 10891 Branch Jump Expanded to 10892 ------ ------ ------------ 10893 bbc chkbit; bno 10894 bbs chkbit; bo 10895 cmpibe cmpije cmpi; be 10896 cmpibg cmpijg cmpi; bg 10897 cmpibge cmpijge cmpi; bge 10898 cmpibl cmpijl cmpi; bl 10899 cmpible cmpijle cmpi; ble 10900 cmpibno cmpijno cmpi; bno 10901 cmpibne cmpijne cmpi; bne 10902 cmpibo cmpijo cmpi; bo 10903 cmpobe cmpoje cmpo; be 10904 cmpobg cmpojg cmpo; bg 10905 cmpobge cmpojge cmpo; bge 10906 cmpobl cmpojl cmpo; bl 10907 cmpoble cmpojle cmpo; ble 10908 cmpobne cmpojne cmpo; bne 10909 10910 10911File: as.info, Node: Syntax of i960, Prev: Opcodes for i960, Up: i960-Dependent 10912 109139.15.5 Syntax for the i960 10914-------------------------- 10915 10916* Menu: 10917 10918* i960-Chars:: Special Characters 10919 10920 10921File: as.info, Node: i960-Chars, Up: Syntax of i960 10922 109239.15.5.1 Special Characters 10924........................... 10925 10926The presence of a `#' on a line indicates the start of a comment that 10927extends to the end of the current line. 10928 10929 If a `#' appears as the first character of a line, the whole line is 10930treated as a comment, but in this case the line can also be a logical 10931line number directive (*note Comments::) or a preprocessor control 10932command (*note Preprocessing::). 10933 10934 The `;' character can be used to separate statements on the same 10935line. 10936 10937 10938File: as.info, Node: IA-64-Dependent, Next: IP2K-Dependent, Prev: i960-Dependent, Up: Machine Dependencies 10939 109409.16 IA-64 Dependent Features 10941============================= 10942 10943* Menu: 10944 10945* IA-64 Options:: Options 10946* IA-64 Syntax:: Syntax 10947* IA-64 Opcodes:: Opcodes 10948 10949 10950File: as.info, Node: IA-64 Options, Next: IA-64 Syntax, Up: IA-64-Dependent 10951 109529.16.1 Options 10953-------------- 10954 10955`-mconstant-gp' 10956 This option instructs the assembler to mark the resulting object 10957 file as using the "constant GP" model. With this model, it is 10958 assumed that the entire program uses a single global pointer (GP) 10959 value. Note that this option does not in any fashion affect the 10960 machine code emitted by the assembler. All it does is turn on the 10961 EF_IA_64_CONS_GP flag in the ELF file header. 10962 10963`-mauto-pic' 10964 This option instructs the assembler to mark the resulting object 10965 file as using the "constant GP without function descriptor" data 10966 model. This model is like the "constant GP" model, except that it 10967 additionally does away with function descriptors. What this means 10968 is that the address of a function refers directly to the 10969 function's code entry-point. Normally, such an address would 10970 refer to a function descriptor, which contains both the code 10971 entry-point and the GP-value needed by the function. Note that 10972 this option does not in any fashion affect the machine code 10973 emitted by the assembler. All it does is turn on the 10974 EF_IA_64_NOFUNCDESC_CONS_GP flag in the ELF file header. 10975 10976`-milp32' 10977`-milp64' 10978`-mlp64' 10979`-mp64' 10980 These options select the data model. The assembler defaults to 10981 `-mlp64' (LP64 data model). 10982 10983`-mle' 10984`-mbe' 10985 These options select the byte order. The `-mle' option selects 10986 little-endian byte order (default) and `-mbe' selects big-endian 10987 byte order. Note that IA-64 machine code always uses 10988 little-endian byte order. 10989 10990`-mtune=itanium1' 10991`-mtune=itanium2' 10992 Tune for a particular IA-64 CPU, ITANIUM1 or ITANIUM2. The default 10993 is ITANIUM2. 10994 10995`-munwind-check=warning' 10996`-munwind-check=error' 10997 These options control what the assembler will do when performing 10998 consistency checks on unwind directives. `-munwind-check=warning' 10999 will make the assembler issue a warning when an unwind directive 11000 check fails. This is the default. `-munwind-check=error' will 11001 make the assembler issue an error when an unwind directive check 11002 fails. 11003 11004`-mhint.b=ok' 11005`-mhint.b=warning' 11006`-mhint.b=error' 11007 These options control what the assembler will do when the `hint.b' 11008 instruction is used. `-mhint.b=ok' will make the assembler accept 11009 `hint.b'. `-mint.b=warning' will make the assembler issue a 11010 warning when `hint.b' is used. `-mhint.b=error' will make the 11011 assembler treat `hint.b' as an error, which is the default. 11012 11013`-x' 11014`-xexplicit' 11015 These options turn on dependency violation checking. 11016 11017`-xauto' 11018 This option instructs the assembler to automatically insert stop 11019 bits where necessary to remove dependency violations. This is the 11020 default mode. 11021 11022`-xnone' 11023 This option turns off dependency violation checking. 11024 11025`-xdebug' 11026 This turns on debug output intended to help tracking down bugs in 11027 the dependency violation checker. 11028 11029`-xdebugn' 11030 This is a shortcut for -xnone -xdebug. 11031 11032`-xdebugx' 11033 This is a shortcut for -xexplicit -xdebug. 11034 11035 11036 11037File: as.info, Node: IA-64 Syntax, Next: IA-64 Opcodes, Prev: IA-64 Options, Up: IA-64-Dependent 11038 110399.16.2 Syntax 11040------------- 11041 11042The assembler syntax closely follows the IA-64 Assembly Language 11043Reference Guide. 11044 11045* Menu: 11046 11047* IA-64-Chars:: Special Characters 11048* IA-64-Regs:: Register Names 11049* IA-64-Bits:: Bit Names 11050* IA-64-Relocs:: Relocations 11051 11052 11053File: as.info, Node: IA-64-Chars, Next: IA-64-Regs, Up: IA-64 Syntax 11054 110559.16.2.1 Special Characters 11056........................... 11057 11058`//' is the line comment token. 11059 11060 `;' can be used instead of a newline to separate statements. 11061 11062 11063File: as.info, Node: IA-64-Regs, Next: IA-64-Bits, Prev: IA-64-Chars, Up: IA-64 Syntax 11064 110659.16.2.2 Register Names 11066....................... 11067 11068The 128 integer registers are referred to as `rN'. The 128 11069floating-point registers are referred to as `fN'. The 128 application 11070registers are referred to as `arN'. The 128 control registers are 11071referred to as `crN'. The 64 one-bit predicate registers are referred 11072to as `pN'. The 8 branch registers are referred to as `bN'. In 11073addition, the assembler defines a number of aliases: `gp' (`r1'), `sp' 11074(`r12'), `rp' (`b0'), `ret0' (`r8'), `ret1' (`r9'), `ret2' (`r10'), 11075`ret3' (`r9'), `fargN' (`f8+N'), and `fretN' (`f8+N'). 11076 11077 For convenience, the assembler also defines aliases for all named 11078application and control registers. For example, `ar.bsp' refers to the 11079register backing store pointer (`ar17'). Similarly, `cr.eoi' refers to 11080the end-of-interrupt register (`cr67'). 11081 11082 11083File: as.info, Node: IA-64-Bits, Next: IA-64-Relocs, Prev: IA-64-Regs, Up: IA-64 Syntax 11084 110859.16.2.3 IA-64 Processor-Status-Register (PSR) Bit Names 11086........................................................ 11087 11088The assembler defines bit masks for each of the bits in the IA-64 11089processor status register. For example, `psr.ic' corresponds to a 11090value of 0x2000. These masks are primarily intended for use with the 11091`ssm'/`sum' and `rsm'/`rum' instructions, but they can be used anywhere 11092else where an integer constant is expected. 11093 11094 11095File: as.info, Node: IA-64-Relocs, Prev: IA-64-Bits, Up: IA-64 Syntax 11096 110979.16.2.4 Relocations 11098.................... 11099 11100In addition to the standard IA-64 relocations, the following 11101relocations are implemented by `as': 11102 11103`@slotcount(V)' 11104 Convert the address offset V into a slot count. This pseudo 11105 function is available only on VMS. The expression V must be known 11106 at assembly time: it can't reference undefined symbols or symbols 11107 in different sections. 11108 11109 11110File: as.info, Node: IA-64 Opcodes, Prev: IA-64 Syntax, Up: IA-64-Dependent 11111 111129.16.3 Opcodes 11113-------------- 11114 11115For detailed information on the IA-64 machine instruction set, see the 11116IA-64 Architecture Handbook 11117(http://developer.intel.com/design/itanium/arch_spec.htm). 11118 11119 11120File: as.info, Node: IP2K-Dependent, Next: LM32-Dependent, Prev: IA-64-Dependent, Up: Machine Dependencies 11121 111229.17 IP2K Dependent Features 11123============================ 11124 11125* Menu: 11126 11127* IP2K-Opts:: IP2K Options 11128* IP2K-Syntax:: IP2K Syntax 11129 11130 11131File: as.info, Node: IP2K-Opts, Next: IP2K-Syntax, Up: IP2K-Dependent 11132 111339.17.1 IP2K Options 11134------------------- 11135 11136The Ubicom IP2K version of `as' has a few machine dependent options: 11137 11138`-mip2022ext' 11139 `as' can assemble the extended IP2022 instructions, but it will 11140 only do so if this is specifically allowed via this command line 11141 option. 11142 11143`-mip2022' 11144 This option restores the assembler's default behaviour of not 11145 permitting the extended IP2022 instructions to be assembled. 11146 11147 11148 11149File: as.info, Node: IP2K-Syntax, Prev: IP2K-Opts, Up: IP2K-Dependent 11150 111519.17.2 IP2K Syntax 11152------------------ 11153 11154* Menu: 11155 11156* IP2K-Chars:: Special Characters 11157 11158 11159File: as.info, Node: IP2K-Chars, Up: IP2K-Syntax 11160 111619.17.2.1 Special Characters 11162........................... 11163 11164The presence of a `;' on a line indicates the start of a comment that 11165extends to the end of the current line. 11166 11167 If a `#' appears as the first character of a line, the whole line is 11168treated as a comment, but in this case the line can also be a logical 11169line number directive (*note Comments::) or a preprocessor control 11170command (*note Preprocessing::). 11171 11172 The IP2K assembler does not currently support a line separator 11173character. 11174 11175 11176File: as.info, Node: LM32-Dependent, Next: M32C-Dependent, Prev: IP2K-Dependent, Up: Machine Dependencies 11177 111789.18 LM32 Dependent Features 11179============================ 11180 11181* Menu: 11182 11183* LM32 Options:: Options 11184* LM32 Syntax:: Syntax 11185* LM32 Opcodes:: Opcodes 11186 11187 11188File: as.info, Node: LM32 Options, Next: LM32 Syntax, Up: LM32-Dependent 11189 111909.18.1 Options 11191-------------- 11192 11193`-mmultiply-enabled' 11194 Enable multiply instructions. 11195 11196`-mdivide-enabled' 11197 Enable divide instructions. 11198 11199`-mbarrel-shift-enabled' 11200 Enable barrel-shift instructions. 11201 11202`-msign-extend-enabled' 11203 Enable sign extend instructions. 11204 11205`-muser-enabled' 11206 Enable user defined instructions. 11207 11208`-micache-enabled' 11209 Enable instruction cache related CSRs. 11210 11211`-mdcache-enabled' 11212 Enable data cache related CSRs. 11213 11214`-mbreak-enabled' 11215 Enable break instructions. 11216 11217`-mall-enabled' 11218 Enable all instructions and CSRs. 11219 11220 11221 11222File: as.info, Node: LM32 Syntax, Next: LM32 Opcodes, Prev: LM32 Options, Up: LM32-Dependent 11223 112249.18.2 Syntax 11225------------- 11226 11227* Menu: 11228 11229* LM32-Regs:: Register Names 11230* LM32-Modifiers:: Relocatable Expression Modifiers 11231* LM32-Chars:: Special Characters 11232 11233 11234File: as.info, Node: LM32-Regs, Next: LM32-Modifiers, Up: LM32 Syntax 11235 112369.18.2.1 Register Names 11237....................... 11238 11239LM32 has 32 x 32-bit general purpose registers `r0', `r1', ... `r31'. 11240 11241 The following aliases are defined: `gp' - `r26', `fp' - `r27', `sp' 11242- `r28', `ra' - `r29', `ea' - `r30', `ba' - `r31'. 11243 11244 LM32 has the following Control and Status Registers (CSRs). 11245 11246`IE' 11247 Interrupt enable. 11248 11249`IM' 11250 Interrupt mask. 11251 11252`IP' 11253 Interrupt pending. 11254 11255`ICC' 11256 Instruction cache control. 11257 11258`DCC' 11259 Data cache control. 11260 11261`CC' 11262 Cycle counter. 11263 11264`CFG' 11265 Configuration. 11266 11267`EBA' 11268 Exception base address. 11269 11270`DC' 11271 Debug control. 11272 11273`DEBA' 11274 Debug exception base address. 11275 11276`JTX' 11277 JTAG transmit. 11278 11279`JRX' 11280 JTAG receive. 11281 11282`BP0' 11283 Breakpoint 0. 11284 11285`BP1' 11286 Breakpoint 1. 11287 11288`BP2' 11289 Breakpoint 2. 11290 11291`BP3' 11292 Breakpoint 3. 11293 11294`WP0' 11295 Watchpoint 0. 11296 11297`WP1' 11298 Watchpoint 1. 11299 11300`WP2' 11301 Watchpoint 2. 11302 11303`WP3' 11304 Watchpoint 3. 11305 11306 11307File: as.info, Node: LM32-Modifiers, Next: LM32-Chars, Prev: LM32-Regs, Up: LM32 Syntax 11308 113099.18.2.2 Relocatable Expression Modifiers 11310......................................... 11311 11312The assembler supports several modifiers when using relocatable 11313addresses in LM32 instruction operands. The general syntax is the 11314following: 11315 11316 modifier(relocatable-expression) 11317 11318`lo' 11319 This modifier allows you to use bits 0 through 15 of an address 11320 expression as 16 bit relocatable expression. 11321 11322`hi' 11323 This modifier allows you to use bits 16 through 23 of an address 11324 expression as 16 bit relocatable expression. 11325 11326 For example 11327 11328 ori r4, r4, lo(sym+10) 11329 orhi r4, r4, hi(sym+10) 11330 11331`gp' 11332 This modified creates a 16-bit relocatable expression that is the 11333 offset of the symbol from the global pointer. 11334 11335 mva r4, gp(sym) 11336 11337`got' 11338 This modifier places a symbol in the GOT and creates a 16-bit 11339 relocatable expression that is the offset into the GOT of this 11340 symbol. 11341 11342 lw r4, (gp+got(sym)) 11343 11344`gotofflo16' 11345 This modifier allows you to use the bits 0 through 15 of an 11346 address which is an offset from the GOT. 11347 11348`gotoffhi16' 11349 This modifier allows you to use the bits 16 through 31 of an 11350 address which is an offset from the GOT. 11351 11352 orhi r4, r4, gotoffhi16(lsym) 11353 addi r4, r4, gotofflo16(lsym) 11354 11355 11356 11357File: as.info, Node: LM32-Chars, Prev: LM32-Modifiers, Up: LM32 Syntax 11358 113599.18.2.3 Special Characters 11360........................... 11361 11362The presence of a `#' on a line indicates the start of a comment that 11363extends to the end of the current line. Note that if a line starts 11364with a `#' character then it can also be a logical line number 11365directive (*note Comments::) or a preprocessor control command (*note 11366Preprocessing::). 11367 11368 A semicolon (`;') can be used to separate multiple statements on the 11369same line. 11370 11371 11372File: as.info, Node: LM32 Opcodes, Prev: LM32 Syntax, Up: LM32-Dependent 11373 113749.18.3 Opcodes 11375-------------- 11376 11377For detailed information on the LM32 machine instruction set, see 11378`http://www.latticesemi.com/products/intellectualproperty/ipcores/mico32/'. 11379 11380 `as' implements all the standard LM32 opcodes. 11381 11382 11383File: as.info, Node: M32C-Dependent, Next: M32R-Dependent, Prev: LM32-Dependent, Up: Machine Dependencies 11384 113859.19 M32C Dependent Features 11386============================ 11387 11388 `as' can assemble code for several different members of the Renesas 11389M32C family. Normally the default is to assemble code for the M16C 11390microprocessor. The `-m32c' option may be used to change the default 11391to the M32C microprocessor. 11392 11393* Menu: 11394 11395* M32C-Opts:: M32C Options 11396* M32C-Syntax:: M32C Syntax 11397 11398 11399File: as.info, Node: M32C-Opts, Next: M32C-Syntax, Up: M32C-Dependent 11400 114019.19.1 M32C Options 11402------------------- 11403 11404The Renesas M32C version of `as' has these machine-dependent options: 11405 11406`-m32c' 11407 Assemble M32C instructions. 11408 11409`-m16c' 11410 Assemble M16C instructions (default). 11411 11412`-relax' 11413 Enable support for link-time relaxations. 11414 11415`-h-tick-hex' 11416 Support H'00 style hex constants in addition to 0x00 style. 11417 11418 11419 11420File: as.info, Node: M32C-Syntax, Prev: M32C-Opts, Up: M32C-Dependent 11421 114229.19.2 M32C Syntax 11423------------------ 11424 11425* Menu: 11426 11427* M32C-Modifiers:: Symbolic Operand Modifiers 11428* M32C-Chars:: Special Characters 11429 11430 11431File: as.info, Node: M32C-Modifiers, Next: M32C-Chars, Up: M32C-Syntax 11432 114339.19.2.1 Symbolic Operand Modifiers 11434................................... 11435 11436The assembler supports several modifiers when using symbol addresses in 11437M32C instruction operands. The general syntax is the following: 11438 11439 %modifier(symbol) 11440 11441`%dsp8' 11442`%dsp16' 11443 These modifiers override the assembler's assumptions about how big 11444 a symbol's address is. Normally, when it sees an operand like 11445 `sym[a0]' it assumes `sym' may require the widest displacement 11446 field (16 bits for `-m16c', 24 bits for `-m32c'). These modifiers 11447 tell it to assume the address will fit in an 8 or 16 bit 11448 (respectively) unsigned displacement. Note that, of course, if it 11449 doesn't actually fit you will get linker errors. Example: 11450 11451 mov.w %dsp8(sym)[a0],r1 11452 mov.b #0,%dsp8(sym)[a0] 11453 11454`%hi8' 11455 This modifier allows you to load bits 16 through 23 of a 24 bit 11456 address into an 8 bit register. This is useful with, for example, 11457 the M16C `smovf' instruction, which expects a 20 bit address in 11458 `r1h' and `a0'. Example: 11459 11460 mov.b #%hi8(sym),r1h 11461 mov.w #%lo16(sym),a0 11462 smovf.b 11463 11464`%lo16' 11465 Likewise, this modifier allows you to load bits 0 through 15 of a 11466 24 bit address into a 16 bit register. 11467 11468`%hi16' 11469 This modifier allows you to load bits 16 through 31 of a 32 bit 11470 address into a 16 bit register. While the M32C family only has 24 11471 bits of address space, it does support addresses in pairs of 16 bit 11472 registers (like `a1a0' for the `lde' instruction). This modifier 11473 is for loading the upper half in such cases. Example: 11474 11475 mov.w #%hi16(sym),a1 11476 mov.w #%lo16(sym),a0 11477 ... 11478 lde.w [a1a0],r1 11479 11480 11481 11482File: as.info, Node: M32C-Chars, Prev: M32C-Modifiers, Up: M32C-Syntax 11483 114849.19.2.2 Special Characters 11485........................... 11486 11487The presence of a `;' character on a line indicates the start of a 11488comment that extends to the end of that line. 11489 11490 If a `#' appears as the first character of a line, the whole line is 11491treated as a comment, but in this case the line can also be a logical 11492line number directive (*note Comments::) or a preprocessor control 11493command (*note Preprocessing::). 11494 11495 The `|' character can be used to separate statements on the same 11496line. 11497 11498 11499File: as.info, Node: M32R-Dependent, Next: M68K-Dependent, Prev: M32C-Dependent, Up: Machine Dependencies 11500 115019.20 M32R Dependent Features 11502============================ 11503 11504* Menu: 11505 11506* M32R-Opts:: M32R Options 11507* M32R-Directives:: M32R Directives 11508* M32R-Warnings:: M32R Warnings 11509 11510 11511File: as.info, Node: M32R-Opts, Next: M32R-Directives, Up: M32R-Dependent 11512 115139.20.1 M32R Options 11514------------------- 11515 11516The Renease M32R version of `as' has a few machine dependent options: 11517 11518`-m32rx' 11519 `as' can assemble code for several different members of the 11520 Renesas M32R family. Normally the default is to assemble code for 11521 the M32R microprocessor. This option may be used to change the 11522 default to the M32RX microprocessor, which adds some more 11523 instructions to the basic M32R instruction set, and some 11524 additional parameters to some of the original instructions. 11525 11526`-m32r2' 11527 This option changes the target processor to the the M32R2 11528 microprocessor. 11529 11530`-m32r' 11531 This option can be used to restore the assembler's default 11532 behaviour of assembling for the M32R microprocessor. This can be 11533 useful if the default has been changed by a previous command line 11534 option. 11535 11536`-little' 11537 This option tells the assembler to produce little-endian code and 11538 data. The default is dependent upon how the toolchain was 11539 configured. 11540 11541`-EL' 11542 This is a synonym for _-little_. 11543 11544`-big' 11545 This option tells the assembler to produce big-endian code and 11546 data. 11547 11548`-EB' 11549 This is a synonum for _-big_. 11550 11551`-KPIC' 11552 This option specifies that the output of the assembler should be 11553 marked as position-independent code (PIC). 11554 11555`-parallel' 11556 This option tells the assembler to attempts to combine two 11557 sequential instructions into a single, parallel instruction, where 11558 it is legal to do so. 11559 11560`-no-parallel' 11561 This option disables a previously enabled _-parallel_ option. 11562 11563`-no-bitinst' 11564 This option disables the support for the extended bit-field 11565 instructions provided by the M32R2. If this support needs to be 11566 re-enabled the _-bitinst_ switch can be used to restore it. 11567 11568`-O' 11569 This option tells the assembler to attempt to optimize the 11570 instructions that it produces. This includes filling delay slots 11571 and converting sequential instructions into parallel ones. This 11572 option implies _-parallel_. 11573 11574`-warn-explicit-parallel-conflicts' 11575 Instructs `as' to produce warning messages when questionable 11576 parallel instructions are encountered. This option is enabled by 11577 default, but `gcc' disables it when it invokes `as' directly. 11578 Questionable instructions are those whose behaviour would be 11579 different if they were executed sequentially. For example the 11580 code fragment `mv r1, r2 || mv r3, r1' produces a different result 11581 from `mv r1, r2 \n mv r3, r1' since the former moves r1 into r3 11582 and then r2 into r1, whereas the later moves r2 into r1 and r3. 11583 11584`-Wp' 11585 This is a shorter synonym for the 11586 _-warn-explicit-parallel-conflicts_ option. 11587 11588`-no-warn-explicit-parallel-conflicts' 11589 Instructs `as' not to produce warning messages when questionable 11590 parallel instructions are encountered. 11591 11592`-Wnp' 11593 This is a shorter synonym for the 11594 _-no-warn-explicit-parallel-conflicts_ option. 11595 11596`-ignore-parallel-conflicts' 11597 This option tells the assembler's to stop checking parallel 11598 instructions for constraint violations. This ability is provided 11599 for hardware vendors testing chip designs and should not be used 11600 under normal circumstances. 11601 11602`-no-ignore-parallel-conflicts' 11603 This option restores the assembler's default behaviour of checking 11604 parallel instructions to detect constraint violations. 11605 11606`-Ip' 11607 This is a shorter synonym for the _-ignore-parallel-conflicts_ 11608 option. 11609 11610`-nIp' 11611 This is a shorter synonym for the _-no-ignore-parallel-conflicts_ 11612 option. 11613 11614`-warn-unmatched-high' 11615 This option tells the assembler to produce a warning message if a 11616 `.high' pseudo op is encountered without a matching `.low' pseudo 11617 op. The presence of such an unmatched pseudo op usually indicates 11618 a programming error. 11619 11620`-no-warn-unmatched-high' 11621 Disables a previously enabled _-warn-unmatched-high_ option. 11622 11623`-Wuh' 11624 This is a shorter synonym for the _-warn-unmatched-high_ option. 11625 11626`-Wnuh' 11627 This is a shorter synonym for the _-no-warn-unmatched-high_ option. 11628 11629 11630 11631File: as.info, Node: M32R-Directives, Next: M32R-Warnings, Prev: M32R-Opts, Up: M32R-Dependent 11632 116339.20.2 M32R Directives 11634---------------------- 11635 11636The Renease M32R version of `as' has a few architecture specific 11637directives: 11638 11639`low EXPRESSION' 11640 The `low' directive computes the value of its expression and 11641 places the lower 16-bits of the result into the immediate-field of 11642 the instruction. For example: 11643 11644 or3 r0, r0, #low(0x12345678) ; compute r0 = r0 | 0x5678 11645 add3, r0, r0, #low(fred) ; compute r0 = r0 + low 16-bits of address of fred 11646 11647`high EXPRESSION' 11648 The `high' directive computes the value of its expression and 11649 places the upper 16-bits of the result into the immediate-field of 11650 the instruction. For example: 11651 11652 seth r0, #high(0x12345678) ; compute r0 = 0x12340000 11653 seth, r0, #high(fred) ; compute r0 = upper 16-bits of address of fred 11654 11655`shigh EXPRESSION' 11656 The `shigh' directive is very similar to the `high' directive. It 11657 also computes the value of its expression and places the upper 11658 16-bits of the result into the immediate-field of the instruction. 11659 The difference is that `shigh' also checks to see if the lower 11660 16-bits could be interpreted as a signed number, and if so it 11661 assumes that a borrow will occur from the upper-16 bits. To 11662 compensate for this the `shigh' directive pre-biases the upper 16 11663 bit value by adding one to it. For example: 11664 11665 For example: 11666 11667 seth r0, #shigh(0x12345678) ; compute r0 = 0x12340000 11668 seth r0, #shigh(0x00008000) ; compute r0 = 0x00010000 11669 11670 In the second example the lower 16-bits are 0x8000. If these are 11671 treated as a signed value and sign extended to 32-bits then the 11672 value becomes 0xffff8000. If this value is then added to 11673 0x00010000 then the result is 0x00008000. 11674 11675 This behaviour is to allow for the different semantics of the 11676 `or3' and `add3' instructions. The `or3' instruction treats its 11677 16-bit immediate argument as unsigned whereas the `add3' treats 11678 its 16-bit immediate as a signed value. So for example: 11679 11680 seth r0, #shigh(0x00008000) 11681 add3 r0, r0, #low(0x00008000) 11682 11683 Produces the correct result in r0, whereas: 11684 11685 seth r0, #shigh(0x00008000) 11686 or3 r0, r0, #low(0x00008000) 11687 11688 Stores 0xffff8000 into r0. 11689 11690 Note - the `shigh' directive does not know where in the assembly 11691 source code the lower 16-bits of the value are going set, so it 11692 cannot check to make sure that an `or3' instruction is being used 11693 rather than an `add3' instruction. It is up to the programmer to 11694 make sure that correct directives are used. 11695 11696`.m32r' 11697 The directive performs a similar thing as the _-m32r_ command line 11698 option. It tells the assembler to only accept M32R instructions 11699 from now on. An instructions from later M32R architectures are 11700 refused. 11701 11702`.m32rx' 11703 The directive performs a similar thing as the _-m32rx_ command 11704 line option. It tells the assembler to start accepting the extra 11705 instructions in the M32RX ISA as well as the ordinary M32R ISA. 11706 11707`.m32r2' 11708 The directive performs a similar thing as the _-m32r2_ command 11709 line option. It tells the assembler to start accepting the extra 11710 instructions in the M32R2 ISA as well as the ordinary M32R ISA. 11711 11712`.little' 11713 The directive performs a similar thing as the _-little_ command 11714 line option. It tells the assembler to start producing 11715 little-endian code and data. This option should be used with care 11716 as producing mixed-endian binary files is fraught with danger. 11717 11718`.big' 11719 The directive performs a similar thing as the _-big_ command line 11720 option. It tells the assembler to start producing big-endian code 11721 and data. This option should be used with care as producing 11722 mixed-endian binary files is fraught with danger. 11723 11724 11725 11726File: as.info, Node: M32R-Warnings, Prev: M32R-Directives, Up: M32R-Dependent 11727 117289.20.3 M32R Warnings 11729-------------------- 11730 11731There are several warning and error messages that can be produced by 11732`as' which are specific to the M32R: 11733 11734`output of 1st instruction is the same as an input to 2nd instruction - is this intentional ?' 11735 This message is only produced if warnings for explicit parallel 11736 conflicts have been enabled. It indicates that the assembler has 11737 encountered a parallel instruction in which the destination 11738 register of the left hand instruction is used as an input register 11739 in the right hand instruction. For example in this code fragment 11740 `mv r1, r2 || neg r3, r1' register r1 is the destination of the 11741 move instruction and the input to the neg instruction. 11742 11743`output of 2nd instruction is the same as an input to 1st instruction - is this intentional ?' 11744 This message is only produced if warnings for explicit parallel 11745 conflicts have been enabled. It indicates that the assembler has 11746 encountered a parallel instruction in which the destination 11747 register of the right hand instruction is used as an input 11748 register in the left hand instruction. For example in this code 11749 fragment `mv r1, r2 || neg r2, r3' register r2 is the destination 11750 of the neg instruction and the input to the move instruction. 11751 11752`instruction `...' is for the M32RX only' 11753 This message is produced when the assembler encounters an 11754 instruction which is only supported by the M32Rx processor, and 11755 the `-m32rx' command line flag has not been specified to allow 11756 assembly of such instructions. 11757 11758`unknown instruction `...'' 11759 This message is produced when the assembler encounters an 11760 instruction which it does not recognize. 11761 11762`only the NOP instruction can be issued in parallel on the m32r' 11763 This message is produced when the assembler encounters a parallel 11764 instruction which does not involve a NOP instruction and the 11765 `-m32rx' command line flag has not been specified. Only the M32Rx 11766 processor is able to execute two instructions in parallel. 11767 11768`instruction `...' cannot be executed in parallel.' 11769 This message is produced when the assembler encounters a parallel 11770 instruction which is made up of one or two instructions which 11771 cannot be executed in parallel. 11772 11773`Instructions share the same execution pipeline' 11774 This message is produced when the assembler encounters a parallel 11775 instruction whoes components both use the same execution pipeline. 11776 11777`Instructions write to the same destination register.' 11778 This message is produced when the assembler encounters a parallel 11779 instruction where both components attempt to modify the same 11780 register. For example these code fragments will produce this 11781 message: `mv r1, r2 || neg r1, r3' `jl r0 || mv r14, r1' `st r2, 11782 @-r1 || mv r1, r3' `mv r1, r2 || ld r0, @r1+' `cmp r1, r2 || addx 11783 r3, r4' (Both write to the condition bit) 11784 11785 11786 11787File: as.info, Node: M68K-Dependent, Next: M68HC11-Dependent, Prev: M32R-Dependent, Up: Machine Dependencies 11788 117899.21 M680x0 Dependent Features 11790============================== 11791 11792* Menu: 11793 11794* M68K-Opts:: M680x0 Options 11795* M68K-Syntax:: Syntax 11796* M68K-Moto-Syntax:: Motorola Syntax 11797* M68K-Float:: Floating Point 11798* M68K-Directives:: 680x0 Machine Directives 11799* M68K-opcodes:: Opcodes 11800 11801 11802File: as.info, Node: M68K-Opts, Next: M68K-Syntax, Up: M68K-Dependent 11803 118049.21.1 M680x0 Options 11805--------------------- 11806 11807The Motorola 680x0 version of `as' has a few machine dependent options: 11808 11809`-march=ARCHITECTURE' 11810 This option specifies a target architecture. The following 11811 architectures are recognized: `68000', `68010', `68020', `68030', 11812 `68040', `68060', `cpu32', `isaa', `isaaplus', `isab', `isac' and 11813 `cfv4e'. 11814 11815`-mcpu=CPU' 11816 This option specifies a target cpu. When used in conjunction with 11817 the `-march' option, the cpu must be within the specified 11818 architecture. Also, the generic features of the architecture are 11819 used for instruction generation, rather than those of the specific 11820 chip. 11821 11822`-m[no-]68851' 11823`-m[no-]68881' 11824`-m[no-]div' 11825`-m[no-]usp' 11826`-m[no-]float' 11827`-m[no-]mac' 11828`-m[no-]emac' 11829 Enable or disable various architecture specific features. If a 11830 chip or architecture by default supports an option (for instance 11831 `-march=isaaplus' includes the `-mdiv' option), explicitly 11832 disabling the option will override the default. 11833 11834`-l' 11835 You can use the `-l' option to shorten the size of references to 11836 undefined symbols. If you do not use the `-l' option, references 11837 to undefined symbols are wide enough for a full `long' (32 bits). 11838 (Since `as' cannot know where these symbols end up, `as' can only 11839 allocate space for the linker to fill in later. Since `as' does 11840 not know how far away these symbols are, it allocates as much 11841 space as it can.) If you use this option, the references are only 11842 one word wide (16 bits). This may be useful if you want the 11843 object file to be as small as possible, and you know that the 11844 relevant symbols are always less than 17 bits away. 11845 11846`--register-prefix-optional' 11847 For some configurations, especially those where the compiler 11848 normally does not prepend an underscore to the names of user 11849 variables, the assembler requires a `%' before any use of a 11850 register name. This is intended to let the assembler distinguish 11851 between C variables and functions named `a0' through `a7', and so 11852 on. The `%' is always accepted, but is not required for certain 11853 configurations, notably `sun3'. The `--register-prefix-optional' 11854 option may be used to permit omitting the `%' even for 11855 configurations for which it is normally required. If this is 11856 done, it will generally be impossible to refer to C variables and 11857 functions with the same names as register names. 11858 11859`--bitwise-or' 11860 Normally the character `|' is treated as a comment character, which 11861 means that it can not be used in expressions. The `--bitwise-or' 11862 option turns `|' into a normal character. In this mode, you must 11863 either use C style comments, or start comments with a `#' character 11864 at the beginning of a line. 11865 11866`--base-size-default-16 --base-size-default-32' 11867 If you use an addressing mode with a base register without 11868 specifying the size, `as' will normally use the full 32 bit value. 11869 For example, the addressing mode `%a0@(%d0)' is equivalent to 11870 `%a0@(%d0:l)'. You may use the `--base-size-default-16' option to 11871 tell `as' to default to using the 16 bit value. In this case, 11872 `%a0@(%d0)' is equivalent to `%a0@(%d0:w)'. You may use the 11873 `--base-size-default-32' option to restore the default behaviour. 11874 11875`--disp-size-default-16 --disp-size-default-32' 11876 If you use an addressing mode with a displacement, and the value 11877 of the displacement is not known, `as' will normally assume that 11878 the value is 32 bits. For example, if the symbol `disp' has not 11879 been defined, `as' will assemble the addressing mode 11880 `%a0@(disp,%d0)' as though `disp' is a 32 bit value. You may use 11881 the `--disp-size-default-16' option to tell `as' to instead assume 11882 that the displacement is 16 bits. In this case, `as' will 11883 assemble `%a0@(disp,%d0)' as though `disp' is a 16 bit value. You 11884 may use the `--disp-size-default-32' option to restore the default 11885 behaviour. 11886 11887`--pcrel' 11888 Always keep branches PC-relative. In the M680x0 architecture all 11889 branches are defined as PC-relative. However, on some processors 11890 they are limited to word displacements maximum. When `as' needs a 11891 long branch that is not available, it normally emits an absolute 11892 jump instead. This option disables this substitution. When this 11893 option is given and no long branches are available, only word 11894 branches will be emitted. An error message will be generated if a 11895 word branch cannot reach its target. This option has no effect on 11896 68020 and other processors that have long branches. *note Branch 11897 Improvement: M68K-Branch. 11898 11899`-m68000' 11900 `as' can assemble code for several different members of the 11901 Motorola 680x0 family. The default depends upon how `as' was 11902 configured when it was built; normally, the default is to assemble 11903 code for the 68020 microprocessor. The following options may be 11904 used to change the default. These options control which 11905 instructions and addressing modes are permitted. The members of 11906 the 680x0 family are very similar. For detailed information about 11907 the differences, see the Motorola manuals. 11908 11909 `-m68000' 11910 `-m68ec000' 11911 `-m68hc000' 11912 `-m68hc001' 11913 `-m68008' 11914 `-m68302' 11915 `-m68306' 11916 `-m68307' 11917 `-m68322' 11918 `-m68356' 11919 Assemble for the 68000. `-m68008', `-m68302', and so on are 11920 synonyms for `-m68000', since the chips are the same from the 11921 point of view of the assembler. 11922 11923 `-m68010' 11924 Assemble for the 68010. 11925 11926 `-m68020' 11927 `-m68ec020' 11928 Assemble for the 68020. This is normally the default. 11929 11930 `-m68030' 11931 `-m68ec030' 11932 Assemble for the 68030. 11933 11934 `-m68040' 11935 `-m68ec040' 11936 Assemble for the 68040. 11937 11938 `-m68060' 11939 `-m68ec060' 11940 Assemble for the 68060. 11941 11942 `-mcpu32' 11943 `-m68330' 11944 `-m68331' 11945 `-m68332' 11946 `-m68333' 11947 `-m68334' 11948 `-m68336' 11949 `-m68340' 11950 `-m68341' 11951 `-m68349' 11952 `-m68360' 11953 Assemble for the CPU32 family of chips. 11954 11955 `-m5200' 11956 `-m5202' 11957 `-m5204' 11958 `-m5206' 11959 `-m5206e' 11960 `-m521x' 11961 `-m5249' 11962 `-m528x' 11963 `-m5307' 11964 `-m5407' 11965 `-m547x' 11966 `-m548x' 11967 `-mcfv4' 11968 `-mcfv4e' 11969 Assemble for the ColdFire family of chips. 11970 11971 `-m68881' 11972 `-m68882' 11973 Assemble 68881 floating point instructions. This is the 11974 default for the 68020, 68030, and the CPU32. The 68040 and 11975 68060 always support floating point instructions. 11976 11977 `-mno-68881' 11978 Do not assemble 68881 floating point instructions. This is 11979 the default for 68000 and the 68010. The 68040 and 68060 11980 always support floating point instructions, even if this 11981 option is used. 11982 11983 `-m68851' 11984 Assemble 68851 MMU instructions. This is the default for the 11985 68020, 68030, and 68060. The 68040 accepts a somewhat 11986 different set of MMU instructions; `-m68851' and `-m68040' 11987 should not be used together. 11988 11989 `-mno-68851' 11990 Do not assemble 68851 MMU instructions. This is the default 11991 for the 68000, 68010, and the CPU32. The 68040 accepts a 11992 somewhat different set of MMU instructions. 11993 11994 11995File: as.info, Node: M68K-Syntax, Next: M68K-Moto-Syntax, Prev: M68K-Opts, Up: M68K-Dependent 11996 119979.21.2 Syntax 11998------------- 11999 12000This syntax for the Motorola 680x0 was developed at MIT. 12001 12002 The 680x0 version of `as' uses instructions names and syntax 12003compatible with the Sun assembler. Intervening periods are ignored; 12004for example, `movl' is equivalent to `mov.l'. 12005 12006 In the following table APC stands for any of the address registers 12007(`%a0' through `%a7'), the program counter (`%pc'), the zero-address 12008relative to the program counter (`%zpc'), a suppressed address register 12009(`%za0' through `%za7'), or it may be omitted entirely. The use of 12010SIZE means one of `w' or `l', and it may be omitted, along with the 12011leading colon, unless a scale is also specified. The use of SCALE 12012means one of `1', `2', `4', or `8', and it may always be omitted along 12013with the leading colon. 12014 12015 The following addressing modes are understood: 12016"Immediate" 12017 `#NUMBER' 12018 12019"Data Register" 12020 `%d0' through `%d7' 12021 12022"Address Register" 12023 `%a0' through `%a7' 12024 `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is 12025 also known as `%fp', the Frame Pointer. 12026 12027"Address Register Indirect" 12028 `%a0@' through `%a7@' 12029 12030"Address Register Postincrement" 12031 `%a0@+' through `%a7@+' 12032 12033"Address Register Predecrement" 12034 `%a0@-' through `%a7@-' 12035 12036"Indirect Plus Offset" 12037 `APC@(NUMBER)' 12038 12039"Index" 12040 `APC@(NUMBER,REGISTER:SIZE:SCALE)' 12041 12042 The NUMBER may be omitted. 12043 12044"Postindex" 12045 `APC@(NUMBER)@(ONUMBER,REGISTER:SIZE:SCALE)' 12046 12047 The ONUMBER or the REGISTER, but not both, may be omitted. 12048 12049"Preindex" 12050 `APC@(NUMBER,REGISTER:SIZE:SCALE)@(ONUMBER)' 12051 12052 The NUMBER may be omitted. Omitting the REGISTER produces the 12053 Postindex addressing mode. 12054 12055"Absolute" 12056 `SYMBOL', or `DIGITS', optionally followed by `:b', `:w', or `:l'. 12057 12058 12059File: as.info, Node: M68K-Moto-Syntax, Next: M68K-Float, Prev: M68K-Syntax, Up: M68K-Dependent 12060 120619.21.3 Motorola Syntax 12062---------------------- 12063 12064The standard Motorola syntax for this chip differs from the syntax 12065already discussed (*note Syntax: M68K-Syntax.). `as' can accept 12066Motorola syntax for operands, even if MIT syntax is used for other 12067operands in the same instruction. The two kinds of syntax are fully 12068compatible. 12069 12070 In the following table APC stands for any of the address registers 12071(`%a0' through `%a7'), the program counter (`%pc'), the zero-address 12072relative to the program counter (`%zpc'), or a suppressed address 12073register (`%za0' through `%za7'). The use of SIZE means one of `w' or 12074`l', and it may always be omitted along with the leading dot. The use 12075of SCALE means one of `1', `2', `4', or `8', and it may always be 12076omitted along with the leading asterisk. 12077 12078 The following additional addressing modes are understood: 12079 12080"Address Register Indirect" 12081 `(%a0)' through `(%a7)' 12082 `%a7' is also known as `%sp', i.e., the Stack Pointer. `%a6' is 12083 also known as `%fp', the Frame Pointer. 12084 12085"Address Register Postincrement" 12086 `(%a0)+' through `(%a7)+' 12087 12088"Address Register Predecrement" 12089 `-(%a0)' through `-(%a7)' 12090 12091"Indirect Plus Offset" 12092 `NUMBER(%A0)' through `NUMBER(%A7)', or `NUMBER(%PC)'. 12093 12094 The NUMBER may also appear within the parentheses, as in 12095 `(NUMBER,%A0)'. When used with the PC, the NUMBER may be omitted 12096 (with an address register, omitting the NUMBER produces Address 12097 Register Indirect mode). 12098 12099"Index" 12100 `NUMBER(APC,REGISTER.SIZE*SCALE)' 12101 12102 The NUMBER may be omitted, or it may appear within the 12103 parentheses. The APC may be omitted. The REGISTER and the APC 12104 may appear in either order. If both APC and REGISTER are address 12105 registers, and the SIZE and SCALE are omitted, then the first 12106 register is taken as the base register, and the second as the 12107 index register. 12108 12109"Postindex" 12110 `([NUMBER,APC],REGISTER.SIZE*SCALE,ONUMBER)' 12111 12112 The ONUMBER, or the REGISTER, or both, may be omitted. Either the 12113 NUMBER or the APC may be omitted, but not both. 12114 12115"Preindex" 12116 `([NUMBER,APC,REGISTER.SIZE*SCALE],ONUMBER)' 12117 12118 The NUMBER, or the APC, or the REGISTER, or any two of them, may 12119 be omitted. The ONUMBER may be omitted. The REGISTER and the APC 12120 may appear in either order. If both APC and REGISTER are address 12121 registers, and the SIZE and SCALE are omitted, then the first 12122 register is taken as the base register, and the second as the 12123 index register. 12124 12125 12126File: as.info, Node: M68K-Float, Next: M68K-Directives, Prev: M68K-Moto-Syntax, Up: M68K-Dependent 12127 121289.21.4 Floating Point 12129--------------------- 12130 12131Packed decimal (P) format floating literals are not supported. Feel 12132free to add the code! 12133 12134 The floating point formats generated by directives are these. 12135 12136`.float' 12137 `Single' precision floating point constants. 12138 12139`.double' 12140 `Double' precision floating point constants. 12141 12142`.extend' 12143`.ldouble' 12144 `Extended' precision (`long double') floating point constants. 12145 12146 12147File: as.info, Node: M68K-Directives, Next: M68K-opcodes, Prev: M68K-Float, Up: M68K-Dependent 12148 121499.21.5 680x0 Machine Directives 12150------------------------------- 12151 12152In order to be compatible with the Sun assembler the 680x0 assembler 12153understands the following directives. 12154 12155`.data1' 12156 This directive is identical to a `.data 1' directive. 12157 12158`.data2' 12159 This directive is identical to a `.data 2' directive. 12160 12161`.even' 12162 This directive is a special case of the `.align' directive; it 12163 aligns the output to an even byte boundary. 12164 12165`.skip' 12166 This directive is identical to a `.space' directive. 12167 12168`.arch NAME' 12169 Select the target architecture and extension features. Valid 12170 values for NAME are the same as for the `-march' command line 12171 option. This directive cannot be specified after any instructions 12172 have been assembled. If it is given multiple times, or in 12173 conjunction with the `-march' option, all uses must be for the 12174 same architecture and extension set. 12175 12176`.cpu NAME' 12177 Select the target cpu. Valid valuse for NAME are the same as for 12178 the `-mcpu' command line option. This directive cannot be 12179 specified after any instructions have been assembled. If it is 12180 given multiple times, or in conjunction with the `-mopt' option, 12181 all uses must be for the same cpu. 12182 12183 12184 12185File: as.info, Node: M68K-opcodes, Prev: M68K-Directives, Up: M68K-Dependent 12186 121879.21.6 Opcodes 12188-------------- 12189 12190* Menu: 12191 12192* M68K-Branch:: Branch Improvement 12193* M68K-Chars:: Special Characters 12194 12195 12196File: as.info, Node: M68K-Branch, Next: M68K-Chars, Up: M68K-opcodes 12197 121989.21.6.1 Branch Improvement 12199........................... 12200 12201Certain pseudo opcodes are permitted for branch instructions. They 12202expand to the shortest branch instruction that reach the target. 12203Generally these mnemonics are made by substituting `j' for `b' at the 12204start of a Motorola mnemonic. 12205 12206 The following table summarizes the pseudo-operations. A `*' flags 12207cases that are more fully described after the table: 12208 12209 Displacement 12210 +------------------------------------------------------------ 12211 | 68020 68000/10, not PC-relative OK 12212 Pseudo-Op |BYTE WORD LONG ABSOLUTE LONG JUMP ** 12213 +------------------------------------------------------------ 12214 jbsr |bsrs bsrw bsrl jsr 12215 jra |bras braw bral jmp 12216 * jXX |bXXs bXXw bXXl bNXs;jmp 12217 * dbXX | N/A dbXXw dbXX;bras;bral dbXX;bras;jmp 12218 fjXX | N/A fbXXw fbXXl N/A 12219 12220 XX: condition 12221 NX: negative of condition XX 12222 `*'--see full description below 12223 `**'--this expansion mode is disallowed by `--pcrel' 12224 12225`jbsr' 12226`jra' 12227 These are the simplest jump pseudo-operations; they always map to 12228 one particular machine instruction, depending on the displacement 12229 to the branch target. This instruction will be a byte or word 12230 branch is that is sufficient. Otherwise, a long branch will be 12231 emitted if available. If no long branches are available and the 12232 `--pcrel' option is not given, an absolute long jump will be 12233 emitted instead. If no long branches are available, the `--pcrel' 12234 option is given, and a word branch cannot reach the target, an 12235 error message is generated. 12236 12237 In addition to standard branch operands, `as' allows these 12238 pseudo-operations to have all operands that are allowed for jsr 12239 and jmp, substituting these instructions if the operand given is 12240 not valid for a branch instruction. 12241 12242`jXX' 12243 Here, `jXX' stands for an entire family of pseudo-operations, 12244 where XX is a conditional branch or condition-code test. The full 12245 list of pseudo-ops in this family is: 12246 jhi jls jcc jcs jne jeq jvc 12247 jvs jpl jmi jge jlt jgt jle 12248 12249 Usually, each of these pseudo-operations expands to a single branch 12250 instruction. However, if a word branch is not sufficient, no long 12251 branches are available, and the `--pcrel' option is not given, `as' 12252 issues a longer code fragment in terms of NX, the opposite 12253 condition to XX. For example, under these conditions: 12254 jXX foo 12255 gives 12256 bNXs oof 12257 jmp foo 12258 oof: 12259 12260`dbXX' 12261 The full family of pseudo-operations covered here is 12262 dbhi dbls dbcc dbcs dbne dbeq dbvc 12263 dbvs dbpl dbmi dbge dblt dbgt dble 12264 dbf dbra dbt 12265 12266 Motorola `dbXX' instructions allow word displacements only. When 12267 a word displacement is sufficient, each of these pseudo-operations 12268 expands to the corresponding Motorola instruction. When a word 12269 displacement is not sufficient and long branches are available, 12270 when the source reads `dbXX foo', `as' emits 12271 dbXX oo1 12272 bras oo2 12273 oo1:bral foo 12274 oo2: 12275 12276 If, however, long branches are not available and the `--pcrel' 12277 option is not given, `as' emits 12278 dbXX oo1 12279 bras oo2 12280 oo1:jmp foo 12281 oo2: 12282 12283`fjXX' 12284 This family includes 12285 fjne fjeq fjge fjlt fjgt fjle fjf 12286 fjt fjgl fjgle fjnge fjngl fjngle fjngt 12287 fjnle fjnlt fjoge fjogl fjogt fjole fjolt 12288 fjor fjseq fjsf fjsne fjst fjueq fjuge 12289 fjugt fjule fjult fjun 12290 12291 Each of these pseudo-operations always expands to a single Motorola 12292 coprocessor branch instruction, word or long. All Motorola 12293 coprocessor branch instructions allow both word and long 12294 displacements. 12295 12296 12297 12298File: as.info, Node: M68K-Chars, Prev: M68K-Branch, Up: M68K-opcodes 12299 123009.21.6.2 Special Characters 12301........................... 12302 12303Line comments are introduced by the `|' character appearing anywhere on 12304a line, unless the `--bitwise-or' command line option has been 12305specified. 12306 12307 An asterisk (`*') as the first character on a line marks the start 12308of a line comment as well. 12309 12310 A hash character (`#') as the first character on a line also marks 12311the start of a line comment, but in this case it could also be a 12312logical line number directive (*note Comments::) or a preprocessor 12313control command (*note Preprocessing::). If the hash character appears 12314elsewhere on a line it is used to introduce an immediate value. (This 12315is for compatibility with Sun's assembler). 12316 12317 Multiple statements on the same line can appear if they are separated 12318by the `;' character. 12319 12320 12321File: as.info, Node: M68HC11-Dependent, Next: MicroBlaze-Dependent, Prev: M68K-Dependent, Up: Machine Dependencies 12322 123239.22 M68HC11 and M68HC12 Dependent Features 12324=========================================== 12325 12326* Menu: 12327 12328* M68HC11-Opts:: M68HC11 and M68HC12 Options 12329* M68HC11-Syntax:: Syntax 12330* M68HC11-Modifiers:: Symbolic Operand Modifiers 12331* M68HC11-Directives:: Assembler Directives 12332* M68HC11-Float:: Floating Point 12333* M68HC11-opcodes:: Opcodes 12334 12335 12336File: as.info, Node: M68HC11-Opts, Next: M68HC11-Syntax, Up: M68HC11-Dependent 12337 123389.22.1 M68HC11 and M68HC12 Options 12339---------------------------------- 12340 12341The Motorola 68HC11 and 68HC12 version of `as' have a few machine 12342dependent options. 12343 12344`-m68hc11' 12345 This option switches the assembler in the M68HC11 mode. In this 12346 mode, the assembler only accepts 68HC11 operands and mnemonics. It 12347 produces code for the 68HC11. 12348 12349`-m68hc12' 12350 This option switches the assembler in the M68HC12 mode. In this 12351 mode, the assembler also accepts 68HC12 operands and mnemonics. It 12352 produces code for the 68HC12. A few 68HC11 instructions are 12353 replaced by some 68HC12 instructions as recommended by Motorola 12354 specifications. 12355 12356`-m68hcs12' 12357 This option switches the assembler in the M68HCS12 mode. This 12358 mode is similar to `-m68hc12' but specifies to assemble for the 12359 68HCS12 series. The only difference is on the assembling of the 12360 `movb' and `movw' instruction when a PC-relative operand is used. 12361 12362`-mshort' 12363 This option controls the ABI and indicates to use a 16-bit integer 12364 ABI. It has no effect on the assembled instructions. This is the 12365 default. 12366 12367`-mlong' 12368 This option controls the ABI and indicates to use a 32-bit integer 12369 ABI. 12370 12371`-mshort-double' 12372 This option controls the ABI and indicates to use a 32-bit float 12373 ABI. This is the default. 12374 12375`-mlong-double' 12376 This option controls the ABI and indicates to use a 64-bit float 12377 ABI. 12378 12379`--strict-direct-mode' 12380 You can use the `--strict-direct-mode' option to disable the 12381 automatic translation of direct page mode addressing into extended 12382 mode when the instruction does not support direct mode. For 12383 example, the `clr' instruction does not support direct page mode 12384 addressing. When it is used with the direct page mode, `as' will 12385 ignore it and generate an absolute addressing. This option 12386 prevents `as' from doing this, and the wrong usage of the direct 12387 page mode will raise an error. 12388 12389`--short-branches' 12390 The `--short-branches' option turns off the translation of 12391 relative branches into absolute branches when the branch offset is 12392 out of range. By default `as' transforms the relative branch 12393 (`bsr', `bgt', `bge', `beq', `bne', `ble', `blt', `bhi', `bcc', 12394 `bls', `bcs', `bmi', `bvs', `bvs', `bra') into an absolute branch 12395 when the offset is out of the -128 .. 127 range. In that case, 12396 the `bsr' instruction is translated into a `jsr', the `bra' 12397 instruction is translated into a `jmp' and the conditional 12398 branches instructions are inverted and followed by a `jmp'. This 12399 option disables these translations and `as' will generate an error 12400 if a relative branch is out of range. This option does not affect 12401 the optimization associated to the `jbra', `jbsr' and `jbXX' 12402 pseudo opcodes. 12403 12404`--force-long-branches' 12405 The `--force-long-branches' option forces the translation of 12406 relative branches into absolute branches. This option does not 12407 affect the optimization associated to the `jbra', `jbsr' and 12408 `jbXX' pseudo opcodes. 12409 12410`--print-insn-syntax' 12411 You can use the `--print-insn-syntax' option to obtain the syntax 12412 description of the instruction when an error is detected. 12413 12414`--print-opcodes' 12415 The `--print-opcodes' option prints the list of all the 12416 instructions with their syntax. The first item of each line 12417 represents the instruction name and the rest of the line indicates 12418 the possible operands for that instruction. The list is printed in 12419 alphabetical order. Once the list is printed `as' exits. 12420 12421`--generate-example' 12422 The `--generate-example' option is similar to `--print-opcodes' 12423 but it generates an example for each instruction instead. 12424 12425 12426File: as.info, Node: M68HC11-Syntax, Next: M68HC11-Modifiers, Prev: M68HC11-Opts, Up: M68HC11-Dependent 12427 124289.22.2 Syntax 12429------------- 12430 12431In the M68HC11 syntax, the instruction name comes first and it may be 12432followed by one or several operands (up to three). Operands are 12433separated by comma (`,'). In the normal mode, `as' will complain if too 12434many operands are specified for a given instruction. In the MRI mode 12435(turned on with `-M' option), it will treat them as comments. Example: 12436 12437 inx 12438 lda #23 12439 bset 2,x #4 12440 brclr *bot #8 foo 12441 12442 The presence of a `;' character or a `!' character anywhere on a 12443line indicates the start of a comment that extends to the end of that 12444line. 12445 12446 A `*' or a `#' character at the start of a line also introduces a 12447line comment, but these characters do not work elsewhere on the line. 12448If the first character of the line is a `#' then as well as starting a 12449comment, the line could also be logical line number directive (*note 12450Comments::) or a preprocessor control command (*note Preprocessing::). 12451 12452 The M68HC11 assembler does not currently support a line separator 12453character. 12454 12455 The following addressing modes are understood for 68HC11 and 68HC12: 12456"Immediate" 12457 `#NUMBER' 12458 12459"Address Register" 12460 `NUMBER,X', `NUMBER,Y' 12461 12462 The NUMBER may be omitted in which case 0 is assumed. 12463 12464"Direct Addressing mode" 12465 `*SYMBOL', or `*DIGITS' 12466 12467"Absolute" 12468 `SYMBOL', or `DIGITS' 12469 12470 The M68HC12 has other more complex addressing modes. All of them are 12471supported and they are represented below: 12472 12473"Constant Offset Indexed Addressing Mode" 12474 `NUMBER,REG' 12475 12476 The NUMBER may be omitted in which case 0 is assumed. The 12477 register can be either `X', `Y', `SP' or `PC'. The assembler will 12478 use the smaller post-byte definition according to the constant 12479 value (5-bit constant offset, 9-bit constant offset or 16-bit 12480 constant offset). If the constant is not known by the assembler 12481 it will use the 16-bit constant offset post-byte and the value 12482 will be resolved at link time. 12483 12484"Offset Indexed Indirect" 12485 `[NUMBER,REG]' 12486 12487 The register can be either `X', `Y', `SP' or `PC'. 12488 12489"Auto Pre-Increment/Pre-Decrement/Post-Increment/Post-Decrement" 12490 `NUMBER,-REG' `NUMBER,+REG' `NUMBER,REG-' `NUMBER,REG+' 12491 12492 The number must be in the range `-8'..`+8' and must not be 0. The 12493 register can be either `X', `Y', `SP' or `PC'. 12494 12495"Accumulator Offset" 12496 `ACC,REG' 12497 12498 The accumulator register can be either `A', `B' or `D'. The 12499 register can be either `X', `Y', `SP' or `PC'. 12500 12501"Accumulator D offset indexed-indirect" 12502 `[D,REG]' 12503 12504 The register can be either `X', `Y', `SP' or `PC'. 12505 12506 12507 For example: 12508 12509 ldab 1024,sp 12510 ldd [10,x] 12511 orab 3,+x 12512 stab -2,y- 12513 ldx a,pc 12514 sty [d,sp] 12515 12516 12517File: as.info, Node: M68HC11-Modifiers, Next: M68HC11-Directives, Prev: M68HC11-Syntax, Up: M68HC11-Dependent 12518 125199.22.3 Symbolic Operand Modifiers 12520--------------------------------- 12521 12522The assembler supports several modifiers when using symbol addresses in 1252368HC11 and 68HC12 instruction operands. The general syntax is the 12524following: 12525 12526 %modifier(symbol) 12527 12528`%addr' 12529 This modifier indicates to the assembler and linker to use the 12530 16-bit physical address corresponding to the symbol. This is 12531 intended to be used on memory window systems to map a symbol in 12532 the memory bank window. If the symbol is in a memory expansion 12533 part, the physical address corresponds to the symbol address 12534 within the memory bank window. If the symbol is not in a memory 12535 expansion part, this is the symbol address (using or not using the 12536 %addr modifier has no effect in that case). 12537 12538`%page' 12539 This modifier indicates to use the memory page number corresponding 12540 to the symbol. If the symbol is in a memory expansion part, its 12541 page number is computed by the linker as a number used to map the 12542 page containing the symbol in the memory bank window. If the 12543 symbol is not in a memory expansion part, the page number is 0. 12544 12545`%hi' 12546 This modifier indicates to use the 8-bit high part of the physical 12547 address of the symbol. 12548 12549`%lo' 12550 This modifier indicates to use the 8-bit low part of the physical 12551 address of the symbol. 12552 12553 12554 For example a 68HC12 call to a function `foo_example' stored in 12555memory expansion part could be written as follows: 12556 12557 call %addr(foo_example),%page(foo_example) 12558 12559 and this is equivalent to 12560 12561 call foo_example 12562 12563 And for 68HC11 it could be written as follows: 12564 12565 ldab #%page(foo_example) 12566 stab _page_switch 12567 jsr %addr(foo_example) 12568 12569 12570File: as.info, Node: M68HC11-Directives, Next: M68HC11-Float, Prev: M68HC11-Modifiers, Up: M68HC11-Dependent 12571 125729.22.4 Assembler Directives 12573--------------------------- 12574 12575The 68HC11 and 68HC12 version of `as' have the following specific 12576assembler directives: 12577 12578`.relax' 12579 The relax directive is used by the `GNU Compiler' to emit a 12580 specific relocation to mark a group of instructions for linker 12581 relaxation. The sequence of instructions within the group must be 12582 known to the linker so that relaxation can be performed. 12583 12584`.mode [mshort|mlong|mshort-double|mlong-double]' 12585 This directive specifies the ABI. It overrides the `-mshort', 12586 `-mlong', `-mshort-double' and `-mlong-double' options. 12587 12588`.far SYMBOL' 12589 This directive marks the symbol as a `far' symbol meaning that it 12590 uses a `call/rtc' calling convention as opposed to `jsr/rts'. 12591 During a final link, the linker will identify references to the 12592 `far' symbol and will verify the proper calling convention. 12593 12594`.interrupt SYMBOL' 12595 This directive marks the symbol as an interrupt entry point. This 12596 information is then used by the debugger to correctly unwind the 12597 frame across interrupts. 12598 12599`.xrefb SYMBOL' 12600 This directive is defined for compatibility with the 12601 `Specification for Motorola 8 and 16-Bit Assembly Language Input 12602 Standard' and is ignored. 12603 12604 12605 12606File: as.info, Node: M68HC11-Float, Next: M68HC11-opcodes, Prev: M68HC11-Directives, Up: M68HC11-Dependent 12607 126089.22.5 Floating Point 12609--------------------- 12610 12611Packed decimal (P) format floating literals are not supported. Feel 12612free to add the code! 12613 12614 The floating point formats generated by directives are these. 12615 12616`.float' 12617 `Single' precision floating point constants. 12618 12619`.double' 12620 `Double' precision floating point constants. 12621 12622`.extend' 12623`.ldouble' 12624 `Extended' precision (`long double') floating point constants. 12625 12626 12627File: as.info, Node: M68HC11-opcodes, Prev: M68HC11-Float, Up: M68HC11-Dependent 12628 126299.22.6 Opcodes 12630-------------- 12631 12632* Menu: 12633 12634* M68HC11-Branch:: Branch Improvement 12635 12636 12637File: as.info, Node: M68HC11-Branch, Up: M68HC11-opcodes 12638 126399.22.6.1 Branch Improvement 12640........................... 12641 12642Certain pseudo opcodes are permitted for branch instructions. They 12643expand to the shortest branch instruction that reach the target. 12644Generally these mnemonics are made by prepending `j' to the start of 12645Motorola mnemonic. These pseudo opcodes are not affected by the 12646`--short-branches' or `--force-long-branches' options. 12647 12648 The following table summarizes the pseudo-operations. 12649 12650 Displacement Width 12651 +-------------------------------------------------------------+ 12652 | Options | 12653 | --short-branches --force-long-branches | 12654 +--------------------------+----------------------------------+ 12655 Op |BYTE WORD | BYTE WORD | 12656 +--------------------------+----------------------------------+ 12657 bsr | bsr <pc-rel> <error> | jsr <abs> | 12658 bra | bra <pc-rel> <error> | jmp <abs> | 12659 jbsr | bsr <pc-rel> jsr <abs> | bsr <pc-rel> jsr <abs> | 12660 jbra | bra <pc-rel> jmp <abs> | bra <pc-rel> jmp <abs> | 12661 bXX | bXX <pc-rel> <error> | bNX +3; jmp <abs> | 12662 jbXX | bXX <pc-rel> bNX +3; | bXX <pc-rel> bNX +3; jmp <abs> | 12663 | jmp <abs> | | 12664 +--------------------------+----------------------------------+ 12665 XX: condition 12666 NX: negative of condition XX 12667 12668`jbsr' 12669`jbra' 12670 These are the simplest jump pseudo-operations; they always map to 12671 one particular machine instruction, depending on the displacement 12672 to the branch target. 12673 12674`jbXX' 12675 Here, `jbXX' stands for an entire family of pseudo-operations, 12676 where XX is a conditional branch or condition-code test. The full 12677 list of pseudo-ops in this family is: 12678 jbcc jbeq jbge jbgt jbhi jbvs jbpl jblo 12679 jbcs jbne jblt jble jbls jbvc jbmi 12680 12681 For the cases of non-PC relative displacements and long 12682 displacements, `as' issues a longer code fragment in terms of NX, 12683 the opposite condition to XX. For example, for the non-PC 12684 relative case: 12685 jbXX foo 12686 gives 12687 bNXs oof 12688 jmp foo 12689 oof: 12690 12691 12692 12693File: as.info, Node: MicroBlaze-Dependent, Next: MIPS-Dependent, Prev: M68HC11-Dependent, Up: Machine Dependencies 12694 126959.23 MicroBlaze Dependent Features 12696================================== 12697 12698 The Xilinx MicroBlaze processor family includes several variants, 12699all using the same core instruction set. This chapter covers features 12700of the GNU assembler that are specific to the MicroBlaze architecture. 12701For details about the MicroBlaze instruction set, please see the 12702`MicroBlaze Processor Reference Guide (UG081)' available at 12703www.xilinx.com. 12704 12705* Menu: 12706 12707* MicroBlaze Directives:: Directives for MicroBlaze Processors. 12708* MicroBlaze Syntax:: Syntax for the MicroBlaze 12709 12710 12711File: as.info, Node: MicroBlaze Directives, Next: MicroBlaze Syntax, Up: MicroBlaze-Dependent 12712 127139.23.1 Directives 12714----------------- 12715 12716A number of assembler directives are available for MicroBlaze. 12717 12718`.data8 EXPRESSION,...' 12719 This directive is an alias for `.byte'. Each expression is 12720 assembled into an eight-bit value. 12721 12722`.data16 EXPRESSION,...' 12723 This directive is an alias for `.hword'. Each expression is 12724 assembled into an 16-bit value. 12725 12726`.data32 EXPRESSION,...' 12727 This directive is an alias for `.word'. Each expression is 12728 assembled into an 32-bit value. 12729 12730`.ent NAME[,LABEL]' 12731 This directive is an alias for `.func' denoting the start of 12732 function NAME at (optional) LABEL. 12733 12734`.end NAME[,LABEL]' 12735 This directive is an alias for `.endfunc' denoting the end of 12736 function NAME. 12737 12738`.gpword LABEL,...' 12739 This directive is an alias for `.rva'. The resolved address of 12740 LABEL is stored in the data section. 12741 12742`.weakext LABEL' 12743 Declare that LABEL is a weak external symbol. 12744 12745`.rodata' 12746 Switch to .rodata section. Equivalent to `.section .rodata' 12747 12748`.sdata2' 12749 Switch to .sdata2 section. Equivalent to `.section .sdata2' 12750 12751`.sdata' 12752 Switch to .sdata section. Equivalent to `.section .sdata' 12753 12754`.bss' 12755 Switch to .bss section. Equivalent to `.section .bss' 12756 12757`.sbss' 12758 Switch to .sbss section. Equivalent to `.section .sbss' 12759 12760 12761File: as.info, Node: MicroBlaze Syntax, Prev: MicroBlaze Directives, Up: MicroBlaze-Dependent 12762 127639.23.2 Syntax for the MicroBlaze 12764-------------------------------- 12765 12766* Menu: 12767 12768* MicroBlaze-Chars:: Special Characters 12769 12770 12771File: as.info, Node: MicroBlaze-Chars, Up: MicroBlaze Syntax 12772 127739.23.2.1 Special Characters 12774........................... 12775 12776The presence of a `#' on a line indicates the start of a comment that 12777extends to the end of the current line. 12778 12779 If a `#' appears as the first character of a line, the whole line is 12780treated as a comment, but in this case the line can also be a logical 12781line number directive (*note Comments::) or a preprocessor control 12782command (*note Preprocessing::). 12783 12784 The `;' character can be used to separate statements on the same 12785line. 12786 12787 12788File: as.info, Node: MIPS-Dependent, Next: MMIX-Dependent, Prev: MicroBlaze-Dependent, Up: Machine Dependencies 12789 127909.24 MIPS Dependent Features 12791============================ 12792 12793 GNU `as' for MIPS architectures supports several different MIPS 12794processors, and MIPS ISA levels I through V, MIPS32, and MIPS64. For 12795information about the MIPS instruction set, see `MIPS RISC 12796Architecture', by Kane and Heindrich (Prentice-Hall). For an overview 12797of MIPS assembly conventions, see "Appendix D: Assembly Language 12798Programming" in the same work. 12799 12800* Menu: 12801 12802* MIPS Opts:: Assembler options 12803* MIPS Object:: ECOFF object code 12804* MIPS Stabs:: Directives for debugging information 12805* MIPS ISA:: Directives to override the ISA level 12806* MIPS assembly options:: Directives to control code generation 12807* MIPS symbol sizes:: Directives to override the size of symbols 12808* MIPS autoextend:: Directives for extending MIPS 16 bit instructions 12809* MIPS insn:: Directive to mark data as an instruction 12810* MIPS option stack:: Directives to save and restore options 12811* MIPS ASE instruction generation overrides:: Directives to control 12812 generation of MIPS ASE instructions 12813* MIPS floating-point:: Directives to override floating-point options 12814* MIPS Syntax:: MIPS specific syntactical considerations 12815 12816 12817File: as.info, Node: MIPS Opts, Next: MIPS Object, Up: MIPS-Dependent 12818 128199.24.1 Assembler options 12820------------------------ 12821 12822The MIPS configurations of GNU `as' support these special options: 12823 12824`-G NUM' 12825 This option sets the largest size of an object that can be 12826 referenced implicitly with the `gp' register. It is only accepted 12827 for targets that use ECOFF format. The default value is 8. 12828 12829`-EB' 12830`-EL' 12831 Any MIPS configuration of `as' can select big-endian or 12832 little-endian output at run time (unlike the other GNU development 12833 tools, which must be configured for one or the other). Use `-EB' 12834 to select big-endian output, and `-EL' for little-endian. 12835 12836`-KPIC' 12837 Generate SVR4-style PIC. This option tells the assembler to 12838 generate SVR4-style position-independent macro expansions. It 12839 also tells the assembler to mark the output file as PIC. 12840 12841`-mvxworks-pic' 12842 Generate VxWorks PIC. This option tells the assembler to generate 12843 VxWorks-style position-independent macro expansions. 12844 12845`-mips1' 12846`-mips2' 12847`-mips3' 12848`-mips4' 12849`-mips5xo' 12850`-mips32' 12851`-mips32r2' 12852`-mips64' 12853`-mips64r2' 12854 Generate code for a particular MIPS Instruction Set Architecture 12855 level. `-mips1' corresponds to the R2000 and R3000 processors, 12856 `-mips2' to the R6000 processor, `-mips3' to the R4000 processor, 12857 and `-mips4' to the R8000 and R10000 processors. `-mips5', 12858 `-mips32', `-mips32r2', `-mips64', and `-mips64r2' correspond to 12859 generic MIPS V, MIPS32, MIPS32 RELEASE 2, MIPS64, and MIPS64 12860 RELEASE 2 ISA processors, respectively. You can also switch 12861 instruction sets during the assembly; see *note Directives to 12862 override the ISA level: MIPS ISA. 12863 12864`-mgp32' 12865`-mfp32' 12866 Some macros have different expansions for 32-bit and 64-bit 12867 registers. The register sizes are normally inferred from the ISA 12868 and ABI, but these flags force a certain group of registers to be 12869 treated as 32 bits wide at all times. `-mgp32' controls the size 12870 of general-purpose registers and `-mfp32' controls the size of 12871 floating-point registers. 12872 12873 The `.set gp=32' and `.set fp=32' directives allow the size of 12874 registers to be changed for parts of an object. The default value 12875 is restored by `.set gp=default' and `.set fp=default'. 12876 12877 On some MIPS variants there is a 32-bit mode flag; when this flag 12878 is set, 64-bit instructions generate a trap. Also, some 32-bit 12879 OSes only save the 32-bit registers on a context switch, so it is 12880 essential never to use the 64-bit registers. 12881 12882`-mgp64' 12883`-mfp64' 12884 Assume that 64-bit registers are available. This is provided in 12885 the interests of symmetry with `-mgp32' and `-mfp32'. 12886 12887 The `.set gp=64' and `.set fp=64' directives allow the size of 12888 registers to be changed for parts of an object. The default value 12889 is restored by `.set gp=default' and `.set fp=default'. 12890 12891`-mips16' 12892`-no-mips16' 12893 Generate code for the MIPS 16 processor. This is equivalent to 12894 putting `.set mips16' at the start of the assembly file. 12895 `-no-mips16' turns off this option. 12896 12897`-mmicromips' 12898`-mno-micromips' 12899 Generate code for the microMIPS processor. This is equivalent to 12900 putting `.set micromips' at the start of the assembly file. 12901 `-mno-micromips' turns off this option. This is equivalent to 12902 putting `.set nomicromips' at the start of the assembly file. 12903 12904`-msmartmips' 12905`-mno-smartmips' 12906 Enables the SmartMIPS extensions to the MIPS32 instruction set, 12907 which provides a number of new instructions which target smartcard 12908 and cryptographic applications. This is equivalent to putting 12909 `.set smartmips' at the start of the assembly file. 12910 `-mno-smartmips' turns off this option. 12911 12912`-mips3d' 12913`-no-mips3d' 12914 Generate code for the MIPS-3D Application Specific Extension. 12915 This tells the assembler to accept MIPS-3D instructions. 12916 `-no-mips3d' turns off this option. 12917 12918`-mdmx' 12919`-no-mdmx' 12920 Generate code for the MDMX Application Specific Extension. This 12921 tells the assembler to accept MDMX instructions. `-no-mdmx' turns 12922 off this option. 12923 12924`-mdsp' 12925`-mno-dsp' 12926 Generate code for the DSP Release 1 Application Specific Extension. 12927 This tells the assembler to accept DSP Release 1 instructions. 12928 `-mno-dsp' turns off this option. 12929 12930`-mdspr2' 12931`-mno-dspr2' 12932 Generate code for the DSP Release 2 Application Specific Extension. 12933 This option implies -mdsp. This tells the assembler to accept DSP 12934 Release 2 instructions. `-mno-dspr2' turns off this option. 12935 12936`-mmt' 12937`-mno-mt' 12938 Generate code for the MT Application Specific Extension. This 12939 tells the assembler to accept MT instructions. `-mno-mt' turns 12940 off this option. 12941 12942`-mmcu' 12943`-mno-mcu' 12944 Generate code for the MCU Application Specific Extension. This 12945 tells the assembler to accept MCU instructions. `-mno-mcu' turns 12946 off this option. 12947 12948`-minsn32' 12949`-mno-insn32' 12950 Only use 32-bit instruction encodings when generating code for the 12951 microMIPS processor. This option inhibits the use of any 16-bit 12952 instructions. This is equivalent to putting `.set insn32' at the 12953 start of the assembly file. `-mno-insn32' turns off this option. 12954 This is equivalent to putting `.set noinsn32' at the start of the 12955 assembly file. By default `-mno-insn32' is selected, allowing all 12956 instructions to be used. 12957 12958`-mfix7000' 12959`-mno-fix7000' 12960 Cause nops to be inserted if the read of the destination register 12961 of an mfhi or mflo instruction occurs in the following two 12962 instructions. 12963 12964`-mfix-loongson2f-jump' 12965`-mno-fix-loongson2f-jump' 12966 Eliminate instruction fetch from outside 256M region to work 12967 around the Loongson2F `jump' instructions. Without it, under 12968 extreme cases, the kernel may crash. The issue has been solved in 12969 latest processor batches, but this fix has no side effect to them. 12970 12971`-mfix-loongson2f-nop' 12972`-mno-fix-loongson2f-nop' 12973 Replace nops by `or at,at,zero' to work around the Loongson2F 12974 `nop' errata. Without it, under extreme cases, cpu might 12975 deadlock. The issue has been solved in latest loongson2f batches, 12976 but this fix has no side effect to them. 12977 12978`-mfix-vr4120' 12979`-mno-fix-vr4120' 12980 Insert nops to work around certain VR4120 errata. This option is 12981 intended to be used on GCC-generated code: it is not designed to 12982 catch all problems in hand-written assembler code. 12983 12984`-mfix-vr4130' 12985`-mno-fix-vr4130' 12986 Insert nops to work around the VR4130 `mflo'/`mfhi' errata. 12987 12988`-mfix-24k' 12989`-no-mfix-24k' 12990 Insert nops to work around the 24K `eret'/`deret' errata. 12991 12992`-mfix-cn63xxp1' 12993`-mno-fix-cn63xxp1' 12994 Replace `pref' hints 0 - 4 and 6 - 24 with hint 28 to work around 12995 certain CN63XXP1 errata. 12996 12997`-m4010' 12998`-no-m4010' 12999 Generate code for the LSI R4010 chip. This tells the assembler to 13000 accept the R4010 specific instructions (`addciu', `ffc', etc.), 13001 and to not schedule `nop' instructions around accesses to the `HI' 13002 and `LO' registers. `-no-m4010' turns off this option. 13003 13004`-m4650' 13005`-no-m4650' 13006 Generate code for the MIPS R4650 chip. This tells the assembler 13007 to accept the `mad' and `madu' instruction, and to not schedule 13008 `nop' instructions around accesses to the `HI' and `LO' registers. 13009 `-no-m4650' turns off this option. 13010 13011`-m3900' 13012`-no-m3900' 13013`-m4100' 13014`-no-m4100' 13015 For each option `-mNNNN', generate code for the MIPS RNNNN chip. 13016 This tells the assembler to accept instructions specific to that 13017 chip, and to schedule for that chip's hazards. 13018 13019`-march=CPU' 13020 Generate code for a particular MIPS cpu. It is exactly equivalent 13021 to `-mCPU', except that there are more value of CPU understood. 13022 Valid CPU value are: 13023 13024 2000, 3000, 3900, 4000, 4010, 4100, 4111, vr4120, vr4130, 13025 vr4181, 4300, 4400, 4600, 4650, 5000, rm5200, rm5230, rm5231, 13026 rm5261, rm5721, vr5400, vr5500, 6000, rm7000, 8000, rm9000, 13027 10000, 12000, 14000, 16000, 4kc, 4km, 4kp, 4ksc, 4kec, 4kem, 13028 4kep, 4ksd, m4k, m4kp, m14k, m14kc, m14ke, m14kec, 24kc, 13029 24kf2_1, 24kf, 24kf1_1, 24kec, 24kef2_1, 24kef, 24kef1_1, 13030 34kc, 34kf2_1, 34kf, 34kf1_1, 74kc, 74kf2_1, 74kf, 74kf1_1, 13031 74kf3_2, 1004kc, 1004kf2_1, 1004kf, 1004kf1_1, 5kc, 5kf, 20kc, 13032 25kf, sb1, sb1a, loongson2e, loongson2f, loongson3a, octeon, 13033 xlr 13034 13035 For compatibility reasons, `Nx' and `Bfx' are accepted as synonyms 13036 for `Nf1_1'. These values are deprecated. 13037 13038`-mtune=CPU' 13039 Schedule and tune for a particular MIPS cpu. Valid CPU values are 13040 identical to `-march=CPU'. 13041 13042`-mabi=ABI' 13043 Record which ABI the source code uses. The recognized arguments 13044 are: `32', `n32', `o64', `64' and `eabi'. 13045 13046`-msym32' 13047`-mno-sym32' 13048 Equivalent to adding `.set sym32' or `.set nosym32' to the 13049 beginning of the assembler input. *Note MIPS symbol sizes::. 13050 13051`-nocpp' 13052 This option is ignored. It is accepted for command-line 13053 compatibility with other assemblers, which use it to turn off C 13054 style preprocessing. With GNU `as', there is no need for 13055 `-nocpp', because the GNU assembler itself never runs the C 13056 preprocessor. 13057 13058`-msoft-float' 13059`-mhard-float' 13060 Disable or enable floating-point instructions. Note that by 13061 default floating-point instructions are always allowed even with 13062 CPU targets that don't have support for these instructions. 13063 13064`-msingle-float' 13065`-mdouble-float' 13066 Disable or enable double-precision floating-point operations. Note 13067 that by default double-precision floating-point operations are 13068 always allowed even with CPU targets that don't have support for 13069 these operations. 13070 13071`--construct-floats' 13072`--no-construct-floats' 13073 The `--no-construct-floats' option disables the construction of 13074 double width floating point constants by loading the two halves of 13075 the value into the two single width floating point registers that 13076 make up the double width register. This feature is useful if the 13077 processor support the FR bit in its status register, and this bit 13078 is known (by the programmer) to be set. This bit prevents the 13079 aliasing of the double width register by the single width 13080 registers. 13081 13082 By default `--construct-floats' is selected, allowing construction 13083 of these floating point constants. 13084 13085`--trap' 13086`--no-break' 13087 `as' automatically macro expands certain division and 13088 multiplication instructions to check for overflow and division by 13089 zero. This option causes `as' to generate code to take a trap 13090 exception rather than a break exception when an error is detected. 13091 The trap instructions are only supported at Instruction Set 13092 Architecture level 2 and higher. 13093 13094`--break' 13095`--no-trap' 13096 Generate code to take a break exception rather than a trap 13097 exception when an error is detected. This is the default. 13098 13099`-mpdr' 13100`-mno-pdr' 13101 Control generation of `.pdr' sections. Off by default on IRIX, on 13102 elsewhere. 13103 13104`-mshared' 13105`-mno-shared' 13106 When generating code using the Unix calling conventions (selected 13107 by `-KPIC' or `-mcall_shared'), gas will normally generate code 13108 which can go into a shared library. The `-mno-shared' option 13109 tells gas to generate code which uses the calling convention, but 13110 can not go into a shared library. The resulting code is slightly 13111 more efficient. This option only affects the handling of the 13112 `.cpload' and `.cpsetup' pseudo-ops. 13113 13114 13115File: as.info, Node: MIPS Object, Next: MIPS Stabs, Prev: MIPS Opts, Up: MIPS-Dependent 13116 131179.24.2 MIPS ECOFF object code 13118----------------------------- 13119 13120Assembling for a MIPS ECOFF target supports some additional sections 13121besides the usual `.text', `.data' and `.bss'. The additional sections 13122are `.rdata', used for read-only data, `.sdata', used for small data, 13123and `.sbss', used for small common objects. 13124 13125 When assembling for ECOFF, the assembler uses the `$gp' (`$28') 13126register to form the address of a "small object". Any object in the 13127`.sdata' or `.sbss' sections is considered "small" in this sense. For 13128external objects, or for objects in the `.bss' section, you can use the 13129`gcc' `-G' option to control the size of objects addressed via `$gp'; 13130the default value is 8, meaning that a reference to any object eight 13131bytes or smaller uses `$gp'. Passing `-G 0' to `as' prevents it from 13132using the `$gp' register on the basis of object size (but the assembler 13133uses `$gp' for objects in `.sdata' or `sbss' in any case). The size of 13134an object in the `.bss' section is set by the `.comm' or `.lcomm' 13135directive that defines it. The size of an external object may be set 13136with the `.extern' directive. For example, `.extern sym,4' declares 13137that the object at `sym' is 4 bytes in length, whie leaving `sym' 13138otherwise undefined. 13139 13140 Using small ECOFF objects requires linker support, and assumes that 13141the `$gp' register is correctly initialized (normally done 13142automatically by the startup code). MIPS ECOFF assembly code must not 13143modify the `$gp' register. 13144 13145 13146File: as.info, Node: MIPS Stabs, Next: MIPS ISA, Prev: MIPS Object, Up: MIPS-Dependent 13147 131489.24.3 Directives for debugging information 13149------------------------------------------- 13150 13151MIPS ECOFF `as' supports several directives used for generating 13152debugging information which are not support by traditional MIPS 13153assemblers. These are `.def', `.endef', `.dim', `.file', `.scl', 13154`.size', `.tag', `.type', `.val', `.stabd', `.stabn', and `.stabs'. 13155The debugging information generated by the three `.stab' directives can 13156only be read by GDB, not by traditional MIPS debuggers (this 13157enhancement is required to fully support C++ debugging). These 13158directives are primarily used by compilers, not assembly language 13159programmers! 13160 13161 13162File: as.info, Node: MIPS symbol sizes, Next: MIPS autoextend, Prev: MIPS assembly options, Up: MIPS-Dependent 13163 131649.24.4 Directives to override the size of symbols 13165------------------------------------------------- 13166 13167The n64 ABI allows symbols to have any 64-bit value. Although this 13168provides a great deal of flexibility, it means that some macros have 13169much longer expansions than their 32-bit counterparts. For example, 13170the non-PIC expansion of `dla $4,sym' is usually: 13171 13172 lui $4,%highest(sym) 13173 lui $1,%hi(sym) 13174 daddiu $4,$4,%higher(sym) 13175 daddiu $1,$1,%lo(sym) 13176 dsll32 $4,$4,0 13177 daddu $4,$4,$1 13178 13179 whereas the 32-bit expansion is simply: 13180 13181 lui $4,%hi(sym) 13182 daddiu $4,$4,%lo(sym) 13183 13184 n64 code is sometimes constructed in such a way that all symbolic 13185constants are known to have 32-bit values, and in such cases, it's 13186preferable to use the 32-bit expansion instead of the 64-bit expansion. 13187 13188 You can use the `.set sym32' directive to tell the assembler that, 13189from this point on, all expressions of the form `SYMBOL' or `SYMBOL + 13190OFFSET' have 32-bit values. For example: 13191 13192 .set sym32 13193 dla $4,sym 13194 lw $4,sym+16 13195 sw $4,sym+0x8000($4) 13196 13197 will cause the assembler to treat `sym', `sym+16' and `sym+0x8000' 13198as 32-bit values. The handling of non-symbolic addresses is not 13199affected. 13200 13201 The directive `.set nosym32' ends a `.set sym32' block and reverts 13202to the normal behavior. It is also possible to change the symbol size 13203using the command-line options `-msym32' and `-mno-sym32'. 13204 13205 These options and directives are always accepted, but at present, 13206they have no effect for anything other than n64. 13207 13208 13209File: as.info, Node: MIPS ISA, Next: MIPS assembly options, Prev: MIPS Stabs, Up: MIPS-Dependent 13210 132119.24.5 Directives to override the ISA level 13212------------------------------------------- 13213 13214GNU `as' supports an additional directive to change the MIPS 13215Instruction Set Architecture level on the fly: `.set mipsN'. N should 13216be a number from 0 to 5, or 32, 32r2, 64 or 64r2. The values other 13217than 0 make the assembler accept instructions for the corresponding ISA 13218level, from that point on in the assembly. `.set mipsN' affects not 13219only which instructions are permitted, but also how certain macros are 13220expanded. `.set mips0' restores the ISA level to its original level: 13221either the level you selected with command line options, or the default 13222for your configuration. You can use this feature to permit specific 13223MIPS3 instructions while assembling in 32 bit mode. Use this directive 13224with care! 13225 13226 The `.set arch=CPU' directive provides even finer control. It 13227changes the effective CPU target and allows the assembler to use 13228instructions specific to a particular CPU. All CPUs supported by the 13229`-march' command line option are also selectable by this directive. 13230The original value is restored by `.set arch=default'. 13231 13232 The directive `.set mips16' puts the assembler into MIPS 16 mode, in 13233which it will assemble instructions for the MIPS 16 processor. Use 13234`.set nomips16' to return to normal 32 bit mode. 13235 13236 Traditional MIPS assemblers do not support this directive. 13237 13238 The directive `.set micromips' puts the assembler into microMIPS 13239mode, in which it will assemble instructions for the microMIPS 13240processor. Use `.set nomicromips' to return to normal 32 bit mode. 13241 13242 Traditional MIPS assemblers do not support this directive. 13243 13244 13245File: as.info, Node: MIPS assembly options, Next: MIPS symbol sizes, Prev: MIPS ISA, Up: MIPS-Dependent 13246 132479.24.6 Directives to control code generation 13248-------------------------------------------- 13249 13250The directive `.set insn32' makes the assembler only use 32-bit 13251instruction encodings when generating code for the microMIPS processor. 13252This directive inhibits the use of any 16-bit instructions from that 13253point on in the assembly. The `.set noinsn32' directive allows 16-bit 13254instructions to be accepted. 13255 13256 Traditional MIPS assemblers do not support this directive. 13257 13258 13259File: as.info, Node: MIPS autoextend, Next: MIPS insn, Prev: MIPS symbol sizes, Up: MIPS-Dependent 13260 132619.24.7 Directives for extending MIPS 16 bit instructions 13262-------------------------------------------------------- 13263 13264By default, MIPS 16 instructions are automatically extended to 32 bits 13265when necessary. The directive `.set noautoextend' will turn this off. 13266When `.set noautoextend' is in effect, any 32 bit instruction must be 13267explicitly extended with the `.e' modifier (e.g., `li.e $4,1000'). The 13268directive `.set autoextend' may be used to once again automatically 13269extend instructions when necessary. 13270 13271 This directive is only meaningful when in MIPS 16 mode. Traditional 13272MIPS assemblers do not support this directive. 13273 13274 13275File: as.info, Node: MIPS insn, Next: MIPS option stack, Prev: MIPS autoextend, Up: MIPS-Dependent 13276 132779.24.8 Directive to mark data as an instruction 13278----------------------------------------------- 13279 13280The `.insn' directive tells `as' that the following data is actually 13281instructions. This makes a difference in MIPS 16 and microMIPS modes: 13282when loading the address of a label which precedes instructions, `as' 13283automatically adds 1 to the value, so that jumping to the loaded 13284address will do the right thing. 13285 13286 The `.global' and `.globl' directives supported by `as' will by 13287default mark the symbol as pointing to a region of data not code. This 13288means that, for example, any instructions following such a symbol will 13289not be disassembled by `objdump' as it will regard them as data. To 13290change this behaviour an optional section name can be placed after the 13291symbol name in the `.global' directive. If this section exists and is 13292known to be a code section, then the symbol will be marked as poiting at 13293code not data. Ie the syntax for the directive is: 13294 13295 `.global SYMBOL[ SECTION][, SYMBOL[ SECTION]] ...', 13296 13297 Here is a short example: 13298 13299 .global foo .text, bar, baz .data 13300 foo: 13301 nop 13302 bar: 13303 .word 0x0 13304 baz: 13305 .word 0x1 13306 13307 13308File: as.info, Node: MIPS option stack, Next: MIPS ASE instruction generation overrides, Prev: MIPS insn, Up: MIPS-Dependent 13309 133109.24.9 Directives to save and restore options 13311--------------------------------------------- 13312 13313The directives `.set push' and `.set pop' may be used to save and 13314restore the current settings for all the options which are controlled 13315by `.set'. The `.set push' directive saves the current settings on a 13316stack. The `.set pop' directive pops the stack and restores the 13317settings. 13318 13319 These directives can be useful inside an macro which must change an 13320option such as the ISA level or instruction reordering but does not want 13321to change the state of the code which invoked the macro. 13322 13323 Traditional MIPS assemblers do not support these directives. 13324 13325 13326File: as.info, Node: MIPS ASE instruction generation overrides, Next: MIPS floating-point, Prev: MIPS option stack, Up: MIPS-Dependent 13327 133289.24.10 Directives to control generation of MIPS ASE instructions 13329----------------------------------------------------------------- 13330 13331The directive `.set mips3d' makes the assembler accept instructions 13332from the MIPS-3D Application Specific Extension from that point on in 13333the assembly. The `.set nomips3d' directive prevents MIPS-3D 13334instructions from being accepted. 13335 13336 The directive `.set smartmips' makes the assembler accept 13337instructions from the SmartMIPS Application Specific Extension to the 13338MIPS32 ISA from that point on in the assembly. The `.set nosmartmips' 13339directive prevents SmartMIPS instructions from being accepted. 13340 13341 The directive `.set mdmx' makes the assembler accept instructions 13342from the MDMX Application Specific Extension from that point on in the 13343assembly. The `.set nomdmx' directive prevents MDMX instructions from 13344being accepted. 13345 13346 The directive `.set dsp' makes the assembler accept instructions 13347from the DSP Release 1 Application Specific Extension from that point 13348on in the assembly. The `.set nodsp' directive prevents DSP Release 1 13349instructions from being accepted. 13350 13351 The directive `.set dspr2' makes the assembler accept instructions 13352from the DSP Release 2 Application Specific Extension from that point 13353on in the assembly. This dirctive implies `.set dsp'. The `.set 13354nodspr2' directive prevents DSP Release 2 instructions from being 13355accepted. 13356 13357 The directive `.set mt' makes the assembler accept instructions from 13358the MT Application Specific Extension from that point on in the 13359assembly. The `.set nomt' directive prevents MT instructions from 13360being accepted. 13361 13362 The directive `.set mcu' makes the assembler accept instructions 13363from the MCU Application Specific Extension from that point on in the 13364assembly. The `.set nomcu' directive prevents MCU instructions from 13365being accepted. 13366 13367 Traditional MIPS assemblers do not support these directives. 13368 13369 13370File: as.info, Node: MIPS floating-point, Next: MIPS Syntax, Prev: MIPS ASE instruction generation overrides, Up: MIPS-Dependent 13371 133729.24.11 Directives to override floating-point options 13373----------------------------------------------------- 13374 13375The directives `.set softfloat' and `.set hardfloat' provide finer 13376control of disabling and enabling float-point instructions. These 13377directives always override the default (that hard-float instructions 13378are accepted) or the command-line options (`-msoft-float' and 13379`-mhard-float'). 13380 13381 The directives `.set singlefloat' and `.set doublefloat' provide 13382finer control of disabling and enabling double-precision float-point 13383operations. These directives always override the default (that 13384double-precision operations are accepted) or the command-line options 13385(`-msingle-float' and `-mdouble-float'). 13386 13387 Traditional MIPS assemblers do not support these directives. 13388 13389 13390File: as.info, Node: MIPS Syntax, Prev: MIPS floating-point, Up: MIPS-Dependent 13391 133929.24.12 Syntactical considerations for the MIPS assembler 13393--------------------------------------------------------- 13394 13395* Menu: 13396 13397* MIPS-Chars:: Special Characters 13398 13399 13400File: as.info, Node: MIPS-Chars, Up: MIPS Syntax 13401 134029.24.12.1 Special Characters 13403............................ 13404 13405The presence of a `#' on a line indicates the start of a comment that 13406extends to the end of the current line. 13407 13408 If a `#' appears as the first character of a line, the whole line is 13409treated as a comment, but in this case the line can also be a logical 13410line number directive (*note Comments::) or a preprocessor control 13411command (*note Preprocessing::). 13412 13413 The `;' character can be used to separate statements on the same 13414line. 13415 13416 13417File: as.info, Node: MMIX-Dependent, Next: MSP430-Dependent, Prev: MIPS-Dependent, Up: Machine Dependencies 13418 134199.25 MMIX Dependent Features 13420============================ 13421 13422* Menu: 13423 13424* MMIX-Opts:: Command-line Options 13425* MMIX-Expand:: Instruction expansion 13426* MMIX-Syntax:: Syntax 13427* MMIX-mmixal:: Differences to `mmixal' syntax and semantics 13428 13429 13430File: as.info, Node: MMIX-Opts, Next: MMIX-Expand, Up: MMIX-Dependent 13431 134329.25.1 Command-line Options 13433--------------------------- 13434 13435The MMIX version of `as' has some machine-dependent options. 13436 13437 When `--fixed-special-register-names' is specified, only the register 13438names specified in *note MMIX-Regs:: are recognized in the instructions 13439`PUT' and `GET'. 13440 13441 You can use the `--globalize-symbols' to make all symbols global. 13442This option is useful when splitting up a `mmixal' program into several 13443files. 13444 13445 The `--gnu-syntax' turns off most syntax compatibility with 13446`mmixal'. Its usability is currently doubtful. 13447 13448 The `--relax' option is not fully supported, but will eventually make 13449the object file prepared for linker relaxation. 13450 13451 If you want to avoid inadvertently calling a predefined symbol and 13452would rather get an error, for example when using `as' with a compiler 13453or other machine-generated code, specify `--no-predefined-syms'. This 13454turns off built-in predefined definitions of all such symbols, 13455including rounding-mode symbols, segment symbols, `BIT' symbols, and 13456`TRAP' symbols used in `mmix' "system calls". It also turns off 13457predefined special-register names, except when used in `PUT' and `GET' 13458instructions. 13459 13460 By default, some instructions are expanded to fit the size of the 13461operand or an external symbol (*note MMIX-Expand::). By passing 13462`--no-expand', no such expansion will be done, instead causing errors 13463at link time if the operand does not fit. 13464 13465 The `mmixal' documentation (*note mmixsite::) specifies that global 13466registers allocated with the `GREG' directive (*note MMIX-greg::) and 13467initialized to the same non-zero value, will refer to the same global 13468register. This isn't strictly enforceable in `as' since the final 13469addresses aren't known until link-time, but it will do an effort unless 13470the `--no-merge-gregs' option is specified. (Register merging isn't 13471yet implemented in `ld'.) 13472 13473 `as' will warn every time it expands an instruction to fit an 13474operand unless the option `-x' is specified. It is believed that this 13475behaviour is more useful than just mimicking `mmixal''s behaviour, in 13476which instructions are only expanded if the `-x' option is specified, 13477and assembly fails otherwise, when an instruction needs to be expanded. 13478It needs to be kept in mind that `mmixal' is both an assembler and 13479linker, while `as' will expand instructions that at link stage can be 13480contracted. (Though linker relaxation isn't yet implemented in `ld'.) 13481The option `-x' also imples `--linker-allocated-gregs'. 13482 13483 If instruction expansion is enabled, `as' can expand a `PUSHJ' 13484instruction into a series of instructions. The shortest expansion is 13485to not expand it, but just mark the call as redirectable to a stub, 13486which `ld' creates at link-time, but only if the original `PUSHJ' 13487instruction is found not to reach the target. The stub consists of the 13488necessary instructions to form a jump to the target. This happens if 13489`as' can assert that the `PUSHJ' instruction can reach such a stub. 13490The option `--no-pushj-stubs' disables this shorter expansion, and the 13491longer series of instructions is then created at assembly-time. The 13492option `--no-stubs' is a synonym, intended for compatibility with 13493future releases, where generation of stubs for other instructions may 13494be implemented. 13495 13496 Usually a two-operand-expression (*note GREG-base::) without a 13497matching `GREG' directive is treated as an error by `as'. When the 13498option `--linker-allocated-gregs' is in effect, they are instead passed 13499through to the linker, which will allocate as many global registers as 13500is needed. 13501 13502 13503File: as.info, Node: MMIX-Expand, Next: MMIX-Syntax, Prev: MMIX-Opts, Up: MMIX-Dependent 13504 135059.25.2 Instruction expansion 13506---------------------------- 13507 13508When `as' encounters an instruction with an operand that is either not 13509known or does not fit the operand size of the instruction, `as' (and 13510`ld') will expand the instruction into a sequence of instructions 13511semantically equivalent to the operand fitting the instruction. 13512Expansion will take place for the following instructions: 13513 13514`GETA' 13515 Expands to a sequence of four instructions: `SETL', `INCML', 13516 `INCMH' and `INCH'. The operand must be a multiple of four. 13517 13518Conditional branches 13519 A branch instruction is turned into a branch with the complemented 13520 condition and prediction bit over five instructions; four 13521 instructions setting `$255' to the operand value, which like with 13522 `GETA' must be a multiple of four, and a final `GO $255,$255,0'. 13523 13524`PUSHJ' 13525 Similar to expansion for conditional branches; four instructions 13526 set `$255' to the operand value, followed by a `PUSHGO 13527 $255,$255,0'. 13528 13529`JMP' 13530 Similar to conditional branches and `PUSHJ'. The final instruction 13531 is `GO $255,$255,0'. 13532 13533 The linker `ld' is expected to shrink these expansions for code 13534assembled with `--relax' (though not currently implemented). 13535 13536 13537File: as.info, Node: MMIX-Syntax, Next: MMIX-mmixal, Prev: MMIX-Expand, Up: MMIX-Dependent 13538 135399.25.3 Syntax 13540------------- 13541 13542The assembly syntax is supposed to be upward compatible with that 13543described in Sections 1.3 and 1.4 of `The Art of Computer Programming, 13544Volume 1'. Draft versions of those chapters as well as other MMIX 13545information is located at 13546`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html'. Most code 13547examples from the mmixal package located there should work unmodified 13548when assembled and linked as single files, with a few noteworthy 13549exceptions (*note MMIX-mmixal::). 13550 13551 Before an instruction is emitted, the current location is aligned to 13552the next four-byte boundary. If a label is defined at the beginning of 13553the line, its value will be the aligned value. 13554 13555 In addition to the traditional hex-prefix `0x', a hexadecimal number 13556can also be specified by the prefix character `#'. 13557 13558 After all operands to an MMIX instruction or directive have been 13559specified, the rest of the line is ignored, treated as a comment. 13560 13561* Menu: 13562 13563* MMIX-Chars:: Special Characters 13564* MMIX-Symbols:: Symbols 13565* MMIX-Regs:: Register Names 13566* MMIX-Pseudos:: Assembler Directives 13567 13568 13569File: as.info, Node: MMIX-Chars, Next: MMIX-Symbols, Up: MMIX-Syntax 13570 135719.25.3.1 Special Characters 13572........................... 13573 13574The characters `*' and `#' are line comment characters; each start a 13575comment at the beginning of a line, but only at the beginning of a 13576line. A `#' prefixes a hexadecimal number if found elsewhere on a 13577line. If a `#' appears at the start of a line the whole line is 13578treated as a comment, but the line can also act as a logical line 13579number directive (*note Comments::) or a preprocessor control command 13580(*note Preprocessing::). 13581 13582 Two other characters, `%' and `!', each start a comment anywhere on 13583the line. Thus you can't use the `modulus' and `not' operators in 13584expressions normally associated with these two characters. 13585 13586 A `;' is a line separator, treated as a new-line, so separate 13587instructions can be specified on a single line. 13588 13589 13590File: as.info, Node: MMIX-Symbols, Next: MMIX-Regs, Prev: MMIX-Chars, Up: MMIX-Syntax 13591 135929.25.3.2 Symbols 13593................ 13594 13595The character `:' is permitted in identifiers. There are two 13596exceptions to it being treated as any other symbol character: if a 13597symbol begins with `:', it means that the symbol is in the global 13598namespace and that the current prefix should not be prepended to that 13599symbol (*note MMIX-prefix::). The `:' is then not considered part of 13600the symbol. For a symbol in the label position (first on a line), a `:' 13601at the end of a symbol is silently stripped off. A label is permitted, 13602but not required, to be followed by a `:', as with many other assembly 13603formats. 13604 13605 The character `@' in an expression, is a synonym for `.', the 13606current location. 13607 13608 In addition to the common forward and backward local symbol formats 13609(*note Symbol Names::), they can be specified with upper-case `B' and 13610`F', as in `8B' and `9F'. A local label defined for the current 13611position is written with a `H' appended to the number: 13612 3H LDB $0,$1,2 13613 This and traditional local-label formats cannot be mixed: a label 13614must be defined and referred to using the same format. 13615 13616 There's a minor caveat: just as for the ordinary local symbols, the 13617local symbols are translated into ordinary symbols using control 13618characters are to hide the ordinal number of the symbol. 13619Unfortunately, these symbols are not translated back in error messages. 13620Thus you may see confusing error messages when local symbols are used. 13621Control characters `\003' (control-C) and `\004' (control-D) are used 13622for the MMIX-specific local-symbol syntax. 13623 13624 The symbol `Main' is handled specially; it is always global. 13625 13626 By defining the symbols `__.MMIX.start..text' and 13627`__.MMIX.start..data', the address of respectively the `.text' and 13628`.data' segments of the final program can be defined, though when 13629linking more than one object file, the code or data in the object file 13630containing the symbol is not guaranteed to be start at that position; 13631just the final executable. *Note MMIX-loc::. 13632 13633 13634File: as.info, Node: MMIX-Regs, Next: MMIX-Pseudos, Prev: MMIX-Symbols, Up: MMIX-Syntax 13635 136369.25.3.3 Register names 13637....................... 13638 13639Local and global registers are specified as `$0' to `$255'. The 13640recognized special register names are `rJ', `rA', `rB', `rC', `rD', 13641`rE', `rF', `rG', `rH', `rI', `rK', `rL', `rM', `rN', `rO', `rP', `rQ', 13642`rR', `rS', `rT', `rU', `rV', `rW', `rX', `rY', `rZ', `rBB', `rTT', 13643`rWW', `rXX', `rYY' and `rZZ'. A leading `:' is optional for special 13644register names. 13645 13646 Local and global symbols can be equated to register names and used in 13647place of ordinary registers. 13648 13649 Similarly for special registers, local and global symbols can be 13650used. Also, symbols equated from numbers and constant expressions are 13651allowed in place of a special register, except when either of the 13652options `--no-predefined-syms' and `--fixed-special-register-names' are 13653specified. Then only the special register names above are allowed for 13654the instructions having a special register operand; `GET' and `PUT'. 13655 13656 13657File: as.info, Node: MMIX-Pseudos, Prev: MMIX-Regs, Up: MMIX-Syntax 13658 136599.25.3.4 Assembler Directives 13660............................. 13661 13662`LOC' 13663 The `LOC' directive sets the current location to the value of the 13664 operand field, which may include changing sections. If the 13665 operand is a constant, the section is set to either `.data' if the 13666 value is `0x2000000000000000' or larger, else it is set to `.text'. 13667 Within a section, the current location may only be changed to 13668 monotonically higher addresses. A LOC expression must be a 13669 previously defined symbol or a "pure" constant. 13670 13671 An example, which sets the label PREV to the current location, and 13672 updates the current location to eight bytes forward: 13673 prev LOC @+8 13674 13675 When a LOC has a constant as its operand, a symbol 13676 `__.MMIX.start..text' or `__.MMIX.start..data' is defined 13677 depending on the address as mentioned above. Each such symbol is 13678 interpreted as special by the linker, locating the section at that 13679 address. Note that if multiple files are linked, the first object 13680 file with that section will be mapped to that address (not 13681 necessarily the file with the LOC definition). 13682 13683`LOCAL' 13684 Example: 13685 LOCAL external_symbol 13686 LOCAL 42 13687 .local asymbol 13688 13689 This directive-operation generates a link-time assertion that the 13690 operand does not correspond to a global register. The operand is 13691 an expression that at link-time resolves to a register symbol or a 13692 number. A number is treated as the register having that number. 13693 There is one restriction on the use of this directive: the 13694 pseudo-directive must be placed in a section with contents, code 13695 or data. 13696 13697`IS' 13698 The `IS' directive: 13699 asymbol IS an_expression 13700 sets the symbol `asymbol' to `an_expression'. A symbol may not be 13701 set more than once using this directive. Local labels may be set 13702 using this directive, for example: 13703 5H IS @+4 13704 13705`GREG' 13706 This directive reserves a global register, gives it an initial 13707 value and optionally gives it a symbolic name. Some examples: 13708 13709 areg GREG 13710 breg GREG data_value 13711 GREG data_buffer 13712 .greg creg, another_data_value 13713 13714 The symbolic register name can be used in place of a (non-special) 13715 register. If a value isn't provided, it defaults to zero. Unless 13716 the option `--no-merge-gregs' is specified, non-zero registers 13717 allocated with this directive may be eliminated by `as'; another 13718 register with the same value used in its place. Any of the 13719 instructions `CSWAP', `GO', `LDA', `LDBU', `LDB', `LDHT', `LDOU', 13720 `LDO', `LDSF', `LDTU', `LDT', `LDUNC', `LDVTS', `LDWU', `LDW', 13721 `PREGO', `PRELD', `PREST', `PUSHGO', `STBU', `STB', `STCO', `STHT', 13722 `STOU', `STSF', `STTU', `STT', `STUNC', `SYNCD', `SYNCID', can 13723 have a value nearby an initial value in place of its second and 13724 third operands. Here, "nearby" is defined as within the range 13725 0...255 from the initial value of such an allocated register. 13726 13727 buffer1 BYTE 0,0,0,0,0 13728 buffer2 BYTE 0,0,0,0,0 13729 ... 13730 GREG buffer1 13731 LDOU $42,buffer2 13732 In the example above, the `Y' field of the `LDOUI' instruction 13733 (LDOU with a constant Z) will be replaced with the global register 13734 allocated for `buffer1', and the `Z' field will have the value 5, 13735 the offset from `buffer1' to `buffer2'. The result is equivalent 13736 to this code: 13737 buffer1 BYTE 0,0,0,0,0 13738 buffer2 BYTE 0,0,0,0,0 13739 ... 13740 tmpreg GREG buffer1 13741 LDOU $42,tmpreg,(buffer2-buffer1) 13742 13743 Global registers allocated with this directive are allocated in 13744 order higher-to-lower within a file. Other than that, the exact 13745 order of register allocation and elimination is undefined. For 13746 example, the order is undefined when more than one file with such 13747 directives are linked together. With the options `-x' and 13748 `--linker-allocated-gregs', `GREG' directives for two-operand 13749 cases like the one mentioned above can be omitted. Sufficient 13750 global registers will then be allocated by the linker. 13751 13752`BYTE' 13753 The `BYTE' directive takes a series of operands separated by a 13754 comma. If an operand is a string (*note Strings::), each 13755 character of that string is emitted as a byte. Other operands 13756 must be constant expressions without forward references, in the 13757 range 0...255. If you need operands having expressions with 13758 forward references, use `.byte' (*note Byte::). An operand can be 13759 omitted, defaulting to a zero value. 13760 13761`WYDE' 13762`TETRA' 13763`OCTA' 13764 The directives `WYDE', `TETRA' and `OCTA' emit constants of two, 13765 four and eight bytes size respectively. Before anything else 13766 happens for the directive, the current location is aligned to the 13767 respective constant-size boundary. If a label is defined at the 13768 beginning of the line, its value will be that after the alignment. 13769 A single operand can be omitted, defaulting to a zero value 13770 emitted for the directive. Operands can be expressed as strings 13771 (*note Strings::), in which case each character in the string is 13772 emitted as a separate constant of the size indicated by the 13773 directive. 13774 13775`PREFIX' 13776 The `PREFIX' directive sets a symbol name prefix to be prepended to 13777 all symbols (except local symbols, *note MMIX-Symbols::), that are 13778 not prefixed with `:', until the next `PREFIX' directive. Such 13779 prefixes accumulate. For example, 13780 PREFIX a 13781 PREFIX b 13782 c IS 0 13783 defines a symbol `abc' with the value 0. 13784 13785`BSPEC' 13786`ESPEC' 13787 A pair of `BSPEC' and `ESPEC' directives delimit a section of 13788 special contents (without specified semantics). Example: 13789 BSPEC 42 13790 TETRA 1,2,3 13791 ESPEC 13792 The single operand to `BSPEC' must be number in the range 0...255. 13793 The `BSPEC' number 80 is used by the GNU binutils implementation. 13794 13795 13796File: as.info, Node: MMIX-mmixal, Prev: MMIX-Syntax, Up: MMIX-Dependent 13797 137989.25.4 Differences to `mmixal' 13799------------------------------ 13800 13801The binutils `as' and `ld' combination has a few differences in 13802function compared to `mmixal' (*note mmixsite::). 13803 13804 The replacement of a symbol with a GREG-allocated register (*note 13805GREG-base::) is not handled the exactly same way in `as' as in 13806`mmixal'. This is apparent in the `mmixal' example file `inout.mms', 13807where different registers with different offsets, eventually yielding 13808the same address, are used in the first instruction. This type of 13809difference should however not affect the function of any program unless 13810it has specific assumptions about the allocated register number. 13811 13812 Line numbers (in the `mmo' object format) are currently not 13813supported. 13814 13815 Expression operator precedence is not that of mmixal: operator 13816precedence is that of the C programming language. It's recommended to 13817use parentheses to explicitly specify wanted operator precedence 13818whenever more than one type of operators are used. 13819 13820 The serialize unary operator `&', the fractional division operator 13821`//', the logical not operator `!' and the modulus operator `%' are not 13822available. 13823 13824 Symbols are not global by default, unless the option 13825`--globalize-symbols' is passed. Use the `.global' directive to 13826globalize symbols (*note Global::). 13827 13828 Operand syntax is a bit stricter with `as' than `mmixal'. For 13829example, you can't say `addu 1,2,3', instead you must write `addu 13830$1,$2,3'. 13831 13832 You can't LOC to a lower address than those already visited (i.e., 13833"backwards"). 13834 13835 A LOC directive must come before any emitted code. 13836 13837 Predefined symbols are visible as file-local symbols after use. (In 13838the ELF file, that is--the linked mmo file has no notion of a file-local 13839symbol.) 13840 13841 Some mapping of constant expressions to sections in LOC expressions 13842is attempted, but that functionality is easily confused and should be 13843avoided unless compatibility with `mmixal' is required. A LOC 13844expression to `0x2000000000000000' or higher, maps to the `.data' 13845section and lower addresses map to the `.text' section (*note 13846MMIX-loc::). 13847 13848 The code and data areas are each contiguous. Sparse programs with 13849far-away LOC directives will take up the same amount of space as a 13850contiguous program with zeros filled in the gaps between the LOC 13851directives. If you need sparse programs, you might try and get the 13852wanted effect with a linker script and splitting up the code parts into 13853sections (*note Section::). Assembly code for this, to be compatible 13854with `mmixal', would look something like: 13855 .if 0 13856 LOC away_expression 13857 .else 13858 .section away,"ax" 13859 .fi 13860 `as' will not execute the LOC directive and `mmixal' ignores the 13861lines with `.'. This construct can be used generally to help 13862compatibility. 13863 13864 Symbols can't be defined twice-not even to the same value. 13865 13866 Instruction mnemonics are recognized case-insensitive, though the 13867`IS' and `GREG' pseudo-operations must be specified in upper-case 13868characters. 13869 13870 There's no unicode support. 13871 13872 The following is a list of programs in `mmix.tar.gz', available at 13873`http://www-cs-faculty.stanford.edu/~knuth/mmix-news.html', last 13874checked with the version dated 2001-08-25 (md5sum 13875c393470cfc86fac040487d22d2bf0172) that assemble with `mmixal' but do 13876not assemble with `as': 13877 13878`silly.mms' 13879 LOC to a previous address. 13880 13881`sim.mms' 13882 Redefines symbol `Done'. 13883 13884`test.mms' 13885 Uses the serial operator `&'. 13886 13887 13888File: as.info, Node: MSP430-Dependent, Next: NS32K-Dependent, Prev: MMIX-Dependent, Up: Machine Dependencies 13889 138909.26 MSP 430 Dependent Features 13891=============================== 13892 13893* Menu: 13894 13895* MSP430 Options:: Options 13896* MSP430 Syntax:: Syntax 13897* MSP430 Floating Point:: Floating Point 13898* MSP430 Directives:: MSP 430 Machine Directives 13899* MSP430 Opcodes:: Opcodes 13900* MSP430 Profiling Capability:: Profiling Capability 13901 13902 13903File: as.info, Node: MSP430 Options, Next: MSP430 Syntax, Up: MSP430-Dependent 13904 139059.26.1 Options 13906-------------- 13907 13908`-m' 13909 select the mpu arch. Currently has no effect. 13910 13911`-mP' 13912 enables polymorph instructions handler. 13913 13914`-mQ' 13915 enables relaxation at assembly time. DANGEROUS! 13916 13917 13918 13919File: as.info, Node: MSP430 Syntax, Next: MSP430 Floating Point, Prev: MSP430 Options, Up: MSP430-Dependent 13920 139219.26.2 Syntax 13922------------- 13923 13924* Menu: 13925 13926* MSP430-Macros:: Macros 13927* MSP430-Chars:: Special Characters 13928* MSP430-Regs:: Register Names 13929* MSP430-Ext:: Assembler Extensions 13930 13931 13932File: as.info, Node: MSP430-Macros, Next: MSP430-Chars, Up: MSP430 Syntax 13933 139349.26.2.1 Macros 13935............... 13936 13937The macro syntax used on the MSP 430 is like that described in the MSP 13938430 Family Assembler Specification. Normal `as' macros should still 13939work. 13940 13941 Additional built-in macros are: 13942 13943`llo(exp)' 13944 Extracts least significant word from 32-bit expression 'exp'. 13945 13946`lhi(exp)' 13947 Extracts most significant word from 32-bit expression 'exp'. 13948 13949`hlo(exp)' 13950 Extracts 3rd word from 64-bit expression 'exp'. 13951 13952`hhi(exp)' 13953 Extracts 4rd word from 64-bit expression 'exp'. 13954 13955 13956 They normally being used as an immediate source operand. 13957 mov #llo(1), r10 ; == mov #1, r10 13958 mov #lhi(1), r10 ; == mov #0, r10 13959 13960 13961File: as.info, Node: MSP430-Chars, Next: MSP430-Regs, Prev: MSP430-Macros, Up: MSP430 Syntax 13962 139639.26.2.2 Special Characters 13964........................... 13965 13966A semicolon (`;') appearing anywhere on a line starts a comment that 13967extends to the end of that line. 13968 13969 If a `#' appears as the first character of a line then the whole 13970line is treated as a comment, but it can also be a logical line number 13971directive (*note Comments::) or a preprocessor control command (*note 13972Preprocessing::). 13973 13974 Multiple statements can appear on the same line provided that they 13975are separated by the `{' character. 13976 13977 The character `$' in jump instructions indicates current location and 13978implemented only for TI syntax compatibility. 13979 13980 13981File: as.info, Node: MSP430-Regs, Next: MSP430-Ext, Prev: MSP430-Chars, Up: MSP430 Syntax 13982 139839.26.2.3 Register Names 13984....................... 13985 13986General-purpose registers are represented by predefined symbols of the 13987form `rN' (for global registers), where N represents a number between 13988`0' and `15'. The leading letters may be in either upper or lower 13989case; for example, `r13' and `R7' are both valid register names. 13990 13991 Register names `PC', `SP' and `SR' cannot be used as register names 13992and will be treated as variables. Use `r0', `r1', and `r2' instead. 13993 13994 13995File: as.info, Node: MSP430-Ext, Prev: MSP430-Regs, Up: MSP430 Syntax 13996 139979.26.2.4 Assembler Extensions 13998............................. 13999 14000`@rN' 14001 As destination operand being treated as `0(rn)' 14002 14003`0(rN)' 14004 As source operand being treated as `@rn' 14005 14006`jCOND +N' 14007 Skips next N bytes followed by jump instruction and equivalent to 14008 `jCOND $+N+2' 14009 14010 14011 Also, there are some instructions, which cannot be found in other 14012assemblers. These are branch instructions, which has different opcodes 14013upon jump distance. They all got PC relative addressing mode. 14014 14015`beq label' 14016 A polymorph instruction which is `jeq label' in case if jump 14017 distance within allowed range for cpu's jump instruction. If not, 14018 this unrolls into a sequence of 14019 jne $+6 14020 br label 14021 14022`bne label' 14023 A polymorph instruction which is `jne label' or `jeq +4; br label' 14024 14025`blt label' 14026 A polymorph instruction which is `jl label' or `jge +4; br label' 14027 14028`bltn label' 14029 A polymorph instruction which is `jn label' or `jn +2; jmp +4; br 14030 label' 14031 14032`bltu label' 14033 A polymorph instruction which is `jlo label' or `jhs +2; br label' 14034 14035`bge label' 14036 A polymorph instruction which is `jge label' or `jl +4; br label' 14037 14038`bgeu label' 14039 A polymorph instruction which is `jhs label' or `jlo +4; br label' 14040 14041`bgt label' 14042 A polymorph instruction which is `jeq +2; jge label' or `jeq +6; 14043 jl +4; br label' 14044 14045`bgtu label' 14046 A polymorph instruction which is `jeq +2; jhs label' or `jeq +6; 14047 jlo +4; br label' 14048 14049`bleu label' 14050 A polymorph instruction which is `jeq label; jlo label' or `jeq 14051 +2; jhs +4; br label' 14052 14053`ble label' 14054 A polymorph instruction which is `jeq label; jl label' or `jeq 14055 +2; jge +4; br label' 14056 14057`jump label' 14058 A polymorph instruction which is `jmp label' or `br label' 14059 14060 14061File: as.info, Node: MSP430 Floating Point, Next: MSP430 Directives, Prev: MSP430 Syntax, Up: MSP430-Dependent 14062 140639.26.3 Floating Point 14064--------------------- 14065 14066The MSP 430 family uses IEEE 32-bit floating-point numbers. 14067 14068 14069File: as.info, Node: MSP430 Directives, Next: MSP430 Opcodes, Prev: MSP430 Floating Point, Up: MSP430-Dependent 14070 140719.26.4 MSP 430 Machine Directives 14072--------------------------------- 14073 14074`.file' 14075 This directive is ignored; it is accepted for compatibility with 14076 other MSP 430 assemblers. 14077 14078 _Warning:_ in other versions of the GNU assembler, `.file' is 14079 used for the directive called `.app-file' in the MSP 430 14080 support. 14081 14082`.line' 14083 This directive is ignored; it is accepted for compatibility with 14084 other MSP 430 assemblers. 14085 14086`.arch' 14087 Currently this directive is ignored; it is accepted for 14088 compatibility with other MSP 430 assemblers. 14089 14090`.profiler' 14091 This directive instructs assembler to add new profile entry to the 14092 object file. 14093 14094 14095 14096File: as.info, Node: MSP430 Opcodes, Next: MSP430 Profiling Capability, Prev: MSP430 Directives, Up: MSP430-Dependent 14097 140989.26.5 Opcodes 14099-------------- 14100 14101`as' implements all the standard MSP 430 opcodes. No additional 14102pseudo-instructions are needed on this family. 14103 14104 For information on the 430 machine instruction set, see `MSP430 14105User's Manual, document slau049d', Texas Instrument, Inc. 14106 14107 14108File: as.info, Node: MSP430 Profiling Capability, Prev: MSP430 Opcodes, Up: MSP430-Dependent 14109 141109.26.6 Profiling Capability 14111--------------------------- 14112 14113It is a performance hit to use gcc's profiling approach for this tiny 14114target. Even more - jtag hardware facility does not perform any 14115profiling functions. However we've got gdb's built-in simulator where 14116we can do anything. 14117 14118 We define new section `.profiler' which holds all profiling 14119information. We define new pseudo operation `.profiler' which will 14120instruct assembler to add new profile entry to the object file. Profile 14121should take place at the present address. 14122 14123 Pseudo operation format: 14124 14125 `.profiler flags,function_to_profile [, cycle_corrector, extra]' 14126 14127 where: 14128 14129 `flags' is a combination of the following characters: 14130 14131 `s' 14132 function entry 14133 14134 `x' 14135 function exit 14136 14137 `i' 14138 function is in init section 14139 14140 `f' 14141 function is in fini section 14142 14143 `l' 14144 library call 14145 14146 `c' 14147 libc standard call 14148 14149 `d' 14150 stack value demand 14151 14152 `I' 14153 interrupt service routine 14154 14155 `P' 14156 prologue start 14157 14158 `p' 14159 prologue end 14160 14161 `E' 14162 epilogue start 14163 14164 `e' 14165 epilogue end 14166 14167 `j' 14168 long jump / sjlj unwind 14169 14170 `a' 14171 an arbitrary code fragment 14172 14173 `t' 14174 extra parameter saved (a constant value like frame size) 14175 14176`function_to_profile' 14177 a function address 14178 14179`cycle_corrector' 14180 a value which should be added to the cycle counter, zero if 14181 omitted. 14182 14183`extra' 14184 any extra parameter, zero if omitted. 14185 14186 14187 For example: 14188 .global fxx 14189 .type fxx,@function 14190 fxx: 14191 .LFrameOffset_fxx=0x08 14192 .profiler "scdP", fxx ; function entry. 14193 ; we also demand stack value to be saved 14194 push r11 14195 push r10 14196 push r9 14197 push r8 14198 .profiler "cdpt",fxx,0, .LFrameOffset_fxx ; check stack value at this point 14199 ; (this is a prologue end) 14200 ; note, that spare var filled with 14201 ; the farme size 14202 mov r15,r8 14203 ... 14204 .profiler cdE,fxx ; check stack 14205 pop r8 14206 pop r9 14207 pop r10 14208 pop r11 14209 .profiler xcde,fxx,3 ; exit adds 3 to the cycle counter 14210 ret ; cause 'ret' insn takes 3 cycles 14211 14212 14213File: as.info, Node: NS32K-Dependent, Next: SH-Dependent, Prev: MSP430-Dependent, Up: Machine Dependencies 14214 142159.27 NS32K Dependent Features 14216============================= 14217 14218* Menu: 14219 14220* NS32K Syntax:: Syntax 14221 14222 14223File: as.info, Node: NS32K Syntax, Up: NS32K-Dependent 14224 142259.27.1 Syntax 14226------------- 14227 14228* Menu: 14229 14230* NS32K-Chars:: Special Characters 14231 14232 14233File: as.info, Node: NS32K-Chars, Up: NS32K Syntax 14234 142359.27.1.1 Special Characters 14236........................... 14237 14238The presence of a `#' appearing anywhere on a line indicates the start 14239of a comment that extends to the end of that line. 14240 14241 If a `#' appears as the first character of a line then the whole 14242line is treated as a comment, but in this case the line can also be a 14243logical line number directive (*note Comments::) or a preprocessor 14244control command (*note Preprocessing::). 14245 14246 If Sequent compatibility has been configured into the assembler then 14247the `|' character appearing as the first character on a line will also 14248indicate the start of a line comment. 14249 14250 The `;' character can be used to separate statements on the same 14251line. 14252 14253 14254File: as.info, Node: PDP-11-Dependent, Next: PJ-Dependent, Prev: SH64-Dependent, Up: Machine Dependencies 14255 142569.28 PDP-11 Dependent Features 14257============================== 14258 14259* Menu: 14260 14261* PDP-11-Options:: Options 14262* PDP-11-Pseudos:: Assembler Directives 14263* PDP-11-Syntax:: DEC Syntax versus BSD Syntax 14264* PDP-11-Mnemonics:: Instruction Naming 14265* PDP-11-Synthetic:: Synthetic Instructions 14266 14267 14268File: as.info, Node: PDP-11-Options, Next: PDP-11-Pseudos, Up: PDP-11-Dependent 14269 142709.28.1 Options 14271-------------- 14272 14273The PDP-11 version of `as' has a rich set of machine dependent options. 14274 142759.28.1.1 Code Generation Options 14276................................ 14277 14278`-mpic | -mno-pic' 14279 Generate position-independent (or position-dependent) code. 14280 14281 The default is to generate position-independent code. 14282 142839.28.1.2 Instruction Set Extension Options 14284.......................................... 14285 14286These options enables or disables the use of extensions over the base 14287line instruction set as introduced by the first PDP-11 CPU: the KA11. 14288Most options come in two variants: a `-m'EXTENSION that enables 14289EXTENSION, and a `-mno-'EXTENSION that disables EXTENSION. 14290 14291 The default is to enable all extensions. 14292 14293`-mall | -mall-extensions' 14294 Enable all instruction set extensions. 14295 14296`-mno-extensions' 14297 Disable all instruction set extensions. 14298 14299`-mcis | -mno-cis' 14300 Enable (or disable) the use of the commercial instruction set, 14301 which consists of these instructions: `ADDNI', `ADDN', `ADDPI', 14302 `ADDP', `ASHNI', `ASHN', `ASHPI', `ASHP', `CMPCI', `CMPC', 14303 `CMPNI', `CMPN', `CMPPI', `CMPP', `CVTLNI', `CVTLN', `CVTLPI', 14304 `CVTLP', `CVTNLI', `CVTNL', `CVTNPI', `CVTNP', `CVTPLI', `CVTPL', 14305 `CVTPNI', `CVTPN', `DIVPI', `DIVP', `L2DR', `L3DR', `LOCCI', 14306 `LOCC', `MATCI', `MATC', `MOVCI', `MOVC', `MOVRCI', `MOVRC', 14307 `MOVTCI', `MOVTC', `MULPI', `MULP', `SCANCI', `SCANC', `SKPCI', 14308 `SKPC', `SPANCI', `SPANC', `SUBNI', `SUBN', `SUBPI', and `SUBP'. 14309 14310`-mcsm | -mno-csm' 14311 Enable (or disable) the use of the `CSM' instruction. 14312 14313`-meis | -mno-eis' 14314 Enable (or disable) the use of the extended instruction set, which 14315 consists of these instructions: `ASHC', `ASH', `DIV', `MARK', 14316 `MUL', `RTT', `SOB' `SXT', and `XOR'. 14317 14318`-mfis | -mkev11' 14319`-mno-fis | -mno-kev11' 14320 Enable (or disable) the use of the KEV11 floating-point 14321 instructions: `FADD', `FDIV', `FMUL', and `FSUB'. 14322 14323`-mfpp | -mfpu | -mfp-11' 14324`-mno-fpp | -mno-fpu | -mno-fp-11' 14325 Enable (or disable) the use of FP-11 floating-point instructions: 14326 `ABSF', `ADDF', `CFCC', `CLRF', `CMPF', `DIVF', `LDCFF', `LDCIF', 14327 `LDEXP', `LDF', `LDFPS', `MODF', `MULF', `NEGF', `SETD', `SETF', 14328 `SETI', `SETL', `STCFF', `STCFI', `STEXP', `STF', `STFPS', `STST', 14329 `SUBF', and `TSTF'. 14330 14331`-mlimited-eis | -mno-limited-eis' 14332 Enable (or disable) the use of the limited extended instruction 14333 set: `MARK', `RTT', `SOB', `SXT', and `XOR'. 14334 14335 The -mno-limited-eis options also implies -mno-eis. 14336 14337`-mmfpt | -mno-mfpt' 14338 Enable (or disable) the use of the `MFPT' instruction. 14339 14340`-mmultiproc | -mno-multiproc' 14341 Enable (or disable) the use of multiprocessor instructions: 14342 `TSTSET' and `WRTLCK'. 14343 14344`-mmxps | -mno-mxps' 14345 Enable (or disable) the use of the `MFPS' and `MTPS' instructions. 14346 14347`-mspl | -mno-spl' 14348 Enable (or disable) the use of the `SPL' instruction. 14349 14350 Enable (or disable) the use of the microcode instructions: `LDUB', 14351 `MED', and `XFC'. 14352 143539.28.1.3 CPU Model Options 14354.......................... 14355 14356These options enable the instruction set extensions supported by a 14357particular CPU, and disables all other extensions. 14358 14359`-mka11' 14360 KA11 CPU. Base line instruction set only. 14361 14362`-mkb11' 14363 KB11 CPU. Enable extended instruction set and `SPL'. 14364 14365`-mkd11a' 14366 KD11-A CPU. Enable limited extended instruction set. 14367 14368`-mkd11b' 14369 KD11-B CPU. Base line instruction set only. 14370 14371`-mkd11d' 14372 KD11-D CPU. Base line instruction set only. 14373 14374`-mkd11e' 14375 KD11-E CPU. Enable extended instruction set, `MFPS', and `MTPS'. 14376 14377`-mkd11f | -mkd11h | -mkd11q' 14378 KD11-F, KD11-H, or KD11-Q CPU. Enable limited extended 14379 instruction set, `MFPS', and `MTPS'. 14380 14381`-mkd11k' 14382 KD11-K CPU. Enable extended instruction set, `LDUB', `MED', 14383 `MFPS', `MFPT', `MTPS', and `XFC'. 14384 14385`-mkd11z' 14386 KD11-Z CPU. Enable extended instruction set, `CSM', `MFPS', 14387 `MFPT', `MTPS', and `SPL'. 14388 14389`-mf11' 14390 F11 CPU. Enable extended instruction set, `MFPS', `MFPT', and 14391 `MTPS'. 14392 14393`-mj11' 14394 J11 CPU. Enable extended instruction set, `CSM', `MFPS', `MFPT', 14395 `MTPS', `SPL', `TSTSET', and `WRTLCK'. 14396 14397`-mt11' 14398 T11 CPU. Enable limited extended instruction set, `MFPS', and 14399 `MTPS'. 14400 144019.28.1.4 Machine Model Options 14402.............................. 14403 14404These options enable the instruction set extensions supported by a 14405particular machine model, and disables all other extensions. 14406 14407`-m11/03' 14408 Same as `-mkd11f'. 14409 14410`-m11/04' 14411 Same as `-mkd11d'. 14412 14413`-m11/05 | -m11/10' 14414 Same as `-mkd11b'. 14415 14416`-m11/15 | -m11/20' 14417 Same as `-mka11'. 14418 14419`-m11/21' 14420 Same as `-mt11'. 14421 14422`-m11/23 | -m11/24' 14423 Same as `-mf11'. 14424 14425`-m11/34' 14426 Same as `-mkd11e'. 14427 14428`-m11/34a' 14429 Ame as `-mkd11e' `-mfpp'. 14430 14431`-m11/35 | -m11/40' 14432 Same as `-mkd11a'. 14433 14434`-m11/44' 14435 Same as `-mkd11z'. 14436 14437`-m11/45 | -m11/50 | -m11/55 | -m11/70' 14438 Same as `-mkb11'. 14439 14440`-m11/53 | -m11/73 | -m11/83 | -m11/84 | -m11/93 | -m11/94' 14441 Same as `-mj11'. 14442 14443`-m11/60' 14444 Same as `-mkd11k'. 14445 14446 14447File: as.info, Node: PDP-11-Pseudos, Next: PDP-11-Syntax, Prev: PDP-11-Options, Up: PDP-11-Dependent 14448 144499.28.2 Assembler Directives 14450--------------------------- 14451 14452The PDP-11 version of `as' has a few machine dependent assembler 14453directives. 14454 14455`.bss' 14456 Switch to the `bss' section. 14457 14458`.even' 14459 Align the location counter to an even number. 14460 14461 14462File: as.info, Node: PDP-11-Syntax, Next: PDP-11-Mnemonics, Prev: PDP-11-Pseudos, Up: PDP-11-Dependent 14463 144649.28.3 PDP-11 Assembly Language Syntax 14465-------------------------------------- 14466 14467`as' supports both DEC syntax and BSD syntax. The only difference is 14468that in DEC syntax, a `#' character is used to denote an immediate 14469constants, while in BSD syntax the character for this purpose is `$'. 14470 14471 general-purpose registers are named `r0' through `r7'. Mnemonic 14472alternatives for `r6' and `r7' are `sp' and `pc', respectively. 14473 14474 Floating-point registers are named `ac0' through `ac3', or 14475alternatively `fr0' through `fr3'. 14476 14477 Comments are started with a `#' or a `/' character, and extend to 14478the end of the line. (FIXME: clash with immediates?) 14479 14480 Multiple statements on the same line can be separated by the `;' 14481character. 14482 14483 14484File: as.info, Node: PDP-11-Mnemonics, Next: PDP-11-Synthetic, Prev: PDP-11-Syntax, Up: PDP-11-Dependent 14485 144869.28.4 Instruction Naming 14487------------------------- 14488 14489Some instructions have alternative names. 14490 14491`BCC' 14492 `BHIS' 14493 14494`BCS' 14495 `BLO' 14496 14497`L2DR' 14498 `L2D' 14499 14500`L3DR' 14501 `L3D' 14502 14503`SYS' 14504 `TRAP' 14505 14506 14507File: as.info, Node: PDP-11-Synthetic, Prev: PDP-11-Mnemonics, Up: PDP-11-Dependent 14508 145099.28.5 Synthetic Instructions 14510----------------------------- 14511 14512The `JBR' and `J'CC synthetic instructions are not supported yet. 14513 14514 14515File: as.info, Node: PJ-Dependent, Next: PPC-Dependent, Prev: PDP-11-Dependent, Up: Machine Dependencies 14516 145179.29 picoJava Dependent Features 14518================================ 14519 14520* Menu: 14521 14522* PJ Options:: Options 14523* PJ Syntax:: PJ Syntax 14524 14525 14526File: as.info, Node: PJ Options, Next: PJ Syntax, Up: PJ-Dependent 14527 145289.29.1 Options 14529-------------- 14530 14531`as' has two additional command-line options for the picoJava 14532architecture. 14533`-ml' 14534 This option selects little endian data output. 14535 14536`-mb' 14537 This option selects big endian data output. 14538 14539 14540File: as.info, Node: PJ Syntax, Prev: PJ Options, Up: PJ-Dependent 14541 145429.29.2 PJ Syntax 14543---------------- 14544 14545* Menu: 14546 14547* PJ-Chars:: Special Characters 14548 14549 14550File: as.info, Node: PJ-Chars, Up: PJ Syntax 14551 145529.29.2.1 Special Characters 14553........................... 14554 14555The presence of a `!' or `/' on a line indicates the start of a comment 14556that extends to the end of the current line. 14557 14558 If a `#' appears as the first character of a line then the whole 14559line is treated as a comment, but in this case the line could also be a 14560logical line number directive (*note Comments::) or a preprocessor 14561control command (*note Preprocessing::). 14562 14563 The `;' character can be used to separate statements on the same 14564line. 14565 14566 14567File: as.info, Node: PPC-Dependent, Next: RX-Dependent, Prev: PJ-Dependent, Up: Machine Dependencies 14568 145699.30 PowerPC Dependent Features 14570=============================== 14571 14572* Menu: 14573 14574* PowerPC-Opts:: Options 14575* PowerPC-Pseudo:: PowerPC Assembler Directives 14576* PowerPC-Syntax:: PowerPC Syntax 14577 14578 14579File: as.info, Node: PowerPC-Opts, Next: PowerPC-Pseudo, Up: PPC-Dependent 14580 145819.30.1 Options 14582-------------- 14583 14584The PowerPC chip family includes several successive levels, using the 14585same core instruction set, but including a few additional instructions 14586at each level. There are exceptions to this however. For details on 14587what instructions each variant supports, please see the chip's 14588architecture reference manual. 14589 14590 The following table lists all available PowerPC options. 14591 14592`-a32' 14593 Generate ELF32 or XCOFF32. 14594 14595`-a64' 14596 Generate ELF64 or XCOFF64. 14597 14598`-K PIC' 14599 Set EF_PPC_RELOCATABLE_LIB in ELF flags. 14600 14601`-mpwrx | -mpwr2' 14602 Generate code for POWER/2 (RIOS2). 14603 14604`-mpwr' 14605 Generate code for POWER (RIOS1) 14606 14607`-m601' 14608 Generate code for PowerPC 601. 14609 14610`-mppc, -mppc32, -m603, -m604' 14611 Generate code for PowerPC 603/604. 14612 14613`-m403, -m405' 14614 Generate code for PowerPC 403/405. 14615 14616`-m440' 14617 Generate code for PowerPC 440. BookE and some 405 instructions. 14618 14619`-m464' 14620 Generate code for PowerPC 464. 14621 14622`-m476' 14623 Generate code for PowerPC 476. 14624 14625`-m7400, -m7410, -m7450, -m7455' 14626 Generate code for PowerPC 7400/7410/7450/7455. 14627 14628`-m750cl' 14629 Generate code for PowerPC 750CL. 14630 14631`-mppc64, -m620' 14632 Generate code for PowerPC 620/625/630. 14633 14634`-me500, -me500x2' 14635 Generate code for Motorola e500 core complex. 14636 14637`-me500mc' 14638 Generate code for Freescale e500mc core complex. 14639 14640`-me500mc64' 14641 Generate code for Freescale e500mc64 core complex. 14642 14643`-mspe' 14644 Generate code for Motorola SPE instructions. 14645 14646`-mtitan' 14647 Generate code for AppliedMicro Titan core complex. 14648 14649`-mppc64bridge' 14650 Generate code for PowerPC 64, including bridge insns. 14651 14652`-mbooke' 14653 Generate code for 32-bit BookE. 14654 14655`-ma2' 14656 Generate code for A2 architecture. 14657 14658`-me300' 14659 Generate code for PowerPC e300 family. 14660 14661`-maltivec' 14662 Generate code for processors with AltiVec instructions. 14663 14664`-mvsx' 14665 Generate code for processors with Vector-Scalar (VSX) instructions. 14666 14667`-mpower4, -mpwr4' 14668 Generate code for Power4 architecture. 14669 14670`-mpower5, -mpwr5, -mpwr5x' 14671 Generate code for Power5 architecture. 14672 14673`-mpower6, -mpwr6' 14674 Generate code for Power6 architecture. 14675 14676`-mpower7, -mpwr7' 14677 Generate code for Power7 architecture. 14678 14679`-mcell' 14680 Generate code for Cell Broadband Engine architecture. 14681 14682`-mcom' 14683 Generate code Power/PowerPC common instructions. 14684 14685`-many' 14686 Generate code for any architecture (PWR/PWRX/PPC). 14687 14688`-mregnames' 14689 Allow symbolic names for registers. 14690 14691`-mno-regnames' 14692 Do not allow symbolic names for registers. 14693 14694`-mrelocatable' 14695 Support for GCC's -mrelocatable option. 14696 14697`-mrelocatable-lib' 14698 Support for GCC's -mrelocatable-lib option. 14699 14700`-memb' 14701 Set PPC_EMB bit in ELF flags. 14702 14703`-mlittle, -mlittle-endian, -le' 14704 Generate code for a little endian machine. 14705 14706`-mbig, -mbig-endian, -be' 14707 Generate code for a big endian machine. 14708 14709`-msolaris' 14710 Generate code for Solaris. 14711 14712`-mno-solaris' 14713 Do not generate code for Solaris. 14714 14715`-nops=COUNT' 14716 If an alignment directive inserts more than COUNT nops, put a 14717 branch at the beginning to skip execution of the nops. 14718 14719 14720File: as.info, Node: PowerPC-Pseudo, Next: PowerPC-Syntax, Prev: PowerPC-Opts, Up: PPC-Dependent 14721 147229.30.2 PowerPC Assembler Directives 14723----------------------------------- 14724 14725A number of assembler directives are available for PowerPC. The 14726following table is far from complete. 14727 14728`.machine "string"' 14729 This directive allows you to change the machine for which code is 14730 generated. `"string"' may be any of the -m cpu selection options 14731 (without the -m) enclosed in double quotes, `"push"', or `"pop"'. 14732 `.machine "push"' saves the currently selected cpu, which may be 14733 restored with `.machine "pop"'. 14734 14735 14736File: as.info, Node: PowerPC-Syntax, Prev: PowerPC-Pseudo, Up: PPC-Dependent 14737 147389.30.3 PowerPC Syntax 14739--------------------- 14740 14741* Menu: 14742 14743* PowerPC-Chars:: Special Characters 14744 14745 14746File: as.info, Node: PowerPC-Chars, Up: PowerPC-Syntax 14747 147489.30.3.1 Special Characters 14749........................... 14750 14751The presence of a `#' on a line indicates the start of a comment that 14752extends to the end of the current line. 14753 14754 If a `#' appears as the first character of a line then the whole 14755line is treated as a comment, but in this case the line could also be a 14756logical line number directive (*note Comments::) or a preprocessor 14757control command (*note Preprocessing::). 14758 14759 If the assembler has been configured for the ppc-*-solaris* target 14760then the `!' character also acts as a line comment character. This can 14761be disabled via the `-mno-solaris' command line option. 14762 14763 The `;' character can be used to separate statements on the same 14764line. 14765 14766 14767File: as.info, Node: RX-Dependent, Next: S/390-Dependent, Prev: PPC-Dependent, Up: Machine Dependencies 14768 147699.31 RX Dependent Features 14770========================== 14771 14772* Menu: 14773 14774* RX-Opts:: RX Assembler Command Line Options 14775* RX-Modifiers:: Symbolic Operand Modifiers 14776* RX-Directives:: Assembler Directives 14777* RX-Float:: Floating Point 14778* RX-Syntax:: Syntax 14779 14780 14781File: as.info, Node: RX-Opts, Next: RX-Modifiers, Up: RX-Dependent 14782 147839.31.1 RX Options 14784----------------- 14785 14786The Renesas RX port of `as' has a few target specfic command line 14787options: 14788 14789`-m32bit-doubles' 14790 This option controls the ABI and indicates to use a 32-bit float 14791 ABI. It has no effect on the assembled instructions, but it does 14792 influence the behaviour of the `.double' pseudo-op. This is the 14793 default. 14794 14795`-m64bit-doubles' 14796 This option controls the ABI and indicates to use a 64-bit float 14797 ABI. It has no effect on the assembled instructions, but it does 14798 influence the behaviour of the `.double' pseudo-op. 14799 14800`-mbig-endian' 14801 This option controls the ABI and indicates to use a big-endian data 14802 ABI. It has no effect on the assembled instructions, but it does 14803 influence the behaviour of the `.short', `.hword', `.int', 14804 `.word', `.long', `.quad' and `.octa' pseudo-ops. 14805 14806`-mlittle-endian' 14807 This option controls the ABI and indicates to use a little-endian 14808 data ABI. It has no effect on the assembled instructions, but it 14809 does influence the behaviour of the `.short', `.hword', `.int', 14810 `.word', `.long', `.quad' and `.octa' pseudo-ops. This is the 14811 default. 14812 14813`-muse-conventional-section-names' 14814 This option controls the default names given to the code (.text), 14815 initialised data (.data) and uninitialised data sections (.bss). 14816 14817`-muse-renesas-section-names' 14818 This option controls the default names given to the code (.P), 14819 initialised data (.D_1) and uninitialised data sections (.B_1). 14820 This is the default. 14821 14822`-msmall-data-limit' 14823 This option tells the assembler that the small data limit feature 14824 of the RX port of GCC is being used. This results in the assembler 14825 generating an undefined reference to a symbol called __gp for use 14826 by the relocations that are needed to support the small data limit 14827 feature. This option is not enabled by default as it would 14828 otherwise pollute the symbol table. 14829 14830 14831 14832File: as.info, Node: RX-Modifiers, Next: RX-Directives, Prev: RX-Opts, Up: RX-Dependent 14833 148349.31.2 Symbolic Operand Modifiers 14835--------------------------------- 14836 14837The assembler supports several modifiers when using symbol addresses in 14838RX instruction operands. The general syntax is the following: 14839 14840 %modifier(symbol) 14841 14842`%gp' 14843 14844 14845File: as.info, Node: RX-Directives, Next: RX-Float, Prev: RX-Modifiers, Up: RX-Dependent 14846 148479.31.3 Assembler Directives 14848--------------------------- 14849 14850The RX version of `as' has the following specific assembler directives: 14851 14852`.3byte' 14853 Inserts a 3-byte value into the output file at the current 14854 location. 14855 14856 14857 14858File: as.info, Node: RX-Float, Next: RX-Syntax, Prev: RX-Directives, Up: RX-Dependent 14859 148609.31.4 Floating Point 14861--------------------- 14862 14863The floating point formats generated by directives are these. 14864 14865`.float' 14866 `Single' precision (32-bit) floating point constants. 14867 14868`.double' 14869 If the `-m64bit-doubles' command line option has been specified 14870 then then `double' directive generates `double' precision (64-bit) 14871 floating point constants, otherwise it generates `single' 14872 precision (32-bit) floating point constants. To force the 14873 generation of 64-bit floating point constants used the `dc.d' 14874 directive instead. 14875 14876 14877 14878File: as.info, Node: RX-Syntax, Prev: RX-Float, Up: RX-Dependent 14879 148809.31.5 Syntax for the RX 14881------------------------ 14882 14883* Menu: 14884 14885* RX-Chars:: Special Characters 14886 14887 14888File: as.info, Node: RX-Chars, Up: RX-Syntax 14889 148909.31.5.1 Special Characters 14891........................... 14892 14893The presence of a `;' appearing anywhere on a line indicates the start 14894of a comment that extends to the end of that line. 14895 14896 If a `#' appears as the first character of a line then the whole 14897line is treated as a comment, but in this case the line can also be a 14898logical line number directive (*note Comments::) or a preprocessor 14899control command (*note Preprocessing::). 14900 14901 The `!' character can be used to separate statements on the same 14902line. 14903 14904 14905File: as.info, Node: S/390-Dependent, Next: SCORE-Dependent, Prev: RX-Dependent, Up: Machine Dependencies 14906 149079.32 IBM S/390 Dependent Features 14908================================= 14909 14910 The s390 version of `as' supports two architectures modes and seven 14911chip levels. The architecture modes are the Enterprise System 14912Architecture (ESA) and the newer z/Architecture mode. The chip levels 14913are g5, g6, z900, z990, z9-109, z9-ec, z10 and z196. 14914 14915* Menu: 14916 14917* s390 Options:: Command-line Options. 14918* s390 Characters:: Special Characters. 14919* s390 Syntax:: Assembler Instruction syntax. 14920* s390 Directives:: Assembler Directives. 14921* s390 Floating Point:: Floating Point. 14922 14923 14924File: as.info, Node: s390 Options, Next: s390 Characters, Up: S/390-Dependent 14925 149269.32.1 Options 14927-------------- 14928 14929The following table lists all available s390 specific options: 14930 14931`-m31 | -m64' 14932 Select 31- or 64-bit ABI implying a word size of 32- or 64-bit. 14933 14934 These options are only available with the ELF object file format, 14935 and require that the necessary BFD support has been included (on a 14936 31-bit platform you must add -enable-64-bit-bfd on the call to the 14937 configure script to enable 64-bit usage and use s390x as target 14938 platform). 14939 14940`-mesa | -mzarch' 14941 Select the architecture mode, either the Enterprise System 14942 Architecture (esa) mode or the z/Architecture mode (zarch). 14943 14944 The 64-bit instructions are only available with the z/Architecture 14945 mode. The combination of `-m64' and `-mesa' results in a warning 14946 message. 14947 14948`-march=CPU' 14949 This option specifies the target processor. The following 14950 processor names are recognized: `g5', `g6', `z900', `z990', 14951 `z9-109', `z9-ec', `z10' and `z196'. Assembling an instruction 14952 that is not supported on the target processor results in an error 14953 message. Do not specify `g5' or `g6' with `-mzarch'. 14954 14955`-mregnames' 14956 Allow symbolic names for registers. 14957 14958`-mno-regnames' 14959 Do not allow symbolic names for registers. 14960 14961`-mwarn-areg-zero' 14962 Warn whenever the operand for a base or index register has been 14963 specified but evaluates to zero. This can indicate the misuse of 14964 general purpose register 0 as an address register. 14965 14966 14967 14968File: as.info, Node: s390 Characters, Next: s390 Syntax, Prev: s390 Options, Up: S/390-Dependent 14969 149709.32.2 Special Characters 14971------------------------- 14972 14973`#' is the line comment character. 14974 14975 If a `#' appears as the first character of a line then the whole 14976line is treated as a comment, but in this case the line could also be a 14977logical line number directive (*note Comments::) or a preprocessor 14978control command (*note Preprocessing::). 14979 14980 The `;' character can be used instead of a newline to separate 14981statements. 14982 14983 14984File: as.info, Node: s390 Syntax, Next: s390 Directives, Prev: s390 Characters, Up: S/390-Dependent 14985 149869.32.3 Instruction syntax 14987------------------------- 14988 14989The assembler syntax closely follows the syntax outlined in Enterprise 14990Systems Architecture/390 Principles of Operation (SA22-7201) and the 14991z/Architecture Principles of Operation (SA22-7832). 14992 14993 Each instruction has two major parts, the instruction mnemonic and 14994the instruction operands. The instruction format varies. 14995 14996* Menu: 14997 14998* s390 Register:: Register Naming 14999* s390 Mnemonics:: Instruction Mnemonics 15000* s390 Operands:: Instruction Operands 15001* s390 Formats:: Instruction Formats 15002* s390 Aliases:: Instruction Aliases 15003* s390 Operand Modifier:: Instruction Operand Modifier 15004* s390 Instruction Marker:: Instruction Marker 15005* s390 Literal Pool Entries:: Literal Pool Entries 15006 15007 15008File: as.info, Node: s390 Register, Next: s390 Mnemonics, Up: s390 Syntax 15009 150109.32.3.1 Register naming 15011........................ 15012 15013The `as' recognizes a number of predefined symbols for the various 15014processor registers. A register specification in one of the instruction 15015formats is an unsigned integer between 0 and 15. The specific 15016instruction and the position of the register in the instruction format 15017denotes the type of the register. The register symbols are prefixed with 15018`%': 15019 15020 %rN the 16 general purpose registers, 0 <= N <= 15 15021 %fN the 16 floating point registers, 0 <= N <= 15 15022 %aN the 16 access registers, 0 <= N <= 15 15023 %cN the 16 control registers, 0 <= N <= 15 15024 %lit an alias for the general purpose register %r13 15025 %sp an alias for the general purpose register %r15 15026 15027 15028File: as.info, Node: s390 Mnemonics, Next: s390 Operands, Prev: s390 Register, Up: s390 Syntax 15029 150309.32.3.2 Instruction Mnemonics 15031.............................. 15032 15033All instructions documented in the Principles of Operation are supported 15034with the mnemonic and order of operands as described. The instruction 15035mnemonic identifies the instruction format (*note s390 Formats::) and 15036the specific operation code for the instruction. For example, the `lr' 15037mnemonic denotes the instruction format `RR' with the operation code 15038`0x18'. 15039 15040 The definition of the various mnemonics follows a scheme, where the 15041first character usually hint at the type of the instruction: 15042 15043 a add instruction, for example `al' for add logical 32-bit 15044 b branch instruction, for example `bc' for branch on condition 15045 c compare or convert instruction, for example `cr' for compare 15046 register 32-bit 15047 d divide instruction, for example `dlr' devide logical register 15048 64-bit to 32-bit 15049 i insert instruction, for example `ic' insert character 15050 l load instruction, for example `ltr' load and test register 15051 mv move instruction, for example `mvc' move character 15052 m multiply instruction, for example `mh' multiply halfword 15053 n and instruction, for example `ni' and immediate 15054 o or instruction, for example `oc' or character 15055 sla, sll shift left single instruction 15056 sra, srl shift right single instruction 15057 st store instruction, for example `stm' store multiple 15058 s subtract instruction, for example `slr' subtract 15059 logical 32-bit 15060 t test or translate instruction, of example `tm' test under mask 15061 x exclusive or instruction, for example `xc' exclusive or 15062 character 15063 15064 Certain characters at the end of the mnemonic may describe a property 15065of the instruction: 15066 15067 c the instruction uses a 8-bit character operand 15068 f the instruction extends a 32-bit operand to 64 bit 15069 g the operands are treated as 64-bit values 15070 h the operand uses a 16-bit halfword operand 15071 i the instruction uses an immediate operand 15072 l the instruction uses unsigned, logical operands 15073 m the instruction uses a mask or operates on multiple values 15074 r if r is the last character, the instruction operates on registers 15075 y the instruction uses 20-bit displacements 15076 15077 There are many exceptions to the scheme outlined in the above lists, 15078in particular for the priviledged instructions. For non-priviledged 15079instruction it works quite well, for example the instruction `clgfr' c: 15080compare instruction, l: unsigned operands, g: 64-bit operands, f: 32- 15081to 64-bit extension, r: register operands. The instruction compares an 1508264-bit value in a register with the zero extended 32-bit value from a 15083second register. For a complete list of all mnemonics see appendix B 15084in the Principles of Operation. 15085 15086 15087File: as.info, Node: s390 Operands, Next: s390 Formats, Prev: s390 Mnemonics, Up: s390 Syntax 15088 150899.32.3.3 Instruction Operands 15090............................. 15091 15092Instruction operands can be grouped into three classes, operands located 15093in registers, immediate operands, and operands in storage. 15094 15095 A register operand can be located in general, floating-point, access, 15096or control register. The register is identified by a four-bit field. 15097The field containing the register operand is called the R field. 15098 15099 Immediate operands are contained within the instruction and can have 151008, 16 or 32 bits. The field containing the immediate operand is called 15101the I field. Dependent on the instruction the I field is either signed 15102or unsigned. 15103 15104 A storage operand consists of an address and a length. The address 15105of a storage operands can be specified in any of these ways: 15106 15107 * The content of a single general R 15108 15109 * The sum of the content of a general register called the base 15110 register B plus the content of a displacement field D 15111 15112 * The sum of the contents of two general registers called the index 15113 register X and the base register B plus the content of a 15114 displacement field 15115 15116 * The sum of the current instruction address and a 32-bit signed 15117 immediate field multiplied by two. 15118 15119 The length of a storage operand can be: 15120 15121 * Implied by the instruction 15122 15123 * Specified by a bitmask 15124 15125 * Specified by a four-bit or eight-bit length field L 15126 15127 * Specified by the content of a general register 15128 15129 The notation for storage operand addresses formed from multiple 15130fields is as follows: 15131 15132`Dn(Bn)' 15133 the address for operand number n is formed from the content of 15134 general register Bn called the base register and the displacement 15135 field Dn. 15136 15137`Dn(Xn,Bn)' 15138 the address for operand number n is formed from the content of 15139 general register Xn called the index register, general register Bn 15140 called the base register and the displacement field Dn. 15141 15142`Dn(Ln,Bn)' 15143 the address for operand number n is formed from the content of 15144 general regiser Bn called the base register and the displacement 15145 field Dn. The length of the operand n is specified by the field 15146 Ln. 15147 15148 The base registers Bn and the index registers Xn of a storage 15149operand can be skipped. If Bn and Xn are skipped, a zero will be stored 15150to the operand field. The notation changes as follows: 15151 15152 full notation short notation 15153 ------------------------------------------ 15154 Dn(0,Bn) Dn(Bn) 15155 Dn(0,0) Dn 15156 Dn(0) Dn 15157 Dn(Ln,0) Dn(Ln) 15158 15159 15160File: as.info, Node: s390 Formats, Next: s390 Aliases, Prev: s390 Operands, Up: s390 Syntax 15161 151629.32.3.4 Instruction Formats 15163............................ 15164 15165The Principles of Operation manuals lists 26 instruction formats where 15166some of the formats have multiple variants. For the `.insn' pseudo 15167directive the assembler recognizes some of the formats. Typically, the 15168most general variant of the instruction format is used by the `.insn' 15169directive. 15170 15171 The following table lists the abbreviations used in the table of 15172instruction formats: 15173 15174 OpCode / OpCd Part of the op code. 15175 Bx Base register number for operand x. 15176 Dx Displacement for operand x. 15177 DLx Displacement lower 12 bits for operand x. 15178 DHx Displacement higher 8-bits for operand x. 15179 Rx Register number for operand x. 15180 Xx Index register number for operand x. 15181 Ix Signed immediate for operand x. 15182 Ux Unsigned immediate for operand x. 15183 15184 An instruction is two, four, or six bytes in length and must be 15185aligned on a 2 byte boundary. The first two bits of the instruction 15186specify the length of the instruction, 00 indicates a two byte 15187instruction, 01 and 10 indicates a four byte instruction, and 11 15188indicates a six byte instruction. 15189 15190 The following table lists the s390 instruction formats that are 15191available with the `.insn' pseudo directive: 15192 15193`E format' 15194 +-------------+ 15195 | OpCode | 15196 +-------------+ 15197 0 15 15198 15199`RI format: <insn> R1,I2' 15200 +--------+----+----+------------------+ 15201 | OpCode | R1 |OpCd| I2 | 15202 +--------+----+----+------------------+ 15203 0 8 12 16 31 15204 15205`RIE format: <insn> R1,R3,I2' 15206 +--------+----+----+------------------+--------+--------+ 15207 | OpCode | R1 | R3 | I2 |////////| OpCode | 15208 +--------+----+----+------------------+--------+--------+ 15209 0 8 12 16 32 40 47 15210 15211`RIL format: <insn> R1,I2' 15212 +--------+----+----+------------------------------------+ 15213 | OpCode | R1 |OpCd| I2 | 15214 +--------+----+----+------------------------------------+ 15215 0 8 12 16 47 15216 15217`RILU format: <insn> R1,U2' 15218 +--------+----+----+------------------------------------+ 15219 | OpCode | R1 |OpCd| U2 | 15220 +--------+----+----+------------------------------------+ 15221 0 8 12 16 47 15222 15223`RIS format: <insn> R1,I2,M3,D4(B4)' 15224 +--------+----+----+----+-------------+--------+--------+ 15225 | OpCode | R1 | M3 | B4 | D4 | I2 | Opcode | 15226 +--------+----+----+----+-------------+--------+--------+ 15227 0 8 12 16 20 32 36 47 15228 15229`RR format: <insn> R1,R2' 15230 +--------+----+----+ 15231 | OpCode | R1 | R2 | 15232 +--------+----+----+ 15233 0 8 12 15 15234 15235`RRE format: <insn> R1,R2' 15236 +------------------+--------+----+----+ 15237 | OpCode |////////| R1 | R2 | 15238 +------------------+--------+----+----+ 15239 0 16 24 28 31 15240 15241`RRF format: <insn> R1,R2,R3,M4' 15242 +------------------+----+----+----+----+ 15243 | OpCode | R3 | M4 | R1 | R2 | 15244 +------------------+----+----+----+----+ 15245 0 16 20 24 28 31 15246 15247`RRS format: <insn> R1,R2,M3,D4(B4)' 15248 +--------+----+----+----+-------------+----+----+--------+ 15249 | OpCode | R1 | R3 | B4 | D4 | M3 |////| OpCode | 15250 +--------+----+----+----+-------------+----+----+--------+ 15251 0 8 12 16 20 32 36 40 47 15252 15253`RS format: <insn> R1,R3,D2(B2)' 15254 +--------+----+----+----+-------------+ 15255 | OpCode | R1 | R3 | B2 | D2 | 15256 +--------+----+----+----+-------------+ 15257 0 8 12 16 20 31 15258 15259`RSE format: <insn> R1,R3,D2(B2)' 15260 +--------+----+----+----+-------------+--------+--------+ 15261 | OpCode | R1 | R3 | B2 | D2 |////////| OpCode | 15262 +--------+----+----+----+-------------+--------+--------+ 15263 0 8 12 16 20 32 40 47 15264 15265`RSI format: <insn> R1,R3,I2' 15266 +--------+----+----+------------------------------------+ 15267 | OpCode | R1 | R3 | I2 | 15268 +--------+----+----+------------------------------------+ 15269 0 8 12 16 47 15270 15271`RSY format: <insn> R1,R3,D2(B2)' 15272 +--------+----+----+----+-------------+--------+--------+ 15273 | OpCode | R1 | R3 | B2 | DL2 | DH2 | OpCode | 15274 +--------+----+----+----+-------------+--------+--------+ 15275 0 8 12 16 20 32 40 47 15276 15277`RX format: <insn> R1,D2(X2,B2)' 15278 +--------+----+----+----+-------------+ 15279 | OpCode | R1 | X2 | B2 | D2 | 15280 +--------+----+----+----+-------------+ 15281 0 8 12 16 20 31 15282 15283`RXE format: <insn> R1,D2(X2,B2)' 15284 +--------+----+----+----+-------------+--------+--------+ 15285 | OpCode | R1 | X2 | B2 | D2 |////////| OpCode | 15286 +--------+----+----+----+-------------+--------+--------+ 15287 0 8 12 16 20 32 40 47 15288 15289`RXF format: <insn> R1,R3,D2(X2,B2)' 15290 +--------+----+----+----+-------------+----+---+--------+ 15291 | OpCode | R3 | X2 | B2 | D2 | R1 |///| OpCode | 15292 +--------+----+----+----+-------------+----+---+--------+ 15293 0 8 12 16 20 32 36 40 47 15294 15295`RXY format: <insn> R1,D2(X2,B2)' 15296 +--------+----+----+----+-------------+--------+--------+ 15297 | OpCode | R1 | X2 | B2 | DL2 | DH2 | OpCode | 15298 +--------+----+----+----+-------------+--------+--------+ 15299 0 8 12 16 20 32 36 40 47 15300 15301`S format: <insn> D2(B2)' 15302 +------------------+----+-------------+ 15303 | OpCode | B2 | D2 | 15304 +------------------+----+-------------+ 15305 0 16 20 31 15306 15307`SI format: <insn> D1(B1),I2' 15308 +--------+---------+----+-------------+ 15309 | OpCode | I2 | B1 | D1 | 15310 +--------+---------+----+-------------+ 15311 0 8 16 20 31 15312 15313`SIY format: <insn> D1(B1),U2' 15314 +--------+---------+----+-------------+--------+--------+ 15315 | OpCode | I2 | B1 | DL1 | DH1 | OpCode | 15316 +--------+---------+----+-------------+--------+--------+ 15317 0 8 16 20 32 36 40 47 15318 15319`SIL format: <insn> D1(B1),I2' 15320 +------------------+----+-------------+-----------------+ 15321 | OpCode | B1 | D1 | I2 | 15322 +------------------+----+-------------+-----------------+ 15323 0 16 20 32 47 15324 15325`SS format: <insn> D1(R1,B1),D2(B3),R3' 15326 +--------+----+----+----+-------------+----+------------+ 15327 | OpCode | R1 | R3 | B1 | D1 | B2 | D2 | 15328 +--------+----+----+----+-------------+----+------------+ 15329 0 8 12 16 20 32 36 47 15330 15331`SSE format: <insn> D1(B1),D2(B2)' 15332 +------------------+----+-------------+----+------------+ 15333 | OpCode | B1 | D1 | B2 | D2 | 15334 +------------------+----+-------------+----+------------+ 15335 0 8 12 16 20 32 36 47 15336 15337`SSF format: <insn> D1(B1),D2(B2),R3' 15338 +--------+----+----+----+-------------+----+------------+ 15339 | OpCode | R3 |OpCd| B1 | D1 | B2 | D2 | 15340 +--------+----+----+----+-------------+----+------------+ 15341 0 8 12 16 20 32 36 47 15342 15343 15344 For the complete list of all instruction format variants see the 15345Principles of Operation manuals. 15346 15347 15348File: as.info, Node: s390 Aliases, Next: s390 Operand Modifier, Prev: s390 Formats, Up: s390 Syntax 15349 153509.32.3.5 Instruction Aliases 15351............................ 15352 15353A specific bit pattern can have multiple mnemonics, for example the bit 15354pattern `0xa7000000' has the mnemonics `tmh' and `tmlh'. In addition, 15355there are a number of mnemonics recognized by `as' that are not present 15356in the Principles of Operation. These are the short forms of the 15357branch instructions, where the condition code mask operand is encoded 15358in the mnemonic. This is relevant for the branch instructions, the 15359compare and branch instructions, and the compare and trap instructions. 15360 15361 For the branch instructions there are 20 condition code strings that 15362can be used as part of the mnemonic in place of a mask operand in the 15363instruction format: 15364 15365 instruction short form 15366 ------------------------------------------ 15367 bcr M1,R2 b<m>r R2 15368 bc M1,D2(X2,B2) b<m> D2(X2,B2) 15369 brc M1,I2 j<m> I2 15370 brcl M1,I2 jg<m> I2 15371 15372 In the mnemonic for a branch instruction the condition code string 15373<m> can be any of the following: 15374 15375 o jump on overflow / if ones 15376 h jump on A high 15377 p jump on plus 15378 nle jump on not low or equal 15379 l jump on A low 15380 m jump on minus 15381 nhe jump on not high or equal 15382 lh jump on low or high 15383 ne jump on A not equal B 15384 nz jump on not zero / if not zeros 15385 e jump on A equal B 15386 z jump on zero / if zeroes 15387 nlh jump on not low or high 15388 he jump on high or equal 15389 nl jump on A not low 15390 nm jump on not minus / if not mixed 15391 le jump on low or equal 15392 nh jump on A not high 15393 np jump on not plus 15394 no jump on not overflow / if not ones 15395 15396 For the compare and branch, and compare and trap instructions there 15397are 12 condition code strings that can be used as part of the mnemonic 15398in place of a mask operand in the instruction format: 15399 15400 instruction short form 15401 -------------------------------------------------------- 15402 crb R1,R2,M3,D4(B4) crb<m> R1,R2,D4(B4) 15403 cgrb R1,R2,M3,D4(B4) cgrb<m> R1,R2,D4(B4) 15404 crj R1,R2,M3,I4 crj<m> R1,R2,I4 15405 cgrj R1,R2,M3,I4 cgrj<m> R1,R2,I4 15406 cib R1,I2,M3,D4(B4) cib<m> R1,I2,D4(B4) 15407 cgib R1,I2,M3,D4(B4) cgib<m> R1,I2,D4(B4) 15408 cij R1,I2,M3,I4 cij<m> R1,I2,I4 15409 cgij R1,I2,M3,I4 cgij<m> R1,I2,I4 15410 crt R1,R2,M3 crt<m> R1,R2 15411 cgrt R1,R2,M3 cgrt<m> R1,R2 15412 cit R1,I2,M3 cit<m> R1,I2 15413 cgit R1,I2,M3 cgit<m> R1,I2 15414 clrb R1,R2,M3,D4(B4) clrb<m> R1,R2,D4(B4) 15415 clgrb R1,R2,M3,D4(B4) clgrb<m> R1,R2,D4(B4) 15416 clrj R1,R2,M3,I4 clrj<m> R1,R2,I4 15417 clgrj R1,R2,M3,I4 clgrj<m> R1,R2,I4 15418 clib R1,I2,M3,D4(B4) clib<m> R1,I2,D4(B4) 15419 clgib R1,I2,M3,D4(B4) clgib<m> R1,I2,D4(B4) 15420 clij R1,I2,M3,I4 clij<m> R1,I2,I4 15421 clgij R1,I2,M3,I4 clgij<m> R1,I2,I4 15422 clrt R1,R2,M3 clrt<m> R1,R2 15423 clgrt R1,R2,M3 clgrt<m> R1,R2 15424 clfit R1,I2,M3 clfit<m> R1,I2 15425 clgit R1,I2,M3 clgit<m> R1,I2 15426 15427 In the mnemonic for a compare and branch and compare and trap 15428instruction the condition code string <m> can be any of the following: 15429 15430 h jump on A high 15431 nle jump on not low or equal 15432 l jump on A low 15433 nhe jump on not high or equal 15434 ne jump on A not equal B 15435 lh jump on low or high 15436 e jump on A equal B 15437 nlh jump on not low or high 15438 nl jump on A not low 15439 he jump on high or equal 15440 nh jump on A not high 15441 le jump on low or equal 15442 15443 15444File: as.info, Node: s390 Operand Modifier, Next: s390 Instruction Marker, Prev: s390 Aliases, Up: s390 Syntax 15445 154469.32.3.6 Instruction Operand Modifier 15447..................................... 15448 15449If a symbol modifier is attached to a symbol in an expression for an 15450instruction operand field, the symbol term is replaced with a reference 15451to an object in the global offset table (GOT) or the procedure linkage 15452table (PLT). The following expressions are allowed: `symbol@modifier + 15453constant', `symbol@modifier + label + constant', and `symbol@modifier - 15454label + constant'. The term `symbol' is the symbol that will be 15455entered into the GOT or PLT, `label' is a local label, and `constant' 15456is an arbitrary expression that the assembler can evaluate to a 15457constant value. 15458 15459 The term `(symbol + constant1)@modifier +/- label + constant2' is 15460also accepted but a warning message is printed and the term is 15461converted to `symbol@modifier +/- label + constant1 + constant2'. 15462 15463`@got' 15464`@got12' 15465 The @got modifier can be used for displacement fields, 16-bit 15466 immediate fields and 32-bit pc-relative immediate fields. The 15467 @got12 modifier is synonym to @got. The symbol is added to the 15468 GOT. For displacement fields and 16-bit immediate fields the 15469 symbol term is replaced with the offset from the start of the GOT 15470 to the GOT slot for the symbol. For a 32-bit pc-relative field 15471 the pc-relative offset to the GOT slot from the current 15472 instruction address is used. 15473 15474`@gotent' 15475 The @gotent modifier can be used for 32-bit pc-relative immediate 15476 fields. The symbol is added to the GOT and the symbol term is 15477 replaced with the pc-relative offset from the current instruction 15478 to the GOT slot for the symbol. 15479 15480`@gotoff' 15481 The @gotoff modifier can be used for 16-bit immediate fields. The 15482 symbol term is replaced with the offset from the start of the GOT 15483 to the address of the symbol. 15484 15485`@gotplt' 15486 The @gotplt modifier can be used for displacement fields, 16-bit 15487 immediate fields, and 32-bit pc-relative immediate fields. A 15488 procedure linkage table entry is generated for the symbol and a 15489 jump slot for the symbol is added to the GOT. For displacement 15490 fields and 16-bit immediate fields the symbol term is replaced 15491 with the offset from the start of the GOT to the jump slot for the 15492 symbol. For a 32-bit pc-relative field the pc-relative offset to 15493 the jump slot from the current instruction address is used. 15494 15495`@plt' 15496 The @plt modifier can be used for 16-bit and 32-bit pc-relative 15497 immediate fields. A procedure linkage table entry is generated for 15498 the symbol. The symbol term is replaced with the relative offset 15499 from the current instruction to the PLT entry for the symbol. 15500 15501`@pltoff' 15502 The @pltoff modifier can be used for 16-bit immediate fields. The 15503 symbol term is replaced with the offset from the start of the PLT 15504 to the address of the symbol. 15505 15506`@gotntpoff' 15507 The @gotntpoff modifier can be used for displacement fields. The 15508 symbol is added to the static TLS block and the negated offset to 15509 the symbol in the static TLS block is added to the GOT. The symbol 15510 term is replaced with the offset to the GOT slot from the start of 15511 the GOT. 15512 15513`@indntpoff' 15514 The @indntpoff modifier can be used for 32-bit pc-relative 15515 immediate fields. The symbol is added to the static TLS block and 15516 the negated offset to the symbol in the static TLS block is added 15517 to the GOT. The symbol term is replaced with the pc-relative 15518 offset to the GOT slot from the current instruction address. 15519 15520 For more information about the thread local storage modifiers 15521`gotntpoff' and `indntpoff' see the ELF extension documentation `ELF 15522Handling For Thread-Local Storage'. 15523 15524 15525File: as.info, Node: s390 Instruction Marker, Next: s390 Literal Pool Entries, Prev: s390 Operand Modifier, Up: s390 Syntax 15526 155279.32.3.7 Instruction Marker 15528........................... 15529 15530The thread local storage instruction markers are used by the linker to 15531perform code optimization. 15532 15533`:tls_load' 15534 The :tls_load marker is used to flag the load instruction in the 15535 initial exec TLS model that retrieves the offset from the thread 15536 pointer to a thread local storage variable from the GOT. 15537 15538`:tls_gdcall' 15539 The :tls_gdcall marker is used to flag the branch-and-save 15540 instruction to the __tls_get_offset function in the global dynamic 15541 TLS model. 15542 15543`:tls_ldcall' 15544 The :tls_ldcall marker is used to flag the branch-and-save 15545 instruction to the __tls_get_offset function in the local dynamic 15546 TLS model. 15547 15548 For more information about the thread local storage instruction 15549marker and the linker optimizations see the ELF extension documentation 15550`ELF Handling For Thread-Local Storage'. 15551 15552 15553File: as.info, Node: s390 Literal Pool Entries, Prev: s390 Instruction Marker, Up: s390 Syntax 15554 155559.32.3.8 Literal Pool Entries 15556............................. 15557 15558A literal pool is a collection of values. To access the values a pointer 15559to the literal pool is loaded to a register, the literal pool register. 15560Usually, register %r13 is used as the literal pool register (*note s390 15561Register::). Literal pool entries are created by adding the suffix 15562:lit1, :lit2, :lit4, or :lit8 to the end of an expression for an 15563instruction operand. The expression is added to the literal pool and the 15564operand is replaced with the offset to the literal in the literal pool. 15565 15566`:lit1' 15567 The literal pool entry is created as an 8-bit value. An operand 15568 modifier must not be used for the original expression. 15569 15570`:lit2' 15571 The literal pool entry is created as a 16 bit value. The operand 15572 modifier @got may be used in the original expression. The term 15573 `x@got:lit2' will put the got offset for the global symbol x to 15574 the literal pool as 16 bit value. 15575 15576`:lit4' 15577 The literal pool entry is created as a 32-bit value. The operand 15578 modifier @got and @plt may be used in the original expression. The 15579 term `x@got:lit4' will put the got offset for the global symbol x 15580 to the literal pool as a 32-bit value. The term `x@plt:lit4' will 15581 put the plt offset for the global symbol x to the literal pool as 15582 a 32-bit value. 15583 15584`:lit8' 15585 The literal pool entry is created as a 64-bit value. The operand 15586 modifier @got and @plt may be used in the original expression. The 15587 term `x@got:lit8' will put the got offset for the global symbol x 15588 to the literal pool as a 64-bit value. The term `x@plt:lit8' will 15589 put the plt offset for the global symbol x to the literal pool as 15590 a 64-bit value. 15591 15592 The assembler directive `.ltorg' is used to emit all literal pool 15593entries to the current position. 15594 15595 15596File: as.info, Node: s390 Directives, Next: s390 Floating Point, Prev: s390 Syntax, Up: S/390-Dependent 15597 155989.32.4 Assembler Directives 15599--------------------------- 15600 15601`as' for s390 supports all of the standard ELF assembler directives as 15602outlined in the main part of this document. Some directives have been 15603extended and there are some additional directives, which are only 15604available for the s390 `as'. 15605 15606`.insn' 15607 This directive permits the numeric representation of an 15608 instructions and makes the assembler insert the operands according 15609 to one of the instructions formats for `.insn' (*note s390 15610 Formats::). For example, the instruction `l %r1,24(%r15)' could 15611 be written as `.insn rx,0x58000000,%r1,24(%r15)'. 15612 15613`.short' 15614`.long' 15615`.quad' 15616 This directive places one or more 16-bit (.short), 32-bit (.long), 15617 or 64-bit (.quad) values into the current section. If an ELF or 15618 TLS modifier is used only the following expressions are allowed: 15619 `symbol@modifier + constant', `symbol@modifier + label + 15620 constant', and `symbol@modifier - label + constant'. The 15621 following modifiers are available: 15622 `@got' 15623 `@got12' 15624 The @got modifier can be used for .short, .long and .quad. 15625 The @got12 modifier is synonym to @got. The symbol is added 15626 to the GOT. The symbol term is replaced with offset from the 15627 start of the GOT to the GOT slot for the symbol. 15628 15629 `@gotoff' 15630 The @gotoff modifier can be used for .short, .long and .quad. 15631 The symbol term is replaced with the offset from the start of 15632 the GOT to the address of the symbol. 15633 15634 `@gotplt' 15635 The @gotplt modifier can be used for .long and .quad. A 15636 procedure linkage table entry is generated for the symbol and 15637 a jump slot for the symbol is added to the GOT. The symbol 15638 term is replaced with the offset from the start of the GOT to 15639 the jump slot for the symbol. 15640 15641 `@plt' 15642 The @plt modifier can be used for .long and .quad. A 15643 procedure linkage table entry us generated for the symbol. 15644 The symbol term is replaced with the address of the PLT entry 15645 for the symbol. 15646 15647 `@pltoff' 15648 The @pltoff modifier can be used for .short, .long and .quad. 15649 The symbol term is replaced with the offset from the start of 15650 the PLT to the address of the symbol. 15651 15652 `@tlsgd' 15653 `@tlsldm' 15654 The @tlsgd and @tlsldm modifier can be used for .long and 15655 .quad. A tls_index structure for the symbol is added to the 15656 GOT. The symbol term is replaced with the offset from the 15657 start of the GOT to the tls_index structure. 15658 15659 `@gotntpoff' 15660 `@indntpoff' 15661 The @gotntpoff and @indntpoff modifier can be used for .long 15662 and .quad. The symbol is added to the static TLS block and 15663 the negated offset to the symbol in the static TLS block is 15664 added to the GOT. For @gotntpoff the symbol term is replaced 15665 with the offset from the start of the GOT to the GOT slot, 15666 for @indntpoff the symbol term is replaced with the address 15667 of the GOT slot. 15668 15669 `@dtpoff' 15670 The @dtpoff modifier can be used for .long and .quad. The 15671 symbol term is replaced with the offset of the symbol 15672 relative to the start of the TLS block it is contained in. 15673 15674 `@ntpoff' 15675 The @ntpoff modifier can be used for .long and .quad. The 15676 symbol term is replaced with the offset of the symbol 15677 relative to the TCB pointer. 15678 15679 For more information about the thread local storage modifiers see 15680 the ELF extension documentation `ELF Handling For Thread-Local 15681 Storage'. 15682 15683`.ltorg' 15684 This directive causes the current contents of the literal pool to 15685 be dumped to the current location (*note s390 Literal Pool 15686 Entries::). 15687 15688`.machine string' 15689 This directive allows you to change the machine for which code is 15690 generated. `string' may be any of the `-march=' selection options 15691 (without the -march=), `push', or `pop'. `.machine push' saves 15692 the currently selected cpu, which may be restored with `.machine 15693 pop'. Be aware that the cpu string has to be put into double 15694 quotes in case it contains characters not appropriate for 15695 identifiers. So you have to write `"z9-109"' instead of just 15696 `z9-109'. 15697 15698 15699File: as.info, Node: s390 Floating Point, Prev: s390 Directives, Up: S/390-Dependent 15700 157019.32.5 Floating Point 15702--------------------- 15703 15704The assembler recognizes both the IEEE floating-point instruction and 15705the hexadecimal floating-point instructions. The floating-point 15706constructors `.float', `.single', and `.double' always emit the IEEE 15707format. To assemble hexadecimal floating-point constants the `.long' 15708and `.quad' directives must be used. 15709 15710 15711File: as.info, Node: SCORE-Dependent, Next: Sparc-Dependent, Prev: S/390-Dependent, Up: Machine Dependencies 15712 157139.33 SCORE Dependent Features 15714============================= 15715 15716* Menu: 15717 15718* SCORE-Opts:: Assembler options 15719* SCORE-Pseudo:: SCORE Assembler Directives 15720* SCORE-Syntax:: Syntax 15721 15722 15723File: as.info, Node: SCORE-Opts, Next: SCORE-Pseudo, Up: SCORE-Dependent 15724 157259.33.1 Options 15726-------------- 15727 15728The following table lists all available SCORE options. 15729 15730`-G NUM' 15731 This option sets the largest size of an object that can be 15732 referenced implicitly with the `gp' register. The default value is 15733 8. 15734 15735`-EB' 15736 Assemble code for a big-endian cpu 15737 15738`-EL' 15739 Assemble code for a little-endian cpu 15740 15741`-FIXDD' 15742 Assemble code for fix data dependency 15743 15744`-NWARN' 15745 Assemble code for no warning message for fix data dependency 15746 15747`-SCORE5' 15748 Assemble code for target is SCORE5 15749 15750`-SCORE5U' 15751 Assemble code for target is SCORE5U 15752 15753`-SCORE7' 15754 Assemble code for target is SCORE7, this is default setting 15755 15756`-SCORE3' 15757 Assemble code for target is SCORE3 15758 15759`-march=score7' 15760 Assemble code for target is SCORE7, this is default setting 15761 15762`-march=score3' 15763 Assemble code for target is SCORE3 15764 15765`-USE_R1' 15766 Assemble code for no warning message when using temp register r1 15767 15768`-KPIC' 15769 Generate code for PIC. This option tells the assembler to generate 15770 score position-independent macro expansions. It also tells the 15771 assembler to mark the output file as PIC. 15772 15773`-O0' 15774 Assembler will not perform any optimizations 15775 15776`-V' 15777 Sunplus release version 15778 15779 15780 15781File: as.info, Node: SCORE-Pseudo, Next: SCORE-Syntax, Prev: SCORE-Opts, Up: SCORE-Dependent 15782 157839.33.2 SCORE Assembler Directives 15784--------------------------------- 15785 15786A number of assembler directives are available for SCORE. The 15787following table is far from complete. 15788 15789`.set nwarn' 15790 Let the assembler not to generate warnings if the source machine 15791 language instructions happen data dependency. 15792 15793`.set fixdd' 15794 Let the assembler to insert bubbles (32 bit nop instruction / 16 15795 bit nop! Instruction) if the source machine language instructions 15796 happen data dependency. 15797 15798`.set nofixdd' 15799 Let the assembler to generate warnings if the source machine 15800 language instructions happen data dependency. (Default) 15801 15802`.set r1' 15803 Let the assembler not to generate warnings if the source program 15804 uses r1. allow user to use r1 15805 15806`set nor1' 15807 Let the assembler to generate warnings if the source program uses 15808 r1. (Default) 15809 15810`.sdata' 15811 Tell the assembler to add subsequent data into the sdata section 15812 15813`.rdata' 15814 Tell the assembler to add subsequent data into the rdata section 15815 15816`.frame "frame-register", "offset", "return-pc-register"' 15817 Describe a stack frame. "frame-register" is the frame register, 15818 "offset" is the distance from the frame register to the virtual 15819 frame pointer, "return-pc-register" is the return program register. 15820 You must use ".ent" before ".frame" and only one ".frame" can be 15821 used per ".ent". 15822 15823`.mask "bitmask", "frameoffset"' 15824 Indicate which of the integer registers are saved in the current 15825 function's stack frame, this is for the debugger to explain the 15826 frame chain. 15827 15828`.ent "proc-name"' 15829 Set the beginning of the procedure "proc_name". Use this directive 15830 when you want to generate information for the debugger. 15831 15832`.end proc-name' 15833 Set the end of a procedure. Use this directive to generate 15834 information for the debugger. 15835 15836`.bss' 15837 Switch the destination of following statements into the bss 15838 section, which is used for data that is uninitialized anywhere. 15839 15840 15841 15842File: as.info, Node: SCORE-Syntax, Prev: SCORE-Pseudo, Up: SCORE-Dependent 15843 158449.33.3 SCORE Syntax 15845------------------- 15846 15847* Menu: 15848 15849* SCORE-Chars:: Special Characters 15850 15851 15852File: as.info, Node: SCORE-Chars, Up: SCORE-Syntax 15853 158549.33.3.1 Special Characters 15855........................... 15856 15857The presence of a `#' appearing anywhere on a line indicates the start 15858of a comment that extends to the end of that line. 15859 15860 If a `#' appears as the first character of a line then the whole 15861line is treated as a comment, but in this case the line can also be a 15862logical line number directive (*note Comments::) or a preprocessor 15863control command (*note Preprocessing::). 15864 15865 The `;' character can be used to separate statements on the same 15866line. 15867 15868 15869File: as.info, Node: SH-Dependent, Next: SH64-Dependent, Prev: NS32K-Dependent, Up: Machine Dependencies 15870 158719.34 Renesas / SuperH SH Dependent Features 15872=========================================== 15873 15874* Menu: 15875 15876* SH Options:: Options 15877* SH Syntax:: Syntax 15878* SH Floating Point:: Floating Point 15879* SH Directives:: SH Machine Directives 15880* SH Opcodes:: Opcodes 15881 15882 15883File: as.info, Node: SH Options, Next: SH Syntax, Up: SH-Dependent 15884 158859.34.1 Options 15886-------------- 15887 15888`as' has following command-line options for the Renesas (formerly 15889Hitachi) / SuperH SH family. 15890 15891`--little' 15892 Generate little endian code. 15893 15894`--big' 15895 Generate big endian code. 15896 15897`--relax' 15898 Alter jump instructions for long displacements. 15899 15900`--small' 15901 Align sections to 4 byte boundaries, not 16. 15902 15903`--dsp' 15904 Enable sh-dsp insns, and disable sh3e / sh4 insns. 15905 15906`--renesas' 15907 Disable optimization with section symbol for compatibility with 15908 Renesas assembler. 15909 15910`--allow-reg-prefix' 15911 Allow '$' as a register name prefix. 15912 15913`--fdpic' 15914 Generate an FDPIC object file. 15915 15916`--isa=sh4 | sh4a' 15917 Specify the sh4 or sh4a instruction set. 15918 15919`--isa=dsp' 15920 Enable sh-dsp insns, and disable sh3e / sh4 insns. 15921 15922`--isa=fp' 15923 Enable sh2e, sh3e, sh4, and sh4a insn sets. 15924 15925`--isa=all' 15926 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 15927 15928`-h-tick-hex' 15929 Support H'00 style hex constants in addition to 0x00 style. 15930 15931 15932 15933File: as.info, Node: SH Syntax, Next: SH Floating Point, Prev: SH Options, Up: SH-Dependent 15934 159359.34.2 Syntax 15936------------- 15937 15938* Menu: 15939 15940* SH-Chars:: Special Characters 15941* SH-Regs:: Register Names 15942* SH-Addressing:: Addressing Modes 15943 15944 15945File: as.info, Node: SH-Chars, Next: SH-Regs, Up: SH Syntax 15946 159479.34.2.1 Special Characters 15948........................... 15949 15950`!' is the line comment character. 15951 15952 You can use `;' instead of a newline to separate statements. 15953 15954 If a `#' appears as the first character of a line then the whole 15955line is treated as a comment, but in this case the line could also be a 15956logical line number directive (*note Comments::) or a preprocessor 15957control command (*note Preprocessing::). 15958 15959 Since `$' has no special meaning, you may use it in symbol names. 15960 15961 15962File: as.info, Node: SH-Regs, Next: SH-Addressing, Prev: SH-Chars, Up: SH Syntax 15963 159649.34.2.2 Register Names 15965....................... 15966 15967You can use the predefined symbols `r0', `r1', `r2', `r3', `r4', `r5', 15968`r6', `r7', `r8', `r9', `r10', `r11', `r12', `r13', `r14', and `r15' to 15969refer to the SH registers. 15970 15971 The SH also has these control registers: 15972 15973`pr' 15974 procedure register (holds return address) 15975 15976`pc' 15977 program counter 15978 15979`mach' 15980`macl' 15981 high and low multiply accumulator registers 15982 15983`sr' 15984 status register 15985 15986`gbr' 15987 global base register 15988 15989`vbr' 15990 vector base register (for interrupt vectors) 15991 15992 15993File: as.info, Node: SH-Addressing, Prev: SH-Regs, Up: SH Syntax 15994 159959.34.2.3 Addressing Modes 15996......................... 15997 15998`as' understands the following addressing modes for the SH. `RN' in 15999the following refers to any of the numbered registers, but _not_ the 16000control registers. 16001 16002`RN' 16003 Register direct 16004 16005`@RN' 16006 Register indirect 16007 16008`@-RN' 16009 Register indirect with pre-decrement 16010 16011`@RN+' 16012 Register indirect with post-increment 16013 16014`@(DISP, RN)' 16015 Register indirect with displacement 16016 16017`@(R0, RN)' 16018 Register indexed 16019 16020`@(DISP, GBR)' 16021 `GBR' offset 16022 16023`@(R0, GBR)' 16024 GBR indexed 16025 16026`ADDR' 16027`@(DISP, PC)' 16028 PC relative address (for branch or for addressing memory). The 16029 `as' implementation allows you to use the simpler form ADDR 16030 anywhere a PC relative address is called for; the alternate form 16031 is supported for compatibility with other assemblers. 16032 16033`#IMM' 16034 Immediate data 16035 16036 16037File: as.info, Node: SH Floating Point, Next: SH Directives, Prev: SH Syntax, Up: SH-Dependent 16038 160399.34.3 Floating Point 16040--------------------- 16041 16042SH2E, SH3E and SH4 groups have on-chip floating-point unit (FPU). Other 16043SH groups can use `.float' directive to generate IEEE floating-point 16044numbers. 16045 16046 SH2E and SH3E support single-precision floating point calculations as 16047well as entirely PCAPI compatible emulation of double-precision 16048floating point calculations. SH2E and SH3E instructions are a subset of 16049the floating point calculations conforming to the IEEE754 standard. 16050 16051 In addition to single-precision and double-precision floating-point 16052operation capability, the on-chip FPU of SH4 has a 128-bit graphic 16053engine that enables 32-bit floating-point data to be processed 128 bits 16054at a time. It also supports 4 * 4 array operations and inner product 16055operations. Also, a superscalar architecture is employed that enables 16056simultaneous execution of two instructions (including FPU 16057instructions), providing performance of up to twice that of 16058conventional architectures at the same frequency. 16059 16060 16061File: as.info, Node: SH Directives, Next: SH Opcodes, Prev: SH Floating Point, Up: SH-Dependent 16062 160639.34.4 SH Machine Directives 16064---------------------------- 16065 16066`uaword' 16067`ualong' 16068 `as' will issue a warning when a misaligned `.word' or `.long' 16069 directive is used. You may use `.uaword' or `.ualong' to indicate 16070 that the value is intentionally misaligned. 16071 16072 16073File: as.info, Node: SH Opcodes, Prev: SH Directives, Up: SH-Dependent 16074 160759.34.5 Opcodes 16076-------------- 16077 16078For detailed information on the SH machine instruction set, see 16079`SH-Microcomputer User's Manual' (Renesas) or `SH-4 32-bit CPU Core 16080Architecture' (SuperH) and `SuperH (SH) 64-Bit RISC Series' (SuperH). 16081 16082 `as' implements all the standard SH opcodes. No additional 16083pseudo-instructions are needed on this family. Note, however, that 16084because `as' supports a simpler form of PC-relative addressing, you may 16085simply write (for example) 16086 16087 mov.l bar,r0 16088 16089where other assemblers might require an explicit displacement to `bar' 16090from the program counter: 16091 16092 mov.l @(DISP, PC) 16093 16094 Here is a summary of SH opcodes: 16095 16096 Legend: 16097 Rn a numbered register 16098 Rm another numbered register 16099 #imm immediate data 16100 disp displacement 16101 disp8 8-bit displacement 16102 disp12 12-bit displacement 16103 16104 add #imm,Rn lds.l @Rn+,PR 16105 add Rm,Rn mac.w @Rm+,@Rn+ 16106 addc Rm,Rn mov #imm,Rn 16107 addv Rm,Rn mov Rm,Rn 16108 and #imm,R0 mov.b Rm,@(R0,Rn) 16109 and Rm,Rn mov.b Rm,@-Rn 16110 and.b #imm,@(R0,GBR) mov.b Rm,@Rn 16111 bf disp8 mov.b @(disp,Rm),R0 16112 bra disp12 mov.b @(disp,GBR),R0 16113 bsr disp12 mov.b @(R0,Rm),Rn 16114 bt disp8 mov.b @Rm+,Rn 16115 clrmac mov.b @Rm,Rn 16116 clrt mov.b R0,@(disp,Rm) 16117 cmp/eq #imm,R0 mov.b R0,@(disp,GBR) 16118 cmp/eq Rm,Rn mov.l Rm,@(disp,Rn) 16119 cmp/ge Rm,Rn mov.l Rm,@(R0,Rn) 16120 cmp/gt Rm,Rn mov.l Rm,@-Rn 16121 cmp/hi Rm,Rn mov.l Rm,@Rn 16122 cmp/hs Rm,Rn mov.l @(disp,Rn),Rm 16123 cmp/pl Rn mov.l @(disp,GBR),R0 16124 cmp/pz Rn mov.l @(disp,PC),Rn 16125 cmp/str Rm,Rn mov.l @(R0,Rm),Rn 16126 div0s Rm,Rn mov.l @Rm+,Rn 16127 div0u mov.l @Rm,Rn 16128 div1 Rm,Rn mov.l R0,@(disp,GBR) 16129 exts.b Rm,Rn mov.w Rm,@(R0,Rn) 16130 exts.w Rm,Rn mov.w Rm,@-Rn 16131 extu.b Rm,Rn mov.w Rm,@Rn 16132 extu.w Rm,Rn mov.w @(disp,Rm),R0 16133 jmp @Rn mov.w @(disp,GBR),R0 16134 jsr @Rn mov.w @(disp,PC),Rn 16135 ldc Rn,GBR mov.w @(R0,Rm),Rn 16136 ldc Rn,SR mov.w @Rm+,Rn 16137 ldc Rn,VBR mov.w @Rm,Rn 16138 ldc.l @Rn+,GBR mov.w R0,@(disp,Rm) 16139 ldc.l @Rn+,SR mov.w R0,@(disp,GBR) 16140 ldc.l @Rn+,VBR mova @(disp,PC),R0 16141 lds Rn,MACH movt Rn 16142 lds Rn,MACL muls Rm,Rn 16143 lds Rn,PR mulu Rm,Rn 16144 lds.l @Rn+,MACH neg Rm,Rn 16145 lds.l @Rn+,MACL negc Rm,Rn 16146 16147 nop stc VBR,Rn 16148 not Rm,Rn stc.l GBR,@-Rn 16149 or #imm,R0 stc.l SR,@-Rn 16150 or Rm,Rn stc.l VBR,@-Rn 16151 or.b #imm,@(R0,GBR) sts MACH,Rn 16152 rotcl Rn sts MACL,Rn 16153 rotcr Rn sts PR,Rn 16154 rotl Rn sts.l MACH,@-Rn 16155 rotr Rn sts.l MACL,@-Rn 16156 rte sts.l PR,@-Rn 16157 rts sub Rm,Rn 16158 sett subc Rm,Rn 16159 shal Rn subv Rm,Rn 16160 shar Rn swap.b Rm,Rn 16161 shll Rn swap.w Rm,Rn 16162 shll16 Rn tas.b @Rn 16163 shll2 Rn trapa #imm 16164 shll8 Rn tst #imm,R0 16165 shlr Rn tst Rm,Rn 16166 shlr16 Rn tst.b #imm,@(R0,GBR) 16167 shlr2 Rn xor #imm,R0 16168 shlr8 Rn xor Rm,Rn 16169 sleep xor.b #imm,@(R0,GBR) 16170 stc GBR,Rn xtrct Rm,Rn 16171 stc SR,Rn 16172 16173 16174File: as.info, Node: SH64-Dependent, Next: PDP-11-Dependent, Prev: SH-Dependent, Up: Machine Dependencies 16175 161769.35 SuperH SH64 Dependent Features 16177=================================== 16178 16179* Menu: 16180 16181* SH64 Options:: Options 16182* SH64 Syntax:: Syntax 16183* SH64 Directives:: SH64 Machine Directives 16184* SH64 Opcodes:: Opcodes 16185 16186 16187File: as.info, Node: SH64 Options, Next: SH64 Syntax, Up: SH64-Dependent 16188 161899.35.1 Options 16190-------------- 16191 16192`-isa=sh4 | sh4a' 16193 Specify the sh4 or sh4a instruction set. 16194 16195`-isa=dsp' 16196 Enable sh-dsp insns, and disable sh3e / sh4 insns. 16197 16198`-isa=fp' 16199 Enable sh2e, sh3e, sh4, and sh4a insn sets. 16200 16201`-isa=all' 16202 Enable sh1, sh2, sh2e, sh3, sh3e, sh4, sh4a, and sh-dsp insn sets. 16203 16204`-isa=shmedia | -isa=shcompact' 16205 Specify the default instruction set. `SHmedia' specifies the 16206 32-bit opcodes, and `SHcompact' specifies the 16-bit opcodes 16207 compatible with previous SH families. The default depends on the 16208 ABI selected; the default for the 64-bit ABI is SHmedia, and the 16209 default for the 32-bit ABI is SHcompact. If neither the ABI nor 16210 the ISA is specified, the default is 32-bit SHcompact. 16211 16212 Note that the `.mode' pseudo-op is not permitted if the ISA is not 16213 specified on the command line. 16214 16215`-abi=32 | -abi=64' 16216 Specify the default ABI. If the ISA is specified and the ABI is 16217 not, the default ABI depends on the ISA, with SHmedia defaulting 16218 to 64-bit and SHcompact defaulting to 32-bit. 16219 16220 Note that the `.abi' pseudo-op is not permitted if the ABI is not 16221 specified on the command line. When the ABI is specified on the 16222 command line, any `.abi' pseudo-ops in the source must match it. 16223 16224`-shcompact-const-crange' 16225 Emit code-range descriptors for constants in SHcompact code 16226 sections. 16227 16228`-no-mix' 16229 Disallow SHmedia code in the same section as constants and 16230 SHcompact code. 16231 16232`-no-expand' 16233 Do not expand MOVI, PT, PTA or PTB instructions. 16234 16235`-expand-pt32' 16236 With -abi=64, expand PT, PTA and PTB instructions to 32 bits only. 16237 16238`-h-tick-hex' 16239 Support H'00 style hex constants in addition to 0x00 style. 16240 16241 16242 16243File: as.info, Node: SH64 Syntax, Next: SH64 Directives, Prev: SH64 Options, Up: SH64-Dependent 16244 162459.35.2 Syntax 16246------------- 16247 16248* Menu: 16249 16250* SH64-Chars:: Special Characters 16251* SH64-Regs:: Register Names 16252* SH64-Addressing:: Addressing Modes 16253 16254 16255File: as.info, Node: SH64-Chars, Next: SH64-Regs, Up: SH64 Syntax 16256 162579.35.2.1 Special Characters 16258........................... 16259 16260`!' is the line comment character. 16261 16262 If a `#' appears as the first character of a line then the whole 16263line is treated as a comment, but in this case the line could also be a 16264logical line number directive (*note Comments::) or a preprocessor 16265control command (*note Preprocessing::). 16266 16267 You can use `;' instead of a newline to separate statements. 16268 16269 Since `$' has no special meaning, you may use it in symbol names. 16270 16271 16272File: as.info, Node: SH64-Regs, Next: SH64-Addressing, Prev: SH64-Chars, Up: SH64 Syntax 16273 162749.35.2.2 Register Names 16275....................... 16276 16277You can use the predefined symbols `r0' through `r63' to refer to the 16278SH64 general registers, `cr0' through `cr63' for control registers, 16279`tr0' through `tr7' for target address registers, `fr0' through `fr63' 16280for single-precision floating point registers, `dr0' through `dr62' 16281(even numbered registers only) for double-precision floating point 16282registers, `fv0' through `fv60' (multiples of four only) for 16283single-precision floating point vectors, `fp0' through `fp62' (even 16284numbered registers only) for single-precision floating point pairs, 16285`mtrx0' through `mtrx48' (multiples of 16 only) for 4x4 matrices of 16286single-precision floating point registers, `pc' for the program 16287counter, and `fpscr' for the floating point status and control register. 16288 16289 You can also refer to the control registers by the mnemonics `sr', 16290`ssr', `pssr', `intevt', `expevt', `pexpevt', `tra', `spc', `pspc', 16291`resvec', `vbr', `tea', `dcr', `kcr0', `kcr1', `ctc', and `usr'. 16292 16293 16294File: as.info, Node: SH64-Addressing, Prev: SH64-Regs, Up: SH64 Syntax 16295 162969.35.2.3 Addressing Modes 16297......................... 16298 16299SH64 operands consist of either a register or immediate value. The 16300immediate value can be a constant or label reference (or portion of a 16301label reference), as in this example: 16302 16303 movi 4,r2 16304 pt function, tr4 16305 movi (function >> 16) & 65535,r0 16306 shori function & 65535, r0 16307 ld.l r0,4,r0 16308 16309 Instruction label references can reference labels in either SHmedia 16310or SHcompact. To differentiate between the two, labels in SHmedia 16311sections will always have the least significant bit set (i.e. they will 16312be odd), which SHcompact labels will have the least significant bit 16313reset (i.e. they will be even). If you need to reference the actual 16314address of a label, you can use the `datalabel' modifier, as in this 16315example: 16316 16317 .long function 16318 .long datalabel function 16319 16320 In that example, the first longword may or may not have the least 16321significant bit set depending on whether the label is an SHmedia label 16322or an SHcompact label. The second longword will be the actual address 16323of the label, regardless of what type of label it is. 16324 16325 16326File: as.info, Node: SH64 Directives, Next: SH64 Opcodes, Prev: SH64 Syntax, Up: SH64-Dependent 16327 163289.35.3 SH64 Machine Directives 16329------------------------------ 16330 16331In addition to the SH directives, the SH64 provides the following 16332directives: 16333 16334`.mode [shmedia|shcompact]' 16335`.isa [shmedia|shcompact]' 16336 Specify the ISA for the following instructions (the two directives 16337 are equivalent). Note that programs such as `objdump' rely on 16338 symbolic labels to determine when such mode switches occur (by 16339 checking the least significant bit of the label's address), so 16340 such mode/isa changes should always be followed by a label (in 16341 practice, this is true anyway). Note that you cannot use these 16342 directives if you didn't specify an ISA on the command line. 16343 16344`.abi [32|64]' 16345 Specify the ABI for the following instructions. Note that you 16346 cannot use this directive unless you specified an ABI on the 16347 command line, and the ABIs specified must match. 16348 16349`.uaquad' 16350 Like .uaword and .ualong, this allows you to specify an 16351 intentionally unaligned quadword (64 bit word). 16352 16353 16354 16355File: as.info, Node: SH64 Opcodes, Prev: SH64 Directives, Up: SH64-Dependent 16356 163579.35.4 Opcodes 16358-------------- 16359 16360For detailed information on the SH64 machine instruction set, see 16361`SuperH 64 bit RISC Series Architecture Manual' (SuperH, Inc.). 16362 16363 `as' implements all the standard SH64 opcodes. In addition, the 16364following pseudo-opcodes may be expanded into one or more alternate 16365opcodes: 16366 16367`movi' 16368 If the value doesn't fit into a standard `movi' opcode, `as' will 16369 replace the `movi' with a sequence of `movi' and `shori' opcodes. 16370 16371`pt' 16372 This expands to a sequence of `movi' and `shori' opcode, followed 16373 by a `ptrel' opcode, or to a `pta' or `ptb' opcode, depending on 16374 the label referenced. 16375 16376 16377 16378File: as.info, Node: Sparc-Dependent, Next: TIC54X-Dependent, Prev: SCORE-Dependent, Up: Machine Dependencies 16379 163809.36 SPARC Dependent Features 16381============================= 16382 16383* Menu: 16384 16385* Sparc-Opts:: Options 16386* Sparc-Aligned-Data:: Option to enforce aligned data 16387* Sparc-Syntax:: Syntax 16388* Sparc-Float:: Floating Point 16389* Sparc-Directives:: Sparc Machine Directives 16390 16391 16392File: as.info, Node: Sparc-Opts, Next: Sparc-Aligned-Data, Up: Sparc-Dependent 16393 163949.36.1 Options 16395-------------- 16396 16397The SPARC chip family includes several successive versions, using the 16398same core instruction set, but including a few additional instructions 16399at each version. There are exceptions to this however. For details on 16400what instructions each variant supports, please see the chip's 16401architecture reference manual. 16402 16403 By default, `as' assumes the core instruction set (SPARC v6), but 16404"bumps" the architecture level as needed: it switches to successively 16405higher architectures as it encounters instructions that only exist in 16406the higher levels. 16407 16408 If not configured for SPARC v9 (`sparc64-*-*') GAS will not bump 16409past sparclite by default, an option must be passed to enable the v9 16410instructions. 16411 16412 GAS treats sparclite as being compatible with v8, unless an 16413architecture is explicitly requested. SPARC v9 is always incompatible 16414with sparclite. 16415 16416`-Av6 | -Av7 | -Av8 | -Asparclet | -Asparclite' 16417`-Av8plus | -Av8plusa | -Av9 | -Av9a' 16418 Use one of the `-A' options to select one of the SPARC 16419 architectures explicitly. If you select an architecture 16420 explicitly, `as' reports a fatal error if it encounters an 16421 instruction or feature requiring an incompatible or higher level. 16422 16423 `-Av8plus' and `-Av8plusa' select a 32 bit environment. 16424 16425 `-Av9' and `-Av9a' select a 64 bit environment and are not 16426 available unless GAS is explicitly configured with 64 bit 16427 environment support. 16428 16429 `-Av8plusa' and `-Av9a' enable the SPARC V9 instruction set with 16430 UltraSPARC extensions. 16431 16432`-xarch=v8plus | -xarch=v8plusa' 16433 For compatibility with the SunOS v9 assembler. These options are 16434 equivalent to -Av8plus and -Av8plusa, respectively. 16435 16436`-bump' 16437 Warn whenever it is necessary to switch to another level. If an 16438 architecture level is explicitly requested, GAS will not issue 16439 warnings until that level is reached, and will then bump the level 16440 as required (except between incompatible levels). 16441 16442`-32 | -64' 16443 Select the word size, either 32 bits or 64 bits. These options 16444 are only available with the ELF object file format, and require 16445 that the necessary BFD support has been included. 16446 16447 16448File: as.info, Node: Sparc-Aligned-Data, Next: Sparc-Syntax, Prev: Sparc-Opts, Up: Sparc-Dependent 16449 164509.36.2 Enforcing aligned data 16451----------------------------- 16452 16453SPARC GAS normally permits data to be misaligned. For example, it 16454permits the `.long' pseudo-op to be used on a byte boundary. However, 16455the native SunOS assemblers issue an error when they see misaligned 16456data. 16457 16458 You can use the `--enforce-aligned-data' option to make SPARC GAS 16459also issue an error about misaligned data, just as the SunOS assemblers 16460do. 16461 16462 The `--enforce-aligned-data' option is not the default because gcc 16463issues misaligned data pseudo-ops when it initializes certain packed 16464data structures (structures defined using the `packed' attribute). You 16465may have to assemble with GAS in order to initialize packed data 16466structures in your own code. 16467 16468 16469File: as.info, Node: Sparc-Syntax, Next: Sparc-Float, Prev: Sparc-Aligned-Data, Up: Sparc-Dependent 16470 164719.36.3 Sparc Syntax 16472------------------- 16473 16474The assembler syntax closely follows The Sparc Architecture Manual, 16475versions 8 and 9, as well as most extensions defined by Sun for their 16476UltraSPARC and Niagara line of processors. 16477 16478* Menu: 16479 16480* Sparc-Chars:: Special Characters 16481* Sparc-Regs:: Register Names 16482* Sparc-Constants:: Constant Names 16483* Sparc-Relocs:: Relocations 16484* Sparc-Size-Translations:: Size Translations 16485 16486 16487File: as.info, Node: Sparc-Chars, Next: Sparc-Regs, Up: Sparc-Syntax 16488 164899.36.3.1 Special Characters 16490........................... 16491 16492A `!' character appearing anywhere on a line indicates the start of a 16493comment that extends to the end of that line. 16494 16495 If a `#' appears as the first character of a line then the whole 16496line is treated as a comment, but in this case the line could also be a 16497logical line number directive (*note Comments::) or a preprocessor 16498control command (*note Preprocessing::). 16499 16500 `;' can be used instead of a newline to separate statements. 16501 16502 16503File: as.info, Node: Sparc-Regs, Next: Sparc-Constants, Prev: Sparc-Chars, Up: Sparc-Syntax 16504 165059.36.3.2 Register Names 16506....................... 16507 16508The Sparc integer register file is broken down into global, outgoing, 16509local, and incoming. 16510 16511 * The 8 global registers are referred to as `%gN'. 16512 16513 * The 8 outgoing registers are referred to as `%oN'. 16514 16515 * The 8 local registers are referred to as `%lN'. 16516 16517 * The 8 incoming registers are referred to as `%iN'. 16518 16519 * The frame pointer register `%i6' can be referenced using the alias 16520 `%fp'. 16521 16522 * The stack pointer register `%o6' can be referenced using the alias 16523 `%sp'. 16524 16525 Floating point registers are simply referred to as `%fN'. When 16526assembling for pre-V9, only 32 floating point registers are available. 16527For V9 and later there are 64, but there are restrictions when 16528referencing the upper 32 registers. They can only be accessed as 16529double or quad, and thus only even or quad numbered accesses are 16530allowed. For example, `%f34' is a legal floating point register, but 16531`%f35' is not. 16532 16533 Certain V9 instructions allow access to ancillary state registers. 16534Most simply they can be referred to as `%asrN' where N can be from 16 16535to 31. However, there are some aliases defined to reference ASR 16536registers defined for various UltraSPARC processors: 16537 16538 * The tick compare register is referred to as `%tick_cmpr'. 16539 16540 * The system tick register is referred to as `%stick'. An alias, 16541 `%sys_tick', exists but is deprecated and should not be used by 16542 new software. 16543 16544 * The system tick compare register is referred to as `%stick_cmpr'. 16545 An alias, `%sys_tick_cmpr', exists but is deprecated and should 16546 not be used by new software. 16547 16548 * The software interrupt register is referred to as `%softint'. 16549 16550 * The set software interrupt register is referred to as 16551 `%set_softint'. The mnemonic `%softint_set' is provided as an 16552 alias. 16553 16554 * The clear software interrupt register is referred to as 16555 `%clear_softint'. The mnemonic `%softint_clear' is provided as an 16556 alias. 16557 16558 * The performance instrumentation counters register is referred to as 16559 `%pic'. 16560 16561 * The performance control register is referred to as `%pcr'. 16562 16563 * The graphics status register is referred to as `%gsr'. 16564 16565 * The V9 dispatch control register is referred to as `%dcr'. 16566 16567 Various V9 branch and conditional move instructions allow 16568specification of which set of integer condition codes to test. These 16569are referred to as `%xcc' and `%icc'. 16570 16571 In V9, there are 4 sets of floating point condition codes which are 16572referred to as `%fccN'. 16573 16574 Several special privileged and non-privileged registers exist: 16575 16576 * The V9 address space identifier register is referred to as `%asi'. 16577 16578 * The V9 restorable windows register is referred to as `%canrestore'. 16579 16580 * The V9 savable windows register is referred to as `%cansave'. 16581 16582 * The V9 clean windows register is referred to as `%cleanwin'. 16583 16584 * The V9 current window pointer register is referred to as `%cwp'. 16585 16586 * The floating-point queue register is referred to as `%fq'. 16587 16588 * The V8 co-processor queue register is referred to as `%cq'. 16589 16590 * The floating point status register is referred to as `%fsr'. 16591 16592 * The other windows register is referred to as `%otherwin'. 16593 16594 * The V9 program counter register is referred to as `%pc'. 16595 16596 * The V9 next program counter register is referred to as `%npc'. 16597 16598 * The V9 processor interrupt level register is referred to as `%pil'. 16599 16600 * The V9 processor state register is referred to as `%pstate'. 16601 16602 * The trap base address register is referred to as `%tba'. 16603 16604 * The V9 tick register is referred to as `%tick'. 16605 16606 * The V9 trap level is referred to as `%tl'. 16607 16608 * The V9 trap program counter is referred to as `%tpc'. 16609 16610 * The V9 trap next program counter is referred to as `%tnpc'. 16611 16612 * The V9 trap state is referred to as `%tstate'. 16613 16614 * The V9 trap type is referred to as `%tt'. 16615 16616 * The V9 condition codes is referred to as `%ccr'. 16617 16618 * The V9 floating-point registers state is referred to as `%fprs'. 16619 16620 * The V9 version register is referred to as `%ver'. 16621 16622 * The V9 window state register is referred to as `%wstate'. 16623 16624 * The Y register is referred to as `%y'. 16625 16626 * The V8 window invalid mask register is referred to as `%wim'. 16627 16628 * The V8 processor state register is referred to as `%psr'. 16629 16630 * The V9 global register level register is referred to as `%gl'. 16631 16632 Several special register names exist for hypervisor mode code: 16633 16634 * The hyperprivileged processor state register is referred to as 16635 `%hpstate'. 16636 16637 * The hyperprivileged trap state register is referred to as 16638 `%htstate'. 16639 16640 * The hyperprivileged interrupt pending register is referred to as 16641 `%hintp'. 16642 16643 * The hyperprivileged trap base address register is referred to as 16644 `%htba'. 16645 16646 * The hyperprivileged implementation version register is referred to 16647 as `%hver'. 16648 16649 * The hyperprivileged system tick compare register is referred to as 16650 `%hstick_cmpr'. Note that there is no `%hstick' register, the 16651 normal `%stick' is used. 16652 16653 16654File: as.info, Node: Sparc-Constants, Next: Sparc-Relocs, Prev: Sparc-Regs, Up: Sparc-Syntax 16655 166569.36.3.3 Constants 16657.................. 16658 16659Several Sparc instructions take an immediate operand field for which 16660mnemonic names exist. Two such examples are `membar' and `prefetch'. 16661Another example are the set of V9 memory access instruction that allow 16662specification of an address space identifier. 16663 16664 The `membar' instruction specifies a memory barrier that is the 16665defined by the operand which is a bitmask. The supported mask 16666mnemonics are: 16667 16668 * `#Sync' requests that all operations (including nonmemory 16669 reference operations) appearing prior to the `membar' must have 16670 been performed and the effects of any exceptions become visible 16671 before any instructions after the `membar' may be initiated. This 16672 corresponds to `membar' cmask field bit 2. 16673 16674 * `#MemIssue' requests that all memory reference operations 16675 appearing prior to the `membar' must have been performed before 16676 any memory operation after the `membar' may be initiated. This 16677 corresponds to `membar' cmask field bit 1. 16678 16679 * `#Lookaside' requests that a store appearing prior to the `membar' 16680 must complete before any load following the `membar' referencing 16681 the same address can be initiated. This corresponds to `membar' 16682 cmask field bit 0. 16683 16684 * `#StoreStore' defines that the effects of all stores appearing 16685 prior to the `membar' instruction must be visible to all 16686 processors before the effect of any stores following the `membar'. 16687 Equivalent to the deprecated `stbar' instruction. This 16688 corresponds to `membar' mmask field bit 3. 16689 16690 * `#LoadStore' defines all loads appearing prior to the `membar' 16691 instruction must have been performed before the effect of any 16692 stores following the `membar' is visible to any other processor. 16693 This corresponds to `membar' mmask field bit 2. 16694 16695 * `#StoreLoad' defines that the effects of all stores appearing 16696 prior to the `membar' instruction must be visible to all 16697 processors before loads following the `membar' may be performed. 16698 This corresponds to `membar' mmask field bit 1. 16699 16700 * `#LoadLoad' defines that all loads appearing prior to the `membar' 16701 instruction must have been performed before any loads following 16702 the `membar' may be performed. This corresponds to `membar' mmask 16703 field bit 0. 16704 16705 16706 These values can be ored together, for example: 16707 16708 membar #Sync 16709 membar #StoreLoad | #LoadLoad 16710 membar #StoreLoad | #StoreStore 16711 16712 The `prefetch' and `prefetcha' instructions take a prefetch function 16713code. The following prefetch function code constant mnemonics are 16714available: 16715 16716 * `#n_reads' requests a prefetch for several reads, and corresponds 16717 to a prefetch function code of 0. 16718 16719 `#one_read' requests a prefetch for one read, and corresponds to a 16720 prefetch function code of 1. 16721 16722 `#n_writes' requests a prefetch for several writes (and possibly 16723 reads), and corresponds to a prefetch function code of 2. 16724 16725 `#one_write' requests a prefetch for one write, and corresponds to 16726 a prefetch function code of 3. 16727 16728 `#page' requests a prefetch page, and corresponds to a prefetch 16729 function code of 4. 16730 16731 `#invalidate' requests a prefetch invalidate, and corresponds to a 16732 prefetch function code of 16. 16733 16734 `#unified' requests a prefetch to the nearest unified cache, and 16735 corresponds to a prefetch function code of 17. 16736 16737 `#n_reads_strong' requests a strong prefetch for several reads, 16738 and corresponds to a prefetch function code of 20. 16739 16740 `#one_read_strong' requests a strong prefetch for one read, and 16741 corresponds to a prefetch function code of 21. 16742 16743 `#n_writes_strong' requests a strong prefetch for several writes, 16744 and corresponds to a prefetch function code of 22. 16745 16746 `#one_write_strong' requests a strong prefetch for one write, and 16747 corresponds to a prefetch function code of 23. 16748 16749 Onle one prefetch code may be specified. Here are some examples: 16750 16751 prefetch [%l0 + %l2], #one_read 16752 prefetch [%g2 + 8], #n_writes 16753 prefetcha [%g1] 0x8, #unified 16754 prefetcha [%o0 + 0x10] %asi, #n_reads 16755 16756 The actual behavior of a given prefetch function code is processor 16757 specific. If a processor does not implement a given prefetch 16758 function code, it will treat the prefetch instruction as a nop. 16759 16760 For instructions that accept an immediate address space identifier, 16761 `as' provides many mnemonics corresponding to V9 defined as well 16762 as UltraSPARC and Niagara extended values. For example, `#ASI_P' 16763 and `#ASI_BLK_INIT_QUAD_LDD_AIUS'. See the V9 and processor 16764 specific manuals for details. 16765 16766 16767 16768File: as.info, Node: Sparc-Relocs, Next: Sparc-Size-Translations, Prev: Sparc-Constants, Up: Sparc-Syntax 16769 167709.36.3.4 Relocations 16771.................... 16772 16773ELF relocations are available as defined in the 32-bit and 64-bit Sparc 16774ELF specifications. 16775 16776 `R_SPARC_HI22' is obtained using `%hi' and `R_SPARC_LO10' is 16777obtained using `%lo'. Likewise `R_SPARC_HIX22' is obtained from `%hix' 16778and `R_SPARC_LOX10' is obtained using `%lox'. For example: 16779 16780 sethi %hi(symbol), %g1 16781 or %g1, %lo(symbol), %g1 16782 16783 sethi %hix(symbol), %g1 16784 xor %g1, %lox(symbol), %g1 16785 16786 These "high" mnemonics extract bits 31:10 of their operand, and the 16787"low" mnemonics extract bits 9:0 of their operand. 16788 16789 V9 code model relocations can be requested as follows: 16790 16791 * `R_SPARC_HH22' is requested using `%hh'. It can also be generated 16792 using `%uhi'. 16793 16794 * `R_SPARC_HM10' is requested using `%hm'. It can also be generated 16795 using `%ulo'. 16796 16797 * `R_SPARC_LM22' is requested using `%lm'. 16798 16799 * `R_SPARC_H44' is requested using `%h44'. 16800 16801 * `R_SPARC_M44' is requested using `%m44'. 16802 16803 * `R_SPARC_L44' is requested using `%l44'. 16804 16805 The PC relative relocation `R_SPARC_PC22' can be obtained by 16806enclosing an operand inside of `%pc22'. Likewise, the `R_SPARC_PC10' 16807relocation can be obtained using `%pc10'. These are mostly used when 16808assembling PIC code. For example, the standard PIC sequence on Sparc 16809to get the base of the global offset table, PC relative, into a 16810register, can be performed as: 16811 16812 sethi %pc22(_GLOBAL_OFFSET_TABLE_-4), %l7 16813 add %l7, %pc10(_GLOBAL_OFFSET_TABLE_+4), %l7 16814 16815 Several relocations exist to allow the link editor to potentially 16816optimize GOT data references. The `R_SPARC_GOTDATA_OP_HIX22' 16817relocation can obtained by enclosing an operand inside of 16818`%gdop_hix22'. The `R_SPARC_GOTDATA_OP_LOX10' relocation can obtained 16819by enclosing an operand inside of `%gdop_lox10'. Likewise, 16820`R_SPARC_GOTDATA_OP' can be obtained by enclosing an operand inside of 16821`%gdop'. For example, assuming the GOT base is in register `%l7': 16822 16823 sethi %gdop_hix22(symbol), %l1 16824 xor %l1, %gdop_lox10(symbol), %l1 16825 ld [%l7 + %l1], %l2, %gdop(symbol) 16826 16827 There are many relocations that can be requested for access to 16828thread local storage variables. All of the Sparc TLS mnemonics are 16829supported: 16830 16831 * `R_SPARC_TLS_GD_HI22' is requested using `%tgd_hi22'. 16832 16833 * `R_SPARC_TLS_GD_LO10' is requested using `%tgd_lo10'. 16834 16835 * `R_SPARC_TLS_GD_ADD' is requested using `%tgd_add'. 16836 16837 * `R_SPARC_TLS_GD_CALL' is requested using `%tgd_call'. 16838 16839 * `R_SPARC_TLS_LDM_HI22' is requested using `%tldm_hi22'. 16840 16841 * `R_SPARC_TLS_LDM_LO10' is requested using `%tldm_lo10'. 16842 16843 * `R_SPARC_TLS_LDM_ADD' is requested using `%tldm_add'. 16844 16845 * `R_SPARC_TLS_LDM_CALL' is requested using `%tldm_call'. 16846 16847 * `R_SPARC_TLS_LDO_HIX22' is requested using `%tldo_hix22'. 16848 16849 * `R_SPARC_TLS_LDO_LOX10' is requested using `%tldo_lox10'. 16850 16851 * `R_SPARC_TLS_LDO_ADD' is requested using `%tldo_add'. 16852 16853 * `R_SPARC_TLS_IE_HI22' is requested using `%tie_hi22'. 16854 16855 * `R_SPARC_TLS_IE_LO10' is requested using `%tie_lo10'. 16856 16857 * `R_SPARC_TLS_IE_LD' is requested using `%tie_ld'. 16858 16859 * `R_SPARC_TLS_IE_LDX' is requested using `%tie_ldx'. 16860 16861 * `R_SPARC_TLS_IE_ADD' is requested using `%tie_add'. 16862 16863 * `R_SPARC_TLS_LE_HIX22' is requested using `%tle_hix22'. 16864 16865 * `R_SPARC_TLS_LE_LOX10' is requested using `%tle_lox10'. 16866 16867 Here are some example TLS model sequences. 16868 16869 First, General Dynamic: 16870 16871 sethi %tgd_hi22(symbol), %l1 16872 add %l1, %tgd_lo10(symbol), %l1 16873 add %l7, %l1, %o0, %tgd_add(symbol) 16874 call __tls_get_addr, %tgd_call(symbol) 16875 nop 16876 16877 Local Dynamic: 16878 16879 sethi %tldm_hi22(symbol), %l1 16880 add %l1, %tldm_lo10(symbol), %l1 16881 add %l7, %l1, %o0, %tldm_add(symbol) 16882 call __tls_get_addr, %tldm_call(symbol) 16883 nop 16884 16885 sethi %tldo_hix22(symbol), %l1 16886 xor %l1, %tldo_lox10(symbol), %l1 16887 add %o0, %l1, %l1, %tldo_add(symbol) 16888 16889 Initial Exec: 16890 16891 sethi %tie_hi22(symbol), %l1 16892 add %l1, %tie_lo10(symbol), %l1 16893 ld [%l7 + %l1], %o0, %tie_ld(symbol) 16894 add %g7, %o0, %o0, %tie_add(symbol) 16895 16896 sethi %tie_hi22(symbol), %l1 16897 add %l1, %tie_lo10(symbol), %l1 16898 ldx [%l7 + %l1], %o0, %tie_ldx(symbol) 16899 add %g7, %o0, %o0, %tie_add(symbol) 16900 16901 And finally, Local Exec: 16902 16903 sethi %tle_hix22(symbol), %l1 16904 add %l1, %tle_lox10(symbol), %l1 16905 add %g7, %l1, %l1 16906 16907 When assembling for 64-bit, and a secondary constant addend is 16908specified in an address expression that would normally generate an 16909`R_SPARC_LO10' relocation, the assembler will emit an `R_SPARC_OLO10' 16910instead. 16911 16912 16913File: as.info, Node: Sparc-Size-Translations, Prev: Sparc-Relocs, Up: Sparc-Syntax 16914 169159.36.3.5 Size Translations 16916.......................... 16917 16918Often it is desirable to write code in an operand size agnostic manner. 16919`as' provides support for this via operand size opcode translations. 16920Translations are supported for loads, stores, shifts, compare-and-swap 16921atomics, and the `clr' synthetic instruction. 16922 16923 If generating 32-bit code, `as' will generate the 32-bit opcode. 16924Whereas if 64-bit code is being generated, the 64-bit opcode will be 16925emitted. For example `ldn' will be transformed into `ld' for 32-bit 16926code and `ldx' for 64-bit code. 16927 16928 Here is an example meant to demonstrate all the supported opcode 16929translations: 16930 16931 ldn [%o0], %o1 16932 ldna [%o0] %asi, %o2 16933 stn %o1, [%o0] 16934 stna %o2, [%o0] %asi 16935 slln %o3, 3, %o3 16936 srln %o4, 8, %o4 16937 sran %o5, 12, %o5 16938 casn [%o0], %o1, %o2 16939 casna [%o0] %asi, %o1, %o2 16940 clrn %g1 16941 16942 In 32-bit mode `as' will emit: 16943 16944 ld [%o0], %o1 16945 lda [%o0] %asi, %o2 16946 st %o1, [%o0] 16947 sta %o2, [%o0] %asi 16948 sll %o3, 3, %o3 16949 srl %o4, 8, %o4 16950 sra %o5, 12, %o5 16951 cas [%o0], %o1, %o2 16952 casa [%o0] %asi, %o1, %o2 16953 clr %g1 16954 16955 And in 64-bit mode `as' will emit: 16956 16957 ldx [%o0], %o1 16958 ldxa [%o0] %asi, %o2 16959 stx %o1, [%o0] 16960 stxa %o2, [%o0] %asi 16961 sllx %o3, 3, %o3 16962 srlx %o4, 8, %o4 16963 srax %o5, 12, %o5 16964 casx [%o0], %o1, %o2 16965 casxa [%o0] %asi, %o1, %o2 16966 clrx %g1 16967 16968 Finally, the `.nword' translating directive is supported as well. 16969It is documented in the section on Sparc machine directives. 16970 16971 16972File: as.info, Node: Sparc-Float, Next: Sparc-Directives, Prev: Sparc-Syntax, Up: Sparc-Dependent 16973 169749.36.4 Floating Point 16975--------------------- 16976 16977The Sparc uses IEEE floating-point numbers. 16978 16979 16980File: as.info, Node: Sparc-Directives, Prev: Sparc-Float, Up: Sparc-Dependent 16981 169829.36.5 Sparc Machine Directives 16983------------------------------- 16984 16985The Sparc version of `as' supports the following additional machine 16986directives: 16987 16988`.align' 16989 This must be followed by the desired alignment in bytes. 16990 16991`.common' 16992 This must be followed by a symbol name, a positive number, and 16993 `"bss"'. This behaves somewhat like `.comm', but the syntax is 16994 different. 16995 16996`.half' 16997 This is functionally identical to `.short'. 16998 16999`.nword' 17000 On the Sparc, the `.nword' directive produces native word sized 17001 value, ie. if assembling with -32 it is equivalent to `.word', if 17002 assembling with -64 it is equivalent to `.xword'. 17003 17004`.proc' 17005 This directive is ignored. Any text following it on the same line 17006 is also ignored. 17007 17008`.register' 17009 This directive declares use of a global application or system 17010 register. It must be followed by a register name %g2, %g3, %g6 or 17011 %g7, comma and the symbol name for that register. If symbol name 17012 is `#scratch', it is a scratch register, if it is `#ignore', it 17013 just suppresses any errors about using undeclared global register, 17014 but does not emit any information about it into the object file. 17015 This can be useful e.g. if you save the register before use and 17016 restore it after. 17017 17018`.reserve' 17019 This must be followed by a symbol name, a positive number, and 17020 `"bss"'. This behaves somewhat like `.lcomm', but the syntax is 17021 different. 17022 17023`.seg' 17024 This must be followed by `"text"', `"data"', or `"data1"'. It 17025 behaves like `.text', `.data', or `.data 1'. 17026 17027`.skip' 17028 This is functionally identical to the `.space' directive. 17029 17030`.word' 17031 On the Sparc, the `.word' directive produces 32 bit values, 17032 instead of the 16 bit values it produces on many other machines. 17033 17034`.xword' 17035 On the Sparc V9 processor, the `.xword' directive produces 64 bit 17036 values. 17037 17038 17039File: as.info, Node: TIC54X-Dependent, Next: TIC6X-Dependent, Prev: Sparc-Dependent, Up: Machine Dependencies 17040 170419.37 TIC54X Dependent Features 17042============================== 17043 17044* Menu: 17045 17046* TIC54X-Opts:: Command-line Options 17047* TIC54X-Block:: Blocking 17048* TIC54X-Env:: Environment Settings 17049* TIC54X-Constants:: Constants Syntax 17050* TIC54X-Subsyms:: String Substitution 17051* TIC54X-Locals:: Local Label Syntax 17052* TIC54X-Builtins:: Builtin Assembler Math Functions 17053* TIC54X-Ext:: Extended Addressing Support 17054* TIC54X-Directives:: Directives 17055* TIC54X-Macros:: Macro Features 17056* TIC54X-MMRegs:: Memory-mapped Registers 17057* TIC54X-Syntax:: Syntax 17058 17059 17060File: as.info, Node: TIC54X-Opts, Next: TIC54X-Block, Up: TIC54X-Dependent 17061 170629.37.1 Options 17063-------------- 17064 17065The TMS320C54X version of `as' has a few machine-dependent options. 17066 17067 You can use the `-mfar-mode' option to enable extended addressing 17068mode. All addresses will be assumed to be > 16 bits, and the 17069appropriate relocation types will be used. This option is equivalent 17070to using the `.far_mode' directive in the assembly code. If you do not 17071use the `-mfar-mode' option, all references will be assumed to be 16 17072bits. This option may be abbreviated to `-mf'. 17073 17074 You can use the `-mcpu' option to specify a particular CPU. This 17075option is equivalent to using the `.version' directive in the assembly 17076code. For recognized CPU codes, see *Note `.version': 17077TIC54X-Directives. The default CPU version is `542'. 17078 17079 You can use the `-merrors-to-file' option to redirect error output 17080to a file (this provided for those deficient environments which don't 17081provide adequate output redirection). This option may be abbreviated to 17082`-me'. 17083 17084 17085File: as.info, Node: TIC54X-Block, Next: TIC54X-Env, Prev: TIC54X-Opts, Up: TIC54X-Dependent 17086 170879.37.2 Blocking 17088--------------- 17089 17090A blocked section or memory block is guaranteed not to cross the 17091blocking boundary (usually a page, or 128 words) if it is smaller than 17092the blocking size, or to start on a page boundary if it is larger than 17093the blocking size. 17094 17095 17096File: as.info, Node: TIC54X-Env, Next: TIC54X-Constants, Prev: TIC54X-Block, Up: TIC54X-Dependent 17097 170989.37.3 Environment Settings 17099--------------------------- 17100 17101`C54XDSP_DIR' and `A_DIR' are semicolon-separated paths which are added 17102to the list of directories normally searched for source and include 17103files. `C54XDSP_DIR' will override `A_DIR'. 17104 17105 17106File: as.info, Node: TIC54X-Constants, Next: TIC54X-Subsyms, Prev: TIC54X-Env, Up: TIC54X-Dependent 17107 171089.37.4 Constants Syntax 17109----------------------- 17110 17111The TIC54X version of `as' allows the following additional constant 17112formats, using a suffix to indicate the radix: 17113 17114 Binary `000000B, 011000b' 17115 Octal `10Q, 224q' 17116 Hexadecimal `45h, 0FH' 17117 17118 17119File: as.info, Node: TIC54X-Subsyms, Next: TIC54X-Locals, Prev: TIC54X-Constants, Up: TIC54X-Dependent 17120 171219.37.5 String Substitution 17122-------------------------- 17123 17124A subset of allowable symbols (which we'll call subsyms) may be assigned 17125arbitrary string values. This is roughly equivalent to C preprocessor 17126#define macros. When `as' encounters one of these symbols, the symbol 17127is replaced in the input stream by its string value. Subsym names 17128*must* begin with a letter. 17129 17130 Subsyms may be defined using the `.asg' and `.eval' directives 17131(*Note `.asg': TIC54X-Directives, *Note `.eval': TIC54X-Directives. 17132 17133 Expansion is recursive until a previously encountered symbol is 17134seen, at which point substitution stops. 17135 17136 In this example, x is replaced with SYM2; SYM2 is replaced with 17137SYM1, and SYM1 is replaced with x. At this point, x has already been 17138encountered and the substitution stops. 17139 17140 .asg "x",SYM1 17141 .asg "SYM1",SYM2 17142 .asg "SYM2",x 17143 add x,a ; final code assembled is "add x, a" 17144 17145 Macro parameters are converted to subsyms; a side effect of this is 17146the normal `as' '\ARG' dereferencing syntax is unnecessary. Subsyms 17147defined within a macro will have global scope, unless the `.var' 17148directive is used to identify the subsym as a local macro variable 17149*note `.var': TIC54X-Directives. 17150 17151 Substitution may be forced in situations where replacement might be 17152ambiguous by placing colons on either side of the subsym. The following 17153code: 17154 17155 .eval "10",x 17156 LAB:X: add #x, a 17157 17158 When assembled becomes: 17159 17160 LAB10 add #10, a 17161 17162 Smaller parts of the string assigned to a subsym may be accessed with 17163the following syntax: 17164 17165``:SYMBOL(CHAR_INDEX):'' 17166 Evaluates to a single-character string, the character at 17167 CHAR_INDEX. 17168 17169``:SYMBOL(START,LENGTH):'' 17170 Evaluates to a substring of SYMBOL beginning at START with length 17171 LENGTH. 17172 17173 17174File: as.info, Node: TIC54X-Locals, Next: TIC54X-Builtins, Prev: TIC54X-Subsyms, Up: TIC54X-Dependent 17175 171769.37.6 Local Labels 17177------------------- 17178 17179Local labels may be defined in two ways: 17180 17181 * $N, where N is a decimal number between 0 and 9 17182 17183 * LABEL?, where LABEL is any legal symbol name. 17184 17185 Local labels thus defined may be redefined or automatically 17186generated. The scope of a local label is based on when it may be 17187undefined or reset. This happens when one of the following situations 17188is encountered: 17189 17190 * .newblock directive *note `.newblock': TIC54X-Directives. 17191 17192 * The current section is changed (.sect, .text, or .data) 17193 17194 * Entering or leaving an included file 17195 17196 * The macro scope where the label was defined is exited 17197 17198 17199File: as.info, Node: TIC54X-Builtins, Next: TIC54X-Ext, Prev: TIC54X-Locals, Up: TIC54X-Dependent 17200 172019.37.7 Math Builtins 17202-------------------- 17203 17204The following built-in functions may be used to generate a 17205floating-point value. All return a floating-point value except `$cvi', 17206`$int', and `$sgn', which return an integer value. 17207 17208``$acos(EXPR)'' 17209 Returns the floating point arccosine of EXPR. 17210 17211``$asin(EXPR)'' 17212 Returns the floating point arcsine of EXPR. 17213 17214``$atan(EXPR)'' 17215 Returns the floating point arctangent of EXPR. 17216 17217``$atan2(EXPR1,EXPR2)'' 17218 Returns the floating point arctangent of EXPR1 / EXPR2. 17219 17220``$ceil(EXPR)'' 17221 Returns the smallest integer not less than EXPR as floating point. 17222 17223``$cosh(EXPR)'' 17224 Returns the floating point hyperbolic cosine of EXPR. 17225 17226``$cos(EXPR)'' 17227 Returns the floating point cosine of EXPR. 17228 17229``$cvf(EXPR)'' 17230 Returns the integer value EXPR converted to floating-point. 17231 17232``$cvi(EXPR)'' 17233 Returns the floating point value EXPR converted to integer. 17234 17235``$exp(EXPR)'' 17236 Returns the floating point value e ^ EXPR. 17237 17238``$fabs(EXPR)'' 17239 Returns the floating point absolute value of EXPR. 17240 17241``$floor(EXPR)'' 17242 Returns the largest integer that is not greater than EXPR as 17243 floating point. 17244 17245``$fmod(EXPR1,EXPR2)'' 17246 Returns the floating point remainder of EXPR1 / EXPR2. 17247 17248``$int(EXPR)'' 17249 Returns 1 if EXPR evaluates to an integer, zero otherwise. 17250 17251``$ldexp(EXPR1,EXPR2)'' 17252 Returns the floating point value EXPR1 * 2 ^ EXPR2. 17253 17254``$log10(EXPR)'' 17255 Returns the base 10 logarithm of EXPR. 17256 17257``$log(EXPR)'' 17258 Returns the natural logarithm of EXPR. 17259 17260``$max(EXPR1,EXPR2)'' 17261 Returns the floating point maximum of EXPR1 and EXPR2. 17262 17263``$min(EXPR1,EXPR2)'' 17264 Returns the floating point minimum of EXPR1 and EXPR2. 17265 17266``$pow(EXPR1,EXPR2)'' 17267 Returns the floating point value EXPR1 ^ EXPR2. 17268 17269``$round(EXPR)'' 17270 Returns the nearest integer to EXPR as a floating point number. 17271 17272``$sgn(EXPR)'' 17273 Returns -1, 0, or 1 based on the sign of EXPR. 17274 17275``$sin(EXPR)'' 17276 Returns the floating point sine of EXPR. 17277 17278``$sinh(EXPR)'' 17279 Returns the floating point hyperbolic sine of EXPR. 17280 17281``$sqrt(EXPR)'' 17282 Returns the floating point square root of EXPR. 17283 17284``$tan(EXPR)'' 17285 Returns the floating point tangent of EXPR. 17286 17287``$tanh(EXPR)'' 17288 Returns the floating point hyperbolic tangent of EXPR. 17289 17290``$trunc(EXPR)'' 17291 Returns the integer value of EXPR truncated towards zero as 17292 floating point. 17293 17294 17295 17296File: as.info, Node: TIC54X-Ext, Next: TIC54X-Directives, Prev: TIC54X-Builtins, Up: TIC54X-Dependent 17297 172989.37.8 Extended Addressing 17299-------------------------- 17300 17301The `LDX' pseudo-op is provided for loading the extended addressing bits 17302of a label or address. For example, if an address `_label' resides in 17303extended program memory, the value of `_label' may be loaded as follows: 17304 ldx #_label,16,a ; loads extended bits of _label 17305 or #_label,a ; loads lower 16 bits of _label 17306 bacc a ; full address is in accumulator A 17307 17308 17309File: as.info, Node: TIC54X-Directives, Next: TIC54X-Macros, Prev: TIC54X-Ext, Up: TIC54X-Dependent 17310 173119.37.9 Directives 17312----------------- 17313 17314`.align [SIZE]' 17315`.even' 17316 Align the section program counter on the next boundary, based on 17317 SIZE. SIZE may be any power of 2. `.even' is equivalent to 17318 `.align' with a SIZE of 2. 17319 `1' 17320 Align SPC to word boundary 17321 17322 `2' 17323 Align SPC to longword boundary (same as .even) 17324 17325 `128' 17326 Align SPC to page boundary 17327 17328`.asg STRING, NAME' 17329 Assign NAME the string STRING. String replacement is performed on 17330 STRING before assignment. 17331 17332`.eval STRING, NAME' 17333 Evaluate the contents of string STRING and assign the result as a 17334 string to the subsym NAME. String replacement is performed on 17335 STRING before assignment. 17336 17337`.bss SYMBOL, SIZE [, [BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 17338 Reserve space for SYMBOL in the .bss section. SIZE is in words. 17339 If present, BLOCKING_FLAG indicates the allocated space should be 17340 aligned on a page boundary if it would otherwise cross a page 17341 boundary. If present, ALIGNMENT_FLAG causes the assembler to 17342 allocate SIZE on a long word boundary. 17343 17344`.byte VALUE [,...,VALUE_N]' 17345`.ubyte VALUE [,...,VALUE_N]' 17346`.char VALUE [,...,VALUE_N]' 17347`.uchar VALUE [,...,VALUE_N]' 17348 Place one or more bytes into consecutive words of the current 17349 section. The upper 8 bits of each word is zero-filled. If a 17350 label is used, it points to the word allocated for the first byte 17351 encountered. 17352 17353`.clink ["SECTION_NAME"]' 17354 Set STYP_CLINK flag for this section, which indicates to the 17355 linker that if no symbols from this section are referenced, the 17356 section should not be included in the link. If SECTION_NAME is 17357 omitted, the current section is used. 17358 17359`.c_mode' 17360 TBD. 17361 17362`.copy "FILENAME" | FILENAME' 17363`.include "FILENAME" | FILENAME' 17364 Read source statements from FILENAME. The normal include search 17365 path is used. Normally .copy will cause statements from the 17366 included file to be printed in the assembly listing and .include 17367 will not, but this distinction is not currently implemented. 17368 17369`.data' 17370 Begin assembling code into the .data section. 17371 17372`.double VALUE [,...,VALUE_N]' 17373`.ldouble VALUE [,...,VALUE_N]' 17374`.float VALUE [,...,VALUE_N]' 17375`.xfloat VALUE [,...,VALUE_N]' 17376 Place an IEEE single-precision floating-point representation of 17377 one or more floating-point values into the current section. All 17378 but `.xfloat' align the result on a longword boundary. Values are 17379 stored most-significant word first. 17380 17381`.drlist' 17382`.drnolist' 17383 Control printing of directives to the listing file. Ignored. 17384 17385`.emsg STRING' 17386`.mmsg STRING' 17387`.wmsg STRING' 17388 Emit a user-defined error, message, or warning, respectively. 17389 17390`.far_mode' 17391 Use extended addressing when assembling statements. This should 17392 appear only once per file, and is equivalent to the -mfar-mode 17393 option *note `-mfar-mode': TIC54X-Opts. 17394 17395`.fclist' 17396`.fcnolist' 17397 Control printing of false conditional blocks to the listing file. 17398 17399`.field VALUE [,SIZE]' 17400 Initialize a bitfield of SIZE bits in the current section. If 17401 VALUE is relocatable, then SIZE must be 16. SIZE defaults to 16 17402 bits. If VALUE does not fit into SIZE bits, the value will be 17403 truncated. Successive `.field' directives will pack starting at 17404 the current word, filling the most significant bits first, and 17405 aligning to the start of the next word if the field size does not 17406 fit into the space remaining in the current word. A `.align' 17407 directive with an operand of 1 will force the next `.field' 17408 directive to begin packing into a new word. If a label is used, it 17409 points to the word that contains the specified field. 17410 17411`.global SYMBOL [,...,SYMBOL_N]' 17412`.def SYMBOL [,...,SYMBOL_N]' 17413`.ref SYMBOL [,...,SYMBOL_N]' 17414 `.def' nominally identifies a symbol defined in the current file 17415 and available to other files. `.ref' identifies a symbol used in 17416 the current file but defined elsewhere. Both map to the standard 17417 `.global' directive. 17418 17419`.half VALUE [,...,VALUE_N]' 17420`.uhalf VALUE [,...,VALUE_N]' 17421`.short VALUE [,...,VALUE_N]' 17422`.ushort VALUE [,...,VALUE_N]' 17423`.int VALUE [,...,VALUE_N]' 17424`.uint VALUE [,...,VALUE_N]' 17425`.word VALUE [,...,VALUE_N]' 17426`.uword VALUE [,...,VALUE_N]' 17427 Place one or more values into consecutive words of the current 17428 section. If a label is used, it points to the word allocated for 17429 the first value encountered. 17430 17431`.label SYMBOL' 17432 Define a special SYMBOL to refer to the load time address of the 17433 current section program counter. 17434 17435`.length' 17436`.width' 17437 Set the page length and width of the output listing file. Ignored. 17438 17439`.list' 17440`.nolist' 17441 Control whether the source listing is printed. Ignored. 17442 17443`.long VALUE [,...,VALUE_N]' 17444`.ulong VALUE [,...,VALUE_N]' 17445`.xlong VALUE [,...,VALUE_N]' 17446 Place one or more 32-bit values into consecutive words in the 17447 current section. The most significant word is stored first. 17448 `.long' and `.ulong' align the result on a longword boundary; 17449 `xlong' does not. 17450 17451`.loop [COUNT]' 17452`.break [CONDITION]' 17453`.endloop' 17454 Repeatedly assemble a block of code. `.loop' begins the block, and 17455 `.endloop' marks its termination. COUNT defaults to 1024, and 17456 indicates the number of times the block should be repeated. 17457 `.break' terminates the loop so that assembly begins after the 17458 `.endloop' directive. The optional CONDITION will cause the loop 17459 to terminate only if it evaluates to zero. 17460 17461`MACRO_NAME .macro [PARAM1][,...PARAM_N]' 17462`[.mexit]' 17463`.endm' 17464 See the section on macros for more explanation (*Note 17465 TIC54X-Macros::. 17466 17467`.mlib "FILENAME" | FILENAME' 17468 Load the macro library FILENAME. FILENAME must be an archived 17469 library (BFD ar-compatible) of text files, expected to contain 17470 only macro definitions. The standard include search path is used. 17471 17472`.mlist' 17473`.mnolist' 17474 Control whether to include macro and loop block expansions in the 17475 listing output. Ignored. 17476 17477`.mmregs' 17478 Define global symbolic names for the 'c54x registers. Supposedly 17479 equivalent to executing `.set' directives for each register with 17480 its memory-mapped value, but in reality is provided only for 17481 compatibility and does nothing. 17482 17483`.newblock' 17484 This directive resets any TIC54X local labels currently defined. 17485 Normal `as' local labels are unaffected. 17486 17487`.option OPTION_LIST' 17488 Set listing options. Ignored. 17489 17490`.sblock "SECTION_NAME" | SECTION_NAME [,"NAME_N" | NAME_N]' 17491 Designate SECTION_NAME for blocking. Blocking guarantees that a 17492 section will start on a page boundary (128 words) if it would 17493 otherwise cross a page boundary. Only initialized sections may be 17494 designated with this directive. See also *Note TIC54X-Block::. 17495 17496`.sect "SECTION_NAME"' 17497 Define a named initialized section and make it the current section. 17498 17499`SYMBOL .set "VALUE"' 17500`SYMBOL .equ "VALUE"' 17501 Equate a constant VALUE to a SYMBOL, which is placed in the symbol 17502 table. SYMBOL may not be previously defined. 17503 17504`.space SIZE_IN_BITS' 17505`.bes SIZE_IN_BITS' 17506 Reserve the given number of bits in the current section and 17507 zero-fill them. If a label is used with `.space', it points to the 17508 *first* word reserved. With `.bes', the label points to the 17509 *last* word reserved. 17510 17511`.sslist' 17512`.ssnolist' 17513 Controls the inclusion of subsym replacement in the listing 17514 output. Ignored. 17515 17516`.string "STRING" [,...,"STRING_N"]' 17517`.pstring "STRING" [,...,"STRING_N"]' 17518 Place 8-bit characters from STRING into the current section. 17519 `.string' zero-fills the upper 8 bits of each word, while 17520 `.pstring' puts two characters into each word, filling the 17521 most-significant bits first. Unused space is zero-filled. If a 17522 label is used, it points to the first word initialized. 17523 17524`[STAG] .struct [OFFSET]' 17525`[NAME_1] element [COUNT_1]' 17526`[NAME_2] element [COUNT_2]' 17527`[TNAME] .tag STAGX [TCOUNT]' 17528`...' 17529`[NAME_N] element [COUNT_N]' 17530`[SSIZE] .endstruct' 17531`LABEL .tag [STAG]' 17532 Assign symbolic offsets to the elements of a structure. STAG 17533 defines a symbol to use to reference the structure. OFFSET 17534 indicates a starting value to use for the first element 17535 encountered; otherwise it defaults to zero. Each element can have 17536 a named offset, NAME, which is a symbol assigned the value of the 17537 element's offset into the structure. If STAG is missing, these 17538 become global symbols. COUNT adjusts the offset that many times, 17539 as if `element' were an array. `element' may be one of `.byte', 17540 `.word', `.long', `.float', or any equivalent of those, and the 17541 structure offset is adjusted accordingly. `.field' and `.string' 17542 are also allowed; the size of `.field' is one bit, and `.string' 17543 is considered to be one word in size. Only element descriptors, 17544 structure/union tags, `.align' and conditional assembly directives 17545 are allowed within `.struct'/`.endstruct'. `.align' aligns member 17546 offsets to word boundaries only. SSIZE, if provided, will always 17547 be assigned the size of the structure. 17548 17549 The `.tag' directive, in addition to being used to define a 17550 structure/union element within a structure, may be used to apply a 17551 structure to a symbol. Once applied to LABEL, the individual 17552 structure elements may be applied to LABEL to produce the desired 17553 offsets using LABEL as the structure base. 17554 17555`.tab' 17556 Set the tab size in the output listing. Ignored. 17557 17558`[UTAG] .union' 17559`[NAME_1] element [COUNT_1]' 17560`[NAME_2] element [COUNT_2]' 17561`[TNAME] .tag UTAGX[,TCOUNT]' 17562`...' 17563`[NAME_N] element [COUNT_N]' 17564`[USIZE] .endstruct' 17565`LABEL .tag [UTAG]' 17566 Similar to `.struct', but the offset after each element is reset to 17567 zero, and the USIZE is set to the maximum of all defined elements. 17568 Starting offset for the union is always zero. 17569 17570`[SYMBOL] .usect "SECTION_NAME", SIZE, [,[BLOCKING_FLAG] [,ALIGNMENT_FLAG]]' 17571 Reserve space for variables in a named, uninitialized section 17572 (similar to .bss). `.usect' allows definitions sections 17573 independent of .bss. SYMBOL points to the first location reserved 17574 by this allocation. The symbol may be used as a variable name. 17575 SIZE is the allocated size in words. BLOCKING_FLAG indicates 17576 whether to block this section on a page boundary (128 words) 17577 (*note TIC54X-Block::). ALIGNMENT FLAG indicates whether the 17578 section should be longword-aligned. 17579 17580`.var SYM[,..., SYM_N]' 17581 Define a subsym to be a local variable within a macro. See *Note 17582 TIC54X-Macros::. 17583 17584`.version VERSION' 17585 Set which processor to build instructions for. Though the 17586 following values are accepted, the op is ignored. 17587 `541' 17588 `542' 17589 `543' 17590 `545' 17591 `545LP' 17592 `546LP' 17593 `548' 17594 `549' 17595 17596 17597File: as.info, Node: TIC54X-Macros, Next: TIC54X-MMRegs, Prev: TIC54X-Directives, Up: TIC54X-Dependent 17598 175999.37.10 Macros 17600-------------- 17601 17602Macros do not require explicit dereferencing of arguments (i.e., \ARG). 17603 17604 During macro expansion, the macro parameters are converted to 17605subsyms. If the number of arguments passed the macro invocation 17606exceeds the number of parameters defined, the last parameter is 17607assigned the string equivalent of all remaining arguments. If fewer 17608arguments are given than parameters, the missing parameters are 17609assigned empty strings. To include a comma in an argument, you must 17610enclose the argument in quotes. 17611 17612 The following built-in subsym functions allow examination of the 17613string value of subsyms (or ordinary strings). The arguments are 17614strings unless otherwise indicated (subsyms passed as args will be 17615replaced by the strings they represent). 17616``$symlen(STR)'' 17617 Returns the length of STR. 17618 17619``$symcmp(STR1,STR2)'' 17620 Returns 0 if STR1 == STR2, non-zero otherwise. 17621 17622``$firstch(STR,CH)'' 17623 Returns index of the first occurrence of character constant CH in 17624 STR. 17625 17626``$lastch(STR,CH)'' 17627 Returns index of the last occurrence of character constant CH in 17628 STR. 17629 17630``$isdefed(SYMBOL)'' 17631 Returns zero if the symbol SYMBOL is not in the symbol table, 17632 non-zero otherwise. 17633 17634``$ismember(SYMBOL,LIST)'' 17635 Assign the first member of comma-separated string LIST to SYMBOL; 17636 LIST is reassigned the remainder of the list. Returns zero if 17637 LIST is a null string. Both arguments must be subsyms. 17638 17639``$iscons(EXPR)'' 17640 Returns 1 if string EXPR is binary, 2 if octal, 3 if hexadecimal, 17641 4 if a character, 5 if decimal, and zero if not an integer. 17642 17643``$isname(NAME)'' 17644 Returns 1 if NAME is a valid symbol name, zero otherwise. 17645 17646``$isreg(REG)'' 17647 Returns 1 if REG is a valid predefined register name (AR0-AR7 17648 only). 17649 17650``$structsz(STAG)'' 17651 Returns the size of the structure or union represented by STAG. 17652 17653``$structacc(STAG)'' 17654 Returns the reference point of the structure or union represented 17655 by STAG. Always returns zero. 17656 17657 17658 17659File: as.info, Node: TIC54X-MMRegs, Next: TIC54X-Syntax, Prev: TIC54X-Macros, Up: TIC54X-Dependent 17660 176619.37.11 Memory-mapped Registers 17662------------------------------- 17663 17664The following symbols are recognized as memory-mapped registers: 17665 17666 17667 17668File: as.info, Node: TIC54X-Syntax, Prev: TIC54X-MMRegs, Up: TIC54X-Dependent 17669 176709.37.12 TIC54X Syntax 17671--------------------- 17672 17673* Menu: 17674 17675* TIC54X-Chars:: Special Characters 17676 17677 17678File: as.info, Node: TIC54X-Chars, Up: TIC54X-Syntax 17679 176809.37.12.1 Special Characters 17681............................ 17682 17683The presence of a `;' appearing anywhere on a line indicates the start 17684of a comment that extends to the end of that line. 17685 17686 If a `#' appears as the first character of a line then the whole 17687line is treated as a comment, but in this case the line can also be a 17688logical line number directive (*note Comments::) or a preprocessor 17689control command (*note Preprocessing::). 17690 17691 The presence of an asterisk (`*') at the start of a line also 17692indicates a comment that extends to the end of that line. 17693 17694 The TIC54X assembler does not currently support a line separator 17695character. 17696 17697 17698File: as.info, Node: TIC6X-Dependent, Next: TILE-Gx-Dependent, Prev: TIC54X-Dependent, Up: Machine Dependencies 17699 177009.38 TIC6X Dependent Features 17701============================= 17702 17703* Menu: 17704 17705* TIC6X Options:: Options 17706* TIC6X Syntax:: Syntax 17707* TIC6X Directives:: Directives 17708 17709 17710File: as.info, Node: TIC6X Options, Next: TIC6X Syntax, Up: TIC6X-Dependent 17711 177129.38.1 TIC6X Options 17713-------------------- 17714 17715`-march=ARCH' 17716 Enable (only) instructions from architecture ARCH. By default, 17717 all instructions are permitted. 17718 17719 The following values of ARCH are accepted: `c62x', `c64x', 17720 `c64x+', `c67x', `c67x+', `c674x'. 17721 17722`-mdsbt' 17723`-mno-dsbt' 17724 The `-mdsbt' option causes the assembler to generate the 17725 `Tag_ABI_DSBT' attribute with a value of 1, indicating that the 17726 code is using DSBT addressing. The `-mno-dsbt' option, the 17727 default, causes the tag to have a value of 0, indicating that the 17728 code does not use DSBT addressing. The linker will emit a warning 17729 if objects of different type (DSBT and non-DSBT) are linked 17730 together. 17731 17732`-mpid=no' 17733`-mpid=near' 17734`-mpid=far' 17735 The `-mpid=' option causes the assembler to generate the 17736 `Tag_ABI_PID' attribute with a value indicating the form of data 17737 addressing used by the code. `-mpid=no', the default, indicates 17738 position-dependent data addressing, `-mpid=near' indicates 17739 position-independent addressing with GOT accesses using near DP 17740 addressing, and `-mpid=far' indicates position-independent 17741 addressing with GOT accesses using far DP addressing. The linker 17742 will emit a warning if objects built with different settings of 17743 this option are linked together. 17744 17745`-mpic' 17746`-mno-pic' 17747 The `-mpic' option causes the assembler to generate the 17748 `Tag_ABI_PIC' attribute with a value of 1, indicating that the 17749 code is using position-independent code addressing, The 17750 `-mno-pic' option, the default, causes the tag to have a value of 17751 0, indicating position-dependent code addressing. The linker will 17752 emit a warning if objects of different type (position-dependent and 17753 position-independent) are linked together. 17754 17755`-mbig-endian' 17756`-mlittle-endian' 17757 Generate code for the specified endianness. The default is 17758 little-endian. 17759 17760 17761 17762File: as.info, Node: TIC6X Syntax, Next: TIC6X Directives, Prev: TIC6X Options, Up: TIC6X-Dependent 17763 177649.38.2 TIC6X Syntax 17765------------------- 17766 17767The presence of a `;' on a line indicates the start of a comment that 17768extends to the end of the current line. If a `#' or `*' appears as the 17769first character of a line, the whole line is treated as a comment. 17770Note that if a line starts with a `#' character then it can also be a 17771logical line number directive (*note Comments::) or a preprocessor 17772control command (*note Preprocessing::). 17773 17774 The `@' character can be used instead of a newline to separate 17775statements. 17776 17777 Instruction, register and functional unit names are case-insensitive. 17778`as' requires fully-specified functional unit names, such as `.S1', 17779`.L1X' or `.D1T2', on all instructions using a functional unit. 17780 17781 For some instructions, there may be syntactic ambiguity between 17782register or functional unit names and the names of labels or other 17783symbols. To avoid this, enclose the ambiguous symbol name in 17784parentheses; register and functional unit names may not be enclosed in 17785parentheses. 17786 17787 17788File: as.info, Node: TIC6X Directives, Prev: TIC6X Syntax, Up: TIC6X-Dependent 17789 177909.38.3 TIC6X Directives 17791----------------------- 17792 17793Directives controlling the set of instructions accepted by the 17794assembler have effect for instructions between the directive and any 17795subsequent directive overriding it. 17796 17797`.arch ARCH' 17798 This has the same effect as `-march=ARCH'. 17799 17800`.cantunwind' 17801 Prevents unwinding through the current function. No personality 17802 routine or exception table data is required or permitted. 17803 17804 If this is not specified then frame unwinding information will be 17805 constructed from CFI directives. *note CFI directives::. 17806 17807`.c6xabi_attribute TAG, VALUE' 17808 Set the C6000 EABI build attribute TAG to VALUE. 17809 17810 The TAG is either an attribute number or one of `Tag_ISA', 17811 `Tag_ABI_wchar_t', `Tag_ABI_stack_align_needed', 17812 `Tag_ABI_stack_align_preserved', `Tag_ABI_DSBT', `Tag_ABI_PID', 17813 `Tag_ABI_PIC', `TAG_ABI_array_object_alignment', 17814 `TAG_ABI_array_object_align_expected', `Tag_ABI_compatibility' and 17815 `Tag_ABI_conformance'. The VALUE is either a `number', 17816 `"string"', or `number, "string"' depending on the tag. 17817 17818`.ehtype SYMBOL' 17819 Output an exception type table reference to SYMBOL. 17820 17821`.endp' 17822 Marks the end of and exception table or function. If preceeded by 17823 a `.handlerdata' directive then this also switched back to the 17824 previous text section. 17825 17826`.handlerdata' 17827 Marks the end of the current function, and the start of the 17828 exception table entry for that function. Anything between this 17829 directive and the `.endp' directive will be added to the exception 17830 table entry. 17831 17832 Must be preceded by a CFI block containing a `.cfi_lsda' directive. 17833 directive. 17834 17835`.nocmp' 17836 Disallow use of C64x+ compact instructions in the current text 17837 section. 17838 17839`.personalityindex INDEX' 17840 Sets the personality routine for the current function to the ABI 17841 specified compact routine number INDEX 17842 17843`.personality NAME' 17844 Sets the personality routine for the current function to NAME. 17845 17846`.scomm SYMBOL, SIZE, ALIGN' 17847 Like `.comm', creating a common symbol SYMBOL with size SIZE and 17848 alignment ALIGN, but unlike when using `.comm', this symbol will 17849 be placed into the small BSS section by the linker. 17850 17851 17852 17853File: as.info, Node: TILE-Gx-Dependent, Next: TILEPro-Dependent, Prev: TIC6X-Dependent, Up: Machine Dependencies 17854 178559.39 TILE-Gx Dependent Features 17856=============================== 17857 17858* Menu: 17859 17860* TILE-Gx Options:: TILE-Gx Options 17861* TILE-Gx Syntax:: TILE-Gx Syntax 17862* TILE-Gx Directives:: TILE-Gx Directives 17863 17864 17865File: as.info, Node: TILE-Gx Options, Next: TILE-Gx Syntax, Up: TILE-Gx-Dependent 17866 178679.39.1 Options 17868-------------- 17869 17870The following table lists all available TILE-Gx specific options: 17871 17872`-m32 | -m64' 17873 Select the word size, either 32 bits or 64 bits. 17874 17875 17876 17877File: as.info, Node: TILE-Gx Syntax, Next: TILE-Gx Directives, Prev: TILE-Gx Options, Up: TILE-Gx-Dependent 17878 178799.39.2 Syntax 17880------------- 17881 17882Block comments are delimited by `/*' and `*/'. End of line comments 17883may be introduced by `#'. 17884 17885 Instructions consist of a leading opcode or macro name followed by 17886whitespace and an optional comma-separated list of operands: 17887 17888 OPCODE [OPERAND, ...] 17889 17890 Instructions must be separated by a newline or semicolon. 17891 17892 There are two ways to write code: either write naked instructions, 17893which the assembler is free to combine into VLIW bundles, or specify 17894the VLIW bundles explicitly. 17895 17896 Bundles are specified using curly braces: 17897 17898 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } 17899 17900 A bundle can span multiple lines. If you want to put multiple 17901instructions on a line, whether in a bundle or not, you need to 17902separate them with semicolons as in this example. 17903 17904 A bundle may contain one or more instructions, up to the limit 17905specified by the ISA (currently three). If fewer instructions are 17906specified than the hardware supports in a bundle, the assembler inserts 17907`fnop' instructions automatically. 17908 17909 The assembler will prefer to preserve the ordering of instructions 17910within the bundle, putting the first instruction in a lower-numbered 17911pipeline than the next one, etc. This fact, combined with the optional 17912use of explicit `fnop' or `nop' instructions, allows precise control 17913over which pipeline executes each instruction. 17914 17915 If the instructions cannot be bundled in the listed order, the 17916assembler will automatically try to find a valid pipeline assignment. 17917If there is no way to bundle the instructions together, the assembler 17918reports an error. 17919 17920 The assembler does not yet auto-bundle (automatically combine 17921multiple instructions into one bundle), but it reserves the right to do 17922so in the future. If you want to force an instruction to run by 17923itself, put it in a bundle explicitly with curly braces and use `nop' 17924instructions (not `fnop') to fill the remaining pipeline slots in that 17925bundle. 17926 17927* Menu: 17928 17929* TILE-Gx Opcodes:: Opcode Naming Conventions. 17930* TILE-Gx Registers:: Register Naming. 17931* TILE-Gx Modifiers:: Symbolic Operand Modifiers. 17932 17933 17934File: as.info, Node: TILE-Gx Opcodes, Next: TILE-Gx Registers, Up: TILE-Gx Syntax 17935 179369.39.2.1 Opcode Names 17937..................... 17938 17939For a complete list of opcodes and descriptions of their semantics, see 17940`TILE-Gx Instruction Set Architecture', available upon request at 17941www.tilera.com. 17942 17943 17944File: as.info, Node: TILE-Gx Registers, Next: TILE-Gx Modifiers, Prev: TILE-Gx Opcodes, Up: TILE-Gx Syntax 17945 179469.39.2.2 Register Names 17947....................... 17948 17949General-purpose registers are represented by predefined symbols of the 17950form `rN', where N represents a number between `0' and `63'. However, 17951the following registers have canonical names that must be used instead: 17952 17953`r54' 17954 sp 17955 17956`r55' 17957 lr 17958 17959`r56' 17960 sn 17961 17962`r57' 17963 idn0 17964 17965`r58' 17966 idn1 17967 17968`r59' 17969 udn0 17970 17971`r60' 17972 udn1 17973 17974`r61' 17975 udn2 17976 17977`r62' 17978 udn3 17979 17980`r63' 17981 zero 17982 17983 17984 The assembler will emit a warning if a numeric name is used instead 17985of the non-numeric name. The `.no_require_canonical_reg_names' 17986assembler pseudo-op turns off this warning. 17987`.require_canonical_reg_names' turns it back on. 17988 17989 17990File: as.info, Node: TILE-Gx Modifiers, Prev: TILE-Gx Registers, Up: TILE-Gx Syntax 17991 179929.39.2.3 Symbolic Operand Modifiers 17993................................... 17994 17995The assembler supports several modifiers when using symbol addresses in 17996TILE-Gx instruction operands. The general syntax is the following: 17997 17998 modifier(symbol) 17999 18000 The following modifiers are supported: 18001 18002`hw0' 18003 This modifier is used to load bits 0-15 of the symbol's address. 18004 18005`hw1' 18006 This modifier is used to load bits 16-31 of the symbol's address. 18007 18008`hw2' 18009 This modifier is used to load bits 32-47 of the symbol's address. 18010 18011`hw3' 18012 This modifier is used to load bits 48-63 of the symbol's address. 18013 18014`hw0_last' 18015 This modifier yields the same value as `hw0', but it also checks 18016 that the value does not overflow. 18017 18018`hw1_last' 18019 This modifier yields the same value as `hw1', but it also checks 18020 that the value does not overflow. 18021 18022`hw2_last' 18023 This modifier yields the same value as `hw2', but it also checks 18024 that the value does not overflow. 18025 18026 A 48-bit symbolic value is constructed by using the following 18027 idiom: 18028 18029 moveli r0, hw2_last(sym) 18030 shl16insli r0, r0, hw1(sym) 18031 shl16insli r0, r0, hw0(sym) 18032 18033`hw0_got' 18034 This modifier is used to load bits 0-15 of the symbol's offset in 18035 the GOT entry corresponding to the symbol. 18036 18037`hw1_got' 18038 This modifier is used to load bits 16-31 of the symbol's offset in 18039 the GOT entry corresponding to the symbol. 18040 18041`hw2_got' 18042 This modifier is used to load bits 32-47 of the symbol's offset in 18043 the GOT entry corresponding to the symbol. 18044 18045`hw3_got' 18046 This modifier is used to load bits 48-63 of the symbol's offset in 18047 the GOT entry corresponding to the symbol. 18048 18049`hw0_last_got' 18050 This modifier yields the same value as `hw0_got', but it also 18051 checks that the value does not overflow. 18052 18053`hw1_last_got' 18054 This modifier yields the same value as `hw1_got', but it also 18055 checks that the value does not overflow. 18056 18057`hw2_last_got' 18058 This modifier yields the same value as `hw2_got', but it also 18059 checks that the value does not overflow. 18060 18061`plt' 18062 This modifier is used for function symbols. It causes a 18063 _procedure linkage table_, an array of code stubs, to be created 18064 at the time the shared object is created or linked against, 18065 together with a global offset table entry. The value is a 18066 pc-relative offset to the corresponding stub code in the procedure 18067 linkage table. This arrangement causes the run-time symbol 18068 resolver to be called to look up and set the value of the symbol 18069 the first time the function is called (at latest; depending 18070 environment variables). It is only safe to leave the symbol 18071 unresolved this way if all references are function calls. 18072 18073`hw0_tls_gd' 18074 This modifier is used to load bits 0-15 of the offset of the GOT 18075 entry of the symbol's TLS descriptor, to be used for 18076 general-dynamic TLS accesses. 18077 18078`hw1_tls_gd' 18079 This modifier is used to load bits 16-31 of the offset of the GOT 18080 entry of the symbol's TLS descriptor, to be used for 18081 general-dynamic TLS accesses. 18082 18083`hw2_tls_gd' 18084 This modifier is used to load bits 32-47 of the offset of the GOT 18085 entry of the symbol's TLS descriptor, to be used for 18086 general-dynamic TLS accesses. 18087 18088`hw3_tls_gd' 18089 This modifier is used to load bits 48-63 of the offset of the GOT 18090 entry of the symbol's TLS descriptor, to be used for 18091 general-dynamic TLS accesses. 18092 18093`hw0_last_tls_gd' 18094 This modifier yields the same value as `hw0_tls_gd', but it also 18095 checks that the value does not overflow. 18096 18097`hw1_last_tls_gd' 18098 This modifier yields the same value as `hw1_tls_gd', but it also 18099 checks that the value does not overflow. 18100 18101`hw2_last_tls_gd' 18102 This modifier yields the same value as `hw2_tls_gd', but it also 18103 checks that the value does not overflow. 18104 18105`hw0_tls_ie' 18106 This modifier is used to load bits 0-15 of the offset of the GOT 18107 entry containing the offset of the symbol's address from the TCB, 18108 to be used for initial-exec TLS accesses. 18109 18110`hw1_tls_ie' 18111 This modifier is used to load bits 16-31 of the offset of the GOT 18112 entry containing the offset of the symbol's address from the TCB, 18113 to be used for initial-exec TLS accesses. 18114 18115`hw2_tls_ie' 18116 This modifier is used to load bits 32-47 of the offset of the GOT 18117 entry containing the offset of the symbol's address from the TCB, 18118 to be used for initial-exec TLS accesses. 18119 18120`hw3_tls_ie' 18121 This modifier is used to load bits 48-63 of the offset of the GOT 18122 entry containing the offset of the symbol's address from the TCB, 18123 to be used for initial-exec TLS accesses. 18124 18125`hw0_last_tls_ie' 18126 This modifier yields the same value as `hw0_tls_ie', but it also 18127 checks that the value does not overflow. 18128 18129`hw1_last_tls_ie' 18130 This modifier yields the same value as `hw1_tls_ie', but it also 18131 checks that the value does not overflow. 18132 18133`hw2_last_tls_ie' 18134 This modifier yields the same value as `hw2_tls_ie', but it also 18135 checks that the value does not overflow. 18136 18137 18138 18139File: as.info, Node: TILE-Gx Directives, Prev: TILE-Gx Syntax, Up: TILE-Gx-Dependent 18140 181419.39.3 TILE-Gx Directives 18142------------------------- 18143 18144`.align EXPRESSION [, EXPRESSION]' 18145 This is the generic .ALIGN directive. The first argument is the 18146 requested alignment in bytes. 18147 18148`.allow_suspicious_bundles' 18149 Turns on error checking for combinations of instructions in a 18150 bundle that probably indicate a programming error. This is on by 18151 default. 18152 18153`.no_allow_suspicious_bundles' 18154 Turns off error checking for combinations of instructions in a 18155 bundle that probably indicate a programming error. 18156 18157`.require_canonical_reg_names' 18158 Require that canonical register names be used, and emit a warning 18159 if the numeric names are used. This is on by default. 18160 18161`.no_require_canonical_reg_names' 18162 Permit the use of numeric names for registers that have canonical 18163 names. 18164 18165 18166 18167File: as.info, Node: TILEPro-Dependent, Next: V850-Dependent, Prev: TILE-Gx-Dependent, Up: Machine Dependencies 18168 181699.40 TILEPro Dependent Features 18170=============================== 18171 18172* Menu: 18173 18174* TILEPro Options:: TILEPro Options 18175* TILEPro Syntax:: TILEPro Syntax 18176* TILEPro Directives:: TILEPro Directives 18177 18178 18179File: as.info, Node: TILEPro Options, Next: TILEPro Syntax, Up: TILEPro-Dependent 18180 181819.40.1 Options 18182-------------- 18183 18184`as' has no machine-dependent command-line options for TILEPro. 18185 18186 18187File: as.info, Node: TILEPro Syntax, Next: TILEPro Directives, Prev: TILEPro Options, Up: TILEPro-Dependent 18188 181899.40.2 Syntax 18190------------- 18191 18192Block comments are delimited by `/*' and `*/'. End of line comments 18193may be introduced by `#'. 18194 18195 Instructions consist of a leading opcode or macro name followed by 18196whitespace and an optional comma-separated list of operands: 18197 18198 OPCODE [OPERAND, ...] 18199 18200 Instructions must be separated by a newline or semicolon. 18201 18202 There are two ways to write code: either write naked instructions, 18203which the assembler is free to combine into VLIW bundles, or specify 18204the VLIW bundles explicitly. 18205 18206 Bundles are specified using curly braces: 18207 18208 { ADD r3,r4,r5 ; ADD r7,r8,r9 ; LW r10,r11 } 18209 18210 A bundle can span multiple lines. If you want to put multiple 18211instructions on a line, whether in a bundle or not, you need to 18212separate them with semicolons as in this example. 18213 18214 A bundle may contain one or more instructions, up to the limit 18215specified by the ISA (currently three). If fewer instructions are 18216specified than the hardware supports in a bundle, the assembler inserts 18217`fnop' instructions automatically. 18218 18219 The assembler will prefer to preserve the ordering of instructions 18220within the bundle, putting the first instruction in a lower-numbered 18221pipeline than the next one, etc. This fact, combined with the optional 18222use of explicit `fnop' or `nop' instructions, allows precise control 18223over which pipeline executes each instruction. 18224 18225 If the instructions cannot be bundled in the listed order, the 18226assembler will automatically try to find a valid pipeline assignment. 18227If there is no way to bundle the instructions together, the assembler 18228reports an error. 18229 18230 The assembler does not yet auto-bundle (automatically combine 18231multiple instructions into one bundle), but it reserves the right to do 18232so in the future. If you want to force an instruction to run by 18233itself, put it in a bundle explicitly with curly braces and use `nop' 18234instructions (not `fnop') to fill the remaining pipeline slots in that 18235bundle. 18236 18237* Menu: 18238 18239* TILEPro Opcodes:: Opcode Naming Conventions. 18240* TILEPro Registers:: Register Naming. 18241* TILEPro Modifiers:: Symbolic Operand Modifiers. 18242 18243 18244File: as.info, Node: TILEPro Opcodes, Next: TILEPro Registers, Up: TILEPro Syntax 18245 182469.40.2.1 Opcode Names 18247..................... 18248 18249For a complete list of opcodes and descriptions of their semantics, see 18250`TILE Processor User Architecture Manual', available upon request at 18251www.tilera.com. 18252 18253 18254File: as.info, Node: TILEPro Registers, Next: TILEPro Modifiers, Prev: TILEPro Opcodes, Up: TILEPro Syntax 18255 182569.40.2.2 Register Names 18257....................... 18258 18259General-purpose registers are represented by predefined symbols of the 18260form `rN', where N represents a number between `0' and `63'. However, 18261the following registers have canonical names that must be used instead: 18262 18263`r54' 18264 sp 18265 18266`r55' 18267 lr 18268 18269`r56' 18270 sn 18271 18272`r57' 18273 idn0 18274 18275`r58' 18276 idn1 18277 18278`r59' 18279 udn0 18280 18281`r60' 18282 udn1 18283 18284`r61' 18285 udn2 18286 18287`r62' 18288 udn3 18289 18290`r63' 18291 zero 18292 18293 18294 The assembler will emit a warning if a numeric name is used instead 18295of the canonical name. The `.no_require_canonical_reg_names' assembler 18296pseudo-op turns off this warning. `.require_canonical_reg_names' turns 18297it back on. 18298 18299 18300File: as.info, Node: TILEPro Modifiers, Prev: TILEPro Registers, Up: TILEPro Syntax 18301 183029.40.2.3 Symbolic Operand Modifiers 18303................................... 18304 18305The assembler supports several modifiers when using symbol addresses in 18306TILEPro instruction operands. The general syntax is the following: 18307 18308 modifier(symbol) 18309 18310 The following modifiers are supported: 18311 18312`lo16' 18313 This modifier is used to load the low 16 bits of the symbol's 18314 address, sign-extended to a 32-bit value (sign-extension allows it 18315 to be range-checked against signed 16 bit immediate operands 18316 without complaint). 18317 18318`hi16' 18319 This modifier is used to load the high 16 bits of the symbol's 18320 address, also sign-extended to a 32-bit value. 18321 18322`ha16' 18323 `ha16(N)' is identical to `hi16(N)', except if `lo16(N)' is 18324 negative it adds one to the `hi16(N)' value. This way `lo16' and 18325 `ha16' can be added to create any 32-bit value using `auli'. For 18326 example, here is how you move an arbitrary 32-bit address into r3: 18327 18328 moveli r3, lo16(sym) 18329 auli r3, r3, ha16(sym) 18330 18331`got' 18332 This modifier is used to load the offset of the GOT entry 18333 corresponding to the symbol. 18334 18335`got_lo16' 18336 This modifier is used to load the sign-extended low 16 bits of the 18337 offset of the GOT entry corresponding to the symbol. 18338 18339`got_hi16' 18340 This modifier is used to load the sign-extended high 16 bits of the 18341 offset of the GOT entry corresponding to the symbol. 18342 18343`got_ha16' 18344 This modifier is like `got_hi16', but it adds one if `got_lo16' of 18345 the input value is negative. 18346 18347`plt' 18348 This modifier is used for function symbols. It causes a 18349 _procedure linkage table_, an array of code stubs, to be created 18350 at the time the shared object is created or linked against, 18351 together with a global offset table entry. The value is a 18352 pc-relative offset to the corresponding stub code in the procedure 18353 linkage table. This arrangement causes the run-time symbol 18354 resolver to be called to look up and set the value of the symbol 18355 the first time the function is called (at latest; depending 18356 environment variables). It is only safe to leave the symbol 18357 unresolved this way if all references are function calls. 18358 18359`tls_gd' 18360 This modifier is used to load the offset of the GOT entry of the 18361 symbol's TLS descriptor, to be used for general-dynamic TLS 18362 accesses. 18363 18364`tls_gd_lo16' 18365 This modifier is used to load the sign-extended low 16 bits of the 18366 offset of the GOT entry of the symbol's TLS descriptor, to be used 18367 for general dynamic TLS accesses. 18368 18369`tls_gd_hi16' 18370 This modifier is used to load the sign-extended high 16 bits of the 18371 offset of the GOT entry of the symbol's TLS descriptor, to be used 18372 for general dynamic TLS accesses. 18373 18374`tls_gd_ha16' 18375 This modifier is like `tls_gd_hi16', but it adds one to the value 18376 if `tls_gd_lo16' of the input value is negative. 18377 18378`tls_ie' 18379 This modifier is used to load the offset of the GOT entry 18380 containing the offset of the symbol's address from the TCB, to be 18381 used for initial-exec TLS accesses. 18382 18383`tls_ie_lo16' 18384 This modifier is used to load the low 16 bits of the offset of the 18385 GOT entry containing the offset of the symbol's address from the 18386 TCB, to be used for initial-exec TLS accesses. 18387 18388`tls_ie_hi16' 18389 This modifier is used to load the high 16 bits of the offset of the 18390 GOT entry containing the offset of the symbol's address from the 18391 TCB, to be used for initial-exec TLS accesses. 18392 18393`tls_ie_ha16' 18394 This modifier is like `tls_ie_hi16', but it adds one to the value 18395 if `tls_ie_lo16' of the input value is negative. 18396 18397 18398 18399File: as.info, Node: TILEPro Directives, Prev: TILEPro Syntax, Up: TILEPro-Dependent 18400 184019.40.3 TILEPro Directives 18402------------------------- 18403 18404`.align EXPRESSION [, EXPRESSION]' 18405 This is the generic .ALIGN directive. The first argument is the 18406 requested alignment in bytes. 18407 18408`.allow_suspicious_bundles' 18409 Turns on error checking for combinations of instructions in a 18410 bundle that probably indicate a programming error. This is on by 18411 default. 18412 18413`.no_allow_suspicious_bundles' 18414 Turns off error checking for combinations of instructions in a 18415 bundle that probably indicate a programming error. 18416 18417`.require_canonical_reg_names' 18418 Require that canonical register names be used, and emit a warning 18419 if the numeric names are used. This is on by default. 18420 18421`.no_require_canonical_reg_names' 18422 Permit the use of numeric names for registers that have canonical 18423 names. 18424 18425 18426 18427File: as.info, Node: Z80-Dependent, Next: Z8000-Dependent, Prev: Xtensa-Dependent, Up: Machine Dependencies 18428 184299.41 Z80 Dependent Features 18430=========================== 18431 18432* Menu: 18433 18434* Z80 Options:: Options 18435* Z80 Syntax:: Syntax 18436* Z80 Floating Point:: Floating Point 18437* Z80 Directives:: Z80 Machine Directives 18438* Z80 Opcodes:: Opcodes 18439 18440 18441File: as.info, Node: Z80 Options, Next: Z80 Syntax, Up: Z80-Dependent 18442 184439.41.1 Options 18444-------------- 18445 18446The Zilog Z80 and Ascii R800 version of `as' have a few machine 18447dependent options. 18448`-z80' 18449 Produce code for the Z80 processor. There are additional options to 18450 request warnings and error messages for undocumented instructions. 18451 18452`-ignore-undocumented-instructions' 18453`-Wnud' 18454 Silently assemble undocumented Z80-instructions that have been 18455 adopted as documented R800-instructions. 18456 18457`-ignore-unportable-instructions' 18458`-Wnup' 18459 Silently assemble all undocumented Z80-instructions. 18460 18461`-warn-undocumented-instructions' 18462`-Wud' 18463 Issue warnings for undocumented Z80-instructions that work on 18464 R800, do not assemble other undocumented instructions without 18465 warning. 18466 18467`-warn-unportable-instructions' 18468`-Wup' 18469 Issue warnings for other undocumented Z80-instructions, do not 18470 treat any undocumented instructions as errors. 18471 18472`-forbid-undocumented-instructions' 18473`-Fud' 18474 Treat all undocumented z80-instructions as errors. 18475 18476`-forbid-unportable-instructions' 18477`-Fup' 18478 Treat undocumented z80-instructions that do not work on R800 as 18479 errors. 18480 18481`-r800' 18482 Produce code for the R800 processor. The assembler does not support 18483 undocumented instructions for the R800. In line with common 18484 practice, `as' uses Z80 instruction names for the R800 processor, 18485 as far as they exist. 18486 18487 18488File: as.info, Node: Z80 Syntax, Next: Z80 Floating Point, Prev: Z80 Options, Up: Z80-Dependent 18489 184909.41.2 Syntax 18491------------- 18492 18493The assembler syntax closely follows the 'Z80 family CPU User Manual' by 18494Zilog. In expressions a single `=' may be used as "is equal to" 18495comparison operator. 18496 18497 Suffices can be used to indicate the radix of integer constants; `H' 18498or `h' for hexadecimal, `D' or `d' for decimal, `Q', `O', `q' or `o' 18499for octal, and `B' for binary. 18500 18501 The suffix `b' denotes a backreference to local label. 18502 18503* Menu: 18504 18505* Z80-Chars:: Special Characters 18506* Z80-Regs:: Register Names 18507* Z80-Case:: Case Sensitivity 18508 18509 18510File: as.info, Node: Z80-Chars, Next: Z80-Regs, Up: Z80 Syntax 18511 185129.41.2.1 Special Characters 18513........................... 18514 18515The semicolon `;' is the line comment character; 18516 18517 If a `#' appears as the first character of a line then the whole 18518line is treated as a comment, but in this case the line could also be a 18519logical line number directive (*note Comments::) or a preprocessor 18520control command (*note Preprocessing::). 18521 18522 The Z80 assembler does not support a line separator character. 18523 18524 The dollar sign `$' can be used as a prefix for hexadecimal numbers 18525and as a symbol denoting the current location counter. 18526 18527 A backslash `\' is an ordinary character for the Z80 assembler. 18528 18529 The single quote `'' must be followed by a closing quote. If there 18530is one character in between, it is a character constant, otherwise it is 18531a string constant. 18532 18533 18534File: as.info, Node: Z80-Regs, Next: Z80-Case, Prev: Z80-Chars, Up: Z80 Syntax 18535 185369.41.2.2 Register Names 18537....................... 18538 18539The registers are referred to with the letters assigned to them by 18540Zilog. In addition `as' recognizes `ixl' and `ixh' as the least and 18541most significant octet in `ix', and similarly `iyl' and `iyh' as parts 18542of `iy'. 18543 18544 18545File: as.info, Node: Z80-Case, Prev: Z80-Regs, Up: Z80 Syntax 18546 185479.41.2.3 Case Sensitivity 18548......................... 18549 18550Upper and lower case are equivalent in register names, opcodes, 18551condition codes and assembler directives. The case of letters is 18552significant in labels and symbol names. The case is also important to 18553distinguish the suffix `b' for a backward reference to a local label 18554from the suffix `B' for a number in binary notation. 18555 18556 18557File: as.info, Node: Z80 Floating Point, Next: Z80 Directives, Prev: Z80 Syntax, Up: Z80-Dependent 18558 185599.41.3 Floating Point 18560--------------------- 18561 18562Floating-point numbers are not supported. 18563 18564 18565File: as.info, Node: Z80 Directives, Next: Z80 Opcodes, Prev: Z80 Floating Point, Up: Z80-Dependent 18566 185679.41.4 Z80 Assembler Directives 18568------------------------------- 18569 18570`as' for the Z80 supports some additional directives for compatibility 18571with other assemblers. 18572 18573 These are the additional directives in `as' for the Z80: 18574 18575`db EXPRESSION|STRING[,EXPRESSION|STRING...]' 18576`defb EXPRESSION|STRING[,EXPRESSION|STRING...]' 18577 For each STRING the characters are copied to the object file, for 18578 each other EXPRESSION the value is stored in one byte. A warning 18579 is issued in case of an overflow. 18580 18581`dw EXPRESSION[,EXPRESSION...]' 18582`defw EXPRESSION[,EXPRESSION...]' 18583 For each EXPRESSION the value is stored in two bytes, ignoring 18584 overflow. 18585 18586`d24 EXPRESSION[,EXPRESSION...]' 18587`def24 EXPRESSION[,EXPRESSION...]' 18588 For each EXPRESSION the value is stored in three bytes, ignoring 18589 overflow. 18590 18591`d32 EXPRESSION[,EXPRESSION...]' 18592`def32 EXPRESSION[,EXPRESSION...]' 18593 For each EXPRESSION the value is stored in four bytes, ignoring 18594 overflow. 18595 18596`ds COUNT[, VALUE]' 18597`defs COUNT[, VALUE]' 18598 Fill COUNT bytes in the object file with VALUE, if VALUE is 18599 omitted it defaults to zero. 18600 18601`SYMBOL equ EXPRESSION' 18602`SYMBOL defl EXPRESSION' 18603 These directives set the value of SYMBOL to EXPRESSION. If `equ' 18604 is used, it is an error if SYMBOL is already defined. Symbols 18605 defined with `equ' are not protected from redefinition. 18606 18607`set' 18608 This is a normal instruction on Z80, and not an assembler 18609 directive. 18610 18611`psect NAME' 18612 A synonym for *Note Section::, no second argument should be given. 18613 18614 18615 18616File: as.info, Node: Z80 Opcodes, Prev: Z80 Directives, Up: Z80-Dependent 18617 186189.41.5 Opcodes 18619-------------- 18620 18621In line with common practice, Z80 mnemonics are used for both the Z80 18622and the R800. 18623 18624 In many instructions it is possible to use one of the half index 18625registers (`ixl',`ixh',`iyl',`iyh') in stead of an 8-bit general 18626purpose register. This yields instructions that are documented on the 18627R800 and undocumented on the Z80. Similarly `in f,(c)' is documented 18628on the R800 and undocumented on the Z80. 18629 18630 The assembler also supports the following undocumented 18631Z80-instructions, that have not been adopted in the R800 instruction 18632set: 18633`out (c),0' 18634 Sends zero to the port pointed to by register c. 18635 18636`sli M' 18637 Equivalent to `M = (M<<1)+1', the operand M can be any operand 18638 that is valid for `sla'. One can use `sll' as a synonym for `sli'. 18639 18640`OP (ix+D), R' 18641 This is equivalent to 18642 18643 ld R, (ix+D) 18644 OPC R 18645 ld (ix+D), R 18646 18647 The operation `OPC' may be any of `res B,', `set B,', `rl', `rlc', 18648 `rr', `rrc', `sla', `sli', `sra' and `srl', and the register `R' 18649 may be any of `a', `b', `c', `d', `e', `h' and `l'. 18650 18651`OPC (iy+D), R' 18652 As above, but with `iy' instead of `ix'. 18653 18654 The web site at `http://www.z80.info' is a good starting place to 18655find more information on programming the Z80. 18656 18657 18658File: as.info, Node: Z8000-Dependent, Next: Vax-Dependent, Prev: Z80-Dependent, Up: Machine Dependencies 18659 186609.42 Z8000 Dependent Features 18661============================= 18662 18663 The Z8000 as supports both members of the Z8000 family: the 18664unsegmented Z8002, with 16 bit addresses, and the segmented Z8001 with 1866524 bit addresses. 18666 18667 When the assembler is in unsegmented mode (specified with the 18668`unsegm' directive), an address takes up one word (16 bit) sized 18669register. When the assembler is in segmented mode (specified with the 18670`segm' directive), a 24-bit address takes up a long (32 bit) register. 18671*Note Assembler Directives for the Z8000: Z8000 Directives, for a list 18672of other Z8000 specific assembler directives. 18673 18674* Menu: 18675 18676* Z8000 Options:: Command-line options for the Z8000 18677* Z8000 Syntax:: Assembler syntax for the Z8000 18678* Z8000 Directives:: Special directives for the Z8000 18679* Z8000 Opcodes:: Opcodes 18680 18681 18682File: as.info, Node: Z8000 Options, Next: Z8000 Syntax, Up: Z8000-Dependent 18683 186849.42.1 Options 18685-------------- 18686 18687`-z8001' 18688 Generate segmented code by default. 18689 18690`-z8002' 18691 Generate unsegmented code by default. 18692 18693 18694File: as.info, Node: Z8000 Syntax, Next: Z8000 Directives, Prev: Z8000 Options, Up: Z8000-Dependent 18695 186969.42.2 Syntax 18697------------- 18698 18699* Menu: 18700 18701* Z8000-Chars:: Special Characters 18702* Z8000-Regs:: Register Names 18703* Z8000-Addressing:: Addressing Modes 18704 18705 18706File: as.info, Node: Z8000-Chars, Next: Z8000-Regs, Up: Z8000 Syntax 18707 187089.42.2.1 Special Characters 18709........................... 18710 18711`!' is the line comment character. 18712 18713 If a `#' appears as the first character of a line then the whole 18714line is treated as a comment, but in this case the line could also be a 18715logical line number directive (*note Comments::) or a preprocessor 18716control command (*note Preprocessing::). 18717 18718 You can use `;' instead of a newline to separate statements. 18719 18720 18721File: as.info, Node: Z8000-Regs, Next: Z8000-Addressing, Prev: Z8000-Chars, Up: Z8000 Syntax 18722 187239.42.2.2 Register Names 18724....................... 18725 18726The Z8000 has sixteen 16 bit registers, numbered 0 to 15. You can refer 18727to different sized groups of registers by register number, with the 18728prefix `r' for 16 bit registers, `rr' for 32 bit registers and `rq' for 1872964 bit registers. You can also refer to the contents of the first 18730eight (of the sixteen 16 bit registers) by bytes. They are named `rlN' 18731and `rhN'. 18732 18733_byte registers_ 18734 rl0 rh0 rl1 rh1 rl2 rh2 rl3 rh3 18735 rl4 rh4 rl5 rh5 rl6 rh6 rl7 rh7 18736 18737_word registers_ 18738 r0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 r14 r15 18739 18740_long word registers_ 18741 rr0 rr2 rr4 rr6 rr8 rr10 rr12 rr14 18742 18743_quad word registers_ 18744 rq0 rq4 rq8 rq12 18745 18746 18747File: as.info, Node: Z8000-Addressing, Prev: Z8000-Regs, Up: Z8000 Syntax 18748 187499.42.2.3 Addressing Modes 18750......................... 18751 18752as understands the following addressing modes for the Z8000: 18753 18754`rlN' 18755`rhN' 18756`rN' 18757`rrN' 18758`rqN' 18759 Register direct: 8bit, 16bit, 32bit, and 64bit registers. 18760 18761`@rN' 18762`@rrN' 18763 Indirect register: @rrN in segmented mode, @rN in unsegmented 18764 mode. 18765 18766`ADDR' 18767 Direct: the 16 bit or 24 bit address (depending on whether the 18768 assembler is in segmented or unsegmented mode) of the operand is 18769 in the instruction. 18770 18771`address(rN)' 18772 Indexed: the 16 or 24 bit address is added to the 16 bit register 18773 to produce the final address in memory of the operand. 18774 18775`rN(#IMM)' 18776`rrN(#IMM)' 18777 Base Address: the 16 or 24 bit register is added to the 16 bit sign 18778 extended immediate displacement to produce the final address in 18779 memory of the operand. 18780 18781`rN(rM)' 18782`rrN(rM)' 18783 Base Index: the 16 or 24 bit register rN or rrN is added to the 18784 sign extended 16 bit index register rM to produce the final 18785 address in memory of the operand. 18786 18787`#XX' 18788 Immediate data XX. 18789 18790 18791File: as.info, Node: Z8000 Directives, Next: Z8000 Opcodes, Prev: Z8000 Syntax, Up: Z8000-Dependent 18792 187939.42.3 Assembler Directives for the Z8000 18794----------------------------------------- 18795 18796The Z8000 port of as includes additional assembler directives, for 18797compatibility with other Z8000 assemblers. These do not begin with `.' 18798(unlike the ordinary as directives). 18799 18800`segm' 18801`.z8001' 18802 Generate code for the segmented Z8001. 18803 18804`unsegm' 18805`.z8002' 18806 Generate code for the unsegmented Z8002. 18807 18808`name' 18809 Synonym for `.file' 18810 18811`global' 18812 Synonym for `.global' 18813 18814`wval' 18815 Synonym for `.word' 18816 18817`lval' 18818 Synonym for `.long' 18819 18820`bval' 18821 Synonym for `.byte' 18822 18823`sval' 18824 Assemble a string. `sval' expects one string literal, delimited by 18825 single quotes. It assembles each byte of the string into 18826 consecutive addresses. You can use the escape sequence `%XX' 18827 (where XX represents a two-digit hexadecimal number) to represent 18828 the character whose ASCII value is XX. Use this feature to 18829 describe single quote and other characters that may not appear in 18830 string literals as themselves. For example, the C statement 18831 `char *a = "he said \"it's 50% off\"";' is represented in Z8000 18832 assembly language (shown with the assembler output in hex at the 18833 left) as 18834 18835 68652073 sval 'he said %22it%27s 50%25 off%22%00' 18836 61696420 18837 22697427 18838 73203530 18839 25206F66 18840 662200 18841 18842`rsect' 18843 synonym for `.section' 18844 18845`block' 18846 synonym for `.space' 18847 18848`even' 18849 special case of `.align'; aligns output to even byte boundary. 18850 18851 18852File: as.info, Node: Z8000 Opcodes, Prev: Z8000 Directives, Up: Z8000-Dependent 18853 188549.42.4 Opcodes 18855-------------- 18856 18857For detailed information on the Z8000 machine instruction set, see 18858`Z8000 Technical Manual'. 18859 18860 The following table summarizes the opcodes and their arguments: 18861 18862 rs 16 bit source register 18863 rd 16 bit destination register 18864 rbs 8 bit source register 18865 rbd 8 bit destination register 18866 rrs 32 bit source register 18867 rrd 32 bit destination register 18868 rqs 64 bit source register 18869 rqd 64 bit destination register 18870 addr 16/24 bit address 18871 imm immediate data 18872 18873 adc rd,rs clrb addr cpsir @rd,@rs,rr,cc 18874 adcb rbd,rbs clrb addr(rd) cpsirb @rd,@rs,rr,cc 18875 add rd,@rs clrb rbd dab rbd 18876 add rd,addr com @rd dbjnz rbd,disp7 18877 add rd,addr(rs) com addr dec @rd,imm4m1 18878 add rd,imm16 com addr(rd) dec addr(rd),imm4m1 18879 add rd,rs com rd dec addr,imm4m1 18880 addb rbd,@rs comb @rd dec rd,imm4m1 18881 addb rbd,addr comb addr decb @rd,imm4m1 18882 addb rbd,addr(rs) comb addr(rd) decb addr(rd),imm4m1 18883 addb rbd,imm8 comb rbd decb addr,imm4m1 18884 addb rbd,rbs comflg flags decb rbd,imm4m1 18885 addl rrd,@rs cp @rd,imm16 di i2 18886 addl rrd,addr cp addr(rd),imm16 div rrd,@rs 18887 addl rrd,addr(rs) cp addr,imm16 div rrd,addr 18888 addl rrd,imm32 cp rd,@rs div rrd,addr(rs) 18889 addl rrd,rrs cp rd,addr div rrd,imm16 18890 and rd,@rs cp rd,addr(rs) div rrd,rs 18891 and rd,addr cp rd,imm16 divl rqd,@rs 18892 and rd,addr(rs) cp rd,rs divl rqd,addr 18893 and rd,imm16 cpb @rd,imm8 divl rqd,addr(rs) 18894 and rd,rs cpb addr(rd),imm8 divl rqd,imm32 18895 andb rbd,@rs cpb addr,imm8 divl rqd,rrs 18896 andb rbd,addr cpb rbd,@rs djnz rd,disp7 18897 andb rbd,addr(rs) cpb rbd,addr ei i2 18898 andb rbd,imm8 cpb rbd,addr(rs) ex rd,@rs 18899 andb rbd,rbs cpb rbd,imm8 ex rd,addr 18900 bit @rd,imm4 cpb rbd,rbs ex rd,addr(rs) 18901 bit addr(rd),imm4 cpd rd,@rs,rr,cc ex rd,rs 18902 bit addr,imm4 cpdb rbd,@rs,rr,cc exb rbd,@rs 18903 bit rd,imm4 cpdr rd,@rs,rr,cc exb rbd,addr 18904 bit rd,rs cpdrb rbd,@rs,rr,cc exb rbd,addr(rs) 18905 bitb @rd,imm4 cpi rd,@rs,rr,cc exb rbd,rbs 18906 bitb addr(rd),imm4 cpib rbd,@rs,rr,cc ext0e imm8 18907 bitb addr,imm4 cpir rd,@rs,rr,cc ext0f imm8 18908 bitb rbd,imm4 cpirb rbd,@rs,rr,cc ext8e imm8 18909 bitb rbd,rs cpl rrd,@rs ext8f imm8 18910 bpt cpl rrd,addr exts rrd 18911 call @rd cpl rrd,addr(rs) extsb rd 18912 call addr cpl rrd,imm32 extsl rqd 18913 call addr(rd) cpl rrd,rrs halt 18914 calr disp12 cpsd @rd,@rs,rr,cc in rd,@rs 18915 clr @rd cpsdb @rd,@rs,rr,cc in rd,imm16 18916 clr addr cpsdr @rd,@rs,rr,cc inb rbd,@rs 18917 clr addr(rd) cpsdrb @rd,@rs,rr,cc inb rbd,imm16 18918 clr rd cpsi @rd,@rs,rr,cc inc @rd,imm4m1 18919 clrb @rd cpsib @rd,@rs,rr,cc inc addr(rd),imm4m1 18920 inc addr,imm4m1 ldb rbd,rs(rx) mult rrd,addr(rs) 18921 inc rd,imm4m1 ldb rd(imm16),rbs mult rrd,imm16 18922 incb @rd,imm4m1 ldb rd(rx),rbs mult rrd,rs 18923 incb addr(rd),imm4m1 ldctl ctrl,rs multl rqd,@rs 18924 incb addr,imm4m1 ldctl rd,ctrl multl rqd,addr 18925 incb rbd,imm4m1 ldd @rs,@rd,rr multl rqd,addr(rs) 18926 ind @rd,@rs,ra lddb @rs,@rd,rr multl rqd,imm32 18927 indb @rd,@rs,rba lddr @rs,@rd,rr multl rqd,rrs 18928 inib @rd,@rs,ra lddrb @rs,@rd,rr neg @rd 18929 inibr @rd,@rs,ra ldi @rd,@rs,rr neg addr 18930 iret ldib @rd,@rs,rr neg addr(rd) 18931 jp cc,@rd ldir @rd,@rs,rr neg rd 18932 jp cc,addr ldirb @rd,@rs,rr negb @rd 18933 jp cc,addr(rd) ldk rd,imm4 negb addr 18934 jr cc,disp8 ldl @rd,rrs negb addr(rd) 18935 ld @rd,imm16 ldl addr(rd),rrs negb rbd 18936 ld @rd,rs ldl addr,rrs nop 18937 ld addr(rd),imm16 ldl rd(imm16),rrs or rd,@rs 18938 ld addr(rd),rs ldl rd(rx),rrs or rd,addr 18939 ld addr,imm16 ldl rrd,@rs or rd,addr(rs) 18940 ld addr,rs ldl rrd,addr or rd,imm16 18941 ld rd(imm16),rs ldl rrd,addr(rs) or rd,rs 18942 ld rd(rx),rs ldl rrd,imm32 orb rbd,@rs 18943 ld rd,@rs ldl rrd,rrs orb rbd,addr 18944 ld rd,addr ldl rrd,rs(imm16) orb rbd,addr(rs) 18945 ld rd,addr(rs) ldl rrd,rs(rx) orb rbd,imm8 18946 ld rd,imm16 ldm @rd,rs,n orb rbd,rbs 18947 ld rd,rs ldm addr(rd),rs,n out @rd,rs 18948 ld rd,rs(imm16) ldm addr,rs,n out imm16,rs 18949 ld rd,rs(rx) ldm rd,@rs,n outb @rd,rbs 18950 lda rd,addr ldm rd,addr(rs),n outb imm16,rbs 18951 lda rd,addr(rs) ldm rd,addr,n outd @rd,@rs,ra 18952 lda rd,rs(imm16) ldps @rs outdb @rd,@rs,rba 18953 lda rd,rs(rx) ldps addr outib @rd,@rs,ra 18954 ldar rd,disp16 ldps addr(rs) outibr @rd,@rs,ra 18955 ldb @rd,imm8 ldr disp16,rs pop @rd,@rs 18956 ldb @rd,rbs ldr rd,disp16 pop addr(rd),@rs 18957 ldb addr(rd),imm8 ldrb disp16,rbs pop addr,@rs 18958 ldb addr(rd),rbs ldrb rbd,disp16 pop rd,@rs 18959 ldb addr,imm8 ldrl disp16,rrs popl @rd,@rs 18960 ldb addr,rbs ldrl rrd,disp16 popl addr(rd),@rs 18961 ldb rbd,@rs mbit popl addr,@rs 18962 ldb rbd,addr mreq rd popl rrd,@rs 18963 ldb rbd,addr(rs) mres push @rd,@rs 18964 ldb rbd,imm8 mset push @rd,addr 18965 ldb rbd,rbs mult rrd,@rs push @rd,addr(rs) 18966 ldb rbd,rs(imm16) mult rrd,addr push @rd,imm16 18967 push @rd,rs set addr,imm4 subl rrd,imm32 18968 pushl @rd,@rs set rd,imm4 subl rrd,rrs 18969 pushl @rd,addr set rd,rs tcc cc,rd 18970 pushl @rd,addr(rs) setb @rd,imm4 tccb cc,rbd 18971 pushl @rd,rrs setb addr(rd),imm4 test @rd 18972 res @rd,imm4 setb addr,imm4 test addr 18973 res addr(rd),imm4 setb rbd,imm4 test addr(rd) 18974 res addr,imm4 setb rbd,rs test rd 18975 res rd,imm4 setflg imm4 testb @rd 18976 res rd,rs sinb rbd,imm16 testb addr 18977 resb @rd,imm4 sinb rd,imm16 testb addr(rd) 18978 resb addr(rd),imm4 sind @rd,@rs,ra testb rbd 18979 resb addr,imm4 sindb @rd,@rs,rba testl @rd 18980 resb rbd,imm4 sinib @rd,@rs,ra testl addr 18981 resb rbd,rs sinibr @rd,@rs,ra testl addr(rd) 18982 resflg imm4 sla rd,imm8 testl rrd 18983 ret cc slab rbd,imm8 trdb @rd,@rs,rba 18984 rl rd,imm1or2 slal rrd,imm8 trdrb @rd,@rs,rba 18985 rlb rbd,imm1or2 sll rd,imm8 trib @rd,@rs,rbr 18986 rlc rd,imm1or2 sllb rbd,imm8 trirb @rd,@rs,rbr 18987 rlcb rbd,imm1or2 slll rrd,imm8 trtdrb @ra,@rb,rbr 18988 rldb rbb,rba sout imm16,rs trtib @ra,@rb,rr 18989 rr rd,imm1or2 soutb imm16,rbs trtirb @ra,@rb,rbr 18990 rrb rbd,imm1or2 soutd @rd,@rs,ra trtrb @ra,@rb,rbr 18991 rrc rd,imm1or2 soutdb @rd,@rs,rba tset @rd 18992 rrcb rbd,imm1or2 soutib @rd,@rs,ra tset addr 18993 rrdb rbb,rba soutibr @rd,@rs,ra tset addr(rd) 18994 rsvd36 sra rd,imm8 tset rd 18995 rsvd38 srab rbd,imm8 tsetb @rd 18996 rsvd78 sral rrd,imm8 tsetb addr 18997 rsvd7e srl rd,imm8 tsetb addr(rd) 18998 rsvd9d srlb rbd,imm8 tsetb rbd 18999 rsvd9f srll rrd,imm8 xor rd,@rs 19000 rsvdb9 sub rd,@rs xor rd,addr 19001 rsvdbf sub rd,addr xor rd,addr(rs) 19002 sbc rd,rs sub rd,addr(rs) xor rd,imm16 19003 sbcb rbd,rbs sub rd,imm16 xor rd,rs 19004 sc imm8 sub rd,rs xorb rbd,@rs 19005 sda rd,rs subb rbd,@rs xorb rbd,addr 19006 sdab rbd,rs subb rbd,addr xorb rbd,addr(rs) 19007 sdal rrd,rs subb rbd,addr(rs) xorb rbd,imm8 19008 sdl rd,rs subb rbd,imm8 xorb rbd,rbs 19009 sdlb rbd,rs subb rbd,rbs xorb rbd,rbs 19010 sdll rrd,rs subl rrd,@rs 19011 set @rd,imm4 subl rrd,addr 19012 set addr(rd),imm4 subl rrd,addr(rs) 19013 19014 19015File: as.info, Node: Vax-Dependent, Prev: Z8000-Dependent, Up: Machine Dependencies 19016 190179.43 VAX Dependent Features 19018=========================== 19019 19020* Menu: 19021 19022* VAX-Opts:: VAX Command-Line Options 19023* VAX-float:: VAX Floating Point 19024* VAX-directives:: Vax Machine Directives 19025* VAX-opcodes:: VAX Opcodes 19026* VAX-branch:: VAX Branch Improvement 19027* VAX-operands:: VAX Operands 19028* VAX-no:: Not Supported on VAX 19029* VAX-Syntax:: VAX Syntax 19030 19031 19032File: as.info, Node: VAX-Opts, Next: VAX-float, Up: Vax-Dependent 19033 190349.43.1 VAX Command-Line Options 19035------------------------------- 19036 19037The Vax version of `as' accepts any of the following options, gives a 19038warning message that the option was ignored and proceeds. These 19039options are for compatibility with scripts designed for other people's 19040assemblers. 19041 19042``-D' (Debug)' 19043``-S' (Symbol Table)' 19044``-T' (Token Trace)' 19045 These are obsolete options used to debug old assemblers. 19046 19047``-d' (Displacement size for JUMPs)' 19048 This option expects a number following the `-d'. Like options 19049 that expect filenames, the number may immediately follow the `-d' 19050 (old standard) or constitute the whole of the command line 19051 argument that follows `-d' (GNU standard). 19052 19053``-V' (Virtualize Interpass Temporary File)' 19054 Some other assemblers use a temporary file. This option commanded 19055 them to keep the information in active memory rather than in a 19056 disk file. `as' always does this, so this option is redundant. 19057 19058``-J' (JUMPify Longer Branches)' 19059 Many 32-bit computers permit a variety of branch instructions to 19060 do the same job. Some of these instructions are short (and fast) 19061 but have a limited range; others are long (and slow) but can 19062 branch anywhere in virtual memory. Often there are 3 flavors of 19063 branch: short, medium and long. Some other assemblers would emit 19064 short and medium branches, unless told by this option to emit 19065 short and long branches. 19066 19067``-t' (Temporary File Directory)' 19068 Some other assemblers may use a temporary file, and this option 19069 takes a filename being the directory to site the temporary file. 19070 Since `as' does not use a temporary disk file, this option makes 19071 no difference. `-t' needs exactly one filename. 19072 19073 The Vax version of the assembler accepts additional options when 19074compiled for VMS: 19075 19076`-h N' 19077 External symbol or section (used for global variables) names are 19078 not case sensitive on VAX/VMS and always mapped to upper case. 19079 This is contrary to the C language definition which explicitly 19080 distinguishes upper and lower case. To implement a standard 19081 conforming C compiler, names must be changed (mapped) to preserve 19082 the case information. The default mapping is to convert all lower 19083 case characters to uppercase and adding an underscore followed by 19084 a 6 digit hex value, representing a 24 digit binary value. The 19085 one digits in the binary value represent which characters are 19086 uppercase in the original symbol name. 19087 19088 The `-h N' option determines how we map names. This takes several 19089 values. No `-h' switch at all allows case hacking as described 19090 above. A value of zero (`-h0') implies names should be upper 19091 case, and inhibits the case hack. A value of 2 (`-h2') implies 19092 names should be all lower case, with no case hack. A value of 3 19093 (`-h3') implies that case should be preserved. The value 1 is 19094 unused. The `-H' option directs `as' to display every mapped 19095 symbol during assembly. 19096 19097 Symbols whose names include a dollar sign `$' are exceptions to the 19098 general name mapping. These symbols are normally only used to 19099 reference VMS library names. Such symbols are always mapped to 19100 upper case. 19101 19102`-+' 19103 The `-+' option causes `as' to truncate any symbol name larger 19104 than 31 characters. The `-+' option also prevents some code 19105 following the `_main' symbol normally added to make the object 19106 file compatible with Vax-11 "C". 19107 19108`-1' 19109 This option is ignored for backward compatibility with `as' 19110 version 1.x. 19111 19112`-H' 19113 The `-H' option causes `as' to print every symbol which was 19114 changed by case mapping. 19115 19116 19117File: as.info, Node: VAX-float, Next: VAX-directives, Prev: VAX-Opts, Up: Vax-Dependent 19118 191199.43.2 VAX Floating Point 19120------------------------- 19121 19122Conversion of flonums to floating point is correct, and compatible with 19123previous assemblers. Rounding is towards zero if the remainder is 19124exactly half the least significant bit. 19125 19126 `D', `F', `G' and `H' floating point formats are understood. 19127 19128 Immediate floating literals (_e.g._ `S`$6.9') are rendered 19129correctly. Again, rounding is towards zero in the boundary case. 19130 19131 The `.float' directive produces `f' format numbers. The `.double' 19132directive produces `d' format numbers. 19133 19134 19135File: as.info, Node: VAX-directives, Next: VAX-opcodes, Prev: VAX-float, Up: Vax-Dependent 19136 191379.43.3 Vax Machine Directives 19138----------------------------- 19139 19140The Vax version of the assembler supports four directives for 19141generating Vax floating point constants. They are described in the 19142table below. 19143 19144`.dfloat' 19145 This expects zero or more flonums, separated by commas, and 19146 assembles Vax `d' format 64-bit floating point constants. 19147 19148`.ffloat' 19149 This expects zero or more flonums, separated by commas, and 19150 assembles Vax `f' format 32-bit floating point constants. 19151 19152`.gfloat' 19153 This expects zero or more flonums, separated by commas, and 19154 assembles Vax `g' format 64-bit floating point constants. 19155 19156`.hfloat' 19157 This expects zero or more flonums, separated by commas, and 19158 assembles Vax `h' format 128-bit floating point constants. 19159 19160 19161 19162File: as.info, Node: VAX-opcodes, Next: VAX-branch, Prev: VAX-directives, Up: Vax-Dependent 19163 191649.43.4 VAX Opcodes 19165------------------ 19166 19167All DEC mnemonics are supported. Beware that `case...' instructions 19168have exactly 3 operands. The dispatch table that follows the `case...' 19169instruction should be made with `.word' statements. This is compatible 19170with all unix assemblers we know of. 19171 19172 19173File: as.info, Node: VAX-branch, Next: VAX-operands, Prev: VAX-opcodes, Up: Vax-Dependent 19174 191759.43.5 VAX Branch Improvement 19176----------------------------- 19177 19178Certain pseudo opcodes are permitted. They are for branch 19179instructions. They expand to the shortest branch instruction that 19180reaches the target. Generally these mnemonics are made by substituting 19181`j' for `b' at the start of a DEC mnemonic. This feature is included 19182both for compatibility and to help compilers. If you do not need this 19183feature, avoid these opcodes. Here are the mnemonics, and the code 19184they can expand into. 19185 19186`jbsb' 19187 `Jsb' is already an instruction mnemonic, so we chose `jbsb'. 19188 (byte displacement) 19189 `bsbb ...' 19190 19191 (word displacement) 19192 `bsbw ...' 19193 19194 (long displacement) 19195 `jsb ...' 19196 19197`jbr' 19198`jr' 19199 Unconditional branch. 19200 (byte displacement) 19201 `brb ...' 19202 19203 (word displacement) 19204 `brw ...' 19205 19206 (long displacement) 19207 `jmp ...' 19208 19209`jCOND' 19210 COND may be any one of the conditional branches `neq', `nequ', 19211 `eql', `eqlu', `gtr', `geq', `lss', `gtru', `lequ', `vc', `vs', 19212 `gequ', `cc', `lssu', `cs'. COND may also be one of the bit tests 19213 `bs', `bc', `bss', `bcs', `bsc', `bcc', `bssi', `bcci', `lbs', 19214 `lbc'. NOTCOND is the opposite condition to COND. 19215 (byte displacement) 19216 `bCOND ...' 19217 19218 (word displacement) 19219 `bNOTCOND foo ; brw ... ; foo:' 19220 19221 (long displacement) 19222 `bNOTCOND foo ; jmp ... ; foo:' 19223 19224`jacbX' 19225 X may be one of `b d f g h l w'. 19226 (word displacement) 19227 `OPCODE ...' 19228 19229 (long displacement) 19230 OPCODE ..., foo ; 19231 brb bar ; 19232 foo: jmp ... ; 19233 bar: 19234 19235`jaobYYY' 19236 YYY may be one of `lss leq'. 19237 19238`jsobZZZ' 19239 ZZZ may be one of `geq gtr'. 19240 (byte displacement) 19241 `OPCODE ...' 19242 19243 (word displacement) 19244 OPCODE ..., foo ; 19245 brb bar ; 19246 foo: brw DESTINATION ; 19247 bar: 19248 19249 (long displacement) 19250 OPCODE ..., foo ; 19251 brb bar ; 19252 foo: jmp DESTINATION ; 19253 bar: 19254 19255`aobleq' 19256`aoblss' 19257`sobgeq' 19258`sobgtr' 19259 19260 (byte displacement) 19261 `OPCODE ...' 19262 19263 (word displacement) 19264 OPCODE ..., foo ; 19265 brb bar ; 19266 foo: brw DESTINATION ; 19267 bar: 19268 19269 (long displacement) 19270 OPCODE ..., foo ; 19271 brb bar ; 19272 foo: jmp DESTINATION ; 19273 bar: 19274 19275 19276File: as.info, Node: VAX-operands, Next: VAX-no, Prev: VAX-branch, Up: Vax-Dependent 19277 192789.43.6 VAX Operands 19279------------------- 19280 19281The immediate character is `$' for Unix compatibility, not `#' as DEC 19282writes it. 19283 19284 The indirect character is `*' for Unix compatibility, not `@' as DEC 19285writes it. 19286 19287 The displacement sizing character is ``' (an accent grave) for Unix 19288compatibility, not `^' as DEC writes it. The letter preceding ``' may 19289have either case. `G' is not understood, but all other letters (`b i l 19290s w') are understood. 19291 19292 Register names understood are `r0 r1 r2 ... r15 ap fp sp pc'. Upper 19293and lower case letters are equivalent. 19294 19295 For instance 19296 tstb *w`$4(r5) 19297 19298 Any expression is permitted in an operand. Operands are comma 19299separated. 19300 19301 19302File: as.info, Node: VAX-no, Next: VAX-Syntax, Prev: VAX-operands, Up: Vax-Dependent 19303 193049.43.7 Not Supported on VAX 19305--------------------------- 19306 19307Vax bit fields can not be assembled with `as'. Someone can add the 19308required code if they really need it. 19309 19310 19311File: as.info, Node: VAX-Syntax, Prev: VAX-no, Up: Vax-Dependent 19312 193139.43.8 VAX Syntax 19314----------------- 19315 19316* Menu: 19317 19318* VAX-Chars:: Special Characters 19319 19320 19321File: as.info, Node: VAX-Chars, Up: VAX-Syntax 19322 193239.43.8.1 Special Characters 19324........................... 19325 19326The presence of a `#' appearing anywhere on a line indicates the start 19327of a comment that extends to the end of that line. 19328 19329 If a `#' appears as the first character of a line then the whole 19330line is treated as a comment, but in this case the line can also be a 19331logical line number directive (*note Comments::) or a preprocessor 19332control command (*note Preprocessing::). 19333 19334 The `;' character can be used to separate statements on the same 19335line. 19336 19337 19338File: as.info, Node: V850-Dependent, Next: XSTORMY16-Dependent, Prev: TILEPro-Dependent, Up: Machine Dependencies 19339 193409.44 v850 Dependent Features 19341============================ 19342 19343* Menu: 19344 19345* V850 Options:: Options 19346* V850 Syntax:: Syntax 19347* V850 Floating Point:: Floating Point 19348* V850 Directives:: V850 Machine Directives 19349* V850 Opcodes:: Opcodes 19350 19351 19352File: as.info, Node: V850 Options, Next: V850 Syntax, Up: V850-Dependent 19353 193549.44.1 Options 19355-------------- 19356 19357`as' supports the following additional command-line options for the 19358V850 processor family: 19359 19360`-wsigned_overflow' 19361 Causes warnings to be produced when signed immediate values 19362 overflow the space available for then within their opcodes. By 19363 default this option is disabled as it is possible to receive 19364 spurious warnings due to using exact bit patterns as immediate 19365 constants. 19366 19367`-wunsigned_overflow' 19368 Causes warnings to be produced when unsigned immediate values 19369 overflow the space available for then within their opcodes. By 19370 default this option is disabled as it is possible to receive 19371 spurious warnings due to using exact bit patterns as immediate 19372 constants. 19373 19374`-mv850' 19375 Specifies that the assembled code should be marked as being 19376 targeted at the V850 processor. This allows the linker to detect 19377 attempts to link such code with code assembled for other 19378 processors. 19379 19380`-mv850e' 19381 Specifies that the assembled code should be marked as being 19382 targeted at the V850E processor. This allows the linker to detect 19383 attempts to link such code with code assembled for other 19384 processors. 19385 19386`-mv850e1' 19387 Specifies that the assembled code should be marked as being 19388 targeted at the V850E1 processor. This allows the linker to 19389 detect attempts to link such code with code assembled for other 19390 processors. 19391 19392`-mv850any' 19393 Specifies that the assembled code should be marked as being 19394 targeted at the V850 processor but support instructions that are 19395 specific to the extended variants of the process. This allows the 19396 production of binaries that contain target specific code, but 19397 which are also intended to be used in a generic fashion. For 19398 example libgcc.a contains generic routines used by the code 19399 produced by GCC for all versions of the v850 architecture, 19400 together with support routines only used by the V850E architecture. 19401 19402`-mv850e2' 19403 Specifies that the assembled code should be marked as being 19404 targeted at the V850E2 processor. This allows the linker to 19405 detect attempts to link such code with code assembled for other 19406 processors. 19407 19408`-mv850e2v3' 19409 Specifies that the assembled code should be marked as being 19410 targeted at the V850E2V3 processor. This allows the linker to 19411 detect attempts to link such code with code assembled for other 19412 processors. 19413 19414`-mrelax' 19415 Enables relaxation. This allows the .longcall and .longjump pseudo 19416 ops to be used in the assembler source code. These ops label 19417 sections of code which are either a long function call or a long 19418 branch. The assembler will then flag these sections of code and 19419 the linker will attempt to relax them. 19420 19421 19422 19423File: as.info, Node: V850 Syntax, Next: V850 Floating Point, Prev: V850 Options, Up: V850-Dependent 19424 194259.44.2 Syntax 19426------------- 19427 19428* Menu: 19429 19430* V850-Chars:: Special Characters 19431* V850-Regs:: Register Names 19432 19433 19434File: as.info, Node: V850-Chars, Next: V850-Regs, Up: V850 Syntax 19435 194369.44.2.1 Special Characters 19437........................... 19438 19439`#' is the line comment character. If a `#' appears as the first 19440character of a line, the whole line is treated as a comment, but in 19441this case the line can also be a logical line number directive (*note 19442Comments::) or a preprocessor control command (*note Preprocessing::). 19443 19444 Two dashes (`--') can also be used to start a line comment. 19445 19446 The `;' character can be used to separate statements on the same 19447line. 19448 19449 19450File: as.info, Node: V850-Regs, Prev: V850-Chars, Up: V850 Syntax 19451 194529.44.2.2 Register Names 19453....................... 19454 19455`as' supports the following names for registers: 19456`general register 0' 19457 r0, zero 19458 19459`general register 1' 19460 r1 19461 19462`general register 2' 19463 r2, hp 19464 19465`general register 3' 19466 r3, sp 19467 19468`general register 4' 19469 r4, gp 19470 19471`general register 5' 19472 r5, tp 19473 19474`general register 6' 19475 r6 19476 19477`general register 7' 19478 r7 19479 19480`general register 8' 19481 r8 19482 19483`general register 9' 19484 r9 19485 19486`general register 10' 19487 r10 19488 19489`general register 11' 19490 r11 19491 19492`general register 12' 19493 r12 19494 19495`general register 13' 19496 r13 19497 19498`general register 14' 19499 r14 19500 19501`general register 15' 19502 r15 19503 19504`general register 16' 19505 r16 19506 19507`general register 17' 19508 r17 19509 19510`general register 18' 19511 r18 19512 19513`general register 19' 19514 r19 19515 19516`general register 20' 19517 r20 19518 19519`general register 21' 19520 r21 19521 19522`general register 22' 19523 r22 19524 19525`general register 23' 19526 r23 19527 19528`general register 24' 19529 r24 19530 19531`general register 25' 19532 r25 19533 19534`general register 26' 19535 r26 19536 19537`general register 27' 19538 r27 19539 19540`general register 28' 19541 r28 19542 19543`general register 29' 19544 r29 19545 19546`general register 30' 19547 r30, ep 19548 19549`general register 31' 19550 r31, lp 19551 19552`system register 0' 19553 eipc 19554 19555`system register 1' 19556 eipsw 19557 19558`system register 2' 19559 fepc 19560 19561`system register 3' 19562 fepsw 19563 19564`system register 4' 19565 ecr 19566 19567`system register 5' 19568 psw 19569 19570`system register 16' 19571 ctpc 19572 19573`system register 17' 19574 ctpsw 19575 19576`system register 18' 19577 dbpc 19578 19579`system register 19' 19580 dbpsw 19581 19582`system register 20' 19583 ctbp 19584 19585 19586File: as.info, Node: V850 Floating Point, Next: V850 Directives, Prev: V850 Syntax, Up: V850-Dependent 19587 195889.44.3 Floating Point 19589--------------------- 19590 19591The V850 family uses IEEE floating-point numbers. 19592 19593 19594File: as.info, Node: V850 Directives, Next: V850 Opcodes, Prev: V850 Floating Point, Up: V850-Dependent 19595 195969.44.4 V850 Machine Directives 19597------------------------------ 19598 19599`.offset <EXPRESSION>' 19600 Moves the offset into the current section to the specified amount. 19601 19602`.section "name", <type>' 19603 This is an extension to the standard .section directive. It sets 19604 the current section to be <type> and creates an alias for this 19605 section called "name". 19606 19607`.v850' 19608 Specifies that the assembled code should be marked as being 19609 targeted at the V850 processor. This allows the linker to detect 19610 attempts to link such code with code assembled for other 19611 processors. 19612 19613`.v850e' 19614 Specifies that the assembled code should be marked as being 19615 targeted at the V850E processor. This allows the linker to detect 19616 attempts to link such code with code assembled for other 19617 processors. 19618 19619`.v850e1' 19620 Specifies that the assembled code should be marked as being 19621 targeted at the V850E1 processor. This allows the linker to 19622 detect attempts to link such code with code assembled for other 19623 processors. 19624 19625`.v850e2' 19626 Specifies that the assembled code should be marked as being 19627 targeted at the V850E2 processor. This allows the linker to 19628 detect attempts to link such code with code assembled for other 19629 processors. 19630 19631`.v850e2v3' 19632 Specifies that the assembled code should be marked as being 19633 targeted at the V850E2V3 processor. This allows the linker to 19634 detect attempts to link such code with code assembled for other 19635 processors. 19636 19637 19638 19639File: as.info, Node: V850 Opcodes, Prev: V850 Directives, Up: V850-Dependent 19640 196419.44.5 Opcodes 19642-------------- 19643 19644`as' implements all the standard V850 opcodes. 19645 19646 `as' also implements the following pseudo ops: 19647 19648`hi0()' 19649 Computes the higher 16 bits of the given expression and stores it 19650 into the immediate operand field of the given instruction. For 19651 example: 19652 19653 `mulhi hi0(here - there), r5, r6' 19654 19655 computes the difference between the address of labels 'here' and 19656 'there', takes the upper 16 bits of this difference, shifts it 19657 down 16 bits and then multiplies it by the lower 16 bits in 19658 register 5, putting the result into register 6. 19659 19660`lo()' 19661 Computes the lower 16 bits of the given expression and stores it 19662 into the immediate operand field of the given instruction. For 19663 example: 19664 19665 `addi lo(here - there), r5, r6' 19666 19667 computes the difference between the address of labels 'here' and 19668 'there', takes the lower 16 bits of this difference and adds it to 19669 register 5, putting the result into register 6. 19670 19671`hi()' 19672 Computes the higher 16 bits of the given expression and then adds 19673 the value of the most significant bit of the lower 16 bits of the 19674 expression and stores the result into the immediate operand field 19675 of the given instruction. For example the following code can be 19676 used to compute the address of the label 'here' and store it into 19677 register 6: 19678 19679 `movhi hi(here), r0, r6' `movea lo(here), r6, r6' 19680 19681 The reason for this special behaviour is that movea performs a sign 19682 extension on its immediate operand. So for example if the address 19683 of 'here' was 0xFFFFFFFF then without the special behaviour of the 19684 hi() pseudo-op the movhi instruction would put 0xFFFF0000 into r6, 19685 then the movea instruction would takes its immediate operand, 19686 0xFFFF, sign extend it to 32 bits, 0xFFFFFFFF, and then add it 19687 into r6 giving 0xFFFEFFFF which is wrong (the fifth nibble is E). 19688 With the hi() pseudo op adding in the top bit of the lo() pseudo 19689 op, the movhi instruction actually stores 0 into r6 (0xFFFF + 1 = 19690 0x0000), so that the movea instruction stores 0xFFFFFFFF into r6 - 19691 the right value. 19692 19693`hilo()' 19694 Computes the 32 bit value of the given expression and stores it 19695 into the immediate operand field of the given instruction (which 19696 must be a mov instruction). For example: 19697 19698 `mov hilo(here), r6' 19699 19700 computes the absolute address of label 'here' and puts the result 19701 into register 6. 19702 19703`sdaoff()' 19704 Computes the offset of the named variable from the start of the 19705 Small Data Area (whoes address is held in register 4, the GP 19706 register) and stores the result as a 16 bit signed value in the 19707 immediate operand field of the given instruction. For example: 19708 19709 `ld.w sdaoff(_a_variable)[gp],r6' 19710 19711 loads the contents of the location pointed to by the label 19712 '_a_variable' into register 6, provided that the label is located 19713 somewhere within +/- 32K of the address held in the GP register. 19714 [Note the linker assumes that the GP register contains a fixed 19715 address set to the address of the label called '__gp'. This can 19716 either be set up automatically by the linker, or specifically set 19717 by using the `--defsym __gp=<value>' command line option]. 19718 19719`tdaoff()' 19720 Computes the offset of the named variable from the start of the 19721 Tiny Data Area (whoes address is held in register 30, the EP 19722 register) and stores the result as a 4,5, 7 or 8 bit unsigned 19723 value in the immediate operand field of the given instruction. 19724 For example: 19725 19726 `sld.w tdaoff(_a_variable)[ep],r6' 19727 19728 loads the contents of the location pointed to by the label 19729 '_a_variable' into register 6, provided that the label is located 19730 somewhere within +256 bytes of the address held in the EP 19731 register. [Note the linker assumes that the EP register contains 19732 a fixed address set to the address of the label called '__ep'. 19733 This can either be set up automatically by the linker, or 19734 specifically set by using the `--defsym __ep=<value>' command line 19735 option]. 19736 19737`zdaoff()' 19738 Computes the offset of the named variable from address 0 and 19739 stores the result as a 16 bit signed value in the immediate 19740 operand field of the given instruction. For example: 19741 19742 `movea zdaoff(_a_variable),zero,r6' 19743 19744 puts the address of the label '_a_variable' into register 6, 19745 assuming that the label is somewhere within the first 32K of 19746 memory. (Strictly speaking it also possible to access the last 19747 32K of memory as well, as the offsets are signed). 19748 19749`ctoff()' 19750 Computes the offset of the named variable from the start of the 19751 Call Table Area (whoes address is helg in system register 20, the 19752 CTBP register) and stores the result a 6 or 16 bit unsigned value 19753 in the immediate field of then given instruction or piece of data. 19754 For example: 19755 19756 `callt ctoff(table_func1)' 19757 19758 will put the call the function whoes address is held in the call 19759 table at the location labeled 'table_func1'. 19760 19761`.longcall `name'' 19762 Indicates that the following sequence of instructions is a long 19763 call to function `name'. The linker will attempt to shorten this 19764 call sequence if `name' is within a 22bit offset of the call. Only 19765 valid if the `-mrelax' command line switch has been enabled. 19766 19767`.longjump `name'' 19768 Indicates that the following sequence of instructions is a long 19769 jump to label `name'. The linker will attempt to shorten this code 19770 sequence if `name' is within a 22bit offset of the jump. Only 19771 valid if the `-mrelax' command line switch has been enabled. 19772 19773 19774 For information on the V850 instruction set, see `V850 Family 1977532-/16-Bit single-Chip Microcontroller Architecture Manual' from NEC. 19776Ltd. 19777 19778 19779File: as.info, Node: XSTORMY16-Dependent, Next: Xtensa-Dependent, Prev: V850-Dependent, Up: Machine Dependencies 19780 197819.45 XStormy16 Dependent Features 19782================================= 19783 19784* Menu: 19785 19786* XStormy16 Syntax:: Syntax 19787* XStormy16 Directives:: Machine Directives 19788* XStormy16 Opcodes:: Pseudo-Opcodes 19789 19790 19791File: as.info, Node: XStormy16 Syntax, Next: XStormy16 Directives, Up: XSTORMY16-Dependent 19792 197939.45.1 Syntax 19794------------- 19795 19796* Menu: 19797 19798* XStormy16-Chars:: Special Characters 19799 19800 19801File: as.info, Node: XStormy16-Chars, Up: XStormy16 Syntax 19802 198039.45.1.1 Special Characters 19804........................... 19805 19806`#' is the line comment character. If a `#' appears as the first 19807character of a line, the whole line is treated as a comment, but in 19808this case the line can also be a logical line number directive (*note 19809Comments::) or a preprocessor control command (*note Preprocessing::). 19810 19811 A semicolon (`;') can be used to start a comment that extends from 19812wherever the character appears on the line up to the end of the line. 19813 19814 The `|' character can be used to separate statements on the same 19815line. 19816 19817 19818File: as.info, Node: XStormy16 Directives, Next: XStormy16 Opcodes, Prev: XStormy16 Syntax, Up: XSTORMY16-Dependent 19819 198209.45.2 XStormy16 Machine Directives 19821----------------------------------- 19822 19823`.16bit_pointers' 19824 Like the `--16bit-pointers' command line option this directive 19825 indicates that the assembly code makes use of 16-bit pointers. 19826 19827`.32bit_pointers' 19828 Like the `--32bit-pointers' command line option this directive 19829 indicates that the assembly code makes use of 32-bit pointers. 19830 19831`.no_pointers' 19832 Like the `--no-pointers' command line option this directive 19833 indicates that the assembly code does not makes use pointers. 19834 19835 19836 19837File: as.info, Node: XStormy16 Opcodes, Prev: XStormy16 Directives, Up: XSTORMY16-Dependent 19838 198399.45.3 XStormy16 Pseudo-Opcodes 19840------------------------------- 19841 19842`as' implements all the standard XStormy16 opcodes. 19843 19844 `as' also implements the following pseudo ops: 19845 19846`@lo()' 19847 Computes the lower 16 bits of the given expression and stores it 19848 into the immediate operand field of the given instruction. For 19849 example: 19850 19851 `add r6, @lo(here - there)' 19852 19853 computes the difference between the address of labels 'here' and 19854 'there', takes the lower 16 bits of this difference and adds it to 19855 register 6. 19856 19857`@hi()' 19858 Computes the higher 16 bits of the given expression and stores it 19859 into the immediate operand field of the given instruction. For 19860 example: 19861 19862 `addc r7, @hi(here - there)' 19863 19864 computes the difference between the address of labels 'here' and 19865 'there', takes the upper 16 bits of this difference, shifts it 19866 down 16 bits and then adds it, along with the carry bit, to the 19867 value in register 7. 19868 19869 19870 19871File: as.info, Node: Xtensa-Dependent, Next: Z80-Dependent, Prev: XSTORMY16-Dependent, Up: Machine Dependencies 19872 198739.46 Xtensa Dependent Features 19874============================== 19875 19876 This chapter covers features of the GNU assembler that are specific 19877to the Xtensa architecture. For details about the Xtensa instruction 19878set, please consult the `Xtensa Instruction Set Architecture (ISA) 19879Reference Manual'. 19880 19881* Menu: 19882 19883* Xtensa Options:: Command-line Options. 19884* Xtensa Syntax:: Assembler Syntax for Xtensa Processors. 19885* Xtensa Optimizations:: Assembler Optimizations. 19886* Xtensa Relaxation:: Other Automatic Transformations. 19887* Xtensa Directives:: Directives for Xtensa Processors. 19888 19889 19890File: as.info, Node: Xtensa Options, Next: Xtensa Syntax, Up: Xtensa-Dependent 19891 198929.46.1 Command Line Options 19893--------------------------- 19894 19895`--text-section-literals | --no-text-section-literals' 19896 Control the treatment of literal pools. The default is 19897 `--no-text-section-literals', which places literals in separate 19898 sections in the output file. This allows the literal pool to be 19899 placed in a data RAM/ROM. With `--text-section-literals', the 19900 literals are interspersed in the text section in order to keep 19901 them as close as possible to their references. This may be 19902 necessary for large assembly files, where the literals would 19903 otherwise be out of range of the `L32R' instructions in the text 19904 section. These options only affect literals referenced via 19905 PC-relative `L32R' instructions; literals for absolute mode `L32R' 19906 instructions are handled separately. *Note literal: Literal 19907 Directive. 19908 19909`--absolute-literals | --no-absolute-literals' 19910 Indicate to the assembler whether `L32R' instructions use absolute 19911 or PC-relative addressing. If the processor includes the absolute 19912 addressing option, the default is to use absolute `L32R' 19913 relocations. Otherwise, only the PC-relative `L32R' relocations 19914 can be used. 19915 19916`--target-align | --no-target-align' 19917 Enable or disable automatic alignment to reduce branch penalties 19918 at some expense in code size. *Note Automatic Instruction 19919 Alignment: Xtensa Automatic Alignment. This optimization is 19920 enabled by default. Note that the assembler will always align 19921 instructions like `LOOP' that have fixed alignment requirements. 19922 19923`--longcalls | --no-longcalls' 19924 Enable or disable transformation of call instructions to allow 19925 calls across a greater range of addresses. *Note Function Call 19926 Relaxation: Xtensa Call Relaxation. This option should be used 19927 when call targets can potentially be out of range. It may degrade 19928 both code size and performance, but the linker can generally 19929 optimize away the unnecessary overhead when a call ends up within 19930 range. The default is `--no-longcalls'. 19931 19932`--transform | --no-transform' 19933 Enable or disable all assembler transformations of Xtensa 19934 instructions, including both relaxation and optimization. The 19935 default is `--transform'; `--no-transform' should only be used in 19936 the rare cases when the instructions must be exactly as specified 19937 in the assembly source. Using `--no-transform' causes out of range 19938 instruction operands to be errors. 19939 19940`--rename-section OLDNAME=NEWNAME' 19941 Rename the OLDNAME section to NEWNAME. This option can be used 19942 multiple times to rename multiple sections. 19943 19944 19945File: as.info, Node: Xtensa Syntax, Next: Xtensa Optimizations, Prev: Xtensa Options, Up: Xtensa-Dependent 19946 199479.46.2 Assembler Syntax 19948----------------------- 19949 19950Block comments are delimited by `/*' and `*/'. End of line comments 19951may be introduced with either `#' or `//'. 19952 19953 If a `#' appears as the first character of a line then the whole 19954line is treated as a comment, but in this case the line could also be a 19955logical line number directive (*note Comments::) or a preprocessor 19956control command (*note Preprocessing::). 19957 19958 Instructions consist of a leading opcode or macro name followed by 19959whitespace and an optional comma-separated list of operands: 19960 19961 OPCODE [OPERAND, ...] 19962 19963 Instructions must be separated by a newline or semicolon (`;'). 19964 19965 FLIX instructions, which bundle multiple opcodes together in a single 19966instruction, are specified by enclosing the bundled opcodes inside 19967braces: 19968 19969 { 19970 [FORMAT] 19971 OPCODE0 [OPERANDS] 19972 OPCODE1 [OPERANDS] 19973 OPCODE2 [OPERANDS] 19974 ... 19975 } 19976 19977 The opcodes in a FLIX instruction are listed in the same order as the 19978corresponding instruction slots in the TIE format declaration. 19979Directives and labels are not allowed inside the braces of a FLIX 19980instruction. A particular TIE format name can optionally be specified 19981immediately after the opening brace, but this is usually unnecessary. 19982The assembler will automatically search for a format that can encode the 19983specified opcodes, so the format name need only be specified in rare 19984cases where there is more than one applicable format and where it 19985matters which of those formats is used. A FLIX instruction can also be 19986specified on a single line by separating the opcodes with semicolons: 19987 19988 { [FORMAT;] OPCODE0 [OPERANDS]; OPCODE1 [OPERANDS]; OPCODE2 [OPERANDS]; ... } 19989 19990 If an opcode can only be encoded in a FLIX instruction but is not 19991specified as part of a FLIX bundle, the assembler will choose the 19992smallest format where the opcode can be encoded and will fill unused 19993instruction slots with no-ops. 19994 19995* Menu: 19996 19997* Xtensa Opcodes:: Opcode Naming Conventions. 19998* Xtensa Registers:: Register Naming. 19999 20000 20001File: as.info, Node: Xtensa Opcodes, Next: Xtensa Registers, Up: Xtensa Syntax 20002 200039.46.2.1 Opcode Names 20004..................... 20005 20006See the `Xtensa Instruction Set Architecture (ISA) Reference Manual' 20007for a complete list of opcodes and descriptions of their semantics. 20008 20009 If an opcode name is prefixed with an underscore character (`_'), 20010`as' will not transform that instruction in any way. The underscore 20011prefix disables both optimization (*note Xtensa Optimizations: Xtensa 20012Optimizations.) and relaxation (*note Xtensa Relaxation: Xtensa 20013Relaxation.) for that particular instruction. Only use the underscore 20014prefix when it is essential to select the exact opcode produced by the 20015assembler. Using this feature unnecessarily makes the code less 20016efficient by disabling assembler optimization and less flexible by 20017disabling relaxation. 20018 20019 Note that this special handling of underscore prefixes only applies 20020to Xtensa opcodes, not to either built-in macros or user-defined macros. 20021When an underscore prefix is used with a macro (e.g., `_MOV'), it 20022refers to a different macro. The assembler generally provides built-in 20023macros both with and without the underscore prefix, where the underscore 20024versions behave as if the underscore carries through to the instructions 20025in the macros. For example, `_MOV' may expand to `_MOV.N'. 20026 20027 The underscore prefix only applies to individual instructions, not to 20028series of instructions. For example, if a series of instructions have 20029underscore prefixes, the assembler will not transform the individual 20030instructions, but it may insert other instructions between them (e.g., 20031to align a `LOOP' instruction). To prevent the assembler from 20032modifying a series of instructions as a whole, use the `no-transform' 20033directive. *Note transform: Transform Directive. 20034 20035 20036File: as.info, Node: Xtensa Registers, Prev: Xtensa Opcodes, Up: Xtensa Syntax 20037 200389.46.2.2 Register Names 20039....................... 20040 20041The assembly syntax for a register file entry is the "short" name for a 20042TIE register file followed by the index into that register file. For 20043example, the general-purpose `AR' register file has a short name of 20044`a', so these registers are named `a0'...`a15'. As a special feature, 20045`sp' is also supported as a synonym for `a1'. Additional registers may 20046be added by processor configuration options and by designer-defined TIE 20047extensions. An initial `$' character is optional in all register names. 20048 20049 20050File: as.info, Node: Xtensa Optimizations, Next: Xtensa Relaxation, Prev: Xtensa Syntax, Up: Xtensa-Dependent 20051 200529.46.3 Xtensa Optimizations 20053--------------------------- 20054 20055The optimizations currently supported by `as' are generation of density 20056instructions where appropriate and automatic branch target alignment. 20057 20058* Menu: 20059 20060* Density Instructions:: Using Density Instructions. 20061* Xtensa Automatic Alignment:: Automatic Instruction Alignment. 20062 20063 20064File: as.info, Node: Density Instructions, Next: Xtensa Automatic Alignment, Up: Xtensa Optimizations 20065 200669.46.3.1 Using Density Instructions 20067................................... 20068 20069The Xtensa instruction set has a code density option that provides 2007016-bit versions of some of the most commonly used opcodes. Use of these 20071opcodes can significantly reduce code size. When possible, the 20072assembler automatically translates instructions from the core Xtensa 20073instruction set into equivalent instructions from the Xtensa code 20074density option. This translation can be disabled by using underscore 20075prefixes (*note Opcode Names: Xtensa Opcodes.), by using the 20076`--no-transform' command-line option (*note Command Line Options: 20077Xtensa Options.), or by using the `no-transform' directive (*note 20078transform: Transform Directive.). 20079 20080 It is a good idea _not_ to use the density instructions directly. 20081The assembler will automatically select dense instructions where 20082possible. If you later need to use an Xtensa processor without the code 20083density option, the same assembly code will then work without 20084modification. 20085 20086 20087File: as.info, Node: Xtensa Automatic Alignment, Prev: Density Instructions, Up: Xtensa Optimizations 20088 200899.46.3.2 Automatic Instruction Alignment 20090........................................ 20091 20092The Xtensa assembler will automatically align certain instructions, both 20093to optimize performance and to satisfy architectural requirements. 20094 20095 As an optimization to improve performance, the assembler attempts to 20096align branch targets so they do not cross instruction fetch boundaries. 20097(Xtensa processors can be configured with either 32-bit or 64-bit 20098instruction fetch widths.) An instruction immediately following a call 20099is treated as a branch target in this context, because it will be the 20100target of a return from the call. This alignment has the potential to 20101reduce branch penalties at some expense in code size. This 20102optimization is enabled by default. You can disable it with the 20103`--no-target-align' command-line option (*note Command Line Options: 20104Xtensa Options.). 20105 20106 The target alignment optimization is done without adding instructions 20107that could increase the execution time of the program. If there are 20108density instructions in the code preceding a target, the assembler can 20109change the target alignment by widening some of those instructions to 20110the equivalent 24-bit instructions. Extra bytes of padding can be 20111inserted immediately following unconditional jump and return 20112instructions. This approach is usually successful in aligning many, 20113but not all, branch targets. 20114 20115 The `LOOP' family of instructions must be aligned such that the 20116first instruction in the loop body does not cross an instruction fetch 20117boundary (e.g., with a 32-bit fetch width, a `LOOP' instruction must be 20118on either a 1 or 2 mod 4 byte boundary). The assembler knows about 20119this restriction and inserts the minimal number of 2 or 3 byte no-op 20120instructions to satisfy it. When no-op instructions are added, any 20121label immediately preceding the original loop will be moved in order to 20122refer to the loop instruction, not the newly generated no-op 20123instruction. To preserve binary compatibility across processors with 20124different fetch widths, the assembler conservatively assumes a 32-bit 20125fetch width when aligning `LOOP' instructions (except if the first 20126instruction in the loop is a 64-bit instruction). 20127 20128 Previous versions of the assembler automatically aligned `ENTRY' 20129instructions to 4-byte boundaries, but that alignment is now the 20130programmer's responsibility. 20131 20132 20133File: as.info, Node: Xtensa Relaxation, Next: Xtensa Directives, Prev: Xtensa Optimizations, Up: Xtensa-Dependent 20134 201359.46.4 Xtensa Relaxation 20136------------------------ 20137 20138When an instruction operand is outside the range allowed for that 20139particular instruction field, `as' can transform the code to use a 20140functionally-equivalent instruction or sequence of instructions. This 20141process is known as "relaxation". This is typically done for branch 20142instructions because the distance of the branch targets is not known 20143until assembly-time. The Xtensa assembler offers branch relaxation and 20144also extends this concept to function calls, `MOVI' instructions and 20145other instructions with immediate fields. 20146 20147* Menu: 20148 20149* Xtensa Branch Relaxation:: Relaxation of Branches. 20150* Xtensa Call Relaxation:: Relaxation of Function Calls. 20151* Xtensa Immediate Relaxation:: Relaxation of other Immediate Fields. 20152 20153 20154File: as.info, Node: Xtensa Branch Relaxation, Next: Xtensa Call Relaxation, Up: Xtensa Relaxation 20155 201569.46.4.1 Conditional Branch Relaxation 20157...................................... 20158 20159When the target of a branch is too far away from the branch itself, 20160i.e., when the offset from the branch to the target is too large to fit 20161in the immediate field of the branch instruction, it may be necessary to 20162replace the branch with a branch around a jump. For example, 20163 20164 beqz a2, L 20165 20166 may result in: 20167 20168 bnez.n a2, M 20169 j L 20170 M: 20171 20172 (The `BNEZ.N' instruction would be used in this example only if the 20173density option is available. Otherwise, `BNEZ' would be used.) 20174 20175 This relaxation works well because the unconditional jump instruction 20176has a much larger offset range than the various conditional branches. 20177However, an error will occur if a branch target is beyond the range of a 20178jump instruction. `as' cannot relax unconditional jumps. Similarly, 20179an error will occur if the original input contains an unconditional 20180jump to a target that is out of range. 20181 20182 Branch relaxation is enabled by default. It can be disabled by using 20183underscore prefixes (*note Opcode Names: Xtensa Opcodes.), the 20184`--no-transform' command-line option (*note Command Line Options: 20185Xtensa Options.), or the `no-transform' directive (*note transform: 20186Transform Directive.). 20187 20188 20189File: as.info, Node: Xtensa Call Relaxation, Next: Xtensa Immediate Relaxation, Prev: Xtensa Branch Relaxation, Up: Xtensa Relaxation 20190 201919.46.4.2 Function Call Relaxation 20192................................. 20193 20194Function calls may require relaxation because the Xtensa immediate call 20195instructions (`CALL0', `CALL4', `CALL8' and `CALL12') provide a 20196PC-relative offset of only 512 Kbytes in either direction. For larger 20197programs, it may be necessary to use indirect calls (`CALLX0', 20198`CALLX4', `CALLX8' and `CALLX12') where the target address is specified 20199in a register. The Xtensa assembler can automatically relax immediate 20200call instructions into indirect call instructions. This relaxation is 20201done by loading the address of the called function into the callee's 20202return address register and then using a `CALLX' instruction. So, for 20203example: 20204 20205 call8 func 20206 20207 might be relaxed to: 20208 20209 .literal .L1, func 20210 l32r a8, .L1 20211 callx8 a8 20212 20213 Because the addresses of targets of function calls are not generally 20214known until link-time, the assembler must assume the worst and relax all 20215the calls to functions in other source files, not just those that really 20216will be out of range. The linker can recognize calls that were 20217unnecessarily relaxed, and it will remove the overhead introduced by the 20218assembler for those cases where direct calls are sufficient. 20219 20220 Call relaxation is disabled by default because it can have a negative 20221effect on both code size and performance, although the linker can 20222usually eliminate the unnecessary overhead. If a program is too large 20223and some of the calls are out of range, function call relaxation can be 20224enabled using the `--longcalls' command-line option or the `longcalls' 20225directive (*note longcalls: Longcalls Directive.). 20226 20227 20228File: as.info, Node: Xtensa Immediate Relaxation, Prev: Xtensa Call Relaxation, Up: Xtensa Relaxation 20229 202309.46.4.3 Other Immediate Field Relaxation 20231......................................... 20232 20233The assembler normally performs the following other relaxations. They 20234can be disabled by using underscore prefixes (*note Opcode Names: 20235Xtensa Opcodes.), the `--no-transform' command-line option (*note 20236Command Line Options: Xtensa Options.), or the `no-transform' directive 20237(*note transform: Transform Directive.). 20238 20239 The `MOVI' machine instruction can only materialize values in the 20240range from -2048 to 2047. Values outside this range are best 20241materialized with `L32R' instructions. Thus: 20242 20243 movi a0, 100000 20244 20245 is assembled into the following machine code: 20246 20247 .literal .L1, 100000 20248 l32r a0, .L1 20249 20250 The `L8UI' machine instruction can only be used with immediate 20251offsets in the range from 0 to 255. The `L16SI' and `L16UI' machine 20252instructions can only be used with offsets from 0 to 510. The `L32I' 20253machine instruction can only be used with offsets from 0 to 1020. A 20254load offset outside these ranges can be materialized with an `L32R' 20255instruction if the destination register of the load is different than 20256the source address register. For example: 20257 20258 l32i a1, a0, 2040 20259 20260 is translated to: 20261 20262 .literal .L1, 2040 20263 l32r a1, .L1 20264 add a1, a0, a1 20265 l32i a1, a1, 0 20266 20267If the load destination and source address register are the same, an 20268out-of-range offset causes an error. 20269 20270 The Xtensa `ADDI' instruction only allows immediate operands in the 20271range from -128 to 127. There are a number of alternate instruction 20272sequences for the `ADDI' operation. First, if the immediate is 0, the 20273`ADDI' will be turned into a `MOV.N' instruction (or the equivalent 20274`OR' instruction if the code density option is not available). If the 20275`ADDI' immediate is outside of the range -128 to 127, but inside the 20276range -32896 to 32639, an `ADDMI' instruction or `ADDMI'/`ADDI' 20277sequence will be used. Finally, if the immediate is outside of this 20278range and a free register is available, an `L32R'/`ADD' sequence will 20279be used with a literal allocated from the literal pool. 20280 20281 For example: 20282 20283 addi a5, a6, 0 20284 addi a5, a6, 512 20285 addi a5, a6, 513 20286 addi a5, a6, 50000 20287 20288 is assembled into the following: 20289 20290 .literal .L1, 50000 20291 mov.n a5, a6 20292 addmi a5, a6, 0x200 20293 addmi a5, a6, 0x200 20294 addi a5, a5, 1 20295 l32r a5, .L1 20296 add a5, a6, a5 20297 20298 20299File: as.info, Node: Xtensa Directives, Prev: Xtensa Relaxation, Up: Xtensa-Dependent 20300 203019.46.5 Directives 20302----------------- 20303 20304The Xtensa assembler supports a region-based directive syntax: 20305 20306 .begin DIRECTIVE [OPTIONS] 20307 ... 20308 .end DIRECTIVE 20309 20310 All the Xtensa-specific directives that apply to a region of code use 20311this syntax. 20312 20313 The directive applies to code between the `.begin' and the `.end'. 20314The state of the option after the `.end' reverts to what it was before 20315the `.begin'. A nested `.begin'/`.end' region can further change the 20316state of the directive without having to be aware of its outer state. 20317For example, consider: 20318 20319 .begin no-transform 20320 L: add a0, a1, a2 20321 .begin transform 20322 M: add a0, a1, a2 20323 .end transform 20324 N: add a0, a1, a2 20325 .end no-transform 20326 20327 The `ADD' opcodes at `L' and `N' in the outer `no-transform' region 20328both result in `ADD' machine instructions, but the assembler selects an 20329`ADD.N' instruction for the `ADD' at `M' in the inner `transform' 20330region. 20331 20332 The advantage of this style is that it works well inside macros 20333which can preserve the context of their callers. 20334 20335 The following directives are available: 20336 20337* Menu: 20338 20339* Schedule Directive:: Enable instruction scheduling. 20340* Longcalls Directive:: Use Indirect Calls for Greater Range. 20341* Transform Directive:: Disable All Assembler Transformations. 20342* Literal Directive:: Intermix Literals with Instructions. 20343* Literal Position Directive:: Specify Inline Literal Pool Locations. 20344* Literal Prefix Directive:: Specify Literal Section Name Prefix. 20345* Absolute Literals Directive:: Control PC-Relative vs. Absolute Literals. 20346 20347 20348File: as.info, Node: Schedule Directive, Next: Longcalls Directive, Up: Xtensa Directives 20349 203509.46.5.1 schedule 20351................. 20352 20353The `schedule' directive is recognized only for compatibility with 20354Tensilica's assembler. 20355 20356 .begin [no-]schedule 20357 .end [no-]schedule 20358 20359 This directive is ignored and has no effect on `as'. 20360 20361 20362File: as.info, Node: Longcalls Directive, Next: Transform Directive, Prev: Schedule Directive, Up: Xtensa Directives 20363 203649.46.5.2 longcalls 20365.................. 20366 20367The `longcalls' directive enables or disables function call relaxation. 20368*Note Function Call Relaxation: Xtensa Call Relaxation. 20369 20370 .begin [no-]longcalls 20371 .end [no-]longcalls 20372 20373 Call relaxation is disabled by default unless the `--longcalls' 20374command-line option is specified. The `longcalls' directive overrides 20375the default determined by the command-line options. 20376 20377 20378File: as.info, Node: Transform Directive, Next: Literal Directive, Prev: Longcalls Directive, Up: Xtensa Directives 20379 203809.46.5.3 transform 20381.................. 20382 20383This directive enables or disables all assembler transformation, 20384including relaxation (*note Xtensa Relaxation: Xtensa Relaxation.) and 20385optimization (*note Xtensa Optimizations: Xtensa Optimizations.). 20386 20387 .begin [no-]transform 20388 .end [no-]transform 20389 20390 Transformations are enabled by default unless the `--no-transform' 20391option is used. The `transform' directive overrides the default 20392determined by the command-line options. An underscore opcode prefix, 20393disabling transformation of that opcode, always takes precedence over 20394both directives and command-line flags. 20395 20396 20397File: as.info, Node: Literal Directive, Next: Literal Position Directive, Prev: Transform Directive, Up: Xtensa Directives 20398 203999.46.5.4 literal 20400................ 20401 20402The `.literal' directive is used to define literal pool data, i.e., 20403read-only 32-bit data accessed via `L32R' instructions. 20404 20405 .literal LABEL, VALUE[, VALUE...] 20406 20407 This directive is similar to the standard `.word' directive, except 20408that the actual location of the literal data is determined by the 20409assembler and linker, not by the position of the `.literal' directive. 20410Using this directive gives the assembler freedom to locate the literal 20411data in the most appropriate place and possibly to combine identical 20412literals. For example, the code: 20413 20414 entry sp, 40 20415 .literal .L1, sym 20416 l32r a4, .L1 20417 20418 can be used to load a pointer to the symbol `sym' into register 20419`a4'. The value of `sym' will not be placed between the `ENTRY' and 20420`L32R' instructions; instead, the assembler puts the data in a literal 20421pool. 20422 20423 Literal pools are placed by default in separate literal sections; 20424however, when using the `--text-section-literals' option (*note Command 20425Line Options: Xtensa Options.), the literal pools for PC-relative mode 20426`L32R' instructions are placed in the current section.(1) These text 20427section literal pools are created automatically before `ENTRY' 20428instructions and manually after `.literal_position' directives (*note 20429literal_position: Literal Position Directive.). If there are no 20430preceding `ENTRY' instructions, explicit `.literal_position' directives 20431must be used to place the text section literal pools; otherwise, `as' 20432will report an error. 20433 20434 When literals are placed in separate sections, the literal section 20435names are derived from the names of the sections where the literals are 20436defined. The base literal section names are `.literal' for PC-relative 20437mode `L32R' instructions and `.lit4' for absolute mode `L32R' 20438instructions (*note absolute-literals: Absolute Literals Directive.). 20439These base names are used for literals defined in the default `.text' 20440section. For literals defined in other sections or within the scope of 20441a `literal_prefix' directive (*note literal_prefix: Literal Prefix 20442Directive.), the following rules determine the literal section name: 20443 20444 1. If the current section is a member of a section group, the literal 20445 section name includes the group name as a suffix to the base 20446 `.literal' or `.lit4' name, with a period to separate the base 20447 name and group name. The literal section is also made a member of 20448 the group. 20449 20450 2. If the current section name (or `literal_prefix' value) begins with 20451 "`.gnu.linkonce.KIND.'", the literal section name is formed by 20452 replacing "`.KIND'" with the base `.literal' or `.lit4' name. For 20453 example, for literals defined in a section named 20454 `.gnu.linkonce.t.func', the literal section will be 20455 `.gnu.linkonce.literal.func' or `.gnu.linkonce.lit4.func'. 20456 20457 3. If the current section name (or `literal_prefix' value) ends with 20458 `.text', the literal section name is formed by replacing that 20459 suffix with the base `.literal' or `.lit4' name. For example, for 20460 literals defined in a section named `.iram0.text', the literal 20461 section will be `.iram0.literal' or `.iram0.lit4'. 20462 20463 4. If none of the preceding conditions apply, the literal section 20464 name is formed by adding the base `.literal' or `.lit4' name as a 20465 suffix to the current section name (or `literal_prefix' value). 20466 20467 ---------- Footnotes ---------- 20468 20469 (1) Literals for the `.init' and `.fini' sections are always placed 20470in separate sections, even when `--text-section-literals' is enabled. 20471 20472 20473File: as.info, Node: Literal Position Directive, Next: Literal Prefix Directive, Prev: Literal Directive, Up: Xtensa Directives 20474 204759.46.5.5 literal_position 20476......................... 20477 20478When using `--text-section-literals' to place literals inline in the 20479section being assembled, the `.literal_position' directive can be used 20480to mark a potential location for a literal pool. 20481 20482 .literal_position 20483 20484 The `.literal_position' directive is ignored when the 20485`--text-section-literals' option is not used or when `L32R' 20486instructions use the absolute addressing mode. 20487 20488 The assembler will automatically place text section literal pools 20489before `ENTRY' instructions, so the `.literal_position' directive is 20490only needed to specify some other location for a literal pool. You may 20491need to add an explicit jump instruction to skip over an inline literal 20492pool. 20493 20494 For example, an interrupt vector does not begin with an `ENTRY' 20495instruction so the assembler will be unable to automatically find a good 20496place to put a literal pool. Moreover, the code for the interrupt 20497vector must be at a specific starting address, so the literal pool 20498cannot come before the start of the code. The literal pool for the 20499vector must be explicitly positioned in the middle of the vector (before 20500any uses of the literals, due to the negative offsets used by 20501PC-relative `L32R' instructions). The `.literal_position' directive 20502can be used to do this. In the following code, the literal for `M' 20503will automatically be aligned correctly and is placed after the 20504unconditional jump. 20505 20506 .global M 20507 code_start: 20508 j continue 20509 .literal_position 20510 .align 4 20511 continue: 20512 movi a4, M 20513 20514 20515File: as.info, Node: Literal Prefix Directive, Next: Absolute Literals Directive, Prev: Literal Position Directive, Up: Xtensa Directives 20516 205179.46.5.6 literal_prefix 20518....................... 20519 20520The `literal_prefix' directive allows you to override the default 20521literal section names, which are derived from the names of the sections 20522where the literals are defined. 20523 20524 .begin literal_prefix [NAME] 20525 .end literal_prefix 20526 20527 For literals defined within the delimited region, the literal section 20528names are derived from the NAME argument instead of the name of the 20529current section. The rules used to derive the literal section names do 20530not change. *Note literal: Literal Directive. If the NAME argument is 20531omitted, the literal sections revert to the defaults. This directive 20532has no effect when using the `--text-section-literals' option (*note 20533Command Line Options: Xtensa Options.). 20534 20535 20536File: as.info, Node: Absolute Literals Directive, Prev: Literal Prefix Directive, Up: Xtensa Directives 20537 205389.46.5.7 absolute-literals 20539.......................... 20540 20541The `absolute-literals' and `no-absolute-literals' directives control 20542the absolute vs. PC-relative mode for `L32R' instructions. These are 20543relevant only for Xtensa configurations that include the absolute 20544addressing option for `L32R' instructions. 20545 20546 .begin [no-]absolute-literals 20547 .end [no-]absolute-literals 20548 20549 These directives do not change the `L32R' mode--they only cause the 20550assembler to emit the appropriate kind of relocation for `L32R' 20551instructions and to place the literal values in the appropriate section. 20552To change the `L32R' mode, the program must write the `LITBASE' special 20553register. It is the programmer's responsibility to keep track of the 20554mode and indicate to the assembler which mode is used in each region of 20555code. 20556 20557 If the Xtensa configuration includes the absolute `L32R' addressing 20558option, the default is to assume absolute `L32R' addressing unless the 20559`--no-absolute-literals' command-line option is specified. Otherwise, 20560the default is to assume PC-relative `L32R' addressing. The 20561`absolute-literals' directive can then be used to override the default 20562determined by the command-line options. 20563 20564 20565File: as.info, Node: Reporting Bugs, Next: Acknowledgements, Prev: Machine Dependencies, Up: Top 20566 2056710 Reporting Bugs 20568***************** 20569 20570Your bug reports play an essential role in making `as' reliable. 20571 20572 Reporting a bug may help you by bringing a solution to your problem, 20573or it may not. But in any case the principal function of a bug report 20574is to help the entire community by making the next version of `as' work 20575better. Bug reports are your contribution to the maintenance of `as'. 20576 20577 In order for a bug report to serve its purpose, you must include the 20578information that enables us to fix the bug. 20579 20580* Menu: 20581 20582* Bug Criteria:: Have you found a bug? 20583* Bug Reporting:: How to report bugs 20584 20585 20586File: as.info, Node: Bug Criteria, Next: Bug Reporting, Up: Reporting Bugs 20587 2058810.1 Have You Found a Bug? 20589========================== 20590 20591If you are not sure whether you have found a bug, here are some 20592guidelines: 20593 20594 * If the assembler gets a fatal signal, for any input whatever, that 20595 is a `as' bug. Reliable assemblers never crash. 20596 20597 * If `as' produces an error message for valid input, that is a bug. 20598 20599 * If `as' does not produce an error message for invalid input, that 20600 is a bug. However, you should note that your idea of "invalid 20601 input" might be our idea of "an extension" or "support for 20602 traditional practice". 20603 20604 * If you are an experienced user of assemblers, your suggestions for 20605 improvement of `as' are welcome in any case. 20606 20607 20608File: as.info, Node: Bug Reporting, Prev: Bug Criteria, Up: Reporting Bugs 20609 2061010.2 How to Report Bugs 20611======================= 20612 20613A number of companies and individuals offer support for GNU products. 20614If you obtained `as' from a support organization, we recommend you 20615contact that organization first. 20616 20617 You can find contact information for many support companies and 20618individuals in the file `etc/SERVICE' in the GNU Emacs distribution. 20619 20620 In any event, we also recommend that you send bug reports for `as' 20621to `https://support.codesourcery.com/GNUToolchain/'. 20622 20623 The fundamental principle of reporting bugs usefully is this: 20624*report all the facts*. If you are not sure whether to state a fact or 20625leave it out, state it! 20626 20627 Often people omit facts because they think they know what causes the 20628problem and assume that some details do not matter. Thus, you might 20629assume that the name of a symbol you use in an example does not matter. 20630Well, probably it does not, but one cannot be sure. Perhaps the bug is 20631a stray memory reference which happens to fetch from the location where 20632that name is stored in memory; perhaps, if the name were different, the 20633contents of that location would fool the assembler into doing the right 20634thing despite the bug. Play it safe and give a specific, complete 20635example. That is the easiest thing for you to do, and the most helpful. 20636 20637 Keep in mind that the purpose of a bug report is to enable us to fix 20638the bug if it is new to us. Therefore, always write your bug reports 20639on the assumption that the bug has not been reported previously. 20640 20641 Sometimes people give a few sketchy facts and ask, "Does this ring a 20642bell?" This cannot help us fix a bug, so it is basically useless. We 20643respond by asking for enough details to enable us to investigate. You 20644might as well expedite matters by sending them to begin with. 20645 20646 To enable us to fix the bug, you should include all these things: 20647 20648 * The version of `as'. `as' announces it if you start it with the 20649 `--version' argument. 20650 20651 Without this, we will not know whether there is any point in 20652 looking for the bug in the current version of `as'. 20653 20654 * Any patches you may have applied to the `as' source. 20655 20656 * The type of machine you are using, and the operating system name 20657 and version number. 20658 20659 * What compiler (and its version) was used to compile `as'--e.g. 20660 "`gcc-2.7'". 20661 20662 * The command arguments you gave the assembler to assemble your 20663 example and observe the bug. To guarantee you will not omit 20664 something important, list them all. A copy of the Makefile (or 20665 the output from make) is sufficient. 20666 20667 If we were to try to guess the arguments, we would probably guess 20668 wrong and then we might not encounter the bug. 20669 20670 * A complete input file that will reproduce the bug. If the bug is 20671 observed when the assembler is invoked via a compiler, send the 20672 assembler source, not the high level language source. Most 20673 compilers will produce the assembler source when run with the `-S' 20674 option. If you are using `gcc', use the options `-v 20675 --save-temps'; this will save the assembler source in a file with 20676 an extension of `.s', and also show you exactly how `as' is being 20677 run. 20678 20679 * A description of what behavior you observe that you believe is 20680 incorrect. For example, "It gets a fatal signal." 20681 20682 Of course, if the bug is that `as' gets a fatal signal, then we 20683 will certainly notice it. But if the bug is incorrect output, we 20684 might not notice unless it is glaringly wrong. You might as well 20685 not give us a chance to make a mistake. 20686 20687 Even if the problem you experience is a fatal signal, you should 20688 still say so explicitly. Suppose something strange is going on, 20689 such as, your copy of `as' is out of sync, or you have encountered 20690 a bug in the C library on your system. (This has happened!) Your 20691 copy might crash and ours would not. If you told us to expect a 20692 crash, then when ours fails to crash, we would know that the bug 20693 was not happening for us. If you had not told us to expect a 20694 crash, then we would not be able to draw any conclusion from our 20695 observations. 20696 20697 * If you wish to suggest changes to the `as' source, send us context 20698 diffs, as generated by `diff' with the `-u', `-c', or `-p' option. 20699 Always send diffs from the old file to the new file. If you even 20700 discuss something in the `as' source, refer to it by context, not 20701 by line number. 20702 20703 The line numbers in our development sources will not match those 20704 in your sources. Your line numbers would convey no useful 20705 information to us. 20706 20707 Here are some things that are not necessary: 20708 20709 * A description of the envelope of the bug. 20710 20711 Often people who encounter a bug spend a lot of time investigating 20712 which changes to the input file will make the bug go away and which 20713 changes will not affect it. 20714 20715 This is often time consuming and not very useful, because the way 20716 we will find the bug is by running a single example under the 20717 debugger with breakpoints, not by pure deduction from a series of 20718 examples. We recommend that you save your time for something else. 20719 20720 Of course, if you can find a simpler example to report _instead_ 20721 of the original one, that is a convenience for us. Errors in the 20722 output will be easier to spot, running under the debugger will take 20723 less time, and so on. 20724 20725 However, simplification is not vital; if you do not want to do 20726 this, report the bug anyway and send us the entire test case you 20727 used. 20728 20729 * A patch for the bug. 20730 20731 A patch for the bug does help us if it is a good one. But do not 20732 omit the necessary information, such as the test case, on the 20733 assumption that a patch is all we need. We might see problems 20734 with your patch and decide to fix the problem another way, or we 20735 might not understand it at all. 20736 20737 Sometimes with a program as complicated as `as' it is very hard to 20738 construct an example that will make the program follow a certain 20739 path through the code. If you do not send us the example, we will 20740 not be able to construct one, so we will not be able to verify 20741 that the bug is fixed. 20742 20743 And if we cannot understand what bug you are trying to fix, or why 20744 your patch should be an improvement, we will not install it. A 20745 test case will help us to understand. 20746 20747 * A guess about what the bug is or what it depends on. 20748 20749 Such guesses are usually wrong. Even we cannot guess right about 20750 such things without first using the debugger to find the facts. 20751 20752 20753File: as.info, Node: Acknowledgements, Next: GNU Free Documentation License, Prev: Reporting Bugs, Up: Top 20754 2075511 Acknowledgements 20756******************* 20757 20758If you have contributed to GAS and your name isn't listed here, it is 20759not meant as a slight. We just don't know about it. Send mail to the 20760maintainer, and we'll correct the situation. Currently the maintainer 20761is Ken Raeburn (email address `raeburn@cygnus.com'). 20762 20763 Dean Elsner wrote the original GNU assembler for the VAX.(1) 20764 20765 Jay Fenlason maintained GAS for a while, adding support for 20766GDB-specific debug information and the 68k series machines, most of the 20767preprocessing pass, and extensive changes in `messages.c', 20768`input-file.c', `write.c'. 20769 20770 K. Richard Pixley maintained GAS for a while, adding various 20771enhancements and many bug fixes, including merging support for several 20772processors, breaking GAS up to handle multiple object file format back 20773ends (including heavy rewrite, testing, an integration of the coff and 20774b.out back ends), adding configuration including heavy testing and 20775verification of cross assemblers and file splits and renaming, 20776converted GAS to strictly ANSI C including full prototypes, added 20777support for m680[34]0 and cpu32, did considerable work on i960 20778including a COFF port (including considerable amounts of reverse 20779engineering), a SPARC opcode file rewrite, DECstation, rs6000, and 20780hp300hpux host ports, updated "know" assertions and made them work, 20781much other reorganization, cleanup, and lint. 20782 20783 Ken Raeburn wrote the high-level BFD interface code to replace most 20784of the code in format-specific I/O modules. 20785 20786 The original VMS support was contributed by David L. Kashtan. Eric 20787Youngdale has done much work with it since. 20788 20789 The Intel 80386 machine description was written by Eliot Dresselhaus. 20790 20791 Minh Tran-Le at IntelliCorp contributed some AIX 386 support. 20792 20793 The Motorola 88k machine description was contributed by Devon Bowen 20794of Buffalo University and Torbjorn Granlund of the Swedish Institute of 20795Computer Science. 20796 20797 Keith Knowles at the Open Software Foundation wrote the original 20798MIPS back end (`tc-mips.c', `tc-mips.h'), and contributed Rose format 20799support (which hasn't been merged in yet). Ralph Campbell worked with 20800the MIPS code to support a.out format. 20801 20802 Support for the Zilog Z8k and Renesas H8/300 processors (tc-z8k, 20803tc-h8300), and IEEE 695 object file format (obj-ieee), was written by 20804Steve Chamberlain of Cygnus Support. Steve also modified the COFF back 20805end to use BFD for some low-level operations, for use with the H8/300 20806and AMD 29k targets. 20807 20808 John Gilmore built the AMD 29000 support, added `.include' support, 20809and simplified the configuration of which versions accept which 20810directives. He updated the 68k machine description so that Motorola's 20811opcodes always produced fixed-size instructions (e.g., `jsr'), while 20812synthetic instructions remained shrinkable (`jbsr'). John fixed many 20813bugs, including true tested cross-compilation support, and one bug in 20814relaxation that took a week and required the proverbial one-bit fix. 20815 20816 Ian Lance Taylor of Cygnus Support merged the Motorola and MIT 20817syntax for the 68k, completed support for some COFF targets (68k, i386 20818SVR3, and SCO Unix), added support for MIPS ECOFF and ELF targets, 20819wrote the initial RS/6000 and PowerPC assembler, and made a few other 20820minor patches. 20821 20822 Steve Chamberlain made GAS able to generate listings. 20823 20824 Hewlett-Packard contributed support for the HP9000/300. 20825 20826 Jeff Law wrote GAS and BFD support for the native HPPA object format 20827(SOM) along with a fairly extensive HPPA testsuite (for both SOM and 20828ELF object formats). This work was supported by both the Center for 20829Software Science at the University of Utah and Cygnus Support. 20830 20831 Support for ELF format files has been worked on by Mark Eichin of 20832Cygnus Support (original, incomplete implementation for SPARC), Pete 20833Hoogenboom and Jeff Law at the University of Utah (HPPA mainly), 20834Michael Meissner of the Open Software Foundation (i386 mainly), and Ken 20835Raeburn of Cygnus Support (sparc, and some initial 64-bit support). 20836 20837 Linas Vepstas added GAS support for the ESA/390 "IBM 370" 20838architecture. 20839 20840 Richard Henderson rewrote the Alpha assembler. Klaus Kaempf wrote 20841GAS and BFD support for openVMS/Alpha. 20842 20843 Timothy Wall, Michael Hayes, and Greg Smart contributed to the 20844various tic* flavors. 20845 20846 David Heine, Sterling Augustine, Bob Wilson and John Ruttenberg from 20847Tensilica, Inc. added support for Xtensa processors. 20848 20849 Several engineers at Cygnus Support have also provided many small 20850bug fixes and configuration enhancements. 20851 20852 Jon Beniston added support for the Lattice Mico32 architecture. 20853 20854 Many others have contributed large or small bugfixes and 20855enhancements. If you have contributed significant work and are not 20856mentioned on this list, and want to be, let us know. Some of the 20857history has been lost; we are not intentionally leaving anyone out. 20858 20859 ---------- Footnotes ---------- 20860 20861 (1) Any more details? 20862 20863 20864File: as.info, Node: GNU Free Documentation License, Next: AS Index, Prev: Acknowledgements, Up: Top 20865 20866Appendix A GNU Free Documentation License 20867***************************************** 20868 20869 Version 1.3, 3 November 2008 20870 20871 Copyright (C) 2000, 2001, 2002, 2007, 2008 Free Software Foundation, Inc. 20872 `http://fsf.org/' 20873 20874 Everyone is permitted to copy and distribute verbatim copies 20875 of this license document, but changing it is not allowed. 20876 20877 0. PREAMBLE 20878 20879 The purpose of this License is to make a manual, textbook, or other 20880 functional and useful document "free" in the sense of freedom: to 20881 assure everyone the effective freedom to copy and redistribute it, 20882 with or without modifying it, either commercially or 20883 noncommercially. Secondarily, this License preserves for the 20884 author and publisher a way to get credit for their work, while not 20885 being considered responsible for modifications made by others. 20886 20887 This License is a kind of "copyleft", which means that derivative 20888 works of the document must themselves be free in the same sense. 20889 It complements the GNU General Public License, which is a copyleft 20890 license designed for free software. 20891 20892 We have designed this License in order to use it for manuals for 20893 free software, because free software needs free documentation: a 20894 free program should come with manuals providing the same freedoms 20895 that the software does. But this License is not limited to 20896 software manuals; it can be used for any textual work, regardless 20897 of subject matter or whether it is published as a printed book. 20898 We recommend this License principally for works whose purpose is 20899 instruction or reference. 20900 20901 1. APPLICABILITY AND DEFINITIONS 20902 20903 This License applies to any manual or other work, in any medium, 20904 that contains a notice placed by the copyright holder saying it 20905 can be distributed under the terms of this License. Such a notice 20906 grants a world-wide, royalty-free license, unlimited in duration, 20907 to use that work under the conditions stated herein. The 20908 "Document", below, refers to any such manual or work. Any member 20909 of the public is a licensee, and is addressed as "you". You 20910 accept the license if you copy, modify or distribute the work in a 20911 way requiring permission under copyright law. 20912 20913 A "Modified Version" of the Document means any work containing the 20914 Document or a portion of it, either copied verbatim, or with 20915 modifications and/or translated into another language. 20916 20917 A "Secondary Section" is a named appendix or a front-matter section 20918 of the Document that deals exclusively with the relationship of the 20919 publishers or authors of the Document to the Document's overall 20920 subject (or to related matters) and contains nothing that could 20921 fall directly within that overall subject. (Thus, if the Document 20922 is in part a textbook of mathematics, a Secondary Section may not 20923 explain any mathematics.) The relationship could be a matter of 20924 historical connection with the subject or with related matters, or 20925 of legal, commercial, philosophical, ethical or political position 20926 regarding them. 20927 20928 The "Invariant Sections" are certain Secondary Sections whose 20929 titles are designated, as being those of Invariant Sections, in 20930 the notice that says that the Document is released under this 20931 License. If a section does not fit the above definition of 20932 Secondary then it is not allowed to be designated as Invariant. 20933 The Document may contain zero Invariant Sections. If the Document 20934 does not identify any Invariant Sections then there are none. 20935 20936 The "Cover Texts" are certain short passages of text that are 20937 listed, as Front-Cover Texts or Back-Cover Texts, in the notice 20938 that says that the Document is released under this License. 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A 20954 copy that is not "Transparent" is called "Opaque". 20955 20956 Examples of suitable formats for Transparent copies include plain 20957 ASCII without markup, Texinfo input format, LaTeX input format, 20958 SGML or XML using a publicly available DTD, and 20959 standard-conforming simple HTML, PostScript or PDF designed for 20960 human modification. Examples of transparent image formats include 20961 PNG, XCF and JPG. Opaque formats include proprietary formats that 20962 can be read and edited only by proprietary word processors, SGML or 20963 XML for which the DTD and/or processing tools are not generally 20964 available, and the machine-generated HTML, PostScript or PDF 20965 produced by some word processors for output purposes only. 20966 20967 The "Title Page" means, for a printed book, the title page itself, 20968 plus such following pages as are needed to hold, legibly, the 20969 material this License requires to appear in the title page. For 20970 works in formats which do not have any title page as such, "Title 20971 Page" means the text near the most prominent appearance of the 20972 work's title, preceding the beginning of the body of the text. 20973 20974 The "publisher" means any person or entity that distributes copies 20975 of the Document to the public. 20976 20977 A section "Entitled XYZ" means a named subunit of the Document 20978 whose title either is precisely XYZ or contains XYZ in parentheses 20979 following text that translates XYZ in another language. (Here XYZ 20980 stands for a specific section name mentioned below, such as 20981 "Acknowledgements", "Dedications", "Endorsements", or "History".) 20982 To "Preserve the Title" of such a section when you modify the 20983 Document means that it remains a section "Entitled XYZ" according 20984 to this definition. 20985 20986 The Document may include Warranty Disclaimers next to the notice 20987 which states that this License applies to the Document. These 20988 Warranty Disclaimers are considered to be included by reference in 20989 this License, but only as regards disclaiming warranties: any other 20990 implication that these Warranty Disclaimers may have is void and 20991 has no effect on the meaning of this License. 20992 20993 2. VERBATIM COPYING 20994 20995 You may copy and distribute the Document in any medium, either 20996 commercially or noncommercially, provided that this License, the 20997 copyright notices, and the license notice saying this License 20998 applies to the Document are reproduced in all copies, and that you 20999 add no other conditions whatsoever to those of this License. You 21000 may not use technical measures to obstruct or control the reading 21001 or further copying of the copies you make or distribute. However, 21002 you may accept compensation in exchange for copies. If you 21003 distribute a large enough number of copies you must also follow 21004 the conditions in section 3. 21005 21006 You may also lend copies, under the same conditions stated above, 21007 and you may publicly display copies. 21008 21009 3. COPYING IN QUANTITY 21010 21011 If you publish printed copies (or copies in media that commonly 21012 have printed covers) of the Document, numbering more than 100, and 21013 the Document's license notice requires Cover Texts, you must 21014 enclose the copies in covers that carry, clearly and legibly, all 21015 these Cover Texts: Front-Cover Texts on the front cover, and 21016 Back-Cover Texts on the back cover. Both covers must also clearly 21017 and legibly identify you as the publisher of these copies. The 21018 front cover must present the full title with all words of the 21019 title equally prominent and visible. You may add other material 21020 on the covers in addition. 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If you use the 21037 latter option, you must take reasonably prudent steps, when you 21038 begin distribution of Opaque copies in quantity, to ensure that 21039 this Transparent copy will remain thus accessible at the stated 21040 location until at least one year after the last time you 21041 distribute an Opaque copy (directly or through your agents or 21042 retailers) of that edition to the public. 21043 21044 It is requested, but not required, that you contact the authors of 21045 the Document well before redistributing any large number of 21046 copies, to give them a chance to provide you with an updated 21047 version of the Document. 21048 21049 4. MODIFICATIONS 21050 21051 You may copy and distribute a Modified Version of the Document 21052 under the conditions of sections 2 and 3 above, provided that you 21053 release the Modified Version under precisely this License, with 21054 the Modified Version filling the role of the Document, thus 21055 licensing distribution and modification of the Modified Version to 21056 whoever possesses a copy of it. In addition, you must do these 21057 things in the Modified Version: 21058 21059 A. Use in the Title Page (and on the covers, if any) a title 21060 distinct from that of the Document, and from those of 21061 previous versions (which should, if there were any, be listed 21062 in the History section of the Document). You may use the 21063 same title as a previous version if the original publisher of 21064 that version gives permission. 21065 21066 B. List on the Title Page, as authors, one or more persons or 21067 entities responsible for authorship of the modifications in 21068 the Modified Version, together with at least five of the 21069 principal authors of the Document (all of its principal 21070 authors, if it has fewer than five), unless they release you 21071 from this requirement. 21072 21073 C. State on the Title page the name of the publisher of the 21074 Modified Version, as the publisher. 21075 21076 D. Preserve all the copyright notices of the Document. 21077 21078 E. Add an appropriate copyright notice for your modifications 21079 adjacent to the other copyright notices. 21080 21081 F. Include, immediately after the copyright notices, a license 21082 notice giving the public permission to use the Modified 21083 Version under the terms of this License, in the form shown in 21084 the Addendum below. 21085 21086 G. Preserve in that license notice the full lists of Invariant 21087 Sections and required Cover Texts given in the Document's 21088 license notice. 21089 21090 H. Include an unaltered copy of this License. 21091 21092 I. Preserve the section Entitled "History", Preserve its Title, 21093 and add to it an item stating at least the title, year, new 21094 authors, and publisher of the Modified Version as given on 21095 the Title Page. If there is no section Entitled "History" in 21096 the Document, create one stating the title, year, authors, 21097 and publisher of the Document as given on its Title Page, 21098 then add an item describing the Modified Version as stated in 21099 the previous sentence. 21100 21101 J. Preserve the network location, if any, given in the Document 21102 for public access to a Transparent copy of the Document, and 21103 likewise the network locations given in the Document for 21104 previous versions it was based on. These may be placed in 21105 the "History" section. You may omit a network location for a 21106 work that was published at least four years before the 21107 Document itself, or if the original publisher of the version 21108 it refers to gives permission. 21109 21110 K. For any section Entitled "Acknowledgements" or "Dedications", 21111 Preserve the Title of the section, and preserve in the 21112 section all the substance and tone of each of the contributor 21113 acknowledgements and/or dedications given therein. 21114 21115 L. Preserve all the Invariant Sections of the Document, 21116 unaltered in their text and in their titles. Section numbers 21117 or the equivalent are not considered part of the section 21118 titles. 21119 21120 M. Delete any section Entitled "Endorsements". Such a section 21121 may not be included in the Modified Version. 21122 21123 N. Do not retitle any existing section to be Entitled 21124 "Endorsements" or to conflict in title with any Invariant 21125 Section. 21126 21127 O. Preserve any Warranty Disclaimers. 21128 21129 If the Modified Version includes new front-matter sections or 21130 appendices that qualify as Secondary Sections and contain no 21131 material copied from the Document, you may at your option 21132 designate some or all of these sections as invariant. To do this, 21133 add their titles to the list of Invariant Sections in the Modified 21134 Version's license notice. These titles must be distinct from any 21135 other section titles. 21136 21137 You may add a section Entitled "Endorsements", provided it contains 21138 nothing but endorsements of your Modified Version by various 21139 parties--for example, statements of peer review or that the text 21140 has been approved by an organization as the authoritative 21141 definition of a standard. 21142 21143 You may add a passage of up to five words as a Front-Cover Text, 21144 and a passage of up to 25 words as a Back-Cover Text, to the end 21145 of the list of Cover Texts in the Modified Version. Only one 21146 passage of Front-Cover Text and one of Back-Cover Text may be 21147 added by (or through arrangements made by) any one entity. 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COMBINING DOCUMENTS 21159 21160 You may combine the Document with other documents released under 21161 this License, under the terms defined in section 4 above for 21162 modified versions, provided that you include in the combination 21163 all of the Invariant Sections of all of the original documents, 21164 unmodified, and list them all as Invariant Sections of your 21165 combined work in its license notice, and that you preserve all 21166 their Warranty Disclaimers. 21167 21168 The combined work need only contain one copy of this License, and 21169 multiple identical Invariant Sections may be replaced with a single 21170 copy. If there are multiple Invariant Sections with the same name 21171 but different contents, make the title of each such section unique 21172 by adding at the end of it, in parentheses, the name of the 21173 original author or publisher of that section if known, or else a 21174 unique number. Make the same adjustment to the section titles in 21175 the list of Invariant Sections in the license notice of the 21176 combined work. 21177 21178 In the combination, you must combine any sections Entitled 21179 "History" in the various original documents, forming one section 21180 Entitled "History"; likewise combine any sections Entitled 21181 "Acknowledgements", and any sections Entitled "Dedications". You 21182 must delete all sections Entitled "Endorsements." 21183 21184 6. COLLECTIONS OF DOCUMENTS 21185 21186 You may make a collection consisting of the Document and other 21187 documents released under this License, and replace the individual 21188 copies of this License in the various documents with a single copy 21189 that is included in the collection, provided that you follow the 21190 rules of this License for verbatim copying of each of the 21191 documents in all other respects. 21192 21193 You may extract a single document from such a collection, and 21194 distribute it individually under this License, provided you insert 21195 a copy of this License into the extracted document, and follow 21196 this License in all other respects regarding verbatim copying of 21197 that document. 21198 21199 7. AGGREGATION WITH INDEPENDENT WORKS 21200 21201 A compilation of the Document or its derivatives with other 21202 separate and independent documents or works, in or on a volume of 21203 a storage or distribution medium, is called an "aggregate" if the 21204 copyright resulting from the compilation is not used to limit the 21205 legal rights of the compilation's users beyond what the individual 21206 works permit. When the Document is included in an aggregate, this 21207 License does not apply to the other works in the aggregate which 21208 are not themselves derivative works of the Document. 21209 21210 If the Cover Text requirement of section 3 is applicable to these 21211 copies of the Document, then if the Document is less than one half 21212 of the entire aggregate, the Document's Cover Texts may be placed 21213 on covers that bracket the Document within the aggregate, or the 21214 electronic equivalent of covers if the Document is in electronic 21215 form. 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Any attempt 21243 otherwise to copy, modify, sublicense, or distribute it is void, 21244 and will automatically terminate your rights under this License. 21245 21246 However, if you cease all violation of this License, then your 21247 license from a particular copyright holder is reinstated (a) 21248 provisionally, unless and until the copyright holder explicitly 21249 and finally terminates your license, and (b) permanently, if the 21250 copyright holder fails to notify you of the violation by some 21251 reasonable means prior to 60 days after the cessation. 21252 21253 Moreover, your license from a particular copyright holder is 21254 reinstated permanently if the copyright holder notifies you of the 21255 violation by some reasonable means, this is the first time you have 21256 received notice of violation of this License (for any work) from 21257 that copyright holder, and you cure the violation prior to 30 days 21258 after your receipt of the notice. 21259 21260 Termination of your rights under this section does not terminate 21261 the licenses of parties who have received copies or rights from 21262 you under this License. If your rights have been terminated and 21263 not permanently reinstated, receipt of a copy of some or all of 21264 the same material does not give you any rights to use it. 21265 21266 10. FUTURE REVISIONS OF THIS LICENSE 21267 21268 The Free Software Foundation may publish new, revised versions of 21269 the GNU Free Documentation License from time to time. Such new 21270 versions will be similar in spirit to the present version, but may 21271 differ in detail to address new problems or concerns. See 21272 `http://www.gnu.org/copyleft/'. 21273 21274 Each version of the License is given a distinguishing version 21275 number. If the Document specifies that a particular numbered 21276 version of this License "or any later version" applies to it, you 21277 have the option of following the terms and conditions either of 21278 that specified version or of any later version that has been 21279 published (not as a draft) by the Free Software Foundation. If 21280 the Document does not specify a version number of this License, 21281 you may choose any version ever published (not as a draft) by the 21282 Free Software Foundation. If the Document specifies that a proxy 21283 can decide which future versions of this License can be used, that 21284 proxy's public statement of acceptance of a version permanently 21285 authorizes you to choose that version for the Document. 21286 21287 11. RELICENSING 21288 21289 "Massive Multiauthor Collaboration Site" (or "MMC Site") means any 21290 World Wide Web server that publishes copyrightable works and also 21291 provides prominent facilities for anybody to edit those works. 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A copy of the license is included in the section entitled ``GNU 21331 Free Documentation License''. 21332 21333 If you have Invariant Sections, Front-Cover Texts and Back-Cover 21334Texts, replace the "with...Texts." line with this: 21335 21336 with the Invariant Sections being LIST THEIR TITLES, with 21337 the Front-Cover Texts being LIST, and with the Back-Cover Texts 21338 being LIST. 21339 21340 If you have Invariant Sections without Cover Texts, or some other 21341combination of the three, merge those two alternatives to suit the 21342situation. 21343 21344 If your document contains nontrivial examples of program code, we 21345recommend releasing these examples in parallel under your choice of 21346free software license, such as the GNU General Public License, to 21347permit their use in free software. 21348 21349 21350File: as.info, Node: AS Index, Prev: GNU Free Documentation License, Up: Top 21351 21352AS Index 21353******** 21354 21355[index] 21356* Menu: 21357 21358* #: Comments. (line 33) 21359* #APP: Preprocessing. (line 26) 21360* #NO_APP: Preprocessing. (line 26) 21361* $ in symbol names <1>: SH64-Chars. (line 15) 21362* $ in symbol names <2>: SH-Chars. (line 15) 21363* $ in symbol names <3>: D30V-Chars. (line 70) 21364* $ in symbol names: D10V-Chars. (line 53) 21365* $a: ARM Mapping Symbols. (line 9) 21366* $acos math builtin, TIC54X: TIC54X-Builtins. (line 10) 21367* $asin math builtin, TIC54X: TIC54X-Builtins. (line 13) 21368* $atan math builtin, TIC54X: TIC54X-Builtins. (line 16) 21369* $atan2 math builtin, TIC54X: TIC54X-Builtins. (line 19) 21370* $ceil math builtin, TIC54X: TIC54X-Builtins. (line 22) 21371* $cos math builtin, TIC54X: TIC54X-Builtins. (line 28) 21372* $cosh math builtin, TIC54X: TIC54X-Builtins. (line 25) 21373* $cvf math builtin, TIC54X: TIC54X-Builtins. (line 31) 21374* $cvi math builtin, TIC54X: TIC54X-Builtins. (line 34) 21375* $d: ARM Mapping Symbols. (line 15) 21376* $exp math builtin, TIC54X: TIC54X-Builtins. (line 37) 21377* $fabs math builtin, TIC54X: TIC54X-Builtins. (line 40) 21378* $firstch subsym builtin, TIC54X: TIC54X-Macros. (line 26) 21379* $floor math builtin, TIC54X: TIC54X-Builtins. (line 43) 21380* $fmod math builtin, TIC54X: TIC54X-Builtins. (line 47) 21381* $int math builtin, TIC54X: TIC54X-Builtins. (line 50) 21382* $iscons subsym builtin, TIC54X: TIC54X-Macros. (line 43) 21383* $isdefed subsym builtin, TIC54X: TIC54X-Macros. (line 34) 21384* $ismember subsym builtin, TIC54X: TIC54X-Macros. (line 38) 21385* $isname subsym builtin, TIC54X: TIC54X-Macros. (line 47) 21386* $isreg subsym builtin, TIC54X: TIC54X-Macros. (line 50) 21387* $lastch subsym builtin, TIC54X: TIC54X-Macros. (line 30) 21388* $ldexp math builtin, TIC54X: TIC54X-Builtins. (line 53) 21389* $log math builtin, TIC54X: TIC54X-Builtins. (line 59) 21390* $log10 math builtin, TIC54X: TIC54X-Builtins. (line 56) 21391* $max math builtin, TIC54X: TIC54X-Builtins. (line 62) 21392* $min math builtin, TIC54X: TIC54X-Builtins. (line 65) 21393* $pow math builtin, TIC54X: TIC54X-Builtins. (line 68) 21394* $round math builtin, TIC54X: TIC54X-Builtins. (line 71) 21395* $sgn math builtin, TIC54X: TIC54X-Builtins. (line 74) 21396* $sin math builtin, TIC54X: TIC54X-Builtins. (line 77) 21397* $sinh math builtin, TIC54X: TIC54X-Builtins. (line 80) 21398* $sqrt math builtin, TIC54X: TIC54X-Builtins. (line 83) 21399* $structacc subsym builtin, TIC54X: TIC54X-Macros. (line 57) 21400* $structsz subsym builtin, TIC54X: TIC54X-Macros. (line 54) 21401* $symcmp subsym builtin, TIC54X: TIC54X-Macros. (line 23) 21402* $symlen subsym builtin, TIC54X: TIC54X-Macros. (line 20) 21403* $t: ARM Mapping Symbols. (line 12) 21404* $tan math builtin, TIC54X: TIC54X-Builtins. (line 86) 21405* $tanh math builtin, TIC54X: TIC54X-Builtins. (line 89) 21406* $trunc math builtin, TIC54X: TIC54X-Builtins. (line 92) 21407* -+ option, VAX/VMS: VAX-Opts. (line 71) 21408* --: Command Line. (line 10) 21409* --32 option, i386: i386-Options. (line 8) 21410* --32 option, x86-64: i386-Options. (line 8) 21411* --64 option, i386: i386-Options. (line 8) 21412* --64 option, x86-64: i386-Options. (line 8) 21413* --absolute-literals: Xtensa Options. (line 21) 21414* --allow-reg-prefix: SH Options. (line 9) 21415* --alternate: alternate. (line 6) 21416* --base-size-default-16: M68K-Opts. (line 65) 21417* --base-size-default-32: M68K-Opts. (line 65) 21418* --big: SH Options. (line 9) 21419* --bitwise-or option, M680x0: M68K-Opts. (line 58) 21420* --disp-size-default-16: M68K-Opts. (line 74) 21421* --disp-size-default-32: M68K-Opts. (line 74) 21422* --divide option, i386: i386-Options. (line 24) 21423* --dsp: SH Options. (line 9) 21424* --emulation=crisaout command line option, CRIS: CRIS-Opts. (line 9) 21425* --emulation=criself command line option, CRIS: CRIS-Opts. (line 9) 21426* --enforce-aligned-data: Sparc-Aligned-Data. (line 11) 21427* --fatal-warnings: W. (line 16) 21428* --fdpic: SH Options. (line 31) 21429* --fix-v4bx command line option, ARM: ARM Options. (line 167) 21430* --fixed-special-register-names command line option, MMIX: MMIX-Opts. 21431 (line 8) 21432* --force-long-branches: M68HC11-Opts. (line 69) 21433* --generate-example: M68HC11-Opts. (line 86) 21434* --globalize-symbols command line option, MMIX: MMIX-Opts. (line 12) 21435* --gnu-syntax command line option, MMIX: MMIX-Opts. (line 16) 21436* --hash-size=NUMBER: Overview. (line 370) 21437* --linker-allocated-gregs command line option, MMIX: MMIX-Opts. 21438 (line 67) 21439* --listing-cont-lines: listing. (line 34) 21440* --listing-lhs-width: listing. (line 16) 21441* --listing-lhs-width2: listing. (line 21) 21442* --listing-rhs-width: listing. (line 28) 21443* --little: SH Options. (line 9) 21444* --longcalls: Xtensa Options. (line 35) 21445* --march=ARCHITECTURE command line option, CRIS: CRIS-Opts. (line 34) 21446* --MD: MD. (line 6) 21447* --mul-bug-abort command line option, CRIS: CRIS-Opts. (line 62) 21448* --no-absolute-literals: Xtensa Options. (line 21) 21449* --no-expand command line option, MMIX: MMIX-Opts. (line 31) 21450* --no-longcalls: Xtensa Options. (line 35) 21451* --no-merge-gregs command line option, MMIX: MMIX-Opts. (line 36) 21452* --no-mul-bug-abort command line option, CRIS: CRIS-Opts. (line 62) 21453* --no-predefined-syms command line option, MMIX: MMIX-Opts. (line 22) 21454* --no-pushj-stubs command line option, MMIX: MMIX-Opts. (line 54) 21455* --no-stubs command line option, MMIX: MMIX-Opts. (line 54) 21456* --no-target-align: Xtensa Options. (line 28) 21457* --no-text-section-literals: Xtensa Options. (line 7) 21458* --no-transform: Xtensa Options. (line 44) 21459* --no-underscore command line option, CRIS: CRIS-Opts. (line 15) 21460* --no-warn: W. (line 11) 21461* --pcrel: M68K-Opts. (line 86) 21462* --pic command line option, CRIS: CRIS-Opts. (line 27) 21463* --print-insn-syntax: M68HC11-Opts. (line 75) 21464* --print-opcodes: M68HC11-Opts. (line 79) 21465* --register-prefix-optional option, M680x0: M68K-Opts. (line 45) 21466* --relax: SH Options. (line 9) 21467* --relax command line option, MMIX: MMIX-Opts. (line 19) 21468* --rename-section: Xtensa Options. (line 52) 21469* --renesas: SH Options. (line 9) 21470* --short-branches: M68HC11-Opts. (line 54) 21471* --small: SH Options. (line 9) 21472* --statistics: statistics. (line 6) 21473* --strict-direct-mode: M68HC11-Opts. (line 44) 21474* --target-align: Xtensa Options. (line 28) 21475* --text-section-literals: Xtensa Options. (line 7) 21476* --traditional-format: traditional-format. (line 6) 21477* --transform: Xtensa Options. (line 44) 21478* --underscore command line option, CRIS: CRIS-Opts. (line 15) 21479* --warn: W. (line 19) 21480* --x32 option, i386: i386-Options. (line 8) 21481* --x32 option, x86-64: i386-Options. (line 8) 21482* -1 option, VAX/VMS: VAX-Opts. (line 77) 21483* -32addr command line option, Alpha: Alpha Options. (line 57) 21484* -a: a. (line 6) 21485* -A options, i960: Options-i960. (line 6) 21486* -ac: a. (line 6) 21487* -ad: a. (line 6) 21488* -ag: a. (line 6) 21489* -ah: a. (line 6) 21490* -al: a. (line 6) 21491* -an: a. (line 6) 21492* -as: a. (line 6) 21493* -Asparclet: Sparc-Opts. (line 25) 21494* -Asparclite: Sparc-Opts. (line 25) 21495* -Av6: Sparc-Opts. (line 25) 21496* -Av8: Sparc-Opts. (line 25) 21497* -Av9: Sparc-Opts. (line 25) 21498* -Av9a: Sparc-Opts. (line 25) 21499* -b option, i960: Options-i960. (line 22) 21500* -big option, M32R: M32R-Opts. (line 35) 21501* -D: D. (line 6) 21502* -D, ignored on VAX: VAX-Opts. (line 11) 21503* -d, VAX option: VAX-Opts. (line 16) 21504* -eabi= command line option, ARM: ARM Options. (line 150) 21505* -EB command line option, ARC: ARC Options. (line 31) 21506* -EB command line option, ARM: ARM Options. (line 155) 21507* -EB option (MIPS): MIPS Opts. (line 13) 21508* -EB option, M32R: M32R-Opts. (line 39) 21509* -EL command line option, ARC: ARC Options. (line 35) 21510* -EL command line option, ARM: ARM Options. (line 159) 21511* -EL option (MIPS): MIPS Opts. (line 13) 21512* -EL option, M32R: M32R-Opts. (line 32) 21513* -f: f. (line 6) 21514* -F command line option, Alpha: Alpha Options. (line 57) 21515* -G command line option, Alpha: Alpha Options. (line 53) 21516* -g command line option, Alpha: Alpha Options. (line 47) 21517* -G option (MIPS): MIPS Opts. (line 8) 21518* -H option, VAX/VMS: VAX-Opts. (line 81) 21519* -h option, VAX/VMS: VAX-Opts. (line 45) 21520* -I PATH: I. (line 6) 21521* -ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 87) 21522* -Ip option, M32RX: M32R-Opts. (line 97) 21523* -J, ignored on VAX: VAX-Opts. (line 27) 21524* -K: K. (line 6) 21525* -k command line option, ARM: ARM Options. (line 163) 21526* -KPIC option, M32R: M32R-Opts. (line 42) 21527* -KPIC option, MIPS: MIPS Opts. (line 21) 21528* -L: L. (line 6) 21529* -l option, M680x0: M68K-Opts. (line 33) 21530* -little option, M32R: M32R-Opts. (line 27) 21531* -M: M. (line 6) 21532* -m11/03: PDP-11-Options. (line 140) 21533* -m11/04: PDP-11-Options. (line 143) 21534* -m11/05: PDP-11-Options. (line 146) 21535* -m11/10: PDP-11-Options. (line 146) 21536* -m11/15: PDP-11-Options. (line 149) 21537* -m11/20: PDP-11-Options. (line 149) 21538* -m11/21: PDP-11-Options. (line 152) 21539* -m11/23: PDP-11-Options. (line 155) 21540* -m11/24: PDP-11-Options. (line 155) 21541* -m11/34: PDP-11-Options. (line 158) 21542* -m11/34a: PDP-11-Options. (line 161) 21543* -m11/35: PDP-11-Options. (line 164) 21544* -m11/40: PDP-11-Options. (line 164) 21545* -m11/44: PDP-11-Options. (line 167) 21546* -m11/45: PDP-11-Options. (line 170) 21547* -m11/50: PDP-11-Options. (line 170) 21548* -m11/53: PDP-11-Options. (line 173) 21549* -m11/55: PDP-11-Options. (line 170) 21550* -m11/60: PDP-11-Options. (line 176) 21551* -m11/70: PDP-11-Options. (line 170) 21552* -m11/73: PDP-11-Options. (line 173) 21553* -m11/83: PDP-11-Options. (line 173) 21554* -m11/84: PDP-11-Options. (line 173) 21555* -m11/93: PDP-11-Options. (line 173) 21556* -m11/94: PDP-11-Options. (line 173) 21557* -m16c option, M16C: M32C-Opts. (line 12) 21558* -m31 option, s390: s390 Options. (line 8) 21559* -m32 option, TILE-Gx: TILE-Gx Options. (line 8) 21560* -m32bit-doubles: RX-Opts. (line 9) 21561* -m32c option, M32C: M32C-Opts. (line 9) 21562* -m32r option, M32R: M32R-Opts. (line 21) 21563* -m32rx option, M32R2: M32R-Opts. (line 17) 21564* -m32rx option, M32RX: M32R-Opts. (line 9) 21565* -m64 option, s390: s390 Options. (line 8) 21566* -m64 option, TILE-Gx: TILE-Gx Options. (line 8) 21567* -m64bit-doubles: RX-Opts. (line 15) 21568* -m68000 and related options: M68K-Opts. (line 98) 21569* -m68hc11: M68HC11-Opts. (line 9) 21570* -m68hc12: M68HC11-Opts. (line 14) 21571* -m68hcs12: M68HC11-Opts. (line 21) 21572* -m[no-]68851 command line option, M680x0: M68K-Opts. (line 21) 21573* -m[no-]68881 command line option, M680x0: M68K-Opts. (line 21) 21574* -m[no-]div command line option, M680x0: M68K-Opts. (line 21) 21575* -m[no-]emac command line option, M680x0: M68K-Opts. (line 21) 21576* -m[no-]float command line option, M680x0: M68K-Opts. (line 21) 21577* -m[no-]mac command line option, M680x0: M68K-Opts. (line 21) 21578* -m[no-]usp command line option, M680x0: M68K-Opts. (line 21) 21579* -mall: PDP-11-Options. (line 26) 21580* -mall-enabled command line option, LM32: LM32 Options. (line 30) 21581* -mall-extensions: PDP-11-Options. (line 26) 21582* -mall-opcodes command line option, AVR: AVR Options. (line 96) 21583* -mapcs-26 command line option, ARM: ARM Options. (line 122) 21584* -mapcs-32 command line option, ARM: ARM Options. (line 122) 21585* -mapcs-float command line option, ARM: ARM Options. (line 136) 21586* -mapcs-reentrant command line option, ARM: ARM Options. (line 141) 21587* -marc[5|6|7|8] command line option, ARC: ARC Options. (line 6) 21588* -march= command line option, ARM: ARM Options. (line 61) 21589* -march= command line option, M680x0: M68K-Opts. (line 8) 21590* -march= command line option, TIC6X: TIC6X Options. (line 6) 21591* -march= option, i386: i386-Options. (line 31) 21592* -march= option, s390: s390 Options. (line 25) 21593* -march= option, x86-64: i386-Options. (line 31) 21594* -matpcs command line option, ARM: ARM Options. (line 128) 21595* -mavxscalar= option, i386: i386-Options. (line 80) 21596* -mavxscalar= option, x86-64: i386-Options. (line 80) 21597* -mbarrel-shift-enabled command line option, LM32: LM32 Options. 21598 (line 12) 21599* -mbig-endian: RX-Opts. (line 20) 21600* -mbreak-enabled command line option, LM32: LM32 Options. (line 27) 21601* -mcis: PDP-11-Options. (line 32) 21602* -mconstant-gp command line option, IA-64: IA-64 Options. (line 6) 21603* -mCPU command line option, Alpha: Alpha Options. (line 6) 21604* -mcpu option, cpu: TIC54X-Opts. (line 15) 21605* -mcpu= command line option, ARM: ARM Options. (line 6) 21606* -mcpu= command line option, Blackfin: Blackfin Options. (line 6) 21607* -mcpu= command line option, M680x0: M68K-Opts. (line 14) 21608* -mcsm: PDP-11-Options. (line 43) 21609* -mdcache-enabled command line option, LM32: LM32 Options. (line 24) 21610* -mdebug command line option, Alpha: Alpha Options. (line 25) 21611* -mdivide-enabled command line option, LM32: LM32 Options. (line 9) 21612* -mdsbt command line option, TIC6X: TIC6X Options. (line 13) 21613* -me option, stderr redirect: TIC54X-Opts. (line 20) 21614* -meis: PDP-11-Options. (line 46) 21615* -merrors-to-file option, stderr redirect: TIC54X-Opts. (line 20) 21616* -mesa option, s390: s390 Options. (line 17) 21617* -mf option, far-mode: TIC54X-Opts. (line 8) 21618* -mf11: PDP-11-Options. (line 122) 21619* -mfar-mode option, far-mode: TIC54X-Opts. (line 8) 21620* -mfdpic command line option, Blackfin: Blackfin Options. (line 19) 21621* -mfis: PDP-11-Options. (line 51) 21622* -mfloat-abi= command line option, ARM: ARM Options. (line 145) 21623* -mfp-11: PDP-11-Options. (line 56) 21624* -mfpp: PDP-11-Options. (line 56) 21625* -mfpu: PDP-11-Options. (line 56) 21626* -mfpu= command line option, ARM: ARM Options. (line 76) 21627* -micache-enabled command line option, LM32: LM32 Options. (line 21) 21628* -mimplicit-it command line option, ARM: ARM Options. (line 106) 21629* -mip2022 option, IP2K: IP2K-Opts. (line 14) 21630* -mip2022ext option, IP2022: IP2K-Opts. (line 9) 21631* -mj11: PDP-11-Options. (line 126) 21632* -mka11: PDP-11-Options. (line 92) 21633* -mkb11: PDP-11-Options. (line 95) 21634* -mkd11a: PDP-11-Options. (line 98) 21635* -mkd11b: PDP-11-Options. (line 101) 21636* -mkd11d: PDP-11-Options. (line 104) 21637* -mkd11e: PDP-11-Options. (line 107) 21638* -mkd11f: PDP-11-Options. (line 110) 21639* -mkd11h: PDP-11-Options. (line 110) 21640* -mkd11k: PDP-11-Options. (line 114) 21641* -mkd11q: PDP-11-Options. (line 110) 21642* -mkd11z: PDP-11-Options. (line 118) 21643* -mkev11: PDP-11-Options. (line 51) 21644* -mlimited-eis: PDP-11-Options. (line 64) 21645* -mlittle-endian: RX-Opts. (line 26) 21646* -mlong: M68HC11-Opts. (line 32) 21647* -mlong-double: M68HC11-Opts. (line 40) 21648* -mmcu= command line option, AVR: AVR Options. (line 6) 21649* -mmfpt: PDP-11-Options. (line 70) 21650* -mmicrocode: PDP-11-Options. (line 83) 21651* -mmnemonic= option, i386: i386-Options. (line 88) 21652* -mmnemonic= option, x86-64: i386-Options. (line 88) 21653* -mmultiply-enabled command line option, LM32: LM32 Options. (line 6) 21654* -mmutiproc: PDP-11-Options. (line 73) 21655* -mmxps: PDP-11-Options. (line 77) 21656* -mnaked-reg option, i386: i386-Options. (line 100) 21657* -mnaked-reg option, x86-64: i386-Options. (line 100) 21658* -mno-cis: PDP-11-Options. (line 32) 21659* -mno-csm: PDP-11-Options. (line 43) 21660* -mno-dsbt command line option, TIC6X: TIC6X Options. (line 13) 21661* -mno-eis: PDP-11-Options. (line 46) 21662* -mno-extensions: PDP-11-Options. (line 29) 21663* -mno-fdpic command line option, Blackfin: Blackfin Options. (line 22) 21664* -mno-fis: PDP-11-Options. (line 51) 21665* -mno-fp-11: PDP-11-Options. (line 56) 21666* -mno-fpp: PDP-11-Options. (line 56) 21667* -mno-fpu: PDP-11-Options. (line 56) 21668* -mno-kev11: PDP-11-Options. (line 51) 21669* -mno-limited-eis: PDP-11-Options. (line 64) 21670* -mno-mfpt: PDP-11-Options. (line 70) 21671* -mno-microcode: PDP-11-Options. (line 83) 21672* -mno-mutiproc: PDP-11-Options. (line 73) 21673* -mno-mxps: PDP-11-Options. (line 77) 21674* -mno-pic: PDP-11-Options. (line 11) 21675* -mno-pic command line option, TIC6X: TIC6X Options. (line 36) 21676* -mno-regnames option, s390: s390 Options. (line 35) 21677* -mno-skip-bug command line option, AVR: AVR Options. (line 99) 21678* -mno-spl: PDP-11-Options. (line 80) 21679* -mno-sym32: MIPS Opts. (line 232) 21680* -mno-wrap command line option, AVR: AVR Options. (line 102) 21681* -mnopic command line option, Blackfin: Blackfin Options. (line 22) 21682* -mpic: PDP-11-Options. (line 11) 21683* -mpic command line option, TIC6X: TIC6X Options. (line 36) 21684* -mpid= command line option, TIC6X: TIC6X Options. (line 23) 21685* -mregnames option, s390: s390 Options. (line 32) 21686* -mrelax command line option, V850: V850 Options. (line 63) 21687* -mshort: M68HC11-Opts. (line 27) 21688* -mshort-double: M68HC11-Opts. (line 36) 21689* -msign-extend-enabled command line option, LM32: LM32 Options. 21690 (line 15) 21691* -msmall-data-limit: RX-Opts. (line 42) 21692* -mspl: PDP-11-Options. (line 80) 21693* -msse-check= option, i386: i386-Options. (line 70) 21694* -msse-check= option, x86-64: i386-Options. (line 70) 21695* -msse2avx option, i386: i386-Options. (line 66) 21696* -msse2avx option, x86-64: i386-Options. (line 66) 21697* -msym32: MIPS Opts. (line 232) 21698* -msyntax= option, i386: i386-Options. (line 94) 21699* -msyntax= option, x86-64: i386-Options. (line 94) 21700* -mt11: PDP-11-Options. (line 130) 21701* -mthumb command line option, ARM: ARM Options. (line 97) 21702* -mthumb-interwork command line option, ARM: ARM Options. (line 102) 21703* -mtune= option, i386: i386-Options. (line 58) 21704* -mtune= option, x86-64: i386-Options. (line 58) 21705* -muse-conventional-section-names: RX-Opts. (line 33) 21706* -muse-renesas-section-names: RX-Opts. (line 37) 21707* -muser-enabled command line option, LM32: LM32 Options. (line 18) 21708* -mv850 command line option, V850: V850 Options. (line 23) 21709* -mv850any command line option, V850: V850 Options. (line 41) 21710* -mv850e command line option, V850: V850 Options. (line 29) 21711* -mv850e1 command line option, V850: V850 Options. (line 35) 21712* -mv850e2 command line option, V850: V850 Options. (line 51) 21713* -mv850e2v3 command line option, V850: V850 Options. (line 57) 21714* -mvxworks-pic option, MIPS: MIPS Opts. (line 26) 21715* -mwarn-areg-zero option, s390: s390 Options. (line 38) 21716* -mwarn-deprecated command line option, ARM: ARM Options. (line 171) 21717* -mzarch option, s390: s390 Options. (line 17) 21718* -N command line option, CRIS: CRIS-Opts. (line 58) 21719* -nIp option, M32RX: M32R-Opts. (line 101) 21720* -no-bitinst, M32R2: M32R-Opts. (line 54) 21721* -no-ignore-parallel-conflicts option, M32RX: M32R-Opts. (line 93) 21722* -no-mdebug command line option, Alpha: Alpha Options. (line 25) 21723* -no-parallel option, M32RX: M32R-Opts. (line 51) 21724* -no-relax option, i960: Options-i960. (line 66) 21725* -no-warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. 21726 (line 79) 21727* -no-warn-unmatched-high option, M32R: M32R-Opts. (line 111) 21728* -nocpp ignored (MIPS): MIPS Opts. (line 235) 21729* -noreplace command line option, Alpha: Alpha Options. (line 40) 21730* -o: o. (line 6) 21731* -O option, M32RX: M32R-Opts. (line 59) 21732* -parallel option, M32RX: M32R-Opts. (line 46) 21733* -R: R. (line 6) 21734* -r800 command line option, Z80: Z80 Options. (line 41) 21735* -relax command line option, Alpha: Alpha Options. (line 32) 21736* -replace command line option, Alpha: Alpha Options. (line 40) 21737* -S, ignored on VAX: VAX-Opts. (line 11) 21738* -t, ignored on VAX: VAX-Opts. (line 36) 21739* -T, ignored on VAX: VAX-Opts. (line 11) 21740* -v: v. (line 6) 21741* -V, redundant on VAX: VAX-Opts. (line 22) 21742* -version: v. (line 6) 21743* -W: W. (line 11) 21744* -warn-explicit-parallel-conflicts option, M32RX: M32R-Opts. (line 65) 21745* -warn-unmatched-high option, M32R: M32R-Opts. (line 105) 21746* -Wnp option, M32RX: M32R-Opts. (line 83) 21747* -Wnuh option, M32RX: M32R-Opts. (line 117) 21748* -Wp option, M32RX: M32R-Opts. (line 75) 21749* -wsigned_overflow command line option, V850: V850 Options. (line 9) 21750* -Wuh option, M32RX: M32R-Opts. (line 114) 21751* -wunsigned_overflow command line option, V850: V850 Options. 21752 (line 16) 21753* -x command line option, MMIX: MMIX-Opts. (line 44) 21754* -z80 command line option, Z80: Z80 Options. (line 8) 21755* -z8001 command line option, Z8000: Z8000 Options. (line 6) 21756* -z8002 command line option, Z8000: Z8000 Options. (line 9) 21757* . (symbol): Dot. (line 6) 21758* .2byte directive, ARM: ARM Directives. (line 6) 21759* .4byte directive, ARM: ARM Directives. (line 6) 21760* .8byte directive, ARM: ARM Directives. (line 6) 21761* .align directive, ARM: ARM Directives. (line 11) 21762* .align directive, TILE-Gx: TILE-Gx Directives. (line 6) 21763* .align directive, TILEPro: TILEPro Directives. (line 6) 21764* .allow_suspicious_bundles directive, TILE-Gx: TILE-Gx Directives. 21765 (line 10) 21766* .allow_suspicious_bundles directive, TILEPro: TILEPro Directives. 21767 (line 10) 21768* .arch directive, ARM: ARM Directives. (line 18) 21769* .arch directive, TIC6X: TIC6X Directives. (line 10) 21770* .arch_extension directive, ARM: ARM Directives. (line 25) 21771* .arm directive, ARM: ARM Directives. (line 34) 21772* .big directive, M32RX: M32R-Directives. (line 88) 21773* .bss directive, ARM: ARM Directives. (line 42) 21774* .c6xabi_attribute directive, TIC6X: TIC6X Directives. (line 20) 21775* .cantunwind directive, ARM: ARM Directives. (line 45) 21776* .cantunwind directive, TIC6X: TIC6X Directives. (line 13) 21777* .code directive, ARM: ARM Directives. (line 49) 21778* .cpu directive, ARM: ARM Directives. (line 53) 21779* .dn and .qn directives, ARM: ARM Directives. (line 60) 21780* .eabi_attribute directive, ARM: ARM Directives. (line 83) 21781* .ehtype directive, TIC6X: TIC6X Directives. (line 31) 21782* .endp directive, TIC6X: TIC6X Directives. (line 34) 21783* .even directive, ARM: ARM Directives. (line 111) 21784* .extend directive, ARM: ARM Directives. (line 114) 21785* .fnend directive, ARM: ARM Directives. (line 120) 21786* .fnstart directive, ARM: ARM Directives. (line 129) 21787* .force_thumb directive, ARM: ARM Directives. (line 132) 21788* .fpu directive, ARM: ARM Directives. (line 136) 21789* .global: MIPS insn. (line 12) 21790* .handlerdata directive, ARM: ARM Directives. (line 140) 21791* .handlerdata directive, TIC6X: TIC6X Directives. (line 39) 21792* .insn: MIPS insn. (line 6) 21793* .insn directive, s390: s390 Directives. (line 11) 21794* .inst directive, ARM: ARM Directives. (line 149) 21795* .ldouble directive, ARM: ARM Directives. (line 114) 21796* .little directive, M32RX: M32R-Directives. (line 82) 21797* .long directive, s390: s390 Directives. (line 16) 21798* .ltorg directive, ARM: ARM Directives. (line 159) 21799* .ltorg directive, s390: s390 Directives. (line 88) 21800* .m32r directive, M32R: M32R-Directives. (line 66) 21801* .m32r2 directive, M32R2: M32R-Directives. (line 77) 21802* .m32rx directive, M32RX: M32R-Directives. (line 72) 21803* .machine directive, s390: s390 Directives. (line 93) 21804* .movsp directive, ARM: ARM Directives. (line 173) 21805* .no_pointers directive, XStormy16: XStormy16 Directives. 21806 (line 14) 21807* .nocmp directive, TIC6X: TIC6X Directives. (line 48) 21808* .o: Object. (line 6) 21809* .object_arch directive, ARM: ARM Directives. (line 178) 21810* .packed directive, ARM: ARM Directives. (line 184) 21811* .pad directive, ARM: ARM Directives. (line 37) 21812* .param on HPPA: HPPA Directives. (line 19) 21813* .personality directive, ARM: ARM Directives. (line 194) 21814* .personality directive, TIC6X: TIC6X Directives. (line 56) 21815* .personalityindex directive, ARM: ARM Directives. (line 197) 21816* .personalityindex directive, TIC6X: TIC6X Directives. (line 52) 21817* .pool directive, ARM: ARM Directives. (line 201) 21818* .quad directive, s390: s390 Directives. (line 16) 21819* .req directive, ARM: ARM Directives. (line 204) 21820* .require_canonical_reg_names directive, TILE-Gx: TILE-Gx Directives. 21821 (line 19) 21822* .require_canonical_reg_names directive, TILEPro: TILEPro Directives. 21823 (line 19) 21824* .save directive, ARM: ARM Directives. (line 209) 21825* .scomm directive, TIC6X: TIC6X Directives. (line 59) 21826* .secrel32 directive, ARM: ARM Directives. (line 247) 21827* .set arch=CPU: MIPS ISA. (line 18) 21828* .set autoextend: MIPS autoextend. (line 6) 21829* .set doublefloat: MIPS floating-point. (line 12) 21830* .set dsp: MIPS ASE instruction generation overrides. 21831 (line 21) 21832* .set dspr2: MIPS ASE instruction generation overrides. 21833 (line 26) 21834* .set hardfloat: MIPS floating-point. (line 6) 21835* .set insn32: MIPS assembly options. 21836 (line 6) 21837* .set mcu: MIPS ASE instruction generation overrides. 21838 (line 37) 21839* .set mdmx: MIPS ASE instruction generation overrides. 21840 (line 16) 21841* .set mips3d: MIPS ASE instruction generation overrides. 21842 (line 6) 21843* .set mipsN: MIPS ISA. (line 6) 21844* .set mt: MIPS ASE instruction generation overrides. 21845 (line 32) 21846* .set noautoextend: MIPS autoextend. (line 6) 21847* .set nodsp: MIPS ASE instruction generation overrides. 21848 (line 21) 21849* .set nodspr2: MIPS ASE instruction generation overrides. 21850 (line 26) 21851* .set noinsn32: MIPS assembly options. 21852 (line 6) 21853* .set nomcu: MIPS ASE instruction generation overrides. 21854 (line 37) 21855* .set nomdmx: MIPS ASE instruction generation overrides. 21856 (line 16) 21857* .set nomips3d: MIPS ASE instruction generation overrides. 21858 (line 6) 21859* .set nomt: MIPS ASE instruction generation overrides. 21860 (line 32) 21861* .set nosmartmips: MIPS ASE instruction generation overrides. 21862 (line 11) 21863* .set nosym32: MIPS symbol sizes. (line 6) 21864* .set pop: MIPS option stack. (line 6) 21865* .set push: MIPS option stack. (line 6) 21866* .set singlefloat: MIPS floating-point. (line 12) 21867* .set smartmips: MIPS ASE instruction generation overrides. 21868 (line 11) 21869* .set softfloat: MIPS floating-point. (line 6) 21870* .set sym32: MIPS symbol sizes. (line 6) 21871* .setfp directive, ARM: ARM Directives. (line 233) 21872* .short directive, s390: s390 Directives. (line 16) 21873* .syntax directive, ARM: ARM Directives. (line 252) 21874* .thumb directive, ARM: ARM Directives. (line 256) 21875* .thumb_func directive, ARM: ARM Directives. (line 259) 21876* .thumb_set directive, ARM: ARM Directives. (line 270) 21877* .tlsdescseq directive, ARM: ARM Directives. (line 277) 21878* .unreq directive, ARM: ARM Directives. (line 282) 21879* .unwind_raw directive, ARM: ARM Directives. (line 293) 21880* .v850 directive, V850: V850 Directives. (line 14) 21881* .v850e directive, V850: V850 Directives. (line 20) 21882* .v850e1 directive, V850: V850 Directives. (line 26) 21883* .v850e2 directive, V850: V850 Directives. (line 32) 21884* .v850e2v3 directive, V850: V850 Directives. (line 38) 21885* .vsave directive, ARM: ARM Directives. (line 300) 21886* .z8001: Z8000 Directives. (line 11) 21887* .z8002: Z8000 Directives. (line 15) 21888* 16-bit code, i386: i386-16bit. (line 6) 21889* 16bit_pointers directive, XStormy16: XStormy16 Directives. 21890 (line 6) 21891* 2byte directive, ARC: ARC Directives. (line 9) 21892* 32bit_pointers directive, XStormy16: XStormy16 Directives. 21893 (line 10) 21894* 3byte directive, ARC: ARC Directives. (line 12) 21895* 3DNow!, i386: i386-SIMD. (line 6) 21896* 3DNow!, x86-64: i386-SIMD. (line 6) 21897* 430 support: MSP430-Dependent. (line 6) 21898* 4byte directive, ARC: ARC Directives. (line 15) 21899* : (label): Statements. (line 31) 21900* @hi pseudo-op, XStormy16: XStormy16 Opcodes. (line 21) 21901* @lo pseudo-op, XStormy16: XStormy16 Opcodes. (line 10) 21902* @word modifier, D10V: D10V-Word. (line 6) 21903* \" (doublequote character): Strings. (line 43) 21904* \\ (\ character): Strings. (line 40) 21905* \b (backspace character): Strings. (line 15) 21906* \DDD (octal character code): Strings. (line 30) 21907* \f (formfeed character): Strings. (line 18) 21908* \n (newline character): Strings. (line 21) 21909* \r (carriage return character): Strings. (line 24) 21910* \t (tab): Strings. (line 27) 21911* \XD... (hex character code): Strings. (line 36) 21912* _ opcode prefix: Xtensa Opcodes. (line 9) 21913* a.out: Object. (line 6) 21914* a.out symbol attributes: a.out Symbols. (line 6) 21915* A_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 21916* ABI options, SH64: SH64 Options. (line 29) 21917* ABORT directive: ABORT (COFF). (line 6) 21918* abort directive: Abort. (line 6) 21919* absolute section: Ld Sections. (line 29) 21920* absolute-literals directive: Absolute Literals Directive. 21921 (line 6) 21922* ADDI instructions, relaxation: Xtensa Immediate Relaxation. 21923 (line 43) 21924* addition, permitted arguments: Infix Ops. (line 44) 21925* addresses: Expressions. (line 6) 21926* addresses, format of: Secs Background. (line 68) 21927* addressing modes, D10V: D10V-Addressing. (line 6) 21928* addressing modes, D30V: D30V-Addressing. (line 6) 21929* addressing modes, H8/300: H8/300-Addressing. (line 6) 21930* addressing modes, M680x0: M68K-Syntax. (line 21) 21931* addressing modes, M68HC11: M68HC11-Syntax. (line 30) 21932* addressing modes, SH: SH-Addressing. (line 6) 21933* addressing modes, SH64: SH64-Addressing. (line 6) 21934* addressing modes, Z8000: Z8000-Addressing. (line 6) 21935* ADR reg,<label> pseudo op, ARM: ARM Opcodes. (line 25) 21936* ADRL reg,<label> pseudo op, ARM: ARM Opcodes. (line 35) 21937* advancing location counter: Org. (line 6) 21938* align directive: Align. (line 6) 21939* align directive, SPARC: Sparc-Directives. (line 9) 21940* align directive, TIC54X: TIC54X-Directives. (line 6) 21941* alignment for NEON instructions: ARM-Neon-Alignment. (line 6) 21942* alignment of branch targets: Xtensa Automatic Alignment. 21943 (line 6) 21944* alignment of LOOP instructions: Xtensa Automatic Alignment. 21945 (line 6) 21946* Alpha floating point (IEEE): Alpha Floating Point. 21947 (line 6) 21948* Alpha line comment character: Alpha-Chars. (line 6) 21949* Alpha line separator: Alpha-Chars. (line 11) 21950* Alpha notes: Alpha Notes. (line 6) 21951* Alpha options: Alpha Options. (line 6) 21952* Alpha registers: Alpha-Regs. (line 6) 21953* Alpha relocations: Alpha-Relocs. (line 6) 21954* Alpha support: Alpha-Dependent. (line 6) 21955* Alpha Syntax: Alpha Options. (line 61) 21956* Alpha-only directives: Alpha Directives. (line 10) 21957* altered difference tables: Word. (line 12) 21958* alternate syntax for the 680x0: M68K-Moto-Syntax. (line 6) 21959* ARC floating point (IEEE): ARC Floating Point. (line 6) 21960* ARC line comment character: ARC-Chars. (line 6) 21961* ARC line separator: ARC-Chars. (line 12) 21962* ARC machine directives: ARC Directives. (line 6) 21963* ARC opcodes: ARC Opcodes. (line 6) 21964* ARC options (none): ARC Options. (line 6) 21965* ARC register names: ARC-Regs. (line 6) 21966* ARC support: ARC-Dependent. (line 6) 21967* arc5 arc5, ARC: ARC Options. (line 10) 21968* arc6 arc6, ARC: ARC Options. (line 13) 21969* arc7 arc7, ARC: ARC Options. (line 21) 21970* arc8 arc8, ARC: ARC Options. (line 24) 21971* arch directive, i386: i386-Arch. (line 6) 21972* arch directive, M680x0: M68K-Directives. (line 22) 21973* arch directive, x86-64: i386-Arch. (line 6) 21974* architecture options, i960: Options-i960. (line 6) 21975* architecture options, IP2022: IP2K-Opts. (line 9) 21976* architecture options, IP2K: IP2K-Opts. (line 14) 21977* architecture options, M16C: M32C-Opts. (line 12) 21978* architecture options, M32C: M32C-Opts. (line 9) 21979* architecture options, M32R: M32R-Opts. (line 21) 21980* architecture options, M32R2: M32R-Opts. (line 17) 21981* architecture options, M32RX: M32R-Opts. (line 9) 21982* architecture options, M680x0: M68K-Opts. (line 98) 21983* Architecture variant option, CRIS: CRIS-Opts. (line 34) 21984* architectures, PowerPC: PowerPC-Opts. (line 6) 21985* architectures, SCORE: SCORE-Opts. (line 6) 21986* architectures, SPARC: Sparc-Opts. (line 6) 21987* arguments for addition: Infix Ops. (line 44) 21988* arguments for subtraction: Infix Ops. (line 49) 21989* arguments in expressions: Arguments. (line 6) 21990* arithmetic functions: Operators. (line 6) 21991* arithmetic operands: Arguments. (line 6) 21992* ARM data relocations: ARM-Relocations. (line 6) 21993* ARM floating point (IEEE): ARM Floating Point. (line 6) 21994* ARM identifiers: ARM-Chars. (line 19) 21995* ARM immediate character: ARM-Chars. (line 17) 21996* ARM line comment character: ARM-Chars. (line 6) 21997* ARM line separator: ARM-Chars. (line 14) 21998* ARM machine directives: ARM Directives. (line 6) 21999* ARM opcodes: ARM Opcodes. (line 6) 22000* ARM options (none): ARM Options. (line 6) 22001* ARM register names: ARM-Regs. (line 6) 22002* ARM support: ARM-Dependent. (line 6) 22003* ascii directive: Ascii. (line 6) 22004* asciz directive: Asciz. (line 6) 22005* asg directive, TIC54X: TIC54X-Directives. (line 20) 22006* assembler bugs, reporting: Bug Reporting. (line 6) 22007* assembler crash: Bug Criteria. (line 9) 22008* assembler directive .3byte, RX: RX-Directives. (line 9) 22009* assembler directive .arch, CRIS: CRIS-Pseudos. (line 45) 22010* assembler directive .dword, CRIS: CRIS-Pseudos. (line 12) 22011* assembler directive .far, M68HC11: M68HC11-Directives. (line 20) 22012* assembler directive .interrupt, M68HC11: M68HC11-Directives. 22013 (line 26) 22014* assembler directive .mode, M68HC11: M68HC11-Directives. (line 16) 22015* assembler directive .relax, M68HC11: M68HC11-Directives. (line 10) 22016* assembler directive .syntax, CRIS: CRIS-Pseudos. (line 17) 22017* assembler directive .xrefb, M68HC11: M68HC11-Directives. (line 31) 22018* assembler directive BSPEC, MMIX: MMIX-Pseudos. (line 131) 22019* assembler directive BYTE, MMIX: MMIX-Pseudos. (line 97) 22020* assembler directive ESPEC, MMIX: MMIX-Pseudos. (line 131) 22021* assembler directive GREG, MMIX: MMIX-Pseudos. (line 50) 22022* assembler directive IS, MMIX: MMIX-Pseudos. (line 42) 22023* assembler directive LOC, MMIX: MMIX-Pseudos. (line 7) 22024* assembler directive LOCAL, MMIX: MMIX-Pseudos. (line 28) 22025* assembler directive OCTA, MMIX: MMIX-Pseudos. (line 108) 22026* assembler directive PREFIX, MMIX: MMIX-Pseudos. (line 120) 22027* assembler directive TETRA, MMIX: MMIX-Pseudos. (line 108) 22028* assembler directive WYDE, MMIX: MMIX-Pseudos. (line 108) 22029* assembler directives, CRIS: CRIS-Pseudos. (line 6) 22030* assembler directives, M68HC11: M68HC11-Directives. (line 6) 22031* assembler directives, M68HC12: M68HC11-Directives. (line 6) 22032* assembler directives, MMIX: MMIX-Pseudos. (line 6) 22033* assembler directives, RX: RX-Directives. (line 6) 22034* assembler internal logic error: As Sections. (line 13) 22035* assembler version: v. (line 6) 22036* assembler, and linker: Secs Background. (line 10) 22037* assembly listings, enabling: a. (line 6) 22038* assigning values to symbols <1>: Equ. (line 6) 22039* assigning values to symbols: Setting Symbols. (line 6) 22040* atmp directive, i860: Directives-i860. (line 16) 22041* att_syntax pseudo op, i386: i386-Variations. (line 6) 22042* att_syntax pseudo op, x86-64: i386-Variations. (line 6) 22043* attributes, symbol: Symbol Attributes. (line 6) 22044* auxiliary attributes, COFF symbols: COFF Symbols. (line 19) 22045* auxiliary symbol information, COFF: Dim. (line 6) 22046* Av7: Sparc-Opts. (line 25) 22047* AVR line comment character: AVR-Chars. (line 6) 22048* AVR line separator: AVR-Chars. (line 14) 22049* AVR modifiers: AVR-Modifiers. (line 6) 22050* AVR opcode summary: AVR Opcodes. (line 6) 22051* AVR options (none): AVR Options. (line 6) 22052* AVR register names: AVR-Regs. (line 6) 22053* AVR support: AVR-Dependent. (line 6) 22054* backslash (\\): Strings. (line 40) 22055* backspace (\b): Strings. (line 15) 22056* balign directive: Balign. (line 6) 22057* balignl directive: Balign. (line 27) 22058* balignw directive: Balign. (line 27) 22059* bes directive, TIC54X: TIC54X-Directives. (line 196) 22060* big endian output, MIPS: Overview. (line 694) 22061* big endian output, PJ: Overview. (line 601) 22062* big-endian output, MIPS: MIPS Opts. (line 13) 22063* big-endian output, TIC6X: TIC6X Options. (line 46) 22064* bignums: Bignums. (line 6) 22065* binary constants, TIC54X: TIC54X-Constants. (line 8) 22066* binary files, including: Incbin. (line 6) 22067* binary integers: Integers. (line 6) 22068* bit names, IA-64: IA-64-Bits. (line 6) 22069* bitfields, not supported on VAX: VAX-no. (line 6) 22070* Blackfin directives: Blackfin Directives. (line 6) 22071* Blackfin options (none): Blackfin Options. (line 6) 22072* Blackfin support: Blackfin-Dependent. (line 6) 22073* Blackfin syntax: Blackfin Syntax. (line 6) 22074* block: Z8000 Directives. (line 55) 22075* BMI, i386: i386-BMI. (line 6) 22076* BMI, x86-64: i386-BMI. (line 6) 22077* branch improvement, M680x0: M68K-Branch. (line 6) 22078* branch improvement, M68HC11: M68HC11-Branch. (line 6) 22079* branch improvement, VAX: VAX-branch. (line 6) 22080* branch instructions, relaxation: Xtensa Branch Relaxation. 22081 (line 6) 22082* branch recording, i960: Options-i960. (line 22) 22083* branch statistics table, i960: Options-i960. (line 40) 22084* branch target alignment: Xtensa Automatic Alignment. 22085 (line 6) 22086* break directive, TIC54X: TIC54X-Directives. (line 143) 22087* BSD syntax: PDP-11-Syntax. (line 6) 22088* bss directive, i960: Directives-i960. (line 6) 22089* bss directive, TIC54X: TIC54X-Directives. (line 29) 22090* bss section <1>: bss. (line 6) 22091* bss section: Ld Sections. (line 20) 22092* bug criteria: Bug Criteria. (line 6) 22093* bug reports: Bug Reporting. (line 6) 22094* bugs in assembler: Reporting Bugs. (line 6) 22095* Built-in symbols, CRIS: CRIS-Symbols. (line 6) 22096* builtin math functions, TIC54X: TIC54X-Builtins. (line 6) 22097* builtin subsym functions, TIC54X: TIC54X-Macros. (line 16) 22098* bus lock prefixes, i386: i386-Prefixes. (line 36) 22099* bval: Z8000 Directives. (line 30) 22100* byte directive: Byte. (line 6) 22101* byte directive, TIC54X: TIC54X-Directives. (line 36) 22102* C54XDSP_DIR environment variable, TIC54X: TIC54X-Env. (line 6) 22103* c_mode directive, TIC54X: TIC54X-Directives. (line 51) 22104* call instructions, i386: i386-Mnemonics. (line 56) 22105* call instructions, relaxation: Xtensa Call Relaxation. 22106 (line 6) 22107* call instructions, x86-64: i386-Mnemonics. (line 56) 22108* callj, i960 pseudo-opcode: callj-i960. (line 6) 22109* carriage return (\r): Strings. (line 24) 22110* case sensitivity, Z80: Z80-Case. (line 6) 22111* cfi_endproc directive: CFI directives. (line 26) 22112* cfi_sections directive: CFI directives. (line 6) 22113* cfi_startproc directive: CFI directives. (line 16) 22114* char directive, TIC54X: TIC54X-Directives. (line 36) 22115* character constant, Z80: Z80-Chars. (line 20) 22116* character constants: Characters. (line 6) 22117* character escape codes: Strings. (line 15) 22118* character escapes, Z80: Z80-Chars. (line 18) 22119* character, single: Chars. (line 6) 22120* characters used in symbols: Symbol Intro. (line 6) 22121* clink directive, TIC54X: TIC54X-Directives. (line 45) 22122* code16 directive, i386: i386-16bit. (line 6) 22123* code16gcc directive, i386: i386-16bit. (line 6) 22124* code32 directive, i386: i386-16bit. (line 6) 22125* code64 directive, i386: i386-16bit. (line 6) 22126* code64 directive, x86-64: i386-16bit. (line 6) 22127* COFF auxiliary symbol information: Dim. (line 6) 22128* COFF structure debugging: Tag. (line 6) 22129* COFF symbol attributes: COFF Symbols. (line 6) 22130* COFF symbol descriptor: Desc. (line 6) 22131* COFF symbol storage class: Scl. (line 6) 22132* COFF symbol type: Type. (line 11) 22133* COFF symbols, debugging: Def. (line 6) 22134* COFF value attribute: Val. (line 6) 22135* COMDAT: Linkonce. (line 6) 22136* comm directive: Comm. (line 6) 22137* command line conventions: Command Line. (line 6) 22138* command line options, V850: V850 Options. (line 9) 22139* command-line options ignored, VAX: VAX-Opts. (line 6) 22140* comment character, XStormy16: XStormy16-Chars. (line 11) 22141* comments: Comments. (line 6) 22142* comments, M680x0: M68K-Chars. (line 6) 22143* comments, removed by preprocessor: Preprocessing. (line 11) 22144* common directive, SPARC: Sparc-Directives. (line 12) 22145* common sections: Linkonce. (line 6) 22146* common variable storage: bss. (line 6) 22147* compare and jump expansions, i960: Compare-and-branch-i960. 22148 (line 13) 22149* compare/branch instructions, i960: Compare-and-branch-i960. 22150 (line 6) 22151* comparison expressions: Infix Ops. (line 55) 22152* conditional assembly: If. (line 6) 22153* constant, single character: Chars. (line 6) 22154* constants: Constants. (line 6) 22155* constants, bignum: Bignums. (line 6) 22156* constants, character: Characters. (line 6) 22157* constants, converted by preprocessor: Preprocessing. (line 14) 22158* constants, floating point: Flonums. (line 6) 22159* constants, integer: Integers. (line 6) 22160* constants, number: Numbers. (line 6) 22161* constants, Sparc: Sparc-Constants. (line 6) 22162* constants, string: Strings. (line 6) 22163* constants, TIC54X: TIC54X-Constants. (line 6) 22164* conversion instructions, i386: i386-Mnemonics. (line 37) 22165* conversion instructions, x86-64: i386-Mnemonics. (line 37) 22166* coprocessor wait, i386: i386-Prefixes. (line 40) 22167* copy directive, TIC54X: TIC54X-Directives. (line 54) 22168* cpu directive, M680x0: M68K-Directives. (line 30) 22169* CR16 line comment character: CR16-Chars. (line 6) 22170* CR16 line separator: CR16-Chars. (line 13) 22171* CR16 Operand Qualifiers: CR16 Operand Qualifiers. 22172 (line 6) 22173* CR16 support: CR16-Dependent. (line 6) 22174* crash of assembler: Bug Criteria. (line 9) 22175* CRIS --emulation=crisaout command line option: CRIS-Opts. (line 9) 22176* CRIS --emulation=criself command line option: CRIS-Opts. (line 9) 22177* CRIS --march=ARCHITECTURE command line option: CRIS-Opts. (line 34) 22178* CRIS --mul-bug-abort command line option: CRIS-Opts. (line 62) 22179* CRIS --no-mul-bug-abort command line option: CRIS-Opts. (line 62) 22180* CRIS --no-underscore command line option: CRIS-Opts. (line 15) 22181* CRIS --pic command line option: CRIS-Opts. (line 27) 22182* CRIS --underscore command line option: CRIS-Opts. (line 15) 22183* CRIS -N command line option: CRIS-Opts. (line 58) 22184* CRIS architecture variant option: CRIS-Opts. (line 34) 22185* CRIS assembler directive .arch: CRIS-Pseudos. (line 45) 22186* CRIS assembler directive .dword: CRIS-Pseudos. (line 12) 22187* CRIS assembler directive .syntax: CRIS-Pseudos. (line 17) 22188* CRIS assembler directives: CRIS-Pseudos. (line 6) 22189* CRIS built-in symbols: CRIS-Symbols. (line 6) 22190* CRIS instruction expansion: CRIS-Expand. (line 6) 22191* CRIS line comment characters: CRIS-Chars. (line 6) 22192* CRIS options: CRIS-Opts. (line 6) 22193* CRIS position-independent code: CRIS-Opts. (line 27) 22194* CRIS pseudo-op .arch: CRIS-Pseudos. (line 45) 22195* CRIS pseudo-op .dword: CRIS-Pseudos. (line 12) 22196* CRIS pseudo-op .syntax: CRIS-Pseudos. (line 17) 22197* CRIS pseudo-ops: CRIS-Pseudos. (line 6) 22198* CRIS register names: CRIS-Regs. (line 6) 22199* CRIS support: CRIS-Dependent. (line 6) 22200* CRIS symbols in position-independent code: CRIS-Pic. (line 6) 22201* ctbp register, V850: V850-Regs. (line 131) 22202* ctoff pseudo-op, V850: V850 Opcodes. (line 111) 22203* ctpc register, V850: V850-Regs. (line 119) 22204* ctpsw register, V850: V850-Regs. (line 122) 22205* current address: Dot. (line 6) 22206* current address, advancing: Org. (line 6) 22207* D10V @word modifier: D10V-Word. (line 6) 22208* D10V addressing modes: D10V-Addressing. (line 6) 22209* D10V floating point: D10V-Float. (line 6) 22210* D10V line comment character: D10V-Chars. (line 6) 22211* D10V opcode summary: D10V-Opcodes. (line 6) 22212* D10V optimization: Overview. (line 470) 22213* D10V options: D10V-Opts. (line 6) 22214* D10V registers: D10V-Regs. (line 6) 22215* D10V size modifiers: D10V-Size. (line 6) 22216* D10V sub-instruction ordering: D10V-Chars. (line 14) 22217* D10V sub-instructions: D10V-Subs. (line 6) 22218* D10V support: D10V-Dependent. (line 6) 22219* D10V syntax: D10V-Syntax. (line 6) 22220* D30V addressing modes: D30V-Addressing. (line 6) 22221* D30V floating point: D30V-Float. (line 6) 22222* D30V Guarded Execution: D30V-Guarded. (line 6) 22223* D30V line comment character: D30V-Chars. (line 6) 22224* D30V nops: Overview. (line 478) 22225* D30V nops after 32-bit multiply: Overview. (line 481) 22226* D30V opcode summary: D30V-Opcodes. (line 6) 22227* D30V optimization: Overview. (line 475) 22228* D30V options: D30V-Opts. (line 6) 22229* D30V registers: D30V-Regs. (line 6) 22230* D30V size modifiers: D30V-Size. (line 6) 22231* D30V sub-instruction ordering: D30V-Chars. (line 14) 22232* D30V sub-instructions: D30V-Subs. (line 6) 22233* D30V support: D30V-Dependent. (line 6) 22234* D30V syntax: D30V-Syntax. (line 6) 22235* data alignment on SPARC: Sparc-Aligned-Data. (line 6) 22236* data and text sections, joining: R. (line 6) 22237* data directive: Data. (line 6) 22238* data directive, TIC54X: TIC54X-Directives. (line 61) 22239* data relocations, ARM: ARM-Relocations. (line 6) 22240* data section: Ld Sections. (line 9) 22241* data1 directive, M680x0: M68K-Directives. (line 9) 22242* data2 directive, M680x0: M68K-Directives. (line 12) 22243* datalabel, SH64: SH64-Addressing. (line 16) 22244* dbpc register, V850: V850-Regs. (line 125) 22245* dbpsw register, V850: V850-Regs. (line 128) 22246* debuggers, and symbol order: Symbols. (line 10) 22247* debugging COFF symbols: Def. (line 6) 22248* DEC syntax: PDP-11-Syntax. (line 6) 22249* decimal integers: Integers. (line 12) 22250* def directive: Def. (line 6) 22251* def directive, TIC54X: TIC54X-Directives. (line 103) 22252* density instructions: Density Instructions. 22253 (line 6) 22254* dependency tracking: MD. (line 6) 22255* deprecated directives: Deprecated. (line 6) 22256* desc directive: Desc. (line 6) 22257* descriptor, of a.out symbol: Symbol Desc. (line 6) 22258* dfloat directive, VAX: VAX-directives. (line 10) 22259* difference tables altered: Word. (line 12) 22260* difference tables, warning: K. (line 6) 22261* differences, mmixal: MMIX-mmixal. (line 6) 22262* dim directive: Dim. (line 6) 22263* directives and instructions: Statements. (line 20) 22264* directives for PowerPC: PowerPC-Pseudo. (line 6) 22265* directives for SCORE: SCORE-Pseudo. (line 6) 22266* directives, Blackfin: Blackfin Directives. (line 6) 22267* directives, M32R: M32R-Directives. (line 6) 22268* directives, M680x0: M68K-Directives. (line 6) 22269* directives, machine independent: Pseudo Ops. (line 6) 22270* directives, Xtensa: Xtensa Directives. (line 6) 22271* directives, Z8000: Z8000 Directives. (line 6) 22272* Disable floating-point instructions: MIPS floating-point. (line 6) 22273* Disable single-precision floating-point operations: MIPS floating-point. 22274 (line 12) 22275* displacement sizing character, VAX: VAX-operands. (line 12) 22276* dollar local symbols: Symbol Names. (line 105) 22277* dot (symbol): Dot. (line 6) 22278* double directive: Double. (line 6) 22279* double directive, i386: i386-Float. (line 14) 22280* double directive, M680x0: M68K-Float. (line 14) 22281* double directive, M68HC11: M68HC11-Float. (line 14) 22282* double directive, RX: RX-Float. (line 11) 22283* double directive, TIC54X: TIC54X-Directives. (line 64) 22284* double directive, VAX: VAX-float. (line 15) 22285* double directive, x86-64: i386-Float. (line 14) 22286* doublequote (\"): Strings. (line 43) 22287* drlist directive, TIC54X: TIC54X-Directives. (line 73) 22288* drnolist directive, TIC54X: TIC54X-Directives. (line 73) 22289* dual directive, i860: Directives-i860. (line 6) 22290* ECOFF sections: MIPS Object. (line 6) 22291* ecr register, V850: V850-Regs. (line 113) 22292* eight-byte integer: Quad. (line 9) 22293* eipc register, V850: V850-Regs. (line 101) 22294* eipsw register, V850: V850-Regs. (line 104) 22295* eject directive: Eject. (line 6) 22296* ELF symbol type: Type. (line 22) 22297* else directive: Else. (line 6) 22298* elseif directive: Elseif. (line 6) 22299* empty expressions: Empty Exprs. (line 6) 22300* emsg directive, TIC54X: TIC54X-Directives. (line 77) 22301* emulation: Overview. (line 820) 22302* encoding options, i386: i386-Mnemonics. (line 32) 22303* encoding options, x86-64: i386-Mnemonics. (line 32) 22304* end directive: End. (line 6) 22305* enddual directive, i860: Directives-i860. (line 11) 22306* endef directive: Endef. (line 6) 22307* endfunc directive: Endfunc. (line 6) 22308* endianness, MIPS: Overview. (line 694) 22309* endianness, PJ: Overview. (line 601) 22310* endif directive: Endif. (line 6) 22311* endloop directive, TIC54X: TIC54X-Directives. (line 143) 22312* endm directive: Macro. (line 138) 22313* endm directive, TIC54X: TIC54X-Directives. (line 153) 22314* endstruct directive, TIC54X: TIC54X-Directives. (line 216) 22315* endunion directive, TIC54X: TIC54X-Directives. (line 250) 22316* environment settings, TIC54X: TIC54X-Env. (line 6) 22317* EOF, newline must precede: Statements. (line 14) 22318* ep register, V850: V850-Regs. (line 95) 22319* equ directive: Equ. (line 6) 22320* equ directive, TIC54X: TIC54X-Directives. (line 191) 22321* equiv directive: Equiv. (line 6) 22322* eqv directive: Eqv. (line 6) 22323* err directive: Err. (line 6) 22324* error directive: Error. (line 6) 22325* error messages: Errors. (line 6) 22326* error on valid input: Bug Criteria. (line 12) 22327* errors, caused by warnings: W. (line 16) 22328* errors, continuing after: Z. (line 6) 22329* ESA/390 floating point (IEEE): ESA/390 Floating Point. 22330 (line 6) 22331* ESA/390 support: ESA/390-Dependent. (line 6) 22332* ESA/390 Syntax: ESA/390 Options. (line 8) 22333* ESA/390-only directives: ESA/390 Directives. (line 12) 22334* escape codes, character: Strings. (line 15) 22335* eval directive, TIC54X: TIC54X-Directives. (line 24) 22336* even: Z8000 Directives. (line 58) 22337* even directive, M680x0: M68K-Directives. (line 15) 22338* even directive, TIC54X: TIC54X-Directives. (line 6) 22339* exitm directive: Macro. (line 141) 22340* expr (internal section): As Sections. (line 17) 22341* expression arguments: Arguments. (line 6) 22342* expressions: Expressions. (line 6) 22343* expressions, comparison: Infix Ops. (line 55) 22344* expressions, empty: Empty Exprs. (line 6) 22345* expressions, integer: Integer Exprs. (line 6) 22346* extAuxRegister directive, ARC: ARC Directives. (line 18) 22347* extCondCode directive, ARC: ARC Directives. (line 41) 22348* extCoreRegister directive, ARC: ARC Directives. (line 53) 22349* extend directive M680x0: M68K-Float. (line 17) 22350* extend directive M68HC11: M68HC11-Float. (line 17) 22351* extended directive, i960: Directives-i960. (line 13) 22352* extern directive: Extern. (line 6) 22353* extInstruction directive, ARC: ARC Directives. (line 78) 22354* fail directive: Fail. (line 6) 22355* far_mode directive, TIC54X: TIC54X-Directives. (line 82) 22356* faster processing (-f): f. (line 6) 22357* fatal signal: Bug Criteria. (line 9) 22358* fclist directive, TIC54X: TIC54X-Directives. (line 87) 22359* fcnolist directive, TIC54X: TIC54X-Directives. (line 87) 22360* fepc register, V850: V850-Regs. (line 107) 22361* fepsw register, V850: V850-Regs. (line 110) 22362* ffloat directive, VAX: VAX-directives. (line 14) 22363* field directive, TIC54X: TIC54X-Directives. (line 91) 22364* file directive: File. (line 6) 22365* file directive, MSP 430: MSP430 Directives. (line 6) 22366* file name, logical: File. (line 13) 22367* files, including: Include. (line 6) 22368* files, input: Input Files. (line 6) 22369* fill directive: Fill. (line 6) 22370* filling memory <1>: Space. (line 6) 22371* filling memory: Skip. (line 6) 22372* FLIX syntax: Xtensa Syntax. (line 6) 22373* float directive: Float. (line 6) 22374* float directive, i386: i386-Float. (line 14) 22375* float directive, M680x0: M68K-Float. (line 11) 22376* float directive, M68HC11: M68HC11-Float. (line 11) 22377* float directive, RX: RX-Float. (line 8) 22378* float directive, TIC54X: TIC54X-Directives. (line 64) 22379* float directive, VAX: VAX-float. (line 15) 22380* float directive, x86-64: i386-Float. (line 14) 22381* floating point numbers: Flonums. (line 6) 22382* floating point numbers (double): Double. (line 6) 22383* floating point numbers (single) <1>: Single. (line 6) 22384* floating point numbers (single): Float. (line 6) 22385* floating point, Alpha (IEEE): Alpha Floating Point. 22386 (line 6) 22387* floating point, ARC (IEEE): ARC Floating Point. (line 6) 22388* floating point, ARM (IEEE): ARM Floating Point. (line 6) 22389* floating point, D10V: D10V-Float. (line 6) 22390* floating point, D30V: D30V-Float. (line 6) 22391* floating point, ESA/390 (IEEE): ESA/390 Floating Point. 22392 (line 6) 22393* floating point, H8/300 (IEEE): H8/300 Floating Point. 22394 (line 6) 22395* floating point, HPPA (IEEE): HPPA Floating Point. (line 6) 22396* floating point, i386: i386-Float. (line 6) 22397* floating point, i960 (IEEE): Floating Point-i960. (line 6) 22398* floating point, M680x0: M68K-Float. (line 6) 22399* floating point, M68HC11: M68HC11-Float. (line 6) 22400* floating point, MSP 430 (IEEE): MSP430 Floating Point. 22401 (line 6) 22402* floating point, RX: RX-Float. (line 6) 22403* floating point, s390: s390 Floating Point. (line 6) 22404* floating point, SH (IEEE): SH Floating Point. (line 6) 22405* floating point, SPARC (IEEE): Sparc-Float. (line 6) 22406* floating point, V850 (IEEE): V850 Floating Point. (line 6) 22407* floating point, VAX: VAX-float. (line 6) 22408* floating point, x86-64: i386-Float. (line 6) 22409* floating point, Z80: Z80 Floating Point. (line 6) 22410* flonums: Flonums. (line 6) 22411* format of error messages: Errors. (line 24) 22412* format of warning messages: Errors. (line 12) 22413* formfeed (\f): Strings. (line 18) 22414* func directive: Func. (line 6) 22415* functions, in expressions: Operators. (line 6) 22416* gbr960, i960 postprocessor: Options-i960. (line 40) 22417* gfloat directive, VAX: VAX-directives. (line 18) 22418* global: Z8000 Directives. (line 21) 22419* global directive: Global. (line 6) 22420* global directive, TIC54X: TIC54X-Directives. (line 103) 22421* gp register, MIPS: MIPS Object. (line 11) 22422* gp register, V850: V850-Regs. (line 17) 22423* grouping data: Sub-Sections. (line 6) 22424* H8/300 addressing modes: H8/300-Addressing. (line 6) 22425* H8/300 floating point (IEEE): H8/300 Floating Point. 22426 (line 6) 22427* H8/300 line comment character: H8/300-Chars. (line 6) 22428* H8/300 line separator: H8/300-Chars. (line 8) 22429* H8/300 machine directives (none): H8/300 Directives. (line 6) 22430* H8/300 opcode summary: H8/300 Opcodes. (line 6) 22431* H8/300 options: H8/300 Options. (line 6) 22432* H8/300 registers: H8/300-Regs. (line 6) 22433* H8/300 size suffixes: H8/300 Opcodes. (line 163) 22434* H8/300 support: H8/300-Dependent. (line 6) 22435* H8/300H, assembling for: H8/300 Directives. (line 8) 22436* half directive, ARC: ARC Directives. (line 156) 22437* half directive, SPARC: Sparc-Directives. (line 17) 22438* half directive, TIC54X: TIC54X-Directives. (line 111) 22439* hex character code (\XD...): Strings. (line 36) 22440* hexadecimal integers: Integers. (line 15) 22441* hexadecimal prefix, Z80: Z80-Chars. (line 15) 22442* hfloat directive, VAX: VAX-directives. (line 22) 22443* hi pseudo-op, V850: V850 Opcodes. (line 33) 22444* hi0 pseudo-op, V850: V850 Opcodes. (line 10) 22445* hidden directive: Hidden. (line 6) 22446* high directive, M32R: M32R-Directives. (line 18) 22447* hilo pseudo-op, V850: V850 Opcodes. (line 55) 22448* HPPA directives not supported: HPPA Directives. (line 11) 22449* HPPA floating point (IEEE): HPPA Floating Point. (line 6) 22450* HPPA Syntax: HPPA Options. (line 8) 22451* HPPA-only directives: HPPA Directives. (line 24) 22452* hword directive: hword. (line 6) 22453* i370 support: ESA/390-Dependent. (line 6) 22454* i386 16-bit code: i386-16bit. (line 6) 22455* i386 arch directive: i386-Arch. (line 6) 22456* i386 att_syntax pseudo op: i386-Variations. (line 6) 22457* i386 conversion instructions: i386-Mnemonics. (line 37) 22458* i386 floating point: i386-Float. (line 6) 22459* i386 immediate operands: i386-Variations. (line 15) 22460* i386 instruction naming: i386-Mnemonics. (line 6) 22461* i386 instruction prefixes: i386-Prefixes. (line 6) 22462* i386 intel_syntax pseudo op: i386-Variations. (line 6) 22463* i386 jump optimization: i386-Jumps. (line 6) 22464* i386 jump, call, return: i386-Variations. (line 41) 22465* i386 jump/call operands: i386-Variations. (line 15) 22466* i386 line comment character: i386-Chars. (line 6) 22467* i386 line separator: i386-Chars. (line 18) 22468* i386 memory references: i386-Memory. (line 6) 22469* i386 mnemonic compatibility: i386-Mnemonics. (line 62) 22470* i386 mul, imul instructions: i386-Notes. (line 6) 22471* i386 options: i386-Options. (line 6) 22472* i386 register operands: i386-Variations. (line 15) 22473* i386 registers: i386-Regs. (line 6) 22474* i386 sections: i386-Variations. (line 47) 22475* i386 size suffixes: i386-Variations. (line 29) 22476* i386 source, destination operands: i386-Variations. (line 22) 22477* i386 support: i386-Dependent. (line 6) 22478* i386 syntax compatibility: i386-Variations. (line 6) 22479* i80386 support: i386-Dependent. (line 6) 22480* i860 line comment character: i860-Chars. (line 6) 22481* i860 line separator: i860-Chars. (line 14) 22482* i860 machine directives: Directives-i860. (line 6) 22483* i860 opcodes: Opcodes for i860. (line 6) 22484* i860 support: i860-Dependent. (line 6) 22485* i960 architecture options: Options-i960. (line 6) 22486* i960 branch recording: Options-i960. (line 22) 22487* i960 callj pseudo-opcode: callj-i960. (line 6) 22488* i960 compare and jump expansions: Compare-and-branch-i960. 22489 (line 13) 22490* i960 compare/branch instructions: Compare-and-branch-i960. 22491 (line 6) 22492* i960 floating point (IEEE): Floating Point-i960. (line 6) 22493* i960 line comment character: i960-Chars. (line 6) 22494* i960 line separator: i960-Chars. (line 14) 22495* i960 machine directives: Directives-i960. (line 6) 22496* i960 opcodes: Opcodes for i960. (line 6) 22497* i960 options: Options-i960. (line 6) 22498* i960 support: i960-Dependent. (line 6) 22499* IA-64 line comment character: IA-64-Chars. (line 6) 22500* IA-64 line separator: IA-64-Chars. (line 8) 22501* IA-64 options: IA-64 Options. (line 6) 22502* IA-64 Processor-status-Register bit names: IA-64-Bits. (line 6) 22503* IA-64 registers: IA-64-Regs. (line 6) 22504* IA-64 relocations: IA-64-Relocs. (line 6) 22505* IA-64 support: IA-64-Dependent. (line 6) 22506* IA-64 Syntax: IA-64 Options. (line 87) 22507* ident directive: Ident. (line 6) 22508* identifiers, ARM: ARM-Chars. (line 19) 22509* identifiers, MSP 430: MSP430-Chars. (line 17) 22510* if directive: If. (line 6) 22511* ifb directive: If. (line 21) 22512* ifc directive: If. (line 25) 22513* ifdef directive: If. (line 16) 22514* ifeq directive: If. (line 33) 22515* ifeqs directive: If. (line 36) 22516* ifge directive: If. (line 40) 22517* ifgt directive: If. (line 44) 22518* ifle directive: If. (line 48) 22519* iflt directive: If. (line 52) 22520* ifnb directive: If. (line 56) 22521* ifnc directive: If. (line 61) 22522* ifndef directive: If. (line 65) 22523* ifne directive: If. (line 72) 22524* ifnes directive: If. (line 76) 22525* ifnotdef directive: If. (line 65) 22526* immediate character, ARM: ARM-Chars. (line 17) 22527* immediate character, M680x0: M68K-Chars. (line 13) 22528* immediate character, VAX: VAX-operands. (line 6) 22529* immediate fields, relaxation: Xtensa Immediate Relaxation. 22530 (line 6) 22531* immediate operands, i386: i386-Variations. (line 15) 22532* immediate operands, x86-64: i386-Variations. (line 15) 22533* imul instruction, i386: i386-Notes. (line 6) 22534* imul instruction, x86-64: i386-Notes. (line 6) 22535* incbin directive: Incbin. (line 6) 22536* include directive: Include. (line 6) 22537* include directive search path: I. (line 6) 22538* indirect character, VAX: VAX-operands. (line 9) 22539* infix operators: Infix Ops. (line 6) 22540* inhibiting interrupts, i386: i386-Prefixes. (line 36) 22541* input: Input Files. (line 6) 22542* input file linenumbers: Input Files. (line 35) 22543* instruction aliases, s390: s390 Aliases. (line 6) 22544* instruction expansion, CRIS: CRIS-Expand. (line 6) 22545* instruction expansion, MMIX: MMIX-Expand. (line 6) 22546* instruction formats, s390: s390 Formats. (line 6) 22547* instruction marker, s390: s390 Instruction Marker. 22548 (line 6) 22549* instruction mnemonics, s390: s390 Mnemonics. (line 6) 22550* instruction naming, i386: i386-Mnemonics. (line 6) 22551* instruction naming, x86-64: i386-Mnemonics. (line 6) 22552* instruction operand modifier, s390: s390 Operand Modifier. 22553 (line 6) 22554* instruction operands, s390: s390 Operands. (line 6) 22555* instruction prefixes, i386: i386-Prefixes. (line 6) 22556* instruction set, M680x0: M68K-opcodes. (line 6) 22557* instruction set, M68HC11: M68HC11-opcodes. (line 6) 22558* instruction summary, AVR: AVR Opcodes. (line 6) 22559* instruction summary, D10V: D10V-Opcodes. (line 6) 22560* instruction summary, D30V: D30V-Opcodes. (line 6) 22561* instruction summary, H8/300: H8/300 Opcodes. (line 6) 22562* instruction summary, LM32: LM32 Opcodes. (line 6) 22563* instruction summary, SH: SH Opcodes. (line 6) 22564* instruction summary, SH64: SH64 Opcodes. (line 6) 22565* instruction summary, Z8000: Z8000 Opcodes. (line 6) 22566* instruction syntax, s390: s390 Syntax. (line 6) 22567* instructions and directives: Statements. (line 20) 22568* int directive: Int. (line 6) 22569* int directive, H8/300: H8/300 Directives. (line 6) 22570* int directive, i386: i386-Float. (line 21) 22571* int directive, TIC54X: TIC54X-Directives. (line 111) 22572* int directive, x86-64: i386-Float. (line 21) 22573* integer expressions: Integer Exprs. (line 6) 22574* integer, 16-byte: Octa. (line 6) 22575* integer, 8-byte: Quad. (line 9) 22576* integers: Integers. (line 6) 22577* integers, 16-bit: hword. (line 6) 22578* integers, 32-bit: Int. (line 6) 22579* integers, binary: Integers. (line 6) 22580* integers, decimal: Integers. (line 12) 22581* integers, hexadecimal: Integers. (line 15) 22582* integers, octal: Integers. (line 9) 22583* integers, one byte: Byte. (line 6) 22584* intel_syntax pseudo op, i386: i386-Variations. (line 6) 22585* intel_syntax pseudo op, x86-64: i386-Variations. (line 6) 22586* internal assembler sections: As Sections. (line 6) 22587* internal directive: Internal. (line 6) 22588* invalid input: Bug Criteria. (line 14) 22589* invocation summary: Overview. (line 6) 22590* IP2K architecture options: IP2K-Opts. (line 9) 22591* IP2K line comment character: IP2K-Chars. (line 6) 22592* IP2K line separator: IP2K-Chars. (line 14) 22593* IP2K options: IP2K-Opts. (line 6) 22594* IP2K support: IP2K-Dependent. (line 6) 22595* irp directive: Irp. (line 6) 22596* irpc directive: Irpc. (line 6) 22597* ISA options, SH64: SH64 Options. (line 6) 22598* joining text and data sections: R. (line 6) 22599* jump instructions, i386: i386-Mnemonics. (line 56) 22600* jump instructions, x86-64: i386-Mnemonics. (line 56) 22601* jump optimization, i386: i386-Jumps. (line 6) 22602* jump optimization, x86-64: i386-Jumps. (line 6) 22603* jump/call operands, i386: i386-Variations. (line 15) 22604* jump/call operands, x86-64: i386-Variations. (line 15) 22605* L16SI instructions, relaxation: Xtensa Immediate Relaxation. 22606 (line 23) 22607* L16UI instructions, relaxation: Xtensa Immediate Relaxation. 22608 (line 23) 22609* L32I instructions, relaxation: Xtensa Immediate Relaxation. 22610 (line 23) 22611* L8UI instructions, relaxation: Xtensa Immediate Relaxation. 22612 (line 23) 22613* label (:): Statements. (line 31) 22614* label directive, TIC54X: TIC54X-Directives. (line 123) 22615* labels: Labels. (line 6) 22616* lcomm directive: Lcomm. (line 6) 22617* lcomm directive, COFF: i386-Directives. (line 6) 22618* ld: Object. (line 15) 22619* ldouble directive M680x0: M68K-Float. (line 17) 22620* ldouble directive M68HC11: M68HC11-Float. (line 17) 22621* ldouble directive, TIC54X: TIC54X-Directives. (line 64) 22622* LDR reg,=<label> pseudo op, ARM: ARM Opcodes. (line 15) 22623* leafproc directive, i960: Directives-i960. (line 18) 22624* length directive, TIC54X: TIC54X-Directives. (line 127) 22625* length of symbols: Symbol Intro. (line 14) 22626* lflags directive (ignored): Lflags. (line 6) 22627* line comment character: Comments. (line 19) 22628* line comment character, Alpha: Alpha-Chars. (line 6) 22629* line comment character, ARC: ARC-Chars. (line 6) 22630* line comment character, ARM: ARM-Chars. (line 6) 22631* line comment character, AVR: AVR-Chars. (line 6) 22632* line comment character, CR16: CR16-Chars. (line 6) 22633* line comment character, D10V: D10V-Chars. (line 6) 22634* line comment character, D30V: D30V-Chars. (line 6) 22635* line comment character, H8/300: H8/300-Chars. (line 6) 22636* line comment character, i386: i386-Chars. (line 6) 22637* line comment character, i860: i860-Chars. (line 6) 22638* line comment character, i960: i960-Chars. (line 6) 22639* line comment character, IA-64: IA-64-Chars. (line 6) 22640* line comment character, IP2K: IP2K-Chars. (line 6) 22641* line comment character, LM32: LM32-Chars. (line 6) 22642* line comment character, M32C: M32C-Chars. (line 6) 22643* line comment character, M680x0: M68K-Chars. (line 6) 22644* line comment character, M68HC11: M68HC11-Syntax. (line 17) 22645* line comment character, MicroBlaze: MicroBlaze-Chars. (line 6) 22646* line comment character, MIPS: MIPS-Chars. (line 6) 22647* line comment character, MSP 430: MSP430-Chars. (line 6) 22648* line comment character, NS32K: NS32K-Chars. (line 6) 22649* line comment character, PJ: PJ-Chars. (line 6) 22650* line comment character, PowerPC: PowerPC-Chars. (line 6) 22651* line comment character, RX: RX-Chars. (line 6) 22652* line comment character, s390: s390 Characters. (line 6) 22653* line comment character, SCORE: SCORE-Chars. (line 6) 22654* line comment character, SH: SH-Chars. (line 6) 22655* line comment character, SH64: SH64-Chars. (line 6) 22656* line comment character, Sparc: Sparc-Chars. (line 6) 22657* line comment character, TIC54X: TIC54X-Chars. (line 6) 22658* line comment character, TIC6X: TIC6X Syntax. (line 6) 22659* line comment character, V850: V850-Chars. (line 6) 22660* line comment character, VAX: VAX-Chars. (line 6) 22661* line comment character, XStormy16: XStormy16-Chars. (line 6) 22662* line comment character, Z80: Z80-Chars. (line 6) 22663* line comment character, Z8000: Z8000-Chars. (line 6) 22664* line comment characters, CRIS: CRIS-Chars. (line 6) 22665* line comment characters, MMIX: MMIX-Chars. (line 6) 22666* line directive: Line. (line 6) 22667* line directive, MSP 430: MSP430 Directives. (line 14) 22668* line numbers, in input files: Input Files. (line 35) 22669* line numbers, in warnings/errors: Errors. (line 16) 22670* line separator character: Statements. (line 6) 22671* line separator, Alpha: Alpha-Chars. (line 11) 22672* line separator, ARC: ARC-Chars. (line 12) 22673* line separator, ARM: ARM-Chars. (line 14) 22674* line separator, AVR: AVR-Chars. (line 14) 22675* line separator, CR16: CR16-Chars. (line 13) 22676* line separator, H8/300: H8/300-Chars. (line 8) 22677* line separator, i386: i386-Chars. (line 18) 22678* line separator, i860: i860-Chars. (line 14) 22679* line separator, i960: i960-Chars. (line 14) 22680* line separator, IA-64: IA-64-Chars. (line 8) 22681* line separator, IP2K: IP2K-Chars. (line 14) 22682* line separator, LM32: LM32-Chars. (line 12) 22683* line separator, M32C: M32C-Chars. (line 14) 22684* line separator, M680x0: M68K-Chars. (line 20) 22685* line separator, M68HC11: M68HC11-Syntax. (line 27) 22686* line separator, MicroBlaze: MicroBlaze-Chars. (line 14) 22687* line separator, MIPS: MIPS-Chars. (line 14) 22688* line separator, MSP 430: MSP430-Chars. (line 14) 22689* line separator, NS32K: NS32K-Chars. (line 18) 22690* line separator, PJ: PJ-Chars. (line 14) 22691* line separator, PowerPC: PowerPC-Chars. (line 18) 22692* line separator, RX: RX-Chars. (line 14) 22693* line separator, s390: s390 Characters. (line 13) 22694* line separator, SCORE: SCORE-Chars. (line 14) 22695* line separator, SH: SH-Chars. (line 8) 22696* line separator, SH64: SH64-Chars. (line 13) 22697* line separator, Sparc: Sparc-Chars. (line 14) 22698* line separator, TIC54X: TIC54X-Chars. (line 17) 22699* line separator, TIC6X: TIC6X Syntax. (line 13) 22700* line separator, V850: V850-Chars. (line 13) 22701* line separator, VAX: VAX-Chars. (line 14) 22702* line separator, XStormy16: XStormy16-Chars. (line 14) 22703* line separator, Z80: Z80-Chars. (line 13) 22704* line separator, Z8000: Z8000-Chars. (line 13) 22705* lines starting with #: Comments. (line 33) 22706* linker: Object. (line 15) 22707* linker, and assembler: Secs Background. (line 10) 22708* linkonce directive: Linkonce. (line 6) 22709* list directive: List. (line 6) 22710* list directive, TIC54X: TIC54X-Directives. (line 131) 22711* listing control, turning off: Nolist. (line 6) 22712* listing control, turning on: List. (line 6) 22713* listing control: new page: Eject. (line 6) 22714* listing control: paper size: Psize. (line 6) 22715* listing control: subtitle: Sbttl. (line 6) 22716* listing control: title line: Title. (line 6) 22717* listings, enabling: a. (line 6) 22718* literal directive: Literal Directive. (line 6) 22719* literal pool entries, s390: s390 Literal Pool Entries. 22720 (line 6) 22721* literal_position directive: Literal Position Directive. 22722 (line 6) 22723* literal_prefix directive: Literal Prefix Directive. 22724 (line 6) 22725* little endian output, MIPS: Overview. (line 697) 22726* little endian output, PJ: Overview. (line 604) 22727* little-endian output, MIPS: MIPS Opts. (line 13) 22728* little-endian output, TIC6X: TIC6X Options. (line 46) 22729* LM32 line comment character: LM32-Chars. (line 6) 22730* LM32 line separator: LM32-Chars. (line 12) 22731* LM32 modifiers: LM32-Modifiers. (line 6) 22732* LM32 opcode summary: LM32 Opcodes. (line 6) 22733* LM32 options (none): LM32 Options. (line 6) 22734* LM32 register names: LM32-Regs. (line 6) 22735* LM32 support: LM32-Dependent. (line 6) 22736* ln directive: Ln. (line 6) 22737* lo pseudo-op, V850: V850 Opcodes. (line 22) 22738* loc directive: Loc. (line 6) 22739* loc_mark_labels directive: Loc_mark_labels. (line 6) 22740* local common symbols: Lcomm. (line 6) 22741* local directive: Local. (line 6) 22742* local labels: Symbol Names. (line 35) 22743* local symbol names: Symbol Names. (line 22) 22744* local symbols, retaining in output: L. (line 6) 22745* location counter: Dot. (line 6) 22746* location counter, advancing: Org. (line 6) 22747* location counter, Z80: Z80-Chars. (line 15) 22748* logical file name: File. (line 13) 22749* logical line number: Line. (line 6) 22750* logical line numbers: Comments. (line 33) 22751* long directive: Long. (line 6) 22752* long directive, ARC: ARC Directives. (line 159) 22753* long directive, i386: i386-Float. (line 21) 22754* long directive, TIC54X: TIC54X-Directives. (line 135) 22755* long directive, x86-64: i386-Float. (line 21) 22756* longcall pseudo-op, V850: V850 Opcodes. (line 123) 22757* longcalls directive: Longcalls Directive. (line 6) 22758* longjump pseudo-op, V850: V850 Opcodes. (line 129) 22759* loop directive, TIC54X: TIC54X-Directives. (line 143) 22760* LOOP instructions, alignment: Xtensa Automatic Alignment. 22761 (line 6) 22762* low directive, M32R: M32R-Directives. (line 9) 22763* lp register, V850: V850-Regs. (line 98) 22764* lval: Z8000 Directives. (line 27) 22765* LWP, i386: i386-LWP. (line 6) 22766* LWP, x86-64: i386-LWP. (line 6) 22767* M16C architecture option: M32C-Opts. (line 12) 22768* M32C architecture option: M32C-Opts. (line 9) 22769* M32C line comment character: M32C-Chars. (line 6) 22770* M32C line separator: M32C-Chars. (line 14) 22771* M32C modifiers: M32C-Modifiers. (line 6) 22772* M32C options: M32C-Opts. (line 6) 22773* M32C support: M32C-Dependent. (line 6) 22774* M32R architecture options: M32R-Opts. (line 9) 22775* M32R directives: M32R-Directives. (line 6) 22776* M32R options: M32R-Opts. (line 6) 22777* M32R support: M32R-Dependent. (line 6) 22778* M32R warnings: M32R-Warnings. (line 6) 22779* M680x0 addressing modes: M68K-Syntax. (line 21) 22780* M680x0 architecture options: M68K-Opts. (line 98) 22781* M680x0 branch improvement: M68K-Branch. (line 6) 22782* M680x0 directives: M68K-Directives. (line 6) 22783* M680x0 floating point: M68K-Float. (line 6) 22784* M680x0 immediate character: M68K-Chars. (line 13) 22785* M680x0 line comment character: M68K-Chars. (line 6) 22786* M680x0 line separator: M68K-Chars. (line 20) 22787* M680x0 opcodes: M68K-opcodes. (line 6) 22788* M680x0 options: M68K-Opts. (line 6) 22789* M680x0 pseudo-opcodes: M68K-Branch. (line 6) 22790* M680x0 size modifiers: M68K-Syntax. (line 8) 22791* M680x0 support: M68K-Dependent. (line 6) 22792* M680x0 syntax: M68K-Syntax. (line 8) 22793* M68HC11 addressing modes: M68HC11-Syntax. (line 30) 22794* M68HC11 and M68HC12 support: M68HC11-Dependent. (line 6) 22795* M68HC11 assembler directive .far: M68HC11-Directives. (line 20) 22796* M68HC11 assembler directive .interrupt: M68HC11-Directives. (line 26) 22797* M68HC11 assembler directive .mode: M68HC11-Directives. (line 16) 22798* M68HC11 assembler directive .relax: M68HC11-Directives. (line 10) 22799* M68HC11 assembler directive .xrefb: M68HC11-Directives. (line 31) 22800* M68HC11 assembler directives: M68HC11-Directives. (line 6) 22801* M68HC11 branch improvement: M68HC11-Branch. (line 6) 22802* M68HC11 floating point: M68HC11-Float. (line 6) 22803* M68HC11 line comment character: M68HC11-Syntax. (line 17) 22804* M68HC11 line separator: M68HC11-Syntax. (line 27) 22805* M68HC11 modifiers: M68HC11-Modifiers. (line 6) 22806* M68HC11 opcodes: M68HC11-opcodes. (line 6) 22807* M68HC11 options: M68HC11-Opts. (line 6) 22808* M68HC11 pseudo-opcodes: M68HC11-Branch. (line 6) 22809* M68HC11 syntax: M68HC11-Syntax. (line 6) 22810* M68HC12 assembler directives: M68HC11-Directives. (line 6) 22811* machine dependencies: Machine Dependencies. 22812 (line 6) 22813* machine directives, ARC: ARC Directives. (line 6) 22814* machine directives, ARM: ARM Directives. (line 6) 22815* machine directives, H8/300 (none): H8/300 Directives. (line 6) 22816* machine directives, i860: Directives-i860. (line 6) 22817* machine directives, i960: Directives-i960. (line 6) 22818* machine directives, MSP 430: MSP430 Directives. (line 6) 22819* machine directives, SH: SH Directives. (line 6) 22820* machine directives, SH64: SH64 Directives. (line 9) 22821* machine directives, SPARC: Sparc-Directives. (line 6) 22822* machine directives, TIC54X: TIC54X-Directives. (line 6) 22823* machine directives, TIC6X: TIC6X Directives. (line 6) 22824* machine directives, TILE-Gx: TILE-Gx Directives. (line 6) 22825* machine directives, TILEPro: TILEPro Directives. (line 6) 22826* machine directives, V850: V850 Directives. (line 6) 22827* machine directives, VAX: VAX-directives. (line 6) 22828* machine directives, x86: i386-Directives. (line 6) 22829* machine directives, XStormy16: XStormy16 Directives. 22830 (line 6) 22831* machine independent directives: Pseudo Ops. (line 6) 22832* machine instructions (not covered): Manual. (line 14) 22833* machine-independent syntax: Syntax. (line 6) 22834* macro directive: Macro. (line 28) 22835* macro directive, TIC54X: TIC54X-Directives. (line 153) 22836* macros: Macro. (line 6) 22837* macros, count executed: Macro. (line 143) 22838* Macros, MSP 430: MSP430-Macros. (line 6) 22839* macros, TIC54X: TIC54X-Macros. (line 6) 22840* make rules: MD. (line 6) 22841* manual, structure and purpose: Manual. (line 6) 22842* math builtins, TIC54X: TIC54X-Builtins. (line 6) 22843* Maximum number of continuation lines: listing. (line 34) 22844* memory references, i386: i386-Memory. (line 6) 22845* memory references, x86-64: i386-Memory. (line 6) 22846* memory-mapped registers, TIC54X: TIC54X-MMRegs. (line 6) 22847* merging text and data sections: R. (line 6) 22848* messages from assembler: Errors. (line 6) 22849* MicroBlaze architectures: MicroBlaze-Dependent. 22850 (line 6) 22851* MicroBlaze directives: MicroBlaze Directives. 22852 (line 6) 22853* MicroBlaze line comment character: MicroBlaze-Chars. (line 6) 22854* MicroBlaze line separator: MicroBlaze-Chars. (line 14) 22855* MicroBlaze support: MicroBlaze-Dependent. 22856 (line 13) 22857* minus, permitted arguments: Infix Ops. (line 49) 22858* MIPS 32-bit microMIPS instruction generation override: MIPS assembly options. 22859 (line 6) 22860* MIPS architecture options: MIPS Opts. (line 29) 22861* MIPS big-endian output: MIPS Opts. (line 13) 22862* MIPS CPU override: MIPS ISA. (line 18) 22863* MIPS debugging directives: MIPS Stabs. (line 6) 22864* MIPS DSP Release 1 instruction generation override: MIPS ASE instruction generation overrides. 22865 (line 21) 22866* MIPS DSP Release 2 instruction generation override: MIPS ASE instruction generation overrides. 22867 (line 26) 22868* MIPS ECOFF sections: MIPS Object. (line 6) 22869* MIPS endianness: Overview. (line 694) 22870* MIPS ISA: Overview. (line 700) 22871* MIPS ISA override: MIPS ISA. (line 6) 22872* MIPS line comment character: MIPS-Chars. (line 6) 22873* MIPS line separator: MIPS-Chars. (line 14) 22874* MIPS little-endian output: MIPS Opts. (line 13) 22875* MIPS MCU instruction generation override: MIPS ASE instruction generation overrides. 22876 (line 37) 22877* MIPS MDMX instruction generation override: MIPS ASE instruction generation overrides. 22878 (line 16) 22879* MIPS MIPS-3D instruction generation override: MIPS ASE instruction generation overrides. 22880 (line 6) 22881* MIPS MT instruction generation override: MIPS ASE instruction generation overrides. 22882 (line 32) 22883* MIPS option stack: MIPS option stack. (line 6) 22884* MIPS processor: MIPS-Dependent. (line 6) 22885* MIT: M68K-Syntax. (line 6) 22886* mlib directive, TIC54X: TIC54X-Directives. (line 159) 22887* mlist directive, TIC54X: TIC54X-Directives. (line 164) 22888* MMIX assembler directive BSPEC: MMIX-Pseudos. (line 131) 22889* MMIX assembler directive BYTE: MMIX-Pseudos. (line 97) 22890* MMIX assembler directive ESPEC: MMIX-Pseudos. (line 131) 22891* MMIX assembler directive GREG: MMIX-Pseudos. (line 50) 22892* MMIX assembler directive IS: MMIX-Pseudos. (line 42) 22893* MMIX assembler directive LOC: MMIX-Pseudos. (line 7) 22894* MMIX assembler directive LOCAL: MMIX-Pseudos. (line 28) 22895* MMIX assembler directive OCTA: MMIX-Pseudos. (line 108) 22896* MMIX assembler directive PREFIX: MMIX-Pseudos. (line 120) 22897* MMIX assembler directive TETRA: MMIX-Pseudos. (line 108) 22898* MMIX assembler directive WYDE: MMIX-Pseudos. (line 108) 22899* MMIX assembler directives: MMIX-Pseudos. (line 6) 22900* MMIX line comment characters: MMIX-Chars. (line 6) 22901* MMIX options: MMIX-Opts. (line 6) 22902* MMIX pseudo-op BSPEC: MMIX-Pseudos. (line 131) 22903* MMIX pseudo-op BYTE: MMIX-Pseudos. (line 97) 22904* MMIX pseudo-op ESPEC: MMIX-Pseudos. (line 131) 22905* MMIX pseudo-op GREG: MMIX-Pseudos. (line 50) 22906* MMIX pseudo-op IS: MMIX-Pseudos. (line 42) 22907* MMIX pseudo-op LOC: MMIX-Pseudos. (line 7) 22908* MMIX pseudo-op LOCAL: MMIX-Pseudos. (line 28) 22909* MMIX pseudo-op OCTA: MMIX-Pseudos. (line 108) 22910* MMIX pseudo-op PREFIX: MMIX-Pseudos. (line 120) 22911* MMIX pseudo-op TETRA: MMIX-Pseudos. (line 108) 22912* MMIX pseudo-op WYDE: MMIX-Pseudos. (line 108) 22913* MMIX pseudo-ops: MMIX-Pseudos. (line 6) 22914* MMIX register names: MMIX-Regs. (line 6) 22915* MMIX support: MMIX-Dependent. (line 6) 22916* mmixal differences: MMIX-mmixal. (line 6) 22917* mmregs directive, TIC54X: TIC54X-Directives. (line 169) 22918* mmsg directive, TIC54X: TIC54X-Directives. (line 77) 22919* MMX, i386: i386-SIMD. (line 6) 22920* MMX, x86-64: i386-SIMD. (line 6) 22921* mnemonic compatibility, i386: i386-Mnemonics. (line 62) 22922* mnemonic suffixes, i386: i386-Variations. (line 29) 22923* mnemonic suffixes, x86-64: i386-Variations. (line 29) 22924* mnemonics for opcodes, VAX: VAX-opcodes. (line 6) 22925* mnemonics, AVR: AVR Opcodes. (line 6) 22926* mnemonics, D10V: D10V-Opcodes. (line 6) 22927* mnemonics, D30V: D30V-Opcodes. (line 6) 22928* mnemonics, H8/300: H8/300 Opcodes. (line 6) 22929* mnemonics, LM32: LM32 Opcodes. (line 6) 22930* mnemonics, SH: SH Opcodes. (line 6) 22931* mnemonics, SH64: SH64 Opcodes. (line 6) 22932* mnemonics, Z8000: Z8000 Opcodes. (line 6) 22933* mnolist directive, TIC54X: TIC54X-Directives. (line 164) 22934* modifiers, M32C: M32C-Modifiers. (line 6) 22935* Motorola syntax for the 680x0: M68K-Moto-Syntax. (line 6) 22936* MOVI instructions, relaxation: Xtensa Immediate Relaxation. 22937 (line 12) 22938* MOVW and MOVT relocations, ARM: ARM-Relocations. (line 20) 22939* MRI compatibility mode: M. (line 6) 22940* mri directive: MRI. (line 6) 22941* MRI mode, temporarily: MRI. (line 6) 22942* MSP 430 floating point (IEEE): MSP430 Floating Point. 22943 (line 6) 22944* MSP 430 identifiers: MSP430-Chars. (line 17) 22945* MSP 430 line comment character: MSP430-Chars. (line 6) 22946* MSP 430 line separator: MSP430-Chars. (line 14) 22947* MSP 430 machine directives: MSP430 Directives. (line 6) 22948* MSP 430 macros: MSP430-Macros. (line 6) 22949* MSP 430 opcodes: MSP430 Opcodes. (line 6) 22950* MSP 430 options (none): MSP430 Options. (line 6) 22951* MSP 430 profiling capability: MSP430 Profiling Capability. 22952 (line 6) 22953* MSP 430 register names: MSP430-Regs. (line 6) 22954* MSP 430 support: MSP430-Dependent. (line 6) 22955* MSP430 Assembler Extensions: MSP430-Ext. (line 6) 22956* mul instruction, i386: i386-Notes. (line 6) 22957* mul instruction, x86-64: i386-Notes. (line 6) 22958* N32K support: NS32K-Dependent. (line 6) 22959* name: Z8000 Directives. (line 18) 22960* named section: Section. (line 6) 22961* named sections: Ld Sections. (line 8) 22962* names, symbol: Symbol Names. (line 6) 22963* naming object file: o. (line 6) 22964* new page, in listings: Eject. (line 6) 22965* newblock directive, TIC54X: TIC54X-Directives. (line 175) 22966* newline (\n): Strings. (line 21) 22967* newline, required at file end: Statements. (line 14) 22968* no-absolute-literals directive: Absolute Literals Directive. 22969 (line 6) 22970* no-longcalls directive: Longcalls Directive. (line 6) 22971* no-schedule directive: Schedule Directive. (line 6) 22972* no-transform directive: Transform Directive. (line 6) 22973* nolist directive: Nolist. (line 6) 22974* nolist directive, TIC54X: TIC54X-Directives. (line 131) 22975* NOP pseudo op, ARM: ARM Opcodes. (line 9) 22976* notes for Alpha: Alpha Notes. (line 6) 22977* NS32K line comment character: NS32K-Chars. (line 6) 22978* NS32K line separator: NS32K-Chars. (line 18) 22979* null-terminated strings: Asciz. (line 6) 22980* number constants: Numbers. (line 6) 22981* number of macros executed: Macro. (line 143) 22982* numbered subsections: Sub-Sections. (line 6) 22983* numbers, 16-bit: hword. (line 6) 22984* numeric values: Expressions. (line 6) 22985* nword directive, SPARC: Sparc-Directives. (line 20) 22986* object attributes: Object Attributes. (line 6) 22987* object file: Object. (line 6) 22988* object file format: Object Formats. (line 6) 22989* object file name: o. (line 6) 22990* object file, after errors: Z. (line 6) 22991* obsolescent directives: Deprecated. (line 6) 22992* octa directive: Octa. (line 6) 22993* octal character code (\DDD): Strings. (line 30) 22994* octal integers: Integers. (line 9) 22995* offset directive: Offset. (line 6) 22996* offset directive, V850: V850 Directives. (line 6) 22997* opcode mnemonics, VAX: VAX-opcodes. (line 6) 22998* opcode names, TILE-Gx: TILE-Gx Opcodes. (line 6) 22999* opcode names, TILEPro: TILEPro Opcodes. (line 6) 23000* opcode names, Xtensa: Xtensa Opcodes. (line 6) 23001* opcode summary, AVR: AVR Opcodes. (line 6) 23002* opcode summary, D10V: D10V-Opcodes. (line 6) 23003* opcode summary, D30V: D30V-Opcodes. (line 6) 23004* opcode summary, H8/300: H8/300 Opcodes. (line 6) 23005* opcode summary, LM32: LM32 Opcodes. (line 6) 23006* opcode summary, SH: SH Opcodes. (line 6) 23007* opcode summary, SH64: SH64 Opcodes. (line 6) 23008* opcode summary, Z8000: Z8000 Opcodes. (line 6) 23009* opcodes for ARC: ARC Opcodes. (line 6) 23010* opcodes for ARM: ARM Opcodes. (line 6) 23011* opcodes for MSP 430: MSP430 Opcodes. (line 6) 23012* opcodes for V850: V850 Opcodes. (line 6) 23013* opcodes, i860: Opcodes for i860. (line 6) 23014* opcodes, i960: Opcodes for i960. (line 6) 23015* opcodes, M680x0: M68K-opcodes. (line 6) 23016* opcodes, M68HC11: M68HC11-opcodes. (line 6) 23017* operand delimiters, i386: i386-Variations. (line 15) 23018* operand delimiters, x86-64: i386-Variations. (line 15) 23019* operand notation, VAX: VAX-operands. (line 6) 23020* operands in expressions: Arguments. (line 6) 23021* operator precedence: Infix Ops. (line 11) 23022* operators, in expressions: Operators. (line 6) 23023* operators, permitted arguments: Infix Ops. (line 6) 23024* optimization, D10V: Overview. (line 470) 23025* optimization, D30V: Overview. (line 475) 23026* optimizations: Xtensa Optimizations. 23027 (line 6) 23028* option directive, ARC: ARC Directives. (line 162) 23029* option directive, TIC54X: TIC54X-Directives. (line 179) 23030* option summary: Overview. (line 6) 23031* options for Alpha: Alpha Options. (line 6) 23032* options for ARC (none): ARC Options. (line 6) 23033* options for ARM (none): ARM Options. (line 6) 23034* options for AVR (none): AVR Options. (line 6) 23035* options for Blackfin (none): Blackfin Options. (line 6) 23036* options for i386: i386-Options. (line 6) 23037* options for IA-64: IA-64 Options. (line 6) 23038* options for LM32 (none): LM32 Options. (line 6) 23039* options for MSP430 (none): MSP430 Options. (line 6) 23040* options for PDP-11: PDP-11-Options. (line 6) 23041* options for PowerPC: PowerPC-Opts. (line 6) 23042* options for s390: s390 Options. (line 6) 23043* options for SCORE: SCORE-Opts. (line 6) 23044* options for SPARC: Sparc-Opts. (line 6) 23045* options for TIC6X: TIC6X Options. (line 6) 23046* options for V850 (none): V850 Options. (line 6) 23047* options for VAX/VMS: VAX-Opts. (line 42) 23048* options for x86-64: i386-Options. (line 6) 23049* options for Z80: Z80 Options. (line 6) 23050* options, all versions of assembler: Invoking. (line 6) 23051* options, command line: Command Line. (line 13) 23052* options, CRIS: CRIS-Opts. (line 6) 23053* options, D10V: D10V-Opts. (line 6) 23054* options, D30V: D30V-Opts. (line 6) 23055* options, H8/300: H8/300 Options. (line 6) 23056* options, i960: Options-i960. (line 6) 23057* options, IP2K: IP2K-Opts. (line 6) 23058* options, M32C: M32C-Opts. (line 6) 23059* options, M32R: M32R-Opts. (line 6) 23060* options, M680x0: M68K-Opts. (line 6) 23061* options, M68HC11: M68HC11-Opts. (line 6) 23062* options, MMIX: MMIX-Opts. (line 6) 23063* options, PJ: PJ Options. (line 6) 23064* options, RX: RX-Opts. (line 6) 23065* options, SH: SH Options. (line 6) 23066* options, SH64: SH64 Options. (line 6) 23067* options, TIC54X: TIC54X-Opts. (line 6) 23068* options, Z8000: Z8000 Options. (line 6) 23069* org directive: Org. (line 6) 23070* other attribute, of a.out symbol: Symbol Other. (line 6) 23071* output file: Object. (line 6) 23072* p2align directive: P2align. (line 6) 23073* p2alignl directive: P2align. (line 28) 23074* p2alignw directive: P2align. (line 28) 23075* padding the location counter: Align. (line 6) 23076* padding the location counter given a power of two: P2align. (line 6) 23077* padding the location counter given number of bytes: Balign. (line 6) 23078* page, in listings: Eject. (line 6) 23079* paper size, for listings: Psize. (line 6) 23080* paths for .include: I. (line 6) 23081* patterns, writing in memory: Fill. (line 6) 23082* PDP-11 comments: PDP-11-Syntax. (line 16) 23083* PDP-11 floating-point register syntax: PDP-11-Syntax. (line 13) 23084* PDP-11 general-purpose register syntax: PDP-11-Syntax. (line 10) 23085* PDP-11 instruction naming: PDP-11-Mnemonics. (line 6) 23086* PDP-11 line separator: PDP-11-Syntax. (line 19) 23087* PDP-11 support: PDP-11-Dependent. (line 6) 23088* PDP-11 syntax: PDP-11-Syntax. (line 6) 23089* PIC code generation for ARM: ARM Options. (line 163) 23090* PIC code generation for M32R: M32R-Opts. (line 42) 23091* PIC selection, MIPS: MIPS Opts. (line 21) 23092* PJ endianness: Overview. (line 601) 23093* PJ line comment character: PJ-Chars. (line 6) 23094* PJ line separator: PJ-Chars. (line 14) 23095* PJ options: PJ Options. (line 6) 23096* PJ support: PJ-Dependent. (line 6) 23097* plus, permitted arguments: Infix Ops. (line 44) 23098* popsection directive: PopSection. (line 6) 23099* Position-independent code, CRIS: CRIS-Opts. (line 27) 23100* Position-independent code, symbols in, CRIS: CRIS-Pic. (line 6) 23101* PowerPC architectures: PowerPC-Opts. (line 6) 23102* PowerPC directives: PowerPC-Pseudo. (line 6) 23103* PowerPC line comment character: PowerPC-Chars. (line 6) 23104* PowerPC line separator: PowerPC-Chars. (line 18) 23105* PowerPC options: PowerPC-Opts. (line 6) 23106* PowerPC support: PPC-Dependent. (line 6) 23107* precedence of operators: Infix Ops. (line 11) 23108* precision, floating point: Flonums. (line 6) 23109* prefix operators: Prefix Ops. (line 6) 23110* prefixes, i386: i386-Prefixes. (line 6) 23111* preprocessing: Preprocessing. (line 6) 23112* preprocessing, turning on and off: Preprocessing. (line 26) 23113* previous directive: Previous. (line 6) 23114* primary attributes, COFF symbols: COFF Symbols. (line 13) 23115* print directive: Print. (line 6) 23116* proc directive, SPARC: Sparc-Directives. (line 25) 23117* profiler directive, MSP 430: MSP430 Directives. (line 22) 23118* profiling capability for MSP 430: MSP430 Profiling Capability. 23119 (line 6) 23120* protected directive: Protected. (line 6) 23121* pseudo-op .arch, CRIS: CRIS-Pseudos. (line 45) 23122* pseudo-op .dword, CRIS: CRIS-Pseudos. (line 12) 23123* pseudo-op .syntax, CRIS: CRIS-Pseudos. (line 17) 23124* pseudo-op BSPEC, MMIX: MMIX-Pseudos. (line 131) 23125* pseudo-op BYTE, MMIX: MMIX-Pseudos. (line 97) 23126* pseudo-op ESPEC, MMIX: MMIX-Pseudos. (line 131) 23127* pseudo-op GREG, MMIX: MMIX-Pseudos. (line 50) 23128* pseudo-op IS, MMIX: MMIX-Pseudos. (line 42) 23129* pseudo-op LOC, MMIX: MMIX-Pseudos. (line 7) 23130* pseudo-op LOCAL, MMIX: MMIX-Pseudos. (line 28) 23131* pseudo-op OCTA, MMIX: MMIX-Pseudos. (line 108) 23132* pseudo-op PREFIX, MMIX: MMIX-Pseudos. (line 120) 23133* pseudo-op TETRA, MMIX: MMIX-Pseudos. (line 108) 23134* pseudo-op WYDE, MMIX: MMIX-Pseudos. (line 108) 23135* pseudo-opcodes for XStormy16: XStormy16 Opcodes. (line 6) 23136* pseudo-opcodes, M680x0: M68K-Branch. (line 6) 23137* pseudo-opcodes, M68HC11: M68HC11-Branch. (line 6) 23138* pseudo-ops for branch, VAX: VAX-branch. (line 6) 23139* pseudo-ops, CRIS: CRIS-Pseudos. (line 6) 23140* pseudo-ops, machine independent: Pseudo Ops. (line 6) 23141* pseudo-ops, MMIX: MMIX-Pseudos. (line 6) 23142* psize directive: Psize. (line 6) 23143* PSR bits: IA-64-Bits. (line 6) 23144* pstring directive, TIC54X: TIC54X-Directives. (line 208) 23145* psw register, V850: V850-Regs. (line 116) 23146* purgem directive: Purgem. (line 6) 23147* purpose of GNU assembler: GNU Assembler. (line 12) 23148* pushsection directive: PushSection. (line 6) 23149* quad directive: Quad. (line 6) 23150* quad directive, i386: i386-Float. (line 21) 23151* quad directive, x86-64: i386-Float. (line 21) 23152* real-mode code, i386: i386-16bit. (line 6) 23153* ref directive, TIC54X: TIC54X-Directives. (line 103) 23154* register directive, SPARC: Sparc-Directives. (line 29) 23155* register names, Alpha: Alpha-Regs. (line 6) 23156* register names, ARC: ARC-Regs. (line 6) 23157* register names, ARM: ARM-Regs. (line 6) 23158* register names, AVR: AVR-Regs. (line 6) 23159* register names, CRIS: CRIS-Regs. (line 6) 23160* register names, H8/300: H8/300-Regs. (line 6) 23161* register names, IA-64: IA-64-Regs. (line 6) 23162* register names, LM32: LM32-Regs. (line 6) 23163* register names, MMIX: MMIX-Regs. (line 6) 23164* register names, MSP 430: MSP430-Regs. (line 6) 23165* register names, Sparc: Sparc-Regs. (line 6) 23166* register names, TILE-Gx: TILE-Gx Registers. (line 6) 23167* register names, TILEPro: TILEPro Registers. (line 6) 23168* register names, V850: V850-Regs. (line 6) 23169* register names, VAX: VAX-operands. (line 17) 23170* register names, Xtensa: Xtensa Registers. (line 6) 23171* register names, Z80: Z80-Regs. (line 6) 23172* register naming, s390: s390 Register. (line 6) 23173* register operands, i386: i386-Variations. (line 15) 23174* register operands, x86-64: i386-Variations. (line 15) 23175* registers, D10V: D10V-Regs. (line 6) 23176* registers, D30V: D30V-Regs. (line 6) 23177* registers, i386: i386-Regs. (line 6) 23178* registers, SH: SH-Regs. (line 6) 23179* registers, SH64: SH64-Regs. (line 6) 23180* registers, TIC54X memory-mapped: TIC54X-MMRegs. (line 6) 23181* registers, x86-64: i386-Regs. (line 6) 23182* registers, Z8000: Z8000-Regs. (line 6) 23183* relaxation: Xtensa Relaxation. (line 6) 23184* relaxation of ADDI instructions: Xtensa Immediate Relaxation. 23185 (line 43) 23186* relaxation of branch instructions: Xtensa Branch Relaxation. 23187 (line 6) 23188* relaxation of call instructions: Xtensa Call Relaxation. 23189 (line 6) 23190* relaxation of immediate fields: Xtensa Immediate Relaxation. 23191 (line 6) 23192* relaxation of L16SI instructions: Xtensa Immediate Relaxation. 23193 (line 23) 23194* relaxation of L16UI instructions: Xtensa Immediate Relaxation. 23195 (line 23) 23196* relaxation of L32I instructions: Xtensa Immediate Relaxation. 23197 (line 23) 23198* relaxation of L8UI instructions: Xtensa Immediate Relaxation. 23199 (line 23) 23200* relaxation of MOVI instructions: Xtensa Immediate Relaxation. 23201 (line 12) 23202* reloc directive: Reloc. (line 6) 23203* relocation: Sections. (line 6) 23204* relocation example: Ld Sections. (line 40) 23205* relocations, Alpha: Alpha-Relocs. (line 6) 23206* relocations, Sparc: Sparc-Relocs. (line 6) 23207* repeat prefixes, i386: i386-Prefixes. (line 44) 23208* reporting bugs in assembler: Reporting Bugs. (line 6) 23209* rept directive: Rept. (line 6) 23210* reserve directive, SPARC: Sparc-Directives. (line 39) 23211* return instructions, i386: i386-Variations. (line 41) 23212* return instructions, x86-64: i386-Variations. (line 41) 23213* REX prefixes, i386: i386-Prefixes. (line 46) 23214* rsect: Z8000 Directives. (line 52) 23215* RX assembler directive .3byte: RX-Directives. (line 9) 23216* RX assembler directives: RX-Directives. (line 6) 23217* RX floating point: RX-Float. (line 6) 23218* RX line comment character: RX-Chars. (line 6) 23219* RX line separator: RX-Chars. (line 14) 23220* RX modifiers: RX-Modifiers. (line 6) 23221* RX options: RX-Opts. (line 6) 23222* RX support: RX-Dependent. (line 6) 23223* s390 floating point: s390 Floating Point. (line 6) 23224* s390 instruction aliases: s390 Aliases. (line 6) 23225* s390 instruction formats: s390 Formats. (line 6) 23226* s390 instruction marker: s390 Instruction Marker. 23227 (line 6) 23228* s390 instruction mnemonics: s390 Mnemonics. (line 6) 23229* s390 instruction operand modifier: s390 Operand Modifier. 23230 (line 6) 23231* s390 instruction operands: s390 Operands. (line 6) 23232* s390 instruction syntax: s390 Syntax. (line 6) 23233* s390 line comment character: s390 Characters. (line 6) 23234* s390 line separator: s390 Characters. (line 13) 23235* s390 literal pool entries: s390 Literal Pool Entries. 23236 (line 6) 23237* s390 options: s390 Options. (line 6) 23238* s390 register naming: s390 Register. (line 6) 23239* s390 support: S/390-Dependent. (line 6) 23240* sblock directive, TIC54X: TIC54X-Directives. (line 182) 23241* sbttl directive: Sbttl. (line 6) 23242* schedule directive: Schedule Directive. (line 6) 23243* scl directive: Scl. (line 6) 23244* SCORE architectures: SCORE-Opts. (line 6) 23245* SCORE directives: SCORE-Pseudo. (line 6) 23246* SCORE line comment character: SCORE-Chars. (line 6) 23247* SCORE line separator: SCORE-Chars. (line 14) 23248* SCORE options: SCORE-Opts. (line 6) 23249* SCORE processor: SCORE-Dependent. (line 6) 23250* sdaoff pseudo-op, V850: V850 Opcodes. (line 65) 23251* search path for .include: I. (line 6) 23252* sect directive, MSP 430: MSP430 Directives. (line 18) 23253* sect directive, TIC54X: TIC54X-Directives. (line 188) 23254* section directive (COFF version): Section. (line 16) 23255* section directive (ELF version): Section. (line 73) 23256* section directive, V850: V850 Directives. (line 9) 23257* section override prefixes, i386: i386-Prefixes. (line 23) 23258* Section Stack <1>: SubSection. (line 6) 23259* Section Stack <2>: Section. (line 68) 23260* Section Stack <3>: PushSection. (line 6) 23261* Section Stack <4>: Previous. (line 6) 23262* Section Stack: PopSection. (line 6) 23263* section-relative addressing: Secs Background. (line 68) 23264* sections: Sections. (line 6) 23265* sections in messages, internal: As Sections. (line 6) 23266* sections, i386: i386-Variations. (line 47) 23267* sections, named: Ld Sections. (line 8) 23268* sections, x86-64: i386-Variations. (line 47) 23269* seg directive, SPARC: Sparc-Directives. (line 44) 23270* segm: Z8000 Directives. (line 10) 23271* set directive: Set. (line 6) 23272* set directive, TIC54X: TIC54X-Directives. (line 191) 23273* SH addressing modes: SH-Addressing. (line 6) 23274* SH floating point (IEEE): SH Floating Point. (line 6) 23275* SH line comment character: SH-Chars. (line 6) 23276* SH line separator: SH-Chars. (line 8) 23277* SH machine directives: SH Directives. (line 6) 23278* SH opcode summary: SH Opcodes. (line 6) 23279* SH options: SH Options. (line 6) 23280* SH registers: SH-Regs. (line 6) 23281* SH support: SH-Dependent. (line 6) 23282* SH64 ABI options: SH64 Options. (line 29) 23283* SH64 addressing modes: SH64-Addressing. (line 6) 23284* SH64 ISA options: SH64 Options. (line 6) 23285* SH64 line comment character: SH64-Chars. (line 6) 23286* SH64 line separator: SH64-Chars. (line 13) 23287* SH64 machine directives: SH64 Directives. (line 9) 23288* SH64 opcode summary: SH64 Opcodes. (line 6) 23289* SH64 options: SH64 Options. (line 6) 23290* SH64 registers: SH64-Regs. (line 6) 23291* SH64 support: SH64-Dependent. (line 6) 23292* shigh directive, M32R: M32R-Directives. (line 26) 23293* short directive: Short. (line 6) 23294* short directive, ARC: ARC Directives. (line 171) 23295* short directive, TIC54X: TIC54X-Directives. (line 111) 23296* SIMD, i386: i386-SIMD. (line 6) 23297* SIMD, x86-64: i386-SIMD. (line 6) 23298* single character constant: Chars. (line 6) 23299* single directive: Single. (line 6) 23300* single directive, i386: i386-Float. (line 14) 23301* single directive, x86-64: i386-Float. (line 14) 23302* single quote, Z80: Z80-Chars. (line 20) 23303* sixteen bit integers: hword. (line 6) 23304* sixteen byte integer: Octa. (line 6) 23305* size directive (COFF version): Size. (line 11) 23306* size directive (ELF version): Size. (line 19) 23307* size modifiers, D10V: D10V-Size. (line 6) 23308* size modifiers, D30V: D30V-Size. (line 6) 23309* size modifiers, M680x0: M68K-Syntax. (line 8) 23310* size prefixes, i386: i386-Prefixes. (line 27) 23311* size suffixes, H8/300: H8/300 Opcodes. (line 163) 23312* size, translations, Sparc: Sparc-Size-Translations. 23313 (line 6) 23314* sizes operands, i386: i386-Variations. (line 29) 23315* sizes operands, x86-64: i386-Variations. (line 29) 23316* skip directive: Skip. (line 6) 23317* skip directive, M680x0: M68K-Directives. (line 19) 23318* skip directive, SPARC: Sparc-Directives. (line 48) 23319* sleb128 directive: Sleb128. (line 6) 23320* small objects, MIPS ECOFF: MIPS Object. (line 11) 23321* SmartMIPS instruction generation override: MIPS ASE instruction generation overrides. 23322 (line 11) 23323* SOM symbol attributes: SOM Symbols. (line 6) 23324* source program: Input Files. (line 6) 23325* source, destination operands; i386: i386-Variations. (line 22) 23326* source, destination operands; x86-64: i386-Variations. (line 22) 23327* sp register: Xtensa Registers. (line 6) 23328* sp register, V850: V850-Regs. (line 14) 23329* space directive: Space. (line 6) 23330* space directive, TIC54X: TIC54X-Directives. (line 196) 23331* space used, maximum for assembly: statistics. (line 6) 23332* SPARC architectures: Sparc-Opts. (line 6) 23333* Sparc constants: Sparc-Constants. (line 6) 23334* SPARC data alignment: Sparc-Aligned-Data. (line 6) 23335* SPARC floating point (IEEE): Sparc-Float. (line 6) 23336* Sparc line comment character: Sparc-Chars. (line 6) 23337* Sparc line separator: Sparc-Chars. (line 14) 23338* SPARC machine directives: Sparc-Directives. (line 6) 23339* SPARC options: Sparc-Opts. (line 6) 23340* Sparc registers: Sparc-Regs. (line 6) 23341* Sparc relocations: Sparc-Relocs. (line 6) 23342* Sparc size translations: Sparc-Size-Translations. 23343 (line 6) 23344* SPARC support: Sparc-Dependent. (line 6) 23345* SPARC syntax: Sparc-Aligned-Data. (line 21) 23346* special characters, M680x0: M68K-Chars. (line 6) 23347* special purpose registers, MSP 430: MSP430-Regs. (line 11) 23348* sslist directive, TIC54X: TIC54X-Directives. (line 203) 23349* ssnolist directive, TIC54X: TIC54X-Directives. (line 203) 23350* stabd directive: Stab. (line 38) 23351* stabn directive: Stab. (line 48) 23352* stabs directive: Stab. (line 51) 23353* stabX directives: Stab. (line 6) 23354* standard assembler sections: Secs Background. (line 27) 23355* standard input, as input file: Command Line. (line 10) 23356* statement separator character: Statements. (line 6) 23357* statement separator, Alpha: Alpha-Chars. (line 11) 23358* statement separator, ARC: ARC-Chars. (line 12) 23359* statement separator, ARM: ARM-Chars. (line 14) 23360* statement separator, AVR: AVR-Chars. (line 14) 23361* statement separator, CR16: CR16-Chars. (line 13) 23362* statement separator, H8/300: H8/300-Chars. (line 8) 23363* statement separator, i386: i386-Chars. (line 18) 23364* statement separator, i860: i860-Chars. (line 14) 23365* statement separator, i960: i960-Chars. (line 14) 23366* statement separator, IA-64: IA-64-Chars. (line 8) 23367* statement separator, IP2K: IP2K-Chars. (line 14) 23368* statement separator, LM32: LM32-Chars. (line 12) 23369* statement separator, M32C: M32C-Chars. (line 14) 23370* statement separator, M68HC11: M68HC11-Syntax. (line 27) 23371* statement separator, MicroBlaze: MicroBlaze-Chars. (line 14) 23372* statement separator, MIPS: MIPS-Chars. (line 14) 23373* statement separator, MSP 430: MSP430-Chars. (line 14) 23374* statement separator, NS32K: NS32K-Chars. (line 18) 23375* statement separator, PJ: PJ-Chars. (line 14) 23376* statement separator, PowerPC: PowerPC-Chars. (line 18) 23377* statement separator, RX: RX-Chars. (line 14) 23378* statement separator, s390: s390 Characters. (line 13) 23379* statement separator, SCORE: SCORE-Chars. (line 14) 23380* statement separator, SH: SH-Chars. (line 8) 23381* statement separator, SH64: SH64-Chars. (line 13) 23382* statement separator, Sparc: Sparc-Chars. (line 14) 23383* statement separator, TIC54X: TIC54X-Chars. (line 17) 23384* statement separator, TIC6X: TIC6X Syntax. (line 13) 23385* statement separator, V850: V850-Chars. (line 13) 23386* statement separator, VAX: VAX-Chars. (line 14) 23387* statement separator, XStormy16: XStormy16-Chars. (line 14) 23388* statement separator, Z80: Z80-Chars. (line 13) 23389* statement separator, Z8000: Z8000-Chars. (line 13) 23390* statements, structure of: Statements. (line 6) 23391* statistics, about assembly: statistics. (line 6) 23392* stopping the assembly: Abort. (line 6) 23393* string constants: Strings. (line 6) 23394* string directive: String. (line 8) 23395* string directive on HPPA: HPPA Directives. (line 137) 23396* string directive, TIC54X: TIC54X-Directives. (line 208) 23397* string literals: Ascii. (line 6) 23398* string, copying to object file: String. (line 8) 23399* string16 directive: String. (line 8) 23400* string16, copying to object file: String. (line 8) 23401* string32 directive: String. (line 8) 23402* string32, copying to object file: String. (line 8) 23403* string64 directive: String. (line 8) 23404* string64, copying to object file: String. (line 8) 23405* string8 directive: String. (line 8) 23406* string8, copying to object file: String. (line 8) 23407* struct directive: Struct. (line 6) 23408* struct directive, TIC54X: TIC54X-Directives. (line 216) 23409* structure debugging, COFF: Tag. (line 6) 23410* sub-instruction ordering, D10V: D10V-Chars. (line 14) 23411* sub-instruction ordering, D30V: D30V-Chars. (line 14) 23412* sub-instructions, D10V: D10V-Subs. (line 6) 23413* sub-instructions, D30V: D30V-Subs. (line 6) 23414* subexpressions: Arguments. (line 24) 23415* subsection directive: SubSection. (line 6) 23416* subsym builtins, TIC54X: TIC54X-Macros. (line 16) 23417* subtitles for listings: Sbttl. (line 6) 23418* subtraction, permitted arguments: Infix Ops. (line 49) 23419* summary of options: Overview. (line 6) 23420* support: HPPA-Dependent. (line 6) 23421* supporting files, including: Include. (line 6) 23422* suppressing warnings: W. (line 11) 23423* sval: Z8000 Directives. (line 33) 23424* symbol attributes: Symbol Attributes. (line 6) 23425* symbol attributes, a.out: a.out Symbols. (line 6) 23426* symbol attributes, COFF: COFF Symbols. (line 6) 23427* symbol attributes, SOM: SOM Symbols. (line 6) 23428* symbol descriptor, COFF: Desc. (line 6) 23429* symbol modifiers <1>: RX-Modifiers. (line 11) 23430* symbol modifiers <2>: M68HC11-Modifiers. (line 12) 23431* symbol modifiers <3>: M32C-Modifiers. (line 11) 23432* symbol modifiers <4>: LM32-Modifiers. (line 12) 23433* symbol modifiers: AVR-Modifiers. (line 12) 23434* symbol modifiers, TILE-Gx: TILE-Gx Modifiers. (line 6) 23435* symbol modifiers, TILEPro: TILEPro Modifiers. (line 6) 23436* symbol names: Symbol Names. (line 6) 23437* symbol names, $ in <1>: SH64-Chars. (line 15) 23438* symbol names, $ in <2>: SH-Chars. (line 15) 23439* symbol names, $ in <3>: D30V-Chars. (line 70) 23440* symbol names, $ in: D10V-Chars. (line 53) 23441* symbol names, local: Symbol Names. (line 22) 23442* symbol names, temporary: Symbol Names. (line 35) 23443* symbol storage class (COFF): Scl. (line 6) 23444* symbol type: Symbol Type. (line 6) 23445* symbol type, COFF: Type. (line 11) 23446* symbol type, ELF: Type. (line 22) 23447* symbol value: Symbol Value. (line 6) 23448* symbol value, setting: Set. (line 6) 23449* symbol values, assigning: Setting Symbols. (line 6) 23450* symbol versioning: Symver. (line 6) 23451* symbol, common: Comm. (line 6) 23452* symbol, making visible to linker: Global. (line 6) 23453* symbolic debuggers, information for: Stab. (line 6) 23454* symbols: Symbols. (line 6) 23455* Symbols in position-independent code, CRIS: CRIS-Pic. (line 6) 23456* symbols with uppercase, VAX/VMS: VAX-Opts. (line 42) 23457* symbols, assigning values to: Equ. (line 6) 23458* Symbols, built-in, CRIS: CRIS-Symbols. (line 6) 23459* Symbols, CRIS, built-in: CRIS-Symbols. (line 6) 23460* symbols, local common: Lcomm. (line 6) 23461* symver directive: Symver. (line 6) 23462* syntax compatibility, i386: i386-Variations. (line 6) 23463* syntax compatibility, x86-64: i386-Variations. (line 6) 23464* syntax, AVR: AVR-Modifiers. (line 6) 23465* syntax, Blackfin: Blackfin Syntax. (line 6) 23466* syntax, D10V: D10V-Syntax. (line 6) 23467* syntax, D30V: D30V-Syntax. (line 6) 23468* syntax, LM32: LM32-Modifiers. (line 6) 23469* syntax, M680x0: M68K-Syntax. (line 8) 23470* syntax, M68HC11 <1>: M68HC11-Modifiers. (line 6) 23471* syntax, M68HC11: M68HC11-Syntax. (line 6) 23472* syntax, machine-independent: Syntax. (line 6) 23473* syntax, RX: RX-Modifiers. (line 6) 23474* syntax, SPARC: Sparc-Aligned-Data. (line 21) 23475* syntax, TILE-Gx: TILE-Gx Syntax. (line 6) 23476* syntax, TILEPro: TILEPro Syntax. (line 6) 23477* syntax, Xtensa assembler: Xtensa Syntax. (line 6) 23478* sysproc directive, i960: Directives-i960. (line 37) 23479* tab (\t): Strings. (line 27) 23480* tab directive, TIC54X: TIC54X-Directives. (line 247) 23481* tag directive: Tag. (line 6) 23482* tag directive, TIC54X: TIC54X-Directives. (line 216) 23483* TBM, i386: i386-TBM. (line 6) 23484* TBM, x86-64: i386-TBM. (line 6) 23485* tdaoff pseudo-op, V850: V850 Opcodes. (line 81) 23486* temporary symbol names: Symbol Names. (line 35) 23487* text and data sections, joining: R. (line 6) 23488* text directive: Text. (line 6) 23489* text section: Ld Sections. (line 9) 23490* tfloat directive, i386: i386-Float. (line 14) 23491* tfloat directive, x86-64: i386-Float. (line 14) 23492* Thumb support: ARM-Dependent. (line 6) 23493* TIC54X builtin math functions: TIC54X-Builtins. (line 6) 23494* TIC54X line comment character: TIC54X-Chars. (line 6) 23495* TIC54X line separator: TIC54X-Chars. (line 17) 23496* TIC54X machine directives: TIC54X-Directives. (line 6) 23497* TIC54X memory-mapped registers: TIC54X-MMRegs. (line 6) 23498* TIC54X options: TIC54X-Opts. (line 6) 23499* TIC54X subsym builtins: TIC54X-Macros. (line 16) 23500* TIC54X support: TIC54X-Dependent. (line 6) 23501* TIC54X-specific macros: TIC54X-Macros. (line 6) 23502* TIC6X big-endian output: TIC6X Options. (line 46) 23503* TIC6X line comment character: TIC6X Syntax. (line 6) 23504* TIC6X line separator: TIC6X Syntax. (line 13) 23505* TIC6X little-endian output: TIC6X Options. (line 46) 23506* TIC6X machine directives: TIC6X Directives. (line 6) 23507* TIC6X options: TIC6X Options. (line 6) 23508* TIC6X support: TIC6X-Dependent. (line 6) 23509* TILE-Gx machine directives: TILE-Gx Directives. (line 6) 23510* TILE-Gx modifiers: TILE-Gx Modifiers. (line 6) 23511* TILE-Gx opcode names: TILE-Gx Opcodes. (line 6) 23512* TILE-Gx register names: TILE-Gx Registers. (line 6) 23513* TILE-Gx support: TILE-Gx-Dependent. (line 6) 23514* TILE-Gx syntax: TILE-Gx Syntax. (line 6) 23515* TILEPro machine directives: TILEPro Directives. (line 6) 23516* TILEPro modifiers: TILEPro Modifiers. (line 6) 23517* TILEPro opcode names: TILEPro Opcodes. (line 6) 23518* TILEPro register names: TILEPro Registers. (line 6) 23519* TILEPro support: TILEPro-Dependent. (line 6) 23520* TILEPro syntax: TILEPro Syntax. (line 6) 23521* time, total for assembly: statistics. (line 6) 23522* title directive: Title. (line 6) 23523* TMS320C6X support: TIC6X-Dependent. (line 6) 23524* tp register, V850: V850-Regs. (line 20) 23525* transform directive: Transform Directive. (line 6) 23526* trusted compiler: f. (line 6) 23527* turning preprocessing on and off: Preprocessing. (line 26) 23528* type directive (COFF version): Type. (line 11) 23529* type directive (ELF version): Type. (line 22) 23530* type of a symbol: Symbol Type. (line 6) 23531* ualong directive, SH: SH Directives. (line 6) 23532* uaword directive, SH: SH Directives. (line 6) 23533* ubyte directive, TIC54X: TIC54X-Directives. (line 36) 23534* uchar directive, TIC54X: TIC54X-Directives. (line 36) 23535* uhalf directive, TIC54X: TIC54X-Directives. (line 111) 23536* uint directive, TIC54X: TIC54X-Directives. (line 111) 23537* uleb128 directive: Uleb128. (line 6) 23538* ulong directive, TIC54X: TIC54X-Directives. (line 135) 23539* undefined section: Ld Sections. (line 36) 23540* union directive, TIC54X: TIC54X-Directives. (line 250) 23541* unsegm: Z8000 Directives. (line 14) 23542* usect directive, TIC54X: TIC54X-Directives. (line 262) 23543* ushort directive, TIC54X: TIC54X-Directives. (line 111) 23544* uword directive, TIC54X: TIC54X-Directives. (line 111) 23545* V850 command line options: V850 Options. (line 9) 23546* V850 floating point (IEEE): V850 Floating Point. (line 6) 23547* V850 line comment character: V850-Chars. (line 6) 23548* V850 line separator: V850-Chars. (line 13) 23549* V850 machine directives: V850 Directives. (line 6) 23550* V850 opcodes: V850 Opcodes. (line 6) 23551* V850 options (none): V850 Options. (line 6) 23552* V850 register names: V850-Regs. (line 6) 23553* V850 support: V850-Dependent. (line 6) 23554* val directive: Val. (line 6) 23555* value attribute, COFF: Val. (line 6) 23556* value of a symbol: Symbol Value. (line 6) 23557* var directive, TIC54X: TIC54X-Directives. (line 272) 23558* VAX bitfields not supported: VAX-no. (line 6) 23559* VAX branch improvement: VAX-branch. (line 6) 23560* VAX command-line options ignored: VAX-Opts. (line 6) 23561* VAX displacement sizing character: VAX-operands. (line 12) 23562* VAX floating point: VAX-float. (line 6) 23563* VAX immediate character: VAX-operands. (line 6) 23564* VAX indirect character: VAX-operands. (line 9) 23565* VAX line comment character: VAX-Chars. (line 6) 23566* VAX line separator: VAX-Chars. (line 14) 23567* VAX machine directives: VAX-directives. (line 6) 23568* VAX opcode mnemonics: VAX-opcodes. (line 6) 23569* VAX operand notation: VAX-operands. (line 6) 23570* VAX register names: VAX-operands. (line 17) 23571* VAX support: Vax-Dependent. (line 6) 23572* Vax-11 C compatibility: VAX-Opts. (line 42) 23573* VAX/VMS options: VAX-Opts. (line 42) 23574* version directive: Version. (line 6) 23575* version directive, TIC54X: TIC54X-Directives. (line 276) 23576* version of assembler: v. (line 6) 23577* versions of symbols: Symver. (line 6) 23578* visibility <1>: Protected. (line 6) 23579* visibility <2>: Internal. (line 6) 23580* visibility: Hidden. (line 6) 23581* VMS (VAX) options: VAX-Opts. (line 42) 23582* vtable_entry directive: VTableEntry. (line 6) 23583* vtable_inherit directive: VTableInherit. (line 6) 23584* warning directive: Warning. (line 6) 23585* warning for altered difference tables: K. (line 6) 23586* warning messages: Errors. (line 6) 23587* warnings, causing error: W. (line 16) 23588* warnings, M32R: M32R-Warnings. (line 6) 23589* warnings, suppressing: W. (line 11) 23590* warnings, switching on: W. (line 19) 23591* weak directive: Weak. (line 6) 23592* weakref directive: Weakref. (line 6) 23593* whitespace: Whitespace. (line 6) 23594* whitespace, removed by preprocessor: Preprocessing. (line 7) 23595* wide floating point directives, VAX: VAX-directives. (line 10) 23596* width directive, TIC54X: TIC54X-Directives. (line 127) 23597* Width of continuation lines of disassembly output: listing. (line 21) 23598* Width of first line disassembly output: listing. (line 16) 23599* Width of source line output: listing. (line 28) 23600* wmsg directive, TIC54X: TIC54X-Directives. (line 77) 23601* word directive: Word. (line 6) 23602* word directive, ARC: ARC Directives. (line 174) 23603* word directive, H8/300: H8/300 Directives. (line 6) 23604* word directive, i386: i386-Float. (line 21) 23605* word directive, SPARC: Sparc-Directives. (line 51) 23606* word directive, TIC54X: TIC54X-Directives. (line 111) 23607* word directive, x86-64: i386-Float. (line 21) 23608* writing patterns in memory: Fill. (line 6) 23609* wval: Z8000 Directives. (line 24) 23610* x86 machine directives: i386-Directives. (line 6) 23611* x86-64 arch directive: i386-Arch. (line 6) 23612* x86-64 att_syntax pseudo op: i386-Variations. (line 6) 23613* x86-64 conversion instructions: i386-Mnemonics. (line 37) 23614* x86-64 floating point: i386-Float. (line 6) 23615* x86-64 immediate operands: i386-Variations. (line 15) 23616* x86-64 instruction naming: i386-Mnemonics. (line 6) 23617* x86-64 intel_syntax pseudo op: i386-Variations. (line 6) 23618* x86-64 jump optimization: i386-Jumps. (line 6) 23619* x86-64 jump, call, return: i386-Variations. (line 41) 23620* x86-64 jump/call operands: i386-Variations. (line 15) 23621* x86-64 memory references: i386-Memory. (line 6) 23622* x86-64 options: i386-Options. (line 6) 23623* x86-64 register operands: i386-Variations. (line 15) 23624* x86-64 registers: i386-Regs. (line 6) 23625* x86-64 sections: i386-Variations. (line 47) 23626* x86-64 size suffixes: i386-Variations. (line 29) 23627* x86-64 source, destination operands: i386-Variations. (line 22) 23628* x86-64 support: i386-Dependent. (line 6) 23629* x86-64 syntax compatibility: i386-Variations. (line 6) 23630* xfloat directive, TIC54X: TIC54X-Directives. (line 64) 23631* xlong directive, TIC54X: TIC54X-Directives. (line 135) 23632* XStormy16 comment character: XStormy16-Chars. (line 11) 23633* XStormy16 line comment character: XStormy16-Chars. (line 6) 23634* XStormy16 line separator: XStormy16-Chars. (line 14) 23635* XStormy16 machine directives: XStormy16 Directives. 23636 (line 6) 23637* XStormy16 pseudo-opcodes: XStormy16 Opcodes. (line 6) 23638* XStormy16 support: XSTORMY16-Dependent. (line 6) 23639* Xtensa architecture: Xtensa-Dependent. (line 6) 23640* Xtensa assembler syntax: Xtensa Syntax. (line 6) 23641* Xtensa directives: Xtensa Directives. (line 6) 23642* Xtensa opcode names: Xtensa Opcodes. (line 6) 23643* Xtensa register names: Xtensa Registers. (line 6) 23644* xword directive, SPARC: Sparc-Directives. (line 55) 23645* Z80 $: Z80-Chars. (line 15) 23646* Z80 ': Z80-Chars. (line 20) 23647* Z80 floating point: Z80 Floating Point. (line 6) 23648* Z80 line comment character: Z80-Chars. (line 6) 23649* Z80 line separator: Z80-Chars. (line 13) 23650* Z80 options: Z80 Options. (line 6) 23651* Z80 registers: Z80-Regs. (line 6) 23652* Z80 support: Z80-Dependent. (line 6) 23653* Z80 Syntax: Z80 Options. (line 47) 23654* Z80, \: Z80-Chars. (line 18) 23655* Z80, case sensitivity: Z80-Case. (line 6) 23656* Z80-only directives: Z80 Directives. (line 9) 23657* Z800 addressing modes: Z8000-Addressing. (line 6) 23658* Z8000 directives: Z8000 Directives. (line 6) 23659* Z8000 line comment character: Z8000-Chars. (line 6) 23660* Z8000 line separator: Z8000-Chars. (line 13) 23661* Z8000 opcode summary: Z8000 Opcodes. (line 6) 23662* Z8000 options: Z8000 Options. (line 6) 23663* Z8000 registers: Z8000-Regs. (line 6) 23664* Z8000 support: Z8000-Dependent. (line 6) 23665* zdaoff pseudo-op, V850: V850 Opcodes. (line 99) 23666* zero register, V850: V850-Regs. (line 7) 23667* zero-terminated strings: Asciz. (line 6) 23668 23669 23670 23671Tag Table: 23672Node: Top944 23673Node: Overview1955 23674Node: Manual32486 23675Node: GNU Assembler33430 23676Node: Object Formats34601 23677Node: Command Line35053 23678Node: Input Files36140 23679Node: Object38121 23680Node: Errors39017 23681Node: Invoking40212 23682Node: a42167 23683Node: alternate44078 23684Node: D44250 23685Node: f44483 23686Node: I44991 23687Node: K45535 23688Node: L45839 23689Node: listing46578 23690Node: M48237 23691Node: MD52638 23692Node: o53064 23693Node: R53519 23694Node: statistics54549 23695Node: traditional-format54956 23696Node: v55429 23697Node: W55704 23698Node: Z56611 23699Node: Syntax57133 23700Node: Preprocessing57725 23701Node: Whitespace59288 23702Node: Comments59684 23703Node: Symbol Intro61695 23704Node: Statements62385 23705Node: Constants64374 23706Node: Characters65005 23707Node: Strings65507 23708Node: Chars67673 23709Node: Numbers68427 23710Node: Integers68967 23711Node: Bignums69623 23712Node: Flonums69979 23713Node: Sections71726 23714Node: Secs Background72104 23715Node: Ld Sections77143 23716Node: As Sections79527 23717Node: Sub-Sections80437 23718Node: bss83582 23719Node: Symbols84532 23720Node: Labels85180 23721Node: Setting Symbols85911 23722Node: Symbol Names86465 23723Node: Dot91506 23724Node: Symbol Attributes91953 23725Node: Symbol Value92690 23726Node: Symbol Type93735 23727Node: a.out Symbols94123 23728Node: Symbol Desc94385 23729Node: Symbol Other94680 23730Node: COFF Symbols94849 23731Node: SOM Symbols95522 23732Node: Expressions95964 23733Node: Empty Exprs96713 23734Node: Integer Exprs97060 23735Node: Arguments97455 23736Node: Operators98561 23737Node: Prefix Ops98896 23738Node: Infix Ops99224 23739Node: Pseudo Ops101614 23740Node: Abort107142 23741Node: ABORT (COFF)107554 23742Node: Align107762 23743Node: Altmacro110044 23744Node: Ascii111373 23745Node: Asciz111682 23746Node: Balign111927 23747Node: Byte113790 23748Node: CFI directives114038 23749Node: Comm119665 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