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  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/toolchains/hndtools-armeabi-2011.09/share/doc/arm-arm-none-eabi/html/getting-started/
1<html><head><meta http-equiv="Content-Type" content="text/html; charset=ISO-8859-1"><title>5.4.�Interrupt Vectors and Handlers</title><link rel="stylesheet" href="cs.css" type="text/css"><meta name="generator" content="DocBook XSL Stylesheets V1.74.0"><link rel="home" href="index.html" title="Sourcery CodeBench Lite"><link rel="up" href="chap-cs3.html" title="Chapter�5.�CS3&#8482;: The CodeSourcery Common Startup Code Sequence"><link rel="prev" href="sec-cs3-memory-layout.html" title="5.3.�Memory Layout"><link rel="next" href="sec-cs3-supported-boards.html" title="5.5.�Supported Boards for ARM EABI"></head><body bgcolor="white" text="black" link="#0000FF" vlink="#840084" alink="#0000FF"><div class="navheader"><table width="100%" summary="Navigation header"><tr><th colspan="3" align="center">5.4.�Interrupt Vectors and Handlers</th></tr><tr><td width="20%" align="left"><a accesskey="p" href="sec-cs3-memory-layout.html">Prev</a>�</td><th width="60%" align="center">Chapter�5.�CS3&#8482;: The CodeSourcery Common Startup Code Sequence</th><td width="20%" align="right">�<a accesskey="n" href="sec-cs3-supported-boards.html">Next</a></td></tr></table><hr></div><div class="section" lang="en"><div class="titlepage"><div><div><h2 class="title" style="clear: both"><a name="sec-cs3-interrupts"></a>5.4.�Interrupt Vectors and Handlers</h2></div></div></div><p>
2      CS3 provides standard handlers for interrupts, exceptions and
3      traps, but also allows you to define your own handlers as needed.
4      In this section, we use the term
5      <em class="firstterm">interrupt</em> as a generic term for this
6      entire class of events.
7    </p><p>
8      Different processors handle interrupts in various ways, but
9      there are two general approaches:
10      </p><div class="itemizedlist"><ul type="disc"><li><p>
11            Some processors fetch an address from an array indexed by
12            the interrupt number, and jump to that address.  We call
13            these <em class="firstterm">address vector</em> processors.
14          </p></li><li><p>
15            Others multiply the interrupt number by some constant
16            factor, add a base address, and jump directly to that
17            address.  Here, the interrupt vector consists of blocks of
18            code, so we call these <em class="firstterm">code vector</em>
19            processors.
20          </p></li><li><p>
21	    Still other processors use a more complicated descriptor
22	    mechanism for the interrupt table.
23	  </p></li></ul></div><p>
24
25      <span>
26        M-profile processors like the Cortex-M3 use the address vector
27	model.  Classic ARM processors (including ARM7/ARM9 as well as
28	Cortex-A/R series processors) are technically code vector processors.
29	However, each vector slot only holds a single instruction.  CS3
30	emulates the address vector model on these processors by placing an
31	indirect branch instruction in each slot of the real exception vector.
32      </span>
33
34      
35
36      
37      
38
39      
40
41      
42
43      The remainder of this section assumes that you have some understanding
44      of the specific requirements for your target; refer to the architecture
45      manuals if necessary.
46    </p><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="id526335"></a>5.4.1.�ARM EABI Interrupt Vector Implementation</h3></div></div></div><p>
47        On address vector processors, the CS3 library provides an array
48        of pointers to interrupt handlers named
49        <code class="varname">__cs3_interrupt_vector_<em class="replaceable"><code>form</code></em></code>,
50        where <em class="replaceable"><code>form</code></em> identifies the particular
51        processor variant the vector is appropriate for.
52        Each entry in the vector holds a reference to a symbol named
53        <code class="function">__cs3_isr_<em class="replaceable"><code>name</code></em></code>,
54        where <em class="replaceable"><code>name</code></em> is the customary name of
55        that interrupt on the processor, or a number if there is no
56        consistently used name.  
57	You can find the interrupt vector details in
58	<a class="xref" href="sec-cs3-vector-tables.html" title="5.6.�Interrupt Vector Tables">Section�5.6, &#8220;Interrupt Vector Tables&#8221;</a>.  The particular
59	vector used by a given CS3-supported board is documented
60	in the tables in <a class="xref" href="sec-cs3-supported-boards.html" title="5.5.�Supported Boards for ARM EABI">Section�5.5, &#8220;Supported Boards for ARM EABI&#8221;</a>.
61      </p><p>
62	CS3 provides a reasonable default definition for each
63        <code class="function">__cs3_isr_<em class="replaceable"><code>name</code></em></code>
64        handler.  Many of these symbols are aliased to a
65	common handler routine.  If your program stops at a default
66	interrupt handler, its name as shown in backtraces may therefore
67	not correctly reflect which interrupt occurred.
68      </p><p>
69        To override an individual handler, provide your own definition
70        for the appropriate
71        <code class="function">__cs3_isr_<em class="replaceable"><code>name</code></em></code>
72        symbol.  The definition need not be placed in any particular
73        object file section.
74      </p><p>
75        To override the entire interrupt vector, you can define
76        <code class="varname">__cs3_interrupt_vector_<em class="replaceable"><code>form</code></em></code>.
77        You must place this definition in a section named
78        <code class="literal">.cs3.interrupt_vector</code>.  The linker script
79        reports an error if the <code class="literal">.cs3.interrupt_vector</code>
80        section is empty, to ensure that the definition of
81        <code class="varname">__cs3_interrupt_vector_<em class="replaceable"><code>form</code></em></code>
82        occupies the proper section.
83      </p><p>
84        You may define the vector in C with an array of pointers using
85        the <code class="literal">section</code> attribute to place it in the
86        appropriate section.  For example, to override the interrupt
87        vector on Altera Cyclone III Cortex-M1 boards, make the following definition:
88        </p><pre class="programlisting">typedef void handler(void);
89handler *__attribute__((section (".cs3.interrupt_vector")))
90  __cs3_interrupt_vector_micro[] =
91{ ... };</pre><p>
92      </p></div><div class="section" lang="en"><div class="titlepage"><div><div><h3 class="title"><a name="sec-cs3-interrupt-handlers"></a>5.4.2.�Writing Interrupt Handlers</h3></div></div></div><p>
93        Interrupt handlers typically require special call/return and
94        register usage conventions that are target-specific and beyond
95        the scope of this document.  In many cases, normal C functions
96	cannot be used as interrupt handlers.
97	<span>
98          For example, the EABI requires that the stack be 8-byte aligned,
99	  but on some ARMv7-M processors, only 4-byte stack alignment
100	  is guaranteed when calling an interrupt vector.  This can cause
101	  subtle runtime failures, usually when 8-byte types are used.
102        </span>
103      </p><p>
104        As an alternative to writing interrupt handlers in assembly language,
105        on ARM targets they may be written in C using the
106        <code class="literal">interrupt</code>
107        
108	attribute.  This tells the compiler to generate appropriate function
109	entry and exit sequences for an interrupt handler.
110	<span>
111  	  For example, to override the
112	  <code class="function">__cs3_isr_nmi</code> handler,
113	  use the following definition:
114          <pre class="programlisting">void __attribute__ ((interrupt)) __cs3_isr_nmi (void)
115{
116  ... custom handler code ...
117}</pre>
118        </span>
119        <span>
120	  On ARM targets, the <code class="literal">interrupt</code> attribute also
121	  takes an optional parameter to specify the type of interrupt.
122        </span>
123        
124	Refer to the GCC manual for more details about attribute syntax
125	and usage.
126      </p></div></div><div class="navfooter"><hr><table width="100%" summary="Navigation footer"><tr><td width="40%" align="left"><a accesskey="p" href="sec-cs3-memory-layout.html">Prev</a>�</td><td width="20%" align="center"><a accesskey="u" href="chap-cs3.html">Up</a></td><td width="40%" align="right">�<a accesskey="n" href="sec-cs3-supported-boards.html">Next</a></td></tr><tr><td width="40%" align="left" valign="top">5.3.�Memory Layout�</td><td width="20%" align="center"><a accesskey="h" href="index.html">Home</a></td><td width="40%" align="right" valign="top">�5.5.�Supported Boards for ARM EABI</td></tr></table></div></body></html>
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