1<html lang="en"> 2<head> 3<title>SH Options - Using the GNU Compiler Collection (GCC)</title> 4<meta http-equiv="Content-Type" content="text/html"> 5<meta name="description" content="Using the GNU Compiler Collection (GCC)"> 6<meta name="generator" content="makeinfo 4.13"> 7<link title="Top" rel="start" href="index.html#Top"> 8<link rel="up" href="Submodel-Options.html#Submodel-Options" title="Submodel Options"> 9<link rel="prev" href="Score-Options.html#Score-Options" title="Score Options"> 10<link rel="next" href="Solaris-2-Options.html#Solaris-2-Options" title="Solaris 2 Options"> 11<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage"> 12<!-- 13Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 141998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 152010 Free Software Foundation, Inc. 16 17Permission is granted to copy, distribute and/or modify this document 18under the terms of the GNU Free Documentation License, Version 1.3 or 19any later version published by the Free Software Foundation; with the 20Invariant Sections being ``Funding Free Software'', the Front-Cover 21Texts being (a) (see below), and with the Back-Cover Texts being (b) 22(see below). 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GCC doesn't generate any DSP 108instructions at the moment. 109 110 <br><dt><code>-mb</code><dd><a name="index-mb-2027"></a>Compile code for the processor in big endian mode. 111 112 <br><dt><code>-ml</code><dd><a name="index-ml-2028"></a>Compile code for the processor in little endian mode. 113 114 <br><dt><code>-mdalign</code><dd><a name="index-mdalign-2029"></a>Align doubles at 64-bit boundaries. Note that this changes the calling 115conventions, and thus some functions from the standard C library will 116not work unless you recompile it first with <samp><span class="option">-mdalign</span></samp>. 117 118 <br><dt><code>-mrelax</code><dd><a name="index-mrelax-2030"></a>Shorten some address references at link time, when possible; uses the 119linker option <samp><span class="option">-relax</span></samp>. 120 121 <br><dt><code>-mbigtable</code><dd><a name="index-mbigtable-2031"></a>Use 32-bit offsets in <code>switch</code> tables. The default is to use 12216-bit offsets. 123 124 <br><dt><code>-mbitops</code><dd><a name="index-mbitops-2032"></a>Enable the use of bit manipulation instructions on SH2A. 125 126 <br><dt><code>-mfmovd</code><dd><a name="index-mfmovd-2033"></a>Enable the use of the instruction <code>fmovd</code>. Check <samp><span class="option">-mdalign</span></samp> for 127alignment constraints. 128 129 <br><dt><code>-mhitachi</code><dd><a name="index-mhitachi-2034"></a>Comply with the calling conventions defined by Renesas. 130 131 <br><dt><code>-mrenesas</code><dd><a name="index-mhitachi-2035"></a>Comply with the calling conventions defined by Renesas. 132 133 <br><dt><code>-mno-renesas</code><dd><a name="index-mhitachi-2036"></a>Comply with the calling conventions defined for GCC before the Renesas 134conventions were available. This option is the default for all 135targets of the SH toolchain except for ‘<samp><span class="samp">sh-symbianelf</span></samp>’. 136 137 <br><dt><code>-mnomacsave</code><dd><a name="index-mnomacsave-2037"></a>Mark the <code>MAC</code> register as call-clobbered, even if 138<samp><span class="option">-mhitachi</span></samp> is given. 139 140 <br><dt><code>-mieee</code><dd><a name="index-mieee-2038"></a>Increase IEEE-compliance of floating-point code. 141At the moment, this is equivalent to <samp><span class="option">-fno-finite-math-only</span></samp>. 142When generating 16 bit SH opcodes, getting IEEE-conforming results for 143comparisons of NANs / infinities incurs extra overhead in every 144floating point comparison, therefore the default is set to 145<samp><span class="option">-ffinite-math-only</span></samp>. 146 147 <br><dt><code>-minline-ic_invalidate</code><dd><a name="index-minline_002dic_005finvalidate-2039"></a>Inline code to invalidate instruction cache entries after setting up 148nested function trampolines. 149This option has no effect if -musermode is in effect and the selected 150code generation option (e.g. -m4) does not allow the use of the icbi 151instruction. 152If the selected code generation option does not allow the use of the icbi 153instruction, and -musermode is not in effect, the inlined code will 154manipulate the instruction cache address array directly with an associative 155write. This not only requires privileged mode, but it will also 156fail if the cache line had been mapped via the TLB and has become unmapped. 157 158 <br><dt><code>-misize</code><dd><a name="index-misize-2040"></a>Dump instruction size and location in the assembly code. 159 160 <br><dt><code>-mpadstruct</code><dd><a name="index-mpadstruct-2041"></a>This option is deprecated. It pads structures to multiple of 4 bytes, 161which is incompatible with the SH ABI. 162 163 <br><dt><code>-mspace</code><dd><a name="index-mspace-2042"></a>Optimize for space instead of speed. Implied by <samp><span class="option">-Os</span></samp>. 164 165 <br><dt><code>-mprefergot</code><dd><a name="index-mprefergot-2043"></a>When generating position-independent code, emit function calls using 166the Global Offset Table instead of the Procedure Linkage Table. 167 168 <br><dt><code>-musermode</code><dd><a name="index-musermode-2044"></a>Don't generate privileged mode only code; implies -mno-inline-ic_invalidate 169if the inlined code would not work in user mode. 170This is the default when the target is <code>sh-*-linux*</code>. 171 172 <br><dt><code>-multcost=</code><var>number</var><dd><a name="index-multcost_003d_0040var_007bnumber_007d-2045"></a>Set the cost to assume for a multiply insn. 173 174 <br><dt><code>-mdiv=</code><var>strategy</var><dd><a name="index-mdiv_003d_0040var_007bstrategy_007d-2046"></a>Set the division strategy to use for SHmedia code. <var>strategy</var> must be 175one of: call, call2, fp, inv, inv:minlat, inv20u, inv20l, inv:call, 176inv:call2, inv:fp . 177"fp" performs the operation in floating point. This has a very high latency, 178but needs only a few instructions, so it might be a good choice if 179your code has enough easily exploitable ILP to allow the compiler to 180schedule the floating point instructions together with other instructions. 181Division by zero causes a floating point exception. 182"inv" uses integer operations to calculate the inverse of the divisor, 183and then multiplies the dividend with the inverse. This strategy allows 184cse and hoisting of the inverse calculation. Division by zero calculates 185an unspecified result, but does not trap. 186"inv:minlat" is a variant of "inv" where if no cse / hoisting opportunities 187have been found, or if the entire operation has been hoisted to the same 188place, the last stages of the inverse calculation are intertwined with the 189final multiply to reduce the overall latency, at the expense of using a few 190more instructions, and thus offering fewer scheduling opportunities with 191other code. 192"call" calls a library function that usually implements the inv:minlat 193strategy. 194This gives high code density for m5-*media-nofpu compilations. 195"call2" uses a different entry point of the same library function, where it 196assumes that a pointer to a lookup table has already been set up, which 197exposes the pointer load to cse / code hoisting optimizations. 198"inv:call", "inv:call2" and "inv:fp" all use the "inv" algorithm for initial 199code generation, but if the code stays unoptimized, revert to the "call", 200"call2", or "fp" strategies, respectively. Note that the 201potentially-trapping side effect of division by zero is carried by a 202separate instruction, so it is possible that all the integer instructions 203are hoisted out, but the marker for the side effect stays where it is. 204A recombination to fp operations or a call is not possible in that case. 205"inv20u" and "inv20l" are variants of the "inv:minlat" strategy. In the case 206that the inverse calculation was nor separated from the multiply, they speed 207up division where the dividend fits into 20 bits (plus sign where applicable), 208by inserting a test to skip a number of operations in this case; this test 209slows down the case of larger dividends. inv20u assumes the case of a such 210a small dividend to be unlikely, and inv20l assumes it to be likely. 211 212 <br><dt><code>-maccumulate-outgoing-args</code><dd><a name="index-maccumulate_002doutgoing_002dargs-2047"></a>Reserve space once for outgoing arguments in the function prologue rather 213than around each call. Generally beneficial for performance and size. Also 214needed for unwinding to avoid changing the stack frame around conditional code. 215 216 <br><dt><code>-mdivsi3_libfunc=</code><var>name</var><dd><a name="index-mdivsi3_005flibfunc_003d_0040var_007bname_007d-2048"></a>Set the name of the library function used for 32 bit signed division to 217<var>name</var>. This only affect the name used in the call and inv:call 218division strategies, and the compiler will still expect the same 219sets of input/output/clobbered registers as if this option was not present. 220 221 <br><dt><code>-mfixed-range=</code><var>register-range</var><dd><a name="index-mfixed_002drange-2049"></a>Generate code treating the given register range as fixed registers. 222A fixed register is one that the register allocator can not use. This is 223useful when compiling kernel code. A register range is specified as 224two registers separated by a dash. Multiple register ranges can be 225specified separated by a comma. 226 227 <br><dt><code>-madjust-unroll</code><dd><a name="index-madjust_002dunroll-2050"></a>Throttle unrolling to avoid thrashing target registers. 228This option only has an effect if the gcc code base supports the 229TARGET_ADJUST_UNROLL_MAX target hook. 230 231 <br><dt><code>-mindexed-addressing</code><dd><a name="index-mindexed_002daddressing-2051"></a>Enable the use of the indexed addressing mode for SHmedia32/SHcompact. 232This is only safe if the hardware and/or OS implement 32 bit wrap-around 233semantics for the indexed addressing mode. The architecture allows the 234implementation of processors with 64 bit MMU, which the OS could use to 235get 32 bit addressing, but since no current hardware implementation supports 236this or any other way to make the indexed addressing mode safe to use in 237the 32 bit ABI, the default is -mno-indexed-addressing. 238 239 <br><dt><code>-mgettrcost=</code><var>number</var><dd><a name="index-mgettrcost_003d_0040var_007bnumber_007d-2052"></a>Set the cost assumed for the gettr instruction to <var>number</var>. 240The default is 2 if <samp><span class="option">-mpt-fixed</span></samp> is in effect, 100 otherwise. 241 242 <br><dt><code>-mpt-fixed</code><dd><a name="index-mpt_002dfixed-2053"></a>Assume pt* instructions won't trap. This will generally generate better 243scheduled code, but is unsafe on current hardware. The current architecture 244definition says that ptabs and ptrel trap when the target anded with 3 is 3. 245This has the unintentional effect of making it unsafe to schedule ptabs / 246ptrel before a branch, or hoist it out of a loop. For example, 247__do_global_ctors, a part of libgcc that runs constructors at program 248startup, calls functions in a list which is delimited by −1. With the 249-mpt-fixed option, the ptabs will be done before testing against −1. 250That means that all the constructors will be run a bit quicker, but when 251the loop comes to the end of the list, the program crashes because ptabs 252loads −1 into a target register. Since this option is unsafe for any 253hardware implementing the current architecture specification, the default 254is -mno-pt-fixed. Unless the user specifies a specific cost with 255<samp><span class="option">-mgettrcost</span></samp>, -mno-pt-fixed also implies <samp><span class="option">-mgettrcost=100</span></samp>; 256this deters register allocation using target registers for storing 257ordinary integers. 258 259 <br><dt><code>-minvalid-symbols</code><dd><a name="index-minvalid_002dsymbols-2054"></a>Assume symbols might be invalid. Ordinary function symbols generated by 260the compiler will always be valid to load with movi/shori/ptabs or 261movi/shori/ptrel, but with assembler and/or linker tricks it is possible 262to generate symbols that will cause ptabs / ptrel to trap. 263This option is only meaningful when <samp><span class="option">-mno-pt-fixed</span></samp> is in effect. 264It will then prevent cross-basic-block cse, hoisting and most scheduling 265of symbol loads. The default is <samp><span class="option">-mno-invalid-symbols</span></samp>. 266</dl> 267 268 </body></html> 269 270