1<html lang="en"> 2<head> 3<title>MIPS DSP Built-in Functions - Using the GNU Compiler Collection (GCC)</title> 4<meta http-equiv="Content-Type" content="text/html"> 5<meta name="description" content="Using the GNU Compiler Collection (GCC)"> 6<meta name="generator" content="makeinfo 4.13"> 7<link title="Top" rel="start" href="index.html#Top"> 8<link rel="up" href="Target-Builtins.html#Target-Builtins" title="Target Builtins"> 9<link rel="prev" href="X86-Built_002din-Functions.html#X86-Built_002din-Functions" title="X86 Built-in Functions"> 10<link rel="next" href="MIPS-Paired_002dSingle-Support.html#MIPS-Paired_002dSingle-Support" title="MIPS Paired-Single Support"> 11<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage"> 12<!-- 13Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 141998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 152010 Free Software Foundation, Inc. 16 17Permission is granted to copy, distribute and/or modify this document 18under the terms of the GNU Free Documentation License, Version 1.3 or 19any later version published by the Free Software Foundation; with the 20Invariant Sections being ``Funding Free Software'', the Front-Cover 21Texts being (a) (see below), and with the Back-Cover Texts being (b) 22(see below). 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It provides instructions that operate on packed 648-bit/16-bit integer data, Q7, Q15 and Q31 fractional data. 65 66 <p>GCC supports MIPS DSP operations using both the generic 67vector extensions (see <a href="Vector-Extensions.html#Vector-Extensions">Vector Extensions</a>) and a collection of 68MIPS-specific built-in functions. Both kinds of support are 69enabled by the <samp><span class="option">-mdsp</span></samp> command-line option. 70 71 <p>Revision 2 of the ASE was introduced in the second half of 2006. 72This revision adds extra instructions to the original ASE, but is 73otherwise backwards-compatible with it. You can select revision 2 74using the command-line option <samp><span class="option">-mdspr2</span></samp>; this option implies 75<samp><span class="option">-mdsp</span></samp>. 76 77 <p>The SCOUNT and POS bits of the DSP control register are global. The 78WRDSP, EXTPDP, EXTPDPV and MTHLIP instructions modify the SCOUNT and 79POS bits. During optimization, the compiler will not delete these 80instructions and it will not delete calls to functions containing 81these instructions. 82 83 <p>At present, GCC only provides support for operations on 32-bit 84vectors. The vector type associated with 8-bit integer data is 85usually called <code>v4i8</code>, the vector type associated with Q7 86is usually called <code>v4q7</code>, the vector type associated with 16-bit 87integer data is usually called <code>v2i16</code>, and the vector type 88associated with Q15 is usually called <code>v2q15</code>. They can be 89defined in C as follows: 90 91<pre class="smallexample"> typedef signed char v4i8 __attribute__ ((vector_size(4))); 92 typedef signed char v4q7 __attribute__ ((vector_size(4))); 93 typedef short v2i16 __attribute__ ((vector_size(4))); 94 typedef short v2q15 __attribute__ ((vector_size(4))); 95</pre> 96 <p><code>v4i8</code>, <code>v4q7</code>, <code>v2i16</code> and <code>v2q15</code> values are 97initialized in the same way as aggregates. For example: 98 99<pre class="smallexample"> v4i8 a = {1, 2, 3, 4}; 100 v4i8 b; 101 b = (v4i8) {5, 6, 7, 8}; 102 103 v2q15 c = {0x0fcb, 0x3a75}; 104 v2q15 d; 105 d = (v2q15) {0.1234 * 0x1.0p15, 0.4567 * 0x1.0p15}; 106</pre> 107 <p><em>Note:</em> The CPU's endianness determines the order in which values 108are packed. On little-endian targets, the first value is the least 109significant and the last value is the most significant. The opposite 110order applies to big-endian targets. For example, the code above will 111set the lowest byte of <code>a</code> to <code>1</code> on little-endian targets 112and <code>4</code> on big-endian targets. 113 114 <p><em>Note:</em> Q7, Q15 and Q31 values must be initialized with their integer 115representation. As shown in this example, the integer representation 116of a Q7 value can be obtained by multiplying the fractional value by 117<code>0x1.0p7</code>. The equivalent for Q15 values is to multiply by 118<code>0x1.0p15</code>. The equivalent for Q31 values is to multiply by 119<code>0x1.0p31</code>. 120 121 <p>The table below lists the <code>v4i8</code> and <code>v2q15</code> operations for which 122hardware support exists. <code>a</code> and <code>b</code> are <code>v4i8</code> values, 123and <code>c</code> and <code>d</code> are <code>v2q15</code> values. 124 125 <p><table summary=""><tr align="left"><td valign="top" width="50%">C code </td><td valign="top" width="50%">MIPS instruction 126<br></td></tr><tr align="left"><td valign="top" width="50%"><code>a + b</code> </td><td valign="top" width="50%"><code>addu.qb</code> 127<br></td></tr><tr align="left"><td valign="top" width="50%"><code>c + d</code> </td><td valign="top" width="50%"><code>addq.ph</code> 128<br></td></tr><tr align="left"><td valign="top" width="50%"><code>a - b</code> </td><td valign="top" width="50%"><code>subu.qb</code> 129<br></td></tr><tr align="left"><td valign="top" width="50%"><code>c - d</code> </td><td valign="top" width="50%"><code>subq.ph</code> 130 <br></td></tr></table> 131 132 <p>The table below lists the <code>v2i16</code> operation for which 133hardware support exists for the DSP ASE REV 2. <code>e</code> and <code>f</code> are 134<code>v2i16</code> values. 135 136 <p><table summary=""><tr align="left"><td valign="top" width="50%">C code </td><td valign="top" width="50%">MIPS instruction 137<br></td></tr><tr align="left"><td valign="top" width="50%"><code>e * f</code> </td><td valign="top" width="50%"><code>mul.ph</code> 138 <br></td></tr></table> 139 140 <p>It is easier to describe the DSP built-in functions if we first define 141the following types: 142 143<pre class="smallexample"> typedef int q31; 144 typedef int i32; 145 typedef unsigned int ui32; 146 typedef long long a64; 147</pre> 148 <p><code>q31</code> and <code>i32</code> are actually the same as <code>int</code>, but we 149use <code>q31</code> to indicate a Q31 fractional value and <code>i32</code> to 150indicate a 32-bit integer value. Similarly, <code>a64</code> is the same as 151<code>long long</code>, but we use <code>a64</code> to indicate values that will 152be placed in one of the four DSP accumulators (<code>$ac0</code>, 153<code>$ac1</code>, <code>$ac2</code> or <code>$ac3</code>). 154 155 <p>Also, some built-in functions prefer or require immediate numbers as 156parameters, because the corresponding DSP instructions accept both immediate 157numbers and register operands, or accept immediate numbers only. The 158immediate parameters are listed as follows. 159 160<pre class="smallexample"> imm0_3: 0 to 3. 161 imm0_7: 0 to 7. 162 imm0_15: 0 to 15. 163 imm0_31: 0 to 31. 164 imm0_63: 0 to 63. 165 imm0_255: 0 to 255. 166 imm_n32_31: -32 to 31. 167 imm_n512_511: -512 to 511. 168</pre> 169 <p>The following built-in functions map directly to a particular MIPS DSP 170instruction. Please refer to the architecture specification 171for details on what each instruction does. 172 173<pre class="smallexample"> v2q15 __builtin_mips_addq_ph (v2q15, v2q15) 174 v2q15 __builtin_mips_addq_s_ph (v2q15, v2q15) 175 q31 __builtin_mips_addq_s_w (q31, q31) 176 v4i8 __builtin_mips_addu_qb (v4i8, v4i8) 177 v4i8 __builtin_mips_addu_s_qb (v4i8, v4i8) 178 v2q15 __builtin_mips_subq_ph (v2q15, v2q15) 179 v2q15 __builtin_mips_subq_s_ph (v2q15, v2q15) 180 q31 __builtin_mips_subq_s_w (q31, q31) 181 v4i8 __builtin_mips_subu_qb (v4i8, v4i8) 182 v4i8 __builtin_mips_subu_s_qb (v4i8, v4i8) 183 i32 __builtin_mips_addsc (i32, i32) 184 i32 __builtin_mips_addwc (i32, i32) 185 i32 __builtin_mips_modsub (i32, i32) 186 i32 __builtin_mips_raddu_w_qb (v4i8) 187 v2q15 __builtin_mips_absq_s_ph (v2q15) 188 q31 __builtin_mips_absq_s_w (q31) 189 v4i8 __builtin_mips_precrq_qb_ph (v2q15, v2q15) 190 v2q15 __builtin_mips_precrq_ph_w (q31, q31) 191 v2q15 __builtin_mips_precrq_rs_ph_w (q31, q31) 192 v4i8 __builtin_mips_precrqu_s_qb_ph (v2q15, v2q15) 193 q31 __builtin_mips_preceq_w_phl (v2q15) 194 q31 __builtin_mips_preceq_w_phr (v2q15) 195 v2q15 __builtin_mips_precequ_ph_qbl (v4i8) 196 v2q15 __builtin_mips_precequ_ph_qbr (v4i8) 197 v2q15 __builtin_mips_precequ_ph_qbla (v4i8) 198 v2q15 __builtin_mips_precequ_ph_qbra (v4i8) 199 v2q15 __builtin_mips_preceu_ph_qbl (v4i8) 200 v2q15 __builtin_mips_preceu_ph_qbr (v4i8) 201 v2q15 __builtin_mips_preceu_ph_qbla (v4i8) 202 v2q15 __builtin_mips_preceu_ph_qbra (v4i8) 203 v4i8 __builtin_mips_shll_qb (v4i8, imm0_7) 204 v4i8 __builtin_mips_shll_qb (v4i8, i32) 205 v2q15 __builtin_mips_shll_ph (v2q15, imm0_15) 206 v2q15 __builtin_mips_shll_ph (v2q15, i32) 207 v2q15 __builtin_mips_shll_s_ph (v2q15, imm0_15) 208 v2q15 __builtin_mips_shll_s_ph (v2q15, i32) 209 q31 __builtin_mips_shll_s_w (q31, imm0_31) 210 q31 __builtin_mips_shll_s_w (q31, i32) 211 v4i8 __builtin_mips_shrl_qb (v4i8, imm0_7) 212 v4i8 __builtin_mips_shrl_qb (v4i8, i32) 213 v2q15 __builtin_mips_shra_ph (v2q15, imm0_15) 214 v2q15 __builtin_mips_shra_ph (v2q15, i32) 215 v2q15 __builtin_mips_shra_r_ph (v2q15, imm0_15) 216 v2q15 __builtin_mips_shra_r_ph (v2q15, i32) 217 q31 __builtin_mips_shra_r_w (q31, imm0_31) 218 q31 __builtin_mips_shra_r_w (q31, i32) 219 v2q15 __builtin_mips_muleu_s_ph_qbl (v4i8, v2q15) 220 v2q15 __builtin_mips_muleu_s_ph_qbr (v4i8, v2q15) 221 v2q15 __builtin_mips_mulq_rs_ph (v2q15, v2q15) 222 q31 __builtin_mips_muleq_s_w_phl (v2q15, v2q15) 223 q31 __builtin_mips_muleq_s_w_phr (v2q15, v2q15) 224 a64 __builtin_mips_dpau_h_qbl (a64, v4i8, v4i8) 225 a64 __builtin_mips_dpau_h_qbr (a64, v4i8, v4i8) 226 a64 __builtin_mips_dpsu_h_qbl (a64, v4i8, v4i8) 227 a64 __builtin_mips_dpsu_h_qbr (a64, v4i8, v4i8) 228 a64 __builtin_mips_dpaq_s_w_ph (a64, v2q15, v2q15) 229 a64 __builtin_mips_dpaq_sa_l_w (a64, q31, q31) 230 a64 __builtin_mips_dpsq_s_w_ph (a64, v2q15, v2q15) 231 a64 __builtin_mips_dpsq_sa_l_w (a64, q31, q31) 232 a64 __builtin_mips_mulsaq_s_w_ph (a64, v2q15, v2q15) 233 a64 __builtin_mips_maq_s_w_phl (a64, v2q15, v2q15) 234 a64 __builtin_mips_maq_s_w_phr (a64, v2q15, v2q15) 235 a64 __builtin_mips_maq_sa_w_phl (a64, v2q15, v2q15) 236 a64 __builtin_mips_maq_sa_w_phr (a64, v2q15, v2q15) 237 i32 __builtin_mips_bitrev (i32) 238 i32 __builtin_mips_insv (i32, i32) 239 v4i8 __builtin_mips_repl_qb (imm0_255) 240 v4i8 __builtin_mips_repl_qb (i32) 241 v2q15 __builtin_mips_repl_ph (imm_n512_511) 242 v2q15 __builtin_mips_repl_ph (i32) 243 void __builtin_mips_cmpu_eq_qb (v4i8, v4i8) 244 void __builtin_mips_cmpu_lt_qb (v4i8, v4i8) 245 void __builtin_mips_cmpu_le_qb (v4i8, v4i8) 246 i32 __builtin_mips_cmpgu_eq_qb (v4i8, v4i8) 247 i32 __builtin_mips_cmpgu_lt_qb (v4i8, v4i8) 248 i32 __builtin_mips_cmpgu_le_qb (v4i8, v4i8) 249 void __builtin_mips_cmp_eq_ph (v2q15, v2q15) 250 void __builtin_mips_cmp_lt_ph (v2q15, v2q15) 251 void __builtin_mips_cmp_le_ph (v2q15, v2q15) 252 v4i8 __builtin_mips_pick_qb (v4i8, v4i8) 253 v2q15 __builtin_mips_pick_ph (v2q15, v2q15) 254 v2q15 __builtin_mips_packrl_ph (v2q15, v2q15) 255 i32 __builtin_mips_extr_w (a64, imm0_31) 256 i32 __builtin_mips_extr_w (a64, i32) 257 i32 __builtin_mips_extr_r_w (a64, imm0_31) 258 i32 __builtin_mips_extr_s_h (a64, i32) 259 i32 __builtin_mips_extr_rs_w (a64, imm0_31) 260 i32 __builtin_mips_extr_rs_w (a64, i32) 261 i32 __builtin_mips_extr_s_h (a64, imm0_31) 262 i32 __builtin_mips_extr_r_w (a64, i32) 263 i32 __builtin_mips_extp (a64, imm0_31) 264 i32 __builtin_mips_extp (a64, i32) 265 i32 __builtin_mips_extpdp (a64, imm0_31) 266 i32 __builtin_mips_extpdp (a64, i32) 267 a64 __builtin_mips_shilo (a64, imm_n32_31) 268 a64 __builtin_mips_shilo (a64, i32) 269 a64 __builtin_mips_mthlip (a64, i32) 270 void __builtin_mips_wrdsp (i32, imm0_63) 271 i32 __builtin_mips_rddsp (imm0_63) 272 i32 __builtin_mips_lbux (void *, i32) 273 i32 __builtin_mips_lhx (void *, i32) 274 i32 __builtin_mips_lwx (void *, i32) 275 i32 __builtin_mips_bposge32 (void) 276 a64 __builtin_mips_madd (a64, i32, i32); 277 a64 __builtin_mips_maddu (a64, ui32, ui32); 278 a64 __builtin_mips_msub (a64, i32, i32); 279 a64 __builtin_mips_msubu (a64, ui32, ui32); 280 a64 __builtin_mips_mult (i32, i32); 281 a64 __builtin_mips_multu (ui32, ui32); 282</pre> 283 <p>The following built-in functions map directly to a particular MIPS DSP REV 2 284instruction. Please refer to the architecture specification 285for details on what each instruction does. 286 287<pre class="smallexample"> v4q7 __builtin_mips_absq_s_qb (v4q7); 288 v2i16 __builtin_mips_addu_ph (v2i16, v2i16); 289 v2i16 __builtin_mips_addu_s_ph (v2i16, v2i16); 290 v4i8 __builtin_mips_adduh_qb (v4i8, v4i8); 291 v4i8 __builtin_mips_adduh_r_qb (v4i8, v4i8); 292 i32 __builtin_mips_append (i32, i32, imm0_31); 293 i32 __builtin_mips_balign (i32, i32, imm0_3); 294 i32 __builtin_mips_cmpgdu_eq_qb (v4i8, v4i8); 295 i32 __builtin_mips_cmpgdu_lt_qb (v4i8, v4i8); 296 i32 __builtin_mips_cmpgdu_le_qb (v4i8, v4i8); 297 a64 __builtin_mips_dpa_w_ph (a64, v2i16, v2i16); 298 a64 __builtin_mips_dps_w_ph (a64, v2i16, v2i16); 299 v2i16 __builtin_mips_mul_ph (v2i16, v2i16); 300 v2i16 __builtin_mips_mul_s_ph (v2i16, v2i16); 301 q31 __builtin_mips_mulq_rs_w (q31, q31); 302 v2q15 __builtin_mips_mulq_s_ph (v2q15, v2q15); 303 q31 __builtin_mips_mulq_s_w (q31, q31); 304 a64 __builtin_mips_mulsa_w_ph (a64, v2i16, v2i16); 305 v4i8 __builtin_mips_precr_qb_ph (v2i16, v2i16); 306 v2i16 __builtin_mips_precr_sra_ph_w (i32, i32, imm0_31); 307 v2i16 __builtin_mips_precr_sra_r_ph_w (i32, i32, imm0_31); 308 i32 __builtin_mips_prepend (i32, i32, imm0_31); 309 v4i8 __builtin_mips_shra_qb (v4i8, imm0_7); 310 v4i8 __builtin_mips_shra_r_qb (v4i8, imm0_7); 311 v4i8 __builtin_mips_shra_qb (v4i8, i32); 312 v4i8 __builtin_mips_shra_r_qb (v4i8, i32); 313 v2i16 __builtin_mips_shrl_ph (v2i16, imm0_15); 314 v2i16 __builtin_mips_shrl_ph (v2i16, i32); 315 v2i16 __builtin_mips_subu_ph (v2i16, v2i16); 316 v2i16 __builtin_mips_subu_s_ph (v2i16, v2i16); 317 v4i8 __builtin_mips_subuh_qb (v4i8, v4i8); 318 v4i8 __builtin_mips_subuh_r_qb (v4i8, v4i8); 319 v2q15 __builtin_mips_addqh_ph (v2q15, v2q15); 320 v2q15 __builtin_mips_addqh_r_ph (v2q15, v2q15); 321 q31 __builtin_mips_addqh_w (q31, q31); 322 q31 __builtin_mips_addqh_r_w (q31, q31); 323 v2q15 __builtin_mips_subqh_ph (v2q15, v2q15); 324 v2q15 __builtin_mips_subqh_r_ph (v2q15, v2q15); 325 q31 __builtin_mips_subqh_w (q31, q31); 326 q31 __builtin_mips_subqh_r_w (q31, q31); 327 a64 __builtin_mips_dpax_w_ph (a64, v2i16, v2i16); 328 a64 __builtin_mips_dpsx_w_ph (a64, v2i16, v2i16); 329 a64 __builtin_mips_dpaqx_s_w_ph (a64, v2q15, v2q15); 330 a64 __builtin_mips_dpaqx_sa_w_ph (a64, v2q15, v2q15); 331 a64 __builtin_mips_dpsqx_s_w_ph (a64, v2q15, v2q15); 332 a64 __builtin_mips_dpsqx_sa_w_ph (a64, v2q15, v2q15); 333</pre> 334 </body></html> 335 336