1<html lang="en"> 2<head> 3<title>M680x0 Options - Using the GNU Compiler Collection (GCC)</title> 4<meta http-equiv="Content-Type" content="text/html"> 5<meta name="description" content="Using the GNU Compiler Collection (GCC)"> 6<meta name="generator" content="makeinfo 4.13"> 7<link title="Top" rel="start" href="index.html#Top"> 8<link rel="up" href="Submodel-Options.html#Submodel-Options" title="Submodel Options"> 9<link rel="prev" href="M32R_002fD-Options.html#M32R_002fD-Options" title="M32R/D Options"> 10<link rel="next" href="M68hc1x-Options.html#M68hc1x-Options" title="M68hc1x Options"> 11<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage"> 12<!-- 13Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 141998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 152010 Free Software Foundation, Inc. 16 17Permission is granted to copy, distribute and/or modify this document 18under the terms of the GNU Free Documentation License, Version 1.3 or 19any later version published by the Free Software Foundation; with the 20Invariant Sections being ``Funding Free Software'', the Front-Cover 21Texts being (a) (see below), and with the Back-Cover Texts being (b) 22(see below). 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Permissible values of <var>arch</var> for M680x0 69architectures are: ‘<samp><span class="samp">68000</span></samp>’, ‘<samp><span class="samp">68010</span></samp>’, ‘<samp><span class="samp">68020</span></samp>’, 70‘<samp><span class="samp">68030</span></samp>’, ‘<samp><span class="samp">68040</span></samp>’, ‘<samp><span class="samp">68060</span></samp>’ and ‘<samp><span class="samp">cpu32</span></samp>’. ColdFire 71architectures are selected according to Freescale's ISA classification 72and the permissible values are: ‘<samp><span class="samp">isaa</span></samp>’, ‘<samp><span class="samp">isaaplus</span></samp>’, 73‘<samp><span class="samp">isab</span></samp>’ and ‘<samp><span class="samp">isac</span></samp>’. 74 75 <p>gcc defines a macro ‘<samp><span class="samp">__mcf</span><var>arch</var><span class="samp">__</span></samp>’ whenever it is generating 76code for a ColdFire target. The <var>arch</var> in this macro is one of the 77<samp><span class="option">-march</span></samp> arguments given above. 78 79 <p>When used together, <samp><span class="option">-march</span></samp> and <samp><span class="option">-mtune</span></samp> select code 80that runs on a family of similar processors but that is optimized 81for a particular microarchitecture. 82 83 <br><dt><code>-mcpu=</code><var>cpu</var><dd><a name="index-mcpu-1505"></a>Generate code for a specific M680x0 or ColdFire processor. 84The M680x0 <var>cpu</var>s are: ‘<samp><span class="samp">68000</span></samp>’, ‘<samp><span class="samp">68010</span></samp>’, ‘<samp><span class="samp">68020</span></samp>’, 85‘<samp><span class="samp">68030</span></samp>’, ‘<samp><span class="samp">68040</span></samp>’, ‘<samp><span class="samp">68060</span></samp>’, ‘<samp><span class="samp">68302</span></samp>’, ‘<samp><span class="samp">68332</span></samp>’ 86and ‘<samp><span class="samp">cpu32</span></samp>’. The ColdFire <var>cpu</var>s are given by the table 87below, which also classifies the CPUs into families: 88 89 <p><table summary=""><tr align="left"><td valign="top" width="20%"><strong>Family</strong> </td><td valign="top" width="80%"><strong>‘</strong><samp><span class="samp">-mcpu</span></samp><strong>’ arguments</strong> 90<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">51</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">51</span></samp>’ ‘<samp><span class="samp">51ac</span></samp>’ ‘<samp><span class="samp">51ag</span></samp>’ ‘<samp><span class="samp">51cn</span></samp>’ ‘<samp><span class="samp">51em</span></samp>’ ‘<samp><span class="samp">51je</span></samp>’ ‘<samp><span class="samp">51jf</span></samp>’ ‘<samp><span class="samp">51jg</span></samp>’ ‘<samp><span class="samp">51jm</span></samp>’ ‘<samp><span class="samp">51mm</span></samp>’ ‘<samp><span class="samp">51qe</span></samp>’ ‘<samp><span class="samp">51qm</span></samp>’ 91<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5206</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5202</span></samp>’ ‘<samp><span class="samp">5204</span></samp>’ ‘<samp><span class="samp">5206</span></samp>’ 92<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5206e</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5206e</span></samp>’ 93<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5208</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5207</span></samp>’ ‘<samp><span class="samp">5208</span></samp>’ 94<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5211a</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5210a</span></samp>’ ‘<samp><span class="samp">5211a</span></samp>’ 95<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5213</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5211</span></samp>’ ‘<samp><span class="samp">5212</span></samp>’ ‘<samp><span class="samp">5213</span></samp>’ 96<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5216</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5214</span></samp>’ ‘<samp><span class="samp">5216</span></samp>’ 97<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">52235</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">52230</span></samp>’ ‘<samp><span class="samp">52231</span></samp>’ ‘<samp><span class="samp">52232</span></samp>’ ‘<samp><span class="samp">52233</span></samp>’ ‘<samp><span class="samp">52234</span></samp>’ ‘<samp><span class="samp">52235</span></samp>’ 98<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5225</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5224</span></samp>’ ‘<samp><span class="samp">5225</span></samp>’ 99<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">52259</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">52252</span></samp>’ ‘<samp><span class="samp">52254</span></samp>’ ‘<samp><span class="samp">52255</span></samp>’ ‘<samp><span class="samp">52256</span></samp>’ ‘<samp><span class="samp">52258</span></samp>’ ‘<samp><span class="samp">52259</span></samp>’ 100<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5235</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5232</span></samp>’ ‘<samp><span class="samp">5233</span></samp>’ ‘<samp><span class="samp">5234</span></samp>’ ‘<samp><span class="samp">5235</span></samp>’ ‘<samp><span class="samp">523x</span></samp>’ 101<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5249</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5249</span></samp>’ 102<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5250</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5250</span></samp>’ 103<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5271</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5270</span></samp>’ ‘<samp><span class="samp">5271</span></samp>’ 104<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5272</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5272</span></samp>’ 105<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5275</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5274</span></samp>’ ‘<samp><span class="samp">5275</span></samp>’ 106<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5282</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5280</span></samp>’ ‘<samp><span class="samp">5281</span></samp>’ ‘<samp><span class="samp">5282</span></samp>’ ‘<samp><span class="samp">528x</span></samp>’ 107<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">53017</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">53011</span></samp>’ ‘<samp><span class="samp">53012</span></samp>’ ‘<samp><span class="samp">53013</span></samp>’ ‘<samp><span class="samp">53014</span></samp>’ ‘<samp><span class="samp">53015</span></samp>’ ‘<samp><span class="samp">53016</span></samp>’ ‘<samp><span class="samp">53017</span></samp>’ 108<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5307</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5307</span></samp>’ 109<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5329</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5327</span></samp>’ ‘<samp><span class="samp">5328</span></samp>’ ‘<samp><span class="samp">5329</span></samp>’ ‘<samp><span class="samp">532x</span></samp>’ 110<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5373</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5372</span></samp>’ ‘<samp><span class="samp">5373</span></samp>’ ‘<samp><span class="samp">537x</span></samp>’ 111<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5407</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5407</span></samp>’ 112<br></td></tr><tr align="left"><td valign="top" width="20%">‘<samp><span class="samp">5475</span></samp>’ </td><td valign="top" width="80%">‘<samp><span class="samp">5470</span></samp>’ ‘<samp><span class="samp">5471</span></samp>’ ‘<samp><span class="samp">5472</span></samp>’ ‘<samp><span class="samp">5473</span></samp>’ ‘<samp><span class="samp">5474</span></samp>’ ‘<samp><span class="samp">5475</span></samp>’ ‘<samp><span class="samp">547x</span></samp>’ ‘<samp><span class="samp">5480</span></samp>’ ‘<samp><span class="samp">5481</span></samp>’ ‘<samp><span class="samp">5482</span></samp>’ ‘<samp><span class="samp">5483</span></samp>’ ‘<samp><span class="samp">5484</span></samp>’ ‘<samp><span class="samp">5485</span></samp>’ 113 <br></td></tr></table> 114 115 <p><samp><span class="option">-mcpu=</span><var>cpu</var></samp> overrides <samp><span class="option">-march=</span><var>arch</var></samp> if 116<var>arch</var> is compatible with <var>cpu</var>. Other combinations of 117<samp><span class="option">-mcpu</span></samp> and <samp><span class="option">-march</span></samp> are rejected. 118 119 <p>gcc defines the macro ‘<samp><span class="samp">__mcf_cpu_</span><var>cpu</var></samp>’ when ColdFire target 120<var>cpu</var> is selected. It also defines ‘<samp><span class="samp">__mcf_family_</span><var>family</var></samp>’, 121where the value of <var>family</var> is given by the table above. 122 123 <br><dt><code>-mtune=</code><var>tune</var><dd><a name="index-mtune-1506"></a>Tune the code for a particular microarchitecture, within the 124constraints set by <samp><span class="option">-march</span></samp> and <samp><span class="option">-mcpu</span></samp>. 125The M680x0 microarchitectures are: ‘<samp><span class="samp">68000</span></samp>’, ‘<samp><span class="samp">68010</span></samp>’, 126‘<samp><span class="samp">68020</span></samp>’, ‘<samp><span class="samp">68030</span></samp>’, ‘<samp><span class="samp">68040</span></samp>’, ‘<samp><span class="samp">68060</span></samp>’ 127and ‘<samp><span class="samp">cpu32</span></samp>’. The ColdFire microarchitectures 128are: ‘<samp><span class="samp">cfv1</span></samp>’, ‘<samp><span class="samp">cfv2</span></samp>’, ‘<samp><span class="samp">cfv3</span></samp>’, ‘<samp><span class="samp">cfv4</span></samp>’ and ‘<samp><span class="samp">cfv4e</span></samp>’. 129 130 <p>You can also use <samp><span class="option">-mtune=68020-40</span></samp> for code that needs 131to run relatively well on 68020, 68030 and 68040 targets. 132<samp><span class="option">-mtune=68020-60</span></samp> is similar but includes 68060 targets 133as well. These two options select the same tuning decisions as 134<samp><span class="option">-m68020-40</span></samp> and <samp><span class="option">-m68020-60</span></samp> respectively. 135 136 <p>gcc defines the macros ‘<samp><span class="samp">__mc</span><var>arch</var></samp>’ and ‘<samp><span class="samp">__mc</span><var>arch</var><span class="samp">__</span></samp>’ 137when tuning for 680x0 architecture <var>arch</var>. It also defines 138‘<samp><span class="samp">mc</span><var>arch</var></samp>’ unless either <samp><span class="option">-ansi</span></samp> or a non-GNU <samp><span class="option">-std</span></samp> 139option is used. If gcc is tuning for a range of architectures, 140as selected by <samp><span class="option">-mtune=68020-40</span></samp> or <samp><span class="option">-mtune=68020-60</span></samp>, 141it defines the macros for every architecture in the range. 142 143 <p>gcc also defines the macro ‘<samp><span class="samp">__m</span><var>uarch</var><span class="samp">__</span></samp>’ when tuning for 144ColdFire microarchitecture <var>uarch</var>, where <var>uarch</var> is one 145of the arguments given above. 146 147 <br><dt><code>-m68000</code><dt><code>-mc68000</code><dd><a name="index-m68000-1507"></a><a name="index-mc68000-1508"></a>Generate output for a 68000. This is the default 148when the compiler is configured for 68000-based systems. 149It is equivalent to <samp><span class="option">-march=68000</span></samp>. 150 151 <p>Use this option for microcontrollers with a 68000 or EC000 core, 152including the 68008, 68302, 68306, 68307, 68322, 68328 and 68356. 153 154 <br><dt><code>-m68010</code><dd><a name="index-m68010-1509"></a>Generate output for a 68010. This is the default 155when the compiler is configured for 68010-based systems. 156It is equivalent to <samp><span class="option">-march=68010</span></samp>. 157 158 <br><dt><code>-m68020</code><dt><code>-mc68020</code><dd><a name="index-m68020-1510"></a><a name="index-mc68020-1511"></a>Generate output for a 68020. This is the default 159when the compiler is configured for 68020-based systems. 160It is equivalent to <samp><span class="option">-march=68020</span></samp>. 161 162 <br><dt><code>-m68030</code><dd><a name="index-m68030-1512"></a>Generate output for a 68030. This is the default when the compiler is 163configured for 68030-based systems. It is equivalent to 164<samp><span class="option">-march=68030</span></samp>. 165 166 <br><dt><code>-m68040</code><dd><a name="index-m68040-1513"></a>Generate output for a 68040. This is the default when the compiler is 167configured for 68040-based systems. It is equivalent to 168<samp><span class="option">-march=68040</span></samp>. 169 170 <p>This option inhibits the use of 68881/68882 instructions that have to be 171emulated by software on the 68040. Use this option if your 68040 does not 172have code to emulate those instructions. 173 174 <br><dt><code>-m68060</code><dd><a name="index-m68060-1514"></a>Generate output for a 68060. This is the default when the compiler is 175configured for 68060-based systems. It is equivalent to 176<samp><span class="option">-march=68060</span></samp>. 177 178 <p>This option inhibits the use of 68020 and 68881/68882 instructions that 179have to be emulated by software on the 68060. Use this option if your 68060 180does not have code to emulate those instructions. 181 182 <br><dt><code>-mcpu32</code><dd><a name="index-mcpu32-1515"></a>Generate output for a CPU32. This is the default 183when the compiler is configured for CPU32-based systems. 184It is equivalent to <samp><span class="option">-march=cpu32</span></samp>. 185 186 <p>Use this option for microcontrollers with a 187CPU32 or CPU32+ core, including the 68330, 68331, 68332, 68333, 68334, 18868336, 68340, 68341, 68349 and 68360. 189 190 <br><dt><code>-m5200</code><dd><a name="index-m5200-1516"></a>Generate output for a 520X ColdFire CPU. This is the default 191when the compiler is configured for 520X-based systems. 192It is equivalent to <samp><span class="option">-mcpu=5206</span></samp>, and is now deprecated 193in favor of that option. 194 195 <p>Use this option for microcontroller with a 5200 core, including 196the MCF5202, MCF5203, MCF5204 and MCF5206. 197 198 <br><dt><code>-m5206e</code><dd><a name="index-m5206e-1517"></a>Generate output for a 5206e ColdFire CPU. The option is now 199deprecated in favor of the equivalent <samp><span class="option">-mcpu=5206e</span></samp>. 200 201 <br><dt><code>-m528x</code><dd><a name="index-m528x-1518"></a>Generate output for a member of the ColdFire 528X family. 202The option is now deprecated in favor of the equivalent 203<samp><span class="option">-mcpu=528x</span></samp>. 204 205 <br><dt><code>-m5307</code><dd><a name="index-m5307-1519"></a>Generate output for a ColdFire 5307 CPU. The option is now deprecated 206in favor of the equivalent <samp><span class="option">-mcpu=5307</span></samp>. 207 208 <br><dt><code>-m5407</code><dd><a name="index-m5407-1520"></a>Generate output for a ColdFire 5407 CPU. The option is now deprecated 209in favor of the equivalent <samp><span class="option">-mcpu=5407</span></samp>. 210 211 <br><dt><code>-mcfv4e</code><dd><a name="index-mcfv4e-1521"></a>Generate output for a ColdFire V4e family CPU (e.g. 547x/548x). 212This includes use of hardware floating point instructions. 213The option is equivalent to <samp><span class="option">-mcpu=547x</span></samp>, and is now 214deprecated in favor of that option. 215 216 <br><dt><code>-m68020-40</code><dd><a name="index-m68020_002d40-1522"></a>Generate output for a 68040, without using any of the new instructions. 217This results in code which can run relatively efficiently on either a 21868020/68881 or a 68030 or a 68040. The generated code does use the 21968881 instructions that are emulated on the 68040. 220 221 <p>The option is equivalent to <samp><span class="option">-march=68020</span></samp> <samp><span class="option">-mtune=68020-40</span></samp>. 222 223 <br><dt><code>-m68020-60</code><dd><a name="index-m68020_002d60-1523"></a>Generate output for a 68060, without using any of the new instructions. 224This results in code which can run relatively efficiently on either a 22568020/68881 or a 68030 or a 68040. The generated code does use the 22668881 instructions that are emulated on the 68060. 227 228 <p>The option is equivalent to <samp><span class="option">-march=68020</span></samp> <samp><span class="option">-mtune=68020-60</span></samp>. 229 230 <br><dt><code>-mhard-float</code><dt><code>-m68881</code><dd><a name="index-mhard_002dfloat-1524"></a><a name="index-m68881-1525"></a>Generate floating-point instructions. This is the default for 68020 231and above, and for ColdFire devices that have an FPU. It defines the 232macro ‘<samp><span class="samp">__HAVE_68881__</span></samp>’ on M680x0 targets and ‘<samp><span class="samp">__mcffpu__</span></samp>’ 233on ColdFire targets. 234 235 <br><dt><code>-msoft-float</code><dd><a name="index-msoft_002dfloat-1526"></a>Do not generate floating-point instructions; use library calls instead. 236This is the default for 68000, 68010, and 68832 targets. It is also 237the default for ColdFire devices that have no FPU. 238 239 <br><dt><code>-mdiv</code><dt><code>-mno-div</code><dd><a name="index-mdiv-1527"></a><a name="index-mno_002ddiv-1528"></a>Generate (do not generate) ColdFire hardware divide and remainder 240instructions. If <samp><span class="option">-march</span></samp> is used without <samp><span class="option">-mcpu</span></samp>, 241the default is “on” for ColdFire architectures and “off” for M680x0 242architectures. Otherwise, the default is taken from the target CPU 243(either the default CPU, or the one specified by <samp><span class="option">-mcpu</span></samp>). For 244example, the default is “off” for <samp><span class="option">-mcpu=5206</span></samp> and “on” for 245<samp><span class="option">-mcpu=5206e</span></samp>. 246 247 <p>gcc defines the macro ‘<samp><span class="samp">__mcfhwdiv__</span></samp>’ when this option is enabled. 248 249 <br><dt><code>-mshort</code><dd><a name="index-mshort-1529"></a>Consider type <code>int</code> to be 16 bits wide, like <code>short int</code>. 250Additionally, parameters passed on the stack are also aligned to a 25116-bit boundary even on targets whose API mandates promotion to 32-bit. 252 253 <br><dt><code>-mno-short</code><dd><a name="index-mno_002dshort-1530"></a>Do not consider type <code>int</code> to be 16 bits wide. This is the default. 254 255 <br><dt><code>-mnobitfield</code><dt><code>-mno-bitfield</code><dd><a name="index-mnobitfield-1531"></a><a name="index-mno_002dbitfield-1532"></a>Do not use the bit-field instructions. The <samp><span class="option">-m68000</span></samp>, <samp><span class="option">-mcpu32</span></samp> 256and <samp><span class="option">-m5200</span></samp> options imply <samp><span class="option">-mnobitfield</span></samp><!-- /@w -->. 257 258 <br><dt><code>-mbitfield</code><dd><a name="index-mbitfield-1533"></a>Do use the bit-field instructions. The <samp><span class="option">-m68020</span></samp> option implies 259<samp><span class="option">-mbitfield</span></samp>. This is the default if you use a configuration 260designed for a 68020. 261 262 <br><dt><code>-mrtd</code><dd><a name="index-mrtd-1534"></a>Use a different function-calling convention, in which functions 263that take a fixed number of arguments return with the <code>rtd</code> 264instruction, which pops their arguments while returning. This 265saves one instruction in the caller since there is no need to pop 266the arguments there. 267 268 <p>This calling convention is incompatible with the one normally 269used on Unix, so you cannot use it if you need to call libraries 270compiled with the Unix compiler. 271 272 <p>Also, you must provide function prototypes for all functions that 273take variable numbers of arguments (including <code>printf</code>); 274otherwise incorrect code will be generated for calls to those 275functions. 276 277 <p>In addition, seriously incorrect code will result if you call a 278function with too many arguments. (Normally, extra arguments are 279harmlessly ignored.) 280 281 <p>The <code>rtd</code> instruction is supported by the 68010, 68020, 68030, 28268040, 68060 and CPU32 processors, but not by the 68000 or 5200. 283 284 <br><dt><code>-mno-rtd</code><dd><a name="index-mno_002drtd-1535"></a>Do not use the calling conventions selected by <samp><span class="option">-mrtd</span></samp>. 285This is the default. 286 287 <br><dt><code>-malign-int</code><dt><code>-mno-align-int</code><dd><a name="index-malign_002dint-1536"></a><a name="index-mno_002dalign_002dint-1537"></a>Control whether GCC aligns <code>int</code>, <code>long</code>, <code>long long</code>, 288<code>float</code>, <code>double</code>, and <code>long double</code> variables on a 32-bit 289boundary (<samp><span class="option">-malign-int</span></samp>) or a 16-bit boundary (<samp><span class="option">-mno-align-int</span></samp>). 290Aligning variables on 32-bit boundaries produces code that runs somewhat 291faster on processors with 32-bit busses at the expense of more memory. 292 293 <p><strong>Warning:</strong> if you use the <samp><span class="option">-malign-int</span></samp> switch, GCC will 294align structures containing the above types differently than 295most published application binary interface specifications for the m68k. 296 297 <br><dt><code>-mpcrel</code><dd><a name="index-mpcrel-1538"></a>Use the pc-relative addressing mode of the 68000 directly, instead of 298using a global offset table. At present, this option implies <samp><span class="option">-fpic</span></samp>, 299allowing at most a 16-bit offset for pc-relative addressing. <samp><span class="option">-fPIC</span></samp> is 300not presently supported with <samp><span class="option">-mpcrel</span></samp>, though this could be supported for 30168020 and higher processors. 302 303 <br><dt><code>-mno-strict-align</code><dt><code>-mstrict-align</code><dd><a name="index-mno_002dstrict_002dalign-1539"></a><a name="index-mstrict_002dalign-1540"></a>Do not (do) assume that unaligned memory references will be handled by 304the system. 305 306 <br><dt><code>-msep-data</code><dd>Generate code that allows the data segment to be located in a different 307area of memory from the text segment. This allows for execute in place in 308an environment without virtual memory management. This option implies 309<samp><span class="option">-fPIC</span></samp>. 310 311 <br><dt><code>-mno-sep-data</code><dd>Generate code that assumes that the data segment follows the text segment. 312This is the default. 313 314 <br><dt><code>-mid-shared-library</code><dd>Generate code that supports shared libraries via the library ID method. 315This allows for execute in place and shared libraries in an environment 316without virtual memory management. This option implies <samp><span class="option">-fPIC</span></samp>. 317 318 <br><dt><code>-mno-id-shared-library</code><dd>Generate code that doesn't assume ID based shared libraries are being used. 319This is the default. 320 321 <br><dt><code>-mshared-library-id=n</code><dd>Specified the identification number of the ID based shared library being 322compiled. Specifying a value of 0 will generate more compact code, specifying 323other values will force the allocation of that number to the current 324library but is no more space or time efficient than omitting this option. 325 326 <br><dt><code>-mxgot</code><dt><code>-mno-xgot</code><dd><a name="index-mxgot-1541"></a><a name="index-mno_002dxgot-1542"></a>When generating position-independent code for ColdFire, generate code 327that works if the GOT has more than 8192 entries. This code is 328larger and slower than code generated without this option. On M680x0 329processors, this option is not needed; <samp><span class="option">-fPIC</span></samp> suffices. 330 331 <p>GCC normally uses a single instruction to load values from the GOT. 332While this is relatively efficient, it only works if the GOT 333is smaller than about 64k. Anything larger causes the linker 334to report an error such as: 335 336 <p><a name="index-relocation-truncated-to-fit-_0028ColdFire_0029-1543"></a> 337 <pre class="smallexample"> relocation truncated to fit: R_68K_GOT16O foobar 338</pre> 339 <p>If this happens, you should recompile your code with <samp><span class="option">-mxgot</span></samp>. 340It should then work with very large GOTs. However, code generated with 341<samp><span class="option">-mxgot</span></samp> is less efficient, since it takes 4 instructions to fetch 342the value of a global symbol. 343 344 <p>Note that some linkers, including newer versions of the GNU linker, 345can create multiple GOTs and sort GOT entries. If you have such a linker, 346you should only need to use <samp><span class="option">-mxgot</span></samp> when compiling a single 347object file that accesses more than 8192 GOT entries. Very few do. 348 349 <p>These options have no effect unless GCC is generating 350position-independent code. 351 352 </dl> 353 354 </body></html> 355 356