1<html lang="en"> 2<head> 3<title>DEC Alpha Options - Using the GNU Compiler Collection (GCC)</title> 4<meta http-equiv="Content-Type" content="text/html"> 5<meta name="description" content="Using the GNU Compiler Collection (GCC)"> 6<meta name="generator" content="makeinfo 4.13"> 7<link title="Top" rel="start" href="index.html#Top"> 8<link rel="up" href="Submodel-Options.html#Submodel-Options" title="Submodel Options"> 9<link rel="prev" href="Darwin-Options.html#Darwin-Options" title="Darwin Options"> 10<link rel="next" href="DEC-Alpha_002fVMS-Options.html#DEC-Alpha_002fVMS-Options" title="DEC Alpha/VMS Options"> 11<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage"> 12<!-- 13Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 141998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 152010 Free Software Foundation, Inc. 16 17Permission is granted to copy, distribute and/or modify this document 18under the terms of the GNU Free Documentation License, Version 1.3 or 19any later version published by the Free Software Foundation; with the 20Invariant Sections being ``Funding Free Software'', the Front-Cover 21Texts being (a) (see below), and with the Back-Cover Texts being (b) 22(see below). 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When <samp><span class="option">-msoft-float</span></samp> is specified, 65functions in <samp><span class="file">libgcc.a</span></samp> will be used to perform floating-point 66operations. Unless they are replaced by routines that emulate the 67floating-point operations, or compiled in such a way as to call such 68emulations routines, these routines will issue floating-point 69operations. If you are compiling for an Alpha without floating-point 70operations, you must ensure that the library is built so as not to call 71them. 72 73 <p>Note that Alpha implementations without floating-point operations are 74required to have floating-point registers. 75 76 <br><dt><code>-mfp-reg</code><dt><code>-mno-fp-regs</code><dd><a name="index-mfp_002dreg-1209"></a><a name="index-mno_002dfp_002dregs-1210"></a>Generate code that uses (does not use) the floating-point register set. 77<samp><span class="option">-mno-fp-regs</span></samp> implies <samp><span class="option">-msoft-float</span></samp>. If the floating-point 78register set is not used, floating point operands are passed in integer 79registers as if they were integers and floating-point results are passed 80in <code>$0</code> instead of <code>$f0</code>. This is a non-standard calling sequence, 81so any function with a floating-point argument or return value called by code 82compiled with <samp><span class="option">-mno-fp-regs</span></samp> must also be compiled with that 83option. 84 85 <p>A typical use of this option is building a kernel that does not use, 86and hence need not save and restore, any floating-point registers. 87 88 <br><dt><code>-mieee</code><dd><a name="index-mieee-1211"></a>The Alpha architecture implements floating-point hardware optimized for 89maximum performance. It is mostly compliant with the IEEE floating 90point standard. However, for full compliance, software assistance is 91required. This option generates code fully IEEE compliant code 92<em>except</em> that the <var>inexact-flag</var> is not maintained (see below). 93If this option is turned on, the preprocessor macro <code>_IEEE_FP</code> is 94defined during compilation. The resulting code is less efficient but is 95able to correctly support denormalized numbers and exceptional IEEE 96values such as not-a-number and plus/minus infinity. Other Alpha 97compilers call this option <samp><span class="option">-ieee_with_no_inexact</span></samp>. 98 99 <br><dt><code>-mieee-with-inexact</code><dd><a name="index-mieee_002dwith_002dinexact-1212"></a>This is like <samp><span class="option">-mieee</span></samp> except the generated code also maintains 100the IEEE <var>inexact-flag</var>. Turning on this option causes the 101generated code to implement fully-compliant IEEE math. In addition to 102<code>_IEEE_FP</code>, <code>_IEEE_FP_EXACT</code> is defined as a preprocessor 103macro. On some Alpha implementations the resulting code may execute 104significantly slower than the code generated by default. Since there is 105very little code that depends on the <var>inexact-flag</var>, you should 106normally not specify this option. Other Alpha compilers call this 107option <samp><span class="option">-ieee_with_inexact</span></samp>. 108 109 <br><dt><code>-mfp-trap-mode=</code><var>trap-mode</var><dd><a name="index-mfp_002dtrap_002dmode-1213"></a>This option controls what floating-point related traps are enabled. 110Other Alpha compilers call this option <samp><span class="option">-fptm </span><var>trap-mode</var></samp>. 111The trap mode can be set to one of four values: 112 113 <dl> 114<dt>‘<samp><span class="samp">n</span></samp>’<dd>This is the default (normal) setting. The only traps that are enabled 115are the ones that cannot be disabled in software (e.g., division by zero 116trap). 117 118 <br><dt>‘<samp><span class="samp">u</span></samp>’<dd>In addition to the traps enabled by ‘<samp><span class="samp">n</span></samp>’, underflow traps are enabled 119as well. 120 121 <br><dt>‘<samp><span class="samp">su</span></samp>’<dd>Like ‘<samp><span class="samp">u</span></samp>’, but the instructions are marked to be safe for software 122completion (see Alpha architecture manual for details). 123 124 <br><dt>‘<samp><span class="samp">sui</span></samp>’<dd>Like ‘<samp><span class="samp">su</span></samp>’, but inexact traps are enabled as well. 125</dl> 126 127 <br><dt><code>-mfp-rounding-mode=</code><var>rounding-mode</var><dd><a name="index-mfp_002drounding_002dmode-1214"></a>Selects the IEEE rounding mode. Other Alpha compilers call this option 128<samp><span class="option">-fprm </span><var>rounding-mode</var></samp>. The <var>rounding-mode</var> can be one 129of: 130 131 <dl> 132<dt>‘<samp><span class="samp">n</span></samp>’<dd>Normal IEEE rounding mode. Floating point numbers are rounded towards 133the nearest machine number or towards the even machine number in case 134of a tie. 135 136 <br><dt>‘<samp><span class="samp">m</span></samp>’<dd>Round towards minus infinity. 137 138 <br><dt>‘<samp><span class="samp">c</span></samp>’<dd>Chopped rounding mode. Floating point numbers are rounded towards zero. 139 140 <br><dt>‘<samp><span class="samp">d</span></samp>’<dd>Dynamic rounding mode. A field in the floating point control register 141(<var>fpcr</var>, see Alpha architecture reference manual) controls the 142rounding mode in effect. The C library initializes this register for 143rounding towards plus infinity. Thus, unless your program modifies the 144<var>fpcr</var>, ‘<samp><span class="samp">d</span></samp>’ corresponds to round towards plus infinity. 145</dl> 146 147 <br><dt><code>-mtrap-precision=</code><var>trap-precision</var><dd><a name="index-mtrap_002dprecision-1215"></a>In the Alpha architecture, floating point traps are imprecise. This 148means without software assistance it is impossible to recover from a 149floating trap and program execution normally needs to be terminated. 150GCC can generate code that can assist operating system trap handlers 151in determining the exact location that caused a floating point trap. 152Depending on the requirements of an application, different levels of 153precisions can be selected: 154 155 <dl> 156<dt>‘<samp><span class="samp">p</span></samp>’<dd>Program precision. This option is the default and means a trap handler 157can only identify which program caused a floating point exception. 158 159 <br><dt>‘<samp><span class="samp">f</span></samp>’<dd>Function precision. The trap handler can determine the function that 160caused a floating point exception. 161 162 <br><dt>‘<samp><span class="samp">i</span></samp>’<dd>Instruction precision. The trap handler can determine the exact 163instruction that caused a floating point exception. 164</dl> 165 166 <p>Other Alpha compilers provide the equivalent options called 167<samp><span class="option">-scope_safe</span></samp> and <samp><span class="option">-resumption_safe</span></samp>. 168 169 <br><dt><code>-mieee-conformant</code><dd><a name="index-mieee_002dconformant-1216"></a>This option marks the generated code as IEEE conformant. You must not 170use this option unless you also specify <samp><span class="option">-mtrap-precision=i</span></samp> and either 171<samp><span class="option">-mfp-trap-mode=su</span></samp> or <samp><span class="option">-mfp-trap-mode=sui</span></samp>. Its only effect 172is to emit the line ‘<samp><span class="samp">.eflag 48</span></samp>’ in the function prologue of the 173generated assembly file. Under DEC Unix, this has the effect that 174IEEE-conformant math library routines will be linked in. 175 176 <br><dt><code>-mbuild-constants</code><dd><a name="index-mbuild_002dconstants-1217"></a>Normally GCC examines a 32- or 64-bit integer constant to 177see if it can construct it from smaller constants in two or three 178instructions. If it cannot, it will output the constant as a literal and 179generate code to load it from the data segment at runtime. 180 181 <p>Use this option to require GCC to construct <em>all</em> integer constants 182using code, even if it takes more instructions (the maximum is six). 183 184 <p>You would typically use this option to build a shared library dynamic 185loader. Itself a shared library, it must relocate itself in memory 186before it can find the variables and constants in its own data segment. 187 188 <br><dt><code>-malpha-as</code><dt><code>-mgas</code><dd><a name="index-malpha_002das-1218"></a><a name="index-mgas-1219"></a>Select whether to generate code to be assembled by the vendor-supplied 189assembler (<samp><span class="option">-malpha-as</span></samp>) or by the GNU assembler <samp><span class="option">-mgas</span></samp>. 190 191 <br><dt><code>-mbwx</code><dt><code>-mno-bwx</code><dt><code>-mcix</code><dt><code>-mno-cix</code><dt><code>-mfix</code><dt><code>-mno-fix</code><dt><code>-mmax</code><dt><code>-mno-max</code><dd><a name="index-mbwx-1220"></a><a name="index-mno_002dbwx-1221"></a><a name="index-mcix-1222"></a><a name="index-mno_002dcix-1223"></a><a name="index-mfix-1224"></a><a name="index-mno_002dfix-1225"></a><a name="index-mmax-1226"></a><a name="index-mno_002dmax-1227"></a>Indicate whether GCC should generate code to use the optional BWX, 192CIX, FIX and MAX instruction sets. The default is to use the instruction 193sets supported by the CPU type specified via <samp><span class="option">-mcpu=</span></samp> option or that 194of the CPU on which GCC was built if none was specified. 195 196 <br><dt><code>-mfloat-vax</code><dt><code>-mfloat-ieee</code><dd><a name="index-mfloat_002dvax-1228"></a><a name="index-mfloat_002dieee-1229"></a>Generate code that uses (does not use) VAX F and G floating point 197arithmetic instead of IEEE single and double precision. 198 199 <br><dt><code>-mexplicit-relocs</code><dt><code>-mno-explicit-relocs</code><dd><a name="index-mexplicit_002drelocs-1230"></a><a name="index-mno_002dexplicit_002drelocs-1231"></a>Older Alpha assemblers provided no way to generate symbol relocations 200except via assembler macros. Use of these macros does not allow 201optimal instruction scheduling. GNU binutils as of version 2.12 202supports a new syntax that allows the compiler to explicitly mark 203which relocations should apply to which instructions. This option 204is mostly useful for debugging, as GCC detects the capabilities of 205the assembler when it is built and sets the default accordingly. 206 207 <br><dt><code>-msmall-data</code><dt><code>-mlarge-data</code><dd><a name="index-msmall_002ddata-1232"></a><a name="index-mlarge_002ddata-1233"></a>When <samp><span class="option">-mexplicit-relocs</span></samp> is in effect, static data is 208accessed via <dfn>gp-relative</dfn> relocations. When <samp><span class="option">-msmall-data</span></samp> 209is used, objects 8 bytes long or smaller are placed in a <dfn>small data area</dfn> 210(the <code>.sdata</code> and <code>.sbss</code> sections) and are accessed via 21116-bit relocations off of the <code>$gp</code> register. This limits the 212size of the small data area to 64KB, but allows the variables to be 213directly accessed via a single instruction. 214 215 <p>The default is <samp><span class="option">-mlarge-data</span></samp>. With this option the data area 216is limited to just below 2GB. Programs that require more than 2GB of 217data must use <code>malloc</code> or <code>mmap</code> to allocate the data in the 218heap instead of in the program's data segment. 219 220 <p>When generating code for shared libraries, <samp><span class="option">-fpic</span></samp> implies 221<samp><span class="option">-msmall-data</span></samp> and <samp><span class="option">-fPIC</span></samp> implies <samp><span class="option">-mlarge-data</span></samp>. 222 223 <br><dt><code>-msmall-text</code><dt><code>-mlarge-text</code><dd><a name="index-msmall_002dtext-1234"></a><a name="index-mlarge_002dtext-1235"></a>When <samp><span class="option">-msmall-text</span></samp> is used, the compiler assumes that the 224code of the entire program (or shared library) fits in 4MB, and is 225thus reachable with a branch instruction. When <samp><span class="option">-msmall-data</span></samp> 226is used, the compiler can assume that all local symbols share the 227same <code>$gp</code> value, and thus reduce the number of instructions 228required for a function call from 4 to 1. 229 230 <p>The default is <samp><span class="option">-mlarge-text</span></samp>. 231 232 <br><dt><code>-mcpu=</code><var>cpu_type</var><dd><a name="index-mcpu-1236"></a>Set the instruction set and instruction scheduling parameters for 233machine type <var>cpu_type</var>. You can specify either the ‘<samp><span class="samp">EV</span></samp>’ 234style name or the corresponding chip number. GCC supports scheduling 235parameters for the EV4, EV5 and EV6 family of processors and will 236choose the default values for the instruction set from the processor 237you specify. If you do not specify a processor type, GCC will default 238to the processor on which the compiler was built. 239 240 <p>Supported values for <var>cpu_type</var> are 241 242 <dl> 243<dt>‘<samp><span class="samp">ev4</span></samp>’<dt>‘<samp><span class="samp">ev45</span></samp>’<dt>‘<samp><span class="samp">21064</span></samp>’<dd>Schedules as an EV4 and has no instruction set extensions. 244 245 <br><dt>‘<samp><span class="samp">ev5</span></samp>’<dt>‘<samp><span class="samp">21164</span></samp>’<dd>Schedules as an EV5 and has no instruction set extensions. 246 247 <br><dt>‘<samp><span class="samp">ev56</span></samp>’<dt>‘<samp><span class="samp">21164a</span></samp>’<dd>Schedules as an EV5 and supports the BWX extension. 248 249 <br><dt>‘<samp><span class="samp">pca56</span></samp>’<dt>‘<samp><span class="samp">21164pc</span></samp>’<dt>‘<samp><span class="samp">21164PC</span></samp>’<dd>Schedules as an EV5 and supports the BWX and MAX extensions. 250 251 <br><dt>‘<samp><span class="samp">ev6</span></samp>’<dt>‘<samp><span class="samp">21264</span></samp>’<dd>Schedules as an EV6 and supports the BWX, FIX, and MAX extensions. 252 253 <br><dt>‘<samp><span class="samp">ev67</span></samp>’<dt>‘<samp><span class="samp">21264a</span></samp>’<dd>Schedules as an EV6 and supports the BWX, CIX, FIX, and MAX extensions. 254</dl> 255 256 <p>Native Linux/GNU toolchains also support the value ‘<samp><span class="samp">native</span></samp>’, 257which selects the best architecture option for the host processor. 258<samp><span class="option">-mcpu=native</span></samp> has no effect if GCC does not recognize 259the processor. 260 261 <br><dt><code>-mtune=</code><var>cpu_type</var><dd><a name="index-mtune-1237"></a>Set only the instruction scheduling parameters for machine type 262<var>cpu_type</var>. The instruction set is not changed. 263 264 <p>Native Linux/GNU toolchains also support the value ‘<samp><span class="samp">native</span></samp>’, 265which selects the best architecture option for the host processor. 266<samp><span class="option">-mtune=native</span></samp> has no effect if GCC does not recognize 267the processor. 268 269 <br><dt><code>-mmemory-latency=</code><var>time</var><dd><a name="index-mmemory_002dlatency-1238"></a>Sets the latency the scheduler should assume for typical memory 270references as seen by the application. This number is highly 271dependent on the memory access patterns used by the application 272and the size of the external cache on the machine. 273 274 <p>Valid options for <var>time</var> are 275 276 <dl> 277<dt>‘<samp><var>number</var></samp>’<dd>A decimal number representing clock cycles. 278 279 <br><dt>‘<samp><span class="samp">L1</span></samp>’<dt>‘<samp><span class="samp">L2</span></samp>’<dt>‘<samp><span class="samp">L3</span></samp>’<dt>‘<samp><span class="samp">main</span></samp>’<dd>The compiler contains estimates of the number of clock cycles for 280“typical” EV4 & EV5 hardware for the Level 1, 2 & 3 caches 281(also called Dcache, Scache, and Bcache), as well as to main memory. 282Note that L3 is only valid for EV5. 283 284 </dl> 285 </dl> 286 287 </body></html> 288 289