1<html lang="en"> 2<head> 3<title>ARM Options - Using the GNU Compiler Collection (GCC)</title> 4<meta http-equiv="Content-Type" content="text/html"> 5<meta name="description" content="Using the GNU Compiler Collection (GCC)"> 6<meta name="generator" content="makeinfo 4.13"> 7<link title="Top" rel="start" href="index.html#Top"> 8<link rel="up" href="Submodel-Options.html#Submodel-Options" title="Submodel Options"> 9<link rel="prev" href="ARC-Options.html#ARC-Options" title="ARC Options"> 10<link rel="next" href="AVR-Options.html#AVR-Options" title="AVR Options"> 11<link href="http://www.gnu.org/software/texinfo/" rel="generator-home" title="Texinfo Homepage"> 12<!-- 13Copyright (C) 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 141998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 152010 Free Software Foundation, Inc. 16 17Permission is granted to copy, distribute and/or modify this document 18under the terms of the GNU Free Documentation License, Version 1.3 or 19any later version published by the Free Software Foundation; with the 20Invariant Sections being ``Funding Free Software'', the Front-Cover 21Texts being (a) (see below), and with the Back-Cover Texts being (b) 22(see below). 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Permissible values are: ‘<samp><span class="samp">apcs-gnu</span></samp>’, 66‘<samp><span class="samp">atpcs</span></samp>’, ‘<samp><span class="samp">aapcs</span></samp>’, ‘<samp><span class="samp">aapcs-linux</span></samp>’ and ‘<samp><span class="samp">iwmmxt</span></samp>’. 67 68 <br><dt><code>-mapcs-frame</code><dd><a name="index-mapcs_002dframe-1032"></a>Generate a stack frame that is compliant with the ARM Procedure Call 69Standard for all functions, even if this is not strictly necessary for 70correct execution of the code. Specifying <samp><span class="option">-fomit-frame-pointer</span></samp> 71with this option will cause the stack frames not to be generated for 72leaf functions. The default is <samp><span class="option">-mno-apcs-frame</span></samp>. 73 74 <br><dt><code>-mapcs</code><dd><a name="index-mapcs-1033"></a>This is a synonym for <samp><span class="option">-mapcs-frame</span></samp>. 75 76 <br><dt><code>-mthumb-interwork</code><dd><a name="index-mthumb_002dinterwork-1034"></a>Generate code which supports calling between the ARM and Thumb 77instruction sets. Without this option the two instruction sets cannot 78be reliably used inside one program. The default is 79<samp><span class="option">-mno-thumb-interwork</span></samp>, since slightly larger code is generated 80when <samp><span class="option">-mthumb-interwork</span></samp> is specified. 81 82 <br><dt><code>-mno-sched-prolog</code><dd><a name="index-mno_002dsched_002dprolog-1035"></a>Prevent the reordering of instructions in the function prolog, or the 83merging of those instruction with the instructions in the function's 84body. This means that all functions will start with a recognizable set 85of instructions (or in fact one of a choice from a small set of 86different function prologues), and this information can be used to 87locate the start if functions inside an executable piece of code. The 88default is <samp><span class="option">-msched-prolog</span></samp>. 89 90 <br><dt><code>-mfloat-abi=</code><var>name</var><dd><a name="index-mfloat_002dabi-1036"></a>Specifies which floating-point ABI to use. Permissible values 91are: ‘<samp><span class="samp">soft</span></samp>’, ‘<samp><span class="samp">softfp</span></samp>’ and ‘<samp><span class="samp">hard</span></samp>’. 92 93 <p>Specifying ‘<samp><span class="samp">soft</span></samp>’ causes GCC to generate output containing 94library calls for floating-point operations. 95‘<samp><span class="samp">softfp</span></samp>’ allows the generation of code using hardware floating-point 96instructions, but still uses the soft-float calling conventions. 97‘<samp><span class="samp">hard</span></samp>’ allows generation of floating-point instructions 98and uses FPU-specific calling conventions. 99 100 <p>The default depends on the specific target configuration. Note that 101the hard-float and soft-float ABIs are not link-compatible; you must 102compile your entire program with the same ABI, and link with a 103compatible set of libraries. 104 105 <br><dt><code>-mhard-float</code><dd><a name="index-mhard_002dfloat-1037"></a>Equivalent to <samp><span class="option">-mfloat-abi=hard</span></samp>. 106 107 <br><dt><code>-msoft-float</code><dd><a name="index-msoft_002dfloat-1038"></a>Equivalent to <samp><span class="option">-mfloat-abi=soft</span></samp>. 108 109 <br><dt><code>-mlittle-endian</code><dd><a name="index-mlittle_002dendian-1039"></a>Generate code for a processor running in little-endian mode. This is 110the default for all standard configurations. 111 112 <br><dt><code>-mbig-endian</code><dd><a name="index-mbig_002dendian-1040"></a>Generate code for a processor running in big-endian mode; the default is 113to compile code for a little-endian processor. 114 115 <br><dt><code>-mwords-little-endian</code><dd><a name="index-mwords_002dlittle_002dendian-1041"></a>This option only applies when generating code for big-endian processors. 116Generate code for a little-endian word order but a big-endian byte 117order. That is, a byte order of the form ‘<samp><span class="samp">32107654</span></samp>’. Note: this 118option should only be used if you require compatibility with code for 119big-endian ARM processors generated by versions of the compiler prior to 1202.8. 121 122 <br><dt><code>-mcpu=</code><var>name</var><dd><a name="index-mcpu-1042"></a>This specifies the name of the target ARM processor. GCC uses this name 123to determine what kind of instructions it can emit when generating 124assembly code. Permissible names are: ‘<samp><span class="samp">arm2</span></samp>’, ‘<samp><span class="samp">arm250</span></samp>’, 125‘<samp><span class="samp">arm3</span></samp>’, ‘<samp><span class="samp">arm6</span></samp>’, ‘<samp><span class="samp">arm60</span></samp>’, ‘<samp><span class="samp">arm600</span></samp>’, ‘<samp><span class="samp">arm610</span></samp>’, 126‘<samp><span class="samp">arm620</span></samp>’, ‘<samp><span class="samp">arm7</span></samp>’, ‘<samp><span class="samp">arm7m</span></samp>’, ‘<samp><span class="samp">arm7d</span></samp>’, ‘<samp><span class="samp">arm7dm</span></samp>’, 127‘<samp><span class="samp">arm7di</span></samp>’, ‘<samp><span class="samp">arm7dmi</span></samp>’, ‘<samp><span class="samp">arm70</span></samp>’, ‘<samp><span class="samp">arm700</span></samp>’, 128‘<samp><span class="samp">arm700i</span></samp>’, ‘<samp><span class="samp">arm710</span></samp>’, ‘<samp><span class="samp">arm710c</span></samp>’, ‘<samp><span class="samp">arm7100</span></samp>’, 129‘<samp><span class="samp">arm720</span></samp>’, 130‘<samp><span class="samp">arm7500</span></samp>’, ‘<samp><span class="samp">arm7500fe</span></samp>’, ‘<samp><span class="samp">arm7tdmi</span></samp>’, ‘<samp><span class="samp">arm7tdmi-s</span></samp>’, 131‘<samp><span class="samp">arm710t</span></samp>’, ‘<samp><span class="samp">arm720t</span></samp>’, ‘<samp><span class="samp">arm740t</span></samp>’, 132‘<samp><span class="samp">strongarm</span></samp>’, ‘<samp><span class="samp">strongarm110</span></samp>’, ‘<samp><span class="samp">strongarm1100</span></samp>’, 133‘<samp><span class="samp">strongarm1110</span></samp>’, 134‘<samp><span class="samp">arm8</span></samp>’, ‘<samp><span class="samp">arm810</span></samp>’, ‘<samp><span class="samp">arm9</span></samp>’, ‘<samp><span class="samp">arm9e</span></samp>’, ‘<samp><span class="samp">arm920</span></samp>’, 135‘<samp><span class="samp">arm920t</span></samp>’, ‘<samp><span class="samp">arm922t</span></samp>’, ‘<samp><span class="samp">arm946e-s</span></samp>’, ‘<samp><span class="samp">arm966e-s</span></samp>’, 136‘<samp><span class="samp">arm968e-s</span></samp>’, ‘<samp><span class="samp">arm926ej-s</span></samp>’, ‘<samp><span class="samp">arm940t</span></samp>’, ‘<samp><span class="samp">arm9tdmi</span></samp>’, 137‘<samp><span class="samp">arm10tdmi</span></samp>’, ‘<samp><span class="samp">arm1020t</span></samp>’, ‘<samp><span class="samp">arm1026ej-s</span></samp>’, 138‘<samp><span class="samp">arm10e</span></samp>’, ‘<samp><span class="samp">arm1020e</span></samp>’, ‘<samp><span class="samp">arm1022e</span></samp>’, 139‘<samp><span class="samp">arm1136j-s</span></samp>’, ‘<samp><span class="samp">arm1136jf-s</span></samp>’, ‘<samp><span class="samp">mpcore</span></samp>’, ‘<samp><span class="samp">mpcorenovfp</span></samp>’, 140‘<samp><span class="samp">arm1156t2-s</span></samp>’, ‘<samp><span class="samp">arm1156t2f-s</span></samp>’, ‘<samp><span class="samp">arm1176jz-s</span></samp>’, ‘<samp><span class="samp">arm1176jzf-s</span></samp>’, 141‘<samp><span class="samp">cortex-a5</span></samp>’, ‘<samp><span class="samp">cortex-a8</span></samp>’, ‘<samp><span class="samp">cortex-a9</span></samp>’, ‘<samp><span class="samp">cortex-a15</span></samp>’, 142‘<samp><span class="samp">cortex-r4</span></samp>’, ‘<samp><span class="samp">cortex-r4f</span></samp>’, ‘<samp><span class="samp">cortex-r5</span></samp>’, ‘<samp><span class="samp">cortex-m4</span></samp>’, 143‘<samp><span class="samp">cortex-m3</span></samp>’, ‘<samp><span class="samp">cortex-m1</span></samp>’, ‘<samp><span class="samp">cortex-m0</span></samp>’, 144‘<samp><span class="samp">xscale</span></samp>’, ‘<samp><span class="samp">iwmmxt</span></samp>’, ‘<samp><span class="samp">iwmmxt2</span></samp>’, ‘<samp><span class="samp">ep9312</span></samp>’. 145 146 <br><dt><code>-mtune=</code><var>name</var><dd><a name="index-mtune-1043"></a>This option is very similar to the <samp><span class="option">-mcpu=</span></samp> option, except that 147instead of specifying the actual target processor type, and hence 148restricting which instructions can be used, it specifies that GCC should 149tune the performance of the code as if the target were of the type 150specified in this option, but still choosing the instructions that it 151will generate based on the CPU specified by a <samp><span class="option">-mcpu=</span></samp> option. 152For some ARM implementations better performance can be obtained by using 153this option. 154 155 <br><dt><code>-march=</code><var>name</var><dd><a name="index-march-1044"></a>This specifies the name of the target ARM architecture. GCC uses this 156name to determine what kind of instructions it can emit when generating 157assembly code. This option can be used in conjunction with or instead 158of the <samp><span class="option">-mcpu=</span></samp> option. Permissible names are: ‘<samp><span class="samp">armv2</span></samp>’, 159‘<samp><span class="samp">armv2a</span></samp>’, ‘<samp><span class="samp">armv3</span></samp>’, ‘<samp><span class="samp">armv3m</span></samp>’, ‘<samp><span class="samp">armv4</span></samp>’, ‘<samp><span class="samp">armv4t</span></samp>’, 160‘<samp><span class="samp">armv5</span></samp>’, ‘<samp><span class="samp">armv5t</span></samp>’, ‘<samp><span class="samp">armv5e</span></samp>’, ‘<samp><span class="samp">armv5te</span></samp>’, 161‘<samp><span class="samp">armv6</span></samp>’, ‘<samp><span class="samp">armv6j</span></samp>’, 162‘<samp><span class="samp">armv6t2</span></samp>’, ‘<samp><span class="samp">armv6z</span></samp>’, ‘<samp><span class="samp">armv6zk</span></samp>’, ‘<samp><span class="samp">armv6-m</span></samp>’, 163‘<samp><span class="samp">armv7</span></samp>’, ‘<samp><span class="samp">armv7-a</span></samp>’, ‘<samp><span class="samp">armv7-r</span></samp>’, ‘<samp><span class="samp">armv7-m</span></samp>’, 164‘<samp><span class="samp">iwmmxt</span></samp>’, ‘<samp><span class="samp">iwmmxt2</span></samp>’, ‘<samp><span class="samp">ep9312</span></samp>’. 165 166 <br><dt><code>-mfpu=</code><var>name</var><dt><code>-mfpe=</code><var>number</var><dt><code>-mfp=</code><var>number</var><dd><a name="index-mfpu-1045"></a><a name="index-mfpe-1046"></a><a name="index-mfp-1047"></a>This specifies what floating point hardware (or hardware emulation) is 167available on the target. Permissible names are: ‘<samp><span class="samp">fpa</span></samp>’, ‘<samp><span class="samp">fpe2</span></samp>’, 168‘<samp><span class="samp">fpe3</span></samp>’, ‘<samp><span class="samp">maverick</span></samp>’, ‘<samp><span class="samp">vfp</span></samp>’, ‘<samp><span class="samp">vfpv3</span></samp>’, ‘<samp><span class="samp">vfpv3-fp16</span></samp>’, 169‘<samp><span class="samp">vfpv3-d16</span></samp>’, ‘<samp><span class="samp">vfpv3-d16-fp16</span></samp>’, ‘<samp><span class="samp">vfpv3xd</span></samp>’, ‘<samp><span class="samp">vfpv3xd-fp16</span></samp>’, 170‘<samp><span class="samp">neon</span></samp>’, ‘<samp><span class="samp">neon-fp16</span></samp>’, ‘<samp><span class="samp">vfpv4</span></samp>’, ‘<samp><span class="samp">vfpv4-d16</span></samp>’, 171‘<samp><span class="samp">fpv4-sp-d16</span></samp>’ and ‘<samp><span class="samp">neon-vfpv4</span></samp>’. 172<samp><span class="option">-mfp</span></samp> and <samp><span class="option">-mfpe</span></samp> are synonyms for 173<samp><span class="option">-mfpu</span></samp>=‘<samp><span class="samp">fpe</span></samp>’<var>number</var>, for compatibility with older versions 174of GCC. 175 176 <p>If <samp><span class="option">-msoft-float</span></samp> is specified this specifies the format of 177floating point values. 178 179 <p>If the selected floating-point hardware includes the NEON extension 180(e.g. <samp><span class="option">-mfpu</span></samp>=‘<samp><span class="samp">neon</span></samp>’), note that floating-point 181operations will not be used by GCC's auto-vectorization pass unless 182<samp><span class="option">-funsafe-math-optimizations</span></samp> is also specified. This is 183because NEON hardware does not fully implement the IEEE 754 standard for 184floating-point arithmetic (in particular denormal values are treated as 185zero), so the use of NEON instructions may lead to a loss of precision. 186 187 <br><dt><code>-mfp16-format=</code><var>name</var><dd><a name="index-mfp16_002dformat-1048"></a>Specify the format of the <code>__fp16</code> half-precision floating-point type. 188Permissible names are ‘<samp><span class="samp">none</span></samp>’, ‘<samp><span class="samp">ieee</span></samp>’, and ‘<samp><span class="samp">alternative</span></samp>’; 189the default is ‘<samp><span class="samp">none</span></samp>’, in which case the <code>__fp16</code> type is not 190defined. See <a href="Half_002dPrecision.html#Half_002dPrecision">Half-Precision</a>, for more information. 191 192 <br><dt><code>-mstructure-size-boundary=</code><var>n</var><dd><a name="index-mstructure_002dsize_002dboundary-1049"></a>The size of all structures and unions will be rounded up to a multiple 193of the number of bits set by this option. Permissible values are 8, 32 194and 64. The default value varies for different toolchains. For the COFF 195targeted toolchain the default value is 8. A value of 64 is only allowed 196if the underlying ABI supports it. 197 198 <p>Specifying the larger number can produce faster, more efficient code, but 199can also increase the size of the program. Different values are potentially 200incompatible. Code compiled with one value cannot necessarily expect to 201work with code or libraries compiled with another value, if they exchange 202information using structures or unions. 203 204 <br><dt><code>-mabort-on-noreturn</code><dd><a name="index-mabort_002don_002dnoreturn-1050"></a>Generate a call to the function <code>abort</code> at the end of a 205<code>noreturn</code> function. It will be executed if the function tries to 206return. 207 208 <br><dt><code>-mlong-calls</code><dt><code>-mno-long-calls</code><dd><a name="index-mlong_002dcalls-1051"></a><a name="index-mno_002dlong_002dcalls-1052"></a>Tells the compiler to perform function calls by first loading the 209address of the function into a register and then performing a subroutine 210call on this register. This switch is needed if the target function 211will lie outside of the 64 megabyte addressing range of the offset based 212version of subroutine call instruction. 213 214 <p>Even if this switch is enabled, not all function calls will be turned 215into long calls. The heuristic is that static functions, functions 216which have the ‘<samp><span class="samp">short-call</span></samp>’ attribute, functions that are inside 217the scope of a ‘<samp><span class="samp">#pragma no_long_calls</span></samp>’ directive and functions whose 218definitions have already been compiled within the current compilation 219unit, will not be turned into long calls. The exception to this rule is 220that weak function definitions, functions with the ‘<samp><span class="samp">long-call</span></samp>’ 221attribute or the ‘<samp><span class="samp">section</span></samp>’ attribute, and functions that are within 222the scope of a ‘<samp><span class="samp">#pragma long_calls</span></samp>’ directive, will always be 223turned into long calls. 224 225 <p>This feature is not enabled by default. Specifying 226<samp><span class="option">-mno-long-calls</span></samp> will restore the default behavior, as will 227placing the function calls within the scope of a ‘<samp><span class="samp">#pragma 228long_calls_off</span></samp>’ directive. Note these switches have no effect on how 229the compiler generates code to handle function calls via function 230pointers. 231 232 <br><dt><code>-msingle-pic-base</code><dd><a name="index-msingle_002dpic_002dbase-1053"></a>Treat the register used for PIC addressing as read-only, rather than 233loading it in the prologue for each function. The run-time system is 234responsible for initializing this register with an appropriate value 235before execution begins. 236 237 <br><dt><code>-mpic-register=</code><var>reg</var><dd><a name="index-mpic_002dregister-1054"></a>Specify the register to be used for PIC addressing. The default is R10 238unless stack-checking is enabled, when R9 is used. 239 240 <br><dt><code>-mcirrus-fix-invalid-insns</code><dd><a name="index-mcirrus_002dfix_002dinvalid_002dinsns-1055"></a><a name="index-mno_002dcirrus_002dfix_002dinvalid_002dinsns-1056"></a>Insert NOPs into the instruction stream to in order to work around 241problems with invalid Maverick instruction combinations. This option 242is only valid if the <samp><span class="option">-mcpu=ep9312</span></samp> option has been used to 243enable generation of instructions for the Cirrus Maverick floating 244point co-processor. This option is not enabled by default, since the 245problem is only present in older Maverick implementations. The default 246can be re-enabled by use of the <samp><span class="option">-mno-cirrus-fix-invalid-insns</span></samp> 247switch. 248 249 <br><dt><code>-mpoke-function-name</code><dd><a name="index-mpoke_002dfunction_002dname-1057"></a>Write the name of each function into the text section, directly 250preceding the function prologue. The generated code is similar to this: 251 252 <pre class="smallexample"> t0 253 .ascii "arm_poke_function_name", 0 254 .align 255 t1 256 .word 0xff000000 + (t1 - t0) 257 arm_poke_function_name 258 mov ip, sp 259 stmfd sp!, {fp, ip, lr, pc} 260 sub fp, ip, #4 261</pre> 262 <p>When performing a stack backtrace, code can inspect the value of 263<code>pc</code> stored at <code>fp + 0</code>. If the trace function then looks at 264location <code>pc - 12</code> and the top 8 bits are set, then we know that 265there is a function name embedded immediately preceding this location 266and has length <code>((pc[-3]) & 0xff000000)</code>. 267 268 <br><dt><code>-mthumb</code><dd><a name="index-mthumb-1058"></a>Generate code for the Thumb instruction set. The default is to 269use the 32-bit ARM instruction set. 270This option automatically enables either 16-bit Thumb-1 or 271mixed 16/32-bit Thumb-2 instructions based on the <samp><span class="option">-mcpu=</span><var>name</var></samp> 272and <samp><span class="option">-march=</span><var>name</var></samp> options. This option is not passed to the 273assembler. If you want to force assembler files to be interpreted as Thumb code, 274either add a ‘<samp><span class="samp">.thumb</span></samp>’ directive to the source or pass the <samp><span class="option">-mthumb</span></samp> 275option directly to the assembler by prefixing it with <samp><span class="option">-Wa</span></samp>. 276 277 <br><dt><code>-mtpcs-frame</code><dd><a name="index-mtpcs_002dframe-1059"></a>Generate a stack frame that is compliant with the Thumb Procedure Call 278Standard for all non-leaf functions. (A leaf function is one that does 279not call any other functions.) The default is <samp><span class="option">-mno-tpcs-frame</span></samp>. 280 281 <br><dt><code>-mtpcs-leaf-frame</code><dd><a name="index-mtpcs_002dleaf_002dframe-1060"></a>Generate a stack frame that is compliant with the Thumb Procedure Call 282Standard for all leaf functions. (A leaf function is one that does 283not call any other functions.) The default is <samp><span class="option">-mno-apcs-leaf-frame</span></samp>. 284 285 <br><dt><code>-mcallee-super-interworking</code><dd><a name="index-mcallee_002dsuper_002dinterworking-1061"></a>Gives all externally visible functions in the file being compiled an ARM 286instruction set header which switches to Thumb mode before executing the 287rest of the function. This allows these functions to be called from 288non-interworking code. This option is not valid in AAPCS configurations 289because interworking is enabled by default. 290 291 <br><dt><code>-mcaller-super-interworking</code><dd><a name="index-mcaller_002dsuper_002dinterworking-1062"></a>Allows calls via function pointers (including virtual functions) to 292execute correctly regardless of whether the target code has been 293compiled for interworking or not. There is a small overhead in the cost 294of executing a function pointer if this option is enabled. This option 295is not valid in AAPCS configurations because interworking is enabled 296by default. 297 298 <br><dt><code>-mtp=</code><var>name</var><dd><a name="index-mtp-1063"></a>Specify the access model for the thread local storage pointer. The valid 299models are <samp><span class="option">soft</span></samp>, which generates calls to <code>__aeabi_read_tp</code>, 300<samp><span class="option">cp15</span></samp>, which fetches the thread pointer from <code>cp15</code> directly 301(supported in the arm6k architecture), and <samp><span class="option">auto</span></samp>, which uses the 302best available method for the selected processor. The default setting is 303<samp><span class="option">auto</span></samp>. 304 305 <br><dt><code>-mtls-dialect=</code><var>dialect</var><dd><a name="index-mtls_002ddialect-1064"></a>Specify the dialect to use for accessing thread local storage. Two 306dialects are supported - <samp><span class="option">gnu</span></samp> and <samp><span class="option">gnu2</span></samp>. The 307<samp><span class="option">gnu</span></samp> dialect selects the original GNU scheme for supporting 308local and global dynamic TLS models. The <samp><span class="option">gnu2</span></samp> dialect 309selects the GNU descriptor scheme, which provides better performance 310for shared libraries. The GNU descriptor scheme is compatible with 311the original scheme, but does require new assembler, linker and 312library support. Initial and local exec TLS models are unaffected by 313this option and always use the original scheme. 314 315 <br><dt><code>-mword-relocations</code><dd><a name="index-mword_002drelocations-1065"></a>Only generate absolute relocations on word sized values (i.e. R_ARM_ABS32). 316This is enabled by default on targets (uClinux, SymbianOS) where the runtime 317loader imposes this restriction, and when <samp><span class="option">-fpic</span></samp> or <samp><span class="option">-fPIC</span></samp> 318is specified. 319 320 <br><dt><code>-mfix-cortex-m3-ldrd</code><dd><a name="index-mfix_002dcortex_002dm3_002dldrd-1066"></a>Some Cortex-M3 cores can cause data corruption when <code>ldrd</code> instructions 321with overlapping destination and base registers are used. This option avoids 322generating these instructions. This option is enabled by default when 323<samp><span class="option">-mcpu=cortex-m3</span></samp> is specified. 324 325 </dl> 326 327 </body></html> 328 329