1/* This file contains the definitions and documentation for the 2 Register Transfer Expressions (rtx's) that make up the 3 Register Transfer Language (rtl) used in the Back End of the GNU compiler. 4 Copyright (C) 1987, 1988, 1992, 1994, 1995, 1997, 1998, 1999, 2000, 2004, 5 2005, 2006, 2007, 2008, 2009, 2010 6 Free Software Foundation, Inc. 7 8This file is part of GCC. 9 10GCC is free software; you can redistribute it and/or modify it under 11the terms of the GNU General Public License as published by the Free 12Software Foundation; either version 3, or (at your option) any later 13version. 14 15GCC is distributed in the hope that it will be useful, but WITHOUT ANY 16WARRANTY; without even the implied warranty of MERCHANTABILITY or 17FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 18for more details. 19 20You should have received a copy of the GNU General Public License 21along with GCC; see the file COPYING3. If not see 22<http://www.gnu.org/licenses/>. */ 23 24 25/* Expression definitions and descriptions for all targets are in this file. 26 Some will not be used for some targets. 27 28 The fields in the cpp macro call "DEF_RTL_EXPR()" 29 are used to create declarations in the C source of the compiler. 30 31 The fields are: 32 33 1. The internal name of the rtx used in the C source. 34 It is a tag in the enumeration "enum rtx_code" defined in "rtl.h". 35 By convention these are in UPPER_CASE. 36 37 2. The name of the rtx in the external ASCII format read by 38 read_rtx(), and printed by print_rtx(). 39 These names are stored in rtx_name[]. 40 By convention these are the internal (field 1) names in lower_case. 41 42 3. The print format, and type of each rtx->u.fld[] (field) in this rtx. 43 These formats are stored in rtx_format[]. 44 The meaning of the formats is documented in front of this array in rtl.c 45 46 4. The class of the rtx. These are stored in rtx_class and are accessed 47 via the GET_RTX_CLASS macro. They are defined as follows: 48 49 RTX_CONST_OBJ 50 an rtx code that can be used to represent a constant object 51 (e.g, CONST_INT) 52 RTX_OBJ 53 an rtx code that can be used to represent an object (e.g, REG, MEM) 54 RTX_COMPARE 55 an rtx code for a comparison (e.g, LT, GT) 56 RTX_COMM_COMPARE 57 an rtx code for a commutative comparison (e.g, EQ, NE, ORDERED) 58 RTX_UNARY 59 an rtx code for a unary arithmetic expression (e.g, NEG, NOT) 60 RTX_COMM_ARITH 61 an rtx code for a commutative binary operation (e.g,, PLUS, MULT) 62 RTX_TERNARY 63 an rtx code for a non-bitfield three input operation (IF_THEN_ELSE) 64 RTX_BIN_ARITH 65 an rtx code for a non-commutative binary operation (e.g., MINUS, DIV) 66 RTX_BITFIELD_OPS 67 an rtx code for a bit-field operation (ZERO_EXTRACT, SIGN_EXTRACT) 68 RTX_INSN 69 an rtx code for a machine insn (INSN, JUMP_INSN, CALL_INSN) 70 RTX_MATCH 71 an rtx code for something that matches in insns (e.g, MATCH_DUP) 72 RTX_AUTOINC 73 an rtx code for autoincrement addressing modes (e.g. POST_DEC) 74 RTX_EXTRA 75 everything else 76 77 All of the expressions that appear only in machine descriptions, 78 not in RTL used by the compiler itself, are at the end of the file. */ 79 80/* Unknown, or no such operation; the enumeration constant should have 81 value zero. */ 82DEF_RTL_EXPR(UNKNOWN, "UnKnown", "*", RTX_EXTRA) 83 84/* Used in the cselib routines to describe a value. Objects of this 85 kind are only allocated in cselib.c, in an alloc pool instead of in 86 GC memory. The only operand of a VALUE is a cselib_val_struct. 87 var-tracking requires this to have a distinct integral value from 88 DECL codes in trees. */ 89DEF_RTL_EXPR(VALUE, "value", "0", RTX_OBJ) 90 91/* The RTL generated for a DEBUG_EXPR_DECL. It links back to the 92 DEBUG_EXPR_DECL in the first operand. */ 93DEF_RTL_EXPR(DEBUG_EXPR, "debug_expr", "0", RTX_OBJ) 94 95/* --------------------------------------------------------------------- 96 Expressions used in constructing lists. 97 --------------------------------------------------------------------- */ 98 99/* a linked list of expressions */ 100DEF_RTL_EXPR(EXPR_LIST, "expr_list", "ee", RTX_EXTRA) 101 102/* a linked list of instructions. 103 The insns are represented in print by their uids. */ 104DEF_RTL_EXPR(INSN_LIST, "insn_list", "ue", RTX_EXTRA) 105 106/* SEQUENCE appears in the result of a `gen_...' function 107 for a DEFINE_EXPAND that wants to make several insns. 108 Its elements are the bodies of the insns that should be made. 109 `emit_insn' takes the SEQUENCE apart and makes separate insns. */ 110DEF_RTL_EXPR(SEQUENCE, "sequence", "E", RTX_EXTRA) 111 112/* Refers to the address of its argument. This is only used in alias.c. */ 113DEF_RTL_EXPR(ADDRESS, "address", "e", RTX_MATCH) 114 115/* ---------------------------------------------------------------------- 116 Expression types used for things in the instruction chain. 117 118 All formats must start with "iuu" to handle the chain. 119 Each insn expression holds an rtl instruction and its semantics 120 during back-end processing. 121 See macros's in "rtl.h" for the meaning of each rtx->u.fld[]. 122 123 ---------------------------------------------------------------------- */ 124 125/* An annotation for variable assignment tracking. */ 126DEF_RTL_EXPR(DEBUG_INSN, "debug_insn", "iuuBeiie", RTX_INSN) 127 128/* An instruction that cannot jump. */ 129DEF_RTL_EXPR(INSN, "insn", "iuuBeiie", RTX_INSN) 130 131/* An instruction that can possibly jump. 132 Fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ 133DEF_RTL_EXPR(JUMP_INSN, "jump_insn", "iuuBeiie0", RTX_INSN) 134 135/* An instruction that can possibly call a subroutine 136 but which will not change which instruction comes next 137 in the current function. 138 Field ( rtx->u.fld[8] ) is CALL_INSN_FUNCTION_USAGE. 139 All other fields ( rtx->u.fld[] ) have exact same meaning as INSN's. */ 140DEF_RTL_EXPR(CALL_INSN, "call_insn", "iuuBeiiee", RTX_INSN) 141 142/* A marker that indicates that control will not flow through. */ 143DEF_RTL_EXPR(BARRIER, "barrier", "iuu00000", RTX_EXTRA) 144 145/* Holds a label that is followed by instructions. 146 Operand: 147 4: is used in jump.c for the use-count of the label. 148 5: is used in the sh backend. 149 6: is a number that is unique in the entire compilation. 150 7: is the user-given name of the label, if any. */ 151DEF_RTL_EXPR(CODE_LABEL, "code_label", "iuuB00is", RTX_EXTRA) 152 153/* Say where in the code a source line starts, for symbol table's sake. 154 Operand: 155 4: note-specific data 156 5: enum insn_note 157 6: unique number if insn_note == note_insn_deleted_label. */ 158DEF_RTL_EXPR(NOTE, "note", "iuuB0ni", RTX_EXTRA) 159 160/* ---------------------------------------------------------------------- 161 Top level constituents of INSN, JUMP_INSN and CALL_INSN. 162 ---------------------------------------------------------------------- */ 163 164/* Conditionally execute code. 165 Operand 0 is the condition that if true, the code is executed. 166 Operand 1 is the code to be executed (typically a SET). 167 168 Semantics are that there are no side effects if the condition 169 is false. This pattern is created automatically by the if_convert 170 pass run after reload or by target-specific splitters. */ 171DEF_RTL_EXPR(COND_EXEC, "cond_exec", "ee", RTX_EXTRA) 172 173/* Several operations to be done in parallel (perhaps under COND_EXEC). */ 174DEF_RTL_EXPR(PARALLEL, "parallel", "E", RTX_EXTRA) 175 176/* A string that is passed through to the assembler as input. 177 One can obviously pass comments through by using the 178 assembler comment syntax. 179 These occur in an insn all by themselves as the PATTERN. 180 They also appear inside an ASM_OPERANDS 181 as a convenient way to hold a string. */ 182DEF_RTL_EXPR(ASM_INPUT, "asm_input", "si", RTX_EXTRA) 183 184/* An assembler instruction with operands. 185 1st operand is the instruction template. 186 2nd operand is the constraint for the output. 187 3rd operand is the number of the output this expression refers to. 188 When an insn stores more than one value, a separate ASM_OPERANDS 189 is made for each output; this integer distinguishes them. 190 4th is a vector of values of input operands. 191 5th is a vector of modes and constraints for the input operands. 192 Each element is an ASM_INPUT containing a constraint string 193 and whose mode indicates the mode of the input operand. 194 6th is a vector of labels that may be branched to by the asm. 195 7th is the source line number. */ 196DEF_RTL_EXPR(ASM_OPERANDS, "asm_operands", "ssiEEEi", RTX_EXTRA) 197 198/* A machine-specific operation. 199 1st operand is a vector of operands being used by the operation so that 200 any needed reloads can be done. 201 2nd operand is a unique value saying which of a number of machine-specific 202 operations is to be performed. 203 (Note that the vector must be the first operand because of the way that 204 genrecog.c record positions within an insn.) 205 206 UNSPEC can occur all by itself in a PATTERN, as a component of a PARALLEL, 207 or inside an expression. 208 UNSPEC by itself or as a component of a PARALLEL 209 is currently considered not deletable. 210 211 FIXME: Replace all uses of UNSPEC that appears by itself or as a component 212 of a PARALLEL with USE. 213 */ 214DEF_RTL_EXPR(UNSPEC, "unspec", "Ei", RTX_EXTRA) 215 216/* Similar, but a volatile operation and one which may trap. */ 217DEF_RTL_EXPR(UNSPEC_VOLATILE, "unspec_volatile", "Ei", RTX_EXTRA) 218 219/* Vector of addresses, stored as full words. */ 220/* Each element is a LABEL_REF to a CODE_LABEL whose address we want. */ 221DEF_RTL_EXPR(ADDR_VEC, "addr_vec", "E", RTX_EXTRA) 222 223/* Vector of address differences X0 - BASE, X1 - BASE, ... 224 First operand is BASE; the vector contains the X's. 225 The machine mode of this rtx says how much space to leave 226 for each difference and is adjusted by branch shortening if 227 CASE_VECTOR_SHORTEN_MODE is defined. 228 The third and fourth operands store the target labels with the 229 minimum and maximum addresses respectively. 230 The fifth operand stores flags for use by branch shortening. 231 Set at the start of shorten_branches: 232 min_align: the minimum alignment for any of the target labels. 233 base_after_vec: true iff BASE is after the ADDR_DIFF_VEC. 234 min_after_vec: true iff minimum addr target label is after the ADDR_DIFF_VEC. 235 max_after_vec: true iff maximum addr target label is after the ADDR_DIFF_VEC. 236 min_after_base: true iff minimum address target label is after BASE. 237 max_after_base: true iff maximum address target label is after BASE. 238 Set by the actual branch shortening process: 239 offset_unsigned: true iff offsets have to be treated as unsigned. 240 scale: scaling that is necessary to make offsets fit into the mode. 241 242 The third, fourth and fifth operands are only valid when 243 CASE_VECTOR_SHORTEN_MODE is defined, and only in an optimizing 244 compilations. */ 245 246DEF_RTL_EXPR(ADDR_DIFF_VEC, "addr_diff_vec", "eEee0", RTX_EXTRA) 247 248/* Memory prefetch, with attributes supported on some targets. 249 Operand 1 is the address of the memory to fetch. 250 Operand 2 is 1 for a write access, 0 otherwise. 251 Operand 3 is the level of temporal locality; 0 means there is no 252 temporal locality and 1, 2, and 3 are for increasing levels of temporal 253 locality. 254 255 The attributes specified by operands 2 and 3 are ignored for targets 256 whose prefetch instructions do not support them. */ 257DEF_RTL_EXPR(PREFETCH, "prefetch", "eee", RTX_EXTRA) 258 259/* ---------------------------------------------------------------------- 260 At the top level of an instruction (perhaps under PARALLEL). 261 ---------------------------------------------------------------------- */ 262 263/* Assignment. 264 Operand 1 is the location (REG, MEM, PC, CC0 or whatever) assigned to. 265 Operand 2 is the value stored there. 266 ALL assignment must use SET. 267 Instructions that do multiple assignments must use multiple SET, 268 under PARALLEL. */ 269DEF_RTL_EXPR(SET, "set", "ee", RTX_EXTRA) 270 271/* Indicate something is used in a way that we don't want to explain. 272 For example, subroutine calls will use the register 273 in which the static chain is passed. 274 275 USE can not appear as an operand of other rtx except for PARALLEL. 276 USE is not deletable, as it indicates that the operand 277 is used in some unknown way. */ 278DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA) 279 280/* Indicate something is clobbered in a way that we don't want to explain. 281 For example, subroutine calls will clobber some physical registers 282 (the ones that are by convention not saved). 283 284 CLOBBER can not appear as an operand of other rtx except for PARALLEL. 285 CLOBBER of a hard register appearing by itself (not within PARALLEL) 286 is considered undeletable before reload. */ 287DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA) 288 289/* Call a subroutine. 290 Operand 1 is the address to call. 291 Operand 2 is the number of arguments. */ 292 293DEF_RTL_EXPR(CALL, "call", "ee", RTX_EXTRA) 294 295/* Return from a subroutine. */ 296 297DEF_RTL_EXPR(RETURN, "return", "", RTX_EXTRA) 298 299/* A plain return, to be used on paths that are reached without going 300 through the function prologue. */ 301DEF_RTL_EXPR(SIMPLE_RETURN, "simple_return", "", RTX_EXTRA) 302 303/* Special for EH return from subroutine. */ 304 305DEF_RTL_EXPR(EH_RETURN, "eh_return", "", RTX_EXTRA) 306 307/* Conditional trap. 308 Operand 1 is the condition. 309 Operand 2 is the trap code. 310 For an unconditional trap, make the condition (const_int 1). */ 311DEF_RTL_EXPR(TRAP_IF, "trap_if", "ee", RTX_EXTRA) 312 313/* ---------------------------------------------------------------------- 314 Primitive values for use in expressions. 315 ---------------------------------------------------------------------- */ 316 317/* numeric integer constant */ 318DEF_RTL_EXPR(CONST_INT, "const_int", "w", RTX_CONST_OBJ) 319 320/* fixed-point constant */ 321DEF_RTL_EXPR(CONST_FIXED, "const_fixed", "www", RTX_CONST_OBJ) 322 323/* numeric floating point constant. 324 Operands hold the value. They are all 'w' and there may be from 2 to 6; 325 see real.h. */ 326DEF_RTL_EXPR(CONST_DOUBLE, "const_double", CONST_DOUBLE_FORMAT, RTX_CONST_OBJ) 327 328/* Describes a vector constant. */ 329DEF_RTL_EXPR(CONST_VECTOR, "const_vector", "E", RTX_CONST_OBJ) 330 331/* String constant. Used for attributes in machine descriptions and 332 for special cases in DWARF2 debug output. NOT used for source- 333 language string constants. */ 334DEF_RTL_EXPR(CONST_STRING, "const_string", "s", RTX_OBJ) 335 336/* This is used to encapsulate an expression whose value is constant 337 (such as the sum of a SYMBOL_REF and a CONST_INT) so that it will be 338 recognized as a constant operand rather than by arithmetic instructions. */ 339 340DEF_RTL_EXPR(CONST, "const", "e", RTX_CONST_OBJ) 341 342/* program counter. Ordinary jumps are represented 343 by a SET whose first operand is (PC). */ 344DEF_RTL_EXPR(PC, "pc", "", RTX_OBJ) 345 346/* A register. The "operand" is the register number, accessed with 347 the REGNO macro. If this number is less than FIRST_PSEUDO_REGISTER 348 than a hardware register is being referred to. The second operand 349 holds the original register number - this will be different for a 350 pseudo register that got turned into a hard register. The third 351 operand points to a reg_attrs structure. 352 This rtx needs to have as many (or more) fields as a MEM, since we 353 can change REG rtx's into MEMs during reload. */ 354DEF_RTL_EXPR(REG, "reg", "i00", RTX_OBJ) 355 356/* A scratch register. This represents a register used only within a 357 single insn. It will be turned into a REG during register allocation 358 or reload unless the constraint indicates that the register won't be 359 needed, in which case it can remain a SCRATCH. This code is 360 marked as having one operand so it can be turned into a REG. */ 361DEF_RTL_EXPR(SCRATCH, "scratch", "0", RTX_OBJ) 362 363/* A reference to a part of another value. The first operand is the 364 complete value and the second is the byte offset of the selected part. */ 365DEF_RTL_EXPR(SUBREG, "subreg", "ei", RTX_EXTRA) 366 367/* This one-argument rtx is used for move instructions 368 that are guaranteed to alter only the low part of a destination. 369 Thus, (SET (SUBREG:HI (REG...)) (MEM:HI ...)) 370 has an unspecified effect on the high part of REG, 371 but (SET (STRICT_LOW_PART (SUBREG:HI (REG...))) (MEM:HI ...)) 372 is guaranteed to alter only the bits of REG that are in HImode. 373 374 The actual instruction used is probably the same in both cases, 375 but the register constraints may be tighter when STRICT_LOW_PART 376 is in use. */ 377 378DEF_RTL_EXPR(STRICT_LOW_PART, "strict_low_part", "e", RTX_EXTRA) 379 380/* (CONCAT a b) represents the virtual concatenation of a and b 381 to make a value that has as many bits as a and b put together. 382 This is used for complex values. Normally it appears only 383 in DECL_RTLs and during RTL generation, but not in the insn chain. */ 384DEF_RTL_EXPR(CONCAT, "concat", "ee", RTX_OBJ) 385 386/* (CONCATN [a1 a2 ... an]) represents the virtual concatenation of 387 all An to make a value. This is an extension of CONCAT to larger 388 number of components. Like CONCAT, it should not appear in the 389 insn chain. Every element of the CONCATN is the same size. */ 390DEF_RTL_EXPR(CONCATN, "concatn", "E", RTX_OBJ) 391 392/* A memory location; operand is the address. The second operand is the 393 alias set to which this MEM belongs. We use `0' instead of `w' for this 394 field so that the field need not be specified in machine descriptions. */ 395DEF_RTL_EXPR(MEM, "mem", "e0", RTX_OBJ) 396 397/* Reference to an assembler label in the code for this function. 398 The operand is a CODE_LABEL found in the insn chain. */ 399DEF_RTL_EXPR(LABEL_REF, "label_ref", "u", RTX_CONST_OBJ) 400 401/* Reference to a named label: 402 Operand 0: label name 403 Operand 1: flags (see SYMBOL_FLAG_* in rtl.h) 404 Operand 2: tree from which this symbol is derived, or null. 405 This is either a DECL node, or some kind of constant. */ 406DEF_RTL_EXPR(SYMBOL_REF, "symbol_ref", "s00", RTX_CONST_OBJ) 407 408/* The condition code register is represented, in our imagination, 409 as a register holding a value that can be compared to zero. 410 In fact, the machine has already compared them and recorded the 411 results; but instructions that look at the condition code 412 pretend to be looking at the entire value and comparing it. */ 413DEF_RTL_EXPR(CC0, "cc0", "", RTX_OBJ) 414 415/* ---------------------------------------------------------------------- 416 Expressions for operators in an rtl pattern 417 ---------------------------------------------------------------------- */ 418 419/* if_then_else. This is used in representing ordinary 420 conditional jump instructions. 421 Operand: 422 0: condition 423 1: then expr 424 2: else expr */ 425DEF_RTL_EXPR(IF_THEN_ELSE, "if_then_else", "eee", RTX_TERNARY) 426 427/* Comparison, produces a condition code result. */ 428DEF_RTL_EXPR(COMPARE, "compare", "ee", RTX_BIN_ARITH) 429 430/* plus */ 431DEF_RTL_EXPR(PLUS, "plus", "ee", RTX_COMM_ARITH) 432 433/* Operand 0 minus operand 1. */ 434DEF_RTL_EXPR(MINUS, "minus", "ee", RTX_BIN_ARITH) 435 436/* Minus operand 0. */ 437DEF_RTL_EXPR(NEG, "neg", "e", RTX_UNARY) 438 439DEF_RTL_EXPR(MULT, "mult", "ee", RTX_COMM_ARITH) 440 441/* Multiplication with signed saturation */ 442DEF_RTL_EXPR(SS_MULT, "ss_mult", "ee", RTX_COMM_ARITH) 443/* Multiplication with unsigned saturation */ 444DEF_RTL_EXPR(US_MULT, "us_mult", "ee", RTX_COMM_ARITH) 445 446/* Operand 0 divided by operand 1. */ 447DEF_RTL_EXPR(DIV, "div", "ee", RTX_BIN_ARITH) 448/* Division with signed saturation */ 449DEF_RTL_EXPR(SS_DIV, "ss_div", "ee", RTX_BIN_ARITH) 450/* Division with unsigned saturation */ 451DEF_RTL_EXPR(US_DIV, "us_div", "ee", RTX_BIN_ARITH) 452 453/* Remainder of operand 0 divided by operand 1. */ 454DEF_RTL_EXPR(MOD, "mod", "ee", RTX_BIN_ARITH) 455 456/* Unsigned divide and remainder. */ 457DEF_RTL_EXPR(UDIV, "udiv", "ee", RTX_BIN_ARITH) 458DEF_RTL_EXPR(UMOD, "umod", "ee", RTX_BIN_ARITH) 459 460/* Bitwise operations. */ 461DEF_RTL_EXPR(AND, "and", "ee", RTX_COMM_ARITH) 462DEF_RTL_EXPR(IOR, "ior", "ee", RTX_COMM_ARITH) 463DEF_RTL_EXPR(XOR, "xor", "ee", RTX_COMM_ARITH) 464DEF_RTL_EXPR(NOT, "not", "e", RTX_UNARY) 465 466/* Operand: 467 0: value to be shifted. 468 1: number of bits. */ 469DEF_RTL_EXPR(ASHIFT, "ashift", "ee", RTX_BIN_ARITH) /* shift left */ 470DEF_RTL_EXPR(ROTATE, "rotate", "ee", RTX_BIN_ARITH) /* rotate left */ 471DEF_RTL_EXPR(ASHIFTRT, "ashiftrt", "ee", RTX_BIN_ARITH) /* arithmetic shift right */ 472DEF_RTL_EXPR(LSHIFTRT, "lshiftrt", "ee", RTX_BIN_ARITH) /* logical shift right */ 473DEF_RTL_EXPR(ROTATERT, "rotatert", "ee", RTX_BIN_ARITH) /* rotate right */ 474 475/* Minimum and maximum values of two operands. We need both signed and 476 unsigned forms. (We cannot use MIN for SMIN because it conflicts 477 with a macro of the same name.) The signed variants should be used 478 with floating point. Further, if both operands are zeros, or if either 479 operand is NaN, then it is unspecified which of the two operands is 480 returned as the result. */ 481 482DEF_RTL_EXPR(SMIN, "smin", "ee", RTX_COMM_ARITH) 483DEF_RTL_EXPR(SMAX, "smax", "ee", RTX_COMM_ARITH) 484DEF_RTL_EXPR(UMIN, "umin", "ee", RTX_COMM_ARITH) 485DEF_RTL_EXPR(UMAX, "umax", "ee", RTX_COMM_ARITH) 486 487/* These unary operations are used to represent incrementation 488 and decrementation as they occur in memory addresses. 489 The amount of increment or decrement are not represented 490 because they can be understood from the machine-mode of the 491 containing MEM. These operations exist in only two cases: 492 1. pushes onto the stack. 493 2. created automatically by the auto-inc-dec pass. */ 494DEF_RTL_EXPR(PRE_DEC, "pre_dec", "e", RTX_AUTOINC) 495DEF_RTL_EXPR(PRE_INC, "pre_inc", "e", RTX_AUTOINC) 496DEF_RTL_EXPR(POST_DEC, "post_dec", "e", RTX_AUTOINC) 497DEF_RTL_EXPR(POST_INC, "post_inc", "e", RTX_AUTOINC) 498 499/* These binary operations are used to represent generic address 500 side-effects in memory addresses, except for simple incrementation 501 or decrementation which use the above operations. They are 502 created automatically by the life_analysis pass in flow.c. 503 The first operand is a REG which is used as the address. 504 The second operand is an expression that is assigned to the 505 register, either before (PRE_MODIFY) or after (POST_MODIFY) 506 evaluating the address. 507 Currently, the compiler can only handle second operands of the 508 form (plus (reg) (reg)) and (plus (reg) (const_int)), where 509 the first operand of the PLUS has to be the same register as 510 the first operand of the *_MODIFY. */ 511DEF_RTL_EXPR(PRE_MODIFY, "pre_modify", "ee", RTX_AUTOINC) 512DEF_RTL_EXPR(POST_MODIFY, "post_modify", "ee", RTX_AUTOINC) 513 514/* Comparison operations. The ordered comparisons exist in two 515 flavors, signed and unsigned. */ 516DEF_RTL_EXPR(NE, "ne", "ee", RTX_COMM_COMPARE) 517DEF_RTL_EXPR(EQ, "eq", "ee", RTX_COMM_COMPARE) 518DEF_RTL_EXPR(GE, "ge", "ee", RTX_COMPARE) 519DEF_RTL_EXPR(GT, "gt", "ee", RTX_COMPARE) 520DEF_RTL_EXPR(LE, "le", "ee", RTX_COMPARE) 521DEF_RTL_EXPR(LT, "lt", "ee", RTX_COMPARE) 522DEF_RTL_EXPR(GEU, "geu", "ee", RTX_COMPARE) 523DEF_RTL_EXPR(GTU, "gtu", "ee", RTX_COMPARE) 524DEF_RTL_EXPR(LEU, "leu", "ee", RTX_COMPARE) 525DEF_RTL_EXPR(LTU, "ltu", "ee", RTX_COMPARE) 526 527/* Additional floating point unordered comparison flavors. */ 528DEF_RTL_EXPR(UNORDERED, "unordered", "ee", RTX_COMM_COMPARE) 529DEF_RTL_EXPR(ORDERED, "ordered", "ee", RTX_COMM_COMPARE) 530 531/* These are equivalent to unordered or ... */ 532DEF_RTL_EXPR(UNEQ, "uneq", "ee", RTX_COMM_COMPARE) 533DEF_RTL_EXPR(UNGE, "unge", "ee", RTX_COMPARE) 534DEF_RTL_EXPR(UNGT, "ungt", "ee", RTX_COMPARE) 535DEF_RTL_EXPR(UNLE, "unle", "ee", RTX_COMPARE) 536DEF_RTL_EXPR(UNLT, "unlt", "ee", RTX_COMPARE) 537 538/* This is an ordered NE, ie !UNEQ, ie false for NaN. */ 539DEF_RTL_EXPR(LTGT, "ltgt", "ee", RTX_COMM_COMPARE) 540 541/* Represents the result of sign-extending the sole operand. 542 The machine modes of the operand and of the SIGN_EXTEND expression 543 determine how much sign-extension is going on. */ 544DEF_RTL_EXPR(SIGN_EXTEND, "sign_extend", "e", RTX_UNARY) 545 546/* Similar for zero-extension (such as unsigned short to int). */ 547DEF_RTL_EXPR(ZERO_EXTEND, "zero_extend", "e", RTX_UNARY) 548 549/* Similar but here the operand has a wider mode. */ 550DEF_RTL_EXPR(TRUNCATE, "truncate", "e", RTX_UNARY) 551 552/* Similar for extending floating-point values (such as SFmode to DFmode). */ 553DEF_RTL_EXPR(FLOAT_EXTEND, "float_extend", "e", RTX_UNARY) 554DEF_RTL_EXPR(FLOAT_TRUNCATE, "float_truncate", "e", RTX_UNARY) 555 556/* Conversion of fixed point operand to floating point value. */ 557DEF_RTL_EXPR(FLOAT, "float", "e", RTX_UNARY) 558 559/* With fixed-point machine mode: 560 Conversion of floating point operand to fixed point value. 561 Value is defined only when the operand's value is an integer. 562 With floating-point machine mode (and operand with same mode): 563 Operand is rounded toward zero to produce an integer value 564 represented in floating point. */ 565DEF_RTL_EXPR(FIX, "fix", "e", RTX_UNARY) 566 567/* Conversion of unsigned fixed point operand to floating point value. */ 568DEF_RTL_EXPR(UNSIGNED_FLOAT, "unsigned_float", "e", RTX_UNARY) 569 570/* With fixed-point machine mode: 571 Conversion of floating point operand to *unsigned* fixed point value. 572 Value is defined only when the operand's value is an integer. */ 573DEF_RTL_EXPR(UNSIGNED_FIX, "unsigned_fix", "e", RTX_UNARY) 574 575/* Conversions involving fractional fixed-point types without saturation, 576 including: 577 fractional to fractional (of different precision), 578 signed integer to fractional, 579 fractional to signed integer, 580 floating point to fractional, 581 fractional to floating point. 582 NOTE: fractional can be either signed or unsigned for conversions. */ 583DEF_RTL_EXPR(FRACT_CONVERT, "fract_convert", "e", RTX_UNARY) 584 585/* Conversions involving fractional fixed-point types and unsigned integer 586 without saturation, including: 587 unsigned integer to fractional, 588 fractional to unsigned integer. 589 NOTE: fractional can be either signed or unsigned for conversions. */ 590DEF_RTL_EXPR(UNSIGNED_FRACT_CONVERT, "unsigned_fract_convert", "e", RTX_UNARY) 591 592/* Conversions involving fractional fixed-point types with saturation, 593 including: 594 fractional to fractional (of different precision), 595 signed integer to fractional, 596 floating point to fractional. 597 NOTE: fractional can be either signed or unsigned for conversions. */ 598DEF_RTL_EXPR(SAT_FRACT, "sat_fract", "e", RTX_UNARY) 599 600/* Conversions involving fractional fixed-point types and unsigned integer 601 with saturation, including: 602 unsigned integer to fractional. 603 NOTE: fractional can be either signed or unsigned for conversions. */ 604DEF_RTL_EXPR(UNSIGNED_SAT_FRACT, "unsigned_sat_fract", "e", RTX_UNARY) 605 606/* Absolute value */ 607DEF_RTL_EXPR(ABS, "abs", "e", RTX_UNARY) 608 609/* Square root */ 610DEF_RTL_EXPR(SQRT, "sqrt", "e", RTX_UNARY) 611 612/* Swap bytes. */ 613DEF_RTL_EXPR(BSWAP, "bswap", "e", RTX_UNARY) 614 615/* Find first bit that is set. 616 Value is 1 + number of trailing zeros in the arg., 617 or 0 if arg is 0. */ 618DEF_RTL_EXPR(FFS, "ffs", "e", RTX_UNARY) 619 620/* Count leading zeros. */ 621DEF_RTL_EXPR(CLZ, "clz", "e", RTX_UNARY) 622 623/* Count trailing zeros. */ 624DEF_RTL_EXPR(CTZ, "ctz", "e", RTX_UNARY) 625 626/* Population count (number of 1 bits). */ 627DEF_RTL_EXPR(POPCOUNT, "popcount", "e", RTX_UNARY) 628 629/* Population parity (number of 1 bits modulo 2). */ 630DEF_RTL_EXPR(PARITY, "parity", "e", RTX_UNARY) 631 632/* Reference to a signed bit-field of specified size and position. 633 Operand 0 is the memory unit (usually SImode or QImode) which 634 contains the field's first bit. Operand 1 is the width, in bits. 635 Operand 2 is the number of bits in the memory unit before the 636 first bit of this field. 637 If BITS_BIG_ENDIAN is defined, the first bit is the msb and 638 operand 2 counts from the msb of the memory unit. 639 Otherwise, the first bit is the lsb and operand 2 counts from 640 the lsb of the memory unit. 641 This kind of expression can not appear as an lvalue in RTL. */ 642DEF_RTL_EXPR(SIGN_EXTRACT, "sign_extract", "eee", RTX_BITFIELD_OPS) 643 644/* Similar for unsigned bit-field. 645 But note! This kind of expression _can_ appear as an lvalue. */ 646DEF_RTL_EXPR(ZERO_EXTRACT, "zero_extract", "eee", RTX_BITFIELD_OPS) 647 648/* For RISC machines. These save memory when splitting insns. */ 649 650/* HIGH are the high-order bits of a constant expression. */ 651DEF_RTL_EXPR(HIGH, "high", "e", RTX_CONST_OBJ) 652 653/* LO_SUM is the sum of a register and the low-order bits 654 of a constant expression. */ 655DEF_RTL_EXPR(LO_SUM, "lo_sum", "ee", RTX_OBJ) 656 657/* Describes a merge operation between two vector values. 658 Operands 0 and 1 are the vectors to be merged, operand 2 is a bitmask 659 that specifies where the parts of the result are taken from. Set bits 660 indicate operand 0, clear bits indicate operand 1. The parts are defined 661 by the mode of the vectors. */ 662DEF_RTL_EXPR(VEC_MERGE, "vec_merge", "eee", RTX_TERNARY) 663 664/* Describes an operation that selects parts of a vector. 665 Operands 0 is the source vector, operand 1 is a PARALLEL that contains 666 a CONST_INT for each of the subparts of the result vector, giving the 667 number of the source subpart that should be stored into it. */ 668DEF_RTL_EXPR(VEC_SELECT, "vec_select", "ee", RTX_BIN_ARITH) 669 670/* Describes a vector concat operation. Operands 0 and 1 are the source 671 vectors, the result is a vector that is as long as operands 0 and 1 672 combined and is the concatenation of the two source vectors. */ 673DEF_RTL_EXPR(VEC_CONCAT, "vec_concat", "ee", RTX_BIN_ARITH) 674 675/* Describes an operation that converts a small vector into a larger one by 676 duplicating the input values. The output vector mode must have the same 677 submodes as the input vector mode, and the number of output parts must be 678 an integer multiple of the number of input parts. */ 679DEF_RTL_EXPR(VEC_DUPLICATE, "vec_duplicate", "e", RTX_UNARY) 680 681/* Addition with signed saturation */ 682DEF_RTL_EXPR(SS_PLUS, "ss_plus", "ee", RTX_COMM_ARITH) 683 684/* Addition with unsigned saturation */ 685DEF_RTL_EXPR(US_PLUS, "us_plus", "ee", RTX_COMM_ARITH) 686 687/* Operand 0 minus operand 1, with signed saturation. */ 688DEF_RTL_EXPR(SS_MINUS, "ss_minus", "ee", RTX_BIN_ARITH) 689 690/* Negation with signed saturation. */ 691DEF_RTL_EXPR(SS_NEG, "ss_neg", "e", RTX_UNARY) 692/* Negation with unsigned saturation. */ 693DEF_RTL_EXPR(US_NEG, "us_neg", "e", RTX_UNARY) 694 695/* Absolute value with signed saturation. */ 696DEF_RTL_EXPR(SS_ABS, "ss_abs", "e", RTX_UNARY) 697 698/* Shift left with signed saturation. */ 699DEF_RTL_EXPR(SS_ASHIFT, "ss_ashift", "ee", RTX_BIN_ARITH) 700 701/* Shift left with unsigned saturation. */ 702DEF_RTL_EXPR(US_ASHIFT, "us_ashift", "ee", RTX_BIN_ARITH) 703 704/* Operand 0 minus operand 1, with unsigned saturation. */ 705DEF_RTL_EXPR(US_MINUS, "us_minus", "ee", RTX_BIN_ARITH) 706 707/* Signed saturating truncate. */ 708DEF_RTL_EXPR(SS_TRUNCATE, "ss_truncate", "e", RTX_UNARY) 709 710/* Unsigned saturating truncate. */ 711DEF_RTL_EXPR(US_TRUNCATE, "us_truncate", "e", RTX_UNARY) 712 713/* Floating point multiply/add combined instruction. */ 714DEF_RTL_EXPR(FMA, "fma", "eee", RTX_TERNARY) 715 716/* Information about the variable and its location. */ 717/* Changed 'te' to 'tei'; the 'i' field is for recording 718 initialization status of variables. */ 719DEF_RTL_EXPR(VAR_LOCATION, "var_location", "tei", RTX_EXTRA) 720 721/* Used in VAR_LOCATION for a pointer to a decl that is no longer 722 addressable. */ 723DEF_RTL_EXPR(DEBUG_IMPLICIT_PTR, "debug_implicit_ptr", "t", RTX_OBJ) 724 725/* All expressions from this point forward appear only in machine 726 descriptions. */ 727#ifdef GENERATOR_FILE 728 729/* Pattern-matching operators: */ 730 731/* Use the function named by the second arg (the string) 732 as a predicate; if matched, store the structure that was matched 733 in the operand table at index specified by the first arg (the integer). 734 If the second arg is the null string, the structure is just stored. 735 736 A third string argument indicates to the register allocator restrictions 737 on where the operand can be allocated. 738 739 If the target needs no restriction on any instruction this field should 740 be the null string. 741 742 The string is prepended by: 743 '=' to indicate the operand is only written to. 744 '+' to indicate the operand is both read and written to. 745 746 Each character in the string represents an allocable class for an operand. 747 'g' indicates the operand can be any valid class. 748 'i' indicates the operand can be immediate (in the instruction) data. 749 'r' indicates the operand can be in a register. 750 'm' indicates the operand can be in memory. 751 'o' a subset of the 'm' class. Those memory addressing modes that 752 can be offset at compile time (have a constant added to them). 753 754 Other characters indicate target dependent operand classes and 755 are described in each target's machine description. 756 757 For instructions with more than one operand, sets of classes can be 758 separated by a comma to indicate the appropriate multi-operand constraints. 759 There must be a 1 to 1 correspondence between these sets of classes in 760 all operands for an instruction. 761 */ 762DEF_RTL_EXPR(MATCH_OPERAND, "match_operand", "iss", RTX_MATCH) 763 764/* Match a SCRATCH or a register. When used to generate rtl, a 765 SCRATCH is generated. As for MATCH_OPERAND, the mode specifies 766 the desired mode and the first argument is the operand number. 767 The second argument is the constraint. */ 768DEF_RTL_EXPR(MATCH_SCRATCH, "match_scratch", "is", RTX_MATCH) 769 770/* Apply a predicate, AND match recursively the operands of the rtx. 771 Operand 0 is the operand-number, as in match_operand. 772 Operand 1 is a predicate to apply (as a string, a function name). 773 Operand 2 is a vector of expressions, each of which must match 774 one subexpression of the rtx this construct is matching. */ 775DEF_RTL_EXPR(MATCH_OPERATOR, "match_operator", "isE", RTX_MATCH) 776 777/* Match a PARALLEL of arbitrary length. The predicate is applied 778 to the PARALLEL and the initial expressions in the PARALLEL are matched. 779 Operand 0 is the operand-number, as in match_operand. 780 Operand 1 is a predicate to apply to the PARALLEL. 781 Operand 2 is a vector of expressions, each of which must match the 782 corresponding element in the PARALLEL. */ 783DEF_RTL_EXPR(MATCH_PARALLEL, "match_parallel", "isE", RTX_MATCH) 784 785/* Match only something equal to what is stored in the operand table 786 at the index specified by the argument. Use with MATCH_OPERAND. */ 787DEF_RTL_EXPR(MATCH_DUP, "match_dup", "i", RTX_MATCH) 788 789/* Match only something equal to what is stored in the operand table 790 at the index specified by the argument. Use with MATCH_OPERATOR. */ 791DEF_RTL_EXPR(MATCH_OP_DUP, "match_op_dup", "iE", RTX_MATCH) 792 793/* Match only something equal to what is stored in the operand table 794 at the index specified by the argument. Use with MATCH_PARALLEL. */ 795DEF_RTL_EXPR(MATCH_PAR_DUP, "match_par_dup", "iE", RTX_MATCH) 796 797/* Appears only in define_predicate/define_special_predicate 798 expressions. Evaluates true only if the operand has an RTX code 799 from the set given by the argument (a comma-separated list). If the 800 second argument is present and nonempty, it is a sequence of digits 801 and/or letters which indicates the subexpression to test, using the 802 same syntax as genextract/genrecog's location strings: 0-9 for 803 XEXP (op, n), a-z for XVECEXP (op, 0, n); each character applies to 804 the result of the one before it. */ 805DEF_RTL_EXPR(MATCH_CODE, "match_code", "ss", RTX_MATCH) 806 807/* Appears only in define_predicate/define_special_predicate 808 expressions. The argument is a C expression to be injected at this 809 point in the predicate formula. */ 810DEF_RTL_EXPR(MATCH_TEST, "match_test", "s", RTX_MATCH) 811 812/* Insn (and related) definitions. */ 813 814/* Definition of the pattern for one kind of instruction. 815 Operand: 816 0: names this instruction. 817 If the name is the null string, the instruction is in the 818 machine description just to be recognized, and will never be emitted by 819 the tree to rtl expander. 820 1: is the pattern. 821 2: is a string which is a C expression 822 giving an additional condition for recognizing this pattern. 823 A null string means no extra condition. 824 3: is the action to execute if this pattern is matched. 825 If this assembler code template starts with a * then it is a fragment of 826 C code to run to decide on a template to use. Otherwise, it is the 827 template to use. 828 4: optionally, a vector of attributes for this insn. 829 */ 830DEF_RTL_EXPR(DEFINE_INSN, "define_insn", "sEsTV", RTX_EXTRA) 831 832/* Definition of a peephole optimization. 833 1st operand: vector of insn patterns to match 834 2nd operand: C expression that must be true 835 3rd operand: template or C code to produce assembler output. 836 4: optionally, a vector of attributes for this insn. 837 838 This form is deprecated; use define_peephole2 instead. */ 839DEF_RTL_EXPR(DEFINE_PEEPHOLE, "define_peephole", "EsTV", RTX_EXTRA) 840 841/* Definition of a split operation. 842 1st operand: insn pattern to match 843 2nd operand: C expression that must be true 844 3rd operand: vector of insn patterns to place into a SEQUENCE 845 4th operand: optionally, some C code to execute before generating the 846 insns. This might, for example, create some RTX's and store them in 847 elements of `recog_data.operand' for use by the vector of 848 insn-patterns. 849 (`operands' is an alias here for `recog_data.operand'). */ 850DEF_RTL_EXPR(DEFINE_SPLIT, "define_split", "EsES", RTX_EXTRA) 851 852/* Definition of an insn and associated split. 853 This is the concatenation, with a few modifications, of a define_insn 854 and a define_split which share the same pattern. 855 Operand: 856 0: names this instruction. 857 If the name is the null string, the instruction is in the 858 machine description just to be recognized, and will never be emitted by 859 the tree to rtl expander. 860 1: is the pattern. 861 2: is a string which is a C expression 862 giving an additional condition for recognizing this pattern. 863 A null string means no extra condition. 864 3: is the action to execute if this pattern is matched. 865 If this assembler code template starts with a * then it is a fragment of 866 C code to run to decide on a template to use. Otherwise, it is the 867 template to use. 868 4: C expression that must be true for split. This may start with "&&" 869 in which case the split condition is the logical and of the insn 870 condition and what follows the "&&" of this operand. 871 5: vector of insn patterns to place into a SEQUENCE 872 6: optionally, some C code to execute before generating the 873 insns. This might, for example, create some RTX's and store them in 874 elements of `recog_data.operand' for use by the vector of 875 insn-patterns. 876 (`operands' is an alias here for `recog_data.operand'). 877 7: optionally, a vector of attributes for this insn. */ 878DEF_RTL_EXPR(DEFINE_INSN_AND_SPLIT, "define_insn_and_split", "sEsTsESV", RTX_EXTRA) 879 880/* Definition of an RTL peephole operation. 881 Follows the same arguments as define_split. */ 882DEF_RTL_EXPR(DEFINE_PEEPHOLE2, "define_peephole2", "EsES", RTX_EXTRA) 883 884/* Define how to generate multiple insns for a standard insn name. 885 1st operand: the insn name. 886 2nd operand: vector of insn-patterns. 887 Use match_operand to substitute an element of `recog_data.operand'. 888 3rd operand: C expression that must be true for this to be available. 889 This may not test any operands. 890 4th operand: Extra C code to execute before generating the insns. 891 This might, for example, create some RTX's and store them in 892 elements of `recog_data.operand' for use by the vector of 893 insn-patterns. 894 (`operands' is an alias here for `recog_data.operand'). */ 895DEF_RTL_EXPR(DEFINE_EXPAND, "define_expand", "sEss", RTX_EXTRA) 896 897/* Define a requirement for delay slots. 898 1st operand: Condition involving insn attributes that, if true, 899 indicates that the insn requires the number of delay slots 900 shown. 901 2nd operand: Vector whose length is the three times the number of delay 902 slots required. 903 Each entry gives three conditions, each involving attributes. 904 The first must be true for an insn to occupy that delay slot 905 location. The second is true for all insns that can be 906 annulled if the branch is true and the third is true for all 907 insns that can be annulled if the branch is false. 908 909 Multiple DEFINE_DELAYs may be present. They indicate differing 910 requirements for delay slots. */ 911DEF_RTL_EXPR(DEFINE_DELAY, "define_delay", "eE", RTX_EXTRA) 912 913/* Define attribute computation for `asm' instructions. */ 914DEF_RTL_EXPR(DEFINE_ASM_ATTRIBUTES, "define_asm_attributes", "V", RTX_EXTRA) 915 916/* Definition of a conditional execution meta operation. Automatically 917 generates new instances of DEFINE_INSN, selected by having attribute 918 "predicable" true. The new pattern will contain a COND_EXEC and the 919 predicate at top-level. 920 921 Operand: 922 0: The predicate pattern. The top-level form should match a 923 relational operator. Operands should have only one alternative. 924 1: A C expression giving an additional condition for recognizing 925 the generated pattern. 926 2: A template or C code to produce assembler output. */ 927DEF_RTL_EXPR(DEFINE_COND_EXEC, "define_cond_exec", "Ess", RTX_EXTRA) 928 929/* Definition of an operand predicate. The difference between 930 DEFINE_PREDICATE and DEFINE_SPECIAL_PREDICATE is that genrecog will 931 not warn about a match_operand with no mode if it has a predicate 932 defined with DEFINE_SPECIAL_PREDICATE. 933 934 Operand: 935 0: The name of the predicate. 936 1: A boolean expression which computes whether or not the predicate 937 matches. This expression can use IOR, AND, NOT, MATCH_OPERAND, 938 MATCH_CODE, and MATCH_TEST. It must be specific enough that genrecog 939 can calculate the set of RTX codes that can possibly match. 940 2: A C function body which must return true for the predicate to match. 941 Optional. Use this when the test is too complicated to fit into a 942 match_test expression. */ 943DEF_RTL_EXPR(DEFINE_PREDICATE, "define_predicate", "ses", RTX_EXTRA) 944DEF_RTL_EXPR(DEFINE_SPECIAL_PREDICATE, "define_special_predicate", "ses", RTX_EXTRA) 945 946/* Definition of a register operand constraint. This simply maps the 947 constraint string to a register class. 948 949 Operand: 950 0: The name of the constraint (often, but not always, a single letter). 951 1: A C expression which evaluates to the appropriate register class for 952 this constraint. If this is not just a constant, it should look only 953 at -m switches and the like. 954 2: A docstring for this constraint, in Texinfo syntax; not currently 955 used, in future will be incorporated into the manual's list of 956 machine-specific operand constraints. */ 957DEF_RTL_EXPR(DEFINE_REGISTER_CONSTRAINT, "define_register_constraint", "sss", RTX_EXTRA) 958 959/* Definition of a non-register operand constraint. These look at the 960 operand and decide whether it fits the constraint. 961 962 DEFINE_CONSTRAINT gets no special treatment if it fails to match. 963 It is appropriate for constant-only constraints, and most others. 964 965 DEFINE_MEMORY_CONSTRAINT tells reload that this constraint can be made 966 to match, if it doesn't already, by converting the operand to the form 967 (mem (reg X)) where X is a base register. It is suitable for constraints 968 that describe a subset of all memory references. 969 970 DEFINE_ADDRESS_CONSTRAINT tells reload that this constraint can be made 971 to match, if it doesn't already, by converting the operand to the form 972 (reg X) where X is a base register. It is suitable for constraints that 973 describe a subset of all address references. 974 975 When in doubt, use plain DEFINE_CONSTRAINT. 976 977 Operand: 978 0: The name of the constraint (often, but not always, a single letter). 979 1: A docstring for this constraint, in Texinfo syntax; not currently 980 used, in future will be incorporated into the manual's list of 981 machine-specific operand constraints. 982 2: A boolean expression which computes whether or not the constraint 983 matches. It should follow the same rules as a define_predicate 984 expression, including the bit about specifying the set of RTX codes 985 that could possibly match. MATCH_TEST subexpressions may make use of 986 these variables: 987 `op' - the RTL object defining the operand. 988 `mode' - the mode of `op'. 989 `ival' - INTVAL(op), if op is a CONST_INT. 990 `hval' - CONST_DOUBLE_HIGH(op), if op is an integer CONST_DOUBLE. 991 `lval' - CONST_DOUBLE_LOW(op), if op is an integer CONST_DOUBLE. 992 `rval' - CONST_DOUBLE_REAL_VALUE(op), if op is a floating-point 993 CONST_DOUBLE. 994 Do not use ival/hval/lval/rval if op is not the appropriate kind of 995 RTL object. */ 996DEF_RTL_EXPR(DEFINE_CONSTRAINT, "define_constraint", "sse", RTX_EXTRA) 997DEF_RTL_EXPR(DEFINE_MEMORY_CONSTRAINT, "define_memory_constraint", "sse", RTX_EXTRA) 998DEF_RTL_EXPR(DEFINE_ADDRESS_CONSTRAINT, "define_address_constraint", "sse", RTX_EXTRA) 999 1000 1001/* Constructions for CPU pipeline description described by NDFAs. */ 1002 1003/* (define_cpu_unit string [string]) describes cpu functional 1004 units (separated by comma). 1005 1006 1st operand: Names of cpu functional units. 1007 2nd operand: Name of automaton (see comments for DEFINE_AUTOMATON). 1008 1009 All define_reservations, define_cpu_units, and 1010 define_query_cpu_units should have unique names which may not be 1011 "nothing". */ 1012DEF_RTL_EXPR(DEFINE_CPU_UNIT, "define_cpu_unit", "sS", RTX_EXTRA) 1013 1014/* (define_query_cpu_unit string [string]) describes cpu functional 1015 units analogously to define_cpu_unit. The reservation of such 1016 units can be queried for automaton state. */ 1017DEF_RTL_EXPR(DEFINE_QUERY_CPU_UNIT, "define_query_cpu_unit", "sS", RTX_EXTRA) 1018 1019/* (exclusion_set string string) means that each CPU functional unit 1020 in the first string can not be reserved simultaneously with any 1021 unit whose name is in the second string and vise versa. CPU units 1022 in the string are separated by commas. For example, it is useful 1023 for description CPU with fully pipelined floating point functional 1024 unit which can execute simultaneously only single floating point 1025 insns or only double floating point insns. All CPU functional 1026 units in a set should belong to the same automaton. */ 1027DEF_RTL_EXPR(EXCLUSION_SET, "exclusion_set", "ss", RTX_EXTRA) 1028 1029/* (presence_set string string) means that each CPU functional unit in 1030 the first string can not be reserved unless at least one of pattern 1031 of units whose names are in the second string is reserved. This is 1032 an asymmetric relation. CPU units or unit patterns in the strings 1033 are separated by commas. Pattern is one unit name or unit names 1034 separated by white-spaces. 1035 1036 For example, it is useful for description that slot1 is reserved 1037 after slot0 reservation for a VLIW processor. We could describe it 1038 by the following construction 1039 1040 (presence_set "slot1" "slot0") 1041 1042 Or slot1 is reserved only after slot0 and unit b0 reservation. In 1043 this case we could write 1044 1045 (presence_set "slot1" "slot0 b0") 1046 1047 All CPU functional units in a set should belong to the same 1048 automaton. */ 1049DEF_RTL_EXPR(PRESENCE_SET, "presence_set", "ss", RTX_EXTRA) 1050 1051/* (final_presence_set string string) is analogous to `presence_set'. 1052 The difference between them is when checking is done. When an 1053 instruction is issued in given automaton state reflecting all 1054 current and planned unit reservations, the automaton state is 1055 changed. The first state is a source state, the second one is a 1056 result state. Checking for `presence_set' is done on the source 1057 state reservation, checking for `final_presence_set' is done on the 1058 result reservation. This construction is useful to describe a 1059 reservation which is actually two subsequent reservations. For 1060 example, if we use 1061 1062 (presence_set "slot1" "slot0") 1063 1064 the following insn will be never issued (because slot1 requires 1065 slot0 which is absent in the source state). 1066 1067 (define_reservation "insn_and_nop" "slot0 + slot1") 1068 1069 but it can be issued if we use analogous `final_presence_set'. */ 1070DEF_RTL_EXPR(FINAL_PRESENCE_SET, "final_presence_set", "ss", RTX_EXTRA) 1071 1072/* (absence_set string string) means that each CPU functional unit in 1073 the first string can be reserved only if each pattern of units 1074 whose names are in the second string is not reserved. This is an 1075 asymmetric relation (actually exclusion set is analogous to this 1076 one but it is symmetric). CPU units or unit patterns in the string 1077 are separated by commas. Pattern is one unit name or unit names 1078 separated by white-spaces. 1079 1080 For example, it is useful for description that slot0 can not be 1081 reserved after slot1 or slot2 reservation for a VLIW processor. We 1082 could describe it by the following construction 1083 1084 (absence_set "slot2" "slot0, slot1") 1085 1086 Or slot2 can not be reserved if slot0 and unit b0 are reserved or 1087 slot1 and unit b1 are reserved . In this case we could write 1088 1089 (absence_set "slot2" "slot0 b0, slot1 b1") 1090 1091 All CPU functional units in a set should to belong the same 1092 automaton. */ 1093DEF_RTL_EXPR(ABSENCE_SET, "absence_set", "ss", RTX_EXTRA) 1094 1095/* (final_absence_set string string) is analogous to `absence_set' but 1096 checking is done on the result (state) reservation. See comments 1097 for `final_presence_set'. */ 1098DEF_RTL_EXPR(FINAL_ABSENCE_SET, "final_absence_set", "ss", RTX_EXTRA) 1099 1100/* (define_bypass number out_insn_names in_insn_names) names bypass 1101 with given latency (the first number) from insns given by the first 1102 string (see define_insn_reservation) into insns given by the second 1103 string. Insn names in the strings are separated by commas. The 1104 third operand is optional name of function which is additional 1105 guard for the bypass. The function will get the two insns as 1106 parameters. If the function returns zero the bypass will be 1107 ignored for this case. Additional guard is necessary to recognize 1108 complicated bypasses, e.g. when consumer is load address. If there 1109 are more one bypass with the same output and input insns, the 1110 chosen bypass is the first bypass with a guard in description whose 1111 guard function returns nonzero. If there is no such bypass, then 1112 bypass without the guard function is chosen. */ 1113DEF_RTL_EXPR(DEFINE_BYPASS, "define_bypass", "issS", RTX_EXTRA) 1114 1115/* (define_automaton string) describes names of automata generated and 1116 used for pipeline hazards recognition. The names are separated by 1117 comma. Actually it is possibly to generate the single automaton 1118 but unfortunately it can be very large. If we use more one 1119 automata, the summary size of the automata usually is less than the 1120 single one. The automaton name is used in define_cpu_unit and 1121 define_query_cpu_unit. All automata should have unique names. */ 1122DEF_RTL_EXPR(DEFINE_AUTOMATON, "define_automaton", "s", RTX_EXTRA) 1123 1124/* (automata_option string) describes option for generation of 1125 automata. Currently there are the following options: 1126 1127 o "no-minimization" which makes no minimization of automata. This 1128 is only worth to do when we are debugging the description and 1129 need to look more accurately at reservations of states. 1130 1131 o "time" which means printing additional time statistics about 1132 generation of automata. 1133 1134 o "v" which means generation of file describing the result 1135 automata. The file has suffix `.dfa' and can be used for the 1136 description verification and debugging. 1137 1138 o "w" which means generation of warning instead of error for 1139 non-critical errors. 1140 1141 o "ndfa" which makes nondeterministic finite state automata. 1142 1143 o "progress" which means output of a progress bar showing how many 1144 states were generated so far for automaton being processed. */ 1145DEF_RTL_EXPR(AUTOMATA_OPTION, "automata_option", "s", RTX_EXTRA) 1146 1147/* (define_reservation string string) names reservation (the first 1148 string) of cpu functional units (the 2nd string). Sometimes unit 1149 reservations for different insns contain common parts. In such 1150 case, you can describe common part and use its name (the 1st 1151 parameter) in regular expression in define_insn_reservation. All 1152 define_reservations, define_cpu_units, and define_query_cpu_units 1153 should have unique names which may not be "nothing". */ 1154DEF_RTL_EXPR(DEFINE_RESERVATION, "define_reservation", "ss", RTX_EXTRA) 1155 1156/* (define_insn_reservation name default_latency condition regexpr) 1157 describes reservation of cpu functional units (the 3nd operand) for 1158 instruction which is selected by the condition (the 2nd parameter). 1159 The first parameter is used for output of debugging information. 1160 The reservations are described by a regular expression according 1161 the following syntax: 1162 1163 regexp = regexp "," oneof 1164 | oneof 1165 1166 oneof = oneof "|" allof 1167 | allof 1168 1169 allof = allof "+" repeat 1170 | repeat 1171 1172 repeat = element "*" number 1173 | element 1174 1175 element = cpu_function_unit_name 1176 | reservation_name 1177 | result_name 1178 | "nothing" 1179 | "(" regexp ")" 1180 1181 1. "," is used for describing start of the next cycle in 1182 reservation. 1183 1184 2. "|" is used for describing the reservation described by the 1185 first regular expression *or* the reservation described by the 1186 second regular expression *or* etc. 1187 1188 3. "+" is used for describing the reservation described by the 1189 first regular expression *and* the reservation described by the 1190 second regular expression *and* etc. 1191 1192 4. "*" is used for convenience and simply means sequence in 1193 which the regular expression are repeated NUMBER times with 1194 cycle advancing (see ","). 1195 1196 5. cpu functional unit name which means its reservation. 1197 1198 6. reservation name -- see define_reservation. 1199 1200 7. string "nothing" means no units reservation. */ 1201 1202DEF_RTL_EXPR(DEFINE_INSN_RESERVATION, "define_insn_reservation", "sies", RTX_EXTRA) 1203 1204/* Expressions used for insn attributes. */ 1205 1206/* Definition of an insn attribute. 1207 1st operand: name of the attribute 1208 2nd operand: comma-separated list of possible attribute values 1209 3rd operand: expression for the default value of the attribute. */ 1210DEF_RTL_EXPR(DEFINE_ATTR, "define_attr", "sse", RTX_EXTRA) 1211 1212/* Definition of an insn attribute that uses an existing enumerated type. 1213 1st operand: name of the attribute 1214 2nd operand: the name of the enumerated type 1215 3rd operand: expression for the default value of the attribute. */ 1216DEF_RTL_EXPR(DEFINE_ENUM_ATTR, "define_enum_attr", "sse", RTX_EXTRA) 1217 1218/* Marker for the name of an attribute. */ 1219DEF_RTL_EXPR(ATTR, "attr", "s", RTX_EXTRA) 1220 1221/* For use in the last (optional) operand of DEFINE_INSN or DEFINE_PEEPHOLE and 1222 in DEFINE_ASM_INSN to specify an attribute to assign to insns matching that 1223 pattern. 1224 1225 (set_attr "name" "value") is equivalent to 1226 (set (attr "name") (const_string "value")) */ 1227DEF_RTL_EXPR(SET_ATTR, "set_attr", "ss", RTX_EXTRA) 1228 1229/* In the last operand of DEFINE_INSN and DEFINE_PEEPHOLE, this can be used to 1230 specify that attribute values are to be assigned according to the 1231 alternative matched. 1232 1233 The following three expressions are equivalent: 1234 1235 (set (attr "att") (cond [(eq_attrq "alternative" "1") (const_string "a1") 1236 (eq_attrq "alternative" "2") (const_string "a2")] 1237 (const_string "a3"))) 1238 (set_attr_alternative "att" [(const_string "a1") (const_string "a2") 1239 (const_string "a3")]) 1240 (set_attr "att" "a1,a2,a3") 1241 */ 1242DEF_RTL_EXPR(SET_ATTR_ALTERNATIVE, "set_attr_alternative", "sE", RTX_EXTRA) 1243 1244/* A conditional expression true if the value of the specified attribute of 1245 the current insn equals the specified value. The first operand is the 1246 attribute name and the second is the comparison value. */ 1247DEF_RTL_EXPR(EQ_ATTR, "eq_attr", "ss", RTX_EXTRA) 1248 1249/* A special case of the above representing a set of alternatives. The first 1250 operand is bitmap of the set, the second one is the default value. */ 1251DEF_RTL_EXPR(EQ_ATTR_ALT, "eq_attr_alt", "ii", RTX_EXTRA) 1252 1253/* A conditional expression which is true if the specified flag is 1254 true for the insn being scheduled in reorg. 1255 1256 genattr.c defines the following flags which can be tested by 1257 (attr_flag "foo") expressions in eligible_for_delay. 1258 1259 forward, backward, very_likely, likely, very_unlikely, and unlikely. */ 1260 1261DEF_RTL_EXPR (ATTR_FLAG, "attr_flag", "s", RTX_EXTRA) 1262 1263/* General conditional. The first operand is a vector composed of pairs of 1264 expressions. The first element of each pair is evaluated, in turn. 1265 The value of the conditional is the second expression of the first pair 1266 whose first expression evaluates nonzero. If none of the expressions is 1267 true, the second operand will be used as the value of the conditional. */ 1268DEF_RTL_EXPR(COND, "cond", "Ee", RTX_EXTRA) 1269 1270#endif /* GENERATOR_FILE */ 1271 1272/* 1273Local variables: 1274mode:c 1275End: 1276*/ 1277