1#ifndef __SOUND_EMU10K1_H 2#define __SOUND_EMU10K1_H 3 4#include <linux/types.h> 5 6/* 7 * Copyright (c) by Jaroslav Kysela <perex@perex.cz>, 8 * Creative Labs, Inc. 9 * Definitions for EMU10K1 (SB Live!) chips 10 * 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 */ 27 28 29/* 30 * ---- FX8010 ---- 31 */ 32 33#define EMU10K1_CARD_CREATIVE 0x00000000 34#define EMU10K1_CARD_EMUAPS 0x00000001 35 36#define EMU10K1_FX8010_PCM_COUNT 8 37 38/* instruction set */ 39#define iMAC0 0x00 /* R = A + (X * Y >> 31) ; saturation */ 40#define iMAC1 0x01 /* R = A + (-X * Y >> 31) ; saturation */ 41#define iMAC2 0x02 /* R = A + (X * Y >> 31) ; wraparound */ 42#define iMAC3 0x03 /* R = A + (-X * Y >> 31) ; wraparound */ 43#define iMACINT0 0x04 /* R = A + X * Y ; saturation */ 44#define iMACINT1 0x05 /* R = A + X * Y ; wraparound (31-bit) */ 45#define iACC3 0x06 /* R = A + X + Y ; saturation */ 46#define iMACMV 0x07 /* R = A, acc += X * Y >> 31 */ 47#define iANDXOR 0x08 /* R = (A & X) ^ Y */ 48#define iTSTNEG 0x09 /* R = (A >= Y) ? X : ~X */ 49#define iLIMITGE 0x0a /* R = (A >= Y) ? X : Y */ 50#define iLIMITLT 0x0b /* R = (A < Y) ? X : Y */ 51#define iLOG 0x0c /* R = linear_data, A (log_data), X (max_exp), Y (format_word) */ 52#define iEXP 0x0d /* R = log_data, A (linear_data), X (max_exp), Y (format_word) */ 53#define iINTERP 0x0e /* R = A + (X * (Y - A) >> 31) ; saturation */ 54#define iSKIP 0x0f /* R = A (cc_reg), X (count), Y (cc_test) */ 55 56/* GPRs */ 57#define FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x0f */ 58#define EXTIN(x) (0x10 + (x)) /* x = 0x00 - 0x0f */ 59#define EXTOUT(x) (0x20 + (x)) /* x = 0x00 - 0x0f physical outs -> FXWC low 16 bits */ 60#define FXBUS2(x) (0x30 + (x)) /* x = 0x00 - 0x0f copies of fx buses for capture -> FXWC high 16 bits */ 61 /* NB: 0x31 and 0x32 are shared with Center/LFE on SB live 5.1 */ 62 63#define C_00000000 0x40 64#define C_00000001 0x41 65#define C_00000002 0x42 66#define C_00000003 0x43 67#define C_00000004 0x44 68#define C_00000008 0x45 69#define C_00000010 0x46 70#define C_00000020 0x47 71#define C_00000100 0x48 72#define C_00010000 0x49 73#define C_00080000 0x4a 74#define C_10000000 0x4b 75#define C_20000000 0x4c 76#define C_40000000 0x4d 77#define C_80000000 0x4e 78#define C_7fffffff 0x4f 79#define C_ffffffff 0x50 80#define C_fffffffe 0x51 81#define C_c0000000 0x52 82#define C_4f1bbcdc 0x53 83#define C_5a7ef9db 0x54 84#define C_00100000 0x55 /* ?? */ 85#define GPR_ACCU 0x56 /* ACCUM, accumulator */ 86#define GPR_COND 0x57 /* CCR, condition register */ 87#define GPR_NOISE0 0x58 /* noise source */ 88#define GPR_NOISE1 0x59 /* noise source */ 89#define GPR_IRQ 0x5a /* IRQ register */ 90#define GPR_DBAC 0x5b /* TRAM Delay Base Address Counter */ 91#define GPR(x) (FXGPREGBASE + (x)) /* free GPRs: x = 0x00 - 0xff */ 92#define ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ 93#define ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ 94#define ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0x7f */ 95#define ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x80 + (x)) /* x = 0x00 - 0x1f */ 96 97#define A_ITRAM_DATA(x) (TANKMEMDATAREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 98#define A_ETRAM_DATA(x) (TANKMEMDATAREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 99#define A_ITRAM_ADDR(x) (TANKMEMADDRREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 100#define A_ETRAM_ADDR(x) (TANKMEMADDRREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 101#define A_ITRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0x00 + (x)) /* x = 0x00 - 0xbf */ 102#define A_ETRAM_CTL(x) (A_TANKMEMCTLREGBASE + 0xc0 + (x)) /* x = 0x00 - 0x3f */ 103 104#define A_FXBUS(x) (0x00 + (x)) /* x = 0x00 - 0x3f FX buses */ 105#define A_EXTIN(x) (0x40 + (x)) /* x = 0x00 - 0x0f physical ins */ 106#define A_P16VIN(x) (0x50 + (x)) /* x = 0x00 - 0x0f p16v ins (A2 only) "EMU32 inputs" */ 107#define A_EXTOUT(x) (0x60 + (x)) /* x = 0x00 - 0x1f physical outs -> A_FXWC1 0x79-7f unknown */ 108#define A_FXBUS2(x) (0x80 + (x)) /* x = 0x00 - 0x1f extra outs used for EFX capture -> A_FXWC2 */ 109#define A_EMU32OUTH(x) (0xa0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_10 - _1F" - ??? */ 110#define A_EMU32OUTL(x) (0xb0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_1 - _F" - ??? */ 111#define A3_EMU32IN(x) (0x160 + (x)) /* x = 0x00 - 0x3f "EMU32_IN_00 - _3F" - Only when .device = 0x0008 */ 112#define A3_EMU32OUT(x) (0x1E0 + (x)) /* x = 0x00 - 0x0f "EMU32_OUT_00 - _3F" - Only when .device = 0x0008 */ 113#define A_GPR(x) (A_FXGPREGBASE + (x)) 114 115/* cc_reg constants */ 116#define CC_REG_NORMALIZED C_00000001 117#define CC_REG_BORROW C_00000002 118#define CC_REG_MINUS C_00000004 119#define CC_REG_ZERO C_00000008 120#define CC_REG_SATURATE C_00000010 121#define CC_REG_NONZERO C_00000100 122 123/* FX buses */ 124#define FXBUS_PCM_LEFT 0x00 125#define FXBUS_PCM_RIGHT 0x01 126#define FXBUS_PCM_LEFT_REAR 0x02 127#define FXBUS_PCM_RIGHT_REAR 0x03 128#define FXBUS_MIDI_LEFT 0x04 129#define FXBUS_MIDI_RIGHT 0x05 130#define FXBUS_PCM_CENTER 0x06 131#define FXBUS_PCM_LFE 0x07 132#define FXBUS_PCM_LEFT_FRONT 0x08 133#define FXBUS_PCM_RIGHT_FRONT 0x09 134#define FXBUS_MIDI_REVERB 0x0c 135#define FXBUS_MIDI_CHORUS 0x0d 136#define FXBUS_PCM_LEFT_SIDE 0x0e 137#define FXBUS_PCM_RIGHT_SIDE 0x0f 138#define FXBUS_PT_LEFT 0x14 139#define FXBUS_PT_RIGHT 0x15 140 141/* Inputs */ 142#define EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ 143#define EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ 144#define EXTIN_SPDIF_CD_L 0x02 /* internal S/PDIF CD - onboard - left */ 145#define EXTIN_SPDIF_CD_R 0x03 /* internal S/PDIF CD - onboard - right */ 146#define EXTIN_ZOOM_L 0x04 /* Zoom Video I2S - left */ 147#define EXTIN_ZOOM_R 0x05 /* Zoom Video I2S - right */ 148#define EXTIN_TOSLINK_L 0x06 /* LiveDrive - TOSLink Optical - left */ 149#define EXTIN_TOSLINK_R 0x07 /* LiveDrive - TOSLink Optical - right */ 150#define EXTIN_LINE1_L 0x08 /* LiveDrive - Line/Mic 1 - left */ 151#define EXTIN_LINE1_R 0x09 /* LiveDrive - Line/Mic 1 - right */ 152#define EXTIN_COAX_SPDIF_L 0x0a /* LiveDrive - Coaxial S/PDIF - left */ 153#define EXTIN_COAX_SPDIF_R 0x0b /* LiveDrive - Coaxial S/PDIF - right */ 154#define EXTIN_LINE2_L 0x0c /* LiveDrive - Line/Mic 2 - left */ 155#define EXTIN_LINE2_R 0x0d /* LiveDrive - Line/Mic 2 - right */ 156 157/* Outputs */ 158#define EXTOUT_AC97_L 0x00 /* AC'97 playback channel - left */ 159#define EXTOUT_AC97_R 0x01 /* AC'97 playback channel - right */ 160#define EXTOUT_TOSLINK_L 0x02 /* LiveDrive - TOSLink Optical - left */ 161#define EXTOUT_TOSLINK_R 0x03 /* LiveDrive - TOSLink Optical - right */ 162#define EXTOUT_AC97_CENTER 0x04 /* SB Live 5.1 - center */ 163#define EXTOUT_AC97_LFE 0x05 /* SB Live 5.1 - LFE */ 164#define EXTOUT_HEADPHONE_L 0x06 /* LiveDrive - Headphone - left */ 165#define EXTOUT_HEADPHONE_R 0x07 /* LiveDrive - Headphone - right */ 166#define EXTOUT_REAR_L 0x08 /* Rear channel - left */ 167#define EXTOUT_REAR_R 0x09 /* Rear channel - right */ 168#define EXTOUT_ADC_CAP_L 0x0a /* ADC Capture buffer - left */ 169#define EXTOUT_ADC_CAP_R 0x0b /* ADC Capture buffer - right */ 170#define EXTOUT_MIC_CAP 0x0c /* MIC Capture buffer */ 171#define EXTOUT_AC97_REAR_L 0x0d /* SB Live 5.1 (c) 2003 - Rear Left */ 172#define EXTOUT_AC97_REAR_R 0x0e /* SB Live 5.1 (c) 2003 - Rear Right */ 173#define EXTOUT_ACENTER 0x11 /* Analog Center */ 174#define EXTOUT_ALFE 0x12 /* Analog LFE */ 175 176/* Audigy Inputs */ 177#define A_EXTIN_AC97_L 0x00 /* AC'97 capture channel - left */ 178#define A_EXTIN_AC97_R 0x01 /* AC'97 capture channel - right */ 179#define A_EXTIN_SPDIF_CD_L 0x02 /* digital CD left */ 180#define A_EXTIN_SPDIF_CD_R 0x03 /* digital CD left */ 181#define A_EXTIN_OPT_SPDIF_L 0x04 /* audigy drive Optical SPDIF - left */ 182#define A_EXTIN_OPT_SPDIF_R 0x05 /* right */ 183#define A_EXTIN_LINE2_L 0x08 /* audigy drive line2/mic2 - left */ 184#define A_EXTIN_LINE2_R 0x09 /* right */ 185#define A_EXTIN_ADC_L 0x0a /* Philips ADC - left */ 186#define A_EXTIN_ADC_R 0x0b /* right */ 187#define A_EXTIN_AUX2_L 0x0c /* audigy drive aux2 - left */ 188#define A_EXTIN_AUX2_R 0x0d /* - right */ 189 190/* Audigiy Outputs */ 191#define A_EXTOUT_FRONT_L 0x00 /* digital front left */ 192#define A_EXTOUT_FRONT_R 0x01 /* right */ 193#define A_EXTOUT_CENTER 0x02 /* digital front center */ 194#define A_EXTOUT_LFE 0x03 /* digital front lfe */ 195#define A_EXTOUT_HEADPHONE_L 0x04 /* headphone audigy drive left */ 196#define A_EXTOUT_HEADPHONE_R 0x05 /* right */ 197#define A_EXTOUT_REAR_L 0x06 /* digital rear left */ 198#define A_EXTOUT_REAR_R 0x07 /* right */ 199#define A_EXTOUT_AFRONT_L 0x08 /* analog front left */ 200#define A_EXTOUT_AFRONT_R 0x09 /* right */ 201#define A_EXTOUT_ACENTER 0x0a /* analog center */ 202#define A_EXTOUT_ALFE 0x0b /* analog LFE */ 203#define A_EXTOUT_ASIDE_L 0x0c /* analog side left - Audigy 2 ZS */ 204#define A_EXTOUT_ASIDE_R 0x0d /* right - Audigy 2 ZS */ 205#define A_EXTOUT_AREAR_L 0x0e /* analog rear left */ 206#define A_EXTOUT_AREAR_R 0x0f /* right */ 207#define A_EXTOUT_AC97_L 0x10 /* AC97 left (front) */ 208#define A_EXTOUT_AC97_R 0x11 /* right */ 209#define A_EXTOUT_ADC_CAP_L 0x16 /* ADC capture buffer left */ 210#define A_EXTOUT_ADC_CAP_R 0x17 /* right */ 211#define A_EXTOUT_MIC_CAP 0x18 /* Mic capture buffer */ 212 213/* Audigy constants */ 214#define A_C_00000000 0xc0 215#define A_C_00000001 0xc1 216#define A_C_00000002 0xc2 217#define A_C_00000003 0xc3 218#define A_C_00000004 0xc4 219#define A_C_00000008 0xc5 220#define A_C_00000010 0xc6 221#define A_C_00000020 0xc7 222#define A_C_00000100 0xc8 223#define A_C_00010000 0xc9 224#define A_C_00000800 0xca 225#define A_C_10000000 0xcb 226#define A_C_20000000 0xcc 227#define A_C_40000000 0xcd 228#define A_C_80000000 0xce 229#define A_C_7fffffff 0xcf 230#define A_C_ffffffff 0xd0 231#define A_C_fffffffe 0xd1 232#define A_C_c0000000 0xd2 233#define A_C_4f1bbcdc 0xd3 234#define A_C_5a7ef9db 0xd4 235#define A_C_00100000 0xd5 236#define A_GPR_ACCU 0xd6 /* ACCUM, accumulator */ 237#define A_GPR_COND 0xd7 /* CCR, condition register */ 238#define A_GPR_NOISE0 0xd8 /* noise source */ 239#define A_GPR_NOISE1 0xd9 /* noise source */ 240#define A_GPR_IRQ 0xda /* IRQ register */ 241#define A_GPR_DBAC 0xdb /* TRAM Delay Base Address Counter - internal */ 242#define A_GPR_DBACE 0xde /* TRAM Delay Base Address Counter - external */ 243 244/* definitions for debug register */ 245#define EMU10K1_DBG_ZC 0x80000000 /* zero tram counter */ 246#define EMU10K1_DBG_SATURATION_OCCURED 0x02000000 /* saturation control */ 247#define EMU10K1_DBG_SATURATION_ADDR 0x01ff0000 /* saturation address */ 248#define EMU10K1_DBG_SINGLE_STEP 0x00008000 /* single step mode */ 249#define EMU10K1_DBG_STEP 0x00004000 /* start single step */ 250#define EMU10K1_DBG_CONDITION_CODE 0x00003e00 /* condition code */ 251#define EMU10K1_DBG_SINGLE_STEP_ADDR 0x000001ff /* single step address */ 252 253/* tank memory address line */ 254#define TANKMEMADDRREG_ADDR_MASK 0x000fffff /* 20 bit tank address field */ 255#define TANKMEMADDRREG_CLEAR 0x00800000 /* Clear tank memory */ 256#define TANKMEMADDRREG_ALIGN 0x00400000 /* Align read or write relative to tank access */ 257#define TANKMEMADDRREG_WRITE 0x00200000 /* Write to tank memory */ 258#define TANKMEMADDRREG_READ 0x00100000 /* Read from tank memory */ 259 260struct snd_emu10k1_fx8010_info { 261 unsigned int internal_tram_size; /* in samples */ 262 unsigned int external_tram_size; /* in samples */ 263 char fxbus_names[16][32]; /* names of FXBUSes */ 264 char extin_names[16][32]; /* names of external inputs */ 265 char extout_names[32][32]; /* names of external outputs */ 266 unsigned int gpr_controls; /* count of GPR controls */ 267}; 268 269#define EMU10K1_GPR_TRANSLATION_NONE 0 270#define EMU10K1_GPR_TRANSLATION_TABLE100 1 271#define EMU10K1_GPR_TRANSLATION_BASS 2 272#define EMU10K1_GPR_TRANSLATION_TREBLE 3 273#define EMU10K1_GPR_TRANSLATION_ONOFF 4 274 275struct snd_emu10k1_fx8010_control_gpr { 276 struct snd_ctl_elem_id id; /* full control ID definition */ 277 unsigned int vcount; /* visible count */ 278 unsigned int count; /* count of GPR (1..16) */ 279 unsigned short gpr[32]; /* GPR number(s) */ 280 unsigned int value[32]; /* initial values */ 281 unsigned int min; /* minimum range */ 282 unsigned int max; /* maximum range */ 283 unsigned int translation; /* translation type (EMU10K1_GPR_TRANSLATION*) */ 284 const unsigned int *tlv; 285}; 286 287/* old ABI without TLV support */ 288struct snd_emu10k1_fx8010_control_old_gpr { 289 struct snd_ctl_elem_id id; 290 unsigned int vcount; 291 unsigned int count; 292 unsigned short gpr[32]; 293 unsigned int value[32]; 294 unsigned int min; 295 unsigned int max; 296 unsigned int translation; 297}; 298 299struct snd_emu10k1_fx8010_code { 300 char name[128]; 301 302 DECLARE_BITMAP(gpr_valid, 0x200); /* bitmask of valid initializers */ 303 __u32 *gpr_map; /* initializers */ 304 305 unsigned int gpr_add_control_count; /* count of GPR controls to add/replace */ 306 struct snd_emu10k1_fx8010_control_gpr *gpr_add_controls; /* GPR controls to add/replace */ 307 308 unsigned int gpr_del_control_count; /* count of GPR controls to remove */ 309 struct snd_ctl_elem_id *gpr_del_controls; /* IDs of GPR controls to remove */ 310 311 unsigned int gpr_list_control_count; /* count of GPR controls to list */ 312 unsigned int gpr_list_control_total; /* total count of GPR controls */ 313 struct snd_emu10k1_fx8010_control_gpr *gpr_list_controls; /* listed GPR controls */ 314 315 DECLARE_BITMAP(tram_valid, 0x100); /* bitmask of valid initializers */ 316 __u32 *tram_data_map; /* data initializers */ 317 __u32 *tram_addr_map; /* map initializers */ 318 319 DECLARE_BITMAP(code_valid, 1024); /* bitmask of valid instructions */ 320 __u32 *code; /* one instruction - 64 bits */ 321}; 322 323struct snd_emu10k1_fx8010_tram { 324 unsigned int address; /* 31.bit == 1 -> external TRAM */ 325 unsigned int size; /* size in samples (4 bytes) */ 326 unsigned int *samples; /* pointer to samples (20-bit) */ 327 /* NULL->clear memory */ 328}; 329 330struct snd_emu10k1_fx8010_pcm_rec { 331 unsigned int substream; /* substream number */ 332 unsigned int res1; /* reserved */ 333 unsigned int channels; /* 16-bit channels count, zero = remove this substream */ 334 unsigned int tram_start; /* ring buffer position in TRAM (in samples) */ 335 unsigned int buffer_size; /* count of buffered samples */ 336 unsigned short gpr_size; /* GPR containing size of ringbuffer in samples (host) */ 337 unsigned short gpr_ptr; /* GPR containing current pointer in the ring buffer (host = reset, FX8010) */ 338 unsigned short gpr_count; /* GPR containing count of samples between two interrupts (host) */ 339 unsigned short gpr_tmpcount; /* GPR containing current count of samples to interrupt (host = set, FX8010) */ 340 unsigned short gpr_trigger; /* GPR containing trigger (activate) information (host) */ 341 unsigned short gpr_running; /* GPR containing info if PCM is running (FX8010) */ 342 unsigned char pad; /* reserved */ 343 unsigned char etram[32]; /* external TRAM address & data (one per channel) */ 344 unsigned int res2; /* reserved */ 345}; 346 347#define SNDRV_EMU10K1_VERSION SNDRV_PROTOCOL_VERSION(1, 0, 1) 348 349#define SNDRV_EMU10K1_IOCTL_INFO _IOR ('H', 0x10, struct snd_emu10k1_fx8010_info) 350#define SNDRV_EMU10K1_IOCTL_CODE_POKE _IOW ('H', 0x11, struct snd_emu10k1_fx8010_code) 351#define SNDRV_EMU10K1_IOCTL_CODE_PEEK _IOWR('H', 0x12, struct snd_emu10k1_fx8010_code) 352#define SNDRV_EMU10K1_IOCTL_TRAM_SETUP _IOW ('H', 0x20, int) 353#define SNDRV_EMU10K1_IOCTL_TRAM_POKE _IOW ('H', 0x21, struct snd_emu10k1_fx8010_tram) 354#define SNDRV_EMU10K1_IOCTL_TRAM_PEEK _IOWR('H', 0x22, struct snd_emu10k1_fx8010_tram) 355#define SNDRV_EMU10K1_IOCTL_PCM_POKE _IOW ('H', 0x30, struct snd_emu10k1_fx8010_pcm_rec) 356#define SNDRV_EMU10K1_IOCTL_PCM_PEEK _IOWR('H', 0x31, struct snd_emu10k1_fx8010_pcm_rec) 357#define SNDRV_EMU10K1_IOCTL_PVERSION _IOR ('H', 0x40, int) 358#define SNDRV_EMU10K1_IOCTL_STOP _IO ('H', 0x80) 359#define SNDRV_EMU10K1_IOCTL_CONTINUE _IO ('H', 0x81) 360#define SNDRV_EMU10K1_IOCTL_ZERO_TRAM_COUNTER _IO ('H', 0x82) 361#define SNDRV_EMU10K1_IOCTL_SINGLE_STEP _IOW ('H', 0x83, int) 362#define SNDRV_EMU10K1_IOCTL_DBG_READ _IOR ('H', 0x84, int) 363 364/* typedefs for compatibility to user-space */ 365typedef struct snd_emu10k1_fx8010_info emu10k1_fx8010_info_t; 366typedef struct snd_emu10k1_fx8010_control_gpr emu10k1_fx8010_control_gpr_t; 367typedef struct snd_emu10k1_fx8010_code emu10k1_fx8010_code_t; 368typedef struct snd_emu10k1_fx8010_tram emu10k1_fx8010_tram_t; 369typedef struct snd_emu10k1_fx8010_pcm_rec emu10k1_fx8010_pcm_t; 370 371#endif /* __SOUND_EMU10K1_H */ 372