1/* Definitions of target machine for GNU compiler, for ARM. 2 Copyright (C) 1991, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 3 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009 4 Free Software Foundation, Inc. 5 Contributed by Pieter `Tiggr' Schoenmakers (rcpieter@win.tue.nl) 6 and Martin Simmons (@harleqn.co.uk). 7 More major hacks by Richard Earnshaw (rearnsha@arm.com) 8 Minor hacks by Nick Clifton (nickc@cygnus.com) 9 10 This file is part of GCC. 11 12 GCC is free software; you can redistribute it and/or modify it 13 under the terms of the GNU General Public License as published 14 by the Free Software Foundation; either version 3, or (at your 15 option) any later version. 16 17 GCC is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 20 License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with GCC; see the file COPYING3. If not see 24 <http://www.gnu.org/licenses/>. */ 25 26#ifndef GCC_ARM_H 27#define GCC_ARM_H 28 29/* We can't use enum machine_mode inside a generator file because it 30 hasn't been created yet; we shouldn't be using any code that 31 needs the real definition though, so this ought to be safe. */ 32#ifdef GENERATOR_FILE 33#define MACHMODE int 34#else 35#include "insn-modes.h" 36#define MACHMODE enum machine_mode 37#endif 38 39#include "config/vxworks-dummy.h" 40 41/* The architecture define. */ 42extern char arm_arch_name[]; 43 44/* Target CPU builtins. */ 45#define TARGET_CPU_CPP_BUILTINS() \ 46 do \ 47 { \ 48 /* Define __arm__ even when in thumb mode, for \ 49 consistency with armcc. */ \ 50 builtin_define ("__arm__"); \ 51 builtin_define ("__APCS_32__"); \ 52 if (TARGET_THUMB) \ 53 builtin_define ("__thumb__"); \ 54 if (TARGET_THUMB2) \ 55 builtin_define ("__thumb2__"); \ 56 \ 57 if (TARGET_BIG_END) \ 58 { \ 59 builtin_define ("__ARMEB__"); \ 60 if (TARGET_THUMB) \ 61 builtin_define ("__THUMBEB__"); \ 62 if (TARGET_LITTLE_WORDS) \ 63 builtin_define ("__ARMWEL__"); \ 64 } \ 65 else \ 66 { \ 67 builtin_define ("__ARMEL__"); \ 68 if (TARGET_THUMB) \ 69 builtin_define ("__THUMBEL__"); \ 70 } \ 71 \ 72 if (TARGET_SOFT_FLOAT) \ 73 builtin_define ("__SOFTFP__"); \ 74 \ 75 if (TARGET_VFP) \ 76 builtin_define ("__VFP_FP__"); \ 77 \ 78 if (TARGET_NEON) \ 79 builtin_define ("__ARM_NEON__"); \ 80 \ 81 /* Add a define for interworking. \ 82 Needed when building libgcc.a. */ \ 83 if (arm_cpp_interwork) \ 84 builtin_define ("__THUMB_INTERWORK__"); \ 85 \ 86 builtin_assert ("cpu=arm"); \ 87 builtin_assert ("machine=arm"); \ 88 \ 89 builtin_define (arm_arch_name); \ 90 if (arm_arch_cirrus) \ 91 builtin_define ("__MAVERICK__"); \ 92 if (arm_arch_xscale) \ 93 builtin_define ("__XSCALE__"); \ 94 if (arm_arch_iwmmxt) \ 95 builtin_define ("__IWMMXT__"); \ 96 if (TARGET_AAPCS_BASED) \ 97 builtin_define ("__ARM_EABI__"); \ 98 } while (0) 99 100/* The various ARM cores. */ 101enum processor_type 102{ 103#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ 104 IDENT, 105#include "arm-cores.def" 106#undef ARM_CORE 107 /* Used to indicate that no processor has been specified. */ 108 arm_none 109}; 110 111enum target_cpus 112{ 113#define ARM_CORE(NAME, IDENT, ARCH, FLAGS, COSTS) \ 114 TARGET_CPU_##IDENT, 115#include "arm-cores.def" 116#undef ARM_CORE 117 TARGET_CPU_generic 118}; 119 120/* The processor for which instructions should be scheduled. */ 121extern enum processor_type arm_tune; 122 123typedef enum arm_cond_code 124{ 125 ARM_EQ = 0, ARM_NE, ARM_CS, ARM_CC, ARM_MI, ARM_PL, ARM_VS, ARM_VC, 126 ARM_HI, ARM_LS, ARM_GE, ARM_LT, ARM_GT, ARM_LE, ARM_AL, ARM_NV 127} 128arm_cc; 129 130extern arm_cc arm_current_cc; 131 132#define ARM_INVERSE_CONDITION_CODE(X) ((arm_cc) (((int)X) ^ 1)) 133 134extern int arm_target_label; 135extern int arm_ccfsm_state; 136extern GTY(()) rtx arm_target_insn; 137/* The label of the current constant pool. */ 138extern rtx pool_vector_label; 139/* Set to 1 when a return insn is output, this means that the epilogue 140 is not needed. */ 141extern int return_used_this_function; 142/* Callback to output language specific object attributes. */ 143extern void (*arm_lang_output_object_attributes_hook)(void); 144 145/* Just in case configure has failed to define anything. */ 146#ifndef TARGET_CPU_DEFAULT 147#define TARGET_CPU_DEFAULT TARGET_CPU_generic 148#endif 149 150 151#undef CPP_SPEC 152#define CPP_SPEC "%(subtarget_cpp_spec) \ 153%{msoft-float:%{mhard-float: \ 154 %e-msoft-float and -mhard_float may not be used together}} \ 155%{mbig-endian:%{mlittle-endian: \ 156 %e-mbig-endian and -mlittle-endian may not be used together}}" 157 158#ifndef CC1_SPEC 159#define CC1_SPEC "" 160#endif 161 162/* This macro defines names of additional specifications to put in the specs 163 that can be used in various specifications like CC1_SPEC. Its definition 164 is an initializer with a subgrouping for each command option. 165 166 Each subgrouping contains a string constant, that defines the 167 specification name, and a string constant that used by the GCC driver 168 program. 169 170 Do not define this macro if it does not need to do anything. */ 171#define EXTRA_SPECS \ 172 { "subtarget_cpp_spec", SUBTARGET_CPP_SPEC }, \ 173 SUBTARGET_EXTRA_SPECS 174 175#ifndef SUBTARGET_EXTRA_SPECS 176#define SUBTARGET_EXTRA_SPECS 177#endif 178 179#ifndef SUBTARGET_CPP_SPEC 180#define SUBTARGET_CPP_SPEC "" 181#endif 182 183/* Run-time Target Specification. */ 184#ifndef TARGET_VERSION 185#define TARGET_VERSION fputs (" (ARM/generic)", stderr); 186#endif 187 188#define TARGET_SOFT_FLOAT (arm_float_abi == ARM_FLOAT_ABI_SOFT) 189/* Use hardware floating point instructions. */ 190#define TARGET_HARD_FLOAT (arm_float_abi != ARM_FLOAT_ABI_SOFT) 191/* Use hardware floating point calling convention. */ 192#define TARGET_HARD_FLOAT_ABI (arm_float_abi == ARM_FLOAT_ABI_HARD) 193#define TARGET_FPA (arm_fpu_desc->model == ARM_FP_MODEL_FPA) 194#define TARGET_MAVERICK (arm_fpu_desc->model == ARM_FP_MODEL_MAVERICK) 195#define TARGET_VFP (arm_fpu_desc->model == ARM_FP_MODEL_VFP) 196#define TARGET_IWMMXT (arm_arch_iwmmxt) 197#define TARGET_REALLY_IWMMXT (TARGET_IWMMXT && TARGET_32BIT) 198#define TARGET_IWMMXT_ABI (TARGET_32BIT && arm_abi == ARM_ABI_IWMMXT) 199#define TARGET_ARM (! TARGET_THUMB) 200#define TARGET_EITHER 1 /* (TARGET_ARM | TARGET_THUMB) */ 201#define TARGET_BACKTRACE (leaf_function_p () \ 202 ? TARGET_TPCS_LEAF_FRAME \ 203 : TARGET_TPCS_FRAME) 204#define TARGET_LDRD (arm_arch5e && ARM_DOUBLEWORD_ALIGN) 205#define TARGET_AAPCS_BASED \ 206 (arm_abi != ARM_ABI_APCS && arm_abi != ARM_ABI_ATPCS) 207 208#define TARGET_HARD_TP (target_thread_pointer == TP_CP15) 209#define TARGET_SOFT_TP (target_thread_pointer == TP_SOFT) 210 211/* Only 16-bit thumb code. */ 212#define TARGET_THUMB1 (TARGET_THUMB && !arm_arch_thumb2) 213/* Arm or Thumb-2 32-bit code. */ 214#define TARGET_32BIT (TARGET_ARM || arm_arch_thumb2) 215/* 32-bit Thumb-2 code. */ 216#define TARGET_THUMB2 (TARGET_THUMB && arm_arch_thumb2) 217/* Thumb-1 only. */ 218#define TARGET_THUMB1_ONLY (TARGET_THUMB1 && !arm_arch_notm) 219/* FPA emulator without LFM. */ 220#define TARGET_FPA_EMU2 (TARGET_FPA && arm_fpu_desc->rev == 2) 221 222/* The following two macros concern the ability to execute coprocessor 223 instructions for VFPv3 or NEON. TARGET_VFP3/TARGET_VFPD32 are currently 224 only ever tested when we know we are generating for VFP hardware; we need 225 to be more careful with TARGET_NEON as noted below. */ 226 227/* FPU is has the full VFPv3/NEON register file of 32 D registers. */ 228#define TARGET_VFPD32 (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_D32) 229 230/* FPU supports VFPv3 instructions. */ 231#define TARGET_VFP3 (TARGET_VFP && arm_fpu_desc->rev >= 3) 232 233/* FPU only supports VFP single-precision instructions. */ 234#define TARGET_VFP_SINGLE (TARGET_VFP && arm_fpu_desc->regs == VFP_REG_SINGLE) 235 236/* FPU supports VFP double-precision instructions. */ 237#define TARGET_VFP_DOUBLE (TARGET_VFP && arm_fpu_desc->regs != VFP_REG_SINGLE) 238 239/* FPU supports half-precision floating-point with NEON element load/store. */ 240#define TARGET_NEON_FP16 \ 241 (TARGET_VFP && arm_fpu_desc->neon && arm_fpu_desc->fp16) 242 243/* FPU supports VFP half-precision floating-point. */ 244#define TARGET_FP16 (TARGET_VFP && arm_fpu_desc->fp16) 245 246/* FPU supports Neon instructions. The setting of this macro gets 247 revealed via __ARM_NEON__ so we add extra guards upon TARGET_32BIT 248 and TARGET_HARD_FLOAT to ensure that NEON instructions are 249 available. */ 250#define TARGET_NEON (TARGET_32BIT && TARGET_HARD_FLOAT \ 251 && TARGET_VFP && arm_fpu_desc->neon) 252 253/* "DSP" multiply instructions, eg. SMULxy. */ 254#define TARGET_DSP_MULTIPLY \ 255 (TARGET_32BIT && arm_arch5e && (arm_arch_notm || arm_arch7em)) 256/* Integer SIMD instructions, and extend-accumulate instructions. */ 257#define TARGET_INT_SIMD \ 258 (TARGET_32BIT && arm_arch6 && (arm_arch_notm || arm_arch7em)) 259 260/* Should MOVW/MOVT be used in preference to a constant pool. */ 261#define TARGET_USE_MOVT (arm_arch_thumb2 && !optimize_size) 262 263/* We could use unified syntax for arm mode, but for now we just use it 264 for Thumb-2. */ 265#define TARGET_UNIFIED_ASM TARGET_THUMB2 266 267 268/* True iff the full BPABI is being used. If TARGET_BPABI is true, 269 then TARGET_AAPCS_BASED must be true -- but the converse does not 270 hold. TARGET_BPABI implies the use of the BPABI runtime library, 271 etc., in addition to just the AAPCS calling conventions. */ 272#ifndef TARGET_BPABI 273#define TARGET_BPABI false 274#endif 275 276/* Support for a compile-time default CPU, et cetera. The rules are: 277 --with-arch is ignored if -march or -mcpu are specified. 278 --with-cpu is ignored if -march or -mcpu are specified, and is overridden 279 by --with-arch. 280 --with-tune is ignored if -mtune or -mcpu are specified (but not affected 281 by -march). 282 --with-float is ignored if -mhard-float, -msoft-float or -mfloat-abi are 283 specified. 284 --with-fpu is ignored if -mfpu is specified. 285 --with-abi is ignored is -mabi is specified. */ 286#define OPTION_DEFAULT_SPECS \ 287 {"arch", "%{!march=*:%{!mcpu=*:-march=%(VALUE)}}" }, \ 288 {"cpu", "%{!march=*:%{!mcpu=*:-mcpu=%(VALUE)}}" }, \ 289 {"tune", "%{!mcpu=*:%{!mtune=*:-mtune=%(VALUE)}}" }, \ 290 {"float", \ 291 "%{!msoft-float:%{!mhard-float:%{!mfloat-abi=*:-mfloat-abi=%(VALUE)}}}" }, \ 292 {"fpu", "%{!mfpu=*:-mfpu=%(VALUE)}"}, \ 293 {"abi", "%{!mabi=*:-mabi=%(VALUE)}"}, \ 294 {"mode", "%{!marm:%{!mthumb:-m%(VALUE)}}"}, 295 296/* Which floating point model to use. */ 297enum arm_fp_model 298{ 299 ARM_FP_MODEL_UNKNOWN, 300 /* FPA model (Hardware or software). */ 301 ARM_FP_MODEL_FPA, 302 /* Cirrus Maverick floating point model. */ 303 ARM_FP_MODEL_MAVERICK, 304 /* VFP floating point model. */ 305 ARM_FP_MODEL_VFP 306}; 307 308enum vfp_reg_type 309{ 310 VFP_NONE = 0, 311 VFP_REG_D16, 312 VFP_REG_D32, 313 VFP_REG_SINGLE 314}; 315 316extern const struct arm_fpu_desc 317{ 318 const char *name; 319 enum arm_fp_model model; 320 int rev; 321 enum vfp_reg_type regs; 322 int neon; 323 int fp16; 324} *arm_fpu_desc; 325 326/* Which floating point hardware to schedule for. */ 327extern int arm_fpu_attr; 328 329enum float_abi_type 330{ 331 ARM_FLOAT_ABI_SOFT, 332 ARM_FLOAT_ABI_SOFTFP, 333 ARM_FLOAT_ABI_HARD 334}; 335 336extern enum float_abi_type arm_float_abi; 337 338#ifndef TARGET_DEFAULT_FLOAT_ABI 339#define TARGET_DEFAULT_FLOAT_ABI ARM_FLOAT_ABI_SOFT 340#endif 341 342/* Which __fp16 format to use. 343 The enumeration values correspond to the numbering for the 344 Tag_ABI_FP_16bit_format attribute. 345 */ 346enum arm_fp16_format_type 347{ 348 ARM_FP16_FORMAT_NONE = 0, 349 ARM_FP16_FORMAT_IEEE = 1, 350 ARM_FP16_FORMAT_ALTERNATIVE = 2 351}; 352 353extern enum arm_fp16_format_type arm_fp16_format; 354#define LARGEST_EXPONENT_IS_NORMAL(bits) \ 355 ((bits) == 16 && arm_fp16_format == ARM_FP16_FORMAT_ALTERNATIVE) 356 357/* Which ABI to use. */ 358enum arm_abi_type 359{ 360 ARM_ABI_APCS, 361 ARM_ABI_ATPCS, 362 ARM_ABI_AAPCS, 363 ARM_ABI_IWMMXT, 364 ARM_ABI_AAPCS_LINUX 365}; 366 367extern enum arm_abi_type arm_abi; 368 369#ifndef ARM_DEFAULT_ABI 370#define ARM_DEFAULT_ABI ARM_ABI_APCS 371#endif 372 373/* Which thread pointer access sequence to use. */ 374enum arm_tp_type { 375 TP_AUTO, 376 TP_SOFT, 377 TP_CP15 378}; 379 380extern enum arm_tp_type target_thread_pointer; 381 382/* Nonzero if this chip supports the ARM Architecture 3M extensions. */ 383extern int arm_arch3m; 384 385/* Nonzero if this chip supports the ARM Architecture 4 extensions. */ 386extern int arm_arch4; 387 388/* Nonzero if this chip supports the ARM Architecture 4T extensions. */ 389extern int arm_arch4t; 390 391/* Nonzero if this chip supports the ARM Architecture 5 extensions. */ 392extern int arm_arch5; 393 394/* Nonzero if this chip supports the ARM Architecture 5E extensions. */ 395extern int arm_arch5e; 396 397/* Nonzero if this chip supports the ARM Architecture 6 extensions. */ 398extern int arm_arch6; 399 400/* Nonzero if instructions not present in the 'M' profile can be used. */ 401extern int arm_arch_notm; 402 403/* Nonzero if instructions present in ARMv7E-M can be used. */ 404extern int arm_arch7em; 405 406/* Nonzero if this chip can benefit from load scheduling. */ 407extern int arm_ld_sched; 408 409/* Nonzero if generating thumb code. */ 410extern int thumb_code; 411 412/* Nonzero if this chip is a StrongARM. */ 413extern int arm_tune_strongarm; 414 415/* Nonzero if this chip is a Cirrus variant. */ 416extern int arm_arch_cirrus; 417 418/* Nonzero if this chip supports Intel XScale with Wireless MMX technology. */ 419extern int arm_arch_iwmmxt; 420 421/* Nonzero if this chip is an XScale. */ 422extern int arm_arch_xscale; 423 424/* Nonzero if tuning for XScale. */ 425extern int arm_tune_xscale; 426 427/* Nonzero if tuning for stores via the write buffer. */ 428extern int arm_tune_wbuf; 429 430/* Nonzero if tuning for Cortex-A9. */ 431extern int arm_tune_cortex_a9; 432 433/* Nonzero if we should define __THUMB_INTERWORK__ in the 434 preprocessor. 435 XXX This is a bit of a hack, it's intended to help work around 436 problems in GLD which doesn't understand that armv5t code is 437 interworking clean. */ 438extern int arm_cpp_interwork; 439 440/* Nonzero if chip supports Thumb 2. */ 441extern int arm_arch_thumb2; 442 443/* Nonzero if chip supports integer division instruction. */ 444extern int arm_arch_hwdiv; 445 446#ifndef TARGET_DEFAULT 447#define TARGET_DEFAULT (MASK_APCS_FRAME) 448#endif 449 450/* The frame pointer register used in gcc has nothing to do with debugging; 451 that is controlled by the APCS-FRAME option. */ 452#define CAN_DEBUG_WITHOUT_FP 453 454#define OVERRIDE_OPTIONS arm_override_options () 455 456#define OPTIMIZATION_OPTIONS(LEVEL,SIZE) \ 457 arm_optimization_options ((LEVEL), (SIZE)) 458 459/* Nonzero if PIC code requires explicit qualifiers to generate 460 PLT and GOT relocs rather than the assembler doing so implicitly. 461 Subtargets can override these if required. */ 462#ifndef NEED_GOT_RELOC 463#define NEED_GOT_RELOC 0 464#endif 465#ifndef NEED_PLT_RELOC 466#define NEED_PLT_RELOC 0 467#endif 468 469/* Nonzero if we need to refer to the GOT with a PC-relative 470 offset. In other words, generate 471 472 .word _GLOBAL_OFFSET_TABLE_ - [. - (.Lxx + 8)] 473 474 rather than 475 476 .word _GLOBAL_OFFSET_TABLE_ - (.Lxx + 8) 477 478 The default is true, which matches NetBSD. Subtargets can 479 override this if required. */ 480#ifndef GOT_PCREL 481#define GOT_PCREL 1 482#endif 483 484/* Target machine storage Layout. */ 485 486 487/* Define this macro if it is advisable to hold scalars in registers 488 in a wider mode than that declared by the program. In such cases, 489 the value is constrained to be within the bounds of the declared 490 type, but kept valid in the wider mode. The signedness of the 491 extension may differ from that of the type. */ 492 493/* It is far faster to zero extend chars than to sign extend them */ 494 495#define PROMOTE_MODE(MODE, UNSIGNEDP, TYPE) \ 496 if (GET_MODE_CLASS (MODE) == MODE_INT \ 497 && GET_MODE_SIZE (MODE) < 4) \ 498 { \ 499 if (MODE == QImode) \ 500 UNSIGNEDP = 1; \ 501 else if (MODE == HImode) \ 502 UNSIGNEDP = 1; \ 503 (MODE) = SImode; \ 504 } 505 506/* Define this if most significant bit is lowest numbered 507 in instructions that operate on numbered bit-fields. */ 508#define BITS_BIG_ENDIAN 0 509 510/* Define this if most significant byte of a word is the lowest numbered. 511 Most ARM processors are run in little endian mode, so that is the default. 512 If you want to have it run-time selectable, change the definition in a 513 cover file to be TARGET_BIG_ENDIAN. */ 514#define BYTES_BIG_ENDIAN (TARGET_BIG_END != 0) 515 516/* Define this if most significant word of a multiword number is the lowest 517 numbered. 518 This is always false, even when in big-endian mode. */ 519#define WORDS_BIG_ENDIAN (BYTES_BIG_ENDIAN && ! TARGET_LITTLE_WORDS) 520 521/* LIBGCC2_WORDS_BIG_ENDIAN has to be a constant, so we define this based 522 on processor pre-defineds when compiling libgcc2.c. */ 523#if defined(__ARMEB__) && !defined(__ARMWEL__) 524#define LIBGCC2_WORDS_BIG_ENDIAN 1 525#else 526#define LIBGCC2_WORDS_BIG_ENDIAN 0 527#endif 528 529/* Define this if most significant word of doubles is the lowest numbered. 530 The rules are different based on whether or not we use FPA-format, 531 VFP-format or some other floating point co-processor's format doubles. */ 532#define FLOAT_WORDS_BIG_ENDIAN (arm_float_words_big_endian ()) 533 534#define UNITS_PER_WORD 4 535 536/* Use the option -mvectorize-with-neon-quad to override the use of doubleword 537 registers when autovectorizing for Neon, at least until multiple vector 538 widths are supported properly by the middle-end. */ 539#define UNITS_PER_SIMD_WORD(MODE) \ 540 (TARGET_NEON ? (TARGET_NEON_VECTORIZE_QUAD ? 16 : 8) : UNITS_PER_WORD) 541 542/* True if natural alignment is used for doubleword types. */ 543#define ARM_DOUBLEWORD_ALIGN TARGET_AAPCS_BASED 544 545#define DOUBLEWORD_ALIGNMENT 64 546 547#define PARM_BOUNDARY 32 548 549#define STACK_BOUNDARY (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 550 551#define PREFERRED_STACK_BOUNDARY \ 552 (arm_abi == ARM_ABI_ATPCS ? 64 : STACK_BOUNDARY) 553 554#define FUNCTION_BOUNDARY ((TARGET_THUMB && optimize_size) ? 16 : 32) 555 556/* The lowest bit is used to indicate Thumb-mode functions, so the 557 vbit must go into the delta field of pointers to member 558 functions. */ 559#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_delta 560 561#define EMPTY_FIELD_BOUNDARY 32 562 563#define BIGGEST_ALIGNMENT (ARM_DOUBLEWORD_ALIGN ? DOUBLEWORD_ALIGNMENT : 32) 564 565/* XXX Blah -- this macro is used directly by libobjc. Since it 566 supports no vector modes, cut out the complexity and fall back 567 on BIGGEST_FIELD_ALIGNMENT. */ 568#ifdef IN_TARGET_LIBS 569#define BIGGEST_FIELD_ALIGNMENT 64 570#endif 571 572/* Make strings word-aligned so strcpy from constants will be faster. */ 573#define CONSTANT_ALIGNMENT_FACTOR (TARGET_THUMB || ! arm_tune_xscale ? 1 : 2) 574 575#define CONSTANT_ALIGNMENT(EXP, ALIGN) \ 576 ((TREE_CODE (EXP) == STRING_CST \ 577 && !optimize_size \ 578 && (ALIGN) < BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR) \ 579 ? BITS_PER_WORD * CONSTANT_ALIGNMENT_FACTOR : (ALIGN)) 580 581/* Align definitions of arrays, unions and structures so that 582 initializations and copies can be made more efficient. This is not 583 ABI-changing, so it only affects places where we can see the 584 definition. */ 585#define DATA_ALIGNMENT(EXP, ALIGN) \ 586 ((((ALIGN) < BITS_PER_WORD) \ 587 && (TREE_CODE (EXP) == ARRAY_TYPE \ 588 || TREE_CODE (EXP) == UNION_TYPE \ 589 || TREE_CODE (EXP) == RECORD_TYPE)) ? BITS_PER_WORD : (ALIGN)) 590 591/* Similarly, make sure that objects on the stack are sensibly aligned. */ 592#define LOCAL_ALIGNMENT(EXP, ALIGN) DATA_ALIGNMENT(EXP, ALIGN) 593 594/* Setting STRUCTURE_SIZE_BOUNDARY to 32 produces more efficient code, but the 595 value set in previous versions of this toolchain was 8, which produces more 596 compact structures. The command line option -mstructure_size_boundary=<n> 597 can be used to change this value. For compatibility with the ARM SDK 598 however the value should be left at 32. ARM SDT Reference Manual (ARM DUI 599 0020D) page 2-20 says "Structures are aligned on word boundaries". 600 The AAPCS specifies a value of 8. */ 601#define STRUCTURE_SIZE_BOUNDARY arm_structure_size_boundary 602extern int arm_structure_size_boundary; 603 604/* This is the value used to initialize arm_structure_size_boundary. If a 605 particular arm target wants to change the default value it should change 606 the definition of this macro, not STRUCTURE_SIZE_BOUNDARY. See netbsd.h 607 for an example of this. */ 608#ifndef DEFAULT_STRUCTURE_SIZE_BOUNDARY 609#define DEFAULT_STRUCTURE_SIZE_BOUNDARY 32 610#endif 611 612/* Nonzero if move instructions will actually fail to work 613 when given unaligned data. */ 614#define STRICT_ALIGNMENT 1 615 616/* wchar_t is unsigned under the AAPCS. */ 617#ifndef WCHAR_TYPE 618#define WCHAR_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "int") 619 620#define WCHAR_TYPE_SIZE BITS_PER_WORD 621#endif 622 623#ifndef SIZE_TYPE 624#define SIZE_TYPE (TARGET_AAPCS_BASED ? "unsigned int" : "long unsigned int") 625#endif 626 627#ifndef PTRDIFF_TYPE 628#define PTRDIFF_TYPE (TARGET_AAPCS_BASED ? "int" : "long int") 629#endif 630 631/* AAPCS requires that structure alignment is affected by bitfields. */ 632#ifndef PCC_BITFIELD_TYPE_MATTERS 633#define PCC_BITFIELD_TYPE_MATTERS TARGET_AAPCS_BASED 634#endif 635 636 637/* Standard register usage. */ 638 639/* Register allocation in ARM Procedure Call Standard (as used on RISCiX): 640 (S - saved over call). 641 642 r0 * argument word/integer result 643 r1-r3 argument word 644 645 r4-r8 S register variable 646 r9 S (rfp) register variable (real frame pointer) 647 648 r10 F S (sl) stack limit (used by -mapcs-stack-check) 649 r11 F S (fp) argument pointer 650 r12 (ip) temp workspace 651 r13 F S (sp) lower end of current stack frame 652 r14 (lr) link address/workspace 653 r15 F (pc) program counter 654 655 f0 floating point result 656 f1-f3 floating point scratch 657 658 f4-f7 S floating point variable 659 660 cc This is NOT a real register, but is used internally 661 to represent things that use or set the condition 662 codes. 663 sfp This isn't either. It is used during rtl generation 664 since the offset between the frame pointer and the 665 auto's isn't known until after register allocation. 666 afp Nor this, we only need this because of non-local 667 goto. Without it fp appears to be used and the 668 elimination code won't get rid of sfp. It tracks 669 fp exactly at all times. 670 671 *: See CONDITIONAL_REGISTER_USAGE */ 672 673/* 674 mvf0 Cirrus floating point result 675 mvf1-mvf3 Cirrus floating point scratch 676 mvf4-mvf15 S Cirrus floating point variable. */ 677 678/* s0-s15 VFP scratch (aka d0-d7). 679 s16-s31 S VFP variable (aka d8-d15). 680 vfpcc Not a real register. Represents the VFP condition 681 code flags. */ 682 683/* The stack backtrace structure is as follows: 684 fp points to here: | save code pointer | [fp] 685 | return link value | [fp, #-4] 686 | return sp value | [fp, #-8] 687 | return fp value | [fp, #-12] 688 [| saved r10 value |] 689 [| saved r9 value |] 690 [| saved r8 value |] 691 [| saved r7 value |] 692 [| saved r6 value |] 693 [| saved r5 value |] 694 [| saved r4 value |] 695 [| saved r3 value |] 696 [| saved r2 value |] 697 [| saved r1 value |] 698 [| saved r0 value |] 699 [| saved f7 value |] three words 700 [| saved f6 value |] three words 701 [| saved f5 value |] three words 702 [| saved f4 value |] three words 703 r0-r3 are not normally saved in a C function. */ 704 705/* 1 for registers that have pervasive standard uses 706 and are not available for the register allocator. */ 707#define FIXED_REGISTERS \ 708{ \ 709 0,0,0,0,0,0,0,0, \ 710 0,0,0,0,0,1,0,1, \ 711 0,0,0,0,0,0,0,0, \ 712 1,1,1, \ 713 1,1,1,1,1,1,1,1, \ 714 1,1,1,1,1,1,1,1, \ 715 1,1,1,1,1,1,1,1, \ 716 1,1,1,1,1,1,1,1, \ 717 1,1,1,1, \ 718 1,1,1,1,1,1,1,1, \ 719 1,1,1,1,1,1,1,1, \ 720 1,1,1,1,1,1,1,1, \ 721 1,1,1,1,1,1,1,1, \ 722 1,1,1,1,1,1,1,1, \ 723 1,1,1,1,1,1,1,1, \ 724 1,1,1,1,1,1,1,1, \ 725 1,1,1,1,1,1,1,1, \ 726 1 \ 727} 728 729/* 1 for registers not available across function calls. 730 These must include the FIXED_REGISTERS and also any 731 registers that can be used without being saved. 732 The latter must include the registers where values are returned 733 and the register where structure-value addresses are passed. 734 Aside from that, you can include as many other registers as you like. 735 The CC is not preserved over function calls on the ARM 6, so it is 736 easier to assume this for all. SFP is preserved, since FP is. */ 737#define CALL_USED_REGISTERS \ 738{ \ 739 1,1,1,1,0,0,0,0, \ 740 0,0,0,0,1,1,1,1, \ 741 1,1,1,1,0,0,0,0, \ 742 1,1,1, \ 743 1,1,1,1,1,1,1,1, \ 744 1,1,1,1,1,1,1,1, \ 745 1,1,1,1,1,1,1,1, \ 746 1,1,1,1,1,1,1,1, \ 747 1,1,1,1, \ 748 1,1,1,1,1,1,1,1, \ 749 1,1,1,1,1,1,1,1, \ 750 1,1,1,1,1,1,1,1, \ 751 1,1,1,1,1,1,1,1, \ 752 1,1,1,1,1,1,1,1, \ 753 1,1,1,1,1,1,1,1, \ 754 1,1,1,1,1,1,1,1, \ 755 1,1,1,1,1,1,1,1, \ 756 1 \ 757} 758 759#ifndef SUBTARGET_CONDITIONAL_REGISTER_USAGE 760#define SUBTARGET_CONDITIONAL_REGISTER_USAGE 761#endif 762 763#define CONDITIONAL_REGISTER_USAGE \ 764{ \ 765 int regno; \ 766 \ 767 if (TARGET_SOFT_FLOAT || TARGET_THUMB1 || !TARGET_FPA) \ 768 { \ 769 for (regno = FIRST_FPA_REGNUM; \ 770 regno <= LAST_FPA_REGNUM; ++regno) \ 771 fixed_regs[regno] = call_used_regs[regno] = 1; \ 772 } \ 773 \ 774 if (TARGET_THUMB && optimize_size) \ 775 { \ 776 /* When optimizing for size, it's better not to use \ 777 the HI regs, because of the overhead of stacking \ 778 them. */ \ 779 /* ??? Is this still true for thumb2? */ \ 780 for (regno = FIRST_HI_REGNUM; \ 781 regno <= LAST_HI_REGNUM; ++regno) \ 782 fixed_regs[regno] = call_used_regs[regno] = 1; \ 783 } \ 784 \ 785 /* The link register can be clobbered by any branch insn, \ 786 but we have no way to track that at present, so mark \ 787 it as unavailable. */ \ 788 if (TARGET_THUMB1) \ 789 fixed_regs[LR_REGNUM] = call_used_regs[LR_REGNUM] = 1; \ 790 \ 791 if (TARGET_32BIT && TARGET_HARD_FLOAT) \ 792 { \ 793 if (TARGET_MAVERICK) \ 794 { \ 795 for (regno = FIRST_FPA_REGNUM; \ 796 regno <= LAST_FPA_REGNUM; ++ regno) \ 797 fixed_regs[regno] = call_used_regs[regno] = 1; \ 798 for (regno = FIRST_CIRRUS_FP_REGNUM; \ 799 regno <= LAST_CIRRUS_FP_REGNUM; ++ regno) \ 800 { \ 801 fixed_regs[regno] = 0; \ 802 call_used_regs[regno] = regno < FIRST_CIRRUS_FP_REGNUM + 4; \ 803 } \ 804 } \ 805 if (TARGET_VFP) \ 806 { \ 807 /* VFPv3 registers are disabled when earlier VFP \ 808 versions are selected due to the definition of \ 809 LAST_VFP_REGNUM. */ \ 810 for (regno = FIRST_VFP_REGNUM; \ 811 regno <= LAST_VFP_REGNUM; ++ regno) \ 812 { \ 813 fixed_regs[regno] = 0; \ 814 call_used_regs[regno] = regno < FIRST_VFP_REGNUM + 16 \ 815 || regno >= FIRST_VFP_REGNUM + 32; \ 816 } \ 817 } \ 818 } \ 819 \ 820 if (TARGET_REALLY_IWMMXT) \ 821 { \ 822 regno = FIRST_IWMMXT_GR_REGNUM; \ 823 /* The 2002/10/09 revision of the XScale ABI has wCG0 \ 824 and wCG1 as call-preserved registers. The 2002/11/21 \ 825 revision changed this so that all wCG registers are \ 826 scratch registers. */ \ 827 for (regno = FIRST_IWMMXT_GR_REGNUM; \ 828 regno <= LAST_IWMMXT_GR_REGNUM; ++ regno) \ 829 fixed_regs[regno] = 0; \ 830 /* The XScale ABI has wR0 - wR9 as scratch registers, \ 831 the rest as call-preserved registers. */ \ 832 for (regno = FIRST_IWMMXT_REGNUM; \ 833 regno <= LAST_IWMMXT_REGNUM; ++ regno) \ 834 { \ 835 fixed_regs[regno] = 0; \ 836 call_used_regs[regno] = regno < FIRST_IWMMXT_REGNUM + 10; \ 837 } \ 838 } \ 839 \ 840 if ((unsigned) PIC_OFFSET_TABLE_REGNUM != INVALID_REGNUM) \ 841 { \ 842 fixed_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 843 call_used_regs[PIC_OFFSET_TABLE_REGNUM] = 1; \ 844 } \ 845 else if (TARGET_APCS_STACK) \ 846 { \ 847 fixed_regs[10] = 1; \ 848 call_used_regs[10] = 1; \ 849 } \ 850 /* -mcaller-super-interworking reserves r11 for calls to \ 851 _interwork_r11_call_via_rN(). Making the register global \ 852 is an easy way of ensuring that it remains valid for all \ 853 calls. */ \ 854 if (TARGET_APCS_FRAME || TARGET_CALLER_INTERWORKING \ 855 || TARGET_TPCS_FRAME || TARGET_TPCS_LEAF_FRAME) \ 856 { \ 857 fixed_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 858 call_used_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 859 if (TARGET_CALLER_INTERWORKING) \ 860 global_regs[ARM_HARD_FRAME_POINTER_REGNUM] = 1; \ 861 } \ 862 SUBTARGET_CONDITIONAL_REGISTER_USAGE \ 863} 864 865/* These are a couple of extensions to the formats accepted 866 by asm_fprintf: 867 %@ prints out ASM_COMMENT_START 868 %r prints out REGISTER_PREFIX reg_names[arg] */ 869#define ASM_FPRINTF_EXTENSIONS(FILE, ARGS, P) \ 870 case '@': \ 871 fputs (ASM_COMMENT_START, FILE); \ 872 break; \ 873 \ 874 case 'r': \ 875 fputs (REGISTER_PREFIX, FILE); \ 876 fputs (reg_names [va_arg (ARGS, int)], FILE); \ 877 break; 878 879/* Round X up to the nearest word. */ 880#define ROUND_UP_WORD(X) (((X) + 3) & ~3) 881 882/* Convert fron bytes to ints. */ 883#define ARM_NUM_INTS(X) (((X) + UNITS_PER_WORD - 1) / UNITS_PER_WORD) 884 885/* The number of (integer) registers required to hold a quantity of type MODE. 886 Also used for VFP registers. */ 887#define ARM_NUM_REGS(MODE) \ 888 ARM_NUM_INTS (GET_MODE_SIZE (MODE)) 889 890/* The number of (integer) registers required to hold a quantity of TYPE MODE. */ 891#define ARM_NUM_REGS2(MODE, TYPE) \ 892 ARM_NUM_INTS ((MODE) == BLKmode ? \ 893 int_size_in_bytes (TYPE) : GET_MODE_SIZE (MODE)) 894 895/* The number of (integer) argument register available. */ 896#define NUM_ARG_REGS 4 897 898/* And similarly for the VFP. */ 899#define NUM_VFP_ARG_REGS 16 900 901/* Return the register number of the N'th (integer) argument. */ 902#define ARG_REGISTER(N) (N - 1) 903 904/* Specify the registers used for certain standard purposes. 905 The values of these macros are register numbers. */ 906 907/* The number of the last argument register. */ 908#define LAST_ARG_REGNUM ARG_REGISTER (NUM_ARG_REGS) 909 910/* The numbers of the Thumb register ranges. */ 911#define FIRST_LO_REGNUM 0 912#define LAST_LO_REGNUM 7 913#define FIRST_HI_REGNUM 8 914#define LAST_HI_REGNUM 11 915 916#ifndef TARGET_UNWIND_INFO 917/* We use sjlj exceptions for backwards compatibility. */ 918#define MUST_USE_SJLJ_EXCEPTIONS 1 919#endif 920 921/* We can generate DWARF2 Unwind info, even though we don't use it. */ 922#define DWARF2_UNWIND_INFO 1 923 924/* Use r0 and r1 to pass exception handling information. */ 925#define EH_RETURN_DATA_REGNO(N) (((N) < 2) ? N : INVALID_REGNUM) 926 927/* The register that holds the return address in exception handlers. */ 928#define ARM_EH_STACKADJ_REGNUM 2 929#define EH_RETURN_STACKADJ_RTX gen_rtx_REG (SImode, ARM_EH_STACKADJ_REGNUM) 930 931/* The native (Norcroft) Pascal compiler for the ARM passes the static chain 932 as an invisible last argument (possible since varargs don't exist in 933 Pascal), so the following is not true. */ 934#define STATIC_CHAIN_REGNUM 12 935 936/* Define this to be where the real frame pointer is if it is not possible to 937 work out the offset between the frame pointer and the automatic variables 938 until after register allocation has taken place. FRAME_POINTER_REGNUM 939 should point to a special register that we will make sure is eliminated. 940 941 For the Thumb we have another problem. The TPCS defines the frame pointer 942 as r11, and GCC believes that it is always possible to use the frame pointer 943 as base register for addressing purposes. (See comments in 944 find_reloads_address()). But - the Thumb does not allow high registers, 945 including r11, to be used as base address registers. Hence our problem. 946 947 The solution used here, and in the old thumb port is to use r7 instead of 948 r11 as the hard frame pointer and to have special code to generate 949 backtrace structures on the stack (if required to do so via a command line 950 option) using r11. This is the only 'user visible' use of r11 as a frame 951 pointer. */ 952#define ARM_HARD_FRAME_POINTER_REGNUM 11 953#define THUMB_HARD_FRAME_POINTER_REGNUM 7 954 955#define HARD_FRAME_POINTER_REGNUM \ 956 (TARGET_ARM \ 957 ? ARM_HARD_FRAME_POINTER_REGNUM \ 958 : THUMB_HARD_FRAME_POINTER_REGNUM) 959 960#define FP_REGNUM HARD_FRAME_POINTER_REGNUM 961 962/* Register to use for pushing function arguments. */ 963#define STACK_POINTER_REGNUM SP_REGNUM 964 965/* ARM floating pointer registers. */ 966#define FIRST_FPA_REGNUM 16 967#define LAST_FPA_REGNUM 23 968#define IS_FPA_REGNUM(REGNUM) \ 969 (((REGNUM) >= FIRST_FPA_REGNUM) && ((REGNUM) <= LAST_FPA_REGNUM)) 970 971#define FIRST_IWMMXT_GR_REGNUM 43 972#define LAST_IWMMXT_GR_REGNUM 46 973#define FIRST_IWMMXT_REGNUM 47 974#define LAST_IWMMXT_REGNUM 62 975#define IS_IWMMXT_REGNUM(REGNUM) \ 976 (((REGNUM) >= FIRST_IWMMXT_REGNUM) && ((REGNUM) <= LAST_IWMMXT_REGNUM)) 977#define IS_IWMMXT_GR_REGNUM(REGNUM) \ 978 (((REGNUM) >= FIRST_IWMMXT_GR_REGNUM) && ((REGNUM) <= LAST_IWMMXT_GR_REGNUM)) 979 980/* Base register for access to local variables of the function. */ 981#define FRAME_POINTER_REGNUM 25 982 983/* Base register for access to arguments of the function. */ 984#define ARG_POINTER_REGNUM 26 985 986#define FIRST_CIRRUS_FP_REGNUM 27 987#define LAST_CIRRUS_FP_REGNUM 42 988#define IS_CIRRUS_REGNUM(REGNUM) \ 989 (((REGNUM) >= FIRST_CIRRUS_FP_REGNUM) && ((REGNUM) <= LAST_CIRRUS_FP_REGNUM)) 990 991#define FIRST_VFP_REGNUM 63 992#define D7_VFP_REGNUM 78 /* Registers 77 and 78 == VFP reg D7. */ 993#define LAST_VFP_REGNUM \ 994 (TARGET_VFPD32 ? LAST_HI_VFP_REGNUM : LAST_LO_VFP_REGNUM) 995 996#define IS_VFP_REGNUM(REGNUM) \ 997 (((REGNUM) >= FIRST_VFP_REGNUM) && ((REGNUM) <= LAST_VFP_REGNUM)) 998 999/* VFP registers are split into two types: those defined by VFP versions < 3 1000 have D registers overlaid on consecutive pairs of S registers. VFP version 3 1001 defines 16 new D registers (d16-d31) which, for simplicity and correctness 1002 in various parts of the backend, we implement as "fake" single-precision 1003 registers (which would be S32-S63, but cannot be used in that way). The 1004 following macros define these ranges of registers. */ 1005#define LAST_LO_VFP_REGNUM 94 1006#define FIRST_HI_VFP_REGNUM 95 1007#define LAST_HI_VFP_REGNUM 126 1008 1009#define VFP_REGNO_OK_FOR_SINGLE(REGNUM) \ 1010 ((REGNUM) <= LAST_LO_VFP_REGNUM) 1011 1012/* DFmode values are only valid in even register pairs. */ 1013#define VFP_REGNO_OK_FOR_DOUBLE(REGNUM) \ 1014 ((((REGNUM) - FIRST_VFP_REGNUM) & 1) == 0) 1015 1016/* Neon Quad values must start at a multiple of four registers. */ 1017#define NEON_REGNO_OK_FOR_QUAD(REGNUM) \ 1018 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0) 1019 1020/* Neon structures of vectors must be in even register pairs and there 1021 must be enough registers available. Because of various patterns 1022 requiring quad registers, we require them to start at a multiple of 1023 four. */ 1024#define NEON_REGNO_OK_FOR_NREGS(REGNUM, N) \ 1025 ((((REGNUM) - FIRST_VFP_REGNUM) & 3) == 0 \ 1026 && (LAST_VFP_REGNUM - (REGNUM) >= 2 * (N) - 1)) 1027 1028/* The number of hard registers is 16 ARM + 8 FPA + 1 CC + 1 SFP + 1 AFP. */ 1029/* + 16 Cirrus registers take us up to 43. */ 1030/* Intel Wireless MMX Technology registers add 16 + 4 more. */ 1031/* VFP (VFP3) adds 32 (64) + 1 more. */ 1032#define FIRST_PSEUDO_REGISTER 128 1033 1034#define DBX_REGISTER_NUMBER(REGNO) arm_dbx_register_number (REGNO) 1035 1036/* Value should be nonzero if functions must have frame pointers. 1037 Zero means the frame pointer need not be set up (and parms may be accessed 1038 via the stack pointer) in functions that seem suitable. 1039 If we have to have a frame pointer we might as well make use of it. 1040 APCS says that the frame pointer does not need to be pushed in leaf 1041 functions, or simple tail call functions. */ 1042 1043#ifndef SUBTARGET_FRAME_POINTER_REQUIRED 1044#define SUBTARGET_FRAME_POINTER_REQUIRED 0 1045#endif 1046 1047/* Return number of consecutive hard regs needed starting at reg REGNO 1048 to hold something of mode MODE. 1049 This is ordinarily the length in words of a value of mode MODE 1050 but can be less for certain modes in special long registers. 1051 1052 On the ARM regs are UNITS_PER_WORD bits wide; FPA regs can hold any FP 1053 mode. */ 1054#define HARD_REGNO_NREGS(REGNO, MODE) \ 1055 ((TARGET_32BIT \ 1056 && REGNO >= FIRST_FPA_REGNUM \ 1057 && REGNO != FRAME_POINTER_REGNUM \ 1058 && REGNO != ARG_POINTER_REGNUM) \ 1059 && !IS_VFP_REGNUM (REGNO) \ 1060 ? 1 : ARM_NUM_REGS (MODE)) 1061 1062/* Return true if REGNO is suitable for holding a quantity of type MODE. */ 1063#define HARD_REGNO_MODE_OK(REGNO, MODE) \ 1064 arm_hard_regno_mode_ok ((REGNO), (MODE)) 1065 1066/* Value is 1 if it is a good idea to tie two pseudo registers 1067 when one has mode MODE1 and one has mode MODE2. 1068 If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2, 1069 for any hard reg, then this must be 0 for correct output. */ 1070#define MODES_TIEABLE_P(MODE1, MODE2) \ 1071 (GET_MODE_CLASS (MODE1) == GET_MODE_CLASS (MODE2)) 1072 1073#define VALID_IWMMXT_REG_MODE(MODE) \ 1074 (arm_vector_mode_supported_p (MODE) || (MODE) == DImode) 1075 1076/* Modes valid for Neon D registers. */ 1077#define VALID_NEON_DREG_MODE(MODE) \ 1078 ((MODE) == V2SImode || (MODE) == V4HImode || (MODE) == V8QImode \ 1079 || (MODE) == V2SFmode || (MODE) == DImode) 1080 1081/* Modes valid for Neon Q registers. */ 1082#define VALID_NEON_QREG_MODE(MODE) \ 1083 ((MODE) == V4SImode || (MODE) == V8HImode || (MODE) == V16QImode \ 1084 || (MODE) == V4SFmode || (MODE) == V2DImode) 1085 1086/* Structure modes valid for Neon registers. */ 1087#define VALID_NEON_STRUCT_MODE(MODE) \ 1088 ((MODE) == TImode || (MODE) == EImode || (MODE) == OImode \ 1089 || (MODE) == CImode || (MODE) == XImode) 1090 1091/* The order in which register should be allocated. It is good to use ip 1092 since no saving is required (though calls clobber it) and it never contains 1093 function parameters. It is quite good to use lr since other calls may 1094 clobber it anyway. Allocate r0 through r3 in reverse order since r3 is 1095 least likely to contain a function parameter; in addition results are 1096 returned in r0. 1097 For VFP/VFPv3, allocate D16-D31 first, then caller-saved registers (D0-D7), 1098 then D8-D15. The reason for doing this is to attempt to reduce register 1099 pressure when both single- and double-precision registers are used in a 1100 function. */ 1101 1102#define REG_ALLOC_ORDER \ 1103{ \ 1104 3, 2, 1, 0, 12, 14, 4, 5, \ 1105 6, 7, 8, 10, 9, 11, 13, 15, \ 1106 16, 17, 18, 19, 20, 21, 22, 23, \ 1107 27, 28, 29, 30, 31, 32, 33, 34, \ 1108 35, 36, 37, 38, 39, 40, 41, 42, \ 1109 43, 44, 45, 46, 47, 48, 49, 50, \ 1110 51, 52, 53, 54, 55, 56, 57, 58, \ 1111 59, 60, 61, 62, \ 1112 24, 25, 26, \ 1113 95, 96, 97, 98, 99, 100, 101, 102, \ 1114 103, 104, 105, 106, 107, 108, 109, 110, \ 1115 111, 112, 113, 114, 115, 116, 117, 118, \ 1116 119, 120, 121, 122, 123, 124, 125, 126, \ 1117 78, 77, 76, 75, 74, 73, 72, 71, \ 1118 70, 69, 68, 67, 66, 65, 64, 63, \ 1119 79, 80, 81, 82, 83, 84, 85, 86, \ 1120 87, 88, 89, 90, 91, 92, 93, 94, \ 1121 127 \ 1122} 1123 1124/* Use different register alloc ordering for Thumb. */ 1125#define ORDER_REGS_FOR_LOCAL_ALLOC arm_order_regs_for_local_alloc () 1126 1127/* Interrupt functions can only use registers that have already been 1128 saved by the prologue, even if they would normally be 1129 call-clobbered. */ 1130#define HARD_REGNO_RENAME_OK(SRC, DST) \ 1131 (! IS_INTERRUPT (cfun->machine->func_type) || \ 1132 df_regs_ever_live_p (DST)) 1133 1134/* Register and constant classes. */ 1135 1136/* Register classes: used to be simple, just all ARM regs or all FPA regs 1137 Now that the Thumb is involved it has become more complicated. */ 1138enum reg_class 1139{ 1140 NO_REGS, 1141 FPA_REGS, 1142 CIRRUS_REGS, 1143 VFP_D0_D7_REGS, 1144 VFP_LO_REGS, 1145 VFP_HI_REGS, 1146 VFP_REGS, 1147 IWMMXT_GR_REGS, 1148 IWMMXT_REGS, 1149 LO_REGS, 1150 STACK_REG, 1151 BASE_REGS, 1152 HI_REGS, 1153 CC_REG, 1154 VFPCC_REG, 1155 GENERAL_REGS, 1156 CORE_REGS, 1157 ALL_REGS, 1158 LIM_REG_CLASSES 1159}; 1160 1161#define N_REG_CLASSES (int) LIM_REG_CLASSES 1162 1163/* Give names of register classes as strings for dump file. */ 1164#define REG_CLASS_NAMES \ 1165{ \ 1166 "NO_REGS", \ 1167 "FPA_REGS", \ 1168 "CIRRUS_REGS", \ 1169 "VFP_D0_D7_REGS", \ 1170 "VFP_LO_REGS", \ 1171 "VFP_HI_REGS", \ 1172 "VFP_REGS", \ 1173 "IWMMXT_GR_REGS", \ 1174 "IWMMXT_REGS", \ 1175 "LO_REGS", \ 1176 "STACK_REG", \ 1177 "BASE_REGS", \ 1178 "HI_REGS", \ 1179 "CC_REG", \ 1180 "VFPCC_REG", \ 1181 "GENERAL_REGS", \ 1182 "CORE_REGS", \ 1183 "ALL_REGS", \ 1184} 1185 1186/* Define which registers fit in which classes. 1187 This is an initializer for a vector of HARD_REG_SET 1188 of length N_REG_CLASSES. */ 1189#define REG_CLASS_CONTENTS \ 1190{ \ 1191 { 0x00000000, 0x00000000, 0x00000000, 0x00000000 }, /* NO_REGS */ \ 1192 { 0x00FF0000, 0x00000000, 0x00000000, 0x00000000 }, /* FPA_REGS */ \ 1193 { 0xF8000000, 0x000007FF, 0x00000000, 0x00000000 }, /* CIRRUS_REGS */ \ 1194 { 0x00000000, 0x80000000, 0x00007FFF, 0x00000000 }, /* VFP_D0_D7_REGS */ \ 1195 { 0x00000000, 0x80000000, 0x7FFFFFFF, 0x00000000 }, /* VFP_LO_REGS */ \ 1196 { 0x00000000, 0x00000000, 0x80000000, 0x7FFFFFFF }, /* VFP_HI_REGS */ \ 1197 { 0x00000000, 0x80000000, 0xFFFFFFFF, 0x7FFFFFFF }, /* VFP_REGS */ \ 1198 { 0x00000000, 0x00007800, 0x00000000, 0x00000000 }, /* IWMMXT_GR_REGS */ \ 1199 { 0x00000000, 0x7FFF8000, 0x00000000, 0x00000000 }, /* IWMMXT_REGS */ \ 1200 { 0x000000FF, 0x00000000, 0x00000000, 0x00000000 }, /* LO_REGS */ \ 1201 { 0x00002000, 0x00000000, 0x00000000, 0x00000000 }, /* STACK_REG */ \ 1202 { 0x000020FF, 0x00000000, 0x00000000, 0x00000000 }, /* BASE_REGS */ \ 1203 { 0x0000DF00, 0x00000000, 0x00000000, 0x00000000 }, /* HI_REGS */ \ 1204 { 0x01000000, 0x00000000, 0x00000000, 0x00000000 }, /* CC_REG */ \ 1205 { 0x00000000, 0x00000000, 0x00000000, 0x80000000 }, /* VFPCC_REG */ \ 1206 { 0x0200DFFF, 0x00000000, 0x00000000, 0x00000000 }, /* GENERAL_REGS */ \ 1207 { 0x0200FFFF, 0x00000000, 0x00000000, 0x00000000 }, /* CORE_REGS */ \ 1208 { 0xFAFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x7FFFFFFF } /* ALL_REGS */ \ 1209} 1210 1211/* Any of the VFP register classes. */ 1212#define IS_VFP_CLASS(X) \ 1213 ((X) == VFP_D0_D7_REGS || (X) == VFP_LO_REGS \ 1214 || (X) == VFP_HI_REGS || (X) == VFP_REGS) 1215 1216/* The same information, inverted: 1217 Return the class number of the smallest class containing 1218 reg number REGNO. This could be a conditional expression 1219 or could index an array. */ 1220#define REGNO_REG_CLASS(REGNO) arm_regno_class (REGNO) 1221 1222/* The following macro defines cover classes for Integrated Register 1223 Allocator. Cover classes is a set of non-intersected register 1224 classes covering all hard registers used for register allocation 1225 purpose. Any move between two registers of a cover class should be 1226 cheaper than load or store of the registers. The macro value is 1227 array of register classes with LIM_REG_CLASSES used as the end 1228 marker. */ 1229 1230#define IRA_COVER_CLASSES \ 1231{ \ 1232 GENERAL_REGS, FPA_REGS, CIRRUS_REGS, VFP_REGS, IWMMXT_GR_REGS, IWMMXT_REGS,\ 1233 LIM_REG_CLASSES \ 1234} 1235 1236/* FPA registers can't do subreg as all values are reformatted to internal 1237 precision. VFP registers may only be accessed in the mode they 1238 were set. */ 1239#define CANNOT_CHANGE_MODE_CLASS(FROM, TO, CLASS) \ 1240 (GET_MODE_SIZE (FROM) != GET_MODE_SIZE (TO) \ 1241 ? reg_classes_intersect_p (FPA_REGS, (CLASS)) \ 1242 || reg_classes_intersect_p (VFP_REGS, (CLASS)) \ 1243 : 0) 1244 1245/* We need to define this for LO_REGS on thumb. Otherwise we can end up 1246 using r0-r4 for function arguments, r7 for the stack frame and don't 1247 have enough left over to do doubleword arithmetic. */ 1248#define CLASS_LIKELY_SPILLED_P(CLASS) \ 1249 ((TARGET_THUMB && (CLASS) == LO_REGS) \ 1250 || (CLASS) == CC_REG) 1251 1252/* The class value for index registers, and the one for base regs. */ 1253#define INDEX_REG_CLASS (TARGET_THUMB1 ? LO_REGS : GENERAL_REGS) 1254#define BASE_REG_CLASS (TARGET_THUMB1 ? LO_REGS : CORE_REGS) 1255 1256/* For the Thumb the high registers cannot be used as base registers 1257 when addressing quantities in QI or HI mode; if we don't know the 1258 mode, then we must be conservative. */ 1259#define MODE_BASE_REG_CLASS(MODE) \ 1260 (TARGET_32BIT ? CORE_REGS : \ 1261 (((MODE) == SImode) ? BASE_REGS : LO_REGS)) 1262 1263/* For Thumb we can not support SP+reg addressing, so we return LO_REGS 1264 instead of BASE_REGS. */ 1265#define MODE_BASE_REG_REG_CLASS(MODE) BASE_REG_CLASS 1266 1267/* When SMALL_REGISTER_CLASSES is nonzero, the compiler allows 1268 registers explicitly used in the rtl to be used as spill registers 1269 but prevents the compiler from extending the lifetime of these 1270 registers. */ 1271#define SMALL_REGISTER_CLASSES TARGET_THUMB1 1272 1273/* Given an rtx X being reloaded into a reg required to be 1274 in class CLASS, return the class of reg to actually use. 1275 In general this is just CLASS, but for the Thumb core registers and 1276 immediate constants we prefer a LO_REGS class or a subset. */ 1277#define PREFERRED_RELOAD_CLASS(X, CLASS) \ 1278 (TARGET_32BIT ? (CLASS) : \ 1279 ((CLASS) == GENERAL_REGS || (CLASS) == HI_REGS \ 1280 || (CLASS) == NO_REGS || (CLASS) == STACK_REG \ 1281 ? LO_REGS : (CLASS))) 1282 1283/* Must leave BASE_REGS reloads alone */ 1284#define THUMB_SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1285 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1286 ? ((true_regnum (X) == -1 ? LO_REGS \ 1287 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1288 : NO_REGS)) \ 1289 : NO_REGS) 1290 1291#define THUMB_SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1292 ((CLASS) != LO_REGS && (CLASS) != BASE_REGS \ 1293 ? ((true_regnum (X) == -1 ? LO_REGS \ 1294 : (true_regnum (X) + HARD_REGNO_NREGS (0, MODE) > 8) ? LO_REGS \ 1295 : NO_REGS)) \ 1296 : NO_REGS) 1297 1298/* Return the register class of a scratch register needed to copy IN into 1299 or out of a register in CLASS in MODE. If it can be done directly, 1300 NO_REGS is returned. */ 1301#define SECONDARY_OUTPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1302 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1303 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1304 && IS_VFP_CLASS (CLASS)) \ 1305 ? coproc_secondary_reload_class (MODE, X, FALSE) \ 1306 : (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) \ 1307 ? coproc_secondary_reload_class (MODE, X, TRUE) \ 1308 : TARGET_32BIT \ 1309 ? (((MODE) == HImode && ! arm_arch4 && true_regnum (X) == -1) \ 1310 ? GENERAL_REGS : NO_REGS) \ 1311 : THUMB_SECONDARY_OUTPUT_RELOAD_CLASS (CLASS, MODE, X)) 1312 1313/* If we need to load shorts byte-at-a-time, then we need a scratch. */ 1314#define SECONDARY_INPUT_RELOAD_CLASS(CLASS, MODE, X) \ 1315 /* Restrict which direct reloads are allowed for VFP/iWMMXt regs. */ \ 1316 ((TARGET_VFP && TARGET_HARD_FLOAT \ 1317 && IS_VFP_CLASS (CLASS)) \ 1318 ? coproc_secondary_reload_class (MODE, X, FALSE) : \ 1319 (TARGET_IWMMXT && (CLASS) == IWMMXT_REGS) ? \ 1320 coproc_secondary_reload_class (MODE, X, TRUE) : \ 1321 /* Cannot load constants into Cirrus registers. */ \ 1322 (TARGET_MAVERICK && TARGET_HARD_FLOAT \ 1323 && (CLASS) == CIRRUS_REGS \ 1324 && (CONSTANT_P (X) || GET_CODE (X) == SYMBOL_REF)) \ 1325 ? GENERAL_REGS : \ 1326 (TARGET_32BIT ? \ 1327 (((CLASS) == IWMMXT_REGS || (CLASS) == IWMMXT_GR_REGS) \ 1328 && CONSTANT_P (X)) \ 1329 ? GENERAL_REGS : \ 1330 (((MODE) == HImode && ! arm_arch4 \ 1331 && (GET_CODE (X) == MEM \ 1332 || ((GET_CODE (X) == REG || GET_CODE (X) == SUBREG) \ 1333 && true_regnum (X) == -1))) \ 1334 ? GENERAL_REGS : NO_REGS) \ 1335 : THUMB_SECONDARY_INPUT_RELOAD_CLASS (CLASS, MODE, X))) 1336 1337/* Try a machine-dependent way of reloading an illegitimate address 1338 operand. If we find one, push the reload and jump to WIN. This 1339 macro is used in only one place: `find_reloads_address' in reload.c. 1340 1341 For the ARM, we wish to handle large displacements off a base 1342 register by splitting the addend across a MOV and the mem insn. 1343 This can cut the number of reloads needed. */ 1344#define ARM_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND, WIN) \ 1345 do \ 1346 { \ 1347 if (GET_CODE (X) == PLUS \ 1348 && GET_CODE (XEXP (X, 0)) == REG \ 1349 && REGNO (XEXP (X, 0)) < FIRST_PSEUDO_REGISTER \ 1350 && REG_MODE_OK_FOR_BASE_P (XEXP (X, 0), MODE) \ 1351 && GET_CODE (XEXP (X, 1)) == CONST_INT) \ 1352 { \ 1353 HOST_WIDE_INT val = INTVAL (XEXP (X, 1)); \ 1354 HOST_WIDE_INT low, high; \ 1355 \ 1356 if (MODE == DImode || (MODE == DFmode && TARGET_SOFT_FLOAT)) \ 1357 low = ((val & 0xf) ^ 0x8) - 0x8; \ 1358 else if (TARGET_MAVERICK && TARGET_HARD_FLOAT) \ 1359 /* Need to be careful, -256 is not a valid offset. */ \ 1360 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 1361 else if (MODE == SImode \ 1362 || (MODE == SFmode && TARGET_SOFT_FLOAT) \ 1363 || ((MODE == HImode || MODE == QImode) && ! arm_arch4)) \ 1364 /* Need to be careful, -4096 is not a valid offset. */ \ 1365 low = val >= 0 ? (val & 0xfff) : -((-val) & 0xfff); \ 1366 else if ((MODE == HImode || MODE == QImode) && arm_arch4) \ 1367 /* Need to be careful, -256 is not a valid offset. */ \ 1368 low = val >= 0 ? (val & 0xff) : -((-val) & 0xff); \ 1369 else if (GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1370 && TARGET_HARD_FLOAT && TARGET_FPA) \ 1371 /* Need to be careful, -1024 is not a valid offset. */ \ 1372 low = val >= 0 ? (val & 0x3ff) : -((-val) & 0x3ff); \ 1373 else \ 1374 break; \ 1375 \ 1376 high = ((((val - low) & (unsigned HOST_WIDE_INT) 0xffffffff) \ 1377 ^ (unsigned HOST_WIDE_INT) 0x80000000) \ 1378 - (unsigned HOST_WIDE_INT) 0x80000000); \ 1379 /* Check for overflow or zero */ \ 1380 if (low == 0 || high == 0 || (high + low != val)) \ 1381 break; \ 1382 \ 1383 /* Reload the high part into a base reg; leave the low part \ 1384 in the mem. */ \ 1385 X = gen_rtx_PLUS (GET_MODE (X), \ 1386 gen_rtx_PLUS (GET_MODE (X), XEXP (X, 0), \ 1387 GEN_INT (high)), \ 1388 GEN_INT (low)); \ 1389 push_reload (XEXP (X, 0), NULL_RTX, &XEXP (X, 0), NULL, \ 1390 MODE_BASE_REG_CLASS (MODE), GET_MODE (X), \ 1391 VOIDmode, 0, 0, OPNUM, TYPE); \ 1392 goto WIN; \ 1393 } \ 1394 } \ 1395 while (0) 1396 1397/* XXX If an HImode FP+large_offset address is converted to an HImode 1398 SP+large_offset address, then reload won't know how to fix it. It sees 1399 only that SP isn't valid for HImode, and so reloads the SP into an index 1400 register, but the resulting address is still invalid because the offset 1401 is too big. We fix it here instead by reloading the entire address. */ 1402/* We could probably achieve better results by defining PROMOTE_MODE to help 1403 cope with the variances between the Thumb's signed and unsigned byte and 1404 halfword load instructions. */ 1405/* ??? This should be safe for thumb2, but we may be able to do better. */ 1406#define THUMB_LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_L, WIN) \ 1407do { \ 1408 rtx new_x = thumb_legitimize_reload_address (&X, MODE, OPNUM, TYPE, IND_L); \ 1409 if (new_x) \ 1410 { \ 1411 X = new_x; \ 1412 goto WIN; \ 1413 } \ 1414} while (0) 1415 1416#define LEGITIMIZE_RELOAD_ADDRESS(X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) \ 1417 if (TARGET_ARM) \ 1418 ARM_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN); \ 1419 else \ 1420 THUMB_LEGITIMIZE_RELOAD_ADDRESS (X, MODE, OPNUM, TYPE, IND_LEVELS, WIN) 1421 1422/* Return the maximum number of consecutive registers 1423 needed to represent mode MODE in a register of class CLASS. 1424 ARM regs are UNITS_PER_WORD bits while FPA regs can hold any FP mode */ 1425#define CLASS_MAX_NREGS(CLASS, MODE) \ 1426 (((CLASS) == FPA_REGS || (CLASS) == CIRRUS_REGS) ? 1 : ARM_NUM_REGS (MODE)) 1427 1428/* If defined, gives a class of registers that cannot be used as the 1429 operand of a SUBREG that changes the mode of the object illegally. */ 1430 1431/* Moves between FPA_REGS and GENERAL_REGS are two memory insns. 1432 Moves between VFP_REGS and GENERAL_REGS are a single insn, but 1433 it is typically more expensive than a single memory access. We set 1434 the cost to less than two memory accesses so that floating 1435 point to integer conversion does not go through memory. */ 1436#define REGISTER_MOVE_COST(MODE, FROM, TO) \ 1437 (TARGET_32BIT ? \ 1438 ((FROM) == FPA_REGS && (TO) != FPA_REGS ? 20 : \ 1439 (FROM) != FPA_REGS && (TO) == FPA_REGS ? 20 : \ 1440 IS_VFP_CLASS (FROM) && !IS_VFP_CLASS (TO) ? 15 : \ 1441 !IS_VFP_CLASS (FROM) && IS_VFP_CLASS (TO) ? 15 : \ 1442 (FROM) == IWMMXT_REGS && (TO) != IWMMXT_REGS ? 4 : \ 1443 (FROM) != IWMMXT_REGS && (TO) == IWMMXT_REGS ? 4 : \ 1444 (FROM) == IWMMXT_GR_REGS || (TO) == IWMMXT_GR_REGS ? 20 : \ 1445 (FROM) == CIRRUS_REGS && (TO) != CIRRUS_REGS ? 20 : \ 1446 (FROM) != CIRRUS_REGS && (TO) == CIRRUS_REGS ? 20 : \ 1447 2) \ 1448 : \ 1449 ((FROM) == HI_REGS || (TO) == HI_REGS) ? 4 : 2) 1450 1451/* Stack layout; function entry, exit and calling. */ 1452 1453/* Define this if pushing a word on the stack 1454 makes the stack pointer a smaller address. */ 1455#define STACK_GROWS_DOWNWARD 1 1456 1457/* Define this to nonzero if the nominal address of the stack frame 1458 is at the high-address end of the local variables; 1459 that is, each additional local variable allocated 1460 goes at a more negative offset in the frame. */ 1461#define FRAME_GROWS_DOWNWARD 1 1462 1463/* The amount of scratch space needed by _interwork_{r7,r11}_call_via_rN(). 1464 When present, it is one word in size, and sits at the top of the frame, 1465 between the soft frame pointer and either r7 or r11. 1466 1467 We only need _interwork_rM_call_via_rN() for -mcaller-super-interworking, 1468 and only then if some outgoing arguments are passed on the stack. It would 1469 be tempting to also check whether the stack arguments are passed by indirect 1470 calls, but there seems to be no reason in principle why a post-reload pass 1471 couldn't convert a direct call into an indirect one. */ 1472#define CALLER_INTERWORKING_SLOT_SIZE \ 1473 (TARGET_CALLER_INTERWORKING \ 1474 && crtl->outgoing_args_size != 0 \ 1475 ? UNITS_PER_WORD : 0) 1476 1477/* Offset within stack frame to start allocating local variables at. 1478 If FRAME_GROWS_DOWNWARD, this is the offset to the END of the 1479 first local allocated. Otherwise, it is the offset to the BEGINNING 1480 of the first local allocated. */ 1481#define STARTING_FRAME_OFFSET 0 1482 1483/* If we generate an insn to push BYTES bytes, 1484 this says how many the stack pointer really advances by. */ 1485/* The push insns do not do this rounding implicitly. 1486 So don't define this. */ 1487/* #define PUSH_ROUNDING(NPUSHED) ROUND_UP_WORD (NPUSHED) */ 1488 1489/* Define this if the maximum size of all the outgoing args is to be 1490 accumulated and pushed during the prologue. The amount can be 1491 found in the variable crtl->outgoing_args_size. */ 1492#define ACCUMULATE_OUTGOING_ARGS 1 1493 1494/* Offset of first parameter from the argument pointer register value. */ 1495#define FIRST_PARM_OFFSET(FNDECL) (TARGET_ARM ? 4 : 0) 1496 1497/* Value is the number of byte of arguments automatically 1498 popped when returning from a subroutine call. 1499 FUNDECL is the declaration node of the function (as a tree), 1500 FUNTYPE is the data type of the function (as a tree), 1501 or for a library call it is an identifier node for the subroutine name. 1502 SIZE is the number of bytes of arguments passed on the stack. 1503 1504 On the ARM, the caller does not pop any of its arguments that were passed 1505 on the stack. */ 1506#define RETURN_POPS_ARGS(FUNDECL, FUNTYPE, SIZE) 0 1507 1508/* Define how to find the value returned by a library function 1509 assuming the value has mode MODE. */ 1510#define LIBCALL_VALUE(MODE) \ 1511 (TARGET_AAPCS_BASED ? aapcs_libcall_value (MODE) \ 1512 : (TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_FPA \ 1513 && GET_MODE_CLASS (MODE) == MODE_FLOAT) \ 1514 ? gen_rtx_REG (MODE, FIRST_FPA_REGNUM) \ 1515 : TARGET_32BIT && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK \ 1516 && GET_MODE_CLASS (MODE) == MODE_FLOAT \ 1517 ? gen_rtx_REG (MODE, FIRST_CIRRUS_FP_REGNUM) \ 1518 : TARGET_IWMMXT_ABI && arm_vector_mode_supported_p (MODE) \ 1519 ? gen_rtx_REG (MODE, FIRST_IWMMXT_REGNUM) \ 1520 : gen_rtx_REG (MODE, ARG_REGISTER (1))) 1521 1522/* 1 if REGNO is a possible register number for a function value. */ 1523#define FUNCTION_VALUE_REGNO_P(REGNO) \ 1524 ((REGNO) == ARG_REGISTER (1) \ 1525 || (TARGET_AAPCS_BASED && TARGET_32BIT \ 1526 && TARGET_VFP && TARGET_HARD_FLOAT \ 1527 && (REGNO) == FIRST_VFP_REGNUM) \ 1528 || (TARGET_32BIT && ((REGNO) == FIRST_CIRRUS_FP_REGNUM) \ 1529 && TARGET_HARD_FLOAT_ABI && TARGET_MAVERICK) \ 1530 || ((REGNO) == FIRST_IWMMXT_REGNUM && TARGET_IWMMXT_ABI) \ 1531 || (TARGET_32BIT && ((REGNO) == FIRST_FPA_REGNUM) \ 1532 && TARGET_HARD_FLOAT_ABI && TARGET_FPA)) 1533 1534/* Amount of memory needed for an untyped call to save all possible return 1535 registers. */ 1536#define APPLY_RESULT_SIZE arm_apply_result_size() 1537 1538/* Define DEFAULT_PCC_STRUCT_RETURN to 1 if all structure and union return 1539 values must be in memory. On the ARM, they need only do so if larger 1540 than a word, or if they contain elements offset from zero in the struct. */ 1541#define DEFAULT_PCC_STRUCT_RETURN 0 1542 1543/* These bits describe the different types of function supported 1544 by the ARM backend. They are exclusive. i.e. a function cannot be both a 1545 normal function and an interworked function, for example. Knowing the 1546 type of a function is important for determining its prologue and 1547 epilogue sequences. 1548 Note value 7 is currently unassigned. Also note that the interrupt 1549 function types all have bit 2 set, so that they can be tested for easily. 1550 Note that 0 is deliberately chosen for ARM_FT_UNKNOWN so that when the 1551 machine_function structure is initialized (to zero) func_type will 1552 default to unknown. This will force the first use of arm_current_func_type 1553 to call arm_compute_func_type. */ 1554#define ARM_FT_UNKNOWN 0 /* Type has not yet been determined. */ 1555#define ARM_FT_NORMAL 1 /* Your normal, straightforward function. */ 1556#define ARM_FT_INTERWORKED 2 /* A function that supports interworking. */ 1557#define ARM_FT_ISR 4 /* An interrupt service routine. */ 1558#define ARM_FT_FIQ 5 /* A fast interrupt service routine. */ 1559#define ARM_FT_EXCEPTION 6 /* An ARM exception handler (subcase of ISR). */ 1560 1561#define ARM_FT_TYPE_MASK ((1 << 3) - 1) 1562 1563/* In addition functions can have several type modifiers, 1564 outlined by these bit masks: */ 1565#define ARM_FT_INTERRUPT (1 << 2) /* Note overlap with FT_ISR and above. */ 1566#define ARM_FT_NAKED (1 << 3) /* No prologue or epilogue. */ 1567#define ARM_FT_VOLATILE (1 << 4) /* Does not return. */ 1568#define ARM_FT_NESTED (1 << 5) /* Embedded inside another func. */ 1569#define ARM_FT_STACKALIGN (1 << 6) /* Called with misaligned stack. */ 1570 1571/* Some macros to test these flags. */ 1572#define ARM_FUNC_TYPE(t) (t & ARM_FT_TYPE_MASK) 1573#define IS_INTERRUPT(t) (t & ARM_FT_INTERRUPT) 1574#define IS_VOLATILE(t) (t & ARM_FT_VOLATILE) 1575#define IS_NAKED(t) (t & ARM_FT_NAKED) 1576#define IS_NESTED(t) (t & ARM_FT_NESTED) 1577#define IS_STACKALIGN(t) (t & ARM_FT_STACKALIGN) 1578 1579 1580/* Structure used to hold the function stack frame layout. Offsets are 1581 relative to the stack pointer on function entry. Positive offsets are 1582 in the direction of stack growth. 1583 Only soft_frame is used in thumb mode. */ 1584 1585typedef struct GTY(()) arm_stack_offsets 1586{ 1587 int saved_args; /* ARG_POINTER_REGNUM. */ 1588 int frame; /* ARM_HARD_FRAME_POINTER_REGNUM. */ 1589 int saved_regs; 1590 int soft_frame; /* FRAME_POINTER_REGNUM. */ 1591 int locals_base; /* THUMB_HARD_FRAME_POINTER_REGNUM. */ 1592 int outgoing_args; /* STACK_POINTER_REGNUM. */ 1593 unsigned int saved_regs_mask; 1594} 1595arm_stack_offsets; 1596 1597/* A C structure for machine-specific, per-function data. 1598 This is added to the cfun structure. */ 1599typedef struct GTY(()) machine_function 1600{ 1601 /* Additional stack adjustment in __builtin_eh_throw. */ 1602 rtx eh_epilogue_sp_ofs; 1603 /* Records if LR has to be saved for far jumps. */ 1604 int far_jump_used; 1605 /* Records if ARG_POINTER was ever live. */ 1606 int arg_pointer_live; 1607 /* Records if the save of LR has been eliminated. */ 1608 int lr_save_eliminated; 1609 /* The size of the stack frame. Only valid after reload. */ 1610 arm_stack_offsets stack_offsets; 1611 /* Records the type of the current function. */ 1612 unsigned long func_type; 1613 /* Record if the function has a variable argument list. */ 1614 int uses_anonymous_args; 1615 /* Records if sibcalls are blocked because an argument 1616 register is needed to preserve stack alignment. */ 1617 int sibcall_blocked; 1618 /* The PIC register for this function. This might be a pseudo. */ 1619 rtx pic_reg; 1620 /* Labels for per-function Thumb call-via stubs. One per potential calling 1621 register. We can never call via LR or PC. We can call via SP if a 1622 trampoline happens to be on the top of the stack. */ 1623 rtx call_via[14]; 1624 /* Set to 1 when a return insn is output, this means that the epilogue 1625 is not needed. */ 1626 int return_used_this_function; 1627} 1628machine_function; 1629 1630/* As in the machine_function, a global set of call-via labels, for code 1631 that is in text_section. */ 1632extern GTY(()) rtx thumb_call_via_label[14]; 1633 1634/* The number of potential ways of assigning to a co-processor. */ 1635#define ARM_NUM_COPROC_SLOTS 1 1636 1637/* Enumeration of procedure calling standard variants. We don't really 1638 support all of these yet. */ 1639enum arm_pcs 1640{ 1641 ARM_PCS_AAPCS, /* Base standard AAPCS. */ 1642 ARM_PCS_AAPCS_VFP, /* Use VFP registers for floating point values. */ 1643 ARM_PCS_AAPCS_IWMMXT, /* Use iWMMXT registers for vectors. */ 1644 /* This must be the last AAPCS variant. */ 1645 ARM_PCS_AAPCS_LOCAL, /* Private call within this compilation unit. */ 1646 ARM_PCS_ATPCS, /* ATPCS. */ 1647 ARM_PCS_APCS, /* APCS (legacy Linux etc). */ 1648 ARM_PCS_UNKNOWN 1649}; 1650 1651/* A C type for declaring a variable that is used as the first argument of 1652 `FUNCTION_ARG' and other related values. */ 1653typedef struct 1654{ 1655 /* This is the number of registers of arguments scanned so far. */ 1656 int nregs; 1657 /* This is the number of iWMMXt register arguments scanned so far. */ 1658 int iwmmxt_nregs; 1659 int named_count; 1660 int nargs; 1661 /* Which procedure call variant to use for this call. */ 1662 enum arm_pcs pcs_variant; 1663 1664 /* AAPCS related state tracking. */ 1665 int aapcs_arg_processed; /* No need to lay out this argument again. */ 1666 int aapcs_cprc_slot; /* Index of co-processor rules to handle 1667 this argument, or -1 if using core 1668 registers. */ 1669 int aapcs_ncrn; 1670 int aapcs_next_ncrn; 1671 rtx aapcs_reg; /* Register assigned to this argument. */ 1672 int aapcs_partial; /* How many bytes are passed in regs (if 1673 split between core regs and stack. 1674 Zero otherwise. */ 1675 int aapcs_cprc_failed[ARM_NUM_COPROC_SLOTS]; 1676 int can_split; /* Argument can be split between core regs 1677 and the stack. */ 1678 /* Private data for tracking VFP register allocation */ 1679 unsigned aapcs_vfp_regs_free; 1680 unsigned aapcs_vfp_reg_alloc; 1681 int aapcs_vfp_rcount; 1682 MACHMODE aapcs_vfp_rmode; 1683} CUMULATIVE_ARGS; 1684 1685/* Define where to put the arguments to a function. 1686 Value is zero to push the argument on the stack, 1687 or a hard register in which to store the argument. 1688 1689 MODE is the argument's machine mode. 1690 TYPE is the data type of the argument (as a tree). 1691 This is null for libcalls where that information may 1692 not be available. 1693 CUM is a variable of type CUMULATIVE_ARGS which gives info about 1694 the preceding args and about the function being called. 1695 NAMED is nonzero if this argument is a named parameter 1696 (otherwise it is an extra parameter matching an ellipsis). 1697 1698 On the ARM, normally the first 16 bytes are passed in registers r0-r3; all 1699 other arguments are passed on the stack. If (NAMED == 0) (which happens 1700 only in assign_parms, since TARGET_SETUP_INCOMING_VARARGS is 1701 defined), say it is passed in the stack (function_prologue will 1702 indeed make it pass in the stack if necessary). */ 1703#define FUNCTION_ARG(CUM, MODE, TYPE, NAMED) \ 1704 arm_function_arg (&(CUM), (MODE), (TYPE), (NAMED)) 1705 1706#define FUNCTION_ARG_PADDING(MODE, TYPE) \ 1707 (arm_pad_arg_upward (MODE, TYPE) ? upward : downward) 1708 1709#define BLOCK_REG_PADDING(MODE, TYPE, FIRST) \ 1710 (arm_pad_reg_upward (MODE, TYPE, FIRST) ? upward : downward) 1711 1712/* For AAPCS, padding should never be below the argument. For other ABIs, 1713 * mimic the default. */ 1714#define PAD_VARARGS_DOWN \ 1715 ((TARGET_AAPCS_BASED) ? 0 : BYTES_BIG_ENDIAN) 1716 1717/* Initialize a variable CUM of type CUMULATIVE_ARGS 1718 for a call to a function whose data type is FNTYPE. 1719 For a library call, FNTYPE is 0. 1720 On the ARM, the offset starts at 0. */ 1721#define INIT_CUMULATIVE_ARGS(CUM, FNTYPE, LIBNAME, FNDECL, N_NAMED_ARGS) \ 1722 arm_init_cumulative_args (&(CUM), (FNTYPE), (LIBNAME), (FNDECL)) 1723 1724/* Update the data in CUM to advance over an argument 1725 of mode MODE and data type TYPE. 1726 (TYPE is null for libcalls where that information may not be available.) */ 1727#define FUNCTION_ARG_ADVANCE(CUM, MODE, TYPE, NAMED) \ 1728 arm_function_arg_advance (&(CUM), (MODE), (TYPE), (NAMED)) 1729 1730/* If defined, a C expression that gives the alignment boundary, in bits, of an 1731 argument with the specified mode and type. If it is not defined, 1732 `PARM_BOUNDARY' is used for all arguments. */ 1733#define FUNCTION_ARG_BOUNDARY(MODE,TYPE) \ 1734 ((ARM_DOUBLEWORD_ALIGN && arm_needs_doubleword_align (MODE, TYPE)) \ 1735 ? DOUBLEWORD_ALIGNMENT \ 1736 : PARM_BOUNDARY ) 1737 1738/* 1 if N is a possible register number for function argument passing. 1739 On the ARM, r0-r3 are used to pass args. */ 1740#define FUNCTION_ARG_REGNO_P(REGNO) \ 1741 (IN_RANGE ((REGNO), 0, 3) \ 1742 || (TARGET_AAPCS_BASED && TARGET_VFP && TARGET_HARD_FLOAT \ 1743 && IN_RANGE ((REGNO), FIRST_VFP_REGNUM, FIRST_VFP_REGNUM + 15)) \ 1744 || (TARGET_IWMMXT_ABI \ 1745 && IN_RANGE ((REGNO), FIRST_IWMMXT_REGNUM, FIRST_IWMMXT_REGNUM + 9))) 1746 1747 1748/* If your target environment doesn't prefix user functions with an 1749 underscore, you may wish to re-define this to prevent any conflicts. */ 1750#ifndef ARM_MCOUNT_NAME 1751#define ARM_MCOUNT_NAME "*mcount" 1752#endif 1753 1754/* Call the function profiler with a given profile label. The Acorn 1755 compiler puts this BEFORE the prolog but gcc puts it afterwards. 1756 On the ARM the full profile code will look like: 1757 .data 1758 LP1 1759 .word 0 1760 .text 1761 mov ip, lr 1762 bl mcount 1763 .word LP1 1764 1765 profile_function() in final.c outputs the .data section, FUNCTION_PROFILER 1766 will output the .text section. 1767 1768 The ``mov ip,lr'' seems like a good idea to stick with cc convention. 1769 ``prof'' doesn't seem to mind about this! 1770 1771 Note - this version of the code is designed to work in both ARM and 1772 Thumb modes. */ 1773#ifndef ARM_FUNCTION_PROFILER 1774#define ARM_FUNCTION_PROFILER(STREAM, LABELNO) \ 1775{ \ 1776 char temp[20]; \ 1777 rtx sym; \ 1778 \ 1779 asm_fprintf (STREAM, "\tmov\t%r, %r\n\tbl\t", \ 1780 IP_REGNUM, LR_REGNUM); \ 1781 assemble_name (STREAM, ARM_MCOUNT_NAME); \ 1782 fputc ('\n', STREAM); \ 1783 ASM_GENERATE_INTERNAL_LABEL (temp, "LP", LABELNO); \ 1784 sym = gen_rtx_SYMBOL_REF (Pmode, temp); \ 1785 assemble_aligned_integer (UNITS_PER_WORD, sym); \ 1786} 1787#endif 1788 1789#ifdef THUMB_FUNCTION_PROFILER 1790#define FUNCTION_PROFILER(STREAM, LABELNO) \ 1791 if (TARGET_ARM) \ 1792 ARM_FUNCTION_PROFILER (STREAM, LABELNO) \ 1793 else \ 1794 THUMB_FUNCTION_PROFILER (STREAM, LABELNO) 1795#else 1796#define FUNCTION_PROFILER(STREAM, LABELNO) \ 1797 ARM_FUNCTION_PROFILER (STREAM, LABELNO) 1798#endif 1799 1800/* EXIT_IGNORE_STACK should be nonzero if, when returning from a function, 1801 the stack pointer does not matter. The value is tested only in 1802 functions that have frame pointers. 1803 No definition is equivalent to always zero. 1804 1805 On the ARM, the function epilogue recovers the stack pointer from the 1806 frame. */ 1807#define EXIT_IGNORE_STACK 1 1808 1809#define EPILOGUE_USES(REGNO) ((REGNO) == LR_REGNUM) 1810 1811/* Determine if the epilogue should be output as RTL. 1812 You should override this if you define FUNCTION_EXTRA_EPILOGUE. */ 1813/* This is disabled for Thumb-2 because it will confuse the 1814 conditional insn counter. */ 1815#define USE_RETURN_INSN(ISCOND) \ 1816 (TARGET_ARM ? use_return_insn (ISCOND, NULL) : 0) 1817 1818/* Definitions for register eliminations. 1819 1820 This is an array of structures. Each structure initializes one pair 1821 of eliminable registers. The "from" register number is given first, 1822 followed by "to". Eliminations of the same "from" register are listed 1823 in order of preference. 1824 1825 We have two registers that can be eliminated on the ARM. First, the 1826 arg pointer register can often be eliminated in favor of the stack 1827 pointer register. Secondly, the pseudo frame pointer register can always 1828 be eliminated; it is replaced with either the stack or the real frame 1829 pointer. Note we have to use {ARM|THUMB}_HARD_FRAME_POINTER_REGNUM 1830 because the definition of HARD_FRAME_POINTER_REGNUM is not a constant. */ 1831 1832#define ELIMINABLE_REGS \ 1833{{ ARG_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1834 { ARG_POINTER_REGNUM, FRAME_POINTER_REGNUM },\ 1835 { ARG_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1836 { ARG_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM },\ 1837 { FRAME_POINTER_REGNUM, STACK_POINTER_REGNUM },\ 1838 { FRAME_POINTER_REGNUM, ARM_HARD_FRAME_POINTER_REGNUM },\ 1839 { FRAME_POINTER_REGNUM, THUMB_HARD_FRAME_POINTER_REGNUM }} 1840 1841/* Define the offset between two registers, one to be eliminated, and the 1842 other its replacement, at the start of a routine. */ 1843#define INITIAL_ELIMINATION_OFFSET(FROM, TO, OFFSET) \ 1844 if (TARGET_ARM) \ 1845 (OFFSET) = arm_compute_initial_elimination_offset (FROM, TO); \ 1846 else \ 1847 (OFFSET) = thumb_compute_initial_elimination_offset (FROM, TO) 1848 1849/* Special case handling of the location of arguments passed on the stack. */ 1850#define DEBUGGER_ARG_OFFSET(value, addr) value ? value : arm_debugger_arg_offset (value, addr) 1851 1852/* Initialize data used by insn expanders. This is called from insn_emit, 1853 once for every function before code is generated. */ 1854#define INIT_EXPANDERS arm_init_expanders () 1855 1856/* Length in units of the trampoline for entering a nested function. */ 1857#define TRAMPOLINE_SIZE (TARGET_32BIT ? 16 : 20) 1858 1859/* Alignment required for a trampoline in bits. */ 1860#define TRAMPOLINE_ALIGNMENT 32 1861 1862/* Addressing modes, and classification of registers for them. */ 1863#define HAVE_POST_INCREMENT 1 1864#define HAVE_PRE_INCREMENT TARGET_32BIT 1865#define HAVE_POST_DECREMENT TARGET_32BIT 1866#define HAVE_PRE_DECREMENT TARGET_32BIT 1867#define HAVE_PRE_MODIFY_DISP TARGET_32BIT 1868#define HAVE_POST_MODIFY_DISP TARGET_32BIT 1869#define HAVE_PRE_MODIFY_REG TARGET_32BIT 1870#define HAVE_POST_MODIFY_REG TARGET_32BIT 1871 1872/* Macros to check register numbers against specific register classes. */ 1873 1874/* These assume that REGNO is a hard or pseudo reg number. 1875 They give nonzero only if REGNO is a hard reg of the suitable class 1876 or a pseudo reg currently allocated to a suitable hard reg. 1877 Since they use reg_renumber, they are safe only once reg_renumber 1878 has been allocated, which happens in local-alloc.c. */ 1879#define TEST_REGNO(R, TEST, VALUE) \ 1880 ((R TEST VALUE) || ((unsigned) reg_renumber[R] TEST VALUE)) 1881 1882/* Don't allow the pc to be used. */ 1883#define ARM_REGNO_OK_FOR_BASE_P(REGNO) \ 1884 (TEST_REGNO (REGNO, <, PC_REGNUM) \ 1885 || TEST_REGNO (REGNO, ==, FRAME_POINTER_REGNUM) \ 1886 || TEST_REGNO (REGNO, ==, ARG_POINTER_REGNUM)) 1887 1888#define THUMB1_REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1889 (TEST_REGNO (REGNO, <=, LAST_LO_REGNUM) \ 1890 || (GET_MODE_SIZE (MODE) >= 4 \ 1891 && TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM))) 1892 1893#define REGNO_MODE_OK_FOR_BASE_P(REGNO, MODE) \ 1894 (TARGET_THUMB1 \ 1895 ? THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO, MODE) \ 1896 : ARM_REGNO_OK_FOR_BASE_P (REGNO)) 1897 1898/* Nonzero if X can be the base register in a reg+reg addressing mode. 1899 For Thumb, we can not use SP + reg, so reject SP. */ 1900#define REGNO_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 1901 REGNO_MODE_OK_FOR_BASE_P (X, QImode) 1902 1903/* For ARM code, we don't care about the mode, but for Thumb, the index 1904 must be suitable for use in a QImode load. */ 1905#define REGNO_OK_FOR_INDEX_P(REGNO) \ 1906 (REGNO_MODE_OK_FOR_BASE_P (REGNO, QImode) \ 1907 && !TEST_REGNO (REGNO, ==, STACK_POINTER_REGNUM)) 1908 1909/* Maximum number of registers that can appear in a valid memory address. 1910 Shifts in addresses can't be by a register. */ 1911#define MAX_REGS_PER_ADDRESS 2 1912 1913/* Recognize any constant value that is a valid address. */ 1914/* XXX We can address any constant, eventually... */ 1915/* ??? Should the TARGET_ARM here also apply to thumb2? */ 1916#define CONSTANT_ADDRESS_P(X) \ 1917 (GET_CODE (X) == SYMBOL_REF \ 1918 && (CONSTANT_POOL_ADDRESS_P (X) \ 1919 || (TARGET_ARM && optimize > 0 && SYMBOL_REF_FLAG (X)))) 1920 1921/* True if SYMBOL + OFFSET constants must refer to something within 1922 SYMBOL's section. */ 1923#define ARM_OFFSETS_MUST_BE_WITHIN_SECTIONS_P 0 1924 1925/* Nonzero if all target requires all absolute relocations be R_ARM_ABS32. */ 1926#ifndef TARGET_DEFAULT_WORD_RELOCATIONS 1927#define TARGET_DEFAULT_WORD_RELOCATIONS 0 1928#endif 1929 1930/* Nonzero if the constant value X is a legitimate general operand. 1931 It is given that X satisfies CONSTANT_P or is a CONST_DOUBLE. 1932 1933 On the ARM, allow any integer (invalid ones are removed later by insn 1934 patterns), nice doubles and symbol_refs which refer to the function's 1935 constant pool XXX. 1936 1937 When generating pic allow anything. */ 1938#define ARM_LEGITIMATE_CONSTANT_P(X) (flag_pic || ! label_mentioned_p (X)) 1939 1940#define THUMB_LEGITIMATE_CONSTANT_P(X) \ 1941 ( GET_CODE (X) == CONST_INT \ 1942 || GET_CODE (X) == CONST_DOUBLE \ 1943 || CONSTANT_ADDRESS_P (X) \ 1944 || flag_pic) 1945 1946#define LEGITIMATE_CONSTANT_P(X) \ 1947 (!arm_cannot_force_const_mem (X) \ 1948 && (TARGET_32BIT ? ARM_LEGITIMATE_CONSTANT_P (X) \ 1949 : THUMB_LEGITIMATE_CONSTANT_P (X))) 1950 1951#ifndef SUBTARGET_NAME_ENCODING_LENGTHS 1952#define SUBTARGET_NAME_ENCODING_LENGTHS 1953#endif 1954 1955/* This is a C fragment for the inside of a switch statement. 1956 Each case label should return the number of characters to 1957 be stripped from the start of a function's name, if that 1958 name starts with the indicated character. */ 1959#define ARM_NAME_ENCODING_LENGTHS \ 1960 case '*': return 1; \ 1961 SUBTARGET_NAME_ENCODING_LENGTHS 1962 1963/* This is how to output a reference to a user-level label named NAME. 1964 `assemble_name' uses this. */ 1965#undef ASM_OUTPUT_LABELREF 1966#define ASM_OUTPUT_LABELREF(FILE, NAME) \ 1967 arm_asm_output_labelref (FILE, NAME) 1968 1969/* Output IT instructions for conditionally executed Thumb-2 instructions. */ 1970#define ASM_OUTPUT_OPCODE(STREAM, PTR) \ 1971 if (TARGET_THUMB2) \ 1972 thumb2_asm_output_opcode (STREAM); 1973 1974/* The EABI specifies that constructors should go in .init_array. 1975 Other targets use .ctors for compatibility. */ 1976#ifndef ARM_EABI_CTORS_SECTION_OP 1977#define ARM_EABI_CTORS_SECTION_OP \ 1978 "\t.section\t.init_array,\"aw\",%init_array" 1979#endif 1980#ifndef ARM_EABI_DTORS_SECTION_OP 1981#define ARM_EABI_DTORS_SECTION_OP \ 1982 "\t.section\t.fini_array,\"aw\",%fini_array" 1983#endif 1984#define ARM_CTORS_SECTION_OP \ 1985 "\t.section\t.ctors,\"aw\",%progbits" 1986#define ARM_DTORS_SECTION_OP \ 1987 "\t.section\t.dtors,\"aw\",%progbits" 1988 1989/* Define CTORS_SECTION_ASM_OP. */ 1990#undef CTORS_SECTION_ASM_OP 1991#undef DTORS_SECTION_ASM_OP 1992#ifndef IN_LIBGCC2 1993# define CTORS_SECTION_ASM_OP \ 1994 (TARGET_AAPCS_BASED ? ARM_EABI_CTORS_SECTION_OP : ARM_CTORS_SECTION_OP) 1995# define DTORS_SECTION_ASM_OP \ 1996 (TARGET_AAPCS_BASED ? ARM_EABI_DTORS_SECTION_OP : ARM_DTORS_SECTION_OP) 1997#else /* !defined (IN_LIBGCC2) */ 1998/* In libgcc, CTORS_SECTION_ASM_OP must be a compile-time constant, 1999 so we cannot use the definition above. */ 2000# ifdef __ARM_EABI__ 2001/* The .ctors section is not part of the EABI, so we do not define 2002 CTORS_SECTION_ASM_OP when in libgcc; that prevents crtstuff 2003 from trying to use it. We do define it when doing normal 2004 compilation, as .init_array can be used instead of .ctors. */ 2005/* There is no need to emit begin or end markers when using 2006 init_array; the dynamic linker will compute the size of the 2007 array itself based on special symbols created by the static 2008 linker. However, we do need to arrange to set up 2009 exception-handling here. */ 2010# define CTOR_LIST_BEGIN asm (ARM_EABI_CTORS_SECTION_OP) 2011# define CTOR_LIST_END /* empty */ 2012# define DTOR_LIST_BEGIN asm (ARM_EABI_DTORS_SECTION_OP) 2013# define DTOR_LIST_END /* empty */ 2014# else /* !defined (__ARM_EABI__) */ 2015# define CTORS_SECTION_ASM_OP ARM_CTORS_SECTION_OP 2016# define DTORS_SECTION_ASM_OP ARM_DTORS_SECTION_OP 2017# endif /* !defined (__ARM_EABI__) */ 2018#endif /* !defined (IN_LIBCC2) */ 2019 2020/* True if the operating system can merge entities with vague linkage 2021 (e.g., symbols in COMDAT group) during dynamic linking. */ 2022#ifndef TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P 2023#define TARGET_ARM_DYNAMIC_VAGUE_LINKAGE_P true 2024#endif 2025 2026#define ARM_OUTPUT_FN_UNWIND(F, PROLOGUE) arm_output_fn_unwind (F, PROLOGUE) 2027 2028#ifdef TARGET_UNWIND_INFO 2029#define ARM_EABI_UNWIND_TABLES \ 2030 ((!USING_SJLJ_EXCEPTIONS && flag_exceptions) || flag_unwind_tables) 2031#else 2032#define ARM_EABI_UNWIND_TABLES 0 2033#endif 2034 2035/* The macros REG_OK_FOR..._P assume that the arg is a REG rtx 2036 and check its validity for a certain class. 2037 We have two alternate definitions for each of them. 2038 The usual definition accepts all pseudo regs; the other rejects 2039 them unless they have been allocated suitable hard regs. 2040 The symbol REG_OK_STRICT causes the latter definition to be used. 2041 Thumb-2 has the same restrictions as arm. */ 2042#ifndef REG_OK_STRICT 2043 2044#define ARM_REG_OK_FOR_BASE_P(X) \ 2045 (REGNO (X) <= LAST_ARM_REGNUM \ 2046 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2047 || REGNO (X) == FRAME_POINTER_REGNUM \ 2048 || REGNO (X) == ARG_POINTER_REGNUM) 2049 2050#define ARM_REG_OK_FOR_INDEX_P(X) \ 2051 ((REGNO (X) <= LAST_ARM_REGNUM \ 2052 && REGNO (X) != STACK_POINTER_REGNUM) \ 2053 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2054 || REGNO (X) == FRAME_POINTER_REGNUM \ 2055 || REGNO (X) == ARG_POINTER_REGNUM) 2056 2057#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2058 (REGNO (X) <= LAST_LO_REGNUM \ 2059 || REGNO (X) >= FIRST_PSEUDO_REGISTER \ 2060 || (GET_MODE_SIZE (MODE) >= 4 \ 2061 && (REGNO (X) == STACK_POINTER_REGNUM \ 2062 || (X) == hard_frame_pointer_rtx \ 2063 || (X) == arg_pointer_rtx))) 2064 2065#define REG_STRICT_P 0 2066 2067#else /* REG_OK_STRICT */ 2068 2069#define ARM_REG_OK_FOR_BASE_P(X) \ 2070 ARM_REGNO_OK_FOR_BASE_P (REGNO (X)) 2071 2072#define ARM_REG_OK_FOR_INDEX_P(X) \ 2073 ARM_REGNO_OK_FOR_INDEX_P (REGNO (X)) 2074 2075#define THUMB1_REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2076 THUMB1_REGNO_MODE_OK_FOR_BASE_P (REGNO (X), MODE) 2077 2078#define REG_STRICT_P 1 2079 2080#endif /* REG_OK_STRICT */ 2081 2082/* Now define some helpers in terms of the above. */ 2083 2084#define REG_MODE_OK_FOR_BASE_P(X, MODE) \ 2085 (TARGET_THUMB1 \ 2086 ? THUMB1_REG_MODE_OK_FOR_BASE_P (X, MODE) \ 2087 : ARM_REG_OK_FOR_BASE_P (X)) 2088 2089/* For 16-bit Thumb, a valid index register is anything that can be used in 2090 a byte load instruction. */ 2091#define THUMB1_REG_OK_FOR_INDEX_P(X) \ 2092 THUMB1_REG_MODE_OK_FOR_BASE_P (X, QImode) 2093 2094/* Nonzero if X is a hard reg that can be used as an index 2095 or if it is a pseudo reg. On the Thumb, the stack pointer 2096 is not suitable. */ 2097#define REG_OK_FOR_INDEX_P(X) \ 2098 (TARGET_THUMB1 \ 2099 ? THUMB1_REG_OK_FOR_INDEX_P (X) \ 2100 : ARM_REG_OK_FOR_INDEX_P (X)) 2101 2102/* Nonzero if X can be the base register in a reg+reg addressing mode. 2103 For Thumb, we can not use SP + reg, so reject SP. */ 2104#define REG_MODE_OK_FOR_REG_BASE_P(X, MODE) \ 2105 REG_OK_FOR_INDEX_P (X) 2106 2107#define ARM_BASE_REGISTER_RTX_P(X) \ 2108 (GET_CODE (X) == REG && ARM_REG_OK_FOR_BASE_P (X)) 2109 2110#define ARM_INDEX_REGISTER_RTX_P(X) \ 2111 (GET_CODE (X) == REG && ARM_REG_OK_FOR_INDEX_P (X)) 2112 2113/* Define this for compatibility reasons. */ 2114#define HANDLE_PRAGMA_PACK_PUSH_POP 2115 2116/* Specify the machine mode that this machine uses 2117 for the index in the tablejump instruction. */ 2118#define CASE_VECTOR_MODE Pmode 2119 2120#define CASE_VECTOR_PC_RELATIVE (TARGET_THUMB2 \ 2121 || (TARGET_THUMB1 \ 2122 && (optimize_size || flag_pic))) 2123 2124#define CASE_VECTOR_SHORTEN_MODE(min, max, body) \ 2125 (TARGET_THUMB1 \ 2126 ? (min >= 0 && max < 512 \ 2127 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, QImode) \ 2128 : min >= -256 && max < 256 \ 2129 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, QImode) \ 2130 : min >= 0 && max < 8192 \ 2131 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 1, HImode) \ 2132 : min >= -4096 && max < 4096 \ 2133 ? (ADDR_DIFF_VEC_FLAGS (body).offset_unsigned = 0, HImode) \ 2134 : SImode) \ 2135 : ((min < 0 || max >= 0x2000 || !TARGET_THUMB2) ? SImode \ 2136 : (max >= 0x200) ? HImode \ 2137 : QImode)) 2138 2139/* signed 'char' is most compatible, but RISC OS wants it unsigned. 2140 unsigned is probably best, but may break some code. */ 2141#ifndef DEFAULT_SIGNED_CHAR 2142#define DEFAULT_SIGNED_CHAR 0 2143#endif 2144 2145/* Max number of bytes we can move from memory to memory 2146 in one reasonably fast instruction. */ 2147#define MOVE_MAX 4 2148 2149#undef MOVE_RATIO 2150#define MOVE_RATIO(speed) (arm_tune_xscale ? 4 : 2) 2151 2152/* Define if operations between registers always perform the operation 2153 on the full register even if a narrower mode is specified. */ 2154#define WORD_REGISTER_OPERATIONS 2155 2156/* Define if loading in MODE, an integral mode narrower than BITS_PER_WORD 2157 will either zero-extend or sign-extend. The value of this macro should 2158 be the code that says which one of the two operations is implicitly 2159 done, UNKNOWN if none. */ 2160#define LOAD_EXTEND_OP(MODE) \ 2161 (TARGET_THUMB ? ZERO_EXTEND : \ 2162 ((arm_arch4 || (MODE) == QImode) ? ZERO_EXTEND \ 2163 : ((BYTES_BIG_ENDIAN && (MODE) == HImode) ? SIGN_EXTEND : UNKNOWN))) 2164 2165/* Nonzero if access to memory by bytes is slow and undesirable. */ 2166#define SLOW_BYTE_ACCESS 0 2167 2168#define SLOW_UNALIGNED_ACCESS(MODE, ALIGN) 1 2169 2170/* Immediate shift counts are truncated by the output routines (or was it 2171 the assembler?). Shift counts in a register are truncated by ARM. Note 2172 that the native compiler puts too large (> 32) immediate shift counts 2173 into a register and shifts by the register, letting the ARM decide what 2174 to do instead of doing that itself. */ 2175/* This is all wrong. Defining SHIFT_COUNT_TRUNCATED tells combine that 2176 code like (X << (Y % 32)) for register X, Y is equivalent to (X << Y). 2177 On the arm, Y in a register is used modulo 256 for the shift. Only for 2178 rotates is modulo 32 used. */ 2179/* #define SHIFT_COUNT_TRUNCATED 1 */ 2180 2181/* All integers have the same format so truncation is easy. */ 2182#define TRULY_NOOP_TRUNCATION(OUTPREC, INPREC) 1 2183 2184/* Calling from registers is a massive pain. */ 2185#define NO_FUNCTION_CSE 1 2186 2187/* The machine modes of pointers and functions */ 2188#define Pmode SImode 2189#define FUNCTION_MODE Pmode 2190 2191#define ARM_FRAME_RTX(X) \ 2192 ( (X) == frame_pointer_rtx || (X) == stack_pointer_rtx \ 2193 || (X) == arg_pointer_rtx) 2194 2195/* Moves to and from memory are quite expensive */ 2196#define MEMORY_MOVE_COST(M, CLASS, IN) \ 2197 (TARGET_32BIT ? 10 : \ 2198 ((GET_MODE_SIZE (M) < 4 ? 8 : 2 * GET_MODE_SIZE (M)) \ 2199 * (CLASS == LO_REGS ? 1 : 2))) 2200 2201/* Try to generate sequences that don't involve branches, we can then use 2202 conditional instructions */ 2203#define BRANCH_COST(speed_p, predictable_p) \ 2204 (TARGET_32BIT ? 4 : (optimize > 0 ? 2 : 0)) 2205 2206/* Position Independent Code. */ 2207/* We decide which register to use based on the compilation options and 2208 the assembler in use; this is more general than the APCS restriction of 2209 using sb (r9) all the time. */ 2210extern unsigned arm_pic_register; 2211 2212/* The register number of the register used to address a table of static 2213 data addresses in memory. */ 2214#define PIC_OFFSET_TABLE_REGNUM arm_pic_register 2215 2216/* We can't directly access anything that contains a symbol, 2217 nor can we indirect via the constant pool. One exception is 2218 UNSPEC_TLS, which is always PIC. */ 2219#define LEGITIMATE_PIC_OPERAND_P(X) \ 2220 (!(symbol_mentioned_p (X) \ 2221 || label_mentioned_p (X) \ 2222 || (GET_CODE (X) == SYMBOL_REF \ 2223 && CONSTANT_POOL_ADDRESS_P (X) \ 2224 && (symbol_mentioned_p (get_pool_constant (X)) \ 2225 || label_mentioned_p (get_pool_constant (X))))) \ 2226 || tls_mentioned_p (X)) 2227 2228/* We need to know when we are making a constant pool; this determines 2229 whether data needs to be in the GOT or can be referenced via a GOT 2230 offset. */ 2231extern int making_const_table; 2232 2233/* Handle pragmas for compatibility with Intel's compilers. */ 2234/* Also abuse this to register additional C specific EABI attributes. */ 2235#define REGISTER_TARGET_PRAGMAS() do { \ 2236 c_register_pragma (0, "long_calls", arm_pr_long_calls); \ 2237 c_register_pragma (0, "no_long_calls", arm_pr_no_long_calls); \ 2238 c_register_pragma (0, "long_calls_off", arm_pr_long_calls_off); \ 2239 arm_lang_object_attributes_init(); \ 2240} while (0) 2241 2242/* Condition code information. */ 2243/* Given a comparison code (EQ, NE, etc.) and the first operand of a COMPARE, 2244 return the mode to be used for the comparison. */ 2245 2246#define SELECT_CC_MODE(OP, X, Y) arm_select_cc_mode (OP, X, Y) 2247 2248#define REVERSIBLE_CC_MODE(MODE) 1 2249 2250#define REVERSE_CONDITION(CODE,MODE) \ 2251 (((MODE) == CCFPmode || (MODE) == CCFPEmode) \ 2252 ? reverse_condition_maybe_unordered (code) \ 2253 : reverse_condition (code)) 2254 2255#define CANONICALIZE_COMPARISON(CODE, OP0, OP1) \ 2256 do \ 2257 { \ 2258 if (GET_CODE (OP1) == CONST_INT \ 2259 && ! (const_ok_for_arm (INTVAL (OP1)) \ 2260 || (const_ok_for_arm (- INTVAL (OP1))))) \ 2261 { \ 2262 rtx const_op = OP1; \ 2263 CODE = arm_canonicalize_comparison ((CODE), GET_MODE (OP0), \ 2264 &const_op); \ 2265 OP1 = const_op; \ 2266 } \ 2267 } \ 2268 while (0) 2269 2270/* The arm5 clz instruction returns 32. */ 2271#define CLZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 2272#define CTZ_DEFINED_VALUE_AT_ZERO(MODE, VALUE) ((VALUE) = 32, 1) 2273 2274#undef ASM_APP_OFF 2275#define ASM_APP_OFF (TARGET_THUMB1 ? "\t.code\t16\n" : \ 2276 TARGET_THUMB2 ? "\t.thumb\n" : "") 2277 2278/* Output a push or a pop instruction (only used when profiling). 2279 We can't push STATIC_CHAIN_REGNUM (r12) directly with Thumb-1. We know 2280 that ASM_OUTPUT_REG_PUSH will be matched with ASM_OUTPUT_REG_POP, and 2281 that r7 isn't used by the function profiler, so we can use it as a 2282 scratch reg. WARNING: This isn't safe in the general case! It may be 2283 sensitive to future changes in final.c:profile_function. */ 2284#define ASM_OUTPUT_REG_PUSH(STREAM, REGNO) \ 2285 do \ 2286 { \ 2287 if (TARGET_ARM) \ 2288 asm_fprintf (STREAM,"\tstmfd\t%r!,{%r}\n", \ 2289 STACK_POINTER_REGNUM, REGNO); \ 2290 else if (TARGET_THUMB1 \ 2291 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2292 { \ 2293 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2294 asm_fprintf (STREAM, "\tmov\tr7, %r\n", REGNO);\ 2295 asm_fprintf (STREAM, "\tpush\t{r7}\n"); \ 2296 } \ 2297 else \ 2298 asm_fprintf (STREAM, "\tpush {%r}\n", REGNO); \ 2299 } while (0) 2300 2301 2302/* See comment for ASM_OUTPUT_REG_PUSH concerning Thumb-1 issue. */ 2303#define ASM_OUTPUT_REG_POP(STREAM, REGNO) \ 2304 do \ 2305 { \ 2306 if (TARGET_ARM) \ 2307 asm_fprintf (STREAM, "\tldmfd\t%r!,{%r}\n", \ 2308 STACK_POINTER_REGNUM, REGNO); \ 2309 else if (TARGET_THUMB1 \ 2310 && (REGNO) == STATIC_CHAIN_REGNUM) \ 2311 { \ 2312 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2313 asm_fprintf (STREAM, "\tmov\t%r, r7\n", REGNO);\ 2314 asm_fprintf (STREAM, "\tpop\t{r7}\n"); \ 2315 } \ 2316 else \ 2317 asm_fprintf (STREAM, "\tpop {%r}\n", REGNO); \ 2318 } while (0) 2319 2320/* Jump table alignment is explicit in ASM_OUTPUT_CASE_LABEL. */ 2321#define ADDR_VEC_ALIGN(JUMPTABLE) 0 2322 2323/* This is how to output a label which precedes a jumptable. Since 2324 Thumb instructions are 2 bytes, we may need explicit alignment here. */ 2325#undef ASM_OUTPUT_CASE_LABEL 2326#define ASM_OUTPUT_CASE_LABEL(FILE, PREFIX, NUM, JUMPTABLE) \ 2327 do \ 2328 { \ 2329 if (TARGET_THUMB && GET_MODE (PATTERN (JUMPTABLE)) == SImode) \ 2330 ASM_OUTPUT_ALIGN (FILE, 2); \ 2331 (*targetm.asm_out.internal_label) (FILE, PREFIX, NUM); \ 2332 } \ 2333 while (0) 2334 2335/* Make sure subsequent insns are aligned after a TBB. */ 2336#define ASM_OUTPUT_CASE_END(FILE, NUM, JUMPTABLE) \ 2337 do \ 2338 { \ 2339 if (GET_MODE (PATTERN (JUMPTABLE)) == QImode) \ 2340 ASM_OUTPUT_ALIGN (FILE, 1); \ 2341 } \ 2342 while (0) 2343 2344#define ARM_DECLARE_FUNCTION_NAME(STREAM, NAME, DECL) \ 2345 do \ 2346 { \ 2347 if (TARGET_THUMB) \ 2348 { \ 2349 if (is_called_in_ARM_mode (DECL) \ 2350 || (TARGET_THUMB1 && !TARGET_THUMB1_ONLY \ 2351 && cfun->is_thunk)) \ 2352 fprintf (STREAM, "\t.code 32\n") ; \ 2353 else if (TARGET_THUMB1) \ 2354 fprintf (STREAM, "\t.code\t16\n\t.thumb_func\n") ; \ 2355 else \ 2356 fprintf (STREAM, "\t.thumb\n\t.thumb_func\n") ; \ 2357 } \ 2358 if (TARGET_POKE_FUNCTION_NAME) \ 2359 arm_poke_function_name (STREAM, (const char *) NAME); \ 2360 } \ 2361 while (0) 2362 2363/* For aliases of functions we use .thumb_set instead. */ 2364#define ASM_OUTPUT_DEF_FROM_DECLS(FILE, DECL1, DECL2) \ 2365 do \ 2366 { \ 2367 const char *const LABEL1 = XSTR (XEXP (DECL_RTL (decl), 0), 0); \ 2368 const char *const LABEL2 = IDENTIFIER_POINTER (DECL2); \ 2369 \ 2370 if (TARGET_THUMB && TREE_CODE (DECL1) == FUNCTION_DECL) \ 2371 { \ 2372 fprintf (FILE, "\t.thumb_set "); \ 2373 assemble_name (FILE, LABEL1); \ 2374 fprintf (FILE, ","); \ 2375 assemble_name (FILE, LABEL2); \ 2376 fprintf (FILE, "\n"); \ 2377 } \ 2378 else \ 2379 ASM_OUTPUT_DEF (FILE, LABEL1, LABEL2); \ 2380 } \ 2381 while (0) 2382 2383#ifdef HAVE_GAS_MAX_SKIP_P2ALIGN 2384/* To support -falign-* switches we need to use .p2align so 2385 that alignment directives in code sections will be padded 2386 with no-op instructions, rather than zeroes. */ 2387#define ASM_OUTPUT_MAX_SKIP_ALIGN(FILE, LOG, MAX_SKIP) \ 2388 if ((LOG) != 0) \ 2389 { \ 2390 if ((MAX_SKIP) == 0) \ 2391 fprintf ((FILE), "\t.p2align %d\n", (int) (LOG)); \ 2392 else \ 2393 fprintf ((FILE), "\t.p2align %d,,%d\n", \ 2394 (int) (LOG), (int) (MAX_SKIP)); \ 2395 } 2396#endif 2397 2398/* Add two bytes to the length of conditionally executed Thumb-2 2399 instructions for the IT instruction. */ 2400#define ADJUST_INSN_LENGTH(insn, length) \ 2401 if (TARGET_THUMB2 && GET_CODE (PATTERN (insn)) == COND_EXEC) \ 2402 length += 2; 2403 2404/* Only perform branch elimination (by making instructions conditional) if 2405 we're optimizing. For Thumb-2 check if any IT instructions need 2406 outputting. */ 2407#define FINAL_PRESCAN_INSN(INSN, OPVEC, NOPERANDS) \ 2408 if (TARGET_ARM && optimize) \ 2409 arm_final_prescan_insn (INSN); \ 2410 else if (TARGET_THUMB2) \ 2411 thumb2_final_prescan_insn (INSN); \ 2412 else if (TARGET_THUMB1) \ 2413 thumb1_final_prescan_insn (INSN) 2414 2415#define PRINT_OPERAND_PUNCT_VALID_P(CODE) \ 2416 (CODE == '@' || CODE == '|' || CODE == '.' \ 2417 || CODE == '(' || CODE == ')' || CODE == '#' \ 2418 || (TARGET_32BIT && (CODE == '?')) \ 2419 || (TARGET_THUMB2 && (CODE == '!')) \ 2420 || (TARGET_THUMB && (CODE == '_'))) 2421 2422/* Output an operand of an instruction. */ 2423#define PRINT_OPERAND(STREAM, X, CODE) \ 2424 arm_print_operand (STREAM, X, CODE) 2425 2426#define ARM_SIGN_EXTEND(x) ((HOST_WIDE_INT) \ 2427 (HOST_BITS_PER_WIDE_INT <= 32 ? (unsigned HOST_WIDE_INT) (x) \ 2428 : ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0xffffffff) |\ 2429 ((((unsigned HOST_WIDE_INT)(x)) & (unsigned HOST_WIDE_INT) 0x80000000) \ 2430 ? ((~ (unsigned HOST_WIDE_INT) 0) \ 2431 & ~ (unsigned HOST_WIDE_INT) 0xffffffff) \ 2432 : 0)))) 2433 2434/* Output the address of an operand. */ 2435#define ARM_PRINT_OPERAND_ADDRESS(STREAM, X) \ 2436{ \ 2437 int is_minus = GET_CODE (X) == MINUS; \ 2438 \ 2439 if (GET_CODE (X) == REG) \ 2440 asm_fprintf (STREAM, "[%r, #0]", REGNO (X)); \ 2441 else if (GET_CODE (X) == PLUS || is_minus) \ 2442 { \ 2443 rtx base = XEXP (X, 0); \ 2444 rtx index = XEXP (X, 1); \ 2445 HOST_WIDE_INT offset = 0; \ 2446 if (GET_CODE (base) != REG \ 2447 || (GET_CODE (index) == REG && REGNO (index) == SP_REGNUM)) \ 2448 { \ 2449 /* Ensure that BASE is a register. */ \ 2450 /* (one of them must be). */ \ 2451 /* Also ensure the SP is not used as in index register. */ \ 2452 rtx temp = base; \ 2453 base = index; \ 2454 index = temp; \ 2455 } \ 2456 switch (GET_CODE (index)) \ 2457 { \ 2458 case CONST_INT: \ 2459 offset = INTVAL (index); \ 2460 if (is_minus) \ 2461 offset = -offset; \ 2462 asm_fprintf (STREAM, "[%r, #%wd]", \ 2463 REGNO (base), offset); \ 2464 break; \ 2465 \ 2466 case REG: \ 2467 asm_fprintf (STREAM, "[%r, %s%r]", \ 2468 REGNO (base), is_minus ? "-" : "", \ 2469 REGNO (index)); \ 2470 break; \ 2471 \ 2472 case MULT: \ 2473 case ASHIFTRT: \ 2474 case LSHIFTRT: \ 2475 case ASHIFT: \ 2476 case ROTATERT: \ 2477 { \ 2478 asm_fprintf (STREAM, "[%r, %s%r", \ 2479 REGNO (base), is_minus ? "-" : "", \ 2480 REGNO (XEXP (index, 0))); \ 2481 arm_print_operand (STREAM, index, 'S'); \ 2482 fputs ("]", STREAM); \ 2483 break; \ 2484 } \ 2485 \ 2486 default: \ 2487 gcc_unreachable (); \ 2488 } \ 2489 } \ 2490 else if (GET_CODE (X) == PRE_INC || GET_CODE (X) == POST_INC \ 2491 || GET_CODE (X) == PRE_DEC || GET_CODE (X) == POST_DEC) \ 2492 { \ 2493 extern enum machine_mode output_memory_reference_mode; \ 2494 \ 2495 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \ 2496 \ 2497 if (GET_CODE (X) == PRE_DEC || GET_CODE (X) == PRE_INC) \ 2498 asm_fprintf (STREAM, "[%r, #%s%d]!", \ 2499 REGNO (XEXP (X, 0)), \ 2500 GET_CODE (X) == PRE_DEC ? "-" : "", \ 2501 GET_MODE_SIZE (output_memory_reference_mode)); \ 2502 else \ 2503 asm_fprintf (STREAM, "[%r], #%s%d", \ 2504 REGNO (XEXP (X, 0)), \ 2505 GET_CODE (X) == POST_DEC ? "-" : "", \ 2506 GET_MODE_SIZE (output_memory_reference_mode)); \ 2507 } \ 2508 else if (GET_CODE (X) == PRE_MODIFY) \ 2509 { \ 2510 asm_fprintf (STREAM, "[%r, ", REGNO (XEXP (X, 0))); \ 2511 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ 2512 asm_fprintf (STREAM, "#%wd]!", \ 2513 INTVAL (XEXP (XEXP (X, 1), 1))); \ 2514 else \ 2515 asm_fprintf (STREAM, "%r]!", \ 2516 REGNO (XEXP (XEXP (X, 1), 1))); \ 2517 } \ 2518 else if (GET_CODE (X) == POST_MODIFY) \ 2519 { \ 2520 asm_fprintf (STREAM, "[%r], ", REGNO (XEXP (X, 0))); \ 2521 if (GET_CODE (XEXP (XEXP (X, 1), 1)) == CONST_INT) \ 2522 asm_fprintf (STREAM, "#%wd", \ 2523 INTVAL (XEXP (XEXP (X, 1), 1))); \ 2524 else \ 2525 asm_fprintf (STREAM, "%r", \ 2526 REGNO (XEXP (XEXP (X, 1), 1))); \ 2527 } \ 2528 else output_addr_const (STREAM, X); \ 2529} 2530 2531#define THUMB_PRINT_OPERAND_ADDRESS(STREAM, X) \ 2532{ \ 2533 if (GET_CODE (X) == REG) \ 2534 asm_fprintf (STREAM, "[%r]", REGNO (X)); \ 2535 else if (GET_CODE (X) == POST_INC) \ 2536 asm_fprintf (STREAM, "%r!", REGNO (XEXP (X, 0))); \ 2537 else if (GET_CODE (X) == PLUS) \ 2538 { \ 2539 gcc_assert (GET_CODE (XEXP (X, 0)) == REG); \ 2540 if (GET_CODE (XEXP (X, 1)) == CONST_INT) \ 2541 asm_fprintf (STREAM, "[%r, #%wd]", \ 2542 REGNO (XEXP (X, 0)), \ 2543 INTVAL (XEXP (X, 1))); \ 2544 else \ 2545 asm_fprintf (STREAM, "[%r, %r]", \ 2546 REGNO (XEXP (X, 0)), \ 2547 REGNO (XEXP (X, 1))); \ 2548 } \ 2549 else \ 2550 output_addr_const (STREAM, X); \ 2551} 2552 2553#define PRINT_OPERAND_ADDRESS(STREAM, X) \ 2554 if (TARGET_32BIT) \ 2555 ARM_PRINT_OPERAND_ADDRESS (STREAM, X) \ 2556 else \ 2557 THUMB_PRINT_OPERAND_ADDRESS (STREAM, X) 2558 2559#define OUTPUT_ADDR_CONST_EXTRA(file, x, fail) \ 2560 if (arm_output_addr_const_extra (file, x) == FALSE) \ 2561 goto fail 2562 2563/* A C expression whose value is RTL representing the value of the return 2564 address for the frame COUNT steps up from the current frame. */ 2565 2566#define RETURN_ADDR_RTX(COUNT, FRAME) \ 2567 arm_return_addr (COUNT, FRAME) 2568 2569/* Mask of the bits in the PC that contain the real return address 2570 when running in 26-bit mode. */ 2571#define RETURN_ADDR_MASK26 (0x03fffffc) 2572 2573/* Pick up the return address upon entry to a procedure. Used for 2574 dwarf2 unwind information. This also enables the table driven 2575 mechanism. */ 2576#define INCOMING_RETURN_ADDR_RTX gen_rtx_REG (Pmode, LR_REGNUM) 2577#define DWARF_FRAME_RETURN_COLUMN DWARF_FRAME_REGNUM (LR_REGNUM) 2578 2579/* Used to mask out junk bits from the return address, such as 2580 processor state, interrupt status, condition codes and the like. */ 2581#define MASK_RETURN_ADDR \ 2582 /* If we are generating code for an ARM2/ARM3 machine or for an ARM6 \ 2583 in 26 bit mode, the condition codes must be masked out of the \ 2584 return address. This does not apply to ARM6 and later processors \ 2585 when running in 32 bit mode. */ \ 2586 ((arm_arch4 || TARGET_THUMB) \ 2587 ? (gen_int_mode ((unsigned long)0xffffffff, Pmode)) \ 2588 : arm_gen_return_addr_mask ()) 2589 2590 2591/* Neon defines builtins from ARM_BUILTIN_MAX upwards, though they don't have 2592 symbolic names defined here (which would require too much duplication). 2593 FIXME? */ 2594enum arm_builtins 2595{ 2596 ARM_BUILTIN_GETWCX, 2597 ARM_BUILTIN_SETWCX, 2598 2599 ARM_BUILTIN_WZERO, 2600 2601 ARM_BUILTIN_WAVG2BR, 2602 ARM_BUILTIN_WAVG2HR, 2603 ARM_BUILTIN_WAVG2B, 2604 ARM_BUILTIN_WAVG2H, 2605 2606 ARM_BUILTIN_WACCB, 2607 ARM_BUILTIN_WACCH, 2608 ARM_BUILTIN_WACCW, 2609 2610 ARM_BUILTIN_WMACS, 2611 ARM_BUILTIN_WMACSZ, 2612 ARM_BUILTIN_WMACU, 2613 ARM_BUILTIN_WMACUZ, 2614 2615 ARM_BUILTIN_WSADB, 2616 ARM_BUILTIN_WSADBZ, 2617 ARM_BUILTIN_WSADH, 2618 ARM_BUILTIN_WSADHZ, 2619 2620 ARM_BUILTIN_WALIGN, 2621 2622 ARM_BUILTIN_TMIA, 2623 ARM_BUILTIN_TMIAPH, 2624 ARM_BUILTIN_TMIABB, 2625 ARM_BUILTIN_TMIABT, 2626 ARM_BUILTIN_TMIATB, 2627 ARM_BUILTIN_TMIATT, 2628 2629 ARM_BUILTIN_TMOVMSKB, 2630 ARM_BUILTIN_TMOVMSKH, 2631 ARM_BUILTIN_TMOVMSKW, 2632 2633 ARM_BUILTIN_TBCSTB, 2634 ARM_BUILTIN_TBCSTH, 2635 ARM_BUILTIN_TBCSTW, 2636 2637 ARM_BUILTIN_WMADDS, 2638 ARM_BUILTIN_WMADDU, 2639 2640 ARM_BUILTIN_WPACKHSS, 2641 ARM_BUILTIN_WPACKWSS, 2642 ARM_BUILTIN_WPACKDSS, 2643 ARM_BUILTIN_WPACKHUS, 2644 ARM_BUILTIN_WPACKWUS, 2645 ARM_BUILTIN_WPACKDUS, 2646 2647 ARM_BUILTIN_WADDB, 2648 ARM_BUILTIN_WADDH, 2649 ARM_BUILTIN_WADDW, 2650 ARM_BUILTIN_WADDSSB, 2651 ARM_BUILTIN_WADDSSH, 2652 ARM_BUILTIN_WADDSSW, 2653 ARM_BUILTIN_WADDUSB, 2654 ARM_BUILTIN_WADDUSH, 2655 ARM_BUILTIN_WADDUSW, 2656 ARM_BUILTIN_WSUBB, 2657 ARM_BUILTIN_WSUBH, 2658 ARM_BUILTIN_WSUBW, 2659 ARM_BUILTIN_WSUBSSB, 2660 ARM_BUILTIN_WSUBSSH, 2661 ARM_BUILTIN_WSUBSSW, 2662 ARM_BUILTIN_WSUBUSB, 2663 ARM_BUILTIN_WSUBUSH, 2664 ARM_BUILTIN_WSUBUSW, 2665 2666 ARM_BUILTIN_WAND, 2667 ARM_BUILTIN_WANDN, 2668 ARM_BUILTIN_WOR, 2669 ARM_BUILTIN_WXOR, 2670 2671 ARM_BUILTIN_WCMPEQB, 2672 ARM_BUILTIN_WCMPEQH, 2673 ARM_BUILTIN_WCMPEQW, 2674 ARM_BUILTIN_WCMPGTUB, 2675 ARM_BUILTIN_WCMPGTUH, 2676 ARM_BUILTIN_WCMPGTUW, 2677 ARM_BUILTIN_WCMPGTSB, 2678 ARM_BUILTIN_WCMPGTSH, 2679 ARM_BUILTIN_WCMPGTSW, 2680 2681 ARM_BUILTIN_TEXTRMSB, 2682 ARM_BUILTIN_TEXTRMSH, 2683 ARM_BUILTIN_TEXTRMSW, 2684 ARM_BUILTIN_TEXTRMUB, 2685 ARM_BUILTIN_TEXTRMUH, 2686 ARM_BUILTIN_TEXTRMUW, 2687 ARM_BUILTIN_TINSRB, 2688 ARM_BUILTIN_TINSRH, 2689 ARM_BUILTIN_TINSRW, 2690 2691 ARM_BUILTIN_WMAXSW, 2692 ARM_BUILTIN_WMAXSH, 2693 ARM_BUILTIN_WMAXSB, 2694 ARM_BUILTIN_WMAXUW, 2695 ARM_BUILTIN_WMAXUH, 2696 ARM_BUILTIN_WMAXUB, 2697 ARM_BUILTIN_WMINSW, 2698 ARM_BUILTIN_WMINSH, 2699 ARM_BUILTIN_WMINSB, 2700 ARM_BUILTIN_WMINUW, 2701 ARM_BUILTIN_WMINUH, 2702 ARM_BUILTIN_WMINUB, 2703 2704 ARM_BUILTIN_WMULUM, 2705 ARM_BUILTIN_WMULSM, 2706 ARM_BUILTIN_WMULUL, 2707 2708 ARM_BUILTIN_PSADBH, 2709 ARM_BUILTIN_WSHUFH, 2710 2711 ARM_BUILTIN_WSLLH, 2712 ARM_BUILTIN_WSLLW, 2713 ARM_BUILTIN_WSLLD, 2714 ARM_BUILTIN_WSRAH, 2715 ARM_BUILTIN_WSRAW, 2716 ARM_BUILTIN_WSRAD, 2717 ARM_BUILTIN_WSRLH, 2718 ARM_BUILTIN_WSRLW, 2719 ARM_BUILTIN_WSRLD, 2720 ARM_BUILTIN_WRORH, 2721 ARM_BUILTIN_WRORW, 2722 ARM_BUILTIN_WRORD, 2723 ARM_BUILTIN_WSLLHI, 2724 ARM_BUILTIN_WSLLWI, 2725 ARM_BUILTIN_WSLLDI, 2726 ARM_BUILTIN_WSRAHI, 2727 ARM_BUILTIN_WSRAWI, 2728 ARM_BUILTIN_WSRADI, 2729 ARM_BUILTIN_WSRLHI, 2730 ARM_BUILTIN_WSRLWI, 2731 ARM_BUILTIN_WSRLDI, 2732 ARM_BUILTIN_WRORHI, 2733 ARM_BUILTIN_WRORWI, 2734 ARM_BUILTIN_WRORDI, 2735 2736 ARM_BUILTIN_WUNPCKIHB, 2737 ARM_BUILTIN_WUNPCKIHH, 2738 ARM_BUILTIN_WUNPCKIHW, 2739 ARM_BUILTIN_WUNPCKILB, 2740 ARM_BUILTIN_WUNPCKILH, 2741 ARM_BUILTIN_WUNPCKILW, 2742 2743 ARM_BUILTIN_WUNPCKEHSB, 2744 ARM_BUILTIN_WUNPCKEHSH, 2745 ARM_BUILTIN_WUNPCKEHSW, 2746 ARM_BUILTIN_WUNPCKEHUB, 2747 ARM_BUILTIN_WUNPCKEHUH, 2748 ARM_BUILTIN_WUNPCKEHUW, 2749 ARM_BUILTIN_WUNPCKELSB, 2750 ARM_BUILTIN_WUNPCKELSH, 2751 ARM_BUILTIN_WUNPCKELSW, 2752 ARM_BUILTIN_WUNPCKELUB, 2753 ARM_BUILTIN_WUNPCKELUH, 2754 ARM_BUILTIN_WUNPCKELUW, 2755 2756 ARM_BUILTIN_THREAD_POINTER, 2757 2758 ARM_BUILTIN_NEON_BASE, 2759 2760 ARM_BUILTIN_MAX = ARM_BUILTIN_NEON_BASE /* FIXME: Wrong! */ 2761}; 2762 2763/* Do not emit .note.GNU-stack by default. */ 2764#ifndef NEED_INDICATE_EXEC_STACK 2765#define NEED_INDICATE_EXEC_STACK 0 2766#endif 2767 2768#endif /* ! GCC_ARM_H */ 2769