1/* 2 * Include file private to the SOC Interconnect support files. 3 * 4 * Copyright (C) 2015, Broadcom Corporation. All Rights Reserved. 5 * 6 * Permission to use, copy, modify, and/or distribute this software for any 7 * purpose with or without fee is hereby granted, provided that the above 8 * copyright notice and this permission notice appear in all copies. 9 * 10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 13 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 15 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 16 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 17 * 18 * $Id: siutils_priv.h 419467 2013-08-21 09:19:48Z $ 19 */ 20 21#ifndef _siutils_priv_h_ 22#define _siutils_priv_h_ 23 24#ifdef BCMDBG_ERR 25#define SI_ERROR(args) printf args 26#else 27#define SI_ERROR(args) 28#endif /* BCMDBG_ERR */ 29 30#ifdef BCMDBG 31#define SI_MSG(args) printf args 32#else 33#define SI_MSG(args) 34#endif /* BCMDBG */ 35 36#ifdef BCMDBG_SI 37#define SI_VMSG(args) printf args 38#else 39#define SI_VMSG(args) 40#endif 41 42#define IS_SIM(chippkg) ((chippkg == HDLSIM_PKG_ID) || (chippkg == HWSIM_PKG_ID)) 43 44typedef uint32 (*si_intrsoff_t)(void *intr_arg); 45typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg); 46typedef bool (*si_intrsenabled_t)(void *intr_arg); 47 48typedef struct gpioh_item { 49 void *arg; 50 bool level; 51 gpio_handler_t handler; 52 uint32 event; 53 struct gpioh_item *next; 54} gpioh_item_t; 55 56/* misc si info needed by some of the routines */ 57typedef struct si_info { 58 struct si_pub pub; /* back plane public state (must be first field) */ 59 60 void *osh; /* osl os handle */ 61 void *sdh; /* bcmsdh handle */ 62 63 uint dev_coreid; /* the core provides driver functions */ 64 void *intr_arg; /* interrupt callback function arg */ 65 si_intrsoff_t intrsoff_fn; /* turns chip interrupts off */ 66 si_intrsrestore_t intrsrestore_fn; /* restore chip interrupts */ 67 si_intrsenabled_t intrsenabled_fn; /* check if interrupts are enabled */ 68 69 void *pch; /* PCI/E core handle */ 70 71 gpioh_item_t *gpioh_head; /* GPIO event handlers list */ 72 73 bool memseg; /* flag to toggle MEM_SEG register */ 74 75 char *vars; 76 uint varsz; 77 78 void *curmap; /* current regs va */ 79 void *regs[SI_MAXCORES]; /* other regs va */ 80 81 uint curidx; /* current core index */ 82 uint numcores; /* # discovered cores */ 83 uint coreid[SI_MAXCORES]; /* id of each core */ 84 uint32 coresba[SI_MAXCORES]; /* backplane address of each core */ 85 void *regs2[SI_MAXCORES]; /* va of each core second register set (usbh20) */ 86 uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */ 87 uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */ 88 uint32 coresba2_size[SI_MAXCORES]; /* second address space size */ 89 90 void *curwrap; /* current wrapper va */ 91 void *wrappers[SI_MAXCORES]; /* other cores wrapper va */ 92 uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */ 93 94 uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */ 95 uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */ 96 uint32 oob_router; /* oob router registers for axi */ 97} si_info_t; 98 99#define SI_INFO(sih) (si_info_t *)(uintptr)sih 100 101#define GOODCOREADDR(x, b) (((x) >= (b)) && ((x) < ((b) + SI_MAXCORES * SI_CORE_SIZE)) && \ 102 ISALIGNED((x), SI_CORE_SIZE)) 103#define GOODREGS(regs) ((regs) != NULL && ISALIGNED((uintptr)(regs), SI_CORE_SIZE)) 104#define BADCOREADDR 0 105#define GOODIDX(idx) (((uint)idx) < SI_MAXCORES) 106#define NOREV -1 /* Invalid rev */ 107 108#define PCI(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 109 ((si)->pub.buscoretype == PCI_CORE_ID)) 110 111#define PCIE_GEN1(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 112 ((si)->pub.buscoretype == PCIE_CORE_ID)) 113 114#define PCIE_GEN2(si) ((BUSTYPE((si)->pub.bustype) == PCI_BUS) && \ 115 ((si)->pub.buscoretype == PCIE2_CORE_ID)) 116 117#define PCIE(si) (PCIE_GEN1(si) || PCIE_GEN2(si)) 118 119#define PCMCIA(si) ((BUSTYPE((si)->pub.bustype) == PCMCIA_BUS) && ((si)->memseg == TRUE)) 120 121/* Newer chips can access PCI/PCIE and CC core without requiring to change 122 * PCI BAR0 WIN 123 */ 124#define SI_FAST(si) (PCIE(si) || (PCI(si) && ((si)->pub.buscorerev >= 13))) 125 126#define PCIEREGS(si) (((char *)((si)->curmap) + PCI_16KB0_PCIREGS_OFFSET)) 127#define CCREGS_FAST(si) (((char *)((si)->curmap) + PCI_16KB0_CCREGS_OFFSET)) 128 129/* 130 * Macros to disable/restore function core(D11, ENET, ILINE20, etc) interrupts before/ 131 * after core switching to avoid invalid register accesss inside ISR. 132 */ 133#define INTR_OFF(si, intr_val) \ 134 if ((si)->intrsoff_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \ 135 intr_val = (*(si)->intrsoff_fn)((si)->intr_arg); } 136#define INTR_RESTORE(si, intr_val) \ 137 if ((si)->intrsrestore_fn && (si)->coreid[(si)->curidx] == (si)->dev_coreid) { \ 138 (*(si)->intrsrestore_fn)((si)->intr_arg, intr_val); } 139 140/* dynamic clock control defines */ 141#define LPOMINFREQ 25000 /* low power oscillator min */ 142#define LPOMAXFREQ 43000 /* low power oscillator max */ 143#define XTALMINFREQ 19800000 /* 20 MHz - 1% */ 144#define XTALMAXFREQ 20200000 /* 20 MHz + 1% */ 145#define PCIMINFREQ 25000000 /* 25 MHz */ 146#define PCIMAXFREQ 34000000 /* 33 MHz + fudge */ 147 148#define ILP_DIV_5MHZ 0 /* ILP = 5 MHz */ 149#define ILP_DIV_1MHZ 4 /* ILP = 1 MHz */ 150 151/* Force fast clock for 4360b0 */ 152#define PCI_FORCEHT(si) \ 153 (((PCIE_GEN1(si)) && (si->pub.chip == BCM4311_CHIP_ID) && ((si->pub.chiprev <= 1))) || \ 154 ((PCI(si) || PCIE_GEN1(si)) && (si->pub.chip == BCM4321_CHIP_ID)) || \ 155 (PCIE_GEN1(si) && (si->pub.chip == BCM4716_CHIP_ID)) || \ 156 (PCIE_GEN1(si) && (si->pub.chip == BCM4748_CHIP_ID))) 157 158/* GPIO Based LED powersave defines */ 159#define DEFAULT_GPIO_ONTIME 10 /* Default: 10% on */ 160#define DEFAULT_GPIO_OFFTIME 90 /* Default: 10% on */ 161 162#ifndef DEFAULT_GPIOTIMERVAL 163#define DEFAULT_GPIOTIMERVAL ((DEFAULT_GPIO_ONTIME << GPIO_ONTIME_SHIFT) | DEFAULT_GPIO_OFFTIME) 164#endif 165 166/* Silicon Backplane externs */ 167extern void sb_scan(si_t *sih, void *regs, uint devid); 168extern uint sb_coreid(si_t *sih); 169extern uint sb_intflag(si_t *sih); 170extern uint sb_flag(si_t *sih); 171extern void sb_setint(si_t *sih, int siflag); 172extern uint sb_corevendor(si_t *sih); 173extern uint sb_corerev(si_t *sih); 174extern uint sb_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 175extern bool sb_iscoreup(si_t *sih); 176extern void *sb_setcoreidx(si_t *sih, uint coreidx); 177extern uint32 sb_core_cflags(si_t *sih, uint32 mask, uint32 val); 178extern void sb_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 179extern uint32 sb_core_sflags(si_t *sih, uint32 mask, uint32 val); 180extern void sb_commit(si_t *sih); 181extern uint32 sb_base(uint32 admatch); 182extern uint32 sb_size(uint32 admatch); 183extern void sb_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 184extern void sb_core_disable(si_t *sih, uint32 bits); 185extern uint32 sb_addrspace(si_t *sih, uint asidx); 186extern uint32 sb_addrspacesize(si_t *sih, uint asidx); 187extern int sb_numaddrspaces(si_t *sih); 188 189extern uint32 sb_set_initiator_to(si_t *sih, uint32 to, uint idx); 190 191extern bool sb_taclear(si_t *sih, bool details); 192 193#ifdef BCMDBG 194extern void sb_view(si_t *sih, bool verbose); 195extern void sb_viewall(si_t *sih, bool verbose); 196#endif 197#if defined(BCMDBG) 198extern void sb_dumpregs(si_t *sih, struct bcmstrbuf *b); 199#endif 200 201/* Wake-on-wireless-LAN (WOWL) */ 202extern bool sb_pci_pmecap(si_t *sih); 203struct osl_info; 204extern bool sb_pci_fastpmecap(struct osl_info *osh); 205extern bool sb_pci_pmeclr(si_t *sih); 206extern void sb_pci_pmeen(si_t *sih); 207extern uint sb_pcie_readreg(void *sih, uint addrtype, uint offset); 208 209/* AMBA Interconnect exported externs */ 210extern si_t *ai_attach(uint pcidev, osl_t *osh, void *regs, uint bustype, 211 void *sdh, char **vars, uint *varsz); 212extern si_t *ai_kattach(osl_t *osh); 213extern void ai_scan(si_t *sih, void *regs, uint devid); 214 215extern uint ai_flag(si_t *sih); 216extern uint ai_flag_alt(si_t *sih); 217extern void ai_setint(si_t *sih, int siflag); 218extern uint ai_coreidx(si_t *sih); 219extern uint ai_corevendor(si_t *sih); 220extern uint ai_corerev(si_t *sih); 221extern bool ai_iscoreup(si_t *sih); 222extern void *ai_setcoreidx(si_t *sih, uint coreidx); 223extern uint32 ai_core_cflags(si_t *sih, uint32 mask, uint32 val); 224extern void ai_core_cflags_wo(si_t *sih, uint32 mask, uint32 val); 225extern uint32 ai_core_sflags(si_t *sih, uint32 mask, uint32 val); 226extern uint ai_corereg(si_t *sih, uint coreidx, uint regoff, uint mask, uint val); 227extern void ai_core_reset(si_t *sih, uint32 bits, uint32 resetbits); 228extern void ai_core_disable(si_t *sih, uint32 bits); 229extern int ai_numaddrspaces(si_t *sih); 230extern uint32 ai_addrspace(si_t *sih, uint asidx); 231extern uint32 ai_addrspacesize(si_t *sih, uint asidx); 232extern void ai_coreaddrspaceX(si_t *sih, uint asidx, uint32 *addr, uint32 *size); 233extern uint ai_wrap_reg(si_t *sih, uint32 offset, uint32 mask, uint32 val); 234 235#ifdef BCMDBG 236extern void ai_view(si_t *sih, bool verbose); 237extern void ai_viewall(si_t *sih, bool verbose); 238#endif 239#if defined(BCMDBG) 240extern void ai_dumpregs(si_t *sih, struct bcmstrbuf *b); 241#endif 242 243#ifdef SI_ENUM_BASE_VARIABLE 244extern void si_enum_base_init(si_t *sih, uint bustype); 245#endif /* SI_ENUM_BASE_VARIABLE */ 246 247#define ub_scan(a, b, c) do {} while (0) 248#define ub_flag(a) (0) 249#define ub_setint(a, b) do {} while (0) 250#define ub_coreidx(a) (0) 251#define ub_corevendor(a) (0) 252#define ub_corerev(a) (0) 253#define ub_iscoreup(a) (0) 254#define ub_setcoreidx(a, b) (0) 255#define ub_core_cflags(a, b, c) (0) 256#define ub_core_cflags_wo(a, b, c) do {} while (0) 257#define ub_core_sflags(a, b, c) (0) 258#define ub_corereg(a, b, c, d, e) (0) 259#define ub_core_reset(a, b, c) do {} while (0) 260#define ub_core_disable(a, b) do {} while (0) 261#define ub_numaddrspaces(a) (0) 262#define ub_addrspace(a, b) (0) 263#define ub_addrspacesize(a, b) (0) 264#define ub_view(a, b) do {} while (0) 265#define ub_dumpregs(a, b) do {} while (0) 266 267#endif /* _siutils_priv_h_ */ 268