1#include <arminc.h>
2#include <sbhndarm.h>
3#include <hndsoc.h>
4#include <ddr_core.h>
5#include <bcmnvram.h>
6#include <sbchipc.h>
7#include <chipcommonb.h>
8
9
10#ifndef __arm__
11#error __arm__ is NOT defined
12#endif
13
14/* Routine begin/end macro */
15#if defined(__thumb__)
16#define FUNC(x) THUMBLEAF(x)
17#else
18#define FUNC(x) LEAF(x)
19#endif  /* __thumb__ */
20
21	.text
22
23FUNC(ddr_init)
24	mov	r9,r0			/* ddr control register base */
25	mov	r8,r1
26	mov	r7,r2
27
28	/* ddr2 or ddr3 */
29	ldr	r3,=0x18108500
30	ldr	r0,[r3]
31	ldr	r2,=DDR_STAT_DDR3
32	and	r0,r0,r2
33	cmp	r0,r2
34	bne	chk_bootdev
35
36	/* Configure DDR3 voltage to 1.5V */
37	ldr	r1,=0x1800c02c
38	ldr	r2,=0x00000200
39	str	r2,[r1]
40	ldr	r3,[r1]
41	/* Enable LDO voltage output */
42	ldr	r1,=0x1800c020			/* pcu_aopc_control */
43	ldr	r2,=0x80000000
44	str	r2,[r1]
45	ldr	r3,[r1]
46	ldr	r2,=0x80000001
47	str	r2,[r1]
48	ldr	r3,[r1]
49	ldr	r4,=0x1800c024			/* pcu_status */
50	ldr	r3,[r4]
51	bic	r3,r3,#0xf
52	lsl	r3,r3,#1
53	ldr	r4,=0x1e
54	bic	r4,r4,r3
55	orr	r2,r2,r3
56	bic	r2,r2,#4
57	str	r2,[r1]
58	ldr	r3,[r1]
59
60chk_bootdev:
61	mov	r6,#0x0
62	ldr	r0,=SISF_NS_BOOTDEV_ROM
63	cmp	r0,r7
64	bne	find_flashnvram
65
66find_otpnvram:
67	ldr	r0,=SI_ENUM_BASE		/* r0:	core regs SI base address */
68	ldr	r4,[r0,#CC_CAPABILITIES]	/* r4:	capabitilies */
69	and	r4,r4,#CC_CAP_OTPSIZE
70	cmp	r4,#0
71	beq	find_flashnvram
72
73	/* Skip OTP initialization here since it was already done in pcie_phy_init */
74	lsr	r2,r4,#CC_CAP_OTPSIZE_SHIFT	/* Get OTP size */
75	adrl	r1,otp_sizes
76	lsl	r2,r2,#0x2
77	ldr	r3,[r1,r2]			/* Get the OTP size from otp_sizes table (in bytes) */
78
79	cmp	r3,#0x0				/* skip zero size */
80	beq	find_flashnvram
81	ldr	r1,[r0,#CC_OTPST]
82	and	r1,r1,#OTPS_READY
83	cmp	r1,#0x0				/* 0: OTP is not ready for whatever reason */
84	beq	find_flashnvram
85	add	r2,r3,r0			/* Seek to the end of OTP region */
86	/* Scan entire OTP from END -> BEGIN to find first
87	 * matching nvram entry */
88	sub	r2,r2,#2
891:
90	add	r4,r2,#CC_SROM_OTP
91	ldrh	r1,[r4]
92	lsl	r1,r1,#0x10
93	sub	r2,r2,#2
94	add	r4,r2,#CC_SROM_OTP
95	ldrh	r3,[r4]
96	orr	r1,r1,r3
97	ldr	r4,=NVRAM_MAGIC
98	cmp	r1,r4
99	beq	1f
100	cmp	r0,r2
101	blt	1b
102	b	find_flashnvram
103	/* no nvram from OTP */
104
105	/* Get sdram params from OTP 16bits at a time */
1061:
107	add	r2,r2,#12
108	add	r4,r2,#CC_SROM_OTP
109	ldrh	r1,[r4]
110	add	r2,r2,#2
111	add	r4,r2,#CC_SROM_OTP
112	ldrh	r3,[r4]
113	lsl	r3,r3,#0x10
114	orr	r6,r1,r3			/* sdram_config + sdram_rehash */
115	add	r2,r2,#2
116	add	r4,r2,#CC_SROM_OTP
117	ldrh	r1,[r4]
118	add	r2,r2,#2
119	add	r4,r2,#CC_SROM_OTP
120	ldrh	r3,[r4]
121	lsl	r3,r3,#0x10
122	orr	r5,r1,r3			/* sdram_ncdl */
123
124find_flashnvram:
125	ldr	r0,=SI_NS_NANDFLASH
126	ldr	r1,=SISF_NS_BOOTDEV_NAND
127	cmp	r1,r7
128	beq	nand_embedded_nv
129
130	ldr	r0,=SI_NS_NORFLASH
131	ldr	r1,=MAX_NVRAM_SPACE
132	sub	r0,r0,r1
133	ldr	r1,=FLASH_MIN
134	ldr	r2,=SI_NS_FLASH_WINDOW
135	ldr	r3,=NVRAM_MAGIC
136
1371:	add	r4,r0,r1
138	ldr	r8,[r4]
139	cmp	r8,r3
140	beq	read_config
141	lsl	r1,r1,#1
142	cmp	r1,r2
143	ble	1b
144
145	/* Try embedded NVRAM at 4KB and 1KB as last resorts */
146	ldr	r0,=SI_NS_NORFLASH
147nand_embedded_nv:
148	add	r4,r0,#0x1000
149	ldr	r8,[r4]
150	cmp	r8,r3
151	beq	read_config
152
153	add	r4,r0,#0x400
154	ldr	r8,[r4]
155	cmp	r8,r3
156	beq	read_config
157
1582:	ldr	r0,=0x0			/* if we have sdram params from OTP then use it */
159	cmp	r6,r0
160	bne	set_ddr_clock
161
162no_sdram_params:
163	ldr	r6,=0x0
164	ldr	r5,=0x0
165	b	set_ddr_clock
166
167read_config:
168	ldr	r6,[r4,#12]		/* Pick up sdram_config & sdram_refresh */
169	ldr	r5,[r4,#16]		/* Pick up sdram_ncdl */
170
171set_ddr_clock:
172	ldr	r0,=DDRC00_START
173	ldr	r1,[r9,#DDRC_CONTROL00]
174	and	r1,r1,r0
175	cmp	r1,r0
176	bne	init_ddrphy		/* The first time */
177	ldr	r1,=0x1000
178	ldr	r0,=BISZ_OFFSET
179	add	r1,r1,r0
180	sub	r1,r1,#4
181	ldr	r0,=0x0
182	ldr	r2,[r1]
183	cmp	r2,r0
184	beq	init_ddrphy		/* No ddrclk specified */
185
186	ldr	r3,=DDR_TABLE_END
187	adrl	r4,ddr_clk_tab
1881:	ldr	r1,[r4]
189	cmp	r1,r3
190	beq	init_ddrphy
191	cmp	r1,r2
192	beq	chg_ddr_clock
193	add	r4,r4,#12
194	b	1b
195
196chg_ddr_clock:
197	/* Put the controller to reset mode first */
198	ldr	r1,=0x18108800
199	ldr	r2,=0x00000001
200	str	r2,[r1]
201	ldr	r1,=0x18109800
202	str	r2,[r1]
203
204	ldr	r0,=CRU_CLKSET_KEY
205	ldr	r1,=0xea68
206	str	r1,[r0]
207
208	ldr	r0,=LCPLL_NDIV_INT
209	ldr	r1,[r0]
210	ldr	r2,=0xf00fffff
211	and	r1,r1,r2
212	ldr	r2,[r4,#4]
213	orr	r1,r1,r2
214	str	r1,[r0]
215	ldr	r0,=LCPLL_CHX_MDIV
216	ldr	r1,[r0]
217	ldr	r2,=0x000000ff
218	and	r1,r1,r2
219	ldr	r2,[r4,#8]
220	orr	r1,r1,r2
221	str	r1,[r0]
222
223en_change:
224	ldr	r0,=LCPLL_LOAD_EN_CH
225	ldr	r1,[r0]
226	orr	r1,r1,#0x7
227	str	r1,[r0]
228	and	r1,r1,#0xfffffff8
229	str	r1,[r0]
230	ldr	r0,=CRU_CLKSET_KEY
231	ldr	r1,=0x0
232	str	r1,[r0]
233
234init_ddrphy:
235	mov	r8,r9		/* save r9 */
236
237	ldr	r1,=0x18108800
238	ldr	r2,=0x00000000
239	str	r2,[r1]
240	ldr	r1,=0x18109800
241	str	r2,[r1]
242
243	ldr	r1,=0x18108408
244	ldr	r2,[r1]
245	ldr	r3,=0xf000ffff
246	and	r2,r2,r3
247	orr	r2,r2,#0x01900000
248	str	r2,[r1]
249
250	ldr	r9,=0x18010800
251	ldr	r1,=0x0
252	ldr	r3,=0x00019000
253
254wait_for_ddr_phy_up:
255	cmp	r3,r1
256	beq	ddr_phy_rdy
257	sub	r3,r3,#0x1
258	ldr	r2,=0x0
259	ldr	r2,[r9]
260	cmp	r2,r1
261	bne	ddr_phy_rdy
262	b	wait_for_ddr_phy_up
263ddr_phy_rdy:
264
265	/* Change PLL divider values inside PHY */
266	ldr	r1,=0x1801081c
267	ldr	r2,=0x00000c10
268	str	r2,[r1]
269	ldr	r3,[r9]
270
271	ldr	r1,=0x18010814
272	ldr	r2,=0x00000010
273	str	r2,[r1]
274	ldr	r3,[r9]
275
276	ldr	r4,=0x18010810
277	ldr	r1,=0x1
278	ldr	r3,=0x00001400
279
280wait_for_ddr_phy_pll_lock:
281	cmp	r3,r1
282	beq	ddr_phy_pll_lock_done
283	sub	r3,r3,#0x1
284	ldr	r2,=0x0
285	ldr	r2,[r4]
286	and	r2,r2,#0x1
287	cmp	r2,r1
288	beq	ddr_phy_pll_lock_done
289	b	wait_for_ddr_phy_pll_lock
290ddr_phy_pll_lock_done:
291
292	ldr	r1,=0x18010b60
293	ldr	r2,=0x00000003
294	str	r2,[r1]
295	ldr	r3,[r9]
296
297	/* Write 2 if ddr2, 3 if ddr3 */
298	ldr	r1,=0x18108500
299	ldr	r3,[r1]
300	ldr	r2,=0x00000001
301	and	r3,r2,r3
302	orr	r2,r3,#0x2
303	ldr	r1,=0x18010bac
304	str	r2,[r1]
305	ldr	r3,[r9]
306
307	ldr	r1,=0x1801083c
308	ldr	r2,=0x00100000
309	str	r2,[r1]
310	ldr	r3,[r9]
311
312	ldr	r1,=0x18010848
313	ldr	r2,=0x08000101
314	str	r2,[r1]
315	ldr	r3,[r9]
316
317	ldr	r4,=0x1801084C
318	ldr	r1,=0x1
319	ldr	r3,=0x00001400
320
321wait_for_ddr_phy_calib_lock:
322	cmp	r3,r1
323	beq	ddr_phy_calib_lock_done
324	sub	r3,r3,#0x1
325	ldr	r2,=0x0
326	ldr	r2,[r4]
327	and	r2,r2,#0x1
328	cmp	r2,r1
329	beq	ddr_phy_calib_lock_done
330	b	wait_for_ddr_phy_calib_lock
331ddr_phy_calib_lock_done:
332
333	ldr	r4,=0x1801084C
334	ldr	r1,=0x2
335	ldr	r2,[r4]
336	and	r2,r2,#0x2
337	cmp	r2,r1
338	beq	ddr_cntrl_prog
339
340calib_override:
341	ldr	r1,=0x18010834
342	ldr	r2,=0x0001003f
343	str	r2,[r1]
344	ldr	r3,[r9]
345
346	ldr	r1,=0x18010a04
347	ldr	r2,=0x0003003f
348	str	r2,[r1]
349	ldr	r3,[r9]
350
351	ldr	r1,=0x18010a10
352	ldr	r2,=0x0003003f
353	str	r2,[r1]
354	ldr	r3,[r9]
355
356	ldr	r1,=0x18010a14
357	ldr	r2,=0x0003003f
358	str	r2,[r1]
359	ldr	r3,[r9]
360
361	ldr	r1,=0x18010a18
362	ldr	r2,=0x0003003f
363	str	r2,[r1]
364	ldr	r3,[r9]
365
366	ldr	r1,=0x18010a1c
367	ldr	r2,=0x0003003f
368	str	r2,[r1]
369	ldr	r3,[r9]
370
371	ldr	r1,=0x18010a20
372	ldr	r2,=0x0003003f
373	str	r2,[r1]
374	ldr	r3,[r9]
375
376	ldr	r1,=0x18010a24
377	ldr	r2,=0x0003003f
378	str	r2,[r1]
379	ldr	r3,[r9]
380
381	ldr	r1,=0x18010a28
382	ldr	r2,=0x0003003f
383	str	r2,[r1]
384	ldr	r3,[r9]
385
386	ldr	r1,=0x18010a2c
387	ldr	r2,=0x0003003f
388	str	r2,[r1]
389	ldr	r3,[r9]
390
391	ldr	r1,=0x18010a30
392	ldr	r2,=0x0003003f
393	str	r2,[r1]
394	ldr	r3,[r9]
395
396	ldr	r1,=0x18010aa4
397	ldr	r2,=0x0003003f
398	str	r2,[r1]
399	ldr	r3,[r9]
400
401	ldr	r1,=0x18010ab0
402	ldr	r2,=0x0003003f
403	str	r2,[r1]
404	ldr	r3,[r9]
405
406	ldr	r1,=0x18010ab4
407	ldr	r2,=0x0003003f
408	str	r2,[r1]
409	ldr	r3,[r9]
410
411	ldr	r1,=0x18010ab8
412	ldr	r2,=0x0003003f
413	str	r2,[r1]
414	ldr	r3,[r9]
415
416	ldr	r1,=0x18010abc
417	ldr	r2,=0x0003003f
418	str	r2,[r1]
419	ldr	r3,[r9]
420
421	ldr	r1,=0x18010ac0
422	ldr	r2,=0x0003003f
423	str	r2,[r1]
424	ldr	r3,[r9]
425
426	ldr	r1,=0x18010ac4
427	ldr	r2,=0x0003003f
428	str	r2,[r1]
429	ldr	r3,[r9]
430
431	ldr	r1,=0x18010ac8
432	ldr	r2,=0x0003003f
433	str	r2,[r1]
434	ldr	r3,[r9]
435
436	ldr	r1,=0x18010acc
437	ldr	r2,=0x0003003f
438	str	r2,[r1]
439	ldr	r3,[r9]
440
441	ldr	r1,=0x18010ad0
442	ldr	r2,=0x0003003f
443	str	r2,[r1]
444	ldr	r3,[r9]
445
446	ldr	r1,=0x18010a08
447	ldr	r2,=0x0003003f
448	str	r2,[r1]
449	ldr	r3,[r9]
450
451	ldr	r1,=0x18010a0c
452	ldr	r2,=0x0003003f
453	str	r2,[r1]
454	ldr	r3,[r9]
455
456	ldr	r1,=0x18010aa8
457	ldr	r2,=0x0003003f
458	str	r2,[r1]
459	ldr	r3,[r9]
460
461	ldr	r1,=0x18010aac
462	ldr	r2,=0x0003003f
463	str	r2,[r1]
464	ldr	r3,[r9]
465
466ddr_cntrl_prog:
467
468	/* correct Vtt voltage */
469	ldr	r1,=0x18010864
470	ldr	r2,=0x01d7ffff
471	str	r2,[r1]
472	ldr	r3,[r9]
473
474	ldr	r1,=0x18010868
475	str	r2,[r1]
476	ldr	r3,[r9]
477
478	mov	r9,r8		/* restore r9 */
479
480init_regs:
481
482	/* ddr2 or ddr3 */
483	ldr	r8,=0x18108500
484	ldr	r0,[r8]
485	ldr	r2,=DDR_STAT_DDR3
486	and	r0,r0,r2
487	cmp	r0,r2
488	beq	ddr3_init
489
490ddr2_init:
491	mov	ip,lr			/* save lr across calls */
492	adrl	r0,ddr2_init_tab
493	bl	ddr_init_regs
494	mov	lr,ip			/* restore lr */
495	b	chparams
496
497ddr3_init:
498	mov	ip,lr			/* save lr across calls */
499	adrl	r0,ddr3_init_tab
500	bl	ddr_init_regs
501	mov	lr,ip			/* restore lr */
502
503chparams:
504	ldr	r0,=0x0
505	cmp	r6,r0
506	beq	turnon			/* No sdram params, use default values */
507
508chtref:
509	lsr	r2,r6,#16
510	cmp	r2,r0
511	beq	chhalf
512	ldr	r1,[r9,#DDRC_CONTROL21]
513	ldr	r3,=0x3fff
514	bic	r1,r1,r3
515	orr	r1,r1,r2
516	str	r1,[r9,#DDRC_CONTROL21]
517	ldr	r1,[r9,#DDRC_CONTROL22]
518	ldr	r3,=0x3fff
519	bic	r1,r1,r3
520	orr	r1,r1,r2
521	str	r1,[r9,#DDRC_CONTROL22]
522
523chhalf:
524	ldr	r1,=0x80
525	and	r1,r1,r6
526	cmp	r1,r0
527	beq	ch8banks
528setreduc:
529	ldr	r1,[r9,#DDRC_CONTROL87]
530	ldr	r2,=0x00000100
531	orr	r1,r1,r2
532	str	r1,[r9,#DDRC_CONTROL87]
533
534ch8banks:
535	ldr	r1,=0x40
536	and	r1,r1,r6
537	cmp	r1,r0
538	beq	do4banks
539do8banks:
540	ldr	r1,[r9,#DDRC_CONTROL82]
541	ldr	r2,=~0x00000300
542	and	r1,r1,r2
543	str	r1,[r9,#DDRC_CONTROL82]
544	b	docols
545do4banks:
546	ldr	r1,[r9,#DDRC_CONTROL82]
547	ldr	r2,=~0x00000300
548	and	r1,r1,r2
549	ldr	r2,=0x00000100
550	orr	r1,r1,r2
551	str	r1,[r9,#DDRC_CONTROL82]
552
553docols:
554	ldr	r1,[r9,#DDRC_CONTROL82]
555	ldr	r2,=~0x07070000
556	and	r1,r1,r2
557	ldr	r2,=0x700
558	and	r2,r2,r6
559	lsl	r2,r2,#16
560	orr	r1,r1,r2
561	str	r1,[r9,#DDRC_CONTROL82]
562
563docaslat:
564	ldr	r0,=0x1f
565	and	r0,r0,r6		/* cas latency */
566	sub	r1,r0,#1		/* wrlat */
567	cmp	r0,#6
568	blt	1f
569	sub	r1,r0,#4
570	lsr	r1,r1,#1
571	sub	r1,r0,r1		/* wrlat */
5721:
573	ldr	r2,[r9,#DDRC_CONTROL05]
574	ldr	r3,=~0x3f1f3f00
575	and	r2,r2,r3
576	lsl	r3,r0,#9		/* cas << 9 */
577	orr	r2,r2,r3
578	lsl	r3,r0,#25		/* cas << 25 */
579	orr	r2,r2,r3
580	lsl	r3,r1,#16		/* wrlat << 16 */
581	orr	r2,r2,r3
582	str	r2,[r9,#DDRC_CONTROL05]
583	ldr	r2,[r9,#DDRC_CONTROL06]
584	ldr	r3,=~0x0000001f
585	and	r2,r2,r3
586	orr	r2,r2,r1
587	str	r2,[r9,#DDRC_CONTROL06]
588
589	ldr	r2,[r9,#DDRC_CONTROL174]
590	ldr	r3,=~0x00001f3f
591	and	r2,r2,r3
592	lsl	r3,r1,#8
593	orr	r2,r2,r3
594	sub	r3,r0,#1
595	orr	r2,r2,r3
596	str	r2,[r9,#DDRC_CONTROL174]
597
598	ldr	r2,[r9,#DDRC_CONTROL44]
599	ldr	r3,=~0x0000f000
600	and	r2,r2,r3
601	mov	r3,r0
602	lsl	r3,r3,#12
603	orr	r2,r2,r3
604	str	r2,[r9,#DDRC_CONTROL44]
605
606	ldr	r2,[r9,#DDRC_CONTROL186]
607	ldr	r3,=~0xff000000
608	and	r2,r2,r3
609	add	r3,r0,#17
610	lsl	r3,r3,#24
611	orr	r2,r2,r3
612	str	r2,[r9,#DDRC_CONTROL186]
613
614	ldr	r8,=0x18108500
615	ldr	r3,[r8]
616	ldr	r2,=DDR_STAT_DDR3
617	and	r3,r3,r2
618	cmp	r3,r2
619	bne	turnon
620
621	ldr	r2,[r9,#DDRC_CONTROL44]
622	ldr	r3,=~0x0000f000
623	and	r2,r2,r3
624	sub	r3,r0,#4
625	lsl	r3,r3,#12
626	orr	r2,r2,r3
627	str	r2,[r9,#DDRC_CONTROL44]
628	ldr	r2,[r9,#DDRC_CONTROL45]
629	ldr	r3,=~0x00380000
630	and	r2,r2,r3
631	sub	r3,r0,#8
632	cmp	r0,#9
633	bgt	1f
634	sub	r3,r0,#7
635	cmp	r0,#7
636	bgt	1f
637	sub	r3,r0,#6
6381:
639	lsl	r3,r3,#19
640	orr	r2,r2,r3
641	str	r2,[r9,#DDRC_CONTROL45]
642
643	ldr	r2,[r9,#DDRC_CONTROL206]
644	ldr	r3,=~0x00001f00
645	and	r2,r2,r3
646	sub	r3,r1,#1
647	lsl	r3,r3,#8
648	orr	r2,r2,r3
649	str	r2,[r9,#DDRC_CONTROL206]
650
651turnon:
652	ldr	r0,=DDRC00_START
653	ldr	r1,[r9,#DDRC_CONTROL00]
654	orr	r1,r1,r0
655	str	r1,[r9,#DDRC_CONTROL00]
656
657poll_ddr_ctrl:
658	ldr	r0,[r9,#DDRC_CONTROL89]
659	ldr	r2,=DDR_INT_INIT_DONE
660	and	r0,r2,r0
661	cmp	r0,r2
662	bne	poll_ddr_ctrl
663
664	ldr	r1,=0x18010b60
665	ldr	r2,=0x00000003
666	str	r2,[r1]
667	ldr	r3,[r9]
668
669	ldr	r1,=0x18010a00
670	ldr	r2,=0x00010120
671	str	r2,[r1]
672	ldr	r3,[r9]
673
674	ldr	r1,=0x18010a74
675	ldr	r2,=0x0001000d
676	str	r2,[r1]
677	ldr	r3,[r9]
678
679	ldr	r1,=0x18010b14
680	ldr	r2,=0x00010020
681	str	r2,[r1]
682	ldr	r3,[r9]
683
684	mov	pc,lr
685	.ltorg
686
687	.align 4
688ddr_clk_tab:
689	.word	333,	0x07800000,	0x1e0f1200
690	.word	389,	0x08c00000,	0x23121200
691	.word	400,	0x08000000,	0x20101000
692	.word	533,	0x08000000,	0x20100c00
693	.word	666,	0x07800000,	0x1e0f0900
694	.word	775,	0x07c00000,	0x20100800
695	.word	800,	0x08000000,	0x20100800
696	.word	DDR_TABLE_END
697
698	.align 4
699ddr2_init_tab:
700	.word	0,	0x00000400
701	.word	1,	0x00000000
702	.word	3,	0x00000050
703	.word	4,	0x000000c8
704	.word	5,	0x0c050c02
705	.word	6,	0x04020405
706	.word	7,	0x05031015
707	.word	8,	0x03101504
708	.word	9,	0x05020305
709	.word	10,	0x03006d60
710	.word	11,	0x05020303
711	.word	12,	0x03006d60
712	.word	13,	0x01000003
713	.word	14,	0x05061001
714	.word	15,	0x000b0b06
715	.word	16,	0x030000c8
716	.word	17,	0x00a01212
717	.word	18,	0x060600a0
718	.word	19,	0x00000000
719	.word	20,	0x00003001
720	.word	21,	0x00300c2d
721	.word	22,	0x00050c2d
722	.word	23,	0x00000200
723	.word	24,	0x000a0002
724	.word	25,	0x0002000a
725	.word	26,	0x00020008
726	.word	27,	0x00c80008
727	.word	28,	0x00c80037
728	.word	29,	0x00000037
729	.word	30,	0x03000001
730	.word	31,	0x00030303
731	.word	36,	0x01000000
732	.word	37,	0x10000000
733	.word	38,	0x00100400
734	.word	39,	0x00000400
735	.word	40,	0x00000100
736	.word	41,	0x00000000
737	.word	42,	0x00000001
738	.word	43,	0x00000000
739	.word	44,	0x000a6300
740	.word	45,	0x00000004
741	.word	46,	0x00040a63
742	.word	47,	0x00000000
743	.word	48,	0x0a630000
744	.word	49,	0x00000004
745	.word	50,	0x00040a63
746	.word	51,	0x00000000
747	.word	52,	0x0a630000
748	.word	53,	0x00000004
749	.word	54,	0x00040a63
750	.word	55,	0x00000000
751	.word	56,	0x0a630000
752	.word	57,	0x00000004
753	.word	58,	0x00040a63
754	.word	59,	0x00000000
755	.word	60,	0x00000000
756	.word	61,	0x00010100
757	.word	78,	0x01000200
758	.word	79,	0x02000040
759	.word	80,	0x00400100
760	.word	81,	0x00000200
761	.word	82,	0x01030001
762	.word	83,	0x01ffff0a
763	.word	84,	0x01010101
764	.word	85,	0x03010101
765	.word	86,	0x01000003
766	.word	87,	0x0000010c
767	.word	88,	0x00010000
768	.word	108,	0x02020101
769	.word	109,	0x08080404
770	.word	110,	0x03020200
771	.word	111,	0x01000202
772	.word	112,	0x00000200
773	.word	116,	0x19000000
774	.word	117,	0x00000028
775	.word	118,	0x00000000
776	.word	119,	0x00010001
777	.word	120,	0x00010001
778	.word	121,	0x00010001
779	.word	122,	0x00010001
780	.word	123,	0x00010001
781	.word	128,	0x001c1c00
782	.word	129,	0x1c1c0001
783	.word	130,	0x00000001
784	.word	133,	0x00011c1c
785	.word	134,	0x00011c1c
786	.word	137,	0x001c1c00
787	.word	138,	0x1c1c0001
788	.word	139,	0x00000001
789	.word	142,	0x00011c1c
790	.word	143,	0x00011c1c
791	.word	144,	0x00000000
792	.word	145,	0x00000000
793	.word	146,	0x001c1c00
794	.word	147,	0x1c1c0001
795	.word	148,	0xffff0001
796	.word	149,	0x00ffff00
797	.word	150,	0x0000ffff
798	.word	151,	0x00000000
799	.word	152,	0x03030303
800	.word	153,	0x03030303
801	.word	156,	0x02006400
802	.word	157,	0x02020202
803	.word	158,	0x02020202
804	.word	160,	0x01020202
805	.word	161,	0x01010064
806	.word	162,	0x01010101
807	.word	163,	0x01010101
808	.word	165,	0x00020101
809	.word	166,	0x00000064
810	.word	167,	0x00000000
811	.word	168,	0x000a0a00
812	.word	169,	0x0c2d0000
813	.word	170,	0x02000200
814	.word	171,	0x02000200
815	.word	172,	0x00000c2d
816	.word	173,	0x00003ce1
817	.word	174,	0x0c2d0505
818	.word	175,	0x02000200
819	.word	176,	0x02000200
820	.word	177,	0x00000c2d
821	.word	178,	0x00003ce1
822	.word	179,	0x02020505
823	.word	180,	0x80000100
824	.word	181,	0x04070303
825	.word	182,	0x0000000a
826	.word	185,	0x0010ffff
827	.word	186,	0x16070303
828	.word	187,	0x0000000f
829	.word	194,	0x00000204
830	.word	202,	0x00000050
831	.word	203,	0x00000050
832	.word	204,	0x00000000
833	.word	205,	0x00000040
834	.word	206,	0x01030301
835	.word	207,	0x00000001
836	.word	DDR_TABLE_END
837
838	.align 4
839ddr3_init_tab:
840	.word	0,	0x00000600
841	.word	1,	0x00000000
842	.word	3,	0x000000a0
843	.word	4,	0x00061a80
844	.word	5,	0x16081600
845	.word	6,	0x06040408
846	.word	7,	0x0b061c27
847	.word	8,	0x061c2706
848	.word	9,	0x0c04060b
849	.word	10,	0x0400db60
850	.word	11,	0x0c040604
851	.word	12,	0x0400db60
852	.word	13,	0x01000004
853	.word	14,	0x0b0c1001
854	.word	15,	0x0017170c
855	.word	16,	0x03000200
856	.word	17,	0x00002020
857	.word	18,	0x0b0b0000
858	.word	19,	0x00000000
859	.word	20,	0x00011801
860	.word	21,	0x01181858
861	.word	22,	0x00051858
862	.word	23,	0x00000500
863	.word	24,	0x00140005
864	.word	25,	0x00000014
865	.word	26,	0x00000000
866	.word	27,	0x02000000
867	.word	28,	0x02000120
868	.word	29,	0x00000120
869	.word	30,	0x08000001
870	.word	31,	0x00080808
871	.word	32,	0x00000000
872	.word	35,	0x00000000
873	.word	36,	0x01000000
874	.word	37,	0x10000000
875	.word	38,	0x00100400
876	.word	39,	0x00000400
877	.word	40,	0x00000100
878	.word	41,	0x00000000
879	.word	42,	0x00000001
880	.word	43,	0x00000000
881	.word	44,	0x000c7000
882	.word	45,	0x00180046
883	.word	46,	0x00460c70
884	.word	47,	0x00000018
885	.word	48,	0x0c700000
886	.word	49,	0x00180046
887	.word	50,	0x00460c70
888	.word	51,	0x00000018
889	.word	52,	0x0c700000
890	.word	53,	0x00180046
891	.word	54,	0x00460c70
892	.word	55,	0x00000018
893	.word	56,	0x0c700000
894	.word	57,	0x00180046
895	.word	58,	0x00460c70
896	.word	59,	0x00000018
897	.word	60,	0x00000000
898	.word	61,	0x00010100
899	.word	62,	0x00000000
900	.word	63,	0x00000000
901	.word	64,	0x00000000
902	.word	65,	0x00000000
903	.word	66,	0x00000000
904	.word	67,	0x00000000
905	.word	68,	0x00000000
906	.word	69,	0x00000000
907	.word	70,	0x00000000
908	.word	71,	0x00000000
909	.word	72,	0x00000000
910	.word	73,	0x00000000
911	.word	74,	0x00000000
912	.word	75,	0x00000000
913	.word	76,	0x00000000
914	.word	77,	0x00000000
915	.word	78,	0x01000200
916	.word	79,	0x02000040
917	.word	80,	0x00400100
918	.word	81,	0x00000200
919	.word	82,	0x01000001
920	.word	83,	0x01ffff0a
921	.word	84,	0x01010101
922	.word	85,	0x03010101
923	.word	86,	0x01000003
924	.word	87,	0x0000010c
925	.word	88,	0x00010000
926	.word	89,	0x00000000
927	.word	90,	0x00000000
928	.word	91,	0x00000000
929	.word	92,	0x00000000
930	.word	93,	0x00000000
931	.word	94,	0x00000000
932	.word	95,	0x00000000
933	.word	96,	0x00000000
934	.word	97,	0x00000000
935	.word	98,	0x00000000
936	.word	99,	0x00000000
937	.word	100,	0x00000000
938	.word	101,	0x00000000
939	.word	102,	0x00000000
940	.word	103,	0x00000000
941	.word	104,	0x00000000
942	.word	105,	0x00000000
943	.word	106,	0x00000000
944	.word	107,	0x00000000
945	.word	108,	0x02040108
946	.word	109,	0x08010402
947	.word	110,	0x02020202
948	.word	111,	0x01000201
949	.word	112,	0x00000200
950	.word	113,	0x00000000
951	.word	114,	0x00000000
952	.word	115,	0x00000000
953	.word	116,	0x19000000
954	.word	117,	0x00000028
955	.word	118,	0x00000000
956	.word	119,	0x00010001
957	.word	120,	0x00010001
958	.word	121,	0x00010001
959	.word	122,	0x00010001
960	.word	123,	0x00010001
961	.word	124,	0x00000000
962	.word	125,	0x00000000
963	.word	126,	0x00000000
964	.word	127,	0x00000000
965	.word	128,	0x00232300
966	.word	129,	0x23230001
967	.word	130,	0x00000001
968	.word	131,	0x00000000
969	.word	132,	0x00000000
970	.word	133,	0x00012323
971	.word	134,	0x00012323
972	.word	135,	0x00000000
973	.word	136,	0x00000000
974	.word	137,	0x00232300
975	.word	138,	0x23230001
976	.word	139,	0x00000001
977	.word	140,	0x00000000
978	.word	141,	0x00000000
979	.word	142,	0x00012323
980	.word	143,	0x00012323
981	.word	144,	0x00000000
982	.word	145,	0x00000000
983	.word	146,	0x00232300
984	.word	147,	0x23230001
985	.word	148,	0xffff0001
986	.word	149,	0x00ffff00
987	.word	150,	0x0000ffff
988	.word	151,	0x00000000
989	.word	152,	0x03030303
990	.word	153,	0x03030303
991	.word	156,	0x02006400
992	.word	157,	0x02020202
993	.word	158,	0x02020202
994	.word	160,	0x01020202
995	.word	161,	0x01010064
996	.word	162,	0x01010101
997	.word	163,	0x01010101
998	.word	165,	0x00020101
999	.word	166,	0x00000064
1000	.word	167,	0x00000000
1001	.word	168,	0x000b0b00
1002	.word	169,	0x18580000
1003	.word	170,	0x02000200
1004	.word	171,	0x02000200
1005	.word	172,	0x00001858
1006	.word	173,	0x000079b8
1007	.word	174,	0x1858080a
1008	.word	175,	0x02000200
1009	.word	176,	0x02000200
1010	.word	177,	0x00001858
1011	.word	178,	0x000079b8
1012	.word	179,	0x0202080a
1013	.word	180,	0x80000100
1014	.word	181,	0x04070303
1015	.word	182,	0x0000000a
1016	.word	183,	0x00000000
1017	.word	184,	0x00000000
1018	.word	185,	0x0010ffff
1019	.word	186,	0x1c070303
1020	.word	187,	0x0000000f
1021	.word	188,	0x00000000
1022	.word	189,	0x00000000
1023	.word	190,	0x00000000
1024	.word	191,	0x00000000
1025	.word	192,	0x00000000
1026	.word	193,	0x00000000
1027	.word	194,	0x00000204
1028	.word	195,	0x00000000
1029	.word	196,	0x00000000
1030	.word	197,	0x00000000
1031	.word	198,	0x00000000
1032	.word	199,	0x00000000
1033	.word	200,	0x00000000
1034	.word	201,	0x00000000
1035	.word	202,	0x00000008
1036	.word	203,	0x00000008
1037	.word	204,	0x00000000
1038	.word	205,	0x00000040
1039	.word	206,	0x00070701
1040	.word	207,	0x00000000
1041	.word	DDR_TABLE_END
1042
1043/* OTP sizes in bytes */
1044otp_sizes:
1045	.word	0
1046	.word	256	/* 2048 bits: 32X64 */
1047	.word	512	/* 4096 bits: 2*32X64 */
1048	.word	1024	/* 8192 bits: 4*32X64 */
1049	.word	512	/* 4096 bits: 64X64 */
1050	.word	768	/* 6144 bits: 5 32X64 */
1051	.word	0	/* 512 bits: dont care */
1052	.word	128	/* 1024 bits: 8X64 */
1053
1054END(ddr_init)
1055
1056
1057FUNC(ddr_init_regs)
1058	mov	r2,r0
1059	ldr	r3,=DDR_TABLE_END
10601:	ldr	r4,[r2]
1061	cmp	r4,r3
1062	beq	2f
1063	ldr	r5,[r2,#4]
1064	lsl	r4,r4,#2
1065	add	r1,r9,r4
1066	str	r5,[r1]
1067	add	r2,r2,#8
1068	b	1b
10692:
1070	mov	pc,lr
1071END(ddr_init_regs)
1072