1/* Simulator instruction semantics for crisv32f. 2 3THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5Copyright 1996-2005 Free Software Foundation, Inc. 6 7This file is part of the GNU simulators. 8 9This program is free software; you can redistribute it and/or modify 10it under the terms of the GNU General Public License as published by 11the Free Software Foundation; either version 3 of the License, or 12(at your option) any later version. 13 14This program is distributed in the hope that it will be useful, 15but WITHOUT ANY WARRANTY; without even the implied warranty of 16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17GNU General Public License for more details. 18 19You should have received a copy of the GNU General Public License 20along with this program. If not, see <http://www.gnu.org/licenses/>. 21 22*/ 23 24#ifdef DEFINE_LABELS 25 26 /* The labels have the case they have because the enum of insn types 27 is all uppercase and in the non-stdc case the insn symbol is built 28 into the enum name. */ 29 30 static struct { 31 int index; 32 void *label; 33 } labels[] = { 34 { CRISV32F_INSN_X_INVALID, && case_sem_INSN_X_INVALID }, 35 { CRISV32F_INSN_X_AFTER, && case_sem_INSN_X_AFTER }, 36 { CRISV32F_INSN_X_BEFORE, && case_sem_INSN_X_BEFORE }, 37 { CRISV32F_INSN_X_CTI_CHAIN, && case_sem_INSN_X_CTI_CHAIN }, 38 { CRISV32F_INSN_X_CHAIN, && case_sem_INSN_X_CHAIN }, 39 { CRISV32F_INSN_X_BEGIN, && case_sem_INSN_X_BEGIN }, 40 { CRISV32F_INSN_MOVE_B_R, && case_sem_INSN_MOVE_B_R }, 41 { CRISV32F_INSN_MOVE_W_R, && case_sem_INSN_MOVE_W_R }, 42 { CRISV32F_INSN_MOVE_D_R, && case_sem_INSN_MOVE_D_R }, 43 { CRISV32F_INSN_MOVEQ, && case_sem_INSN_MOVEQ }, 44 { CRISV32F_INSN_MOVS_B_R, && case_sem_INSN_MOVS_B_R }, 45 { CRISV32F_INSN_MOVS_W_R, && case_sem_INSN_MOVS_W_R }, 46 { CRISV32F_INSN_MOVU_B_R, && case_sem_INSN_MOVU_B_R }, 47 { CRISV32F_INSN_MOVU_W_R, && case_sem_INSN_MOVU_W_R }, 48 { CRISV32F_INSN_MOVECBR, && case_sem_INSN_MOVECBR }, 49 { CRISV32F_INSN_MOVECWR, && case_sem_INSN_MOVECWR }, 50 { CRISV32F_INSN_MOVECDR, && case_sem_INSN_MOVECDR }, 51 { CRISV32F_INSN_MOVSCBR, && case_sem_INSN_MOVSCBR }, 52 { CRISV32F_INSN_MOVSCWR, && case_sem_INSN_MOVSCWR }, 53 { CRISV32F_INSN_MOVUCBR, && case_sem_INSN_MOVUCBR }, 54 { CRISV32F_INSN_MOVUCWR, && case_sem_INSN_MOVUCWR }, 55 { CRISV32F_INSN_ADDQ, && case_sem_INSN_ADDQ }, 56 { CRISV32F_INSN_SUBQ, && case_sem_INSN_SUBQ }, 57 { CRISV32F_INSN_CMP_R_B_R, && case_sem_INSN_CMP_R_B_R }, 58 { CRISV32F_INSN_CMP_R_W_R, && case_sem_INSN_CMP_R_W_R }, 59 { CRISV32F_INSN_CMP_R_D_R, && case_sem_INSN_CMP_R_D_R }, 60 { CRISV32F_INSN_CMP_M_B_M, && case_sem_INSN_CMP_M_B_M }, 61 { CRISV32F_INSN_CMP_M_W_M, && case_sem_INSN_CMP_M_W_M }, 62 { CRISV32F_INSN_CMP_M_D_M, && case_sem_INSN_CMP_M_D_M }, 63 { CRISV32F_INSN_CMPCBR, && case_sem_INSN_CMPCBR }, 64 { CRISV32F_INSN_CMPCWR, && case_sem_INSN_CMPCWR }, 65 { CRISV32F_INSN_CMPCDR, && case_sem_INSN_CMPCDR }, 66 { CRISV32F_INSN_CMPQ, && case_sem_INSN_CMPQ }, 67 { CRISV32F_INSN_CMPS_M_B_M, && case_sem_INSN_CMPS_M_B_M }, 68 { CRISV32F_INSN_CMPS_M_W_M, && case_sem_INSN_CMPS_M_W_M }, 69 { CRISV32F_INSN_CMPSCBR, && case_sem_INSN_CMPSCBR }, 70 { CRISV32F_INSN_CMPSCWR, && case_sem_INSN_CMPSCWR }, 71 { CRISV32F_INSN_CMPU_M_B_M, && case_sem_INSN_CMPU_M_B_M }, 72 { CRISV32F_INSN_CMPU_M_W_M, && case_sem_INSN_CMPU_M_W_M }, 73 { CRISV32F_INSN_CMPUCBR, && case_sem_INSN_CMPUCBR }, 74 { CRISV32F_INSN_CMPUCWR, && case_sem_INSN_CMPUCWR }, 75 { CRISV32F_INSN_MOVE_M_B_M, && case_sem_INSN_MOVE_M_B_M }, 76 { CRISV32F_INSN_MOVE_M_W_M, && case_sem_INSN_MOVE_M_W_M }, 77 { CRISV32F_INSN_MOVE_M_D_M, && case_sem_INSN_MOVE_M_D_M }, 78 { CRISV32F_INSN_MOVS_M_B_M, && case_sem_INSN_MOVS_M_B_M }, 79 { CRISV32F_INSN_MOVS_M_W_M, && case_sem_INSN_MOVS_M_W_M }, 80 { CRISV32F_INSN_MOVU_M_B_M, && case_sem_INSN_MOVU_M_B_M }, 81 { CRISV32F_INSN_MOVU_M_W_M, && case_sem_INSN_MOVU_M_W_M }, 82 { CRISV32F_INSN_MOVE_R_SPRV32, && case_sem_INSN_MOVE_R_SPRV32 }, 83 { CRISV32F_INSN_MOVE_SPR_RV32, && case_sem_INSN_MOVE_SPR_RV32 }, 84 { CRISV32F_INSN_MOVE_M_SPRV32, && case_sem_INSN_MOVE_M_SPRV32 }, 85 { CRISV32F_INSN_MOVE_C_SPRV32_P2, && case_sem_INSN_MOVE_C_SPRV32_P2 }, 86 { CRISV32F_INSN_MOVE_C_SPRV32_P3, && case_sem_INSN_MOVE_C_SPRV32_P3 }, 87 { CRISV32F_INSN_MOVE_C_SPRV32_P5, && case_sem_INSN_MOVE_C_SPRV32_P5 }, 88 { CRISV32F_INSN_MOVE_C_SPRV32_P6, && case_sem_INSN_MOVE_C_SPRV32_P6 }, 89 { CRISV32F_INSN_MOVE_C_SPRV32_P7, && case_sem_INSN_MOVE_C_SPRV32_P7 }, 90 { CRISV32F_INSN_MOVE_C_SPRV32_P9, && case_sem_INSN_MOVE_C_SPRV32_P9 }, 91 { CRISV32F_INSN_MOVE_C_SPRV32_P10, && case_sem_INSN_MOVE_C_SPRV32_P10 }, 92 { CRISV32F_INSN_MOVE_C_SPRV32_P11, && case_sem_INSN_MOVE_C_SPRV32_P11 }, 93 { CRISV32F_INSN_MOVE_C_SPRV32_P12, && case_sem_INSN_MOVE_C_SPRV32_P12 }, 94 { CRISV32F_INSN_MOVE_C_SPRV32_P13, && case_sem_INSN_MOVE_C_SPRV32_P13 }, 95 { CRISV32F_INSN_MOVE_C_SPRV32_P14, && case_sem_INSN_MOVE_C_SPRV32_P14 }, 96 { CRISV32F_INSN_MOVE_C_SPRV32_P15, && case_sem_INSN_MOVE_C_SPRV32_P15 }, 97 { CRISV32F_INSN_MOVE_SPR_MV32, && case_sem_INSN_MOVE_SPR_MV32 }, 98 { CRISV32F_INSN_MOVE_SS_R, && case_sem_INSN_MOVE_SS_R }, 99 { CRISV32F_INSN_MOVE_R_SS, && case_sem_INSN_MOVE_R_SS }, 100 { CRISV32F_INSN_MOVEM_R_M_V32, && case_sem_INSN_MOVEM_R_M_V32 }, 101 { CRISV32F_INSN_MOVEM_M_R_V32, && case_sem_INSN_MOVEM_M_R_V32 }, 102 { CRISV32F_INSN_ADD_B_R, && case_sem_INSN_ADD_B_R }, 103 { CRISV32F_INSN_ADD_W_R, && case_sem_INSN_ADD_W_R }, 104 { CRISV32F_INSN_ADD_D_R, && case_sem_INSN_ADD_D_R }, 105 { CRISV32F_INSN_ADD_M_B_M, && case_sem_INSN_ADD_M_B_M }, 106 { CRISV32F_INSN_ADD_M_W_M, && case_sem_INSN_ADD_M_W_M }, 107 { CRISV32F_INSN_ADD_M_D_M, && case_sem_INSN_ADD_M_D_M }, 108 { CRISV32F_INSN_ADDCBR, && case_sem_INSN_ADDCBR }, 109 { CRISV32F_INSN_ADDCWR, && case_sem_INSN_ADDCWR }, 110 { CRISV32F_INSN_ADDCDR, && case_sem_INSN_ADDCDR }, 111 { CRISV32F_INSN_ADDS_B_R, && case_sem_INSN_ADDS_B_R }, 112 { CRISV32F_INSN_ADDS_W_R, && case_sem_INSN_ADDS_W_R }, 113 { CRISV32F_INSN_ADDS_M_B_M, && case_sem_INSN_ADDS_M_B_M }, 114 { CRISV32F_INSN_ADDS_M_W_M, && case_sem_INSN_ADDS_M_W_M }, 115 { CRISV32F_INSN_ADDSCBR, && case_sem_INSN_ADDSCBR }, 116 { CRISV32F_INSN_ADDSCWR, && case_sem_INSN_ADDSCWR }, 117 { CRISV32F_INSN_ADDU_B_R, && case_sem_INSN_ADDU_B_R }, 118 { CRISV32F_INSN_ADDU_W_R, && case_sem_INSN_ADDU_W_R }, 119 { CRISV32F_INSN_ADDU_M_B_M, && case_sem_INSN_ADDU_M_B_M }, 120 { CRISV32F_INSN_ADDU_M_W_M, && case_sem_INSN_ADDU_M_W_M }, 121 { CRISV32F_INSN_ADDUCBR, && case_sem_INSN_ADDUCBR }, 122 { CRISV32F_INSN_ADDUCWR, && case_sem_INSN_ADDUCWR }, 123 { CRISV32F_INSN_SUB_B_R, && case_sem_INSN_SUB_B_R }, 124 { CRISV32F_INSN_SUB_W_R, && case_sem_INSN_SUB_W_R }, 125 { CRISV32F_INSN_SUB_D_R, && case_sem_INSN_SUB_D_R }, 126 { CRISV32F_INSN_SUB_M_B_M, && case_sem_INSN_SUB_M_B_M }, 127 { CRISV32F_INSN_SUB_M_W_M, && case_sem_INSN_SUB_M_W_M }, 128 { CRISV32F_INSN_SUB_M_D_M, && case_sem_INSN_SUB_M_D_M }, 129 { CRISV32F_INSN_SUBCBR, && case_sem_INSN_SUBCBR }, 130 { CRISV32F_INSN_SUBCWR, && case_sem_INSN_SUBCWR }, 131 { CRISV32F_INSN_SUBCDR, && case_sem_INSN_SUBCDR }, 132 { CRISV32F_INSN_SUBS_B_R, && case_sem_INSN_SUBS_B_R }, 133 { CRISV32F_INSN_SUBS_W_R, && case_sem_INSN_SUBS_W_R }, 134 { CRISV32F_INSN_SUBS_M_B_M, && case_sem_INSN_SUBS_M_B_M }, 135 { CRISV32F_INSN_SUBS_M_W_M, && case_sem_INSN_SUBS_M_W_M }, 136 { CRISV32F_INSN_SUBSCBR, && case_sem_INSN_SUBSCBR }, 137 { CRISV32F_INSN_SUBSCWR, && case_sem_INSN_SUBSCWR }, 138 { CRISV32F_INSN_SUBU_B_R, && case_sem_INSN_SUBU_B_R }, 139 { CRISV32F_INSN_SUBU_W_R, && case_sem_INSN_SUBU_W_R }, 140 { CRISV32F_INSN_SUBU_M_B_M, && case_sem_INSN_SUBU_M_B_M }, 141 { CRISV32F_INSN_SUBU_M_W_M, && case_sem_INSN_SUBU_M_W_M }, 142 { CRISV32F_INSN_SUBUCBR, && case_sem_INSN_SUBUCBR }, 143 { CRISV32F_INSN_SUBUCWR, && case_sem_INSN_SUBUCWR }, 144 { CRISV32F_INSN_ADDC_R, && case_sem_INSN_ADDC_R }, 145 { CRISV32F_INSN_ADDC_M, && case_sem_INSN_ADDC_M }, 146 { CRISV32F_INSN_ADDC_C, && case_sem_INSN_ADDC_C }, 147 { CRISV32F_INSN_LAPC_D, && case_sem_INSN_LAPC_D }, 148 { CRISV32F_INSN_LAPCQ, && case_sem_INSN_LAPCQ }, 149 { CRISV32F_INSN_ADDI_B_R, && case_sem_INSN_ADDI_B_R }, 150 { CRISV32F_INSN_ADDI_W_R, && case_sem_INSN_ADDI_W_R }, 151 { CRISV32F_INSN_ADDI_D_R, && case_sem_INSN_ADDI_D_R }, 152 { CRISV32F_INSN_NEG_B_R, && case_sem_INSN_NEG_B_R }, 153 { CRISV32F_INSN_NEG_W_R, && case_sem_INSN_NEG_W_R }, 154 { CRISV32F_INSN_NEG_D_R, && case_sem_INSN_NEG_D_R }, 155 { CRISV32F_INSN_TEST_M_B_M, && case_sem_INSN_TEST_M_B_M }, 156 { CRISV32F_INSN_TEST_M_W_M, && case_sem_INSN_TEST_M_W_M }, 157 { CRISV32F_INSN_TEST_M_D_M, && case_sem_INSN_TEST_M_D_M }, 158 { CRISV32F_INSN_MOVE_R_M_B_M, && case_sem_INSN_MOVE_R_M_B_M }, 159 { CRISV32F_INSN_MOVE_R_M_W_M, && case_sem_INSN_MOVE_R_M_W_M }, 160 { CRISV32F_INSN_MOVE_R_M_D_M, && case_sem_INSN_MOVE_R_M_D_M }, 161 { CRISV32F_INSN_MULS_B, && case_sem_INSN_MULS_B }, 162 { CRISV32F_INSN_MULS_W, && case_sem_INSN_MULS_W }, 163 { CRISV32F_INSN_MULS_D, && case_sem_INSN_MULS_D }, 164 { CRISV32F_INSN_MULU_B, && case_sem_INSN_MULU_B }, 165 { CRISV32F_INSN_MULU_W, && case_sem_INSN_MULU_W }, 166 { CRISV32F_INSN_MULU_D, && case_sem_INSN_MULU_D }, 167 { CRISV32F_INSN_MCP, && case_sem_INSN_MCP }, 168 { CRISV32F_INSN_DSTEP, && case_sem_INSN_DSTEP }, 169 { CRISV32F_INSN_ABS, && case_sem_INSN_ABS }, 170 { CRISV32F_INSN_AND_B_R, && case_sem_INSN_AND_B_R }, 171 { CRISV32F_INSN_AND_W_R, && case_sem_INSN_AND_W_R }, 172 { CRISV32F_INSN_AND_D_R, && case_sem_INSN_AND_D_R }, 173 { CRISV32F_INSN_AND_M_B_M, && case_sem_INSN_AND_M_B_M }, 174 { CRISV32F_INSN_AND_M_W_M, && case_sem_INSN_AND_M_W_M }, 175 { CRISV32F_INSN_AND_M_D_M, && case_sem_INSN_AND_M_D_M }, 176 { CRISV32F_INSN_ANDCBR, && case_sem_INSN_ANDCBR }, 177 { CRISV32F_INSN_ANDCWR, && case_sem_INSN_ANDCWR }, 178 { CRISV32F_INSN_ANDCDR, && case_sem_INSN_ANDCDR }, 179 { CRISV32F_INSN_ANDQ, && case_sem_INSN_ANDQ }, 180 { CRISV32F_INSN_ORR_B_R, && case_sem_INSN_ORR_B_R }, 181 { CRISV32F_INSN_ORR_W_R, && case_sem_INSN_ORR_W_R }, 182 { CRISV32F_INSN_ORR_D_R, && case_sem_INSN_ORR_D_R }, 183 { CRISV32F_INSN_OR_M_B_M, && case_sem_INSN_OR_M_B_M }, 184 { CRISV32F_INSN_OR_M_W_M, && case_sem_INSN_OR_M_W_M }, 185 { CRISV32F_INSN_OR_M_D_M, && case_sem_INSN_OR_M_D_M }, 186 { CRISV32F_INSN_ORCBR, && case_sem_INSN_ORCBR }, 187 { CRISV32F_INSN_ORCWR, && case_sem_INSN_ORCWR }, 188 { CRISV32F_INSN_ORCDR, && case_sem_INSN_ORCDR }, 189 { CRISV32F_INSN_ORQ, && case_sem_INSN_ORQ }, 190 { CRISV32F_INSN_XOR, && case_sem_INSN_XOR }, 191 { CRISV32F_INSN_SWAP, && case_sem_INSN_SWAP }, 192 { CRISV32F_INSN_ASRR_B_R, && case_sem_INSN_ASRR_B_R }, 193 { CRISV32F_INSN_ASRR_W_R, && case_sem_INSN_ASRR_W_R }, 194 { CRISV32F_INSN_ASRR_D_R, && case_sem_INSN_ASRR_D_R }, 195 { CRISV32F_INSN_ASRQ, && case_sem_INSN_ASRQ }, 196 { CRISV32F_INSN_LSRR_B_R, && case_sem_INSN_LSRR_B_R }, 197 { CRISV32F_INSN_LSRR_W_R, && case_sem_INSN_LSRR_W_R }, 198 { CRISV32F_INSN_LSRR_D_R, && case_sem_INSN_LSRR_D_R }, 199 { CRISV32F_INSN_LSRQ, && case_sem_INSN_LSRQ }, 200 { CRISV32F_INSN_LSLR_B_R, && case_sem_INSN_LSLR_B_R }, 201 { CRISV32F_INSN_LSLR_W_R, && case_sem_INSN_LSLR_W_R }, 202 { CRISV32F_INSN_LSLR_D_R, && case_sem_INSN_LSLR_D_R }, 203 { CRISV32F_INSN_LSLQ, && case_sem_INSN_LSLQ }, 204 { CRISV32F_INSN_BTST, && case_sem_INSN_BTST }, 205 { CRISV32F_INSN_BTSTQ, && case_sem_INSN_BTSTQ }, 206 { CRISV32F_INSN_SETF, && case_sem_INSN_SETF }, 207 { CRISV32F_INSN_CLEARF, && case_sem_INSN_CLEARF }, 208 { CRISV32F_INSN_RFE, && case_sem_INSN_RFE }, 209 { CRISV32F_INSN_SFE, && case_sem_INSN_SFE }, 210 { CRISV32F_INSN_RFG, && case_sem_INSN_RFG }, 211 { CRISV32F_INSN_RFN, && case_sem_INSN_RFN }, 212 { CRISV32F_INSN_HALT, && case_sem_INSN_HALT }, 213 { CRISV32F_INSN_BCC_B, && case_sem_INSN_BCC_B }, 214 { CRISV32F_INSN_BA_B, && case_sem_INSN_BA_B }, 215 { CRISV32F_INSN_BCC_W, && case_sem_INSN_BCC_W }, 216 { CRISV32F_INSN_BA_W, && case_sem_INSN_BA_W }, 217 { CRISV32F_INSN_JAS_R, && case_sem_INSN_JAS_R }, 218 { CRISV32F_INSN_JAS_C, && case_sem_INSN_JAS_C }, 219 { CRISV32F_INSN_JUMP_P, && case_sem_INSN_JUMP_P }, 220 { CRISV32F_INSN_BAS_C, && case_sem_INSN_BAS_C }, 221 { CRISV32F_INSN_JASC_R, && case_sem_INSN_JASC_R }, 222 { CRISV32F_INSN_JASC_C, && case_sem_INSN_JASC_C }, 223 { CRISV32F_INSN_BASC_C, && case_sem_INSN_BASC_C }, 224 { CRISV32F_INSN_BREAK, && case_sem_INSN_BREAK }, 225 { CRISV32F_INSN_BOUND_R_B_R, && case_sem_INSN_BOUND_R_B_R }, 226 { CRISV32F_INSN_BOUND_R_W_R, && case_sem_INSN_BOUND_R_W_R }, 227 { CRISV32F_INSN_BOUND_R_D_R, && case_sem_INSN_BOUND_R_D_R }, 228 { CRISV32F_INSN_BOUND_CB, && case_sem_INSN_BOUND_CB }, 229 { CRISV32F_INSN_BOUND_CW, && case_sem_INSN_BOUND_CW }, 230 { CRISV32F_INSN_BOUND_CD, && case_sem_INSN_BOUND_CD }, 231 { CRISV32F_INSN_SCC, && case_sem_INSN_SCC }, 232 { CRISV32F_INSN_LZ, && case_sem_INSN_LZ }, 233 { CRISV32F_INSN_ADDOQ, && case_sem_INSN_ADDOQ }, 234 { CRISV32F_INSN_ADDO_M_B_M, && case_sem_INSN_ADDO_M_B_M }, 235 { CRISV32F_INSN_ADDO_M_W_M, && case_sem_INSN_ADDO_M_W_M }, 236 { CRISV32F_INSN_ADDO_M_D_M, && case_sem_INSN_ADDO_M_D_M }, 237 { CRISV32F_INSN_ADDO_CB, && case_sem_INSN_ADDO_CB }, 238 { CRISV32F_INSN_ADDO_CW, && case_sem_INSN_ADDO_CW }, 239 { CRISV32F_INSN_ADDO_CD, && case_sem_INSN_ADDO_CD }, 240 { CRISV32F_INSN_ADDI_ACR_B_R, && case_sem_INSN_ADDI_ACR_B_R }, 241 { CRISV32F_INSN_ADDI_ACR_W_R, && case_sem_INSN_ADDI_ACR_W_R }, 242 { CRISV32F_INSN_ADDI_ACR_D_R, && case_sem_INSN_ADDI_ACR_D_R }, 243 { CRISV32F_INSN_FIDXI, && case_sem_INSN_FIDXI }, 244 { CRISV32F_INSN_FTAGI, && case_sem_INSN_FTAGI }, 245 { CRISV32F_INSN_FIDXD, && case_sem_INSN_FIDXD }, 246 { CRISV32F_INSN_FTAGD, && case_sem_INSN_FTAGD }, 247 { 0, 0 } 248 }; 249 int i; 250 251 for (i = 0; labels[i].label != 0; ++i) 252 { 253#if FAST_P 254 CPU_IDESC (current_cpu) [labels[i].index].sem_fast_lab = labels[i].label; 255#else 256 CPU_IDESC (current_cpu) [labels[i].index].sem_full_lab = labels[i].label; 257#endif 258 } 259 260#undef DEFINE_LABELS 261#endif /* DEFINE_LABELS */ 262 263#ifdef DEFINE_SWITCH 264 265/* If hyper-fast [well not unnecessarily slow] execution is selected, turn 266 off frills like tracing and profiling. */ 267/* FIXME: A better way would be to have TRACE_RESULT check for something 268 that can cause it to be optimized out. Another way would be to emit 269 special handlers into the instruction "stream". */ 270 271#if FAST_P 272#undef TRACE_RESULT 273#define TRACE_RESULT(cpu, abuf, name, type, val) 274#endif 275 276#undef GET_ATTR 277#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) 278#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_##attr) 279#else 280#define GET_ATTR(cpu, num, attr) CGEN_ATTR_VALUE (NULL, abuf->idesc->attrs, CGEN_INSN_/**/attr) 281#endif 282 283{ 284 285#if WITH_SCACHE_PBB 286 287/* Branch to next handler without going around main loop. */ 288#define NEXT(vpc) goto * SEM_ARGBUF (vpc) -> semantic.sem_case 289SWITCH (sem, SEM_ARGBUF (vpc) -> semantic.sem_case) 290 291#else /* ! WITH_SCACHE_PBB */ 292 293#define NEXT(vpc) BREAK (sem) 294#ifdef __GNUC__ 295#if FAST_P 296 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_fast_lab) 297#else 298 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->sem_full_lab) 299#endif 300#else 301 SWITCH (sem, SEM_ARGBUF (sc) -> idesc->num) 302#endif 303 304#endif /* ! WITH_SCACHE_PBB */ 305 306 { 307 308 CASE (sem, INSN_X_INVALID) : /* --invalid-- */ 309{ 310 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 311 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 312#define FLD(f) abuf->fields.fmt_empty.f 313 int UNUSED written = 0; 314 IADDR UNUSED pc = abuf->addr; 315 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 316 317 { 318 /* Update the recorded pc in the cpu state struct. 319 Only necessary for WITH_SCACHE case, but to avoid the 320 conditional compilation .... */ 321 SET_H_PC (pc); 322 /* Virtual insns have zero size. Overwrite vpc with address of next insn 323 using the default-insn-bitsize spec. When executing insns in parallel 324 we may want to queue the fault and continue execution. */ 325 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 326 vpc = sim_engine_invalid_insn (current_cpu, pc, vpc); 327 } 328 329#undef FLD 330} 331 NEXT (vpc); 332 333 CASE (sem, INSN_X_AFTER) : /* --after-- */ 334{ 335 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 336 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 337#define FLD(f) abuf->fields.fmt_empty.f 338 int UNUSED written = 0; 339 IADDR UNUSED pc = abuf->addr; 340 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 341 342 { 343#if WITH_SCACHE_PBB_CRISV32F 344 crisv32f_pbb_after (current_cpu, sem_arg); 345#endif 346 } 347 348#undef FLD 349} 350 NEXT (vpc); 351 352 CASE (sem, INSN_X_BEFORE) : /* --before-- */ 353{ 354 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 355 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 356#define FLD(f) abuf->fields.fmt_empty.f 357 int UNUSED written = 0; 358 IADDR UNUSED pc = abuf->addr; 359 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 360 361 { 362#if WITH_SCACHE_PBB_CRISV32F 363 crisv32f_pbb_before (current_cpu, sem_arg); 364#endif 365 } 366 367#undef FLD 368} 369 NEXT (vpc); 370 371 CASE (sem, INSN_X_CTI_CHAIN) : /* --cti-chain-- */ 372{ 373 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 374 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 375#define FLD(f) abuf->fields.fmt_empty.f 376 int UNUSED written = 0; 377 IADDR UNUSED pc = abuf->addr; 378 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 379 380 { 381#if WITH_SCACHE_PBB_CRISV32F 382#ifdef DEFINE_SWITCH 383 vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg, 384 pbb_br_type, pbb_br_npc); 385 BREAK (sem); 386#else 387 /* FIXME: Allow provision of explicit ifmt spec in insn spec. */ 388 vpc = crisv32f_pbb_cti_chain (current_cpu, sem_arg, 389 CPU_PBB_BR_TYPE (current_cpu), 390 CPU_PBB_BR_NPC (current_cpu)); 391#endif 392#endif 393 } 394 395#undef FLD 396} 397 NEXT (vpc); 398 399 CASE (sem, INSN_X_CHAIN) : /* --chain-- */ 400{ 401 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 402 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 403#define FLD(f) abuf->fields.fmt_empty.f 404 int UNUSED written = 0; 405 IADDR UNUSED pc = abuf->addr; 406 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 407 408 { 409#if WITH_SCACHE_PBB_CRISV32F 410 vpc = crisv32f_pbb_chain (current_cpu, sem_arg); 411#ifdef DEFINE_SWITCH 412 BREAK (sem); 413#endif 414#endif 415 } 416 417#undef FLD 418} 419 NEXT (vpc); 420 421 CASE (sem, INSN_X_BEGIN) : /* --begin-- */ 422{ 423 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 424 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 425#define FLD(f) abuf->fields.fmt_empty.f 426 int UNUSED written = 0; 427 IADDR UNUSED pc = abuf->addr; 428 vpc = SEM_NEXT_VPC (sem_arg, pc, 0); 429 430 { 431#if WITH_SCACHE_PBB_CRISV32F 432#if defined DEFINE_SWITCH || defined FAST_P 433 /* In the switch case FAST_P is a constant, allowing several optimizations 434 in any called inline functions. */ 435 vpc = crisv32f_pbb_begin (current_cpu, FAST_P); 436#else 437#if 0 /* cgen engine can't handle dynamic fast/full switching yet. */ 438 vpc = crisv32f_pbb_begin (current_cpu, STATE_RUN_FAST_P (CPU_STATE (current_cpu))); 439#else 440 vpc = crisv32f_pbb_begin (current_cpu, 0); 441#endif 442#endif 443#endif 444 } 445 446#undef FLD 447} 448 NEXT (vpc); 449 450 CASE (sem, INSN_MOVE_B_R) : /* move.b move.m ${Rs},${Rd} */ 451{ 452 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 453 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 454#define FLD(f) abuf->fields.sfmt_addc_m.f 455 int UNUSED written = 0; 456 IADDR UNUSED pc = abuf->addr; 457 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 458 459{ 460 QI tmp_newval; 461 tmp_newval = GET_H_GR (FLD (f_operand1)); 462{ 463 SI tmp_oldregval; 464 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 465 { 466 SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); 467 SET_H_GR (FLD (f_operand2), opval); 468 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 469 } 470} 471{ 472 { 473 BI opval = LTQI (tmp_newval, 0); 474 CPU (h_nbit) = opval; 475 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 476 } 477 { 478 BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 479 CPU (h_zbit) = opval; 480 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 481 } 482SET_H_CBIT_MOVE (0); 483SET_H_VBIT_MOVE (0); 484{ 485 { 486 BI opval = 0; 487 CPU (h_xbit) = opval; 488 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 489 } 490 { 491 BI opval = 0; 492 SET_H_INSN_PREFIXED_P (opval); 493 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 494 } 495} 496} 497} 498 499#undef FLD 500} 501 NEXT (vpc); 502 503 CASE (sem, INSN_MOVE_W_R) : /* move.w move.m ${Rs},${Rd} */ 504{ 505 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 506 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 507#define FLD(f) abuf->fields.sfmt_addc_m.f 508 int UNUSED written = 0; 509 IADDR UNUSED pc = abuf->addr; 510 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 511 512{ 513 HI tmp_newval; 514 tmp_newval = GET_H_GR (FLD (f_operand1)); 515{ 516 SI tmp_oldregval; 517 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 518 { 519 SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 520 SET_H_GR (FLD (f_operand2), opval); 521 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 522 } 523} 524{ 525 { 526 BI opval = LTHI (tmp_newval, 0); 527 CPU (h_nbit) = opval; 528 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 529 } 530 { 531 BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 532 CPU (h_zbit) = opval; 533 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 534 } 535SET_H_CBIT_MOVE (0); 536SET_H_VBIT_MOVE (0); 537{ 538 { 539 BI opval = 0; 540 CPU (h_xbit) = opval; 541 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 542 } 543 { 544 BI opval = 0; 545 SET_H_INSN_PREFIXED_P (opval); 546 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 547 } 548} 549} 550} 551 552#undef FLD 553} 554 NEXT (vpc); 555 556 CASE (sem, INSN_MOVE_D_R) : /* move.d move.m ${Rs},${Rd} */ 557{ 558 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 559 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 560#define FLD(f) abuf->fields.sfmt_addc_m.f 561 int UNUSED written = 0; 562 IADDR UNUSED pc = abuf->addr; 563 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 564 565{ 566 SI tmp_newval; 567 tmp_newval = GET_H_GR (FLD (f_operand1)); 568 { 569 SI opval = tmp_newval; 570 SET_H_GR (FLD (f_operand2), opval); 571 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 572 } 573{ 574 { 575 BI opval = LTSI (tmp_newval, 0); 576 CPU (h_nbit) = opval; 577 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 578 } 579 { 580 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 581 CPU (h_zbit) = opval; 582 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 583 } 584SET_H_CBIT_MOVE (0); 585SET_H_VBIT_MOVE (0); 586{ 587 { 588 BI opval = 0; 589 CPU (h_xbit) = opval; 590 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 591 } 592 { 593 BI opval = 0; 594 SET_H_INSN_PREFIXED_P (opval); 595 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 596 } 597} 598} 599} 600 601#undef FLD 602} 603 NEXT (vpc); 604 605 CASE (sem, INSN_MOVEQ) : /* moveq $i,$Rd */ 606{ 607 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 608 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 609#define FLD(f) abuf->fields.sfmt_moveq.f 610 int UNUSED written = 0; 611 IADDR UNUSED pc = abuf->addr; 612 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 613 614{ 615 SI tmp_newval; 616 tmp_newval = FLD (f_s6); 617 { 618 SI opval = tmp_newval; 619 SET_H_GR (FLD (f_operand2), opval); 620 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 621 } 622{ 623SET_H_NBIT_MOVE (LTSI (tmp_newval, 0)); 624SET_H_ZBIT_MOVE (ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1)))); 625SET_H_CBIT_MOVE (0); 626SET_H_VBIT_MOVE (0); 627{ 628 { 629 BI opval = 0; 630 CPU (h_xbit) = opval; 631 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 632 } 633 { 634 BI opval = 0; 635 SET_H_INSN_PREFIXED_P (opval); 636 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 637 } 638} 639} 640} 641 642#undef FLD 643} 644 NEXT (vpc); 645 646 CASE (sem, INSN_MOVS_B_R) : /* movs.b movs.m ${Rs},${Rd} */ 647{ 648 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 649 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 650#define FLD(f) abuf->fields.sfmt_muls_b.f 651 int UNUSED written = 0; 652 IADDR UNUSED pc = abuf->addr; 653 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 654 655{ 656 QI tmp_newval; 657 tmp_newval = GET_H_GR (FLD (f_operand1)); 658 { 659 SI opval = EXTQISI (tmp_newval); 660 SET_H_GR (FLD (f_operand2), opval); 661 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 662 } 663{ 664 { 665 BI opval = LTSI (tmp_newval, 0); 666 CPU (h_nbit) = opval; 667 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 668 } 669 { 670 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 671 CPU (h_zbit) = opval; 672 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 673 } 674SET_H_CBIT_MOVE (0); 675SET_H_VBIT_MOVE (0); 676{ 677 { 678 BI opval = 0; 679 CPU (h_xbit) = opval; 680 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 681 } 682 { 683 BI opval = 0; 684 SET_H_INSN_PREFIXED_P (opval); 685 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 686 } 687} 688} 689} 690 691#undef FLD 692} 693 NEXT (vpc); 694 695 CASE (sem, INSN_MOVS_W_R) : /* movs.w movs.m ${Rs},${Rd} */ 696{ 697 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 698 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 699#define FLD(f) abuf->fields.sfmt_muls_b.f 700 int UNUSED written = 0; 701 IADDR UNUSED pc = abuf->addr; 702 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 703 704{ 705 HI tmp_newval; 706 tmp_newval = GET_H_GR (FLD (f_operand1)); 707 { 708 SI opval = EXTHISI (tmp_newval); 709 SET_H_GR (FLD (f_operand2), opval); 710 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 711 } 712{ 713 { 714 BI opval = LTSI (tmp_newval, 0); 715 CPU (h_nbit) = opval; 716 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 717 } 718 { 719 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 720 CPU (h_zbit) = opval; 721 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 722 } 723SET_H_CBIT_MOVE (0); 724SET_H_VBIT_MOVE (0); 725{ 726 { 727 BI opval = 0; 728 CPU (h_xbit) = opval; 729 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 730 } 731 { 732 BI opval = 0; 733 SET_H_INSN_PREFIXED_P (opval); 734 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 735 } 736} 737} 738} 739 740#undef FLD 741} 742 NEXT (vpc); 743 744 CASE (sem, INSN_MOVU_B_R) : /* movu.b movu.m ${Rs},${Rd} */ 745{ 746 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 747 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 748#define FLD(f) abuf->fields.sfmt_muls_b.f 749 int UNUSED written = 0; 750 IADDR UNUSED pc = abuf->addr; 751 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 752 753{ 754 QI tmp_newval; 755 tmp_newval = GET_H_GR (FLD (f_operand1)); 756 { 757 SI opval = ZEXTQISI (tmp_newval); 758 SET_H_GR (FLD (f_operand2), opval); 759 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 760 } 761{ 762 { 763 BI opval = LTSI (tmp_newval, 0); 764 CPU (h_nbit) = opval; 765 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 766 } 767 { 768 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 769 CPU (h_zbit) = opval; 770 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 771 } 772SET_H_CBIT_MOVE (0); 773SET_H_VBIT_MOVE (0); 774{ 775 { 776 BI opval = 0; 777 CPU (h_xbit) = opval; 778 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 779 } 780 { 781 BI opval = 0; 782 SET_H_INSN_PREFIXED_P (opval); 783 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 784 } 785} 786} 787} 788 789#undef FLD 790} 791 NEXT (vpc); 792 793 CASE (sem, INSN_MOVU_W_R) : /* movu.w movu.m ${Rs},${Rd} */ 794{ 795 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 796 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 797#define FLD(f) abuf->fields.sfmt_muls_b.f 798 int UNUSED written = 0; 799 IADDR UNUSED pc = abuf->addr; 800 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 801 802{ 803 HI tmp_newval; 804 tmp_newval = GET_H_GR (FLD (f_operand1)); 805 { 806 SI opval = ZEXTHISI (tmp_newval); 807 SET_H_GR (FLD (f_operand2), opval); 808 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 809 } 810{ 811 { 812 BI opval = LTSI (tmp_newval, 0); 813 CPU (h_nbit) = opval; 814 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 815 } 816 { 817 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 818 CPU (h_zbit) = opval; 819 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 820 } 821SET_H_CBIT_MOVE (0); 822SET_H_VBIT_MOVE (0); 823{ 824 { 825 BI opval = 0; 826 CPU (h_xbit) = opval; 827 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 828 } 829 { 830 BI opval = 0; 831 SET_H_INSN_PREFIXED_P (opval); 832 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 833 } 834} 835} 836} 837 838#undef FLD 839} 840 NEXT (vpc); 841 842 CASE (sem, INSN_MOVECBR) : /* move.b ${sconst8},${Rd} */ 843{ 844 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 845 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 846#define FLD(f) abuf->fields.sfmt_addcbr.f 847 int UNUSED written = 0; 848 IADDR UNUSED pc = abuf->addr; 849 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 850 851{ 852 QI tmp_newval; 853 tmp_newval = FLD (f_indir_pc__byte); 854{ 855 SI tmp_oldregval; 856 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 857 { 858 SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); 859 SET_H_GR (FLD (f_operand2), opval); 860 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 861 } 862} 863{ 864 { 865 BI opval = LTQI (tmp_newval, 0); 866 CPU (h_nbit) = opval; 867 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 868 } 869 { 870 BI opval = ANDIF (EQQI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 871 CPU (h_zbit) = opval; 872 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 873 } 874SET_H_CBIT_MOVE (0); 875SET_H_VBIT_MOVE (0); 876{ 877 { 878 BI opval = 0; 879 CPU (h_xbit) = opval; 880 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 881 } 882 { 883 BI opval = 0; 884 SET_H_INSN_PREFIXED_P (opval); 885 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 886 } 887} 888} 889} 890 891#undef FLD 892} 893 NEXT (vpc); 894 895 CASE (sem, INSN_MOVECWR) : /* move.w ${sconst16},${Rd} */ 896{ 897 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 898 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 899#define FLD(f) abuf->fields.sfmt_addcwr.f 900 int UNUSED written = 0; 901 IADDR UNUSED pc = abuf->addr; 902 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 903 904{ 905 HI tmp_newval; 906 tmp_newval = FLD (f_indir_pc__word); 907{ 908 SI tmp_oldregval; 909 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 910 { 911 SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 912 SET_H_GR (FLD (f_operand2), opval); 913 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 914 } 915} 916{ 917 { 918 BI opval = LTHI (tmp_newval, 0); 919 CPU (h_nbit) = opval; 920 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 921 } 922 { 923 BI opval = ANDIF (EQHI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 924 CPU (h_zbit) = opval; 925 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 926 } 927SET_H_CBIT_MOVE (0); 928SET_H_VBIT_MOVE (0); 929{ 930 { 931 BI opval = 0; 932 CPU (h_xbit) = opval; 933 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 934 } 935 { 936 BI opval = 0; 937 SET_H_INSN_PREFIXED_P (opval); 938 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 939 } 940} 941} 942} 943 944#undef FLD 945} 946 NEXT (vpc); 947 948 CASE (sem, INSN_MOVECDR) : /* move.d ${const32},${Rd} */ 949{ 950 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 951 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 952#define FLD(f) abuf->fields.sfmt_bound_cd.f 953 int UNUSED written = 0; 954 IADDR UNUSED pc = abuf->addr; 955 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 956 957{ 958 SI tmp_newval; 959 tmp_newval = FLD (f_indir_pc__dword); 960 { 961 SI opval = tmp_newval; 962 SET_H_GR (FLD (f_operand2), opval); 963 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 964 } 965{ 966 { 967 BI opval = LTSI (tmp_newval, 0); 968 CPU (h_nbit) = opval; 969 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 970 } 971 { 972 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 973 CPU (h_zbit) = opval; 974 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 975 } 976SET_H_CBIT_MOVE (0); 977SET_H_VBIT_MOVE (0); 978{ 979 { 980 BI opval = 0; 981 CPU (h_xbit) = opval; 982 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 983 } 984 { 985 BI opval = 0; 986 SET_H_INSN_PREFIXED_P (opval); 987 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 988 } 989} 990} 991} 992 993#undef FLD 994} 995 NEXT (vpc); 996 997 CASE (sem, INSN_MOVSCBR) : /* movs.b ${sconst8},${Rd} */ 998{ 999 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1000 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1001#define FLD(f) abuf->fields.sfmt_bound_cb.f 1002 int UNUSED written = 0; 1003 IADDR UNUSED pc = abuf->addr; 1004 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1005 1006{ 1007 SI tmp_newval; 1008 tmp_newval = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))); 1009 { 1010 SI opval = tmp_newval; 1011 SET_H_GR (FLD (f_operand2), opval); 1012 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1013 } 1014{ 1015 { 1016 BI opval = LTSI (tmp_newval, 0); 1017 CPU (h_nbit) = opval; 1018 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1019 } 1020 { 1021 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 1022 CPU (h_zbit) = opval; 1023 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1024 } 1025SET_H_CBIT_MOVE (0); 1026SET_H_VBIT_MOVE (0); 1027{ 1028 { 1029 BI opval = 0; 1030 CPU (h_xbit) = opval; 1031 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1032 } 1033 { 1034 BI opval = 0; 1035 SET_H_INSN_PREFIXED_P (opval); 1036 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1037 } 1038} 1039} 1040} 1041 1042#undef FLD 1043} 1044 NEXT (vpc); 1045 1046 CASE (sem, INSN_MOVSCWR) : /* movs.w ${sconst16},${Rd} */ 1047{ 1048 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1049 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1050#define FLD(f) abuf->fields.sfmt_bound_cw.f 1051 int UNUSED written = 0; 1052 IADDR UNUSED pc = abuf->addr; 1053 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1054 1055{ 1056 SI tmp_newval; 1057 tmp_newval = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))); 1058 { 1059 SI opval = tmp_newval; 1060 SET_H_GR (FLD (f_operand2), opval); 1061 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1062 } 1063{ 1064 { 1065 BI opval = LTSI (tmp_newval, 0); 1066 CPU (h_nbit) = opval; 1067 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1068 } 1069 { 1070 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 1071 CPU (h_zbit) = opval; 1072 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1073 } 1074SET_H_CBIT_MOVE (0); 1075SET_H_VBIT_MOVE (0); 1076{ 1077 { 1078 BI opval = 0; 1079 CPU (h_xbit) = opval; 1080 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1081 } 1082 { 1083 BI opval = 0; 1084 SET_H_INSN_PREFIXED_P (opval); 1085 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1086 } 1087} 1088} 1089} 1090 1091#undef FLD 1092} 1093 NEXT (vpc); 1094 1095 CASE (sem, INSN_MOVUCBR) : /* movu.b ${uconst8},${Rd} */ 1096{ 1097 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1098 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1099#define FLD(f) abuf->fields.sfmt_bound_cb.f 1100 int UNUSED written = 0; 1101 IADDR UNUSED pc = abuf->addr; 1102 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1103 1104{ 1105 SI tmp_newval; 1106 tmp_newval = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))); 1107 { 1108 SI opval = tmp_newval; 1109 SET_H_GR (FLD (f_operand2), opval); 1110 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1111 } 1112{ 1113 { 1114 BI opval = LTSI (tmp_newval, 0); 1115 CPU (h_nbit) = opval; 1116 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1117 } 1118 { 1119 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 1120 CPU (h_zbit) = opval; 1121 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1122 } 1123SET_H_CBIT_MOVE (0); 1124SET_H_VBIT_MOVE (0); 1125{ 1126 { 1127 BI opval = 0; 1128 CPU (h_xbit) = opval; 1129 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1130 } 1131 { 1132 BI opval = 0; 1133 SET_H_INSN_PREFIXED_P (opval); 1134 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1135 } 1136} 1137} 1138} 1139 1140#undef FLD 1141} 1142 NEXT (vpc); 1143 1144 CASE (sem, INSN_MOVUCWR) : /* movu.w ${uconst16},${Rd} */ 1145{ 1146 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1147 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1148#define FLD(f) abuf->fields.sfmt_bound_cw.f 1149 int UNUSED written = 0; 1150 IADDR UNUSED pc = abuf->addr; 1151 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1152 1153{ 1154 SI tmp_newval; 1155 tmp_newval = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))); 1156 { 1157 SI opval = tmp_newval; 1158 SET_H_GR (FLD (f_operand2), opval); 1159 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1160 } 1161{ 1162 { 1163 BI opval = LTSI (tmp_newval, 0); 1164 CPU (h_nbit) = opval; 1165 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1166 } 1167 { 1168 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 1169 CPU (h_zbit) = opval; 1170 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1171 } 1172SET_H_CBIT_MOVE (0); 1173SET_H_VBIT_MOVE (0); 1174{ 1175 { 1176 BI opval = 0; 1177 CPU (h_xbit) = opval; 1178 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1179 } 1180 { 1181 BI opval = 0; 1182 SET_H_INSN_PREFIXED_P (opval); 1183 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1184 } 1185} 1186} 1187} 1188 1189#undef FLD 1190} 1191 NEXT (vpc); 1192 1193 CASE (sem, INSN_ADDQ) : /* addq $j,$Rd */ 1194{ 1195 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1196 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1197#define FLD(f) abuf->fields.sfmt_addq.f 1198 int UNUSED written = 0; 1199 IADDR UNUSED pc = abuf->addr; 1200 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1201 1202{ 1203 SI tmp_tmpopd; 1204 SI tmp_tmpops; 1205 BI tmp_carry; 1206 SI tmp_newval; 1207 tmp_tmpops = FLD (f_u6); 1208 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 1209 tmp_carry = CPU (h_cbit); 1210 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 1211 { 1212 SI opval = tmp_newval; 1213 SET_H_GR (FLD (f_operand2), opval); 1214 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1215 } 1216{ 1217 { 1218 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 1219 CPU (h_cbit) = opval; 1220 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 1221 } 1222 { 1223 BI opval = LTSI (tmp_newval, 0); 1224 CPU (h_nbit) = opval; 1225 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1226 } 1227 { 1228 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 1229 CPU (h_zbit) = opval; 1230 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1231 } 1232 { 1233 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 1234 CPU (h_vbit) = opval; 1235 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 1236 } 1237{ 1238 { 1239 BI opval = 0; 1240 CPU (h_xbit) = opval; 1241 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1242 } 1243 { 1244 BI opval = 0; 1245 SET_H_INSN_PREFIXED_P (opval); 1246 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1247 } 1248} 1249} 1250} 1251 1252#undef FLD 1253} 1254 NEXT (vpc); 1255 1256 CASE (sem, INSN_SUBQ) : /* subq $j,$Rd */ 1257{ 1258 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1259 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1260#define FLD(f) abuf->fields.sfmt_addq.f 1261 int UNUSED written = 0; 1262 IADDR UNUSED pc = abuf->addr; 1263 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1264 1265{ 1266 SI tmp_tmpopd; 1267 SI tmp_tmpops; 1268 BI tmp_carry; 1269 SI tmp_newval; 1270 tmp_tmpops = FLD (f_u6); 1271 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 1272 tmp_carry = CPU (h_cbit); 1273 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 1274 { 1275 SI opval = tmp_newval; 1276 SET_H_GR (FLD (f_operand2), opval); 1277 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1278 } 1279{ 1280 { 1281 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 1282 CPU (h_cbit) = opval; 1283 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 1284 } 1285 { 1286 BI opval = LTSI (tmp_newval, 0); 1287 CPU (h_nbit) = opval; 1288 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1289 } 1290 { 1291 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 1292 CPU (h_zbit) = opval; 1293 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1294 } 1295 { 1296 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 1297 CPU (h_vbit) = opval; 1298 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 1299 } 1300{ 1301 { 1302 BI opval = 0; 1303 CPU (h_xbit) = opval; 1304 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1305 } 1306 { 1307 BI opval = 0; 1308 SET_H_INSN_PREFIXED_P (opval); 1309 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1310 } 1311} 1312} 1313} 1314 1315#undef FLD 1316} 1317 NEXT (vpc); 1318 1319 CASE (sem, INSN_CMP_R_B_R) : /* cmp-r.b $Rs,$Rd */ 1320{ 1321 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1322 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1323#define FLD(f) abuf->fields.sfmt_muls_b.f 1324 int UNUSED written = 0; 1325 IADDR UNUSED pc = abuf->addr; 1326 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1327 1328{ 1329 QI tmp_tmpopd; 1330 QI tmp_tmpops; 1331 BI tmp_carry; 1332 QI tmp_newval; 1333 tmp_tmpops = GET_H_GR (FLD (f_operand1)); 1334 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 1335 tmp_carry = CPU (h_cbit); 1336 tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 1337((void) 0); /*nop*/ 1338{ 1339 { 1340 BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0)))); 1341 CPU (h_cbit) = opval; 1342 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 1343 } 1344 { 1345 BI opval = LTQI (tmp_newval, 0); 1346 CPU (h_nbit) = opval; 1347 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1348 } 1349 { 1350 BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 1351 CPU (h_zbit) = opval; 1352 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1353 } 1354 { 1355 BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0))); 1356 CPU (h_vbit) = opval; 1357 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 1358 } 1359{ 1360 { 1361 BI opval = 0; 1362 CPU (h_xbit) = opval; 1363 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1364 } 1365 { 1366 BI opval = 0; 1367 SET_H_INSN_PREFIXED_P (opval); 1368 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1369 } 1370} 1371} 1372} 1373 1374#undef FLD 1375} 1376 NEXT (vpc); 1377 1378 CASE (sem, INSN_CMP_R_W_R) : /* cmp-r.w $Rs,$Rd */ 1379{ 1380 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1381 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1382#define FLD(f) abuf->fields.sfmt_muls_b.f 1383 int UNUSED written = 0; 1384 IADDR UNUSED pc = abuf->addr; 1385 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1386 1387{ 1388 HI tmp_tmpopd; 1389 HI tmp_tmpops; 1390 BI tmp_carry; 1391 HI tmp_newval; 1392 tmp_tmpops = GET_H_GR (FLD (f_operand1)); 1393 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 1394 tmp_carry = CPU (h_cbit); 1395 tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 1396((void) 0); /*nop*/ 1397{ 1398 { 1399 BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0)))); 1400 CPU (h_cbit) = opval; 1401 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 1402 } 1403 { 1404 BI opval = LTHI (tmp_newval, 0); 1405 CPU (h_nbit) = opval; 1406 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1407 } 1408 { 1409 BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 1410 CPU (h_zbit) = opval; 1411 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1412 } 1413 { 1414 BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0))); 1415 CPU (h_vbit) = opval; 1416 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 1417 } 1418{ 1419 { 1420 BI opval = 0; 1421 CPU (h_xbit) = opval; 1422 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1423 } 1424 { 1425 BI opval = 0; 1426 SET_H_INSN_PREFIXED_P (opval); 1427 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1428 } 1429} 1430} 1431} 1432 1433#undef FLD 1434} 1435 NEXT (vpc); 1436 1437 CASE (sem, INSN_CMP_R_D_R) : /* cmp-r.d $Rs,$Rd */ 1438{ 1439 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1440 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1441#define FLD(f) abuf->fields.sfmt_muls_b.f 1442 int UNUSED written = 0; 1443 IADDR UNUSED pc = abuf->addr; 1444 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1445 1446{ 1447 SI tmp_tmpopd; 1448 SI tmp_tmpops; 1449 BI tmp_carry; 1450 SI tmp_newval; 1451 tmp_tmpops = GET_H_GR (FLD (f_operand1)); 1452 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 1453 tmp_carry = CPU (h_cbit); 1454 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 1455((void) 0); /*nop*/ 1456{ 1457 { 1458 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 1459 CPU (h_cbit) = opval; 1460 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 1461 } 1462 { 1463 BI opval = LTSI (tmp_newval, 0); 1464 CPU (h_nbit) = opval; 1465 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1466 } 1467 { 1468 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 1469 CPU (h_zbit) = opval; 1470 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1471 } 1472 { 1473 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 1474 CPU (h_vbit) = opval; 1475 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 1476 } 1477{ 1478 { 1479 BI opval = 0; 1480 CPU (h_xbit) = opval; 1481 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1482 } 1483 { 1484 BI opval = 0; 1485 SET_H_INSN_PREFIXED_P (opval); 1486 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1487 } 1488} 1489} 1490} 1491 1492#undef FLD 1493} 1494 NEXT (vpc); 1495 1496 CASE (sem, INSN_CMP_M_B_M) : /* cmp-m.b [${Rs}${inc}],${Rd} */ 1497{ 1498 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1499 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1500#define FLD(f) abuf->fields.sfmt_addc_m.f 1501 int UNUSED written = 0; 1502 IADDR UNUSED pc = abuf->addr; 1503 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1504 1505{ 1506 QI tmp_tmpopd; 1507 QI tmp_tmpops; 1508 BI tmp_carry; 1509 QI tmp_newval; 1510 tmp_tmpops = ({ SI tmp_addr; 1511 QI tmp_tmp_mem; 1512 BI tmp_postinc; 1513 tmp_postinc = FLD (f_memmode); 1514; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 1515; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 1516; if (NEBI (tmp_postinc, 0)) { 1517{ 1518if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 1519 tmp_addr = ADDSI (tmp_addr, 1); 1520} 1521 { 1522 SI opval = tmp_addr; 1523 SET_H_GR (FLD (f_operand1), opval); 1524 written |= (1 << 9); 1525 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1526 } 1527} 1528} 1529; tmp_tmp_mem; }); 1530 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 1531 tmp_carry = CPU (h_cbit); 1532 tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 1533((void) 0); /*nop*/ 1534{ 1535 { 1536 BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0)))); 1537 CPU (h_cbit) = opval; 1538 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 1539 } 1540 { 1541 BI opval = LTQI (tmp_newval, 0); 1542 CPU (h_nbit) = opval; 1543 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1544 } 1545 { 1546 BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 1547 CPU (h_zbit) = opval; 1548 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1549 } 1550 { 1551 BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0))); 1552 CPU (h_vbit) = opval; 1553 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 1554 } 1555{ 1556 { 1557 BI opval = 0; 1558 CPU (h_xbit) = opval; 1559 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1560 } 1561 { 1562 BI opval = 0; 1563 SET_H_INSN_PREFIXED_P (opval); 1564 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1565 } 1566} 1567} 1568} 1569 1570 abuf->written = written; 1571#undef FLD 1572} 1573 NEXT (vpc); 1574 1575 CASE (sem, INSN_CMP_M_W_M) : /* cmp-m.w [${Rs}${inc}],${Rd} */ 1576{ 1577 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1578 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1579#define FLD(f) abuf->fields.sfmt_addc_m.f 1580 int UNUSED written = 0; 1581 IADDR UNUSED pc = abuf->addr; 1582 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1583 1584{ 1585 HI tmp_tmpopd; 1586 HI tmp_tmpops; 1587 BI tmp_carry; 1588 HI tmp_newval; 1589 tmp_tmpops = ({ SI tmp_addr; 1590 HI tmp_tmp_mem; 1591 BI tmp_postinc; 1592 tmp_postinc = FLD (f_memmode); 1593; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 1594; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 1595; if (NEBI (tmp_postinc, 0)) { 1596{ 1597if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 1598 tmp_addr = ADDSI (tmp_addr, 2); 1599} 1600 { 1601 SI opval = tmp_addr; 1602 SET_H_GR (FLD (f_operand1), opval); 1603 written |= (1 << 9); 1604 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1605 } 1606} 1607} 1608; tmp_tmp_mem; }); 1609 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 1610 tmp_carry = CPU (h_cbit); 1611 tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 1612((void) 0); /*nop*/ 1613{ 1614 { 1615 BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0)))); 1616 CPU (h_cbit) = opval; 1617 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 1618 } 1619 { 1620 BI opval = LTHI (tmp_newval, 0); 1621 CPU (h_nbit) = opval; 1622 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1623 } 1624 { 1625 BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 1626 CPU (h_zbit) = opval; 1627 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1628 } 1629 { 1630 BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0))); 1631 CPU (h_vbit) = opval; 1632 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 1633 } 1634{ 1635 { 1636 BI opval = 0; 1637 CPU (h_xbit) = opval; 1638 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1639 } 1640 { 1641 BI opval = 0; 1642 SET_H_INSN_PREFIXED_P (opval); 1643 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1644 } 1645} 1646} 1647} 1648 1649 abuf->written = written; 1650#undef FLD 1651} 1652 NEXT (vpc); 1653 1654 CASE (sem, INSN_CMP_M_D_M) : /* cmp-m.d [${Rs}${inc}],${Rd} */ 1655{ 1656 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1657 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1658#define FLD(f) abuf->fields.sfmt_addc_m.f 1659 int UNUSED written = 0; 1660 IADDR UNUSED pc = abuf->addr; 1661 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1662 1663{ 1664 SI tmp_tmpopd; 1665 SI tmp_tmpops; 1666 BI tmp_carry; 1667 SI tmp_newval; 1668 tmp_tmpops = ({ SI tmp_addr; 1669 SI tmp_tmp_mem; 1670 BI tmp_postinc; 1671 tmp_postinc = FLD (f_memmode); 1672; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 1673; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 1674; if (NEBI (tmp_postinc, 0)) { 1675{ 1676if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 1677 tmp_addr = ADDSI (tmp_addr, 4); 1678} 1679 { 1680 SI opval = tmp_addr; 1681 SET_H_GR (FLD (f_operand1), opval); 1682 written |= (1 << 9); 1683 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1684 } 1685} 1686} 1687; tmp_tmp_mem; }); 1688 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 1689 tmp_carry = CPU (h_cbit); 1690 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 1691((void) 0); /*nop*/ 1692{ 1693 { 1694 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 1695 CPU (h_cbit) = opval; 1696 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 1697 } 1698 { 1699 BI opval = LTSI (tmp_newval, 0); 1700 CPU (h_nbit) = opval; 1701 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1702 } 1703 { 1704 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 1705 CPU (h_zbit) = opval; 1706 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1707 } 1708 { 1709 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 1710 CPU (h_vbit) = opval; 1711 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 1712 } 1713{ 1714 { 1715 BI opval = 0; 1716 CPU (h_xbit) = opval; 1717 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1718 } 1719 { 1720 BI opval = 0; 1721 SET_H_INSN_PREFIXED_P (opval); 1722 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1723 } 1724} 1725} 1726} 1727 1728 abuf->written = written; 1729#undef FLD 1730} 1731 NEXT (vpc); 1732 1733 CASE (sem, INSN_CMPCBR) : /* cmp.b $sconst8,$Rd */ 1734{ 1735 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1736 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1737#define FLD(f) abuf->fields.sfmt_bound_cb.f 1738 int UNUSED written = 0; 1739 IADDR UNUSED pc = abuf->addr; 1740 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1741 1742{ 1743 QI tmp_tmpopd; 1744 QI tmp_tmpops; 1745 BI tmp_carry; 1746 QI tmp_newval; 1747 tmp_tmpops = TRUNCSIQI (FLD (f_indir_pc__byte)); 1748 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 1749 tmp_carry = CPU (h_cbit); 1750 tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 1751((void) 0); /*nop*/ 1752{ 1753 { 1754 BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0)))); 1755 CPU (h_cbit) = opval; 1756 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 1757 } 1758 { 1759 BI opval = LTQI (tmp_newval, 0); 1760 CPU (h_nbit) = opval; 1761 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1762 } 1763 { 1764 BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 1765 CPU (h_zbit) = opval; 1766 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1767 } 1768 { 1769 BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0))); 1770 CPU (h_vbit) = opval; 1771 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 1772 } 1773{ 1774 { 1775 BI opval = 0; 1776 CPU (h_xbit) = opval; 1777 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1778 } 1779 { 1780 BI opval = 0; 1781 SET_H_INSN_PREFIXED_P (opval); 1782 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1783 } 1784} 1785} 1786} 1787 1788#undef FLD 1789} 1790 NEXT (vpc); 1791 1792 CASE (sem, INSN_CMPCWR) : /* cmp.w $sconst16,$Rd */ 1793{ 1794 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1795 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1796#define FLD(f) abuf->fields.sfmt_bound_cw.f 1797 int UNUSED written = 0; 1798 IADDR UNUSED pc = abuf->addr; 1799 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 1800 1801{ 1802 HI tmp_tmpopd; 1803 HI tmp_tmpops; 1804 BI tmp_carry; 1805 HI tmp_newval; 1806 tmp_tmpops = TRUNCSIHI (FLD (f_indir_pc__word)); 1807 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 1808 tmp_carry = CPU (h_cbit); 1809 tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 1810((void) 0); /*nop*/ 1811{ 1812 { 1813 BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0)))); 1814 CPU (h_cbit) = opval; 1815 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 1816 } 1817 { 1818 BI opval = LTHI (tmp_newval, 0); 1819 CPU (h_nbit) = opval; 1820 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1821 } 1822 { 1823 BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 1824 CPU (h_zbit) = opval; 1825 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1826 } 1827 { 1828 BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0))); 1829 CPU (h_vbit) = opval; 1830 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 1831 } 1832{ 1833 { 1834 BI opval = 0; 1835 CPU (h_xbit) = opval; 1836 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1837 } 1838 { 1839 BI opval = 0; 1840 SET_H_INSN_PREFIXED_P (opval); 1841 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1842 } 1843} 1844} 1845} 1846 1847#undef FLD 1848} 1849 NEXT (vpc); 1850 1851 CASE (sem, INSN_CMPCDR) : /* cmp.d $const32,$Rd */ 1852{ 1853 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1854 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1855#define FLD(f) abuf->fields.sfmt_bound_cd.f 1856 int UNUSED written = 0; 1857 IADDR UNUSED pc = abuf->addr; 1858 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 1859 1860{ 1861 SI tmp_tmpopd; 1862 SI tmp_tmpops; 1863 BI tmp_carry; 1864 SI tmp_newval; 1865 tmp_tmpops = FLD (f_indir_pc__dword); 1866 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 1867 tmp_carry = CPU (h_cbit); 1868 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 1869((void) 0); /*nop*/ 1870{ 1871 { 1872 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 1873 CPU (h_cbit) = opval; 1874 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 1875 } 1876 { 1877 BI opval = LTSI (tmp_newval, 0); 1878 CPU (h_nbit) = opval; 1879 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1880 } 1881 { 1882 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 1883 CPU (h_zbit) = opval; 1884 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1885 } 1886 { 1887 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 1888 CPU (h_vbit) = opval; 1889 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 1890 } 1891{ 1892 { 1893 BI opval = 0; 1894 CPU (h_xbit) = opval; 1895 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1896 } 1897 { 1898 BI opval = 0; 1899 SET_H_INSN_PREFIXED_P (opval); 1900 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1901 } 1902} 1903} 1904} 1905 1906#undef FLD 1907} 1908 NEXT (vpc); 1909 1910 CASE (sem, INSN_CMPQ) : /* cmpq $i,$Rd */ 1911{ 1912 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1913 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1914#define FLD(f) abuf->fields.sfmt_andq.f 1915 int UNUSED written = 0; 1916 IADDR UNUSED pc = abuf->addr; 1917 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1918 1919{ 1920 SI tmp_tmpopd; 1921 SI tmp_tmpops; 1922 BI tmp_carry; 1923 SI tmp_newval; 1924 tmp_tmpops = FLD (f_s6); 1925 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 1926 tmp_carry = CPU (h_cbit); 1927 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 1928((void) 0); /*nop*/ 1929{ 1930 { 1931 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 1932 CPU (h_cbit) = opval; 1933 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 1934 } 1935 { 1936 BI opval = LTSI (tmp_newval, 0); 1937 CPU (h_nbit) = opval; 1938 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 1939 } 1940 { 1941 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 1942 CPU (h_zbit) = opval; 1943 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 1944 } 1945 { 1946 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 1947 CPU (h_vbit) = opval; 1948 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 1949 } 1950{ 1951 { 1952 BI opval = 0; 1953 CPU (h_xbit) = opval; 1954 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 1955 } 1956 { 1957 BI opval = 0; 1958 SET_H_INSN_PREFIXED_P (opval); 1959 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 1960 } 1961} 1962} 1963} 1964 1965#undef FLD 1966} 1967 NEXT (vpc); 1968 1969 CASE (sem, INSN_CMPS_M_B_M) : /* cmps-m.b [${Rs}${inc}],$Rd */ 1970{ 1971 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 1972 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 1973#define FLD(f) abuf->fields.sfmt_addc_m.f 1974 int UNUSED written = 0; 1975 IADDR UNUSED pc = abuf->addr; 1976 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 1977 1978{ 1979 SI tmp_tmpopd; 1980 SI tmp_tmpops; 1981 BI tmp_carry; 1982 SI tmp_newval; 1983 tmp_tmpops = EXTQISI (({ SI tmp_addr; 1984 QI tmp_tmp_mem; 1985 BI tmp_postinc; 1986 tmp_postinc = FLD (f_memmode); 1987; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 1988; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 1989; if (NEBI (tmp_postinc, 0)) { 1990{ 1991if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 1992 tmp_addr = ADDSI (tmp_addr, 1); 1993} 1994 { 1995 SI opval = tmp_addr; 1996 SET_H_GR (FLD (f_operand1), opval); 1997 written |= (1 << 9); 1998 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 1999 } 2000} 2001} 2002; tmp_tmp_mem; })); 2003 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 2004 tmp_carry = CPU (h_cbit); 2005 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 2006((void) 0); /*nop*/ 2007{ 2008 { 2009 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 2010 CPU (h_cbit) = opval; 2011 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 2012 } 2013 { 2014 BI opval = LTSI (tmp_newval, 0); 2015 CPU (h_nbit) = opval; 2016 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2017 } 2018 { 2019 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 2020 CPU (h_zbit) = opval; 2021 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2022 } 2023 { 2024 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 2025 CPU (h_vbit) = opval; 2026 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 2027 } 2028{ 2029 { 2030 BI opval = 0; 2031 CPU (h_xbit) = opval; 2032 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2033 } 2034 { 2035 BI opval = 0; 2036 SET_H_INSN_PREFIXED_P (opval); 2037 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2038 } 2039} 2040} 2041} 2042 2043 abuf->written = written; 2044#undef FLD 2045} 2046 NEXT (vpc); 2047 2048 CASE (sem, INSN_CMPS_M_W_M) : /* cmps-m.w [${Rs}${inc}],$Rd */ 2049{ 2050 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2051 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2052#define FLD(f) abuf->fields.sfmt_addc_m.f 2053 int UNUSED written = 0; 2054 IADDR UNUSED pc = abuf->addr; 2055 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2056 2057{ 2058 SI tmp_tmpopd; 2059 SI tmp_tmpops; 2060 BI tmp_carry; 2061 SI tmp_newval; 2062 tmp_tmpops = EXTHISI (({ SI tmp_addr; 2063 HI tmp_tmp_mem; 2064 BI tmp_postinc; 2065 tmp_postinc = FLD (f_memmode); 2066; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 2067; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 2068; if (NEBI (tmp_postinc, 0)) { 2069{ 2070if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 2071 tmp_addr = ADDSI (tmp_addr, 2); 2072} 2073 { 2074 SI opval = tmp_addr; 2075 SET_H_GR (FLD (f_operand1), opval); 2076 written |= (1 << 9); 2077 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2078 } 2079} 2080} 2081; tmp_tmp_mem; })); 2082 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 2083 tmp_carry = CPU (h_cbit); 2084 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 2085((void) 0); /*nop*/ 2086{ 2087 { 2088 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 2089 CPU (h_cbit) = opval; 2090 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 2091 } 2092 { 2093 BI opval = LTSI (tmp_newval, 0); 2094 CPU (h_nbit) = opval; 2095 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2096 } 2097 { 2098 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 2099 CPU (h_zbit) = opval; 2100 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2101 } 2102 { 2103 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 2104 CPU (h_vbit) = opval; 2105 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 2106 } 2107{ 2108 { 2109 BI opval = 0; 2110 CPU (h_xbit) = opval; 2111 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2112 } 2113 { 2114 BI opval = 0; 2115 SET_H_INSN_PREFIXED_P (opval); 2116 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2117 } 2118} 2119} 2120} 2121 2122 abuf->written = written; 2123#undef FLD 2124} 2125 NEXT (vpc); 2126 2127 CASE (sem, INSN_CMPSCBR) : /* [${Rs}${inc}],$Rd */ 2128{ 2129 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2130 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2131#define FLD(f) abuf->fields.sfmt_bound_cb.f 2132 int UNUSED written = 0; 2133 IADDR UNUSED pc = abuf->addr; 2134 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2135 2136{ 2137 SI tmp_tmpopd; 2138 SI tmp_tmpops; 2139 BI tmp_carry; 2140 SI tmp_newval; 2141 tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))); 2142 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 2143 tmp_carry = CPU (h_cbit); 2144 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 2145((void) 0); /*nop*/ 2146{ 2147 { 2148 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 2149 CPU (h_cbit) = opval; 2150 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 2151 } 2152 { 2153 BI opval = LTSI (tmp_newval, 0); 2154 CPU (h_nbit) = opval; 2155 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2156 } 2157 { 2158 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 2159 CPU (h_zbit) = opval; 2160 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2161 } 2162 { 2163 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 2164 CPU (h_vbit) = opval; 2165 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 2166 } 2167{ 2168 { 2169 BI opval = 0; 2170 CPU (h_xbit) = opval; 2171 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2172 } 2173 { 2174 BI opval = 0; 2175 SET_H_INSN_PREFIXED_P (opval); 2176 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2177 } 2178} 2179} 2180} 2181 2182#undef FLD 2183} 2184 NEXT (vpc); 2185 2186 CASE (sem, INSN_CMPSCWR) : /* [${Rs}${inc}],$Rd */ 2187{ 2188 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2189 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2190#define FLD(f) abuf->fields.sfmt_bound_cw.f 2191 int UNUSED written = 0; 2192 IADDR UNUSED pc = abuf->addr; 2193 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2194 2195{ 2196 SI tmp_tmpopd; 2197 SI tmp_tmpops; 2198 BI tmp_carry; 2199 SI tmp_newval; 2200 tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))); 2201 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 2202 tmp_carry = CPU (h_cbit); 2203 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 2204((void) 0); /*nop*/ 2205{ 2206 { 2207 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 2208 CPU (h_cbit) = opval; 2209 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 2210 } 2211 { 2212 BI opval = LTSI (tmp_newval, 0); 2213 CPU (h_nbit) = opval; 2214 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2215 } 2216 { 2217 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 2218 CPU (h_zbit) = opval; 2219 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2220 } 2221 { 2222 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 2223 CPU (h_vbit) = opval; 2224 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 2225 } 2226{ 2227 { 2228 BI opval = 0; 2229 CPU (h_xbit) = opval; 2230 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2231 } 2232 { 2233 BI opval = 0; 2234 SET_H_INSN_PREFIXED_P (opval); 2235 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2236 } 2237} 2238} 2239} 2240 2241#undef FLD 2242} 2243 NEXT (vpc); 2244 2245 CASE (sem, INSN_CMPU_M_B_M) : /* cmpu-m.b [${Rs}${inc}],$Rd */ 2246{ 2247 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2248 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2249#define FLD(f) abuf->fields.sfmt_addc_m.f 2250 int UNUSED written = 0; 2251 IADDR UNUSED pc = abuf->addr; 2252 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2253 2254{ 2255 SI tmp_tmpopd; 2256 SI tmp_tmpops; 2257 BI tmp_carry; 2258 SI tmp_newval; 2259 tmp_tmpops = ZEXTQISI (({ SI tmp_addr; 2260 QI tmp_tmp_mem; 2261 BI tmp_postinc; 2262 tmp_postinc = FLD (f_memmode); 2263; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 2264; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 2265; if (NEBI (tmp_postinc, 0)) { 2266{ 2267if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 2268 tmp_addr = ADDSI (tmp_addr, 1); 2269} 2270 { 2271 SI opval = tmp_addr; 2272 SET_H_GR (FLD (f_operand1), opval); 2273 written |= (1 << 9); 2274 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2275 } 2276} 2277} 2278; tmp_tmp_mem; })); 2279 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 2280 tmp_carry = CPU (h_cbit); 2281 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 2282((void) 0); /*nop*/ 2283{ 2284 { 2285 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 2286 CPU (h_cbit) = opval; 2287 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 2288 } 2289 { 2290 BI opval = LTSI (tmp_newval, 0); 2291 CPU (h_nbit) = opval; 2292 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2293 } 2294 { 2295 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 2296 CPU (h_zbit) = opval; 2297 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2298 } 2299 { 2300 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 2301 CPU (h_vbit) = opval; 2302 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 2303 } 2304{ 2305 { 2306 BI opval = 0; 2307 CPU (h_xbit) = opval; 2308 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2309 } 2310 { 2311 BI opval = 0; 2312 SET_H_INSN_PREFIXED_P (opval); 2313 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2314 } 2315} 2316} 2317} 2318 2319 abuf->written = written; 2320#undef FLD 2321} 2322 NEXT (vpc); 2323 2324 CASE (sem, INSN_CMPU_M_W_M) : /* cmpu-m.w [${Rs}${inc}],$Rd */ 2325{ 2326 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2327 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2328#define FLD(f) abuf->fields.sfmt_addc_m.f 2329 int UNUSED written = 0; 2330 IADDR UNUSED pc = abuf->addr; 2331 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2332 2333{ 2334 SI tmp_tmpopd; 2335 SI tmp_tmpops; 2336 BI tmp_carry; 2337 SI tmp_newval; 2338 tmp_tmpops = ZEXTHISI (({ SI tmp_addr; 2339 HI tmp_tmp_mem; 2340 BI tmp_postinc; 2341 tmp_postinc = FLD (f_memmode); 2342; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 2343; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 2344; if (NEBI (tmp_postinc, 0)) { 2345{ 2346if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 2347 tmp_addr = ADDSI (tmp_addr, 2); 2348} 2349 { 2350 SI opval = tmp_addr; 2351 SET_H_GR (FLD (f_operand1), opval); 2352 written |= (1 << 9); 2353 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2354 } 2355} 2356} 2357; tmp_tmp_mem; })); 2358 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 2359 tmp_carry = CPU (h_cbit); 2360 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 2361((void) 0); /*nop*/ 2362{ 2363 { 2364 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 2365 CPU (h_cbit) = opval; 2366 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 2367 } 2368 { 2369 BI opval = LTSI (tmp_newval, 0); 2370 CPU (h_nbit) = opval; 2371 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2372 } 2373 { 2374 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 2375 CPU (h_zbit) = opval; 2376 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2377 } 2378 { 2379 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 2380 CPU (h_vbit) = opval; 2381 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 2382 } 2383{ 2384 { 2385 BI opval = 0; 2386 CPU (h_xbit) = opval; 2387 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2388 } 2389 { 2390 BI opval = 0; 2391 SET_H_INSN_PREFIXED_P (opval); 2392 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2393 } 2394} 2395} 2396} 2397 2398 abuf->written = written; 2399#undef FLD 2400} 2401 NEXT (vpc); 2402 2403 CASE (sem, INSN_CMPUCBR) : /* [${Rs}${inc}],$Rd */ 2404{ 2405 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2406 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2407#define FLD(f) abuf->fields.sfmt_bound_cb.f 2408 int UNUSED written = 0; 2409 IADDR UNUSED pc = abuf->addr; 2410 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2411 2412{ 2413 SI tmp_tmpopd; 2414 SI tmp_tmpops; 2415 BI tmp_carry; 2416 SI tmp_newval; 2417 tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))); 2418 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 2419 tmp_carry = CPU (h_cbit); 2420 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 2421((void) 0); /*nop*/ 2422{ 2423 { 2424 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 2425 CPU (h_cbit) = opval; 2426 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 2427 } 2428 { 2429 BI opval = LTSI (tmp_newval, 0); 2430 CPU (h_nbit) = opval; 2431 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2432 } 2433 { 2434 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 2435 CPU (h_zbit) = opval; 2436 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2437 } 2438 { 2439 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 2440 CPU (h_vbit) = opval; 2441 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 2442 } 2443{ 2444 { 2445 BI opval = 0; 2446 CPU (h_xbit) = opval; 2447 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2448 } 2449 { 2450 BI opval = 0; 2451 SET_H_INSN_PREFIXED_P (opval); 2452 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2453 } 2454} 2455} 2456} 2457 2458#undef FLD 2459} 2460 NEXT (vpc); 2461 2462 CASE (sem, INSN_CMPUCWR) : /* [${Rs}${inc}],$Rd */ 2463{ 2464 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2465 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2466#define FLD(f) abuf->fields.sfmt_bound_cw.f 2467 int UNUSED written = 0; 2468 IADDR UNUSED pc = abuf->addr; 2469 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 2470 2471{ 2472 SI tmp_tmpopd; 2473 SI tmp_tmpops; 2474 BI tmp_carry; 2475 SI tmp_newval; 2476 tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))); 2477 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 2478 tmp_carry = CPU (h_cbit); 2479 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 2480((void) 0); /*nop*/ 2481{ 2482 { 2483 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 2484 CPU (h_cbit) = opval; 2485 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 2486 } 2487 { 2488 BI opval = LTSI (tmp_newval, 0); 2489 CPU (h_nbit) = opval; 2490 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2491 } 2492 { 2493 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 2494 CPU (h_zbit) = opval; 2495 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2496 } 2497 { 2498 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 2499 CPU (h_vbit) = opval; 2500 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 2501 } 2502{ 2503 { 2504 BI opval = 0; 2505 CPU (h_xbit) = opval; 2506 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2507 } 2508 { 2509 BI opval = 0; 2510 SET_H_INSN_PREFIXED_P (opval); 2511 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2512 } 2513} 2514} 2515} 2516 2517#undef FLD 2518} 2519 NEXT (vpc); 2520 2521 CASE (sem, INSN_MOVE_M_B_M) : /* move-m.b [${Rs}${inc}],${Rd} */ 2522{ 2523 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2524 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2525#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 2526 int UNUSED written = 0; 2527 IADDR UNUSED pc = abuf->addr; 2528 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2529 2530{ 2531 SI tmp_tmp; 2532 tmp_tmp = ({ SI tmp_addr; 2533 QI tmp_tmp_mem; 2534 BI tmp_postinc; 2535 tmp_postinc = FLD (f_memmode); 2536; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 2537; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 2538; if (NEBI (tmp_postinc, 0)) { 2539{ 2540if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 2541 tmp_addr = ADDSI (tmp_addr, 1); 2542} 2543 { 2544 SI opval = tmp_addr; 2545 SET_H_GR (FLD (f_operand1), opval); 2546 written |= (1 << 10); 2547 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2548 } 2549} 2550} 2551; tmp_tmp_mem; }); 2552{ 2553 SI tmp_oldregval; 2554 tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2)))); 2555 { 2556 SI opval = ORSI (ANDSI (tmp_tmp, 255), ANDSI (tmp_oldregval, 0xffffff00)); 2557 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 2558 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2559 } 2560} 2561{ 2562 { 2563 BI opval = LTQI (tmp_tmp, 0); 2564 CPU (h_nbit) = opval; 2565 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2566 } 2567 { 2568 BI opval = ANDIF (EQQI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 2569 CPU (h_zbit) = opval; 2570 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2571 } 2572SET_H_CBIT_MOVE (0); 2573SET_H_VBIT_MOVE (0); 2574{ 2575 { 2576 BI opval = 0; 2577 CPU (h_xbit) = opval; 2578 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2579 } 2580 { 2581 BI opval = 0; 2582 SET_H_INSN_PREFIXED_P (opval); 2583 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2584 } 2585} 2586} 2587} 2588 2589 abuf->written = written; 2590#undef FLD 2591} 2592 NEXT (vpc); 2593 2594 CASE (sem, INSN_MOVE_M_W_M) : /* move-m.w [${Rs}${inc}],${Rd} */ 2595{ 2596 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2597 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2598#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 2599 int UNUSED written = 0; 2600 IADDR UNUSED pc = abuf->addr; 2601 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2602 2603{ 2604 SI tmp_tmp; 2605 tmp_tmp = ({ SI tmp_addr; 2606 HI tmp_tmp_mem; 2607 BI tmp_postinc; 2608 tmp_postinc = FLD (f_memmode); 2609; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 2610; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 2611; if (NEBI (tmp_postinc, 0)) { 2612{ 2613if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 2614 tmp_addr = ADDSI (tmp_addr, 2); 2615} 2616 { 2617 SI opval = tmp_addr; 2618 SET_H_GR (FLD (f_operand1), opval); 2619 written |= (1 << 10); 2620 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2621 } 2622} 2623} 2624; tmp_tmp_mem; }); 2625{ 2626 SI tmp_oldregval; 2627 tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2)))); 2628 { 2629 SI opval = ORSI (ANDSI (tmp_tmp, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 2630 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 2631 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2632 } 2633} 2634{ 2635 { 2636 BI opval = LTHI (tmp_tmp, 0); 2637 CPU (h_nbit) = opval; 2638 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2639 } 2640 { 2641 BI opval = ANDIF (EQHI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 2642 CPU (h_zbit) = opval; 2643 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2644 } 2645SET_H_CBIT_MOVE (0); 2646SET_H_VBIT_MOVE (0); 2647{ 2648 { 2649 BI opval = 0; 2650 CPU (h_xbit) = opval; 2651 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2652 } 2653 { 2654 BI opval = 0; 2655 SET_H_INSN_PREFIXED_P (opval); 2656 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2657 } 2658} 2659} 2660} 2661 2662 abuf->written = written; 2663#undef FLD 2664} 2665 NEXT (vpc); 2666 2667 CASE (sem, INSN_MOVE_M_D_M) : /* move-m.d [${Rs}${inc}],${Rd} */ 2668{ 2669 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2670 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2671#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 2672 int UNUSED written = 0; 2673 IADDR UNUSED pc = abuf->addr; 2674 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2675 2676{ 2677 SI tmp_tmp; 2678 tmp_tmp = ({ SI tmp_addr; 2679 SI tmp_tmp_mem; 2680 BI tmp_postinc; 2681 tmp_postinc = FLD (f_memmode); 2682; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 2683; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 2684; if (NEBI (tmp_postinc, 0)) { 2685{ 2686if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 2687 tmp_addr = ADDSI (tmp_addr, 4); 2688} 2689 { 2690 SI opval = tmp_addr; 2691 SET_H_GR (FLD (f_operand1), opval); 2692 written |= (1 << 9); 2693 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2694 } 2695} 2696} 2697; tmp_tmp_mem; }); 2698 { 2699 SI opval = tmp_tmp; 2700 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 2701 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2702 } 2703{ 2704 { 2705 BI opval = LTSI (tmp_tmp, 0); 2706 CPU (h_nbit) = opval; 2707 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2708 } 2709 { 2710 BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 2711 CPU (h_zbit) = opval; 2712 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2713 } 2714SET_H_CBIT_MOVE (0); 2715SET_H_VBIT_MOVE (0); 2716{ 2717 { 2718 BI opval = 0; 2719 CPU (h_xbit) = opval; 2720 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2721 } 2722 { 2723 BI opval = 0; 2724 SET_H_INSN_PREFIXED_P (opval); 2725 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2726 } 2727} 2728} 2729} 2730 2731 abuf->written = written; 2732#undef FLD 2733} 2734 NEXT (vpc); 2735 2736 CASE (sem, INSN_MOVS_M_B_M) : /* movs-m.b [${Rs}${inc}],${Rd} */ 2737{ 2738 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2739 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2740#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f 2741 int UNUSED written = 0; 2742 IADDR UNUSED pc = abuf->addr; 2743 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2744 2745{ 2746 SI tmp_tmp; 2747 tmp_tmp = EXTQISI (({ SI tmp_addr; 2748 QI tmp_tmp_mem; 2749 BI tmp_postinc; 2750 tmp_postinc = FLD (f_memmode); 2751; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 2752; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 2753; if (NEBI (tmp_postinc, 0)) { 2754{ 2755if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 2756 tmp_addr = ADDSI (tmp_addr, 1); 2757} 2758 { 2759 SI opval = tmp_addr; 2760 SET_H_GR (FLD (f_operand1), opval); 2761 written |= (1 << 8); 2762 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2763 } 2764} 2765} 2766; tmp_tmp_mem; })); 2767if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) { 2768 { 2769 SI opval = tmp_tmp; 2770 SET_H_GR (FLD (f_operand1), opval); 2771 written |= (1 << 8); 2772 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2773 } 2774} else { 2775 { 2776 SI opval = tmp_tmp; 2777 SET_H_GR (FLD (f_operand2), opval); 2778 written |= (1 << 7); 2779 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2780 } 2781} 2782{ 2783 { 2784 BI opval = LTSI (tmp_tmp, 0); 2785 CPU (h_nbit) = opval; 2786 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2787 } 2788 { 2789 BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 2790 CPU (h_zbit) = opval; 2791 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2792 } 2793SET_H_CBIT_MOVE (0); 2794SET_H_VBIT_MOVE (0); 2795{ 2796 { 2797 BI opval = 0; 2798 CPU (h_xbit) = opval; 2799 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2800 } 2801 { 2802 BI opval = 0; 2803 SET_H_INSN_PREFIXED_P (opval); 2804 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2805 } 2806} 2807} 2808} 2809 2810 abuf->written = written; 2811#undef FLD 2812} 2813 NEXT (vpc); 2814 2815 CASE (sem, INSN_MOVS_M_W_M) : /* movs-m.w [${Rs}${inc}],${Rd} */ 2816{ 2817 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2818 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2819#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f 2820 int UNUSED written = 0; 2821 IADDR UNUSED pc = abuf->addr; 2822 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2823 2824{ 2825 SI tmp_tmp; 2826 tmp_tmp = EXTHISI (({ SI tmp_addr; 2827 HI tmp_tmp_mem; 2828 BI tmp_postinc; 2829 tmp_postinc = FLD (f_memmode); 2830; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 2831; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 2832; if (NEBI (tmp_postinc, 0)) { 2833{ 2834if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 2835 tmp_addr = ADDSI (tmp_addr, 2); 2836} 2837 { 2838 SI opval = tmp_addr; 2839 SET_H_GR (FLD (f_operand1), opval); 2840 written |= (1 << 8); 2841 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2842 } 2843} 2844} 2845; tmp_tmp_mem; })); 2846if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) { 2847 { 2848 SI opval = tmp_tmp; 2849 SET_H_GR (FLD (f_operand1), opval); 2850 written |= (1 << 8); 2851 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2852 } 2853} else { 2854 { 2855 SI opval = tmp_tmp; 2856 SET_H_GR (FLD (f_operand2), opval); 2857 written |= (1 << 7); 2858 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2859 } 2860} 2861{ 2862 { 2863 BI opval = LTSI (tmp_tmp, 0); 2864 CPU (h_nbit) = opval; 2865 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2866 } 2867 { 2868 BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 2869 CPU (h_zbit) = opval; 2870 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2871 } 2872SET_H_CBIT_MOVE (0); 2873SET_H_VBIT_MOVE (0); 2874{ 2875 { 2876 BI opval = 0; 2877 CPU (h_xbit) = opval; 2878 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2879 } 2880 { 2881 BI opval = 0; 2882 SET_H_INSN_PREFIXED_P (opval); 2883 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2884 } 2885} 2886} 2887} 2888 2889 abuf->written = written; 2890#undef FLD 2891} 2892 NEXT (vpc); 2893 2894 CASE (sem, INSN_MOVU_M_B_M) : /* movu-m.b [${Rs}${inc}],${Rd} */ 2895{ 2896 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2897 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2898#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f 2899 int UNUSED written = 0; 2900 IADDR UNUSED pc = abuf->addr; 2901 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2902 2903{ 2904 SI tmp_tmp; 2905 tmp_tmp = ZEXTQISI (({ SI tmp_addr; 2906 QI tmp_tmp_mem; 2907 BI tmp_postinc; 2908 tmp_postinc = FLD (f_memmode); 2909; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 2910; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 2911; if (NEBI (tmp_postinc, 0)) { 2912{ 2913if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 2914 tmp_addr = ADDSI (tmp_addr, 1); 2915} 2916 { 2917 SI opval = tmp_addr; 2918 SET_H_GR (FLD (f_operand1), opval); 2919 written |= (1 << 8); 2920 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2921 } 2922} 2923} 2924; tmp_tmp_mem; })); 2925if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) { 2926 { 2927 SI opval = tmp_tmp; 2928 SET_H_GR (FLD (f_operand1), opval); 2929 written |= (1 << 8); 2930 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2931 } 2932} else { 2933 { 2934 SI opval = tmp_tmp; 2935 SET_H_GR (FLD (f_operand2), opval); 2936 written |= (1 << 7); 2937 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 2938 } 2939} 2940{ 2941 { 2942 BI opval = LTSI (tmp_tmp, 0); 2943 CPU (h_nbit) = opval; 2944 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 2945 } 2946 { 2947 BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 2948 CPU (h_zbit) = opval; 2949 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 2950 } 2951SET_H_CBIT_MOVE (0); 2952SET_H_VBIT_MOVE (0); 2953{ 2954 { 2955 BI opval = 0; 2956 CPU (h_xbit) = opval; 2957 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 2958 } 2959 { 2960 BI opval = 0; 2961 SET_H_INSN_PREFIXED_P (opval); 2962 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 2963 } 2964} 2965} 2966} 2967 2968 abuf->written = written; 2969#undef FLD 2970} 2971 NEXT (vpc); 2972 2973 CASE (sem, INSN_MOVU_M_W_M) : /* movu-m.w [${Rs}${inc}],${Rd} */ 2974{ 2975 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 2976 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 2977#define FLD(f) abuf->fields.sfmt_movs_m_b_m.f 2978 int UNUSED written = 0; 2979 IADDR UNUSED pc = abuf->addr; 2980 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 2981 2982{ 2983 SI tmp_tmp; 2984 tmp_tmp = ZEXTHISI (({ SI tmp_addr; 2985 HI tmp_tmp_mem; 2986 BI tmp_postinc; 2987 tmp_postinc = FLD (f_memmode); 2988; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 2989; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 2990; if (NEBI (tmp_postinc, 0)) { 2991{ 2992if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 2993 tmp_addr = ADDSI (tmp_addr, 2); 2994} 2995 { 2996 SI opval = tmp_addr; 2997 SET_H_GR (FLD (f_operand1), opval); 2998 written |= (1 << 8); 2999 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3000 } 3001} 3002} 3003; tmp_tmp_mem; })); 3004if (ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) { 3005 { 3006 SI opval = tmp_tmp; 3007 SET_H_GR (FLD (f_operand1), opval); 3008 written |= (1 << 8); 3009 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3010 } 3011} else { 3012 { 3013 SI opval = tmp_tmp; 3014 SET_H_GR (FLD (f_operand2), opval); 3015 written |= (1 << 7); 3016 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3017 } 3018} 3019{ 3020 { 3021 BI opval = LTSI (tmp_tmp, 0); 3022 CPU (h_nbit) = opval; 3023 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 3024 } 3025 { 3026 BI opval = ANDIF (EQSI (tmp_tmp, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 3027 CPU (h_zbit) = opval; 3028 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 3029 } 3030SET_H_CBIT_MOVE (0); 3031SET_H_VBIT_MOVE (0); 3032{ 3033 { 3034 BI opval = 0; 3035 CPU (h_xbit) = opval; 3036 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3037 } 3038 { 3039 BI opval = 0; 3040 SET_H_INSN_PREFIXED_P (opval); 3041 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3042 } 3043} 3044} 3045} 3046 3047 abuf->written = written; 3048#undef FLD 3049} 3050 NEXT (vpc); 3051 3052 CASE (sem, INSN_MOVE_R_SPRV32) : /* move ${Rs},${Pd} */ 3053{ 3054 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3055 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3056#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f 3057 int UNUSED written = 0; 3058 IADDR UNUSED pc = abuf->addr; 3059 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 3060 3061{ 3062 SI tmp_tmp; 3063 SI tmp_rno; 3064 tmp_tmp = GET_H_GR (FLD (f_operand1)); 3065 tmp_rno = FLD (f_operand2); 3066if (ORIF (ORIF (EQSI (tmp_rno, 0), EQSI (tmp_rno, 1)), ORIF (EQSI (tmp_rno, 4), EQSI (tmp_rno, 8)))) { 3067cgen_rtx_error (current_cpu, "move-r-spr: trying to set a read-only special register"); 3068} 3069 else { 3070 { 3071 SI opval = tmp_tmp; 3072 SET_H_SR (FLD (f_operand2), opval); 3073 written |= (1 << 2); 3074 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3075 } 3076} 3077{ 3078 { 3079 BI opval = 0; 3080 CPU (h_xbit) = opval; 3081 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3082 } 3083 { 3084 BI opval = 0; 3085 SET_H_INSN_PREFIXED_P (opval); 3086 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3087 } 3088} 3089} 3090 3091 abuf->written = written; 3092#undef FLD 3093} 3094 NEXT (vpc); 3095 3096 CASE (sem, INSN_MOVE_SPR_RV32) : /* move ${Ps},${Rd-sfield} */ 3097{ 3098 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3099 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3100#define FLD(f) abuf->fields.sfmt_mcp.f 3101 int UNUSED written = 0; 3102 IADDR UNUSED pc = abuf->addr; 3103 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 3104 3105{ 3106 SI tmp_grno; 3107 SI tmp_prno; 3108 SI tmp_newval; 3109 tmp_prno = FLD (f_operand2); 3110 tmp_newval = GET_H_SR (FLD (f_operand2)); 3111if (EQSI (tmp_prno, 2)) { 3112{ 3113 SI tmp_oldregval; 3114 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); 3115 { 3116 SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); 3117 SET_H_GR (FLD (f_operand1), opval); 3118 written |= (1 << 4); 3119 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3120 } 3121} 3122} 3123 else if (EQSI (tmp_prno, 3)) { 3124{ 3125 SI tmp_oldregval; 3126 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); 3127 { 3128 SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); 3129 SET_H_GR (FLD (f_operand1), opval); 3130 written |= (1 << 4); 3131 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3132 } 3133} 3134} 3135 else if (EQSI (tmp_prno, 5)) { 3136 { 3137 SI opval = tmp_newval; 3138 SET_H_GR (FLD (f_operand1), opval); 3139 written |= (1 << 4); 3140 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3141 } 3142} 3143 else if (EQSI (tmp_prno, 6)) { 3144 { 3145 SI opval = tmp_newval; 3146 SET_H_GR (FLD (f_operand1), opval); 3147 written |= (1 << 4); 3148 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3149 } 3150} 3151 else if (EQSI (tmp_prno, 7)) { 3152 { 3153 SI opval = tmp_newval; 3154 SET_H_GR (FLD (f_operand1), opval); 3155 written |= (1 << 4); 3156 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3157 } 3158} 3159 else if (EQSI (tmp_prno, 9)) { 3160 { 3161 SI opval = tmp_newval; 3162 SET_H_GR (FLD (f_operand1), opval); 3163 written |= (1 << 4); 3164 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3165 } 3166} 3167 else if (EQSI (tmp_prno, 10)) { 3168 { 3169 SI opval = tmp_newval; 3170 SET_H_GR (FLD (f_operand1), opval); 3171 written |= (1 << 4); 3172 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3173 } 3174} 3175 else if (EQSI (tmp_prno, 11)) { 3176 { 3177 SI opval = tmp_newval; 3178 SET_H_GR (FLD (f_operand1), opval); 3179 written |= (1 << 4); 3180 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3181 } 3182} 3183 else if (EQSI (tmp_prno, 12)) { 3184 { 3185 SI opval = tmp_newval; 3186 SET_H_GR (FLD (f_operand1), opval); 3187 written |= (1 << 4); 3188 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3189 } 3190} 3191 else if (EQSI (tmp_prno, 13)) { 3192 { 3193 SI opval = tmp_newval; 3194 SET_H_GR (FLD (f_operand1), opval); 3195 written |= (1 << 4); 3196 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3197 } 3198} 3199 else if (EQSI (tmp_prno, 14)) { 3200 { 3201 SI opval = tmp_newval; 3202 SET_H_GR (FLD (f_operand1), opval); 3203 written |= (1 << 4); 3204 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3205 } 3206} 3207 else if (EQSI (tmp_prno, 15)) { 3208 { 3209 SI opval = tmp_newval; 3210 SET_H_GR (FLD (f_operand1), opval); 3211 written |= (1 << 4); 3212 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3213 } 3214} 3215 else if (EQSI (tmp_prno, 0)) { 3216{ 3217 SI tmp_oldregval; 3218 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); 3219 { 3220 SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); 3221 SET_H_GR (FLD (f_operand1), opval); 3222 written |= (1 << 4); 3223 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3224 } 3225} 3226} 3227 else if (EQSI (tmp_prno, 1)) { 3228{ 3229 SI tmp_oldregval; 3230 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); 3231 { 3232 SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); 3233 SET_H_GR (FLD (f_operand1), opval); 3234 written |= (1 << 4); 3235 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3236 } 3237} 3238} 3239 else if (EQSI (tmp_prno, 4)) { 3240{ 3241 SI tmp_oldregval; 3242 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand1)); 3243 { 3244 SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 3245 SET_H_GR (FLD (f_operand1), opval); 3246 written |= (1 << 4); 3247 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3248 } 3249} 3250} 3251 else if (EQSI (tmp_prno, 8)) { 3252 { 3253 SI opval = tmp_newval; 3254 SET_H_GR (FLD (f_operand1), opval); 3255 written |= (1 << 4); 3256 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3257 } 3258} 3259 else { 3260cgen_rtx_error (current_cpu, "move-spr-r from unimplemented register"); 3261} 3262{ 3263 { 3264 BI opval = 0; 3265 CPU (h_xbit) = opval; 3266 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3267 } 3268 { 3269 BI opval = 0; 3270 SET_H_INSN_PREFIXED_P (opval); 3271 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3272 } 3273} 3274} 3275 3276 abuf->written = written; 3277#undef FLD 3278} 3279 NEXT (vpc); 3280 3281 CASE (sem, INSN_MOVE_M_SPRV32) : /* move [${Rs}${inc}],${Pd} */ 3282{ 3283 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3284 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3285#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f 3286 int UNUSED written = 0; 3287 IADDR UNUSED pc = abuf->addr; 3288 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 3289 3290{ 3291 SI tmp_rno; 3292 SI tmp_newval; 3293 tmp_rno = FLD (f_operand2); 3294if (EQSI (tmp_rno, 2)) { 3295 tmp_newval = EXTQISI (({ SI tmp_addr; 3296 QI tmp_tmp_mem; 3297 BI tmp_postinc; 3298 tmp_postinc = FLD (f_memmode); 3299; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 3300; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 3301; if (NEBI (tmp_postinc, 0)) { 3302{ 3303if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 3304 tmp_addr = ADDSI (tmp_addr, 1); 3305} 3306 { 3307 SI opval = tmp_addr; 3308 SET_H_GR (FLD (f_operand1), opval); 3309 written |= (1 << 8); 3310 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3311 } 3312} 3313} 3314; tmp_tmp_mem; })); 3315} 3316 else if (EQSI (tmp_rno, 3)) { 3317 tmp_newval = EXTQISI (({ SI tmp_addr; 3318 QI tmp_tmp_mem; 3319 BI tmp_postinc; 3320 tmp_postinc = FLD (f_memmode); 3321; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 3322; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 3323; if (NEBI (tmp_postinc, 0)) { 3324{ 3325if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 3326 tmp_addr = ADDSI (tmp_addr, 1); 3327} 3328 { 3329 SI opval = tmp_addr; 3330 SET_H_GR (FLD (f_operand1), opval); 3331 written |= (1 << 8); 3332 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3333 } 3334} 3335} 3336; tmp_tmp_mem; })); 3337} 3338 else if (EQSI (tmp_rno, 5)) { 3339 tmp_newval = ({ SI tmp_addr; 3340 SI tmp_tmp_mem; 3341 BI tmp_postinc; 3342 tmp_postinc = FLD (f_memmode); 3343; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 3344; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 3345; if (NEBI (tmp_postinc, 0)) { 3346{ 3347if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 3348 tmp_addr = ADDSI (tmp_addr, 4); 3349} 3350 { 3351 SI opval = tmp_addr; 3352 SET_H_GR (FLD (f_operand1), opval); 3353 written |= (1 << 8); 3354 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3355 } 3356} 3357} 3358; tmp_tmp_mem; }); 3359} 3360 else if (EQSI (tmp_rno, 6)) { 3361 tmp_newval = ({ SI tmp_addr; 3362 SI tmp_tmp_mem; 3363 BI tmp_postinc; 3364 tmp_postinc = FLD (f_memmode); 3365; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 3366; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 3367; if (NEBI (tmp_postinc, 0)) { 3368{ 3369if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 3370 tmp_addr = ADDSI (tmp_addr, 4); 3371} 3372 { 3373 SI opval = tmp_addr; 3374 SET_H_GR (FLD (f_operand1), opval); 3375 written |= (1 << 8); 3376 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3377 } 3378} 3379} 3380; tmp_tmp_mem; }); 3381} 3382 else if (EQSI (tmp_rno, 7)) { 3383 tmp_newval = ({ SI tmp_addr; 3384 SI tmp_tmp_mem; 3385 BI tmp_postinc; 3386 tmp_postinc = FLD (f_memmode); 3387; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 3388; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 3389; if (NEBI (tmp_postinc, 0)) { 3390{ 3391if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 3392 tmp_addr = ADDSI (tmp_addr, 4); 3393} 3394 { 3395 SI opval = tmp_addr; 3396 SET_H_GR (FLD (f_operand1), opval); 3397 written |= (1 << 8); 3398 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3399 } 3400} 3401} 3402; tmp_tmp_mem; }); 3403} 3404 else if (EQSI (tmp_rno, 9)) { 3405 tmp_newval = ({ SI tmp_addr; 3406 SI tmp_tmp_mem; 3407 BI tmp_postinc; 3408 tmp_postinc = FLD (f_memmode); 3409; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 3410; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 3411; if (NEBI (tmp_postinc, 0)) { 3412{ 3413if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 3414 tmp_addr = ADDSI (tmp_addr, 4); 3415} 3416 { 3417 SI opval = tmp_addr; 3418 SET_H_GR (FLD (f_operand1), opval); 3419 written |= (1 << 8); 3420 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3421 } 3422} 3423} 3424; tmp_tmp_mem; }); 3425} 3426 else if (EQSI (tmp_rno, 10)) { 3427 tmp_newval = ({ SI tmp_addr; 3428 SI tmp_tmp_mem; 3429 BI tmp_postinc; 3430 tmp_postinc = FLD (f_memmode); 3431; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 3432; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 3433; if (NEBI (tmp_postinc, 0)) { 3434{ 3435if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 3436 tmp_addr = ADDSI (tmp_addr, 4); 3437} 3438 { 3439 SI opval = tmp_addr; 3440 SET_H_GR (FLD (f_operand1), opval); 3441 written |= (1 << 8); 3442 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3443 } 3444} 3445} 3446; tmp_tmp_mem; }); 3447} 3448 else if (EQSI (tmp_rno, 11)) { 3449 tmp_newval = ({ SI tmp_addr; 3450 SI tmp_tmp_mem; 3451 BI tmp_postinc; 3452 tmp_postinc = FLD (f_memmode); 3453; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 3454; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 3455; if (NEBI (tmp_postinc, 0)) { 3456{ 3457if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 3458 tmp_addr = ADDSI (tmp_addr, 4); 3459} 3460 { 3461 SI opval = tmp_addr; 3462 SET_H_GR (FLD (f_operand1), opval); 3463 written |= (1 << 8); 3464 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3465 } 3466} 3467} 3468; tmp_tmp_mem; }); 3469} 3470 else if (EQSI (tmp_rno, 12)) { 3471 tmp_newval = ({ SI tmp_addr; 3472 SI tmp_tmp_mem; 3473 BI tmp_postinc; 3474 tmp_postinc = FLD (f_memmode); 3475; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 3476; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 3477; if (NEBI (tmp_postinc, 0)) { 3478{ 3479if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 3480 tmp_addr = ADDSI (tmp_addr, 4); 3481} 3482 { 3483 SI opval = tmp_addr; 3484 SET_H_GR (FLD (f_operand1), opval); 3485 written |= (1 << 8); 3486 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3487 } 3488} 3489} 3490; tmp_tmp_mem; }); 3491} 3492 else if (EQSI (tmp_rno, 13)) { 3493 tmp_newval = ({ SI tmp_addr; 3494 SI tmp_tmp_mem; 3495 BI tmp_postinc; 3496 tmp_postinc = FLD (f_memmode); 3497; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 3498; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 3499; if (NEBI (tmp_postinc, 0)) { 3500{ 3501if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 3502 tmp_addr = ADDSI (tmp_addr, 4); 3503} 3504 { 3505 SI opval = tmp_addr; 3506 SET_H_GR (FLD (f_operand1), opval); 3507 written |= (1 << 8); 3508 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3509 } 3510} 3511} 3512; tmp_tmp_mem; }); 3513} 3514 else if (EQSI (tmp_rno, 14)) { 3515 tmp_newval = ({ SI tmp_addr; 3516 SI tmp_tmp_mem; 3517 BI tmp_postinc; 3518 tmp_postinc = FLD (f_memmode); 3519; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 3520; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 3521; if (NEBI (tmp_postinc, 0)) { 3522{ 3523if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 3524 tmp_addr = ADDSI (tmp_addr, 4); 3525} 3526 { 3527 SI opval = tmp_addr; 3528 SET_H_GR (FLD (f_operand1), opval); 3529 written |= (1 << 8); 3530 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3531 } 3532} 3533} 3534; tmp_tmp_mem; }); 3535} 3536 else if (EQSI (tmp_rno, 15)) { 3537 tmp_newval = ({ SI tmp_addr; 3538 SI tmp_tmp_mem; 3539 BI tmp_postinc; 3540 tmp_postinc = FLD (f_memmode); 3541; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 3542; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 3543; if (NEBI (tmp_postinc, 0)) { 3544{ 3545if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 3546 tmp_addr = ADDSI (tmp_addr, 4); 3547} 3548 { 3549 SI opval = tmp_addr; 3550 SET_H_GR (FLD (f_operand1), opval); 3551 written |= (1 << 8); 3552 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 3553 } 3554} 3555} 3556; tmp_tmp_mem; }); 3557} 3558 else { 3559cgen_rtx_error (current_cpu, "Trying to set unimplemented special register"); 3560} 3561 { 3562 SI opval = tmp_newval; 3563 SET_H_SR (FLD (f_operand2), opval); 3564 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3565 } 3566{ 3567 { 3568 BI opval = 0; 3569 CPU (h_xbit) = opval; 3570 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3571 } 3572 { 3573 BI opval = 0; 3574 SET_H_INSN_PREFIXED_P (opval); 3575 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3576 } 3577} 3578} 3579 3580 abuf->written = written; 3581#undef FLD 3582} 3583 NEXT (vpc); 3584 3585 CASE (sem, INSN_MOVE_C_SPRV32_P2) : /* move ${const32},${Pd} */ 3586{ 3587 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3588 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3589#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 3590 int UNUSED written = 0; 3591 IADDR UNUSED pc = abuf->addr; 3592 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 3593 3594{ 3595 { 3596 SI opval = FLD (f_indir_pc__dword); 3597 SET_H_SR (FLD (f_operand2), opval); 3598 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3599 } 3600{ 3601 { 3602 BI opval = 0; 3603 CPU (h_xbit) = opval; 3604 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3605 } 3606 { 3607 BI opval = 0; 3608 SET_H_INSN_PREFIXED_P (opval); 3609 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3610 } 3611} 3612} 3613 3614#undef FLD 3615} 3616 NEXT (vpc); 3617 3618 CASE (sem, INSN_MOVE_C_SPRV32_P3) : /* move ${const32},${Pd} */ 3619{ 3620 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3621 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3622#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 3623 int UNUSED written = 0; 3624 IADDR UNUSED pc = abuf->addr; 3625 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 3626 3627{ 3628 { 3629 SI opval = FLD (f_indir_pc__dword); 3630 SET_H_SR (FLD (f_operand2), opval); 3631 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3632 } 3633{ 3634 { 3635 BI opval = 0; 3636 CPU (h_xbit) = opval; 3637 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3638 } 3639 { 3640 BI opval = 0; 3641 SET_H_INSN_PREFIXED_P (opval); 3642 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3643 } 3644} 3645} 3646 3647#undef FLD 3648} 3649 NEXT (vpc); 3650 3651 CASE (sem, INSN_MOVE_C_SPRV32_P5) : /* move ${const32},${Pd} */ 3652{ 3653 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3654 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3655#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 3656 int UNUSED written = 0; 3657 IADDR UNUSED pc = abuf->addr; 3658 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 3659 3660{ 3661 { 3662 SI opval = FLD (f_indir_pc__dword); 3663 SET_H_SR (FLD (f_operand2), opval); 3664 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3665 } 3666{ 3667 { 3668 BI opval = 0; 3669 CPU (h_xbit) = opval; 3670 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3671 } 3672 { 3673 BI opval = 0; 3674 SET_H_INSN_PREFIXED_P (opval); 3675 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3676 } 3677} 3678} 3679 3680#undef FLD 3681} 3682 NEXT (vpc); 3683 3684 CASE (sem, INSN_MOVE_C_SPRV32_P6) : /* move ${const32},${Pd} */ 3685{ 3686 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3687 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3688#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 3689 int UNUSED written = 0; 3690 IADDR UNUSED pc = abuf->addr; 3691 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 3692 3693{ 3694 { 3695 SI opval = FLD (f_indir_pc__dword); 3696 SET_H_SR (FLD (f_operand2), opval); 3697 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3698 } 3699{ 3700 { 3701 BI opval = 0; 3702 CPU (h_xbit) = opval; 3703 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3704 } 3705 { 3706 BI opval = 0; 3707 SET_H_INSN_PREFIXED_P (opval); 3708 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3709 } 3710} 3711} 3712 3713#undef FLD 3714} 3715 NEXT (vpc); 3716 3717 CASE (sem, INSN_MOVE_C_SPRV32_P7) : /* move ${const32},${Pd} */ 3718{ 3719 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3720 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3721#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 3722 int UNUSED written = 0; 3723 IADDR UNUSED pc = abuf->addr; 3724 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 3725 3726{ 3727 { 3728 SI opval = FLD (f_indir_pc__dword); 3729 SET_H_SR (FLD (f_operand2), opval); 3730 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3731 } 3732{ 3733 { 3734 BI opval = 0; 3735 CPU (h_xbit) = opval; 3736 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3737 } 3738 { 3739 BI opval = 0; 3740 SET_H_INSN_PREFIXED_P (opval); 3741 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3742 } 3743} 3744} 3745 3746#undef FLD 3747} 3748 NEXT (vpc); 3749 3750 CASE (sem, INSN_MOVE_C_SPRV32_P9) : /* move ${const32},${Pd} */ 3751{ 3752 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3753 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3754#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 3755 int UNUSED written = 0; 3756 IADDR UNUSED pc = abuf->addr; 3757 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 3758 3759{ 3760 { 3761 SI opval = FLD (f_indir_pc__dword); 3762 SET_H_SR (FLD (f_operand2), opval); 3763 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3764 } 3765{ 3766 { 3767 BI opval = 0; 3768 CPU (h_xbit) = opval; 3769 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3770 } 3771 { 3772 BI opval = 0; 3773 SET_H_INSN_PREFIXED_P (opval); 3774 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3775 } 3776} 3777} 3778 3779#undef FLD 3780} 3781 NEXT (vpc); 3782 3783 CASE (sem, INSN_MOVE_C_SPRV32_P10) : /* move ${const32},${Pd} */ 3784{ 3785 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3786 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3787#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 3788 int UNUSED written = 0; 3789 IADDR UNUSED pc = abuf->addr; 3790 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 3791 3792{ 3793 { 3794 SI opval = FLD (f_indir_pc__dword); 3795 SET_H_SR (FLD (f_operand2), opval); 3796 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3797 } 3798{ 3799 { 3800 BI opval = 0; 3801 CPU (h_xbit) = opval; 3802 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3803 } 3804 { 3805 BI opval = 0; 3806 SET_H_INSN_PREFIXED_P (opval); 3807 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3808 } 3809} 3810} 3811 3812#undef FLD 3813} 3814 NEXT (vpc); 3815 3816 CASE (sem, INSN_MOVE_C_SPRV32_P11) : /* move ${const32},${Pd} */ 3817{ 3818 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3819 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3820#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 3821 int UNUSED written = 0; 3822 IADDR UNUSED pc = abuf->addr; 3823 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 3824 3825{ 3826 { 3827 SI opval = FLD (f_indir_pc__dword); 3828 SET_H_SR (FLD (f_operand2), opval); 3829 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3830 } 3831{ 3832 { 3833 BI opval = 0; 3834 CPU (h_xbit) = opval; 3835 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3836 } 3837 { 3838 BI opval = 0; 3839 SET_H_INSN_PREFIXED_P (opval); 3840 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3841 } 3842} 3843} 3844 3845#undef FLD 3846} 3847 NEXT (vpc); 3848 3849 CASE (sem, INSN_MOVE_C_SPRV32_P12) : /* move ${const32},${Pd} */ 3850{ 3851 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3852 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3853#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 3854 int UNUSED written = 0; 3855 IADDR UNUSED pc = abuf->addr; 3856 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 3857 3858{ 3859 { 3860 SI opval = FLD (f_indir_pc__dword); 3861 SET_H_SR (FLD (f_operand2), opval); 3862 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3863 } 3864{ 3865 { 3866 BI opval = 0; 3867 CPU (h_xbit) = opval; 3868 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3869 } 3870 { 3871 BI opval = 0; 3872 SET_H_INSN_PREFIXED_P (opval); 3873 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3874 } 3875} 3876} 3877 3878#undef FLD 3879} 3880 NEXT (vpc); 3881 3882 CASE (sem, INSN_MOVE_C_SPRV32_P13) : /* move ${const32},${Pd} */ 3883{ 3884 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3885 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3886#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 3887 int UNUSED written = 0; 3888 IADDR UNUSED pc = abuf->addr; 3889 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 3890 3891{ 3892 { 3893 SI opval = FLD (f_indir_pc__dword); 3894 SET_H_SR (FLD (f_operand2), opval); 3895 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3896 } 3897{ 3898 { 3899 BI opval = 0; 3900 CPU (h_xbit) = opval; 3901 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3902 } 3903 { 3904 BI opval = 0; 3905 SET_H_INSN_PREFIXED_P (opval); 3906 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3907 } 3908} 3909} 3910 3911#undef FLD 3912} 3913 NEXT (vpc); 3914 3915 CASE (sem, INSN_MOVE_C_SPRV32_P14) : /* move ${const32},${Pd} */ 3916{ 3917 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3918 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3919#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 3920 int UNUSED written = 0; 3921 IADDR UNUSED pc = abuf->addr; 3922 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 3923 3924{ 3925 { 3926 SI opval = FLD (f_indir_pc__dword); 3927 SET_H_SR (FLD (f_operand2), opval); 3928 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3929 } 3930{ 3931 { 3932 BI opval = 0; 3933 CPU (h_xbit) = opval; 3934 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3935 } 3936 { 3937 BI opval = 0; 3938 SET_H_INSN_PREFIXED_P (opval); 3939 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3940 } 3941} 3942} 3943 3944#undef FLD 3945} 3946 NEXT (vpc); 3947 3948 CASE (sem, INSN_MOVE_C_SPRV32_P15) : /* move ${const32},${Pd} */ 3949{ 3950 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3951 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3952#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 3953 int UNUSED written = 0; 3954 IADDR UNUSED pc = abuf->addr; 3955 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 3956 3957{ 3958 { 3959 SI opval = FLD (f_indir_pc__dword); 3960 SET_H_SR (FLD (f_operand2), opval); 3961 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 3962 } 3963{ 3964 { 3965 BI opval = 0; 3966 CPU (h_xbit) = opval; 3967 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 3968 } 3969 { 3970 BI opval = 0; 3971 SET_H_INSN_PREFIXED_P (opval); 3972 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 3973 } 3974} 3975} 3976 3977#undef FLD 3978} 3979 NEXT (vpc); 3980 3981 CASE (sem, INSN_MOVE_SPR_MV32) : /* move ${Ps},[${Rd-sfield}${inc}] */ 3982{ 3983 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 3984 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 3985#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f 3986 int UNUSED written = 0; 3987 IADDR UNUSED pc = abuf->addr; 3988 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 3989 3990{ 3991 SI tmp_rno; 3992 tmp_rno = FLD (f_operand2); 3993if (EQSI (tmp_rno, 2)) { 3994{ 3995 SI tmp_addr; 3996 BI tmp_postinc; 3997 tmp_postinc = FLD (f_memmode); 3998 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 3999if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4000if (EQBI (CPU (h_pbit), 0)) { 4001{ 4002 { 4003 QI opval = GET_H_SR (FLD (f_operand2)); 4004 SETMEMQI (current_cpu, pc, tmp_addr, opval); 4005 written |= (1 << 12); 4006 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4007 } 4008 { 4009 BI opval = CPU (h_pbit); 4010 CPU (h_cbit) = opval; 4011 written |= (1 << 10); 4012 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4013 } 4014} 4015} else { 4016 { 4017 BI opval = 1; 4018 CPU (h_cbit) = opval; 4019 written |= (1 << 10); 4020 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4021 } 4022} 4023} else { 4024 { 4025 QI opval = GET_H_SR (FLD (f_operand2)); 4026 SETMEMQI (current_cpu, pc, tmp_addr, opval); 4027 written |= (1 << 12); 4028 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4029 } 4030} 4031if (NEBI (tmp_postinc, 0)) { 4032{ 4033if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4034 tmp_addr = ADDSI (tmp_addr, 1); 4035} 4036 { 4037 SI opval = tmp_addr; 4038 SET_H_GR (FLD (f_operand1), opval); 4039 written |= (1 << 9); 4040 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4041 } 4042} 4043} 4044} 4045} 4046 else if (EQSI (tmp_rno, 3)) { 4047{ 4048 SI tmp_addr; 4049 BI tmp_postinc; 4050 tmp_postinc = FLD (f_memmode); 4051 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4052if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4053if (EQBI (CPU (h_pbit), 0)) { 4054{ 4055 { 4056 QI opval = GET_H_SR (FLD (f_operand2)); 4057 SETMEMQI (current_cpu, pc, tmp_addr, opval); 4058 written |= (1 << 12); 4059 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4060 } 4061 { 4062 BI opval = CPU (h_pbit); 4063 CPU (h_cbit) = opval; 4064 written |= (1 << 10); 4065 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4066 } 4067} 4068} else { 4069 { 4070 BI opval = 1; 4071 CPU (h_cbit) = opval; 4072 written |= (1 << 10); 4073 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4074 } 4075} 4076} else { 4077 { 4078 QI opval = GET_H_SR (FLD (f_operand2)); 4079 SETMEMQI (current_cpu, pc, tmp_addr, opval); 4080 written |= (1 << 12); 4081 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4082 } 4083} 4084if (NEBI (tmp_postinc, 0)) { 4085{ 4086if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4087 tmp_addr = ADDSI (tmp_addr, 1); 4088} 4089 { 4090 SI opval = tmp_addr; 4091 SET_H_GR (FLD (f_operand1), opval); 4092 written |= (1 << 9); 4093 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4094 } 4095} 4096} 4097} 4098} 4099 else if (EQSI (tmp_rno, 5)) { 4100{ 4101 SI tmp_addr; 4102 BI tmp_postinc; 4103 tmp_postinc = FLD (f_memmode); 4104 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4105if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4106if (EQBI (CPU (h_pbit), 0)) { 4107{ 4108 { 4109 SI opval = GET_H_SR (FLD (f_operand2)); 4110 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4111 written |= (1 << 13); 4112 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4113 } 4114 { 4115 BI opval = CPU (h_pbit); 4116 CPU (h_cbit) = opval; 4117 written |= (1 << 10); 4118 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4119 } 4120} 4121} else { 4122 { 4123 BI opval = 1; 4124 CPU (h_cbit) = opval; 4125 written |= (1 << 10); 4126 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4127 } 4128} 4129} else { 4130 { 4131 SI opval = GET_H_SR (FLD (f_operand2)); 4132 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4133 written |= (1 << 13); 4134 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4135 } 4136} 4137if (NEBI (tmp_postinc, 0)) { 4138{ 4139if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4140 tmp_addr = ADDSI (tmp_addr, 4); 4141} 4142 { 4143 SI opval = tmp_addr; 4144 SET_H_GR (FLD (f_operand1), opval); 4145 written |= (1 << 9); 4146 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4147 } 4148} 4149} 4150} 4151} 4152 else if (EQSI (tmp_rno, 6)) { 4153{ 4154 SI tmp_addr; 4155 BI tmp_postinc; 4156 tmp_postinc = FLD (f_memmode); 4157 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4158if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4159if (EQBI (CPU (h_pbit), 0)) { 4160{ 4161 { 4162 SI opval = GET_H_SR (FLD (f_operand2)); 4163 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4164 written |= (1 << 13); 4165 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4166 } 4167 { 4168 BI opval = CPU (h_pbit); 4169 CPU (h_cbit) = opval; 4170 written |= (1 << 10); 4171 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4172 } 4173} 4174} else { 4175 { 4176 BI opval = 1; 4177 CPU (h_cbit) = opval; 4178 written |= (1 << 10); 4179 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4180 } 4181} 4182} else { 4183 { 4184 SI opval = GET_H_SR (FLD (f_operand2)); 4185 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4186 written |= (1 << 13); 4187 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4188 } 4189} 4190if (NEBI (tmp_postinc, 0)) { 4191{ 4192if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4193 tmp_addr = ADDSI (tmp_addr, 4); 4194} 4195 { 4196 SI opval = tmp_addr; 4197 SET_H_GR (FLD (f_operand1), opval); 4198 written |= (1 << 9); 4199 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4200 } 4201} 4202} 4203} 4204} 4205 else if (EQSI (tmp_rno, 7)) { 4206{ 4207 SI tmp_addr; 4208 BI tmp_postinc; 4209 tmp_postinc = FLD (f_memmode); 4210 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4211if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4212if (EQBI (CPU (h_pbit), 0)) { 4213{ 4214 { 4215 SI opval = GET_H_SR (FLD (f_operand2)); 4216 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4217 written |= (1 << 13); 4218 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4219 } 4220 { 4221 BI opval = CPU (h_pbit); 4222 CPU (h_cbit) = opval; 4223 written |= (1 << 10); 4224 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4225 } 4226} 4227} else { 4228 { 4229 BI opval = 1; 4230 CPU (h_cbit) = opval; 4231 written |= (1 << 10); 4232 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4233 } 4234} 4235} else { 4236 { 4237 SI opval = GET_H_SR (FLD (f_operand2)); 4238 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4239 written |= (1 << 13); 4240 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4241 } 4242} 4243if (NEBI (tmp_postinc, 0)) { 4244{ 4245if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4246 tmp_addr = ADDSI (tmp_addr, 4); 4247} 4248 { 4249 SI opval = tmp_addr; 4250 SET_H_GR (FLD (f_operand1), opval); 4251 written |= (1 << 9); 4252 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4253 } 4254} 4255} 4256} 4257} 4258 else if (EQSI (tmp_rno, 9)) { 4259{ 4260 SI tmp_addr; 4261 BI tmp_postinc; 4262 tmp_postinc = FLD (f_memmode); 4263 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4264if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4265if (EQBI (CPU (h_pbit), 0)) { 4266{ 4267 { 4268 SI opval = GET_H_SR (FLD (f_operand2)); 4269 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4270 written |= (1 << 13); 4271 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4272 } 4273 { 4274 BI opval = CPU (h_pbit); 4275 CPU (h_cbit) = opval; 4276 written |= (1 << 10); 4277 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4278 } 4279} 4280} else { 4281 { 4282 BI opval = 1; 4283 CPU (h_cbit) = opval; 4284 written |= (1 << 10); 4285 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4286 } 4287} 4288} else { 4289 { 4290 SI opval = GET_H_SR (FLD (f_operand2)); 4291 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4292 written |= (1 << 13); 4293 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4294 } 4295} 4296if (NEBI (tmp_postinc, 0)) { 4297{ 4298if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4299 tmp_addr = ADDSI (tmp_addr, 4); 4300} 4301 { 4302 SI opval = tmp_addr; 4303 SET_H_GR (FLD (f_operand1), opval); 4304 written |= (1 << 9); 4305 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4306 } 4307} 4308} 4309} 4310} 4311 else if (EQSI (tmp_rno, 10)) { 4312{ 4313 SI tmp_addr; 4314 BI tmp_postinc; 4315 tmp_postinc = FLD (f_memmode); 4316 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4317if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4318if (EQBI (CPU (h_pbit), 0)) { 4319{ 4320 { 4321 SI opval = GET_H_SR (FLD (f_operand2)); 4322 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4323 written |= (1 << 13); 4324 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4325 } 4326 { 4327 BI opval = CPU (h_pbit); 4328 CPU (h_cbit) = opval; 4329 written |= (1 << 10); 4330 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4331 } 4332} 4333} else { 4334 { 4335 BI opval = 1; 4336 CPU (h_cbit) = opval; 4337 written |= (1 << 10); 4338 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4339 } 4340} 4341} else { 4342 { 4343 SI opval = GET_H_SR (FLD (f_operand2)); 4344 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4345 written |= (1 << 13); 4346 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4347 } 4348} 4349if (NEBI (tmp_postinc, 0)) { 4350{ 4351if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4352 tmp_addr = ADDSI (tmp_addr, 4); 4353} 4354 { 4355 SI opval = tmp_addr; 4356 SET_H_GR (FLD (f_operand1), opval); 4357 written |= (1 << 9); 4358 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4359 } 4360} 4361} 4362} 4363} 4364 else if (EQSI (tmp_rno, 11)) { 4365{ 4366 SI tmp_addr; 4367 BI tmp_postinc; 4368 tmp_postinc = FLD (f_memmode); 4369 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4370if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4371if (EQBI (CPU (h_pbit), 0)) { 4372{ 4373 { 4374 SI opval = GET_H_SR (FLD (f_operand2)); 4375 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4376 written |= (1 << 13); 4377 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4378 } 4379 { 4380 BI opval = CPU (h_pbit); 4381 CPU (h_cbit) = opval; 4382 written |= (1 << 10); 4383 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4384 } 4385} 4386} else { 4387 { 4388 BI opval = 1; 4389 CPU (h_cbit) = opval; 4390 written |= (1 << 10); 4391 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4392 } 4393} 4394} else { 4395 { 4396 SI opval = GET_H_SR (FLD (f_operand2)); 4397 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4398 written |= (1 << 13); 4399 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4400 } 4401} 4402if (NEBI (tmp_postinc, 0)) { 4403{ 4404if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4405 tmp_addr = ADDSI (tmp_addr, 4); 4406} 4407 { 4408 SI opval = tmp_addr; 4409 SET_H_GR (FLD (f_operand1), opval); 4410 written |= (1 << 9); 4411 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4412 } 4413} 4414} 4415} 4416} 4417 else if (EQSI (tmp_rno, 12)) { 4418{ 4419 SI tmp_addr; 4420 BI tmp_postinc; 4421 tmp_postinc = FLD (f_memmode); 4422 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4423if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4424if (EQBI (CPU (h_pbit), 0)) { 4425{ 4426 { 4427 SI opval = GET_H_SR (FLD (f_operand2)); 4428 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4429 written |= (1 << 13); 4430 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4431 } 4432 { 4433 BI opval = CPU (h_pbit); 4434 CPU (h_cbit) = opval; 4435 written |= (1 << 10); 4436 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4437 } 4438} 4439} else { 4440 { 4441 BI opval = 1; 4442 CPU (h_cbit) = opval; 4443 written |= (1 << 10); 4444 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4445 } 4446} 4447} else { 4448 { 4449 SI opval = GET_H_SR (FLD (f_operand2)); 4450 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4451 written |= (1 << 13); 4452 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4453 } 4454} 4455if (NEBI (tmp_postinc, 0)) { 4456{ 4457if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4458 tmp_addr = ADDSI (tmp_addr, 4); 4459} 4460 { 4461 SI opval = tmp_addr; 4462 SET_H_GR (FLD (f_operand1), opval); 4463 written |= (1 << 9); 4464 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4465 } 4466} 4467} 4468} 4469} 4470 else if (EQSI (tmp_rno, 13)) { 4471{ 4472 SI tmp_addr; 4473 BI tmp_postinc; 4474 tmp_postinc = FLD (f_memmode); 4475 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4476if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4477if (EQBI (CPU (h_pbit), 0)) { 4478{ 4479 { 4480 SI opval = GET_H_SR (FLD (f_operand2)); 4481 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4482 written |= (1 << 13); 4483 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4484 } 4485 { 4486 BI opval = CPU (h_pbit); 4487 CPU (h_cbit) = opval; 4488 written |= (1 << 10); 4489 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4490 } 4491} 4492} else { 4493 { 4494 BI opval = 1; 4495 CPU (h_cbit) = opval; 4496 written |= (1 << 10); 4497 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4498 } 4499} 4500} else { 4501 { 4502 SI opval = GET_H_SR (FLD (f_operand2)); 4503 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4504 written |= (1 << 13); 4505 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4506 } 4507} 4508if (NEBI (tmp_postinc, 0)) { 4509{ 4510if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4511 tmp_addr = ADDSI (tmp_addr, 4); 4512} 4513 { 4514 SI opval = tmp_addr; 4515 SET_H_GR (FLD (f_operand1), opval); 4516 written |= (1 << 9); 4517 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4518 } 4519} 4520} 4521} 4522} 4523 else if (EQSI (tmp_rno, 14)) { 4524{ 4525 SI tmp_addr; 4526 BI tmp_postinc; 4527 tmp_postinc = FLD (f_memmode); 4528 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4529if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4530if (EQBI (CPU (h_pbit), 0)) { 4531{ 4532 { 4533 SI opval = GET_H_SR (FLD (f_operand2)); 4534 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4535 written |= (1 << 13); 4536 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4537 } 4538 { 4539 BI opval = CPU (h_pbit); 4540 CPU (h_cbit) = opval; 4541 written |= (1 << 10); 4542 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4543 } 4544} 4545} else { 4546 { 4547 BI opval = 1; 4548 CPU (h_cbit) = opval; 4549 written |= (1 << 10); 4550 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4551 } 4552} 4553} else { 4554 { 4555 SI opval = GET_H_SR (FLD (f_operand2)); 4556 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4557 written |= (1 << 13); 4558 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4559 } 4560} 4561if (NEBI (tmp_postinc, 0)) { 4562{ 4563if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4564 tmp_addr = ADDSI (tmp_addr, 4); 4565} 4566 { 4567 SI opval = tmp_addr; 4568 SET_H_GR (FLD (f_operand1), opval); 4569 written |= (1 << 9); 4570 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4571 } 4572} 4573} 4574} 4575} 4576 else if (EQSI (tmp_rno, 15)) { 4577{ 4578 SI tmp_addr; 4579 BI tmp_postinc; 4580 tmp_postinc = FLD (f_memmode); 4581 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4582if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4583if (EQBI (CPU (h_pbit), 0)) { 4584{ 4585 { 4586 SI opval = GET_H_SR (FLD (f_operand2)); 4587 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4588 written |= (1 << 13); 4589 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4590 } 4591 { 4592 BI opval = CPU (h_pbit); 4593 CPU (h_cbit) = opval; 4594 written |= (1 << 10); 4595 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4596 } 4597} 4598} else { 4599 { 4600 BI opval = 1; 4601 CPU (h_cbit) = opval; 4602 written |= (1 << 10); 4603 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4604 } 4605} 4606} else { 4607 { 4608 SI opval = GET_H_SR (FLD (f_operand2)); 4609 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4610 written |= (1 << 13); 4611 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4612 } 4613} 4614if (NEBI (tmp_postinc, 0)) { 4615{ 4616if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4617 tmp_addr = ADDSI (tmp_addr, 4); 4618} 4619 { 4620 SI opval = tmp_addr; 4621 SET_H_GR (FLD (f_operand1), opval); 4622 written |= (1 << 9); 4623 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4624 } 4625} 4626} 4627} 4628} 4629 else if (EQSI (tmp_rno, 0)) { 4630{ 4631 SI tmp_addr; 4632 BI tmp_postinc; 4633 tmp_postinc = FLD (f_memmode); 4634 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4635if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4636if (EQBI (CPU (h_pbit), 0)) { 4637{ 4638 { 4639 QI opval = GET_H_SR (FLD (f_operand2)); 4640 SETMEMQI (current_cpu, pc, tmp_addr, opval); 4641 written |= (1 << 12); 4642 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4643 } 4644 { 4645 BI opval = CPU (h_pbit); 4646 CPU (h_cbit) = opval; 4647 written |= (1 << 10); 4648 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4649 } 4650} 4651} else { 4652 { 4653 BI opval = 1; 4654 CPU (h_cbit) = opval; 4655 written |= (1 << 10); 4656 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4657 } 4658} 4659} else { 4660 { 4661 QI opval = GET_H_SR (FLD (f_operand2)); 4662 SETMEMQI (current_cpu, pc, tmp_addr, opval); 4663 written |= (1 << 12); 4664 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4665 } 4666} 4667if (NEBI (tmp_postinc, 0)) { 4668{ 4669if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4670 tmp_addr = ADDSI (tmp_addr, 1); 4671} 4672 { 4673 SI opval = tmp_addr; 4674 SET_H_GR (FLD (f_operand1), opval); 4675 written |= (1 << 9); 4676 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4677 } 4678} 4679} 4680} 4681} 4682 else if (EQSI (tmp_rno, 1)) { 4683{ 4684 SI tmp_addr; 4685 BI tmp_postinc; 4686 tmp_postinc = FLD (f_memmode); 4687 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4688if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4689if (EQBI (CPU (h_pbit), 0)) { 4690{ 4691 { 4692 QI opval = GET_H_SR (FLD (f_operand2)); 4693 SETMEMQI (current_cpu, pc, tmp_addr, opval); 4694 written |= (1 << 12); 4695 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4696 } 4697 { 4698 BI opval = CPU (h_pbit); 4699 CPU (h_cbit) = opval; 4700 written |= (1 << 10); 4701 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4702 } 4703} 4704} else { 4705 { 4706 BI opval = 1; 4707 CPU (h_cbit) = opval; 4708 written |= (1 << 10); 4709 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4710 } 4711} 4712} else { 4713 { 4714 QI opval = GET_H_SR (FLD (f_operand2)); 4715 SETMEMQI (current_cpu, pc, tmp_addr, opval); 4716 written |= (1 << 12); 4717 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4718 } 4719} 4720if (NEBI (tmp_postinc, 0)) { 4721{ 4722if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4723 tmp_addr = ADDSI (tmp_addr, 1); 4724} 4725 { 4726 SI opval = tmp_addr; 4727 SET_H_GR (FLD (f_operand1), opval); 4728 written |= (1 << 9); 4729 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4730 } 4731} 4732} 4733} 4734} 4735 else if (EQSI (tmp_rno, 4)) { 4736{ 4737 SI tmp_addr; 4738 BI tmp_postinc; 4739 tmp_postinc = FLD (f_memmode); 4740 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4741if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4742if (EQBI (CPU (h_pbit), 0)) { 4743{ 4744 { 4745 HI opval = GET_H_SR (FLD (f_operand2)); 4746 SETMEMHI (current_cpu, pc, tmp_addr, opval); 4747 written |= (1 << 11); 4748 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4749 } 4750 { 4751 BI opval = CPU (h_pbit); 4752 CPU (h_cbit) = opval; 4753 written |= (1 << 10); 4754 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4755 } 4756} 4757} else { 4758 { 4759 BI opval = 1; 4760 CPU (h_cbit) = opval; 4761 written |= (1 << 10); 4762 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4763 } 4764} 4765} else { 4766 { 4767 HI opval = GET_H_SR (FLD (f_operand2)); 4768 SETMEMHI (current_cpu, pc, tmp_addr, opval); 4769 written |= (1 << 11); 4770 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4771 } 4772} 4773if (NEBI (tmp_postinc, 0)) { 4774{ 4775if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4776 tmp_addr = ADDSI (tmp_addr, 2); 4777} 4778 { 4779 SI opval = tmp_addr; 4780 SET_H_GR (FLD (f_operand1), opval); 4781 written |= (1 << 9); 4782 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4783 } 4784} 4785} 4786} 4787} 4788 else if (EQSI (tmp_rno, 8)) { 4789{ 4790 SI tmp_addr; 4791 BI tmp_postinc; 4792 tmp_postinc = FLD (f_memmode); 4793 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 4794if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 4795if (EQBI (CPU (h_pbit), 0)) { 4796{ 4797 { 4798 SI opval = GET_H_SR (FLD (f_operand2)); 4799 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4800 written |= (1 << 13); 4801 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4802 } 4803 { 4804 BI opval = CPU (h_pbit); 4805 CPU (h_cbit) = opval; 4806 written |= (1 << 10); 4807 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4808 } 4809} 4810} else { 4811 { 4812 BI opval = 1; 4813 CPU (h_cbit) = opval; 4814 written |= (1 << 10); 4815 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 4816 } 4817} 4818} else { 4819 { 4820 SI opval = GET_H_SR (FLD (f_operand2)); 4821 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4822 written |= (1 << 13); 4823 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4824 } 4825} 4826if (NEBI (tmp_postinc, 0)) { 4827{ 4828if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 4829 tmp_addr = ADDSI (tmp_addr, 4); 4830} 4831 { 4832 SI opval = tmp_addr; 4833 SET_H_GR (FLD (f_operand1), opval); 4834 written |= (1 << 9); 4835 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4836 } 4837} 4838} 4839} 4840} 4841 else { 4842cgen_rtx_error (current_cpu, "write from unimplemented special register"); 4843} 4844{ 4845 { 4846 BI opval = 0; 4847 CPU (h_xbit) = opval; 4848 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 4849 } 4850 { 4851 BI opval = 0; 4852 SET_H_INSN_PREFIXED_P (opval); 4853 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 4854 } 4855} 4856} 4857 4858 abuf->written = written; 4859#undef FLD 4860} 4861 NEXT (vpc); 4862 4863 CASE (sem, INSN_MOVE_SS_R) : /* move ${Ss},${Rd-sfield} */ 4864{ 4865 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 4866 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 4867#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f 4868 int UNUSED written = 0; 4869 IADDR UNUSED pc = abuf->addr; 4870 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 4871 4872{ 4873 { 4874 SI opval = GET_H_SUPR (FLD (f_operand2)); 4875 SET_H_GR (FLD (f_operand1), opval); 4876 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 4877 } 4878{ 4879 { 4880 BI opval = 0; 4881 CPU (h_xbit) = opval; 4882 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 4883 } 4884 { 4885 BI opval = 0; 4886 SET_H_INSN_PREFIXED_P (opval); 4887 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 4888 } 4889} 4890} 4891 4892#undef FLD 4893} 4894 NEXT (vpc); 4895 4896 CASE (sem, INSN_MOVE_R_SS) : /* move ${Rs},${Sd} */ 4897{ 4898 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 4899 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 4900#define FLD(f) abuf->fields.sfmt_mcp.f 4901 int UNUSED written = 0; 4902 IADDR UNUSED pc = abuf->addr; 4903 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 4904 4905{ 4906 { 4907 SI opval = GET_H_GR (FLD (f_operand1)); 4908 SET_H_SUPR (FLD (f_operand2), opval); 4909 TRACE_RESULT (current_cpu, abuf, "supr", 'x', opval); 4910 } 4911{ 4912 { 4913 BI opval = 0; 4914 CPU (h_xbit) = opval; 4915 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 4916 } 4917 { 4918 BI opval = 0; 4919 SET_H_INSN_PREFIXED_P (opval); 4920 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 4921 } 4922} 4923} 4924 4925#undef FLD 4926} 4927 NEXT (vpc); 4928 4929 CASE (sem, INSN_MOVEM_R_M_V32) : /* movem ${Rs-dfield},[${Rd-sfield}${inc}] */ 4930{ 4931 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 4932 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 4933#define FLD(f) abuf->fields.sfmt_movem_r_m_v32.f 4934 int UNUSED written = 0; 4935 IADDR UNUSED pc = abuf->addr; 4936 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 4937 4938{ 4939 SI tmp_addr; 4940 BI tmp_postinc; 4941 tmp_postinc = FLD (f_memmode); 4942{ 4943 SI tmp_dummy; 4944 tmp_dummy = GET_H_GR (FLD (f_operand2)); 4945} 4946 tmp_addr = GET_H_GR (FLD (f_operand1)); 4947{ 4948if (GESI (FLD (f_operand2), 0)) { 4949{ 4950 SI tmp_tmp; 4951 tmp_tmp = GET_H_GR (((UINT) 0)); 4952 { 4953 SI opval = tmp_tmp; 4954 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4955 written |= (1 << 21); 4956 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4957 } 4958 tmp_addr = ADDSI (tmp_addr, 4); 4959} 4960} 4961if (GESI (FLD (f_operand2), 1)) { 4962{ 4963 SI tmp_tmp; 4964 tmp_tmp = GET_H_GR (((UINT) 1)); 4965 { 4966 SI opval = tmp_tmp; 4967 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4968 written |= (1 << 21); 4969 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4970 } 4971 tmp_addr = ADDSI (tmp_addr, 4); 4972} 4973} 4974if (GESI (FLD (f_operand2), 2)) { 4975{ 4976 SI tmp_tmp; 4977 tmp_tmp = GET_H_GR (((UINT) 2)); 4978 { 4979 SI opval = tmp_tmp; 4980 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4981 written |= (1 << 21); 4982 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4983 } 4984 tmp_addr = ADDSI (tmp_addr, 4); 4985} 4986} 4987if (GESI (FLD (f_operand2), 3)) { 4988{ 4989 SI tmp_tmp; 4990 tmp_tmp = GET_H_GR (((UINT) 3)); 4991 { 4992 SI opval = tmp_tmp; 4993 SETMEMSI (current_cpu, pc, tmp_addr, opval); 4994 written |= (1 << 21); 4995 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 4996 } 4997 tmp_addr = ADDSI (tmp_addr, 4); 4998} 4999} 5000if (GESI (FLD (f_operand2), 4)) { 5001{ 5002 SI tmp_tmp; 5003 tmp_tmp = GET_H_GR (((UINT) 4)); 5004 { 5005 SI opval = tmp_tmp; 5006 SETMEMSI (current_cpu, pc, tmp_addr, opval); 5007 written |= (1 << 21); 5008 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 5009 } 5010 tmp_addr = ADDSI (tmp_addr, 4); 5011} 5012} 5013if (GESI (FLD (f_operand2), 5)) { 5014{ 5015 SI tmp_tmp; 5016 tmp_tmp = GET_H_GR (((UINT) 5)); 5017 { 5018 SI opval = tmp_tmp; 5019 SETMEMSI (current_cpu, pc, tmp_addr, opval); 5020 written |= (1 << 21); 5021 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 5022 } 5023 tmp_addr = ADDSI (tmp_addr, 4); 5024} 5025} 5026if (GESI (FLD (f_operand2), 6)) { 5027{ 5028 SI tmp_tmp; 5029 tmp_tmp = GET_H_GR (((UINT) 6)); 5030 { 5031 SI opval = tmp_tmp; 5032 SETMEMSI (current_cpu, pc, tmp_addr, opval); 5033 written |= (1 << 21); 5034 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 5035 } 5036 tmp_addr = ADDSI (tmp_addr, 4); 5037} 5038} 5039if (GESI (FLD (f_operand2), 7)) { 5040{ 5041 SI tmp_tmp; 5042 tmp_tmp = GET_H_GR (((UINT) 7)); 5043 { 5044 SI opval = tmp_tmp; 5045 SETMEMSI (current_cpu, pc, tmp_addr, opval); 5046 written |= (1 << 21); 5047 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 5048 } 5049 tmp_addr = ADDSI (tmp_addr, 4); 5050} 5051} 5052if (GESI (FLD (f_operand2), 8)) { 5053{ 5054 SI tmp_tmp; 5055 tmp_tmp = GET_H_GR (((UINT) 8)); 5056 { 5057 SI opval = tmp_tmp; 5058 SETMEMSI (current_cpu, pc, tmp_addr, opval); 5059 written |= (1 << 21); 5060 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 5061 } 5062 tmp_addr = ADDSI (tmp_addr, 4); 5063} 5064} 5065if (GESI (FLD (f_operand2), 9)) { 5066{ 5067 SI tmp_tmp; 5068 tmp_tmp = GET_H_GR (((UINT) 9)); 5069 { 5070 SI opval = tmp_tmp; 5071 SETMEMSI (current_cpu, pc, tmp_addr, opval); 5072 written |= (1 << 21); 5073 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 5074 } 5075 tmp_addr = ADDSI (tmp_addr, 4); 5076} 5077} 5078if (GESI (FLD (f_operand2), 10)) { 5079{ 5080 SI tmp_tmp; 5081 tmp_tmp = GET_H_GR (((UINT) 10)); 5082 { 5083 SI opval = tmp_tmp; 5084 SETMEMSI (current_cpu, pc, tmp_addr, opval); 5085 written |= (1 << 21); 5086 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 5087 } 5088 tmp_addr = ADDSI (tmp_addr, 4); 5089} 5090} 5091if (GESI (FLD (f_operand2), 11)) { 5092{ 5093 SI tmp_tmp; 5094 tmp_tmp = GET_H_GR (((UINT) 11)); 5095 { 5096 SI opval = tmp_tmp; 5097 SETMEMSI (current_cpu, pc, tmp_addr, opval); 5098 written |= (1 << 21); 5099 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 5100 } 5101 tmp_addr = ADDSI (tmp_addr, 4); 5102} 5103} 5104if (GESI (FLD (f_operand2), 12)) { 5105{ 5106 SI tmp_tmp; 5107 tmp_tmp = GET_H_GR (((UINT) 12)); 5108 { 5109 SI opval = tmp_tmp; 5110 SETMEMSI (current_cpu, pc, tmp_addr, opval); 5111 written |= (1 << 21); 5112 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 5113 } 5114 tmp_addr = ADDSI (tmp_addr, 4); 5115} 5116} 5117if (GESI (FLD (f_operand2), 13)) { 5118{ 5119 SI tmp_tmp; 5120 tmp_tmp = GET_H_GR (((UINT) 13)); 5121 { 5122 SI opval = tmp_tmp; 5123 SETMEMSI (current_cpu, pc, tmp_addr, opval); 5124 written |= (1 << 21); 5125 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 5126 } 5127 tmp_addr = ADDSI (tmp_addr, 4); 5128} 5129} 5130if (GESI (FLD (f_operand2), 14)) { 5131{ 5132 SI tmp_tmp; 5133 tmp_tmp = GET_H_GR (((UINT) 14)); 5134 { 5135 SI opval = tmp_tmp; 5136 SETMEMSI (current_cpu, pc, tmp_addr, opval); 5137 written |= (1 << 21); 5138 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 5139 } 5140 tmp_addr = ADDSI (tmp_addr, 4); 5141} 5142} 5143if (GESI (FLD (f_operand2), 15)) { 5144{ 5145 SI tmp_tmp; 5146 tmp_tmp = GET_H_GR (((UINT) 15)); 5147 { 5148 SI opval = tmp_tmp; 5149 SETMEMSI (current_cpu, pc, tmp_addr, opval); 5150 written |= (1 << 21); 5151 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 5152 } 5153 tmp_addr = ADDSI (tmp_addr, 4); 5154} 5155} 5156} 5157if (NEBI (tmp_postinc, 0)) { 5158 { 5159 SI opval = tmp_addr; 5160 SET_H_GR (FLD (f_operand1), opval); 5161 written |= (1 << 20); 5162 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5163 } 5164} 5165{ 5166 { 5167 BI opval = 0; 5168 CPU (h_xbit) = opval; 5169 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 5170 } 5171 { 5172 BI opval = 0; 5173 SET_H_INSN_PREFIXED_P (opval); 5174 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 5175 } 5176} 5177} 5178 5179 abuf->written = written; 5180#undef FLD 5181} 5182 NEXT (vpc); 5183 5184 CASE (sem, INSN_MOVEM_M_R_V32) : /* movem [${Rs}${inc}],${Rd} */ 5185{ 5186 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 5187 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 5188#define FLD(f) abuf->fields.sfmt_movem_m_r_v32.f 5189 int UNUSED written = 0; 5190 IADDR UNUSED pc = abuf->addr; 5191 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 5192 5193{ 5194 SI tmp_addr; 5195 BI tmp_postinc; 5196 tmp_postinc = FLD (f_memmode); 5197 tmp_addr = GET_H_GR (FLD (f_operand1)); 5198{ 5199 SI tmp_dummy; 5200 tmp_dummy = GET_H_GR (FLD (f_operand2)); 5201} 5202{ 5203if (GESI (FLD (f_operand2), 0)) { 5204{ 5205 SI tmp_tmp; 5206 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5207 { 5208 SI opval = tmp_tmp; 5209 SET_H_GR (((UINT) 0), opval); 5210 written |= (1 << 6); 5211 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5212 } 5213 tmp_addr = ADDSI (tmp_addr, 4); 5214} 5215} 5216if (GESI (FLD (f_operand2), 1)) { 5217{ 5218 SI tmp_tmp; 5219 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5220 { 5221 SI opval = tmp_tmp; 5222 SET_H_GR (((UINT) 1), opval); 5223 written |= (1 << 7); 5224 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5225 } 5226 tmp_addr = ADDSI (tmp_addr, 4); 5227} 5228} 5229if (GESI (FLD (f_operand2), 2)) { 5230{ 5231 SI tmp_tmp; 5232 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5233 { 5234 SI opval = tmp_tmp; 5235 SET_H_GR (((UINT) 2), opval); 5236 written |= (1 << 14); 5237 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5238 } 5239 tmp_addr = ADDSI (tmp_addr, 4); 5240} 5241} 5242if (GESI (FLD (f_operand2), 3)) { 5243{ 5244 SI tmp_tmp; 5245 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5246 { 5247 SI opval = tmp_tmp; 5248 SET_H_GR (((UINT) 3), opval); 5249 written |= (1 << 15); 5250 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5251 } 5252 tmp_addr = ADDSI (tmp_addr, 4); 5253} 5254} 5255if (GESI (FLD (f_operand2), 4)) { 5256{ 5257 SI tmp_tmp; 5258 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5259 { 5260 SI opval = tmp_tmp; 5261 SET_H_GR (((UINT) 4), opval); 5262 written |= (1 << 16); 5263 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5264 } 5265 tmp_addr = ADDSI (tmp_addr, 4); 5266} 5267} 5268if (GESI (FLD (f_operand2), 5)) { 5269{ 5270 SI tmp_tmp; 5271 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5272 { 5273 SI opval = tmp_tmp; 5274 SET_H_GR (((UINT) 5), opval); 5275 written |= (1 << 17); 5276 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5277 } 5278 tmp_addr = ADDSI (tmp_addr, 4); 5279} 5280} 5281if (GESI (FLD (f_operand2), 6)) { 5282{ 5283 SI tmp_tmp; 5284 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5285 { 5286 SI opval = tmp_tmp; 5287 SET_H_GR (((UINT) 6), opval); 5288 written |= (1 << 18); 5289 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5290 } 5291 tmp_addr = ADDSI (tmp_addr, 4); 5292} 5293} 5294if (GESI (FLD (f_operand2), 7)) { 5295{ 5296 SI tmp_tmp; 5297 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5298 { 5299 SI opval = tmp_tmp; 5300 SET_H_GR (((UINT) 7), opval); 5301 written |= (1 << 19); 5302 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5303 } 5304 tmp_addr = ADDSI (tmp_addr, 4); 5305} 5306} 5307if (GESI (FLD (f_operand2), 8)) { 5308{ 5309 SI tmp_tmp; 5310 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5311 { 5312 SI opval = tmp_tmp; 5313 SET_H_GR (((UINT) 8), opval); 5314 written |= (1 << 20); 5315 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5316 } 5317 tmp_addr = ADDSI (tmp_addr, 4); 5318} 5319} 5320if (GESI (FLD (f_operand2), 9)) { 5321{ 5322 SI tmp_tmp; 5323 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5324 { 5325 SI opval = tmp_tmp; 5326 SET_H_GR (((UINT) 9), opval); 5327 written |= (1 << 21); 5328 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5329 } 5330 tmp_addr = ADDSI (tmp_addr, 4); 5331} 5332} 5333if (GESI (FLD (f_operand2), 10)) { 5334{ 5335 SI tmp_tmp; 5336 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5337 { 5338 SI opval = tmp_tmp; 5339 SET_H_GR (((UINT) 10), opval); 5340 written |= (1 << 8); 5341 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5342 } 5343 tmp_addr = ADDSI (tmp_addr, 4); 5344} 5345} 5346if (GESI (FLD (f_operand2), 11)) { 5347{ 5348 SI tmp_tmp; 5349 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5350 { 5351 SI opval = tmp_tmp; 5352 SET_H_GR (((UINT) 11), opval); 5353 written |= (1 << 9); 5354 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5355 } 5356 tmp_addr = ADDSI (tmp_addr, 4); 5357} 5358} 5359if (GESI (FLD (f_operand2), 12)) { 5360{ 5361 SI tmp_tmp; 5362 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5363 { 5364 SI opval = tmp_tmp; 5365 SET_H_GR (((UINT) 12), opval); 5366 written |= (1 << 10); 5367 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5368 } 5369 tmp_addr = ADDSI (tmp_addr, 4); 5370} 5371} 5372if (GESI (FLD (f_operand2), 13)) { 5373{ 5374 SI tmp_tmp; 5375 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5376 { 5377 SI opval = tmp_tmp; 5378 SET_H_GR (((UINT) 13), opval); 5379 written |= (1 << 11); 5380 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5381 } 5382 tmp_addr = ADDSI (tmp_addr, 4); 5383} 5384} 5385if (GESI (FLD (f_operand2), 14)) { 5386{ 5387 SI tmp_tmp; 5388 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5389 { 5390 SI opval = tmp_tmp; 5391 SET_H_GR (((UINT) 14), opval); 5392 written |= (1 << 12); 5393 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5394 } 5395 tmp_addr = ADDSI (tmp_addr, 4); 5396} 5397} 5398if (GESI (FLD (f_operand2), 15)) { 5399{ 5400 SI tmp_tmp; 5401 tmp_tmp = GETMEMSI (current_cpu, pc, tmp_addr); 5402 { 5403 SI opval = tmp_tmp; 5404 SET_H_GR (((UINT) 15), opval); 5405 written |= (1 << 13); 5406 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5407 } 5408 tmp_addr = ADDSI (tmp_addr, 4); 5409} 5410} 5411} 5412if (NEBI (tmp_postinc, 0)) { 5413 { 5414 SI opval = tmp_addr; 5415 SET_H_GR (FLD (f_operand1), opval); 5416 written |= (1 << 5); 5417 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5418 } 5419} 5420{ 5421 { 5422 BI opval = 0; 5423 CPU (h_xbit) = opval; 5424 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 5425 } 5426 { 5427 BI opval = 0; 5428 SET_H_INSN_PREFIXED_P (opval); 5429 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 5430 } 5431} 5432} 5433 5434 abuf->written = written; 5435#undef FLD 5436} 5437 NEXT (vpc); 5438 5439 CASE (sem, INSN_ADD_B_R) : /* add.b $Rs,$Rd */ 5440{ 5441 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 5442 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 5443#define FLD(f) abuf->fields.sfmt_addc_m.f 5444 int UNUSED written = 0; 5445 IADDR UNUSED pc = abuf->addr; 5446 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 5447 5448{ 5449 QI tmp_tmpopd; 5450 QI tmp_tmpops; 5451 BI tmp_carry; 5452 QI tmp_newval; 5453 tmp_tmpops = GET_H_GR (FLD (f_operand1)); 5454 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 5455 tmp_carry = CPU (h_cbit); 5456 tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 5457{ 5458 SI tmp_oldregval; 5459 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 5460 { 5461 SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); 5462 SET_H_GR (FLD (f_operand2), opval); 5463 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5464 } 5465} 5466{ 5467 { 5468 BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0)))); 5469 CPU (h_cbit) = opval; 5470 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 5471 } 5472 { 5473 BI opval = LTQI (tmp_newval, 0); 5474 CPU (h_nbit) = opval; 5475 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 5476 } 5477 { 5478 BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 5479 CPU (h_zbit) = opval; 5480 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 5481 } 5482 { 5483 BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0))); 5484 CPU (h_vbit) = opval; 5485 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 5486 } 5487{ 5488 { 5489 BI opval = 0; 5490 CPU (h_xbit) = opval; 5491 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 5492 } 5493 { 5494 BI opval = 0; 5495 SET_H_INSN_PREFIXED_P (opval); 5496 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 5497 } 5498} 5499} 5500} 5501 5502#undef FLD 5503} 5504 NEXT (vpc); 5505 5506 CASE (sem, INSN_ADD_W_R) : /* add.w $Rs,$Rd */ 5507{ 5508 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 5509 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 5510#define FLD(f) abuf->fields.sfmt_addc_m.f 5511 int UNUSED written = 0; 5512 IADDR UNUSED pc = abuf->addr; 5513 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 5514 5515{ 5516 HI tmp_tmpopd; 5517 HI tmp_tmpops; 5518 BI tmp_carry; 5519 HI tmp_newval; 5520 tmp_tmpops = GET_H_GR (FLD (f_operand1)); 5521 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 5522 tmp_carry = CPU (h_cbit); 5523 tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 5524{ 5525 SI tmp_oldregval; 5526 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 5527 { 5528 SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 5529 SET_H_GR (FLD (f_operand2), opval); 5530 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5531 } 5532} 5533{ 5534 { 5535 BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0)))); 5536 CPU (h_cbit) = opval; 5537 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 5538 } 5539 { 5540 BI opval = LTHI (tmp_newval, 0); 5541 CPU (h_nbit) = opval; 5542 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 5543 } 5544 { 5545 BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 5546 CPU (h_zbit) = opval; 5547 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 5548 } 5549 { 5550 BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0))); 5551 CPU (h_vbit) = opval; 5552 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 5553 } 5554{ 5555 { 5556 BI opval = 0; 5557 CPU (h_xbit) = opval; 5558 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 5559 } 5560 { 5561 BI opval = 0; 5562 SET_H_INSN_PREFIXED_P (opval); 5563 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 5564 } 5565} 5566} 5567} 5568 5569#undef FLD 5570} 5571 NEXT (vpc); 5572 5573 CASE (sem, INSN_ADD_D_R) : /* add.d $Rs,$Rd */ 5574{ 5575 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 5576 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 5577#define FLD(f) abuf->fields.sfmt_addc_m.f 5578 int UNUSED written = 0; 5579 IADDR UNUSED pc = abuf->addr; 5580 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 5581 5582{ 5583 SI tmp_tmpopd; 5584 SI tmp_tmpops; 5585 BI tmp_carry; 5586 SI tmp_newval; 5587 tmp_tmpops = GET_H_GR (FLD (f_operand1)); 5588 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 5589 tmp_carry = CPU (h_cbit); 5590 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 5591 { 5592 SI opval = tmp_newval; 5593 SET_H_GR (FLD (f_operand2), opval); 5594 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5595 } 5596{ 5597 { 5598 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 5599 CPU (h_cbit) = opval; 5600 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 5601 } 5602 { 5603 BI opval = LTSI (tmp_newval, 0); 5604 CPU (h_nbit) = opval; 5605 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 5606 } 5607 { 5608 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 5609 CPU (h_zbit) = opval; 5610 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 5611 } 5612 { 5613 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 5614 CPU (h_vbit) = opval; 5615 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 5616 } 5617{ 5618 { 5619 BI opval = 0; 5620 CPU (h_xbit) = opval; 5621 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 5622 } 5623 { 5624 BI opval = 0; 5625 SET_H_INSN_PREFIXED_P (opval); 5626 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 5627 } 5628} 5629} 5630} 5631 5632#undef FLD 5633} 5634 NEXT (vpc); 5635 5636 CASE (sem, INSN_ADD_M_B_M) : /* add-m.b [${Rs}${inc}],${Rd} */ 5637{ 5638 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 5639 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 5640#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 5641 int UNUSED written = 0; 5642 IADDR UNUSED pc = abuf->addr; 5643 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 5644 5645{ 5646 QI tmp_tmpopd; 5647 QI tmp_tmpops; 5648 BI tmp_carry; 5649 QI tmp_newval; 5650 tmp_tmpops = ({ SI tmp_addr; 5651 QI tmp_tmp_mem; 5652 BI tmp_postinc; 5653 tmp_postinc = FLD (f_memmode); 5654; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 5655; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 5656; if (NEBI (tmp_postinc, 0)) { 5657{ 5658if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 5659 tmp_addr = ADDSI (tmp_addr, 1); 5660} 5661 { 5662 SI opval = tmp_addr; 5663 SET_H_GR (FLD (f_operand1), opval); 5664 written |= (1 << 12); 5665 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5666 } 5667} 5668} 5669; tmp_tmp_mem; }); 5670 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 5671 tmp_carry = CPU (h_cbit); 5672 tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 5673{ 5674 SI tmp_oldregval; 5675 tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2)))); 5676 { 5677 SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); 5678 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 5679 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5680 } 5681} 5682{ 5683 { 5684 BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0)))); 5685 CPU (h_cbit) = opval; 5686 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 5687 } 5688 { 5689 BI opval = LTQI (tmp_newval, 0); 5690 CPU (h_nbit) = opval; 5691 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 5692 } 5693 { 5694 BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 5695 CPU (h_zbit) = opval; 5696 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 5697 } 5698 { 5699 BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0))); 5700 CPU (h_vbit) = opval; 5701 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 5702 } 5703{ 5704 { 5705 BI opval = 0; 5706 CPU (h_xbit) = opval; 5707 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 5708 } 5709 { 5710 BI opval = 0; 5711 SET_H_INSN_PREFIXED_P (opval); 5712 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 5713 } 5714} 5715} 5716} 5717 5718 abuf->written = written; 5719#undef FLD 5720} 5721 NEXT (vpc); 5722 5723 CASE (sem, INSN_ADD_M_W_M) : /* add-m.w [${Rs}${inc}],${Rd} */ 5724{ 5725 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 5726 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 5727#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 5728 int UNUSED written = 0; 5729 IADDR UNUSED pc = abuf->addr; 5730 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 5731 5732{ 5733 HI tmp_tmpopd; 5734 HI tmp_tmpops; 5735 BI tmp_carry; 5736 HI tmp_newval; 5737 tmp_tmpops = ({ SI tmp_addr; 5738 HI tmp_tmp_mem; 5739 BI tmp_postinc; 5740 tmp_postinc = FLD (f_memmode); 5741; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 5742; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 5743; if (NEBI (tmp_postinc, 0)) { 5744{ 5745if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 5746 tmp_addr = ADDSI (tmp_addr, 2); 5747} 5748 { 5749 SI opval = tmp_addr; 5750 SET_H_GR (FLD (f_operand1), opval); 5751 written |= (1 << 12); 5752 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5753 } 5754} 5755} 5756; tmp_tmp_mem; }); 5757 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 5758 tmp_carry = CPU (h_cbit); 5759 tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 5760{ 5761 SI tmp_oldregval; 5762 tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2)))); 5763 { 5764 SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 5765 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 5766 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5767 } 5768} 5769{ 5770 { 5771 BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0)))); 5772 CPU (h_cbit) = opval; 5773 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 5774 } 5775 { 5776 BI opval = LTHI (tmp_newval, 0); 5777 CPU (h_nbit) = opval; 5778 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 5779 } 5780 { 5781 BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 5782 CPU (h_zbit) = opval; 5783 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 5784 } 5785 { 5786 BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0))); 5787 CPU (h_vbit) = opval; 5788 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 5789 } 5790{ 5791 { 5792 BI opval = 0; 5793 CPU (h_xbit) = opval; 5794 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 5795 } 5796 { 5797 BI opval = 0; 5798 SET_H_INSN_PREFIXED_P (opval); 5799 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 5800 } 5801} 5802} 5803} 5804 5805 abuf->written = written; 5806#undef FLD 5807} 5808 NEXT (vpc); 5809 5810 CASE (sem, INSN_ADD_M_D_M) : /* add-m.d [${Rs}${inc}],${Rd} */ 5811{ 5812 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 5813 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 5814#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 5815 int UNUSED written = 0; 5816 IADDR UNUSED pc = abuf->addr; 5817 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 5818 5819{ 5820 SI tmp_tmpopd; 5821 SI tmp_tmpops; 5822 BI tmp_carry; 5823 SI tmp_newval; 5824 tmp_tmpops = ({ SI tmp_addr; 5825 SI tmp_tmp_mem; 5826 BI tmp_postinc; 5827 tmp_postinc = FLD (f_memmode); 5828; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 5829; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 5830; if (NEBI (tmp_postinc, 0)) { 5831{ 5832if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 5833 tmp_addr = ADDSI (tmp_addr, 4); 5834} 5835 { 5836 SI opval = tmp_addr; 5837 SET_H_GR (FLD (f_operand1), opval); 5838 written |= (1 << 11); 5839 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5840 } 5841} 5842} 5843; tmp_tmp_mem; }); 5844 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 5845 tmp_carry = CPU (h_cbit); 5846 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 5847 { 5848 SI opval = tmp_newval; 5849 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 5850 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5851 } 5852{ 5853 { 5854 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 5855 CPU (h_cbit) = opval; 5856 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 5857 } 5858 { 5859 BI opval = LTSI (tmp_newval, 0); 5860 CPU (h_nbit) = opval; 5861 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 5862 } 5863 { 5864 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 5865 CPU (h_zbit) = opval; 5866 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 5867 } 5868 { 5869 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 5870 CPU (h_vbit) = opval; 5871 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 5872 } 5873{ 5874 { 5875 BI opval = 0; 5876 CPU (h_xbit) = opval; 5877 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 5878 } 5879 { 5880 BI opval = 0; 5881 SET_H_INSN_PREFIXED_P (opval); 5882 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 5883 } 5884} 5885} 5886} 5887 5888 abuf->written = written; 5889#undef FLD 5890} 5891 NEXT (vpc); 5892 5893 CASE (sem, INSN_ADDCBR) : /* add.b ${sconst8}],${Rd} */ 5894{ 5895 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 5896 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 5897#define FLD(f) abuf->fields.sfmt_addcbr.f 5898 int UNUSED written = 0; 5899 IADDR UNUSED pc = abuf->addr; 5900 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 5901 5902{ 5903 QI tmp_tmpopd; 5904 QI tmp_tmpops; 5905 BI tmp_carry; 5906 QI tmp_newval; 5907 tmp_tmpops = FLD (f_indir_pc__byte); 5908 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 5909 tmp_carry = CPU (h_cbit); 5910 tmp_newval = ADDCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 5911{ 5912 SI tmp_oldregval; 5913 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 5914 { 5915 SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); 5916 SET_H_GR (FLD (f_operand2), opval); 5917 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5918 } 5919} 5920{ 5921 { 5922 BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), ORIF (ANDIF (LTQI (tmp_tmpopd, 0), GEQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_newval, 0)))); 5923 CPU (h_cbit) = opval; 5924 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 5925 } 5926 { 5927 BI opval = LTQI (tmp_newval, 0); 5928 CPU (h_nbit) = opval; 5929 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 5930 } 5931 { 5932 BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 5933 CPU (h_zbit) = opval; 5934 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 5935 } 5936 { 5937 BI opval = ORIF (ANDIF (ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (GEQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0))); 5938 CPU (h_vbit) = opval; 5939 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 5940 } 5941{ 5942 { 5943 BI opval = 0; 5944 CPU (h_xbit) = opval; 5945 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 5946 } 5947 { 5948 BI opval = 0; 5949 SET_H_INSN_PREFIXED_P (opval); 5950 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 5951 } 5952} 5953} 5954} 5955 5956#undef FLD 5957} 5958 NEXT (vpc); 5959 5960 CASE (sem, INSN_ADDCWR) : /* add.w ${sconst16}],${Rd} */ 5961{ 5962 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 5963 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 5964#define FLD(f) abuf->fields.sfmt_addcwr.f 5965 int UNUSED written = 0; 5966 IADDR UNUSED pc = abuf->addr; 5967 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 5968 5969{ 5970 HI tmp_tmpopd; 5971 HI tmp_tmpops; 5972 BI tmp_carry; 5973 HI tmp_newval; 5974 tmp_tmpops = FLD (f_indir_pc__word); 5975 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 5976 tmp_carry = CPU (h_cbit); 5977 tmp_newval = ADDCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 5978{ 5979 SI tmp_oldregval; 5980 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 5981 { 5982 SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 5983 SET_H_GR (FLD (f_operand2), opval); 5984 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 5985 } 5986} 5987{ 5988 { 5989 BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), ORIF (ANDIF (LTHI (tmp_tmpopd, 0), GEHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_newval, 0)))); 5990 CPU (h_cbit) = opval; 5991 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 5992 } 5993 { 5994 BI opval = LTHI (tmp_newval, 0); 5995 CPU (h_nbit) = opval; 5996 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 5997 } 5998 { 5999 BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6000 CPU (h_zbit) = opval; 6001 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6002 } 6003 { 6004 BI opval = ORIF (ANDIF (ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (GEHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0))); 6005 CPU (h_vbit) = opval; 6006 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6007 } 6008{ 6009 { 6010 BI opval = 0; 6011 CPU (h_xbit) = opval; 6012 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6013 } 6014 { 6015 BI opval = 0; 6016 SET_H_INSN_PREFIXED_P (opval); 6017 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6018 } 6019} 6020} 6021} 6022 6023#undef FLD 6024} 6025 NEXT (vpc); 6026 6027 CASE (sem, INSN_ADDCDR) : /* add.d ${const32}],${Rd} */ 6028{ 6029 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6030 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6031#define FLD(f) abuf->fields.sfmt_addcdr.f 6032 int UNUSED written = 0; 6033 IADDR UNUSED pc = abuf->addr; 6034 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 6035 6036{ 6037 SI tmp_tmpopd; 6038 SI tmp_tmpops; 6039 BI tmp_carry; 6040 SI tmp_newval; 6041 tmp_tmpops = FLD (f_indir_pc__dword); 6042 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6043 tmp_carry = CPU (h_cbit); 6044 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6045 { 6046 SI opval = tmp_newval; 6047 SET_H_GR (FLD (f_operand2), opval); 6048 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6049 } 6050{ 6051 { 6052 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 6053 CPU (h_cbit) = opval; 6054 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6055 } 6056 { 6057 BI opval = LTSI (tmp_newval, 0); 6058 CPU (h_nbit) = opval; 6059 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6060 } 6061 { 6062 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6063 CPU (h_zbit) = opval; 6064 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6065 } 6066 { 6067 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 6068 CPU (h_vbit) = opval; 6069 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6070 } 6071{ 6072 { 6073 BI opval = 0; 6074 CPU (h_xbit) = opval; 6075 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6076 } 6077 { 6078 BI opval = 0; 6079 SET_H_INSN_PREFIXED_P (opval); 6080 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6081 } 6082} 6083} 6084} 6085 6086#undef FLD 6087} 6088 NEXT (vpc); 6089 6090 CASE (sem, INSN_ADDS_B_R) : /* adds.b $Rs,$Rd */ 6091{ 6092 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6093 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6094#define FLD(f) abuf->fields.sfmt_addc_m.f 6095 int UNUSED written = 0; 6096 IADDR UNUSED pc = abuf->addr; 6097 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 6098 6099{ 6100 SI tmp_tmpopd; 6101 SI tmp_tmpops; 6102 BI tmp_carry; 6103 SI tmp_newval; 6104 tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1)))); 6105 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6106 tmp_carry = CPU (h_cbit); 6107 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6108 { 6109 SI opval = tmp_newval; 6110 SET_H_GR (FLD (f_operand2), opval); 6111 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6112 } 6113{ 6114 { 6115 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 6116 CPU (h_cbit) = opval; 6117 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6118 } 6119 { 6120 BI opval = LTSI (tmp_newval, 0); 6121 CPU (h_nbit) = opval; 6122 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6123 } 6124 { 6125 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6126 CPU (h_zbit) = opval; 6127 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6128 } 6129 { 6130 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 6131 CPU (h_vbit) = opval; 6132 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6133 } 6134{ 6135 { 6136 BI opval = 0; 6137 CPU (h_xbit) = opval; 6138 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6139 } 6140 { 6141 BI opval = 0; 6142 SET_H_INSN_PREFIXED_P (opval); 6143 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6144 } 6145} 6146} 6147} 6148 6149#undef FLD 6150} 6151 NEXT (vpc); 6152 6153 CASE (sem, INSN_ADDS_W_R) : /* adds.w $Rs,$Rd */ 6154{ 6155 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6156 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6157#define FLD(f) abuf->fields.sfmt_addc_m.f 6158 int UNUSED written = 0; 6159 IADDR UNUSED pc = abuf->addr; 6160 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 6161 6162{ 6163 SI tmp_tmpopd; 6164 SI tmp_tmpops; 6165 BI tmp_carry; 6166 SI tmp_newval; 6167 tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1)))); 6168 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6169 tmp_carry = CPU (h_cbit); 6170 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6171 { 6172 SI opval = tmp_newval; 6173 SET_H_GR (FLD (f_operand2), opval); 6174 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6175 } 6176{ 6177 { 6178 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 6179 CPU (h_cbit) = opval; 6180 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6181 } 6182 { 6183 BI opval = LTSI (tmp_newval, 0); 6184 CPU (h_nbit) = opval; 6185 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6186 } 6187 { 6188 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6189 CPU (h_zbit) = opval; 6190 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6191 } 6192 { 6193 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 6194 CPU (h_vbit) = opval; 6195 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6196 } 6197{ 6198 { 6199 BI opval = 0; 6200 CPU (h_xbit) = opval; 6201 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6202 } 6203 { 6204 BI opval = 0; 6205 SET_H_INSN_PREFIXED_P (opval); 6206 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6207 } 6208} 6209} 6210} 6211 6212#undef FLD 6213} 6214 NEXT (vpc); 6215 6216 CASE (sem, INSN_ADDS_M_B_M) : /* adds-m.b [${Rs}${inc}],$Rd */ 6217{ 6218 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6219 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6220#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 6221 int UNUSED written = 0; 6222 IADDR UNUSED pc = abuf->addr; 6223 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 6224 6225{ 6226 SI tmp_tmpopd; 6227 SI tmp_tmpops; 6228 BI tmp_carry; 6229 SI tmp_newval; 6230 tmp_tmpops = EXTQISI (({ SI tmp_addr; 6231 QI tmp_tmp_mem; 6232 BI tmp_postinc; 6233 tmp_postinc = FLD (f_memmode); 6234; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 6235; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 6236; if (NEBI (tmp_postinc, 0)) { 6237{ 6238if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 6239 tmp_addr = ADDSI (tmp_addr, 1); 6240} 6241 { 6242 SI opval = tmp_addr; 6243 SET_H_GR (FLD (f_operand1), opval); 6244 written |= (1 << 11); 6245 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6246 } 6247} 6248} 6249; tmp_tmp_mem; })); 6250 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6251 tmp_carry = CPU (h_cbit); 6252 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6253 { 6254 SI opval = tmp_newval; 6255 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 6256 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6257 } 6258{ 6259 { 6260 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 6261 CPU (h_cbit) = opval; 6262 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6263 } 6264 { 6265 BI opval = LTSI (tmp_newval, 0); 6266 CPU (h_nbit) = opval; 6267 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6268 } 6269 { 6270 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6271 CPU (h_zbit) = opval; 6272 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6273 } 6274 { 6275 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 6276 CPU (h_vbit) = opval; 6277 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6278 } 6279{ 6280 { 6281 BI opval = 0; 6282 CPU (h_xbit) = opval; 6283 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6284 } 6285 { 6286 BI opval = 0; 6287 SET_H_INSN_PREFIXED_P (opval); 6288 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6289 } 6290} 6291} 6292} 6293 6294 abuf->written = written; 6295#undef FLD 6296} 6297 NEXT (vpc); 6298 6299 CASE (sem, INSN_ADDS_M_W_M) : /* adds-m.w [${Rs}${inc}],$Rd */ 6300{ 6301 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6302 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6303#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 6304 int UNUSED written = 0; 6305 IADDR UNUSED pc = abuf->addr; 6306 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 6307 6308{ 6309 SI tmp_tmpopd; 6310 SI tmp_tmpops; 6311 BI tmp_carry; 6312 SI tmp_newval; 6313 tmp_tmpops = EXTHISI (({ SI tmp_addr; 6314 HI tmp_tmp_mem; 6315 BI tmp_postinc; 6316 tmp_postinc = FLD (f_memmode); 6317; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 6318; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 6319; if (NEBI (tmp_postinc, 0)) { 6320{ 6321if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 6322 tmp_addr = ADDSI (tmp_addr, 2); 6323} 6324 { 6325 SI opval = tmp_addr; 6326 SET_H_GR (FLD (f_operand1), opval); 6327 written |= (1 << 11); 6328 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6329 } 6330} 6331} 6332; tmp_tmp_mem; })); 6333 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6334 tmp_carry = CPU (h_cbit); 6335 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6336 { 6337 SI opval = tmp_newval; 6338 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 6339 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6340 } 6341{ 6342 { 6343 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 6344 CPU (h_cbit) = opval; 6345 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6346 } 6347 { 6348 BI opval = LTSI (tmp_newval, 0); 6349 CPU (h_nbit) = opval; 6350 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6351 } 6352 { 6353 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6354 CPU (h_zbit) = opval; 6355 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6356 } 6357 { 6358 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 6359 CPU (h_vbit) = opval; 6360 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6361 } 6362{ 6363 { 6364 BI opval = 0; 6365 CPU (h_xbit) = opval; 6366 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6367 } 6368 { 6369 BI opval = 0; 6370 SET_H_INSN_PREFIXED_P (opval); 6371 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6372 } 6373} 6374} 6375} 6376 6377 abuf->written = written; 6378#undef FLD 6379} 6380 NEXT (vpc); 6381 6382 CASE (sem, INSN_ADDSCBR) : /* [${Rs}${inc}],$Rd */ 6383{ 6384 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6385 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6386#define FLD(f) abuf->fields.sfmt_addcbr.f 6387 int UNUSED written = 0; 6388 IADDR UNUSED pc = abuf->addr; 6389 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 6390 6391{ 6392 SI tmp_tmpopd; 6393 SI tmp_tmpops; 6394 BI tmp_carry; 6395 SI tmp_newval; 6396 tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))); 6397 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6398 tmp_carry = CPU (h_cbit); 6399 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6400 { 6401 SI opval = tmp_newval; 6402 SET_H_GR (FLD (f_operand2), opval); 6403 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6404 } 6405{ 6406 { 6407 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 6408 CPU (h_cbit) = opval; 6409 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6410 } 6411 { 6412 BI opval = LTSI (tmp_newval, 0); 6413 CPU (h_nbit) = opval; 6414 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6415 } 6416 { 6417 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6418 CPU (h_zbit) = opval; 6419 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6420 } 6421 { 6422 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 6423 CPU (h_vbit) = opval; 6424 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6425 } 6426{ 6427 { 6428 BI opval = 0; 6429 CPU (h_xbit) = opval; 6430 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6431 } 6432 { 6433 BI opval = 0; 6434 SET_H_INSN_PREFIXED_P (opval); 6435 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6436 } 6437} 6438} 6439} 6440 6441#undef FLD 6442} 6443 NEXT (vpc); 6444 6445 CASE (sem, INSN_ADDSCWR) : /* [${Rs}${inc}],$Rd */ 6446{ 6447 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6448 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6449#define FLD(f) abuf->fields.sfmt_addcwr.f 6450 int UNUSED written = 0; 6451 IADDR UNUSED pc = abuf->addr; 6452 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 6453 6454{ 6455 SI tmp_tmpopd; 6456 SI tmp_tmpops; 6457 BI tmp_carry; 6458 SI tmp_newval; 6459 tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))); 6460 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6461 tmp_carry = CPU (h_cbit); 6462 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6463 { 6464 SI opval = tmp_newval; 6465 SET_H_GR (FLD (f_operand2), opval); 6466 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6467 } 6468{ 6469 { 6470 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 6471 CPU (h_cbit) = opval; 6472 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6473 } 6474 { 6475 BI opval = LTSI (tmp_newval, 0); 6476 CPU (h_nbit) = opval; 6477 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6478 } 6479 { 6480 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6481 CPU (h_zbit) = opval; 6482 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6483 } 6484 { 6485 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 6486 CPU (h_vbit) = opval; 6487 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6488 } 6489{ 6490 { 6491 BI opval = 0; 6492 CPU (h_xbit) = opval; 6493 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6494 } 6495 { 6496 BI opval = 0; 6497 SET_H_INSN_PREFIXED_P (opval); 6498 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6499 } 6500} 6501} 6502} 6503 6504#undef FLD 6505} 6506 NEXT (vpc); 6507 6508 CASE (sem, INSN_ADDU_B_R) : /* addu.b $Rs,$Rd */ 6509{ 6510 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6511 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6512#define FLD(f) abuf->fields.sfmt_addc_m.f 6513 int UNUSED written = 0; 6514 IADDR UNUSED pc = abuf->addr; 6515 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 6516 6517{ 6518 SI tmp_tmpopd; 6519 SI tmp_tmpops; 6520 BI tmp_carry; 6521 SI tmp_newval; 6522 tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1)))); 6523 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6524 tmp_carry = CPU (h_cbit); 6525 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6526 { 6527 SI opval = tmp_newval; 6528 SET_H_GR (FLD (f_operand2), opval); 6529 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6530 } 6531{ 6532 { 6533 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 6534 CPU (h_cbit) = opval; 6535 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6536 } 6537 { 6538 BI opval = LTSI (tmp_newval, 0); 6539 CPU (h_nbit) = opval; 6540 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6541 } 6542 { 6543 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6544 CPU (h_zbit) = opval; 6545 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6546 } 6547 { 6548 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 6549 CPU (h_vbit) = opval; 6550 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6551 } 6552{ 6553 { 6554 BI opval = 0; 6555 CPU (h_xbit) = opval; 6556 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6557 } 6558 { 6559 BI opval = 0; 6560 SET_H_INSN_PREFIXED_P (opval); 6561 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6562 } 6563} 6564} 6565} 6566 6567#undef FLD 6568} 6569 NEXT (vpc); 6570 6571 CASE (sem, INSN_ADDU_W_R) : /* addu.w $Rs,$Rd */ 6572{ 6573 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6574 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6575#define FLD(f) abuf->fields.sfmt_addc_m.f 6576 int UNUSED written = 0; 6577 IADDR UNUSED pc = abuf->addr; 6578 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 6579 6580{ 6581 SI tmp_tmpopd; 6582 SI tmp_tmpops; 6583 BI tmp_carry; 6584 SI tmp_newval; 6585 tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1)))); 6586 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6587 tmp_carry = CPU (h_cbit); 6588 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6589 { 6590 SI opval = tmp_newval; 6591 SET_H_GR (FLD (f_operand2), opval); 6592 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6593 } 6594{ 6595 { 6596 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 6597 CPU (h_cbit) = opval; 6598 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6599 } 6600 { 6601 BI opval = LTSI (tmp_newval, 0); 6602 CPU (h_nbit) = opval; 6603 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6604 } 6605 { 6606 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6607 CPU (h_zbit) = opval; 6608 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6609 } 6610 { 6611 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 6612 CPU (h_vbit) = opval; 6613 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6614 } 6615{ 6616 { 6617 BI opval = 0; 6618 CPU (h_xbit) = opval; 6619 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6620 } 6621 { 6622 BI opval = 0; 6623 SET_H_INSN_PREFIXED_P (opval); 6624 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6625 } 6626} 6627} 6628} 6629 6630#undef FLD 6631} 6632 NEXT (vpc); 6633 6634 CASE (sem, INSN_ADDU_M_B_M) : /* addu-m.b [${Rs}${inc}],$Rd */ 6635{ 6636 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6637 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6638#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 6639 int UNUSED written = 0; 6640 IADDR UNUSED pc = abuf->addr; 6641 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 6642 6643{ 6644 SI tmp_tmpopd; 6645 SI tmp_tmpops; 6646 BI tmp_carry; 6647 SI tmp_newval; 6648 tmp_tmpops = ZEXTQISI (({ SI tmp_addr; 6649 QI tmp_tmp_mem; 6650 BI tmp_postinc; 6651 tmp_postinc = FLD (f_memmode); 6652; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 6653; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 6654; if (NEBI (tmp_postinc, 0)) { 6655{ 6656if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 6657 tmp_addr = ADDSI (tmp_addr, 1); 6658} 6659 { 6660 SI opval = tmp_addr; 6661 SET_H_GR (FLD (f_operand1), opval); 6662 written |= (1 << 11); 6663 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6664 } 6665} 6666} 6667; tmp_tmp_mem; })); 6668 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6669 tmp_carry = CPU (h_cbit); 6670 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6671 { 6672 SI opval = tmp_newval; 6673 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 6674 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6675 } 6676{ 6677 { 6678 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 6679 CPU (h_cbit) = opval; 6680 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6681 } 6682 { 6683 BI opval = LTSI (tmp_newval, 0); 6684 CPU (h_nbit) = opval; 6685 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6686 } 6687 { 6688 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6689 CPU (h_zbit) = opval; 6690 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6691 } 6692 { 6693 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 6694 CPU (h_vbit) = opval; 6695 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6696 } 6697{ 6698 { 6699 BI opval = 0; 6700 CPU (h_xbit) = opval; 6701 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6702 } 6703 { 6704 BI opval = 0; 6705 SET_H_INSN_PREFIXED_P (opval); 6706 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6707 } 6708} 6709} 6710} 6711 6712 abuf->written = written; 6713#undef FLD 6714} 6715 NEXT (vpc); 6716 6717 CASE (sem, INSN_ADDU_M_W_M) : /* addu-m.w [${Rs}${inc}],$Rd */ 6718{ 6719 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6720 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6721#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 6722 int UNUSED written = 0; 6723 IADDR UNUSED pc = abuf->addr; 6724 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 6725 6726{ 6727 SI tmp_tmpopd; 6728 SI tmp_tmpops; 6729 BI tmp_carry; 6730 SI tmp_newval; 6731 tmp_tmpops = ZEXTHISI (({ SI tmp_addr; 6732 HI tmp_tmp_mem; 6733 BI tmp_postinc; 6734 tmp_postinc = FLD (f_memmode); 6735; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 6736; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 6737; if (NEBI (tmp_postinc, 0)) { 6738{ 6739if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 6740 tmp_addr = ADDSI (tmp_addr, 2); 6741} 6742 { 6743 SI opval = tmp_addr; 6744 SET_H_GR (FLD (f_operand1), opval); 6745 written |= (1 << 11); 6746 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6747 } 6748} 6749} 6750; tmp_tmp_mem; })); 6751 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6752 tmp_carry = CPU (h_cbit); 6753 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6754 { 6755 SI opval = tmp_newval; 6756 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 6757 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6758 } 6759{ 6760 { 6761 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 6762 CPU (h_cbit) = opval; 6763 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6764 } 6765 { 6766 BI opval = LTSI (tmp_newval, 0); 6767 CPU (h_nbit) = opval; 6768 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6769 } 6770 { 6771 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6772 CPU (h_zbit) = opval; 6773 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6774 } 6775 { 6776 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 6777 CPU (h_vbit) = opval; 6778 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6779 } 6780{ 6781 { 6782 BI opval = 0; 6783 CPU (h_xbit) = opval; 6784 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6785 } 6786 { 6787 BI opval = 0; 6788 SET_H_INSN_PREFIXED_P (opval); 6789 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6790 } 6791} 6792} 6793} 6794 6795 abuf->written = written; 6796#undef FLD 6797} 6798 NEXT (vpc); 6799 6800 CASE (sem, INSN_ADDUCBR) : /* [${Rs}${inc}],$Rd */ 6801{ 6802 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6803 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6804#define FLD(f) abuf->fields.sfmt_addcbr.f 6805 int UNUSED written = 0; 6806 IADDR UNUSED pc = abuf->addr; 6807 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 6808 6809{ 6810 SI tmp_tmpopd; 6811 SI tmp_tmpops; 6812 BI tmp_carry; 6813 SI tmp_newval; 6814 tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))); 6815 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6816 tmp_carry = CPU (h_cbit); 6817 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6818 { 6819 SI opval = tmp_newval; 6820 SET_H_GR (FLD (f_operand2), opval); 6821 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6822 } 6823{ 6824 { 6825 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 6826 CPU (h_cbit) = opval; 6827 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6828 } 6829 { 6830 BI opval = LTSI (tmp_newval, 0); 6831 CPU (h_nbit) = opval; 6832 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6833 } 6834 { 6835 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6836 CPU (h_zbit) = opval; 6837 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6838 } 6839 { 6840 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 6841 CPU (h_vbit) = opval; 6842 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6843 } 6844{ 6845 { 6846 BI opval = 0; 6847 CPU (h_xbit) = opval; 6848 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6849 } 6850 { 6851 BI opval = 0; 6852 SET_H_INSN_PREFIXED_P (opval); 6853 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6854 } 6855} 6856} 6857} 6858 6859#undef FLD 6860} 6861 NEXT (vpc); 6862 6863 CASE (sem, INSN_ADDUCWR) : /* [${Rs}${inc}],$Rd */ 6864{ 6865 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6866 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6867#define FLD(f) abuf->fields.sfmt_addcwr.f 6868 int UNUSED written = 0; 6869 IADDR UNUSED pc = abuf->addr; 6870 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 6871 6872{ 6873 SI tmp_tmpopd; 6874 SI tmp_tmpops; 6875 BI tmp_carry; 6876 SI tmp_newval; 6877 tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))); 6878 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6879 tmp_carry = CPU (h_cbit); 6880 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6881 { 6882 SI opval = tmp_newval; 6883 SET_H_GR (FLD (f_operand2), opval); 6884 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6885 } 6886{ 6887 { 6888 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 6889 CPU (h_cbit) = opval; 6890 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6891 } 6892 { 6893 BI opval = LTSI (tmp_newval, 0); 6894 CPU (h_nbit) = opval; 6895 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6896 } 6897 { 6898 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6899 CPU (h_zbit) = opval; 6900 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6901 } 6902 { 6903 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 6904 CPU (h_vbit) = opval; 6905 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6906 } 6907{ 6908 { 6909 BI opval = 0; 6910 CPU (h_xbit) = opval; 6911 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6912 } 6913 { 6914 BI opval = 0; 6915 SET_H_INSN_PREFIXED_P (opval); 6916 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6917 } 6918} 6919} 6920} 6921 6922#undef FLD 6923} 6924 NEXT (vpc); 6925 6926 CASE (sem, INSN_SUB_B_R) : /* sub.b $Rs,$Rd */ 6927{ 6928 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6929 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6930#define FLD(f) abuf->fields.sfmt_addc_m.f 6931 int UNUSED written = 0; 6932 IADDR UNUSED pc = abuf->addr; 6933 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 6934 6935{ 6936 QI tmp_tmpopd; 6937 QI tmp_tmpops; 6938 BI tmp_carry; 6939 QI tmp_newval; 6940 tmp_tmpops = GET_H_GR (FLD (f_operand1)); 6941 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 6942 tmp_carry = CPU (h_cbit); 6943 tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 6944{ 6945 SI tmp_oldregval; 6946 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 6947 { 6948 SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); 6949 SET_H_GR (FLD (f_operand2), opval); 6950 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 6951 } 6952} 6953{ 6954 { 6955 BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0)))); 6956 CPU (h_cbit) = opval; 6957 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 6958 } 6959 { 6960 BI opval = LTQI (tmp_newval, 0); 6961 CPU (h_nbit) = opval; 6962 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 6963 } 6964 { 6965 BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 6966 CPU (h_zbit) = opval; 6967 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 6968 } 6969 { 6970 BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0))); 6971 CPU (h_vbit) = opval; 6972 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 6973 } 6974{ 6975 { 6976 BI opval = 0; 6977 CPU (h_xbit) = opval; 6978 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 6979 } 6980 { 6981 BI opval = 0; 6982 SET_H_INSN_PREFIXED_P (opval); 6983 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 6984 } 6985} 6986} 6987} 6988 6989#undef FLD 6990} 6991 NEXT (vpc); 6992 6993 CASE (sem, INSN_SUB_W_R) : /* sub.w $Rs,$Rd */ 6994{ 6995 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 6996 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 6997#define FLD(f) abuf->fields.sfmt_addc_m.f 6998 int UNUSED written = 0; 6999 IADDR UNUSED pc = abuf->addr; 7000 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 7001 7002{ 7003 HI tmp_tmpopd; 7004 HI tmp_tmpops; 7005 BI tmp_carry; 7006 HI tmp_newval; 7007 tmp_tmpops = GET_H_GR (FLD (f_operand1)); 7008 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7009 tmp_carry = CPU (h_cbit); 7010 tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7011{ 7012 SI tmp_oldregval; 7013 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 7014 { 7015 SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 7016 SET_H_GR (FLD (f_operand2), opval); 7017 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7018 } 7019} 7020{ 7021 { 7022 BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0)))); 7023 CPU (h_cbit) = opval; 7024 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7025 } 7026 { 7027 BI opval = LTHI (tmp_newval, 0); 7028 CPU (h_nbit) = opval; 7029 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7030 } 7031 { 7032 BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7033 CPU (h_zbit) = opval; 7034 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7035 } 7036 { 7037 BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0))); 7038 CPU (h_vbit) = opval; 7039 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7040 } 7041{ 7042 { 7043 BI opval = 0; 7044 CPU (h_xbit) = opval; 7045 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7046 } 7047 { 7048 BI opval = 0; 7049 SET_H_INSN_PREFIXED_P (opval); 7050 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7051 } 7052} 7053} 7054} 7055 7056#undef FLD 7057} 7058 NEXT (vpc); 7059 7060 CASE (sem, INSN_SUB_D_R) : /* sub.d $Rs,$Rd */ 7061{ 7062 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7063 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7064#define FLD(f) abuf->fields.sfmt_addc_m.f 7065 int UNUSED written = 0; 7066 IADDR UNUSED pc = abuf->addr; 7067 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 7068 7069{ 7070 SI tmp_tmpopd; 7071 SI tmp_tmpops; 7072 BI tmp_carry; 7073 SI tmp_newval; 7074 tmp_tmpops = GET_H_GR (FLD (f_operand1)); 7075 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7076 tmp_carry = CPU (h_cbit); 7077 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7078 { 7079 SI opval = tmp_newval; 7080 SET_H_GR (FLD (f_operand2), opval); 7081 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7082 } 7083{ 7084 { 7085 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 7086 CPU (h_cbit) = opval; 7087 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7088 } 7089 { 7090 BI opval = LTSI (tmp_newval, 0); 7091 CPU (h_nbit) = opval; 7092 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7093 } 7094 { 7095 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7096 CPU (h_zbit) = opval; 7097 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7098 } 7099 { 7100 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 7101 CPU (h_vbit) = opval; 7102 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7103 } 7104{ 7105 { 7106 BI opval = 0; 7107 CPU (h_xbit) = opval; 7108 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7109 } 7110 { 7111 BI opval = 0; 7112 SET_H_INSN_PREFIXED_P (opval); 7113 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7114 } 7115} 7116} 7117} 7118 7119#undef FLD 7120} 7121 NEXT (vpc); 7122 7123 CASE (sem, INSN_SUB_M_B_M) : /* sub-m.b [${Rs}${inc}],${Rd} */ 7124{ 7125 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7126 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7127#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 7128 int UNUSED written = 0; 7129 IADDR UNUSED pc = abuf->addr; 7130 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 7131 7132{ 7133 QI tmp_tmpopd; 7134 QI tmp_tmpops; 7135 BI tmp_carry; 7136 QI tmp_newval; 7137 tmp_tmpops = ({ SI tmp_addr; 7138 QI tmp_tmp_mem; 7139 BI tmp_postinc; 7140 tmp_postinc = FLD (f_memmode); 7141; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 7142; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 7143; if (NEBI (tmp_postinc, 0)) { 7144{ 7145if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 7146 tmp_addr = ADDSI (tmp_addr, 1); 7147} 7148 { 7149 SI opval = tmp_addr; 7150 SET_H_GR (FLD (f_operand1), opval); 7151 written |= (1 << 12); 7152 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7153 } 7154} 7155} 7156; tmp_tmp_mem; }); 7157 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7158 tmp_carry = CPU (h_cbit); 7159 tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7160{ 7161 SI tmp_oldregval; 7162 tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2)))); 7163 { 7164 SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); 7165 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 7166 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7167 } 7168} 7169{ 7170 { 7171 BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0)))); 7172 CPU (h_cbit) = opval; 7173 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7174 } 7175 { 7176 BI opval = LTQI (tmp_newval, 0); 7177 CPU (h_nbit) = opval; 7178 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7179 } 7180 { 7181 BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7182 CPU (h_zbit) = opval; 7183 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7184 } 7185 { 7186 BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0))); 7187 CPU (h_vbit) = opval; 7188 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7189 } 7190{ 7191 { 7192 BI opval = 0; 7193 CPU (h_xbit) = opval; 7194 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7195 } 7196 { 7197 BI opval = 0; 7198 SET_H_INSN_PREFIXED_P (opval); 7199 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7200 } 7201} 7202} 7203} 7204 7205 abuf->written = written; 7206#undef FLD 7207} 7208 NEXT (vpc); 7209 7210 CASE (sem, INSN_SUB_M_W_M) : /* sub-m.w [${Rs}${inc}],${Rd} */ 7211{ 7212 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7213 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7214#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 7215 int UNUSED written = 0; 7216 IADDR UNUSED pc = abuf->addr; 7217 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 7218 7219{ 7220 HI tmp_tmpopd; 7221 HI tmp_tmpops; 7222 BI tmp_carry; 7223 HI tmp_newval; 7224 tmp_tmpops = ({ SI tmp_addr; 7225 HI tmp_tmp_mem; 7226 BI tmp_postinc; 7227 tmp_postinc = FLD (f_memmode); 7228; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 7229; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 7230; if (NEBI (tmp_postinc, 0)) { 7231{ 7232if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 7233 tmp_addr = ADDSI (tmp_addr, 2); 7234} 7235 { 7236 SI opval = tmp_addr; 7237 SET_H_GR (FLD (f_operand1), opval); 7238 written |= (1 << 12); 7239 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7240 } 7241} 7242} 7243; tmp_tmp_mem; }); 7244 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7245 tmp_carry = CPU (h_cbit); 7246 tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7247{ 7248 SI tmp_oldregval; 7249 tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2)))); 7250 { 7251 SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 7252 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 7253 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7254 } 7255} 7256{ 7257 { 7258 BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0)))); 7259 CPU (h_cbit) = opval; 7260 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7261 } 7262 { 7263 BI opval = LTHI (tmp_newval, 0); 7264 CPU (h_nbit) = opval; 7265 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7266 } 7267 { 7268 BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7269 CPU (h_zbit) = opval; 7270 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7271 } 7272 { 7273 BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0))); 7274 CPU (h_vbit) = opval; 7275 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7276 } 7277{ 7278 { 7279 BI opval = 0; 7280 CPU (h_xbit) = opval; 7281 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7282 } 7283 { 7284 BI opval = 0; 7285 SET_H_INSN_PREFIXED_P (opval); 7286 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7287 } 7288} 7289} 7290} 7291 7292 abuf->written = written; 7293#undef FLD 7294} 7295 NEXT (vpc); 7296 7297 CASE (sem, INSN_SUB_M_D_M) : /* sub-m.d [${Rs}${inc}],${Rd} */ 7298{ 7299 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7300 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7301#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 7302 int UNUSED written = 0; 7303 IADDR UNUSED pc = abuf->addr; 7304 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 7305 7306{ 7307 SI tmp_tmpopd; 7308 SI tmp_tmpops; 7309 BI tmp_carry; 7310 SI tmp_newval; 7311 tmp_tmpops = ({ SI tmp_addr; 7312 SI tmp_tmp_mem; 7313 BI tmp_postinc; 7314 tmp_postinc = FLD (f_memmode); 7315; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 7316; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 7317; if (NEBI (tmp_postinc, 0)) { 7318{ 7319if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 7320 tmp_addr = ADDSI (tmp_addr, 4); 7321} 7322 { 7323 SI opval = tmp_addr; 7324 SET_H_GR (FLD (f_operand1), opval); 7325 written |= (1 << 11); 7326 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7327 } 7328} 7329} 7330; tmp_tmp_mem; }); 7331 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7332 tmp_carry = CPU (h_cbit); 7333 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7334 { 7335 SI opval = tmp_newval; 7336 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 7337 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7338 } 7339{ 7340 { 7341 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 7342 CPU (h_cbit) = opval; 7343 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7344 } 7345 { 7346 BI opval = LTSI (tmp_newval, 0); 7347 CPU (h_nbit) = opval; 7348 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7349 } 7350 { 7351 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7352 CPU (h_zbit) = opval; 7353 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7354 } 7355 { 7356 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 7357 CPU (h_vbit) = opval; 7358 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7359 } 7360{ 7361 { 7362 BI opval = 0; 7363 CPU (h_xbit) = opval; 7364 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7365 } 7366 { 7367 BI opval = 0; 7368 SET_H_INSN_PREFIXED_P (opval); 7369 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7370 } 7371} 7372} 7373} 7374 7375 abuf->written = written; 7376#undef FLD 7377} 7378 NEXT (vpc); 7379 7380 CASE (sem, INSN_SUBCBR) : /* sub.b ${sconst8}],${Rd} */ 7381{ 7382 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7383 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7384#define FLD(f) abuf->fields.sfmt_addcbr.f 7385 int UNUSED written = 0; 7386 IADDR UNUSED pc = abuf->addr; 7387 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 7388 7389{ 7390 QI tmp_tmpopd; 7391 QI tmp_tmpops; 7392 BI tmp_carry; 7393 QI tmp_newval; 7394 tmp_tmpops = FLD (f_indir_pc__byte); 7395 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7396 tmp_carry = CPU (h_cbit); 7397 tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7398{ 7399 SI tmp_oldregval; 7400 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 7401 { 7402 SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); 7403 SET_H_GR (FLD (f_operand2), opval); 7404 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7405 } 7406} 7407{ 7408 { 7409 BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0)))); 7410 CPU (h_cbit) = opval; 7411 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7412 } 7413 { 7414 BI opval = LTQI (tmp_newval, 0); 7415 CPU (h_nbit) = opval; 7416 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7417 } 7418 { 7419 BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7420 CPU (h_zbit) = opval; 7421 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7422 } 7423 { 7424 BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0))); 7425 CPU (h_vbit) = opval; 7426 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7427 } 7428{ 7429 { 7430 BI opval = 0; 7431 CPU (h_xbit) = opval; 7432 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7433 } 7434 { 7435 BI opval = 0; 7436 SET_H_INSN_PREFIXED_P (opval); 7437 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7438 } 7439} 7440} 7441} 7442 7443#undef FLD 7444} 7445 NEXT (vpc); 7446 7447 CASE (sem, INSN_SUBCWR) : /* sub.w ${sconst16}],${Rd} */ 7448{ 7449 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7450 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7451#define FLD(f) abuf->fields.sfmt_addcwr.f 7452 int UNUSED written = 0; 7453 IADDR UNUSED pc = abuf->addr; 7454 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 7455 7456{ 7457 HI tmp_tmpopd; 7458 HI tmp_tmpops; 7459 BI tmp_carry; 7460 HI tmp_newval; 7461 tmp_tmpops = FLD (f_indir_pc__word); 7462 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7463 tmp_carry = CPU (h_cbit); 7464 tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7465{ 7466 SI tmp_oldregval; 7467 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 7468 { 7469 SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 7470 SET_H_GR (FLD (f_operand2), opval); 7471 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7472 } 7473} 7474{ 7475 { 7476 BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0)))); 7477 CPU (h_cbit) = opval; 7478 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7479 } 7480 { 7481 BI opval = LTHI (tmp_newval, 0); 7482 CPU (h_nbit) = opval; 7483 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7484 } 7485 { 7486 BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7487 CPU (h_zbit) = opval; 7488 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7489 } 7490 { 7491 BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0))); 7492 CPU (h_vbit) = opval; 7493 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7494 } 7495{ 7496 { 7497 BI opval = 0; 7498 CPU (h_xbit) = opval; 7499 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7500 } 7501 { 7502 BI opval = 0; 7503 SET_H_INSN_PREFIXED_P (opval); 7504 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7505 } 7506} 7507} 7508} 7509 7510#undef FLD 7511} 7512 NEXT (vpc); 7513 7514 CASE (sem, INSN_SUBCDR) : /* sub.d ${const32}],${Rd} */ 7515{ 7516 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7517 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7518#define FLD(f) abuf->fields.sfmt_addcdr.f 7519 int UNUSED written = 0; 7520 IADDR UNUSED pc = abuf->addr; 7521 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 7522 7523{ 7524 SI tmp_tmpopd; 7525 SI tmp_tmpops; 7526 BI tmp_carry; 7527 SI tmp_newval; 7528 tmp_tmpops = FLD (f_indir_pc__dword); 7529 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7530 tmp_carry = CPU (h_cbit); 7531 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7532 { 7533 SI opval = tmp_newval; 7534 SET_H_GR (FLD (f_operand2), opval); 7535 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7536 } 7537{ 7538 { 7539 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 7540 CPU (h_cbit) = opval; 7541 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7542 } 7543 { 7544 BI opval = LTSI (tmp_newval, 0); 7545 CPU (h_nbit) = opval; 7546 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7547 } 7548 { 7549 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7550 CPU (h_zbit) = opval; 7551 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7552 } 7553 { 7554 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 7555 CPU (h_vbit) = opval; 7556 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7557 } 7558{ 7559 { 7560 BI opval = 0; 7561 CPU (h_xbit) = opval; 7562 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7563 } 7564 { 7565 BI opval = 0; 7566 SET_H_INSN_PREFIXED_P (opval); 7567 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7568 } 7569} 7570} 7571} 7572 7573#undef FLD 7574} 7575 NEXT (vpc); 7576 7577 CASE (sem, INSN_SUBS_B_R) : /* subs.b $Rs,$Rd */ 7578{ 7579 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7580 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7581#define FLD(f) abuf->fields.sfmt_addc_m.f 7582 int UNUSED written = 0; 7583 IADDR UNUSED pc = abuf->addr; 7584 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 7585 7586{ 7587 SI tmp_tmpopd; 7588 SI tmp_tmpops; 7589 BI tmp_carry; 7590 SI tmp_newval; 7591 tmp_tmpops = EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1)))); 7592 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7593 tmp_carry = CPU (h_cbit); 7594 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7595 { 7596 SI opval = tmp_newval; 7597 SET_H_GR (FLD (f_operand2), opval); 7598 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7599 } 7600{ 7601 { 7602 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 7603 CPU (h_cbit) = opval; 7604 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7605 } 7606 { 7607 BI opval = LTSI (tmp_newval, 0); 7608 CPU (h_nbit) = opval; 7609 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7610 } 7611 { 7612 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7613 CPU (h_zbit) = opval; 7614 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7615 } 7616 { 7617 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 7618 CPU (h_vbit) = opval; 7619 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7620 } 7621{ 7622 { 7623 BI opval = 0; 7624 CPU (h_xbit) = opval; 7625 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7626 } 7627 { 7628 BI opval = 0; 7629 SET_H_INSN_PREFIXED_P (opval); 7630 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7631 } 7632} 7633} 7634} 7635 7636#undef FLD 7637} 7638 NEXT (vpc); 7639 7640 CASE (sem, INSN_SUBS_W_R) : /* subs.w $Rs,$Rd */ 7641{ 7642 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7643 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7644#define FLD(f) abuf->fields.sfmt_addc_m.f 7645 int UNUSED written = 0; 7646 IADDR UNUSED pc = abuf->addr; 7647 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 7648 7649{ 7650 SI tmp_tmpopd; 7651 SI tmp_tmpops; 7652 BI tmp_carry; 7653 SI tmp_newval; 7654 tmp_tmpops = EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1)))); 7655 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7656 tmp_carry = CPU (h_cbit); 7657 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7658 { 7659 SI opval = tmp_newval; 7660 SET_H_GR (FLD (f_operand2), opval); 7661 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7662 } 7663{ 7664 { 7665 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 7666 CPU (h_cbit) = opval; 7667 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7668 } 7669 { 7670 BI opval = LTSI (tmp_newval, 0); 7671 CPU (h_nbit) = opval; 7672 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7673 } 7674 { 7675 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7676 CPU (h_zbit) = opval; 7677 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7678 } 7679 { 7680 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 7681 CPU (h_vbit) = opval; 7682 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7683 } 7684{ 7685 { 7686 BI opval = 0; 7687 CPU (h_xbit) = opval; 7688 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7689 } 7690 { 7691 BI opval = 0; 7692 SET_H_INSN_PREFIXED_P (opval); 7693 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7694 } 7695} 7696} 7697} 7698 7699#undef FLD 7700} 7701 NEXT (vpc); 7702 7703 CASE (sem, INSN_SUBS_M_B_M) : /* subs-m.b [${Rs}${inc}],$Rd */ 7704{ 7705 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7706 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7707#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 7708 int UNUSED written = 0; 7709 IADDR UNUSED pc = abuf->addr; 7710 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 7711 7712{ 7713 SI tmp_tmpopd; 7714 SI tmp_tmpops; 7715 BI tmp_carry; 7716 SI tmp_newval; 7717 tmp_tmpops = EXTQISI (({ SI tmp_addr; 7718 QI tmp_tmp_mem; 7719 BI tmp_postinc; 7720 tmp_postinc = FLD (f_memmode); 7721; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 7722; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 7723; if (NEBI (tmp_postinc, 0)) { 7724{ 7725if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 7726 tmp_addr = ADDSI (tmp_addr, 1); 7727} 7728 { 7729 SI opval = tmp_addr; 7730 SET_H_GR (FLD (f_operand1), opval); 7731 written |= (1 << 11); 7732 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7733 } 7734} 7735} 7736; tmp_tmp_mem; })); 7737 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7738 tmp_carry = CPU (h_cbit); 7739 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7740 { 7741 SI opval = tmp_newval; 7742 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 7743 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7744 } 7745{ 7746 { 7747 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 7748 CPU (h_cbit) = opval; 7749 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7750 } 7751 { 7752 BI opval = LTSI (tmp_newval, 0); 7753 CPU (h_nbit) = opval; 7754 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7755 } 7756 { 7757 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7758 CPU (h_zbit) = opval; 7759 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7760 } 7761 { 7762 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 7763 CPU (h_vbit) = opval; 7764 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7765 } 7766{ 7767 { 7768 BI opval = 0; 7769 CPU (h_xbit) = opval; 7770 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7771 } 7772 { 7773 BI opval = 0; 7774 SET_H_INSN_PREFIXED_P (opval); 7775 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7776 } 7777} 7778} 7779} 7780 7781 abuf->written = written; 7782#undef FLD 7783} 7784 NEXT (vpc); 7785 7786 CASE (sem, INSN_SUBS_M_W_M) : /* subs-m.w [${Rs}${inc}],$Rd */ 7787{ 7788 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7789 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7790#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 7791 int UNUSED written = 0; 7792 IADDR UNUSED pc = abuf->addr; 7793 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 7794 7795{ 7796 SI tmp_tmpopd; 7797 SI tmp_tmpops; 7798 BI tmp_carry; 7799 SI tmp_newval; 7800 tmp_tmpops = EXTHISI (({ SI tmp_addr; 7801 HI tmp_tmp_mem; 7802 BI tmp_postinc; 7803 tmp_postinc = FLD (f_memmode); 7804; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 7805; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 7806; if (NEBI (tmp_postinc, 0)) { 7807{ 7808if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 7809 tmp_addr = ADDSI (tmp_addr, 2); 7810} 7811 { 7812 SI opval = tmp_addr; 7813 SET_H_GR (FLD (f_operand1), opval); 7814 written |= (1 << 11); 7815 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7816 } 7817} 7818} 7819; tmp_tmp_mem; })); 7820 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7821 tmp_carry = CPU (h_cbit); 7822 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7823 { 7824 SI opval = tmp_newval; 7825 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 7826 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7827 } 7828{ 7829 { 7830 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 7831 CPU (h_cbit) = opval; 7832 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7833 } 7834 { 7835 BI opval = LTSI (tmp_newval, 0); 7836 CPU (h_nbit) = opval; 7837 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7838 } 7839 { 7840 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7841 CPU (h_zbit) = opval; 7842 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7843 } 7844 { 7845 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 7846 CPU (h_vbit) = opval; 7847 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7848 } 7849{ 7850 { 7851 BI opval = 0; 7852 CPU (h_xbit) = opval; 7853 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7854 } 7855 { 7856 BI opval = 0; 7857 SET_H_INSN_PREFIXED_P (opval); 7858 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7859 } 7860} 7861} 7862} 7863 7864 abuf->written = written; 7865#undef FLD 7866} 7867 NEXT (vpc); 7868 7869 CASE (sem, INSN_SUBSCBR) : /* [${Rs}${inc}],$Rd */ 7870{ 7871 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7872 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7873#define FLD(f) abuf->fields.sfmt_addcbr.f 7874 int UNUSED written = 0; 7875 IADDR UNUSED pc = abuf->addr; 7876 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 7877 7878{ 7879 SI tmp_tmpopd; 7880 SI tmp_tmpops; 7881 BI tmp_carry; 7882 SI tmp_newval; 7883 tmp_tmpops = EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))); 7884 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7885 tmp_carry = CPU (h_cbit); 7886 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7887 { 7888 SI opval = tmp_newval; 7889 SET_H_GR (FLD (f_operand2), opval); 7890 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7891 } 7892{ 7893 { 7894 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 7895 CPU (h_cbit) = opval; 7896 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7897 } 7898 { 7899 BI opval = LTSI (tmp_newval, 0); 7900 CPU (h_nbit) = opval; 7901 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7902 } 7903 { 7904 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7905 CPU (h_zbit) = opval; 7906 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7907 } 7908 { 7909 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 7910 CPU (h_vbit) = opval; 7911 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7912 } 7913{ 7914 { 7915 BI opval = 0; 7916 CPU (h_xbit) = opval; 7917 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7918 } 7919 { 7920 BI opval = 0; 7921 SET_H_INSN_PREFIXED_P (opval); 7922 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7923 } 7924} 7925} 7926} 7927 7928#undef FLD 7929} 7930 NEXT (vpc); 7931 7932 CASE (sem, INSN_SUBSCWR) : /* [${Rs}${inc}],$Rd */ 7933{ 7934 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7935 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7936#define FLD(f) abuf->fields.sfmt_addcwr.f 7937 int UNUSED written = 0; 7938 IADDR UNUSED pc = abuf->addr; 7939 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 7940 7941{ 7942 SI tmp_tmpopd; 7943 SI tmp_tmpops; 7944 BI tmp_carry; 7945 SI tmp_newval; 7946 tmp_tmpops = EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))); 7947 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 7948 tmp_carry = CPU (h_cbit); 7949 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 7950 { 7951 SI opval = tmp_newval; 7952 SET_H_GR (FLD (f_operand2), opval); 7953 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 7954 } 7955{ 7956 { 7957 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 7958 CPU (h_cbit) = opval; 7959 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 7960 } 7961 { 7962 BI opval = LTSI (tmp_newval, 0); 7963 CPU (h_nbit) = opval; 7964 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 7965 } 7966 { 7967 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 7968 CPU (h_zbit) = opval; 7969 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 7970 } 7971 { 7972 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 7973 CPU (h_vbit) = opval; 7974 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 7975 } 7976{ 7977 { 7978 BI opval = 0; 7979 CPU (h_xbit) = opval; 7980 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 7981 } 7982 { 7983 BI opval = 0; 7984 SET_H_INSN_PREFIXED_P (opval); 7985 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 7986 } 7987} 7988} 7989} 7990 7991#undef FLD 7992} 7993 NEXT (vpc); 7994 7995 CASE (sem, INSN_SUBU_B_R) : /* subu.b $Rs,$Rd */ 7996{ 7997 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 7998 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 7999#define FLD(f) abuf->fields.sfmt_addc_m.f 8000 int UNUSED written = 0; 8001 IADDR UNUSED pc = abuf->addr; 8002 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 8003 8004{ 8005 SI tmp_tmpopd; 8006 SI tmp_tmpops; 8007 BI tmp_carry; 8008 SI tmp_newval; 8009 tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1)))); 8010 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 8011 tmp_carry = CPU (h_cbit); 8012 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 8013 { 8014 SI opval = tmp_newval; 8015 SET_H_GR (FLD (f_operand2), opval); 8016 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8017 } 8018{ 8019 { 8020 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 8021 CPU (h_cbit) = opval; 8022 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 8023 } 8024 { 8025 BI opval = LTSI (tmp_newval, 0); 8026 CPU (h_nbit) = opval; 8027 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 8028 } 8029 { 8030 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 8031 CPU (h_zbit) = opval; 8032 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 8033 } 8034 { 8035 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 8036 CPU (h_vbit) = opval; 8037 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 8038 } 8039{ 8040 { 8041 BI opval = 0; 8042 CPU (h_xbit) = opval; 8043 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8044 } 8045 { 8046 BI opval = 0; 8047 SET_H_INSN_PREFIXED_P (opval); 8048 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8049 } 8050} 8051} 8052} 8053 8054#undef FLD 8055} 8056 NEXT (vpc); 8057 8058 CASE (sem, INSN_SUBU_W_R) : /* subu.w $Rs,$Rd */ 8059{ 8060 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8061 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8062#define FLD(f) abuf->fields.sfmt_addc_m.f 8063 int UNUSED written = 0; 8064 IADDR UNUSED pc = abuf->addr; 8065 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 8066 8067{ 8068 SI tmp_tmpopd; 8069 SI tmp_tmpops; 8070 BI tmp_carry; 8071 SI tmp_newval; 8072 tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1)))); 8073 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 8074 tmp_carry = CPU (h_cbit); 8075 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 8076 { 8077 SI opval = tmp_newval; 8078 SET_H_GR (FLD (f_operand2), opval); 8079 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8080 } 8081{ 8082 { 8083 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 8084 CPU (h_cbit) = opval; 8085 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 8086 } 8087 { 8088 BI opval = LTSI (tmp_newval, 0); 8089 CPU (h_nbit) = opval; 8090 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 8091 } 8092 { 8093 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 8094 CPU (h_zbit) = opval; 8095 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 8096 } 8097 { 8098 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 8099 CPU (h_vbit) = opval; 8100 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 8101 } 8102{ 8103 { 8104 BI opval = 0; 8105 CPU (h_xbit) = opval; 8106 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8107 } 8108 { 8109 BI opval = 0; 8110 SET_H_INSN_PREFIXED_P (opval); 8111 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8112 } 8113} 8114} 8115} 8116 8117#undef FLD 8118} 8119 NEXT (vpc); 8120 8121 CASE (sem, INSN_SUBU_M_B_M) : /* subu-m.b [${Rs}${inc}],$Rd */ 8122{ 8123 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8124 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8125#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 8126 int UNUSED written = 0; 8127 IADDR UNUSED pc = abuf->addr; 8128 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 8129 8130{ 8131 SI tmp_tmpopd; 8132 SI tmp_tmpops; 8133 BI tmp_carry; 8134 SI tmp_newval; 8135 tmp_tmpops = ZEXTQISI (({ SI tmp_addr; 8136 QI tmp_tmp_mem; 8137 BI tmp_postinc; 8138 tmp_postinc = FLD (f_memmode); 8139; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 8140; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 8141; if (NEBI (tmp_postinc, 0)) { 8142{ 8143if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 8144 tmp_addr = ADDSI (tmp_addr, 1); 8145} 8146 { 8147 SI opval = tmp_addr; 8148 SET_H_GR (FLD (f_operand1), opval); 8149 written |= (1 << 11); 8150 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8151 } 8152} 8153} 8154; tmp_tmp_mem; })); 8155 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 8156 tmp_carry = CPU (h_cbit); 8157 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 8158 { 8159 SI opval = tmp_newval; 8160 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 8161 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8162 } 8163{ 8164 { 8165 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 8166 CPU (h_cbit) = opval; 8167 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 8168 } 8169 { 8170 BI opval = LTSI (tmp_newval, 0); 8171 CPU (h_nbit) = opval; 8172 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 8173 } 8174 { 8175 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 8176 CPU (h_zbit) = opval; 8177 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 8178 } 8179 { 8180 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 8181 CPU (h_vbit) = opval; 8182 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 8183 } 8184{ 8185 { 8186 BI opval = 0; 8187 CPU (h_xbit) = opval; 8188 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8189 } 8190 { 8191 BI opval = 0; 8192 SET_H_INSN_PREFIXED_P (opval); 8193 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8194 } 8195} 8196} 8197} 8198 8199 abuf->written = written; 8200#undef FLD 8201} 8202 NEXT (vpc); 8203 8204 CASE (sem, INSN_SUBU_M_W_M) : /* subu-m.w [${Rs}${inc}],$Rd */ 8205{ 8206 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8207 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8208#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 8209 int UNUSED written = 0; 8210 IADDR UNUSED pc = abuf->addr; 8211 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 8212 8213{ 8214 SI tmp_tmpopd; 8215 SI tmp_tmpops; 8216 BI tmp_carry; 8217 SI tmp_newval; 8218 tmp_tmpops = ZEXTHISI (({ SI tmp_addr; 8219 HI tmp_tmp_mem; 8220 BI tmp_postinc; 8221 tmp_postinc = FLD (f_memmode); 8222; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 8223; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 8224; if (NEBI (tmp_postinc, 0)) { 8225{ 8226if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 8227 tmp_addr = ADDSI (tmp_addr, 2); 8228} 8229 { 8230 SI opval = tmp_addr; 8231 SET_H_GR (FLD (f_operand1), opval); 8232 written |= (1 << 11); 8233 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8234 } 8235} 8236} 8237; tmp_tmp_mem; })); 8238 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 8239 tmp_carry = CPU (h_cbit); 8240 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 8241 { 8242 SI opval = tmp_newval; 8243 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 8244 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8245 } 8246{ 8247 { 8248 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 8249 CPU (h_cbit) = opval; 8250 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 8251 } 8252 { 8253 BI opval = LTSI (tmp_newval, 0); 8254 CPU (h_nbit) = opval; 8255 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 8256 } 8257 { 8258 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 8259 CPU (h_zbit) = opval; 8260 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 8261 } 8262 { 8263 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 8264 CPU (h_vbit) = opval; 8265 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 8266 } 8267{ 8268 { 8269 BI opval = 0; 8270 CPU (h_xbit) = opval; 8271 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8272 } 8273 { 8274 BI opval = 0; 8275 SET_H_INSN_PREFIXED_P (opval); 8276 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8277 } 8278} 8279} 8280} 8281 8282 abuf->written = written; 8283#undef FLD 8284} 8285 NEXT (vpc); 8286 8287 CASE (sem, INSN_SUBUCBR) : /* [${Rs}${inc}],$Rd */ 8288{ 8289 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8290 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8291#define FLD(f) abuf->fields.sfmt_addcbr.f 8292 int UNUSED written = 0; 8293 IADDR UNUSED pc = abuf->addr; 8294 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 8295 8296{ 8297 SI tmp_tmpopd; 8298 SI tmp_tmpops; 8299 BI tmp_carry; 8300 SI tmp_newval; 8301 tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))); 8302 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 8303 tmp_carry = CPU (h_cbit); 8304 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 8305 { 8306 SI opval = tmp_newval; 8307 SET_H_GR (FLD (f_operand2), opval); 8308 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8309 } 8310{ 8311 { 8312 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 8313 CPU (h_cbit) = opval; 8314 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 8315 } 8316 { 8317 BI opval = LTSI (tmp_newval, 0); 8318 CPU (h_nbit) = opval; 8319 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 8320 } 8321 { 8322 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 8323 CPU (h_zbit) = opval; 8324 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 8325 } 8326 { 8327 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 8328 CPU (h_vbit) = opval; 8329 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 8330 } 8331{ 8332 { 8333 BI opval = 0; 8334 CPU (h_xbit) = opval; 8335 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8336 } 8337 { 8338 BI opval = 0; 8339 SET_H_INSN_PREFIXED_P (opval); 8340 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8341 } 8342} 8343} 8344} 8345 8346#undef FLD 8347} 8348 NEXT (vpc); 8349 8350 CASE (sem, INSN_SUBUCWR) : /* [${Rs}${inc}],$Rd */ 8351{ 8352 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8353 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8354#define FLD(f) abuf->fields.sfmt_addcwr.f 8355 int UNUSED written = 0; 8356 IADDR UNUSED pc = abuf->addr; 8357 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 8358 8359{ 8360 SI tmp_tmpopd; 8361 SI tmp_tmpops; 8362 BI tmp_carry; 8363 SI tmp_newval; 8364 tmp_tmpops = ZEXTHISI (TRUNCSIHI (FLD (f_indir_pc__word))); 8365 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 8366 tmp_carry = CPU (h_cbit); 8367 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 8368 { 8369 SI opval = tmp_newval; 8370 SET_H_GR (FLD (f_operand2), opval); 8371 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8372 } 8373{ 8374 { 8375 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 8376 CPU (h_cbit) = opval; 8377 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 8378 } 8379 { 8380 BI opval = LTSI (tmp_newval, 0); 8381 CPU (h_nbit) = opval; 8382 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 8383 } 8384 { 8385 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 8386 CPU (h_zbit) = opval; 8387 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 8388 } 8389 { 8390 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 8391 CPU (h_vbit) = opval; 8392 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 8393 } 8394{ 8395 { 8396 BI opval = 0; 8397 CPU (h_xbit) = opval; 8398 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8399 } 8400 { 8401 BI opval = 0; 8402 SET_H_INSN_PREFIXED_P (opval); 8403 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8404 } 8405} 8406} 8407} 8408 8409#undef FLD 8410} 8411 NEXT (vpc); 8412 8413 CASE (sem, INSN_ADDC_R) : /* addc $Rs,$Rd */ 8414{ 8415 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8416 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8417#define FLD(f) abuf->fields.sfmt_addc_m.f 8418 int UNUSED written = 0; 8419 IADDR UNUSED pc = abuf->addr; 8420 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 8421 8422{ 8423CPU (h_xbit) = 1; 8424{ 8425 SI tmp_tmpopd; 8426 SI tmp_tmpops; 8427 BI tmp_carry; 8428 SI tmp_newval; 8429 tmp_tmpops = GET_H_GR (FLD (f_operand1)); 8430 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 8431 tmp_carry = CPU (h_cbit); 8432 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 8433 { 8434 SI opval = tmp_newval; 8435 SET_H_GR (FLD (f_operand2), opval); 8436 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8437 } 8438{ 8439 { 8440 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 8441 CPU (h_cbit) = opval; 8442 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 8443 } 8444 { 8445 BI opval = LTSI (tmp_newval, 0); 8446 CPU (h_nbit) = opval; 8447 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 8448 } 8449 { 8450 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 8451 CPU (h_zbit) = opval; 8452 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 8453 } 8454 { 8455 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 8456 CPU (h_vbit) = opval; 8457 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 8458 } 8459{ 8460 { 8461 BI opval = 0; 8462 CPU (h_xbit) = opval; 8463 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8464 } 8465 { 8466 BI opval = 0; 8467 SET_H_INSN_PREFIXED_P (opval); 8468 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8469 } 8470} 8471} 8472} 8473} 8474 8475#undef FLD 8476} 8477 NEXT (vpc); 8478 8479 CASE (sem, INSN_ADDC_M) : /* addc [${Rs}${inc}],${Rd} */ 8480{ 8481 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8482 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8483#define FLD(f) abuf->fields.sfmt_addc_m.f 8484 int UNUSED written = 0; 8485 IADDR UNUSED pc = abuf->addr; 8486 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 8487 8488{ 8489CPU (h_xbit) = 1; 8490{ 8491 SI tmp_tmpopd; 8492 SI tmp_tmpops; 8493 BI tmp_carry; 8494 SI tmp_newval; 8495 tmp_tmpops = ({ SI tmp_addr; 8496 SI tmp_tmp_mem; 8497 BI tmp_postinc; 8498 tmp_postinc = FLD (f_memmode); 8499; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 8500; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 8501; if (NEBI (tmp_postinc, 0)) { 8502{ 8503if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 8504 tmp_addr = ADDSI (tmp_addr, 4); 8505} 8506 { 8507 SI opval = tmp_addr; 8508 SET_H_GR (FLD (f_operand1), opval); 8509 written |= (1 << 10); 8510 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8511 } 8512} 8513} 8514; tmp_tmp_mem; }); 8515 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 8516 tmp_carry = CPU (h_cbit); 8517 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 8518 { 8519 SI opval = tmp_newval; 8520 SET_H_GR (FLD (f_operand2), opval); 8521 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8522 } 8523{ 8524 { 8525 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 8526 CPU (h_cbit) = opval; 8527 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 8528 } 8529 { 8530 BI opval = LTSI (tmp_newval, 0); 8531 CPU (h_nbit) = opval; 8532 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 8533 } 8534 { 8535 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 8536 CPU (h_zbit) = opval; 8537 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 8538 } 8539 { 8540 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 8541 CPU (h_vbit) = opval; 8542 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 8543 } 8544{ 8545 { 8546 BI opval = 0; 8547 CPU (h_xbit) = opval; 8548 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8549 } 8550 { 8551 BI opval = 0; 8552 SET_H_INSN_PREFIXED_P (opval); 8553 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8554 } 8555} 8556} 8557} 8558} 8559 8560 abuf->written = written; 8561#undef FLD 8562} 8563 NEXT (vpc); 8564 8565 CASE (sem, INSN_ADDC_C) : /* addc ${const32},${Rd} */ 8566{ 8567 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8568 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8569#define FLD(f) abuf->fields.sfmt_addcdr.f 8570 int UNUSED written = 0; 8571 IADDR UNUSED pc = abuf->addr; 8572 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 8573 8574{ 8575CPU (h_xbit) = 1; 8576{ 8577 SI tmp_tmpopd; 8578 SI tmp_tmpops; 8579 BI tmp_carry; 8580 SI tmp_newval; 8581 tmp_tmpops = FLD (f_indir_pc__dword); 8582 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 8583 tmp_carry = CPU (h_cbit); 8584 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 8585 { 8586 SI opval = tmp_newval; 8587 SET_H_GR (FLD (f_operand2), opval); 8588 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8589 } 8590{ 8591 { 8592 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 8593 CPU (h_cbit) = opval; 8594 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 8595 } 8596 { 8597 BI opval = LTSI (tmp_newval, 0); 8598 CPU (h_nbit) = opval; 8599 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 8600 } 8601 { 8602 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 8603 CPU (h_zbit) = opval; 8604 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 8605 } 8606 { 8607 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 8608 CPU (h_vbit) = opval; 8609 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 8610 } 8611{ 8612 { 8613 BI opval = 0; 8614 CPU (h_xbit) = opval; 8615 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8616 } 8617 { 8618 BI opval = 0; 8619 SET_H_INSN_PREFIXED_P (opval); 8620 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8621 } 8622} 8623} 8624} 8625} 8626 8627#undef FLD 8628} 8629 NEXT (vpc); 8630 8631 CASE (sem, INSN_LAPC_D) : /* lapc.d ${const32-pcrel},${Rd} */ 8632{ 8633 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8634 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8635#define FLD(f) abuf->fields.sfmt_lapc_d.f 8636 int UNUSED written = 0; 8637 IADDR UNUSED pc = abuf->addr; 8638 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 8639 8640{ 8641 { 8642 SI opval = FLD (i_const32_pcrel); 8643 SET_H_GR (FLD (f_operand2), opval); 8644 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8645 } 8646{ 8647 { 8648 BI opval = 0; 8649 CPU (h_xbit) = opval; 8650 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8651 } 8652 { 8653 BI opval = 0; 8654 SET_H_INSN_PREFIXED_P (opval); 8655 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8656 } 8657} 8658} 8659 8660#undef FLD 8661} 8662 NEXT (vpc); 8663 8664 CASE (sem, INSN_LAPCQ) : /* lapcq ${qo},${Rd} */ 8665{ 8666 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8667 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8668#define FLD(f) abuf->fields.sfmt_lapcq.f 8669 int UNUSED written = 0; 8670 IADDR UNUSED pc = abuf->addr; 8671 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 8672 8673{ 8674 { 8675 SI opval = FLD (i_qo); 8676 SET_H_GR (FLD (f_operand2), opval); 8677 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8678 } 8679{ 8680 { 8681 BI opval = 0; 8682 CPU (h_xbit) = opval; 8683 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8684 } 8685 { 8686 BI opval = 0; 8687 SET_H_INSN_PREFIXED_P (opval); 8688 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8689 } 8690} 8691} 8692 8693#undef FLD 8694} 8695 NEXT (vpc); 8696 8697 CASE (sem, INSN_ADDI_B_R) : /* addi.b ${Rs-dfield}.m,${Rd-sfield} */ 8698{ 8699 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8700 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8701#define FLD(f) abuf->fields.sfmt_addc_m.f 8702 int UNUSED written = 0; 8703 IADDR UNUSED pc = abuf->addr; 8704 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 8705 8706{ 8707 { 8708 SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1)); 8709 SET_H_GR (FLD (f_operand1), opval); 8710 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8711 } 8712{ 8713 { 8714 BI opval = 0; 8715 CPU (h_xbit) = opval; 8716 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8717 } 8718 { 8719 BI opval = 0; 8720 SET_H_INSN_PREFIXED_P (opval); 8721 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8722 } 8723} 8724} 8725 8726#undef FLD 8727} 8728 NEXT (vpc); 8729 8730 CASE (sem, INSN_ADDI_W_R) : /* addi.w ${Rs-dfield}.m,${Rd-sfield} */ 8731{ 8732 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8733 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8734#define FLD(f) abuf->fields.sfmt_addc_m.f 8735 int UNUSED written = 0; 8736 IADDR UNUSED pc = abuf->addr; 8737 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 8738 8739{ 8740 { 8741 SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2)); 8742 SET_H_GR (FLD (f_operand1), opval); 8743 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8744 } 8745{ 8746 { 8747 BI opval = 0; 8748 CPU (h_xbit) = opval; 8749 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8750 } 8751 { 8752 BI opval = 0; 8753 SET_H_INSN_PREFIXED_P (opval); 8754 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8755 } 8756} 8757} 8758 8759#undef FLD 8760} 8761 NEXT (vpc); 8762 8763 CASE (sem, INSN_ADDI_D_R) : /* addi.d ${Rs-dfield}.m,${Rd-sfield} */ 8764{ 8765 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8766 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8767#define FLD(f) abuf->fields.sfmt_addc_m.f 8768 int UNUSED written = 0; 8769 IADDR UNUSED pc = abuf->addr; 8770 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 8771 8772{ 8773 { 8774 SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4)); 8775 SET_H_GR (FLD (f_operand1), opval); 8776 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8777 } 8778{ 8779 { 8780 BI opval = 0; 8781 CPU (h_xbit) = opval; 8782 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8783 } 8784 { 8785 BI opval = 0; 8786 SET_H_INSN_PREFIXED_P (opval); 8787 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8788 } 8789} 8790} 8791 8792#undef FLD 8793} 8794 NEXT (vpc); 8795 8796 CASE (sem, INSN_NEG_B_R) : /* neg.b $Rs,$Rd */ 8797{ 8798 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8799 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8800#define FLD(f) abuf->fields.sfmt_addc_m.f 8801 int UNUSED written = 0; 8802 IADDR UNUSED pc = abuf->addr; 8803 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 8804 8805{ 8806 QI tmp_tmpopd; 8807 QI tmp_tmpops; 8808 BI tmp_carry; 8809 QI tmp_newval; 8810 tmp_tmpops = GET_H_GR (FLD (f_operand1)); 8811 tmp_tmpopd = 0; 8812 tmp_carry = CPU (h_cbit); 8813 tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 8814{ 8815 SI tmp_oldregval; 8816 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 8817 { 8818 SI opval = ORSI (ANDSI (tmp_newval, 255), ANDSI (tmp_oldregval, 0xffffff00)); 8819 SET_H_GR (FLD (f_operand2), opval); 8820 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8821 } 8822} 8823{ 8824 { 8825 BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0)))); 8826 CPU (h_cbit) = opval; 8827 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 8828 } 8829 { 8830 BI opval = LTQI (tmp_newval, 0); 8831 CPU (h_nbit) = opval; 8832 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 8833 } 8834 { 8835 BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 8836 CPU (h_zbit) = opval; 8837 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 8838 } 8839 { 8840 BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0))); 8841 CPU (h_vbit) = opval; 8842 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 8843 } 8844{ 8845 { 8846 BI opval = 0; 8847 CPU (h_xbit) = opval; 8848 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8849 } 8850 { 8851 BI opval = 0; 8852 SET_H_INSN_PREFIXED_P (opval); 8853 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8854 } 8855} 8856} 8857} 8858 8859#undef FLD 8860} 8861 NEXT (vpc); 8862 8863 CASE (sem, INSN_NEG_W_R) : /* neg.w $Rs,$Rd */ 8864{ 8865 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8866 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8867#define FLD(f) abuf->fields.sfmt_addc_m.f 8868 int UNUSED written = 0; 8869 IADDR UNUSED pc = abuf->addr; 8870 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 8871 8872{ 8873 HI tmp_tmpopd; 8874 HI tmp_tmpops; 8875 BI tmp_carry; 8876 HI tmp_newval; 8877 tmp_tmpops = GET_H_GR (FLD (f_operand1)); 8878 tmp_tmpopd = 0; 8879 tmp_carry = CPU (h_cbit); 8880 tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 8881{ 8882 SI tmp_oldregval; 8883 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 8884 { 8885 SI opval = ORSI (ANDSI (tmp_newval, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 8886 SET_H_GR (FLD (f_operand2), opval); 8887 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8888 } 8889} 8890{ 8891 { 8892 BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0)))); 8893 CPU (h_cbit) = opval; 8894 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 8895 } 8896 { 8897 BI opval = LTHI (tmp_newval, 0); 8898 CPU (h_nbit) = opval; 8899 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 8900 } 8901 { 8902 BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 8903 CPU (h_zbit) = opval; 8904 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 8905 } 8906 { 8907 BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0))); 8908 CPU (h_vbit) = opval; 8909 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 8910 } 8911{ 8912 { 8913 BI opval = 0; 8914 CPU (h_xbit) = opval; 8915 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8916 } 8917 { 8918 BI opval = 0; 8919 SET_H_INSN_PREFIXED_P (opval); 8920 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8921 } 8922} 8923} 8924} 8925 8926#undef FLD 8927} 8928 NEXT (vpc); 8929 8930 CASE (sem, INSN_NEG_D_R) : /* neg.d $Rs,$Rd */ 8931{ 8932 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8933 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8934#define FLD(f) abuf->fields.sfmt_addc_m.f 8935 int UNUSED written = 0; 8936 IADDR UNUSED pc = abuf->addr; 8937 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 8938 8939{ 8940 SI tmp_tmpopd; 8941 SI tmp_tmpops; 8942 BI tmp_carry; 8943 SI tmp_newval; 8944 tmp_tmpops = GET_H_GR (FLD (f_operand1)); 8945 tmp_tmpopd = 0; 8946 tmp_carry = CPU (h_cbit); 8947 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 8948 { 8949 SI opval = tmp_newval; 8950 SET_H_GR (FLD (f_operand2), opval); 8951 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 8952 } 8953{ 8954 { 8955 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 8956 CPU (h_cbit) = opval; 8957 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 8958 } 8959 { 8960 BI opval = LTSI (tmp_newval, 0); 8961 CPU (h_nbit) = opval; 8962 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 8963 } 8964 { 8965 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 8966 CPU (h_zbit) = opval; 8967 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 8968 } 8969 { 8970 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 8971 CPU (h_vbit) = opval; 8972 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 8973 } 8974{ 8975 { 8976 BI opval = 0; 8977 CPU (h_xbit) = opval; 8978 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 8979 } 8980 { 8981 BI opval = 0; 8982 SET_H_INSN_PREFIXED_P (opval); 8983 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 8984 } 8985} 8986} 8987} 8988 8989#undef FLD 8990} 8991 NEXT (vpc); 8992 8993 CASE (sem, INSN_TEST_M_B_M) : /* test-m.b [${Rs}${inc}] */ 8994{ 8995 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 8996 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 8997#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f 8998 int UNUSED written = 0; 8999 IADDR UNUSED pc = abuf->addr; 9000 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9001 9002{ 9003 QI tmp_tmpd; 9004 tmp_tmpd = ({ SI tmp_addr; 9005 QI tmp_tmp_mem; 9006 BI tmp_postinc; 9007 tmp_postinc = FLD (f_memmode); 9008; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 9009; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 9010; if (NEBI (tmp_postinc, 0)) { 9011{ 9012if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 9013 tmp_addr = ADDSI (tmp_addr, 1); 9014} 9015 { 9016 SI opval = tmp_addr; 9017 SET_H_GR (FLD (f_operand1), opval); 9018 written |= (1 << 8); 9019 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9020 } 9021} 9022} 9023; tmp_tmp_mem; }); 9024{ 9025 QI tmp_tmpopd; 9026 QI tmp_tmpops; 9027 BI tmp_carry; 9028 QI tmp_newval; 9029 tmp_tmpops = 0; 9030 tmp_tmpopd = tmp_tmpd; 9031 tmp_carry = CPU (h_cbit); 9032 tmp_newval = SUBCQI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 9033((void) 0); /*nop*/ 9034{ 9035 { 9036 BI opval = ORIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), ORIF (ANDIF (GEQI (tmp_tmpopd, 0), LTQI (tmp_newval, 0)), ANDIF (LTQI (tmp_tmpops, 0), LTQI (tmp_newval, 0)))); 9037 CPU (h_cbit) = opval; 9038 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9039 } 9040 { 9041 BI opval = LTQI (tmp_newval, 0); 9042 CPU (h_nbit) = opval; 9043 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 9044 } 9045 { 9046 BI opval = ANDIF (EQQI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 9047 CPU (h_zbit) = opval; 9048 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 9049 } 9050 { 9051 BI opval = ORIF (ANDIF (ANDIF (GEQI (tmp_tmpops, 0), LTQI (tmp_tmpopd, 0)), GEQI (tmp_newval, 0)), ANDIF (ANDIF (LTQI (tmp_tmpops, 0), GEQI (tmp_tmpopd, 0)), LTQI (tmp_newval, 0))); 9052 CPU (h_vbit) = opval; 9053 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 9054 } 9055{ 9056 { 9057 BI opval = 0; 9058 CPU (h_xbit) = opval; 9059 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9060 } 9061 { 9062 BI opval = 0; 9063 SET_H_INSN_PREFIXED_P (opval); 9064 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9065 } 9066} 9067} 9068} 9069} 9070 9071 abuf->written = written; 9072#undef FLD 9073} 9074 NEXT (vpc); 9075 9076 CASE (sem, INSN_TEST_M_W_M) : /* test-m.w [${Rs}${inc}] */ 9077{ 9078 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 9079 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 9080#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f 9081 int UNUSED written = 0; 9082 IADDR UNUSED pc = abuf->addr; 9083 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9084 9085{ 9086 HI tmp_tmpd; 9087 tmp_tmpd = ({ SI tmp_addr; 9088 HI tmp_tmp_mem; 9089 BI tmp_postinc; 9090 tmp_postinc = FLD (f_memmode); 9091; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 9092; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 9093; if (NEBI (tmp_postinc, 0)) { 9094{ 9095if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 9096 tmp_addr = ADDSI (tmp_addr, 2); 9097} 9098 { 9099 SI opval = tmp_addr; 9100 SET_H_GR (FLD (f_operand1), opval); 9101 written |= (1 << 8); 9102 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9103 } 9104} 9105} 9106; tmp_tmp_mem; }); 9107{ 9108 HI tmp_tmpopd; 9109 HI tmp_tmpops; 9110 BI tmp_carry; 9111 HI tmp_newval; 9112 tmp_tmpops = 0; 9113 tmp_tmpopd = tmp_tmpd; 9114 tmp_carry = CPU (h_cbit); 9115 tmp_newval = SUBCHI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 9116((void) 0); /*nop*/ 9117{ 9118 { 9119 BI opval = ORIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), ORIF (ANDIF (GEHI (tmp_tmpopd, 0), LTHI (tmp_newval, 0)), ANDIF (LTHI (tmp_tmpops, 0), LTHI (tmp_newval, 0)))); 9120 CPU (h_cbit) = opval; 9121 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9122 } 9123 { 9124 BI opval = LTHI (tmp_newval, 0); 9125 CPU (h_nbit) = opval; 9126 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 9127 } 9128 { 9129 BI opval = ANDIF (EQHI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 9130 CPU (h_zbit) = opval; 9131 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 9132 } 9133 { 9134 BI opval = ORIF (ANDIF (ANDIF (GEHI (tmp_tmpops, 0), LTHI (tmp_tmpopd, 0)), GEHI (tmp_newval, 0)), ANDIF (ANDIF (LTHI (tmp_tmpops, 0), GEHI (tmp_tmpopd, 0)), LTHI (tmp_newval, 0))); 9135 CPU (h_vbit) = opval; 9136 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 9137 } 9138{ 9139 { 9140 BI opval = 0; 9141 CPU (h_xbit) = opval; 9142 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9143 } 9144 { 9145 BI opval = 0; 9146 SET_H_INSN_PREFIXED_P (opval); 9147 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9148 } 9149} 9150} 9151} 9152} 9153 9154 abuf->written = written; 9155#undef FLD 9156} 9157 NEXT (vpc); 9158 9159 CASE (sem, INSN_TEST_M_D_M) : /* test-m.d [${Rs}${inc}] */ 9160{ 9161 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 9162 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 9163#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f 9164 int UNUSED written = 0; 9165 IADDR UNUSED pc = abuf->addr; 9166 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9167 9168{ 9169 SI tmp_tmpd; 9170 tmp_tmpd = ({ SI tmp_addr; 9171 SI tmp_tmp_mem; 9172 BI tmp_postinc; 9173 tmp_postinc = FLD (f_memmode); 9174; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 9175; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 9176; if (NEBI (tmp_postinc, 0)) { 9177{ 9178if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 9179 tmp_addr = ADDSI (tmp_addr, 4); 9180} 9181 { 9182 SI opval = tmp_addr; 9183 SET_H_GR (FLD (f_operand1), opval); 9184 written |= (1 << 8); 9185 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9186 } 9187} 9188} 9189; tmp_tmp_mem; }); 9190{ 9191 SI tmp_tmpopd; 9192 SI tmp_tmpops; 9193 BI tmp_carry; 9194 SI tmp_newval; 9195 tmp_tmpops = 0; 9196 tmp_tmpopd = tmp_tmpd; 9197 tmp_carry = CPU (h_cbit); 9198 tmp_newval = SUBCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 9199((void) 0); /*nop*/ 9200{ 9201 { 9202 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), ORIF (ANDIF (GESI (tmp_tmpopd, 0), LTSI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_newval, 0)))); 9203 CPU (h_cbit) = opval; 9204 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9205 } 9206 { 9207 BI opval = LTSI (tmp_newval, 0); 9208 CPU (h_nbit) = opval; 9209 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 9210 } 9211 { 9212 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 9213 CPU (h_zbit) = opval; 9214 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 9215 } 9216 { 9217 BI opval = ORIF (ANDIF (ANDIF (GESI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 9218 CPU (h_vbit) = opval; 9219 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 9220 } 9221{ 9222 { 9223 BI opval = 0; 9224 CPU (h_xbit) = opval; 9225 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9226 } 9227 { 9228 BI opval = 0; 9229 SET_H_INSN_PREFIXED_P (opval); 9230 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9231 } 9232} 9233} 9234} 9235} 9236 9237 abuf->written = written; 9238#undef FLD 9239} 9240 NEXT (vpc); 9241 9242 CASE (sem, INSN_MOVE_R_M_B_M) : /* move-r-m.b ${Rs-dfield},[${Rd-sfield}${inc}] */ 9243{ 9244 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 9245 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 9246#define FLD(f) abuf->fields.sfmt_addc_m.f 9247 int UNUSED written = 0; 9248 IADDR UNUSED pc = abuf->addr; 9249 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9250 9251{ 9252 QI tmp_tmpd; 9253 tmp_tmpd = GET_H_GR (FLD (f_operand2)); 9254{ 9255 SI tmp_addr; 9256 BI tmp_postinc; 9257 tmp_postinc = FLD (f_memmode); 9258 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 9259if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 9260if (EQBI (CPU (h_pbit), 0)) { 9261{ 9262 { 9263 QI opval = tmp_tmpd; 9264 SETMEMQI (current_cpu, pc, tmp_addr, opval); 9265 written |= (1 << 10); 9266 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 9267 } 9268 { 9269 BI opval = CPU (h_pbit); 9270 CPU (h_cbit) = opval; 9271 written |= (1 << 9); 9272 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9273 } 9274} 9275} else { 9276 { 9277 BI opval = 1; 9278 CPU (h_cbit) = opval; 9279 written |= (1 << 9); 9280 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9281 } 9282} 9283} else { 9284 { 9285 QI opval = tmp_tmpd; 9286 SETMEMQI (current_cpu, pc, tmp_addr, opval); 9287 written |= (1 << 10); 9288 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 9289 } 9290} 9291if (NEBI (tmp_postinc, 0)) { 9292{ 9293if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 9294 tmp_addr = ADDSI (tmp_addr, 1); 9295} 9296 { 9297 SI opval = tmp_addr; 9298 SET_H_GR (FLD (f_operand1), opval); 9299 written |= (1 << 8); 9300 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9301 } 9302} 9303} 9304} 9305{ 9306 { 9307 BI opval = 0; 9308 CPU (h_xbit) = opval; 9309 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9310 } 9311 { 9312 BI opval = 0; 9313 SET_H_INSN_PREFIXED_P (opval); 9314 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9315 } 9316} 9317} 9318 9319 abuf->written = written; 9320#undef FLD 9321} 9322 NEXT (vpc); 9323 9324 CASE (sem, INSN_MOVE_R_M_W_M) : /* move-r-m.w ${Rs-dfield},[${Rd-sfield}${inc}] */ 9325{ 9326 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 9327 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 9328#define FLD(f) abuf->fields.sfmt_addc_m.f 9329 int UNUSED written = 0; 9330 IADDR UNUSED pc = abuf->addr; 9331 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9332 9333{ 9334 HI tmp_tmpd; 9335 tmp_tmpd = GET_H_GR (FLD (f_operand2)); 9336{ 9337 SI tmp_addr; 9338 BI tmp_postinc; 9339 tmp_postinc = FLD (f_memmode); 9340 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 9341if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 9342if (EQBI (CPU (h_pbit), 0)) { 9343{ 9344 { 9345 HI opval = tmp_tmpd; 9346 SETMEMHI (current_cpu, pc, tmp_addr, opval); 9347 written |= (1 << 10); 9348 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 9349 } 9350 { 9351 BI opval = CPU (h_pbit); 9352 CPU (h_cbit) = opval; 9353 written |= (1 << 9); 9354 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9355 } 9356} 9357} else { 9358 { 9359 BI opval = 1; 9360 CPU (h_cbit) = opval; 9361 written |= (1 << 9); 9362 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9363 } 9364} 9365} else { 9366 { 9367 HI opval = tmp_tmpd; 9368 SETMEMHI (current_cpu, pc, tmp_addr, opval); 9369 written |= (1 << 10); 9370 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 9371 } 9372} 9373if (NEBI (tmp_postinc, 0)) { 9374{ 9375if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 9376 tmp_addr = ADDSI (tmp_addr, 2); 9377} 9378 { 9379 SI opval = tmp_addr; 9380 SET_H_GR (FLD (f_operand1), opval); 9381 written |= (1 << 8); 9382 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9383 } 9384} 9385} 9386} 9387{ 9388 { 9389 BI opval = 0; 9390 CPU (h_xbit) = opval; 9391 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9392 } 9393 { 9394 BI opval = 0; 9395 SET_H_INSN_PREFIXED_P (opval); 9396 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9397 } 9398} 9399} 9400 9401 abuf->written = written; 9402#undef FLD 9403} 9404 NEXT (vpc); 9405 9406 CASE (sem, INSN_MOVE_R_M_D_M) : /* move-r-m.d ${Rs-dfield},[${Rd-sfield}${inc}] */ 9407{ 9408 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 9409 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 9410#define FLD(f) abuf->fields.sfmt_addc_m.f 9411 int UNUSED written = 0; 9412 IADDR UNUSED pc = abuf->addr; 9413 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9414 9415{ 9416 SI tmp_tmpd; 9417 tmp_tmpd = GET_H_GR (FLD (f_operand2)); 9418{ 9419 SI tmp_addr; 9420 BI tmp_postinc; 9421 tmp_postinc = FLD (f_memmode); 9422 tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 9423if (ANDIF (GET_H_V32_V32 (), NEBI (CPU (h_xbit), 0))) { 9424if (EQBI (CPU (h_pbit), 0)) { 9425{ 9426 { 9427 SI opval = tmp_tmpd; 9428 SETMEMSI (current_cpu, pc, tmp_addr, opval); 9429 written |= (1 << 10); 9430 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 9431 } 9432 { 9433 BI opval = CPU (h_pbit); 9434 CPU (h_cbit) = opval; 9435 written |= (1 << 9); 9436 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9437 } 9438} 9439} else { 9440 { 9441 BI opval = 1; 9442 CPU (h_cbit) = opval; 9443 written |= (1 << 9); 9444 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9445 } 9446} 9447} else { 9448 { 9449 SI opval = tmp_tmpd; 9450 SETMEMSI (current_cpu, pc, tmp_addr, opval); 9451 written |= (1 << 10); 9452 TRACE_RESULT (current_cpu, abuf, "memory", 'x', opval); 9453 } 9454} 9455if (NEBI (tmp_postinc, 0)) { 9456{ 9457if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 9458 tmp_addr = ADDSI (tmp_addr, 4); 9459} 9460 { 9461 SI opval = tmp_addr; 9462 SET_H_GR (FLD (f_operand1), opval); 9463 written |= (1 << 8); 9464 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9465 } 9466} 9467} 9468} 9469{ 9470 { 9471 BI opval = 0; 9472 CPU (h_xbit) = opval; 9473 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9474 } 9475 { 9476 BI opval = 0; 9477 SET_H_INSN_PREFIXED_P (opval); 9478 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9479 } 9480} 9481} 9482 9483 abuf->written = written; 9484#undef FLD 9485} 9486 NEXT (vpc); 9487 9488 CASE (sem, INSN_MULS_B) : /* muls.b $Rs,$Rd */ 9489{ 9490 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 9491 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 9492#define FLD(f) abuf->fields.sfmt_muls_b.f 9493 int UNUSED written = 0; 9494 IADDR UNUSED pc = abuf->addr; 9495 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9496 9497{ 9498 DI tmp_src1; 9499 DI tmp_src2; 9500 DI tmp_tmpr; 9501 tmp_src1 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1)))); 9502 tmp_src2 = EXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))); 9503 tmp_tmpr = MULDI (tmp_src1, tmp_src2); 9504 { 9505 SI opval = TRUNCDISI (tmp_tmpr); 9506 SET_H_GR (FLD (f_operand2), opval); 9507 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9508 } 9509 { 9510 SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32)); 9511 SET_H_SR (((UINT) 7), opval); 9512 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 9513 } 9514{ 9515 { 9516 BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit)); 9517 CPU (h_cbit) = opval; 9518 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9519 } 9520 { 9521 BI opval = LTDI (tmp_tmpr, 0); 9522 CPU (h_nbit) = opval; 9523 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 9524 } 9525 { 9526 BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 9527 CPU (h_zbit) = opval; 9528 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 9529 } 9530 { 9531 BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr))); 9532 CPU (h_vbit) = opval; 9533 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 9534 } 9535{ 9536 { 9537 BI opval = 0; 9538 CPU (h_xbit) = opval; 9539 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9540 } 9541 { 9542 BI opval = 0; 9543 SET_H_INSN_PREFIXED_P (opval); 9544 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9545 } 9546} 9547} 9548} 9549 9550#undef FLD 9551} 9552 NEXT (vpc); 9553 9554 CASE (sem, INSN_MULS_W) : /* muls.w $Rs,$Rd */ 9555{ 9556 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 9557 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 9558#define FLD(f) abuf->fields.sfmt_muls_b.f 9559 int UNUSED written = 0; 9560 IADDR UNUSED pc = abuf->addr; 9561 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9562 9563{ 9564 DI tmp_src1; 9565 DI tmp_src2; 9566 DI tmp_tmpr; 9567 tmp_src1 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1)))); 9568 tmp_src2 = EXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))); 9569 tmp_tmpr = MULDI (tmp_src1, tmp_src2); 9570 { 9571 SI opval = TRUNCDISI (tmp_tmpr); 9572 SET_H_GR (FLD (f_operand2), opval); 9573 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9574 } 9575 { 9576 SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32)); 9577 SET_H_SR (((UINT) 7), opval); 9578 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 9579 } 9580{ 9581 { 9582 BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit)); 9583 CPU (h_cbit) = opval; 9584 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9585 } 9586 { 9587 BI opval = LTDI (tmp_tmpr, 0); 9588 CPU (h_nbit) = opval; 9589 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 9590 } 9591 { 9592 BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 9593 CPU (h_zbit) = opval; 9594 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 9595 } 9596 { 9597 BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr))); 9598 CPU (h_vbit) = opval; 9599 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 9600 } 9601{ 9602 { 9603 BI opval = 0; 9604 CPU (h_xbit) = opval; 9605 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9606 } 9607 { 9608 BI opval = 0; 9609 SET_H_INSN_PREFIXED_P (opval); 9610 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9611 } 9612} 9613} 9614} 9615 9616#undef FLD 9617} 9618 NEXT (vpc); 9619 9620 CASE (sem, INSN_MULS_D) : /* muls.d $Rs,$Rd */ 9621{ 9622 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 9623 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 9624#define FLD(f) abuf->fields.sfmt_muls_b.f 9625 int UNUSED written = 0; 9626 IADDR UNUSED pc = abuf->addr; 9627 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9628 9629{ 9630 DI tmp_src1; 9631 DI tmp_src2; 9632 DI tmp_tmpr; 9633 tmp_src1 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1)))); 9634 tmp_src2 = EXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))); 9635 tmp_tmpr = MULDI (tmp_src1, tmp_src2); 9636 { 9637 SI opval = TRUNCDISI (tmp_tmpr); 9638 SET_H_GR (FLD (f_operand2), opval); 9639 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9640 } 9641 { 9642 SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32)); 9643 SET_H_SR (((UINT) 7), opval); 9644 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 9645 } 9646{ 9647 { 9648 BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit)); 9649 CPU (h_cbit) = opval; 9650 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9651 } 9652 { 9653 BI opval = LTDI (tmp_tmpr, 0); 9654 CPU (h_nbit) = opval; 9655 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 9656 } 9657 { 9658 BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 9659 CPU (h_zbit) = opval; 9660 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 9661 } 9662 { 9663 BI opval = NEDI (tmp_tmpr, EXTSIDI (TRUNCDISI (tmp_tmpr))); 9664 CPU (h_vbit) = opval; 9665 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 9666 } 9667{ 9668 { 9669 BI opval = 0; 9670 CPU (h_xbit) = opval; 9671 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9672 } 9673 { 9674 BI opval = 0; 9675 SET_H_INSN_PREFIXED_P (opval); 9676 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9677 } 9678} 9679} 9680} 9681 9682#undef FLD 9683} 9684 NEXT (vpc); 9685 9686 CASE (sem, INSN_MULU_B) : /* mulu.b $Rs,$Rd */ 9687{ 9688 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 9689 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 9690#define FLD(f) abuf->fields.sfmt_muls_b.f 9691 int UNUSED written = 0; 9692 IADDR UNUSED pc = abuf->addr; 9693 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9694 9695{ 9696 DI tmp_src1; 9697 DI tmp_src2; 9698 DI tmp_tmpr; 9699 tmp_src1 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand1)))); 9700 tmp_src2 = ZEXTQIDI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))); 9701 tmp_tmpr = MULDI (tmp_src1, tmp_src2); 9702 { 9703 SI opval = TRUNCDISI (tmp_tmpr); 9704 SET_H_GR (FLD (f_operand2), opval); 9705 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9706 } 9707 { 9708 SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32)); 9709 SET_H_SR (((UINT) 7), opval); 9710 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 9711 } 9712{ 9713 { 9714 BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit)); 9715 CPU (h_cbit) = opval; 9716 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9717 } 9718 { 9719 BI opval = LTDI (tmp_tmpr, 0); 9720 CPU (h_nbit) = opval; 9721 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 9722 } 9723 { 9724 BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 9725 CPU (h_zbit) = opval; 9726 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 9727 } 9728 { 9729 BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr))); 9730 CPU (h_vbit) = opval; 9731 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 9732 } 9733{ 9734 { 9735 BI opval = 0; 9736 CPU (h_xbit) = opval; 9737 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9738 } 9739 { 9740 BI opval = 0; 9741 SET_H_INSN_PREFIXED_P (opval); 9742 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9743 } 9744} 9745} 9746} 9747 9748#undef FLD 9749} 9750 NEXT (vpc); 9751 9752 CASE (sem, INSN_MULU_W) : /* mulu.w $Rs,$Rd */ 9753{ 9754 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 9755 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 9756#define FLD(f) abuf->fields.sfmt_muls_b.f 9757 int UNUSED written = 0; 9758 IADDR UNUSED pc = abuf->addr; 9759 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9760 9761{ 9762 DI tmp_src1; 9763 DI tmp_src2; 9764 DI tmp_tmpr; 9765 tmp_src1 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand1)))); 9766 tmp_src2 = ZEXTHIDI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))); 9767 tmp_tmpr = MULDI (tmp_src1, tmp_src2); 9768 { 9769 SI opval = TRUNCDISI (tmp_tmpr); 9770 SET_H_GR (FLD (f_operand2), opval); 9771 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9772 } 9773 { 9774 SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32)); 9775 SET_H_SR (((UINT) 7), opval); 9776 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 9777 } 9778{ 9779 { 9780 BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit)); 9781 CPU (h_cbit) = opval; 9782 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9783 } 9784 { 9785 BI opval = LTDI (tmp_tmpr, 0); 9786 CPU (h_nbit) = opval; 9787 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 9788 } 9789 { 9790 BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 9791 CPU (h_zbit) = opval; 9792 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 9793 } 9794 { 9795 BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr))); 9796 CPU (h_vbit) = opval; 9797 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 9798 } 9799{ 9800 { 9801 BI opval = 0; 9802 CPU (h_xbit) = opval; 9803 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9804 } 9805 { 9806 BI opval = 0; 9807 SET_H_INSN_PREFIXED_P (opval); 9808 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9809 } 9810} 9811} 9812} 9813 9814#undef FLD 9815} 9816 NEXT (vpc); 9817 9818 CASE (sem, INSN_MULU_D) : /* mulu.d $Rs,$Rd */ 9819{ 9820 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 9821 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 9822#define FLD(f) abuf->fields.sfmt_muls_b.f 9823 int UNUSED written = 0; 9824 IADDR UNUSED pc = abuf->addr; 9825 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9826 9827{ 9828 DI tmp_src1; 9829 DI tmp_src2; 9830 DI tmp_tmpr; 9831 tmp_src1 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand1)))); 9832 tmp_src2 = ZEXTSIDI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))); 9833 tmp_tmpr = MULDI (tmp_src1, tmp_src2); 9834 { 9835 SI opval = TRUNCDISI (tmp_tmpr); 9836 SET_H_GR (FLD (f_operand2), opval); 9837 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9838 } 9839 { 9840 SI opval = TRUNCDISI (SRLDI (tmp_tmpr, 32)); 9841 SET_H_SR (((UINT) 7), opval); 9842 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 9843 } 9844{ 9845 { 9846 BI opval = ANDIF (GET_H_V32_V32 (), CPU (h_cbit)); 9847 CPU (h_cbit) = opval; 9848 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 9849 } 9850 { 9851 BI opval = LTDI (tmp_tmpr, 0); 9852 CPU (h_nbit) = opval; 9853 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 9854 } 9855 { 9856 BI opval = ANDIF (EQDI (tmp_tmpr, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 9857 CPU (h_zbit) = opval; 9858 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 9859 } 9860 { 9861 BI opval = NEDI (tmp_tmpr, ZEXTSIDI (TRUNCDISI (tmp_tmpr))); 9862 CPU (h_vbit) = opval; 9863 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 9864 } 9865{ 9866 { 9867 BI opval = 0; 9868 CPU (h_xbit) = opval; 9869 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9870 } 9871 { 9872 BI opval = 0; 9873 SET_H_INSN_PREFIXED_P (opval); 9874 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9875 } 9876} 9877} 9878} 9879 9880#undef FLD 9881} 9882 NEXT (vpc); 9883 9884 CASE (sem, INSN_MCP) : /* mcp $Ps,$Rd */ 9885{ 9886 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 9887 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 9888#define FLD(f) abuf->fields.sfmt_mcp.f 9889 int UNUSED written = 0; 9890 IADDR UNUSED pc = abuf->addr; 9891 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9892 9893{ 9894CPU (h_xbit) = 1; 9895CPU (h_zbit) = 1; 9896{ 9897 SI tmp_tmpopd; 9898 SI tmp_tmpops; 9899 BI tmp_carry; 9900 SI tmp_newval; 9901 tmp_tmpops = GET_H_SR (FLD (f_operand2)); 9902 tmp_tmpopd = GET_H_GR (FLD (f_operand1)); 9903 tmp_carry = CPU (h_rbit); 9904 tmp_newval = ADDCSI (tmp_tmpopd, tmp_tmpops, ((EQBI (CPU (h_xbit), 0)) ? (0) : (tmp_carry))); 9905 { 9906 SI opval = tmp_newval; 9907 SET_H_GR (FLD (f_operand1), opval); 9908 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9909 } 9910{ 9911 { 9912 BI opval = ORIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), ORIF (ANDIF (LTSI (tmp_tmpopd, 0), GESI (tmp_newval, 0)), ANDIF (LTSI (tmp_tmpops, 0), GESI (tmp_newval, 0)))); 9913 CPU (h_rbit) = opval; 9914 TRACE_RESULT (current_cpu, abuf, "rbit", 'x', opval); 9915 } 9916 { 9917 BI opval = LTSI (tmp_newval, 0); 9918 CPU (h_nbit) = opval; 9919 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 9920 } 9921 { 9922 BI opval = ANDIF (EQSI (tmp_newval, 0), ORIF (CPU (h_zbit), NOTBI (CPU (h_xbit)))); 9923 CPU (h_zbit) = opval; 9924 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 9925 } 9926 { 9927 BI opval = ORIF (ANDIF (ANDIF (LTSI (tmp_tmpops, 0), LTSI (tmp_tmpopd, 0)), GESI (tmp_newval, 0)), ANDIF (ANDIF (GESI (tmp_tmpops, 0), GESI (tmp_tmpopd, 0)), LTSI (tmp_newval, 0))); 9928 CPU (h_vbit) = opval; 9929 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 9930 } 9931{ 9932 { 9933 BI opval = 0; 9934 CPU (h_xbit) = opval; 9935 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9936 } 9937 { 9938 BI opval = 0; 9939 SET_H_INSN_PREFIXED_P (opval); 9940 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9941 } 9942} 9943} 9944} 9945} 9946 9947#undef FLD 9948} 9949 NEXT (vpc); 9950 9951 CASE (sem, INSN_DSTEP) : /* dstep $Rs,$Rd */ 9952{ 9953 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 9954 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 9955#define FLD(f) abuf->fields.sfmt_muls_b.f 9956 int UNUSED written = 0; 9957 IADDR UNUSED pc = abuf->addr; 9958 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 9959 9960{ 9961 SI tmp_tmp; 9962 SI tmp_tmps; 9963 SI tmp_tmpd; 9964 tmp_tmps = GET_H_GR (FLD (f_operand1)); 9965 tmp_tmp = SLLSI (GET_H_GR (FLD (f_operand2)), 1); 9966 tmp_tmpd = ((GEUSI (tmp_tmp, tmp_tmps)) ? (SUBSI (tmp_tmp, tmp_tmps)) : (tmp_tmp)); 9967 { 9968 SI opval = tmp_tmpd; 9969 SET_H_GR (FLD (f_operand2), opval); 9970 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 9971 } 9972{ 9973 { 9974 BI opval = LTSI (tmp_tmpd, 0); 9975 CPU (h_nbit) = opval; 9976 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 9977 } 9978 { 9979 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 9980 CPU (h_zbit) = opval; 9981 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 9982 } 9983SET_H_CBIT_MOVE (0); 9984SET_H_VBIT_MOVE (0); 9985{ 9986 { 9987 BI opval = 0; 9988 CPU (h_xbit) = opval; 9989 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 9990 } 9991 { 9992 BI opval = 0; 9993 SET_H_INSN_PREFIXED_P (opval); 9994 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 9995 } 9996} 9997} 9998} 9999 10000#undef FLD 10001} 10002 NEXT (vpc); 10003 10004 CASE (sem, INSN_ABS) : /* abs $Rs,$Rd */ 10005{ 10006 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10007 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10008#define FLD(f) abuf->fields.sfmt_muls_b.f 10009 int UNUSED written = 0; 10010 IADDR UNUSED pc = abuf->addr; 10011 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10012 10013{ 10014 SI tmp_tmpd; 10015 tmp_tmpd = ABSSI (GET_H_GR (FLD (f_operand1))); 10016 { 10017 SI opval = tmp_tmpd; 10018 SET_H_GR (FLD (f_operand2), opval); 10019 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10020 } 10021{ 10022 { 10023 BI opval = LTSI (tmp_tmpd, 0); 10024 CPU (h_nbit) = opval; 10025 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10026 } 10027 { 10028 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10029 CPU (h_zbit) = opval; 10030 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10031 } 10032SET_H_CBIT_MOVE (0); 10033SET_H_VBIT_MOVE (0); 10034{ 10035 { 10036 BI opval = 0; 10037 CPU (h_xbit) = opval; 10038 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10039 } 10040 { 10041 BI opval = 0; 10042 SET_H_INSN_PREFIXED_P (opval); 10043 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10044 } 10045} 10046} 10047} 10048 10049#undef FLD 10050} 10051 NEXT (vpc); 10052 10053 CASE (sem, INSN_AND_B_R) : /* and.b $Rs,$Rd */ 10054{ 10055 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10056 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10057#define FLD(f) abuf->fields.sfmt_addc_m.f 10058 int UNUSED written = 0; 10059 IADDR UNUSED pc = abuf->addr; 10060 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10061 10062{ 10063 QI tmp_tmpd; 10064 tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1))); 10065{ 10066 SI tmp_oldregval; 10067 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 10068 { 10069 SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00)); 10070 SET_H_GR (FLD (f_operand2), opval); 10071 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10072 } 10073} 10074{ 10075 { 10076 BI opval = LTQI (tmp_tmpd, 0); 10077 CPU (h_nbit) = opval; 10078 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10079 } 10080 { 10081 BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10082 CPU (h_zbit) = opval; 10083 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10084 } 10085SET_H_CBIT_MOVE (0); 10086SET_H_VBIT_MOVE (0); 10087{ 10088 { 10089 BI opval = 0; 10090 CPU (h_xbit) = opval; 10091 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10092 } 10093 { 10094 BI opval = 0; 10095 SET_H_INSN_PREFIXED_P (opval); 10096 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10097 } 10098} 10099} 10100} 10101 10102#undef FLD 10103} 10104 NEXT (vpc); 10105 10106 CASE (sem, INSN_AND_W_R) : /* and.w $Rs,$Rd */ 10107{ 10108 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10109 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10110#define FLD(f) abuf->fields.sfmt_addc_m.f 10111 int UNUSED written = 0; 10112 IADDR UNUSED pc = abuf->addr; 10113 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10114 10115{ 10116 HI tmp_tmpd; 10117 tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1))); 10118{ 10119 SI tmp_oldregval; 10120 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 10121 { 10122 SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 10123 SET_H_GR (FLD (f_operand2), opval); 10124 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10125 } 10126} 10127{ 10128 { 10129 BI opval = LTHI (tmp_tmpd, 0); 10130 CPU (h_nbit) = opval; 10131 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10132 } 10133 { 10134 BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10135 CPU (h_zbit) = opval; 10136 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10137 } 10138SET_H_CBIT_MOVE (0); 10139SET_H_VBIT_MOVE (0); 10140{ 10141 { 10142 BI opval = 0; 10143 CPU (h_xbit) = opval; 10144 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10145 } 10146 { 10147 BI opval = 0; 10148 SET_H_INSN_PREFIXED_P (opval); 10149 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10150 } 10151} 10152} 10153} 10154 10155#undef FLD 10156} 10157 NEXT (vpc); 10158 10159 CASE (sem, INSN_AND_D_R) : /* and.d $Rs,$Rd */ 10160{ 10161 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10162 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10163#define FLD(f) abuf->fields.sfmt_addc_m.f 10164 int UNUSED written = 0; 10165 IADDR UNUSED pc = abuf->addr; 10166 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10167 10168{ 10169 SI tmp_tmpd; 10170 tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1))); 10171 { 10172 SI opval = tmp_tmpd; 10173 SET_H_GR (FLD (f_operand2), opval); 10174 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10175 } 10176{ 10177 { 10178 BI opval = LTSI (tmp_tmpd, 0); 10179 CPU (h_nbit) = opval; 10180 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10181 } 10182 { 10183 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10184 CPU (h_zbit) = opval; 10185 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10186 } 10187SET_H_CBIT_MOVE (0); 10188SET_H_VBIT_MOVE (0); 10189{ 10190 { 10191 BI opval = 0; 10192 CPU (h_xbit) = opval; 10193 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10194 } 10195 { 10196 BI opval = 0; 10197 SET_H_INSN_PREFIXED_P (opval); 10198 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10199 } 10200} 10201} 10202} 10203 10204#undef FLD 10205} 10206 NEXT (vpc); 10207 10208 CASE (sem, INSN_AND_M_B_M) : /* and-m.b [${Rs}${inc}],${Rd} */ 10209{ 10210 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10211 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10212#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 10213 int UNUSED written = 0; 10214 IADDR UNUSED pc = abuf->addr; 10215 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10216 10217{ 10218 QI tmp_tmpd; 10219 tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr; 10220 QI tmp_tmp_mem; 10221 BI tmp_postinc; 10222 tmp_postinc = FLD (f_memmode); 10223; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 10224; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 10225; if (NEBI (tmp_postinc, 0)) { 10226{ 10227if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 10228 tmp_addr = ADDSI (tmp_addr, 1); 10229} 10230 { 10231 SI opval = tmp_addr; 10232 SET_H_GR (FLD (f_operand1), opval); 10233 written |= (1 << 11); 10234 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10235 } 10236} 10237} 10238; tmp_tmp_mem; })); 10239{ 10240 SI tmp_oldregval; 10241 tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2)))); 10242 { 10243 SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00)); 10244 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 10245 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10246 } 10247} 10248{ 10249 { 10250 BI opval = LTQI (tmp_tmpd, 0); 10251 CPU (h_nbit) = opval; 10252 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10253 } 10254 { 10255 BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10256 CPU (h_zbit) = opval; 10257 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10258 } 10259SET_H_CBIT_MOVE (0); 10260SET_H_VBIT_MOVE (0); 10261{ 10262 { 10263 BI opval = 0; 10264 CPU (h_xbit) = opval; 10265 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10266 } 10267 { 10268 BI opval = 0; 10269 SET_H_INSN_PREFIXED_P (opval); 10270 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10271 } 10272} 10273} 10274} 10275 10276 abuf->written = written; 10277#undef FLD 10278} 10279 NEXT (vpc); 10280 10281 CASE (sem, INSN_AND_M_W_M) : /* and-m.w [${Rs}${inc}],${Rd} */ 10282{ 10283 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10284 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10285#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 10286 int UNUSED written = 0; 10287 IADDR UNUSED pc = abuf->addr; 10288 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10289 10290{ 10291 HI tmp_tmpd; 10292 tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr; 10293 HI tmp_tmp_mem; 10294 BI tmp_postinc; 10295 tmp_postinc = FLD (f_memmode); 10296; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 10297; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 10298; if (NEBI (tmp_postinc, 0)) { 10299{ 10300if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 10301 tmp_addr = ADDSI (tmp_addr, 2); 10302} 10303 { 10304 SI opval = tmp_addr; 10305 SET_H_GR (FLD (f_operand1), opval); 10306 written |= (1 << 11); 10307 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10308 } 10309} 10310} 10311; tmp_tmp_mem; })); 10312{ 10313 SI tmp_oldregval; 10314 tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2)))); 10315 { 10316 SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 10317 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 10318 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10319 } 10320} 10321{ 10322 { 10323 BI opval = LTHI (tmp_tmpd, 0); 10324 CPU (h_nbit) = opval; 10325 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10326 } 10327 { 10328 BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10329 CPU (h_zbit) = opval; 10330 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10331 } 10332SET_H_CBIT_MOVE (0); 10333SET_H_VBIT_MOVE (0); 10334{ 10335 { 10336 BI opval = 0; 10337 CPU (h_xbit) = opval; 10338 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10339 } 10340 { 10341 BI opval = 0; 10342 SET_H_INSN_PREFIXED_P (opval); 10343 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10344 } 10345} 10346} 10347} 10348 10349 abuf->written = written; 10350#undef FLD 10351} 10352 NEXT (vpc); 10353 10354 CASE (sem, INSN_AND_M_D_M) : /* and-m.d [${Rs}${inc}],${Rd} */ 10355{ 10356 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10357 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10358#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 10359 int UNUSED written = 0; 10360 IADDR UNUSED pc = abuf->addr; 10361 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10362 10363{ 10364 SI tmp_tmpd; 10365 tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr; 10366 SI tmp_tmp_mem; 10367 BI tmp_postinc; 10368 tmp_postinc = FLD (f_memmode); 10369; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 10370; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 10371; if (NEBI (tmp_postinc, 0)) { 10372{ 10373if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 10374 tmp_addr = ADDSI (tmp_addr, 4); 10375} 10376 { 10377 SI opval = tmp_addr; 10378 SET_H_GR (FLD (f_operand1), opval); 10379 written |= (1 << 10); 10380 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10381 } 10382} 10383} 10384; tmp_tmp_mem; })); 10385 { 10386 SI opval = tmp_tmpd; 10387 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 10388 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10389 } 10390{ 10391 { 10392 BI opval = LTSI (tmp_tmpd, 0); 10393 CPU (h_nbit) = opval; 10394 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10395 } 10396 { 10397 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10398 CPU (h_zbit) = opval; 10399 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10400 } 10401SET_H_CBIT_MOVE (0); 10402SET_H_VBIT_MOVE (0); 10403{ 10404 { 10405 BI opval = 0; 10406 CPU (h_xbit) = opval; 10407 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10408 } 10409 { 10410 BI opval = 0; 10411 SET_H_INSN_PREFIXED_P (opval); 10412 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10413 } 10414} 10415} 10416} 10417 10418 abuf->written = written; 10419#undef FLD 10420} 10421 NEXT (vpc); 10422 10423 CASE (sem, INSN_ANDCBR) : /* and.b ${sconst8}],${Rd} */ 10424{ 10425 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10426 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10427#define FLD(f) abuf->fields.sfmt_addcbr.f 10428 int UNUSED written = 0; 10429 IADDR UNUSED pc = abuf->addr; 10430 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 10431 10432{ 10433 QI tmp_tmpd; 10434 tmp_tmpd = ANDQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte)); 10435{ 10436 SI tmp_oldregval; 10437 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 10438 { 10439 SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00)); 10440 SET_H_GR (FLD (f_operand2), opval); 10441 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10442 } 10443} 10444{ 10445 { 10446 BI opval = LTQI (tmp_tmpd, 0); 10447 CPU (h_nbit) = opval; 10448 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10449 } 10450 { 10451 BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10452 CPU (h_zbit) = opval; 10453 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10454 } 10455SET_H_CBIT_MOVE (0); 10456SET_H_VBIT_MOVE (0); 10457{ 10458 { 10459 BI opval = 0; 10460 CPU (h_xbit) = opval; 10461 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10462 } 10463 { 10464 BI opval = 0; 10465 SET_H_INSN_PREFIXED_P (opval); 10466 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10467 } 10468} 10469} 10470} 10471 10472#undef FLD 10473} 10474 NEXT (vpc); 10475 10476 CASE (sem, INSN_ANDCWR) : /* and.w ${sconst16}],${Rd} */ 10477{ 10478 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10479 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10480#define FLD(f) abuf->fields.sfmt_addcwr.f 10481 int UNUSED written = 0; 10482 IADDR UNUSED pc = abuf->addr; 10483 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 10484 10485{ 10486 HI tmp_tmpd; 10487 tmp_tmpd = ANDHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word)); 10488{ 10489 SI tmp_oldregval; 10490 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 10491 { 10492 SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 10493 SET_H_GR (FLD (f_operand2), opval); 10494 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10495 } 10496} 10497{ 10498 { 10499 BI opval = LTHI (tmp_tmpd, 0); 10500 CPU (h_nbit) = opval; 10501 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10502 } 10503 { 10504 BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10505 CPU (h_zbit) = opval; 10506 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10507 } 10508SET_H_CBIT_MOVE (0); 10509SET_H_VBIT_MOVE (0); 10510{ 10511 { 10512 BI opval = 0; 10513 CPU (h_xbit) = opval; 10514 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10515 } 10516 { 10517 BI opval = 0; 10518 SET_H_INSN_PREFIXED_P (opval); 10519 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10520 } 10521} 10522} 10523} 10524 10525#undef FLD 10526} 10527 NEXT (vpc); 10528 10529 CASE (sem, INSN_ANDCDR) : /* and.d ${const32}],${Rd} */ 10530{ 10531 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10532 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10533#define FLD(f) abuf->fields.sfmt_addcdr.f 10534 int UNUSED written = 0; 10535 IADDR UNUSED pc = abuf->addr; 10536 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 10537 10538{ 10539 SI tmp_tmpd; 10540 tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword)); 10541 { 10542 SI opval = tmp_tmpd; 10543 SET_H_GR (FLD (f_operand2), opval); 10544 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10545 } 10546{ 10547 { 10548 BI opval = LTSI (tmp_tmpd, 0); 10549 CPU (h_nbit) = opval; 10550 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10551 } 10552 { 10553 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10554 CPU (h_zbit) = opval; 10555 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10556 } 10557SET_H_CBIT_MOVE (0); 10558SET_H_VBIT_MOVE (0); 10559{ 10560 { 10561 BI opval = 0; 10562 CPU (h_xbit) = opval; 10563 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10564 } 10565 { 10566 BI opval = 0; 10567 SET_H_INSN_PREFIXED_P (opval); 10568 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10569 } 10570} 10571} 10572} 10573 10574#undef FLD 10575} 10576 NEXT (vpc); 10577 10578 CASE (sem, INSN_ANDQ) : /* andq $i,$Rd */ 10579{ 10580 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10581 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10582#define FLD(f) abuf->fields.sfmt_andq.f 10583 int UNUSED written = 0; 10584 IADDR UNUSED pc = abuf->addr; 10585 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10586 10587{ 10588 SI tmp_tmpd; 10589 tmp_tmpd = ANDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6)); 10590 { 10591 SI opval = tmp_tmpd; 10592 SET_H_GR (FLD (f_operand2), opval); 10593 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10594 } 10595{ 10596 { 10597 BI opval = LTSI (tmp_tmpd, 0); 10598 CPU (h_nbit) = opval; 10599 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10600 } 10601 { 10602 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10603 CPU (h_zbit) = opval; 10604 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10605 } 10606SET_H_CBIT_MOVE (0); 10607SET_H_VBIT_MOVE (0); 10608{ 10609 { 10610 BI opval = 0; 10611 CPU (h_xbit) = opval; 10612 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10613 } 10614 { 10615 BI opval = 0; 10616 SET_H_INSN_PREFIXED_P (opval); 10617 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10618 } 10619} 10620} 10621} 10622 10623#undef FLD 10624} 10625 NEXT (vpc); 10626 10627 CASE (sem, INSN_ORR_B_R) : /* orr.b $Rs,$Rd */ 10628{ 10629 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10630 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10631#define FLD(f) abuf->fields.sfmt_addc_m.f 10632 int UNUSED written = 0; 10633 IADDR UNUSED pc = abuf->addr; 10634 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10635 10636{ 10637 QI tmp_tmpd; 10638 tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1))); 10639{ 10640 SI tmp_oldregval; 10641 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 10642 { 10643 SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00)); 10644 SET_H_GR (FLD (f_operand2), opval); 10645 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10646 } 10647} 10648{ 10649 { 10650 BI opval = LTQI (tmp_tmpd, 0); 10651 CPU (h_nbit) = opval; 10652 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10653 } 10654 { 10655 BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10656 CPU (h_zbit) = opval; 10657 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10658 } 10659SET_H_CBIT_MOVE (0); 10660SET_H_VBIT_MOVE (0); 10661{ 10662 { 10663 BI opval = 0; 10664 CPU (h_xbit) = opval; 10665 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10666 } 10667 { 10668 BI opval = 0; 10669 SET_H_INSN_PREFIXED_P (opval); 10670 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10671 } 10672} 10673} 10674} 10675 10676#undef FLD 10677} 10678 NEXT (vpc); 10679 10680 CASE (sem, INSN_ORR_W_R) : /* orr.w $Rs,$Rd */ 10681{ 10682 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10683 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10684#define FLD(f) abuf->fields.sfmt_addc_m.f 10685 int UNUSED written = 0; 10686 IADDR UNUSED pc = abuf->addr; 10687 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10688 10689{ 10690 HI tmp_tmpd; 10691 tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1))); 10692{ 10693 SI tmp_oldregval; 10694 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 10695 { 10696 SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 10697 SET_H_GR (FLD (f_operand2), opval); 10698 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10699 } 10700} 10701{ 10702 { 10703 BI opval = LTHI (tmp_tmpd, 0); 10704 CPU (h_nbit) = opval; 10705 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10706 } 10707 { 10708 BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10709 CPU (h_zbit) = opval; 10710 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10711 } 10712SET_H_CBIT_MOVE (0); 10713SET_H_VBIT_MOVE (0); 10714{ 10715 { 10716 BI opval = 0; 10717 CPU (h_xbit) = opval; 10718 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10719 } 10720 { 10721 BI opval = 0; 10722 SET_H_INSN_PREFIXED_P (opval); 10723 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10724 } 10725} 10726} 10727} 10728 10729#undef FLD 10730} 10731 NEXT (vpc); 10732 10733 CASE (sem, INSN_ORR_D_R) : /* orr.d $Rs,$Rd */ 10734{ 10735 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10736 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10737#define FLD(f) abuf->fields.sfmt_addc_m.f 10738 int UNUSED written = 0; 10739 IADDR UNUSED pc = abuf->addr; 10740 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10741 10742{ 10743 SI tmp_tmpd; 10744 tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1))); 10745 { 10746 SI opval = tmp_tmpd; 10747 SET_H_GR (FLD (f_operand2), opval); 10748 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10749 } 10750{ 10751 { 10752 BI opval = LTSI (tmp_tmpd, 0); 10753 CPU (h_nbit) = opval; 10754 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10755 } 10756 { 10757 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10758 CPU (h_zbit) = opval; 10759 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10760 } 10761SET_H_CBIT_MOVE (0); 10762SET_H_VBIT_MOVE (0); 10763{ 10764 { 10765 BI opval = 0; 10766 CPU (h_xbit) = opval; 10767 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10768 } 10769 { 10770 BI opval = 0; 10771 SET_H_INSN_PREFIXED_P (opval); 10772 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10773 } 10774} 10775} 10776} 10777 10778#undef FLD 10779} 10780 NEXT (vpc); 10781 10782 CASE (sem, INSN_OR_M_B_M) : /* or-m.b [${Rs}${inc}],${Rd} */ 10783{ 10784 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10785 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10786#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 10787 int UNUSED written = 0; 10788 IADDR UNUSED pc = abuf->addr; 10789 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10790 10791{ 10792 QI tmp_tmpd; 10793 tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr; 10794 QI tmp_tmp_mem; 10795 BI tmp_postinc; 10796 tmp_postinc = FLD (f_memmode); 10797; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 10798; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 10799; if (NEBI (tmp_postinc, 0)) { 10800{ 10801if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 10802 tmp_addr = ADDSI (tmp_addr, 1); 10803} 10804 { 10805 SI opval = tmp_addr; 10806 SET_H_GR (FLD (f_operand1), opval); 10807 written |= (1 << 11); 10808 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10809 } 10810} 10811} 10812; tmp_tmp_mem; })); 10813{ 10814 SI tmp_oldregval; 10815 tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2)))); 10816 { 10817 SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00)); 10818 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 10819 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10820 } 10821} 10822{ 10823 { 10824 BI opval = LTQI (tmp_tmpd, 0); 10825 CPU (h_nbit) = opval; 10826 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10827 } 10828 { 10829 BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10830 CPU (h_zbit) = opval; 10831 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10832 } 10833SET_H_CBIT_MOVE (0); 10834SET_H_VBIT_MOVE (0); 10835{ 10836 { 10837 BI opval = 0; 10838 CPU (h_xbit) = opval; 10839 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10840 } 10841 { 10842 BI opval = 0; 10843 SET_H_INSN_PREFIXED_P (opval); 10844 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10845 } 10846} 10847} 10848} 10849 10850 abuf->written = written; 10851#undef FLD 10852} 10853 NEXT (vpc); 10854 10855 CASE (sem, INSN_OR_M_W_M) : /* or-m.w [${Rs}${inc}],${Rd} */ 10856{ 10857 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10858 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10859#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 10860 int UNUSED written = 0; 10861 IADDR UNUSED pc = abuf->addr; 10862 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10863 10864{ 10865 HI tmp_tmpd; 10866 tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr; 10867 HI tmp_tmp_mem; 10868 BI tmp_postinc; 10869 tmp_postinc = FLD (f_memmode); 10870; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 10871; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 10872; if (NEBI (tmp_postinc, 0)) { 10873{ 10874if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 10875 tmp_addr = ADDSI (tmp_addr, 2); 10876} 10877 { 10878 SI opval = tmp_addr; 10879 SET_H_GR (FLD (f_operand1), opval); 10880 written |= (1 << 11); 10881 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10882 } 10883} 10884} 10885; tmp_tmp_mem; })); 10886{ 10887 SI tmp_oldregval; 10888 tmp_oldregval = GET_H_RAW_GR_ACR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2)))); 10889 { 10890 SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 10891 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 10892 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10893 } 10894} 10895{ 10896 { 10897 BI opval = LTHI (tmp_tmpd, 0); 10898 CPU (h_nbit) = opval; 10899 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10900 } 10901 { 10902 BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10903 CPU (h_zbit) = opval; 10904 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10905 } 10906SET_H_CBIT_MOVE (0); 10907SET_H_VBIT_MOVE (0); 10908{ 10909 { 10910 BI opval = 0; 10911 CPU (h_xbit) = opval; 10912 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10913 } 10914 { 10915 BI opval = 0; 10916 SET_H_INSN_PREFIXED_P (opval); 10917 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10918 } 10919} 10920} 10921} 10922 10923 abuf->written = written; 10924#undef FLD 10925} 10926 NEXT (vpc); 10927 10928 CASE (sem, INSN_OR_M_D_M) : /* or-m.d [${Rs}${inc}],${Rd} */ 10929{ 10930 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 10931 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 10932#define FLD(f) abuf->fields.sfmt_add_m_b_m.f 10933 int UNUSED written = 0; 10934 IADDR UNUSED pc = abuf->addr; 10935 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 10936 10937{ 10938 SI tmp_tmpd; 10939 tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), ({ SI tmp_addr; 10940 SI tmp_tmp_mem; 10941 BI tmp_postinc; 10942 tmp_postinc = FLD (f_memmode); 10943; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 10944; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 10945; if (NEBI (tmp_postinc, 0)) { 10946{ 10947if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 10948 tmp_addr = ADDSI (tmp_addr, 4); 10949} 10950 { 10951 SI opval = tmp_addr; 10952 SET_H_GR (FLD (f_operand1), opval); 10953 written |= (1 << 10); 10954 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10955 } 10956} 10957} 10958; tmp_tmp_mem; })); 10959 { 10960 SI opval = tmp_tmpd; 10961 SET_H_GR (((ANDIF (GET_H_INSN_PREFIXED_P (), NOTSI (FLD (f_memmode)))) ? (FLD (f_operand1)) : (FLD (f_operand2))), opval); 10962 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 10963 } 10964{ 10965 { 10966 BI opval = LTSI (tmp_tmpd, 0); 10967 CPU (h_nbit) = opval; 10968 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 10969 } 10970 { 10971 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 10972 CPU (h_zbit) = opval; 10973 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 10974 } 10975SET_H_CBIT_MOVE (0); 10976SET_H_VBIT_MOVE (0); 10977{ 10978 { 10979 BI opval = 0; 10980 CPU (h_xbit) = opval; 10981 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 10982 } 10983 { 10984 BI opval = 0; 10985 SET_H_INSN_PREFIXED_P (opval); 10986 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 10987 } 10988} 10989} 10990} 10991 10992 abuf->written = written; 10993#undef FLD 10994} 10995 NEXT (vpc); 10996 10997 CASE (sem, INSN_ORCBR) : /* or.b ${sconst8}],${Rd} */ 10998{ 10999 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11000 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11001#define FLD(f) abuf->fields.sfmt_addcbr.f 11002 int UNUSED written = 0; 11003 IADDR UNUSED pc = abuf->addr; 11004 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 11005 11006{ 11007 QI tmp_tmpd; 11008 tmp_tmpd = ORQI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__byte)); 11009{ 11010 SI tmp_oldregval; 11011 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 11012 { 11013 SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00)); 11014 SET_H_GR (FLD (f_operand2), opval); 11015 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11016 } 11017} 11018{ 11019 { 11020 BI opval = LTQI (tmp_tmpd, 0); 11021 CPU (h_nbit) = opval; 11022 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11023 } 11024 { 11025 BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11026 CPU (h_zbit) = opval; 11027 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11028 } 11029SET_H_CBIT_MOVE (0); 11030SET_H_VBIT_MOVE (0); 11031{ 11032 { 11033 BI opval = 0; 11034 CPU (h_xbit) = opval; 11035 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11036 } 11037 { 11038 BI opval = 0; 11039 SET_H_INSN_PREFIXED_P (opval); 11040 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11041 } 11042} 11043} 11044} 11045 11046#undef FLD 11047} 11048 NEXT (vpc); 11049 11050 CASE (sem, INSN_ORCWR) : /* or.w ${sconst16}],${Rd} */ 11051{ 11052 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11053 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11054#define FLD(f) abuf->fields.sfmt_addcwr.f 11055 int UNUSED written = 0; 11056 IADDR UNUSED pc = abuf->addr; 11057 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 11058 11059{ 11060 HI tmp_tmpd; 11061 tmp_tmpd = ORHI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__word)); 11062{ 11063 SI tmp_oldregval; 11064 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 11065 { 11066 SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 11067 SET_H_GR (FLD (f_operand2), opval); 11068 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11069 } 11070} 11071{ 11072 { 11073 BI opval = LTHI (tmp_tmpd, 0); 11074 CPU (h_nbit) = opval; 11075 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11076 } 11077 { 11078 BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11079 CPU (h_zbit) = opval; 11080 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11081 } 11082SET_H_CBIT_MOVE (0); 11083SET_H_VBIT_MOVE (0); 11084{ 11085 { 11086 BI opval = 0; 11087 CPU (h_xbit) = opval; 11088 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11089 } 11090 { 11091 BI opval = 0; 11092 SET_H_INSN_PREFIXED_P (opval); 11093 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11094 } 11095} 11096} 11097} 11098 11099#undef FLD 11100} 11101 NEXT (vpc); 11102 11103 CASE (sem, INSN_ORCDR) : /* or.d ${const32}],${Rd} */ 11104{ 11105 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11106 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11107#define FLD(f) abuf->fields.sfmt_addcdr.f 11108 int UNUSED written = 0; 11109 IADDR UNUSED pc = abuf->addr; 11110 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 11111 11112{ 11113 SI tmp_tmpd; 11114 tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword)); 11115 { 11116 SI opval = tmp_tmpd; 11117 SET_H_GR (FLD (f_operand2), opval); 11118 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11119 } 11120{ 11121 { 11122 BI opval = LTSI (tmp_tmpd, 0); 11123 CPU (h_nbit) = opval; 11124 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11125 } 11126 { 11127 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11128 CPU (h_zbit) = opval; 11129 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11130 } 11131SET_H_CBIT_MOVE (0); 11132SET_H_VBIT_MOVE (0); 11133{ 11134 { 11135 BI opval = 0; 11136 CPU (h_xbit) = opval; 11137 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11138 } 11139 { 11140 BI opval = 0; 11141 SET_H_INSN_PREFIXED_P (opval); 11142 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11143 } 11144} 11145} 11146} 11147 11148#undef FLD 11149} 11150 NEXT (vpc); 11151 11152 CASE (sem, INSN_ORQ) : /* orq $i,$Rd */ 11153{ 11154 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11155 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11156#define FLD(f) abuf->fields.sfmt_andq.f 11157 int UNUSED written = 0; 11158 IADDR UNUSED pc = abuf->addr; 11159 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11160 11161{ 11162 SI tmp_tmpd; 11163 tmp_tmpd = ORSI (GET_H_GR (FLD (f_operand2)), FLD (f_s6)); 11164 { 11165 SI opval = tmp_tmpd; 11166 SET_H_GR (FLD (f_operand2), opval); 11167 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11168 } 11169{ 11170 { 11171 BI opval = LTSI (tmp_tmpd, 0); 11172 CPU (h_nbit) = opval; 11173 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11174 } 11175 { 11176 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11177 CPU (h_zbit) = opval; 11178 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11179 } 11180SET_H_CBIT_MOVE (0); 11181SET_H_VBIT_MOVE (0); 11182{ 11183 { 11184 BI opval = 0; 11185 CPU (h_xbit) = opval; 11186 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11187 } 11188 { 11189 BI opval = 0; 11190 SET_H_INSN_PREFIXED_P (opval); 11191 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11192 } 11193} 11194} 11195} 11196 11197#undef FLD 11198} 11199 NEXT (vpc); 11200 11201 CASE (sem, INSN_XOR) : /* xor $Rs,$Rd */ 11202{ 11203 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11204 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11205#define FLD(f) abuf->fields.sfmt_muls_b.f 11206 int UNUSED written = 0; 11207 IADDR UNUSED pc = abuf->addr; 11208 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11209 11210{ 11211 SI tmp_tmpd; 11212 tmp_tmpd = XORSI (GET_H_GR (FLD (f_operand2)), GET_H_GR (FLD (f_operand1))); 11213 { 11214 SI opval = tmp_tmpd; 11215 SET_H_GR (FLD (f_operand2), opval); 11216 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11217 } 11218{ 11219 { 11220 BI opval = LTSI (tmp_tmpd, 0); 11221 CPU (h_nbit) = opval; 11222 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11223 } 11224 { 11225 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11226 CPU (h_zbit) = opval; 11227 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11228 } 11229SET_H_CBIT_MOVE (0); 11230SET_H_VBIT_MOVE (0); 11231{ 11232 { 11233 BI opval = 0; 11234 CPU (h_xbit) = opval; 11235 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11236 } 11237 { 11238 BI opval = 0; 11239 SET_H_INSN_PREFIXED_P (opval); 11240 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11241 } 11242} 11243} 11244} 11245 11246#undef FLD 11247} 11248 NEXT (vpc); 11249 11250 CASE (sem, INSN_SWAP) : /* swap${swapoption} ${Rs} */ 11251{ 11252 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11253 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11254#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f 11255 int UNUSED written = 0; 11256 IADDR UNUSED pc = abuf->addr; 11257 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11258 11259{ 11260 SI tmp_tmps; 11261 SI tmp_tmpd; 11262 tmp_tmps = GET_H_GR (FLD (f_operand1)); 11263 tmp_tmpd = ({ SI tmp_tmpcode; 11264 SI tmp_tmpval; 11265 SI tmp_tmpres; 11266 tmp_tmpcode = FLD (f_operand2); 11267; tmp_tmpval = tmp_tmps; 11268; if (EQSI (tmp_tmpcode, 0)) { 11269 tmp_tmpres = (cgen_rtx_error (current_cpu, "SWAP without swap modifier isn't implemented"), 0); 11270} 11271 else if (EQSI (tmp_tmpcode, 1)) { 11272 tmp_tmpres = ({ SI tmp_tmpr; 11273 tmp_tmpr = tmp_tmpval; 11274; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); }); 11275} 11276 else if (EQSI (tmp_tmpcode, 2)) { 11277 tmp_tmpres = ({ SI tmp_tmpb; 11278 tmp_tmpb = tmp_tmpval; 11279; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); }); 11280} 11281 else if (EQSI (tmp_tmpcode, 3)) { 11282 tmp_tmpres = ({ SI tmp_tmpr; 11283 tmp_tmpr = ({ SI tmp_tmpb; 11284 tmp_tmpb = tmp_tmpval; 11285; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); }); 11286; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); }); 11287} 11288 else if (EQSI (tmp_tmpcode, 4)) { 11289 tmp_tmpres = ({ SI tmp_tmpb; 11290 tmp_tmpb = tmp_tmpval; 11291; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); }); 11292} 11293 else if (EQSI (tmp_tmpcode, 5)) { 11294 tmp_tmpres = ({ SI tmp_tmpr; 11295 tmp_tmpr = ({ SI tmp_tmpb; 11296 tmp_tmpb = tmp_tmpval; 11297; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); }); 11298; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); }); 11299} 11300 else if (EQSI (tmp_tmpcode, 6)) { 11301 tmp_tmpres = ({ SI tmp_tmpb; 11302 tmp_tmpb = ({ SI tmp_tmpb; 11303 tmp_tmpb = tmp_tmpval; 11304; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); }); 11305; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); }); 11306} 11307 else if (EQSI (tmp_tmpcode, 7)) { 11308 tmp_tmpres = ({ SI tmp_tmpr; 11309 tmp_tmpr = ({ SI tmp_tmpb; 11310 tmp_tmpb = ({ SI tmp_tmpb; 11311 tmp_tmpb = tmp_tmpval; 11312; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); }); 11313; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); }); 11314; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); }); 11315} 11316 else if (EQSI (tmp_tmpcode, 8)) { 11317 tmp_tmpres = INVSI (tmp_tmpval); 11318} 11319 else if (EQSI (tmp_tmpcode, 9)) { 11320 tmp_tmpres = ({ SI tmp_tmpr; 11321 tmp_tmpr = INVSI (tmp_tmpval); 11322; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); }); 11323} 11324 else if (EQSI (tmp_tmpcode, 10)) { 11325 tmp_tmpres = ({ SI tmp_tmpb; 11326 tmp_tmpb = INVSI (tmp_tmpval); 11327; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); }); 11328} 11329 else if (EQSI (tmp_tmpcode, 11)) { 11330 tmp_tmpres = ({ SI tmp_tmpr; 11331 tmp_tmpr = ({ SI tmp_tmpb; 11332 tmp_tmpb = INVSI (tmp_tmpval); 11333; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); }); 11334; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); }); 11335} 11336 else if (EQSI (tmp_tmpcode, 12)) { 11337 tmp_tmpres = ({ SI tmp_tmpb; 11338 tmp_tmpb = INVSI (tmp_tmpval); 11339; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); }); 11340} 11341 else if (EQSI (tmp_tmpcode, 13)) { 11342 tmp_tmpres = ({ SI tmp_tmpr; 11343 tmp_tmpr = ({ SI tmp_tmpb; 11344 tmp_tmpb = INVSI (tmp_tmpval); 11345; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); }); 11346; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); }); 11347} 11348 else if (EQSI (tmp_tmpcode, 14)) { 11349 tmp_tmpres = ({ SI tmp_tmpb; 11350 tmp_tmpb = ({ SI tmp_tmpb; 11351 tmp_tmpb = INVSI (tmp_tmpval); 11352; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); }); 11353; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); }); 11354} 11355 else if (EQSI (tmp_tmpcode, 15)) { 11356 tmp_tmpres = ({ SI tmp_tmpr; 11357 tmp_tmpr = ({ SI tmp_tmpb; 11358 tmp_tmpb = ({ SI tmp_tmpb; 11359 tmp_tmpb = INVSI (tmp_tmpval); 11360; ORSI (ANDSI (SLLSI (tmp_tmpb, 16), 0xffff0000), ANDSI (SRLSI (tmp_tmpb, 16), 65535)); }); 11361; ORSI (ANDSI (SLLSI (tmp_tmpb, 8), 0xff00ff00), ANDSI (SRLSI (tmp_tmpb, 8), 16711935)); }); 11362; ORSI (SLLSI (ANDSI (tmp_tmpr, 16843009), 7), ORSI (SLLSI (ANDSI (tmp_tmpr, 33686018), 5), ORSI (SLLSI (ANDSI (tmp_tmpr, 67372036), 3), ORSI (SLLSI (ANDSI (tmp_tmpr, 134744072), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 269488144), 1), ORSI (SRLSI (ANDSI (tmp_tmpr, 538976288), 3), ORSI (SRLSI (ANDSI (tmp_tmpr, 1077952576), 5), SRLSI (ANDSI (tmp_tmpr, 0x80808080), 7)))))))); }); 11363} 11364; tmp_tmpres; }); 11365 { 11366 SI opval = tmp_tmpd; 11367 SET_H_GR (FLD (f_operand1), opval); 11368 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11369 } 11370{ 11371 { 11372 BI opval = LTSI (tmp_tmpd, 0); 11373 CPU (h_nbit) = opval; 11374 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11375 } 11376 { 11377 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11378 CPU (h_zbit) = opval; 11379 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11380 } 11381SET_H_CBIT_MOVE (0); 11382SET_H_VBIT_MOVE (0); 11383{ 11384 { 11385 BI opval = 0; 11386 CPU (h_xbit) = opval; 11387 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11388 } 11389 { 11390 BI opval = 0; 11391 SET_H_INSN_PREFIXED_P (opval); 11392 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11393 } 11394} 11395} 11396} 11397 11398#undef FLD 11399} 11400 NEXT (vpc); 11401 11402 CASE (sem, INSN_ASRR_B_R) : /* asrr.b $Rs,$Rd */ 11403{ 11404 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11405 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11406#define FLD(f) abuf->fields.sfmt_addc_m.f 11407 int UNUSED written = 0; 11408 IADDR UNUSED pc = abuf->addr; 11409 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11410 11411{ 11412 QI tmp_tmpd; 11413 SI tmp_cnt1; 11414 SI tmp_cnt2; 11415 tmp_cnt1 = GET_H_GR (FLD (f_operand1)); 11416 tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31))); 11417 tmp_tmpd = SRASI (EXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2); 11418{ 11419 SI tmp_oldregval; 11420 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 11421 { 11422 SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00)); 11423 SET_H_GR (FLD (f_operand2), opval); 11424 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11425 } 11426} 11427{ 11428 { 11429 BI opval = LTQI (tmp_tmpd, 0); 11430 CPU (h_nbit) = opval; 11431 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11432 } 11433 { 11434 BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11435 CPU (h_zbit) = opval; 11436 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11437 } 11438SET_H_CBIT_MOVE (0); 11439SET_H_VBIT_MOVE (0); 11440{ 11441 { 11442 BI opval = 0; 11443 CPU (h_xbit) = opval; 11444 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11445 } 11446 { 11447 BI opval = 0; 11448 SET_H_INSN_PREFIXED_P (opval); 11449 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11450 } 11451} 11452} 11453} 11454 11455#undef FLD 11456} 11457 NEXT (vpc); 11458 11459 CASE (sem, INSN_ASRR_W_R) : /* asrr.w $Rs,$Rd */ 11460{ 11461 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11462 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11463#define FLD(f) abuf->fields.sfmt_addc_m.f 11464 int UNUSED written = 0; 11465 IADDR UNUSED pc = abuf->addr; 11466 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11467 11468{ 11469 HI tmp_tmpd; 11470 SI tmp_cnt1; 11471 SI tmp_cnt2; 11472 tmp_cnt1 = GET_H_GR (FLD (f_operand1)); 11473 tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31))); 11474 tmp_tmpd = SRASI (EXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2); 11475{ 11476 SI tmp_oldregval; 11477 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 11478 { 11479 SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 11480 SET_H_GR (FLD (f_operand2), opval); 11481 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11482 } 11483} 11484{ 11485 { 11486 BI opval = LTHI (tmp_tmpd, 0); 11487 CPU (h_nbit) = opval; 11488 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11489 } 11490 { 11491 BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11492 CPU (h_zbit) = opval; 11493 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11494 } 11495SET_H_CBIT_MOVE (0); 11496SET_H_VBIT_MOVE (0); 11497{ 11498 { 11499 BI opval = 0; 11500 CPU (h_xbit) = opval; 11501 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11502 } 11503 { 11504 BI opval = 0; 11505 SET_H_INSN_PREFIXED_P (opval); 11506 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11507 } 11508} 11509} 11510} 11511 11512#undef FLD 11513} 11514 NEXT (vpc); 11515 11516 CASE (sem, INSN_ASRR_D_R) : /* asrr.d $Rs,$Rd */ 11517{ 11518 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11519 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11520#define FLD(f) abuf->fields.sfmt_addc_m.f 11521 int UNUSED written = 0; 11522 IADDR UNUSED pc = abuf->addr; 11523 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11524 11525{ 11526 SI tmp_tmpd; 11527 SI tmp_cnt1; 11528 SI tmp_cnt2; 11529 tmp_cnt1 = GET_H_GR (FLD (f_operand1)); 11530 tmp_cnt2 = ((NESI (ANDSI (tmp_cnt1, 32), 0)) ? (31) : (ANDSI (tmp_cnt1, 31))); 11531 tmp_tmpd = SRASI (EXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), tmp_cnt2); 11532 { 11533 SI opval = tmp_tmpd; 11534 SET_H_GR (FLD (f_operand2), opval); 11535 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11536 } 11537{ 11538 { 11539 BI opval = LTSI (tmp_tmpd, 0); 11540 CPU (h_nbit) = opval; 11541 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11542 } 11543 { 11544 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11545 CPU (h_zbit) = opval; 11546 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11547 } 11548SET_H_CBIT_MOVE (0); 11549SET_H_VBIT_MOVE (0); 11550{ 11551 { 11552 BI opval = 0; 11553 CPU (h_xbit) = opval; 11554 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11555 } 11556 { 11557 BI opval = 0; 11558 SET_H_INSN_PREFIXED_P (opval); 11559 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11560 } 11561} 11562} 11563} 11564 11565#undef FLD 11566} 11567 NEXT (vpc); 11568 11569 CASE (sem, INSN_ASRQ) : /* asrq $c,${Rd} */ 11570{ 11571 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11572 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11573#define FLD(f) abuf->fields.sfmt_asrq.f 11574 int UNUSED written = 0; 11575 IADDR UNUSED pc = abuf->addr; 11576 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11577 11578{ 11579 SI tmp_tmpd; 11580 tmp_tmpd = SRASI (GET_H_GR (FLD (f_operand2)), FLD (f_u5)); 11581 { 11582 SI opval = tmp_tmpd; 11583 SET_H_GR (FLD (f_operand2), opval); 11584 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11585 } 11586{ 11587 { 11588 BI opval = LTSI (tmp_tmpd, 0); 11589 CPU (h_nbit) = opval; 11590 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11591 } 11592 { 11593 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11594 CPU (h_zbit) = opval; 11595 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11596 } 11597SET_H_CBIT_MOVE (0); 11598SET_H_VBIT_MOVE (0); 11599{ 11600 { 11601 BI opval = 0; 11602 CPU (h_xbit) = opval; 11603 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11604 } 11605 { 11606 BI opval = 0; 11607 SET_H_INSN_PREFIXED_P (opval); 11608 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11609 } 11610} 11611} 11612} 11613 11614#undef FLD 11615} 11616 NEXT (vpc); 11617 11618 CASE (sem, INSN_LSRR_B_R) : /* lsrr.b $Rs,$Rd */ 11619{ 11620 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11621 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11622#define FLD(f) abuf->fields.sfmt_addc_m.f 11623 int UNUSED written = 0; 11624 IADDR UNUSED pc = abuf->addr; 11625 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11626 11627{ 11628 SI tmp_tmpd; 11629 SI tmp_cnt; 11630 tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63); 11631 tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31)))); 11632{ 11633 SI tmp_oldregval; 11634 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 11635 { 11636 SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00)); 11637 SET_H_GR (FLD (f_operand2), opval); 11638 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11639 } 11640} 11641{ 11642 { 11643 BI opval = LTQI (tmp_tmpd, 0); 11644 CPU (h_nbit) = opval; 11645 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11646 } 11647 { 11648 BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11649 CPU (h_zbit) = opval; 11650 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11651 } 11652SET_H_CBIT_MOVE (0); 11653SET_H_VBIT_MOVE (0); 11654{ 11655 { 11656 BI opval = 0; 11657 CPU (h_xbit) = opval; 11658 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11659 } 11660 { 11661 BI opval = 0; 11662 SET_H_INSN_PREFIXED_P (opval); 11663 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11664 } 11665} 11666} 11667} 11668 11669#undef FLD 11670} 11671 NEXT (vpc); 11672 11673 CASE (sem, INSN_LSRR_W_R) : /* lsrr.w $Rs,$Rd */ 11674{ 11675 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11676 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11677#define FLD(f) abuf->fields.sfmt_addc_m.f 11678 int UNUSED written = 0; 11679 IADDR UNUSED pc = abuf->addr; 11680 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11681 11682{ 11683 SI tmp_tmpd; 11684 SI tmp_cnt; 11685 tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63); 11686 tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31)))); 11687{ 11688 SI tmp_oldregval; 11689 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 11690 { 11691 SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 11692 SET_H_GR (FLD (f_operand2), opval); 11693 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11694 } 11695} 11696{ 11697 { 11698 BI opval = LTHI (tmp_tmpd, 0); 11699 CPU (h_nbit) = opval; 11700 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11701 } 11702 { 11703 BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11704 CPU (h_zbit) = opval; 11705 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11706 } 11707SET_H_CBIT_MOVE (0); 11708SET_H_VBIT_MOVE (0); 11709{ 11710 { 11711 BI opval = 0; 11712 CPU (h_xbit) = opval; 11713 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11714 } 11715 { 11716 BI opval = 0; 11717 SET_H_INSN_PREFIXED_P (opval); 11718 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11719 } 11720} 11721} 11722} 11723 11724#undef FLD 11725} 11726 NEXT (vpc); 11727 11728 CASE (sem, INSN_LSRR_D_R) : /* lsrr.d $Rs,$Rd */ 11729{ 11730 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11731 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11732#define FLD(f) abuf->fields.sfmt_addc_m.f 11733 int UNUSED written = 0; 11734 IADDR UNUSED pc = abuf->addr; 11735 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11736 11737{ 11738 SI tmp_tmpd; 11739 SI tmp_cnt; 11740 tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63); 11741 tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SRLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31)))); 11742 { 11743 SI opval = tmp_tmpd; 11744 SET_H_GR (FLD (f_operand2), opval); 11745 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11746 } 11747{ 11748 { 11749 BI opval = LTSI (tmp_tmpd, 0); 11750 CPU (h_nbit) = opval; 11751 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11752 } 11753 { 11754 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11755 CPU (h_zbit) = opval; 11756 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11757 } 11758SET_H_CBIT_MOVE (0); 11759SET_H_VBIT_MOVE (0); 11760{ 11761 { 11762 BI opval = 0; 11763 CPU (h_xbit) = opval; 11764 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11765 } 11766 { 11767 BI opval = 0; 11768 SET_H_INSN_PREFIXED_P (opval); 11769 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11770 } 11771} 11772} 11773} 11774 11775#undef FLD 11776} 11777 NEXT (vpc); 11778 11779 CASE (sem, INSN_LSRQ) : /* lsrq $c,${Rd} */ 11780{ 11781 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11782 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11783#define FLD(f) abuf->fields.sfmt_asrq.f 11784 int UNUSED written = 0; 11785 IADDR UNUSED pc = abuf->addr; 11786 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11787 11788{ 11789 SI tmp_tmpd; 11790 tmp_tmpd = SRLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5)); 11791 { 11792 SI opval = tmp_tmpd; 11793 SET_H_GR (FLD (f_operand2), opval); 11794 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11795 } 11796{ 11797 { 11798 BI opval = LTSI (tmp_tmpd, 0); 11799 CPU (h_nbit) = opval; 11800 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11801 } 11802 { 11803 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11804 CPU (h_zbit) = opval; 11805 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11806 } 11807SET_H_CBIT_MOVE (0); 11808SET_H_VBIT_MOVE (0); 11809{ 11810 { 11811 BI opval = 0; 11812 CPU (h_xbit) = opval; 11813 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11814 } 11815 { 11816 BI opval = 0; 11817 SET_H_INSN_PREFIXED_P (opval); 11818 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11819 } 11820} 11821} 11822} 11823 11824#undef FLD 11825} 11826 NEXT (vpc); 11827 11828 CASE (sem, INSN_LSLR_B_R) : /* lslr.b $Rs,$Rd */ 11829{ 11830 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11831 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11832#define FLD(f) abuf->fields.sfmt_addc_m.f 11833 int UNUSED written = 0; 11834 IADDR UNUSED pc = abuf->addr; 11835 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11836 11837{ 11838 SI tmp_tmpd; 11839 SI tmp_cnt; 11840 tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63); 11841 tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31)))); 11842{ 11843 SI tmp_oldregval; 11844 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 11845 { 11846 SI opval = ORSI (ANDSI (tmp_tmpd, 255), ANDSI (tmp_oldregval, 0xffffff00)); 11847 SET_H_GR (FLD (f_operand2), opval); 11848 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11849 } 11850} 11851{ 11852 { 11853 BI opval = LTQI (tmp_tmpd, 0); 11854 CPU (h_nbit) = opval; 11855 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11856 } 11857 { 11858 BI opval = ANDIF (EQQI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11859 CPU (h_zbit) = opval; 11860 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11861 } 11862SET_H_CBIT_MOVE (0); 11863SET_H_VBIT_MOVE (0); 11864{ 11865 { 11866 BI opval = 0; 11867 CPU (h_xbit) = opval; 11868 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11869 } 11870 { 11871 BI opval = 0; 11872 SET_H_INSN_PREFIXED_P (opval); 11873 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11874 } 11875} 11876} 11877} 11878 11879#undef FLD 11880} 11881 NEXT (vpc); 11882 11883 CASE (sem, INSN_LSLR_W_R) : /* lslr.w $Rs,$Rd */ 11884{ 11885 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11886 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11887#define FLD(f) abuf->fields.sfmt_addc_m.f 11888 int UNUSED written = 0; 11889 IADDR UNUSED pc = abuf->addr; 11890 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11891 11892{ 11893 SI tmp_tmpd; 11894 SI tmp_cnt; 11895 tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63); 11896 tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31)))); 11897{ 11898 SI tmp_oldregval; 11899 tmp_oldregval = GET_H_RAW_GR_ACR (FLD (f_operand2)); 11900 { 11901 SI opval = ORSI (ANDSI (tmp_tmpd, 65535), ANDSI (tmp_oldregval, 0xffff0000)); 11902 SET_H_GR (FLD (f_operand2), opval); 11903 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11904 } 11905} 11906{ 11907 { 11908 BI opval = LTHI (tmp_tmpd, 0); 11909 CPU (h_nbit) = opval; 11910 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11911 } 11912 { 11913 BI opval = ANDIF (EQHI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11914 CPU (h_zbit) = opval; 11915 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11916 } 11917SET_H_CBIT_MOVE (0); 11918SET_H_VBIT_MOVE (0); 11919{ 11920 { 11921 BI opval = 0; 11922 CPU (h_xbit) = opval; 11923 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11924 } 11925 { 11926 BI opval = 0; 11927 SET_H_INSN_PREFIXED_P (opval); 11928 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11929 } 11930} 11931} 11932} 11933 11934#undef FLD 11935} 11936 NEXT (vpc); 11937 11938 CASE (sem, INSN_LSLR_D_R) : /* lslr.d $Rs,$Rd */ 11939{ 11940 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11941 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11942#define FLD(f) abuf->fields.sfmt_addc_m.f 11943 int UNUSED written = 0; 11944 IADDR UNUSED pc = abuf->addr; 11945 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11946 11947{ 11948 SI tmp_tmpd; 11949 SI tmp_cnt; 11950 tmp_cnt = ANDSI (GET_H_GR (FLD (f_operand1)), 63); 11951 tmp_tmpd = ((NESI (ANDSI (tmp_cnt, 32), 0)) ? (0) : (SLLSI (ZEXTSISI (TRUNCSISI (GET_H_GR (FLD (f_operand2)))), ANDSI (tmp_cnt, 31)))); 11952 { 11953 SI opval = tmp_tmpd; 11954 SET_H_GR (FLD (f_operand2), opval); 11955 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 11956 } 11957{ 11958 { 11959 BI opval = LTSI (tmp_tmpd, 0); 11960 CPU (h_nbit) = opval; 11961 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 11962 } 11963 { 11964 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 11965 CPU (h_zbit) = opval; 11966 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 11967 } 11968SET_H_CBIT_MOVE (0); 11969SET_H_VBIT_MOVE (0); 11970{ 11971 { 11972 BI opval = 0; 11973 CPU (h_xbit) = opval; 11974 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 11975 } 11976 { 11977 BI opval = 0; 11978 SET_H_INSN_PREFIXED_P (opval); 11979 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 11980 } 11981} 11982} 11983} 11984 11985#undef FLD 11986} 11987 NEXT (vpc); 11988 11989 CASE (sem, INSN_LSLQ) : /* lslq $c,${Rd} */ 11990{ 11991 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 11992 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 11993#define FLD(f) abuf->fields.sfmt_asrq.f 11994 int UNUSED written = 0; 11995 IADDR UNUSED pc = abuf->addr; 11996 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 11997 11998{ 11999 SI tmp_tmpd; 12000 tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), FLD (f_u5)); 12001 { 12002 SI opval = tmp_tmpd; 12003 SET_H_GR (FLD (f_operand2), opval); 12004 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 12005 } 12006{ 12007 { 12008 BI opval = LTSI (tmp_tmpd, 0); 12009 CPU (h_nbit) = opval; 12010 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 12011 } 12012 { 12013 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 12014 CPU (h_zbit) = opval; 12015 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 12016 } 12017SET_H_CBIT_MOVE (0); 12018SET_H_VBIT_MOVE (0); 12019{ 12020 { 12021 BI opval = 0; 12022 CPU (h_xbit) = opval; 12023 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12024 } 12025 { 12026 BI opval = 0; 12027 SET_H_INSN_PREFIXED_P (opval); 12028 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12029 } 12030} 12031} 12032} 12033 12034#undef FLD 12035} 12036 NEXT (vpc); 12037 12038 CASE (sem, INSN_BTST) : /* $Rs,$Rd */ 12039{ 12040 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12041 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12042#define FLD(f) abuf->fields.sfmt_muls_b.f 12043 int UNUSED written = 0; 12044 IADDR UNUSED pc = abuf->addr; 12045 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12046 12047{ 12048 SI tmp_tmpd; 12049 SI tmp_cnt; 12050 tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, ANDSI (GET_H_GR (FLD (f_operand1)), 31))); 12051{ 12052 { 12053 BI opval = LTSI (tmp_tmpd, 0); 12054 CPU (h_nbit) = opval; 12055 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 12056 } 12057 { 12058 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 12059 CPU (h_zbit) = opval; 12060 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 12061 } 12062SET_H_CBIT_MOVE (0); 12063SET_H_VBIT_MOVE (0); 12064{ 12065 { 12066 BI opval = 0; 12067 CPU (h_xbit) = opval; 12068 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12069 } 12070 { 12071 BI opval = 0; 12072 SET_H_INSN_PREFIXED_P (opval); 12073 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12074 } 12075} 12076} 12077} 12078 12079#undef FLD 12080} 12081 NEXT (vpc); 12082 12083 CASE (sem, INSN_BTSTQ) : /* btstq $c,${Rd} */ 12084{ 12085 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12086 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12087#define FLD(f) abuf->fields.sfmt_asrq.f 12088 int UNUSED written = 0; 12089 IADDR UNUSED pc = abuf->addr; 12090 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12091 12092{ 12093 SI tmp_tmpd; 12094 tmp_tmpd = SLLSI (GET_H_GR (FLD (f_operand2)), SUBSI (31, FLD (f_u5))); 12095{ 12096 { 12097 BI opval = LTSI (tmp_tmpd, 0); 12098 CPU (h_nbit) = opval; 12099 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 12100 } 12101 { 12102 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 12103 CPU (h_zbit) = opval; 12104 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 12105 } 12106SET_H_CBIT_MOVE (0); 12107SET_H_VBIT_MOVE (0); 12108{ 12109 { 12110 BI opval = 0; 12111 CPU (h_xbit) = opval; 12112 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12113 } 12114 { 12115 BI opval = 0; 12116 SET_H_INSN_PREFIXED_P (opval); 12117 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12118 } 12119} 12120} 12121} 12122 12123#undef FLD 12124} 12125 NEXT (vpc); 12126 12127 CASE (sem, INSN_SETF) : /* setf ${list-of-flags} */ 12128{ 12129 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12130 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12131#define FLD(f) abuf->fields.sfmt_setf.f 12132 int UNUSED written = 0; 12133 IADDR UNUSED pc = abuf->addr; 12134 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12135 12136{ 12137 SI tmp_tmp; 12138 tmp_tmp = FLD (f_dstsrc); 12139if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) { 12140 { 12141 BI opval = 1; 12142 CPU (h_cbit) = opval; 12143 written |= (1 << 1); 12144 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 12145 } 12146} 12147if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) { 12148 { 12149 BI opval = 1; 12150 CPU (h_vbit) = opval; 12151 written |= (1 << 7); 12152 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 12153 } 12154} 12155if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) { 12156 { 12157 BI opval = 1; 12158 CPU (h_zbit) = opval; 12159 written |= (1 << 9); 12160 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 12161 } 12162} 12163if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) { 12164 { 12165 BI opval = 1; 12166 CPU (h_nbit) = opval; 12167 written |= (1 << 3); 12168 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 12169 } 12170} 12171if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) { 12172 { 12173 BI opval = 1; 12174 CPU (h_xbit) = opval; 12175 written |= (1 << 8); 12176 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12177 } 12178} 12179if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) { 12180 { 12181 BI opval = 1; 12182 SET_H_IBIT (opval); 12183 written |= (1 << 2); 12184 TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval); 12185 } 12186} 12187if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) { 12188 { 12189 BI opval = 1; 12190 SET_H_UBIT (opval); 12191 written |= (1 << 6); 12192 TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval); 12193 } 12194} 12195if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) { 12196 { 12197 BI opval = 1; 12198 CPU (h_pbit) = opval; 12199 written |= (1 << 4); 12200 TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval); 12201 } 12202} 12203 { 12204 BI opval = 0; 12205 SET_H_INSN_PREFIXED_P (opval); 12206 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12207 } 12208if (EQSI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) { 12209 { 12210 BI opval = 0; 12211 CPU (h_xbit) = opval; 12212 written |= (1 << 8); 12213 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12214 } 12215} 12216} 12217 12218 abuf->written = written; 12219#undef FLD 12220} 12221 NEXT (vpc); 12222 12223 CASE (sem, INSN_CLEARF) : /* clearf ${list-of-flags} */ 12224{ 12225 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12226 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12227#define FLD(f) abuf->fields.sfmt_setf.f 12228 int UNUSED written = 0; 12229 IADDR UNUSED pc = abuf->addr; 12230 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12231 12232{ 12233 SI tmp_tmp; 12234 tmp_tmp = FLD (f_dstsrc); 12235if (NESI (ANDSI (tmp_tmp, SLLSI (1, 0)), 0)) { 12236 { 12237 BI opval = 0; 12238 CPU (h_cbit) = opval; 12239 written |= (1 << 1); 12240 TRACE_RESULT (current_cpu, abuf, "cbit", 'x', opval); 12241 } 12242} 12243if (NESI (ANDSI (tmp_tmp, SLLSI (1, 1)), 0)) { 12244 { 12245 BI opval = 0; 12246 CPU (h_vbit) = opval; 12247 written |= (1 << 7); 12248 TRACE_RESULT (current_cpu, abuf, "vbit", 'x', opval); 12249 } 12250} 12251if (NESI (ANDSI (tmp_tmp, SLLSI (1, 2)), 0)) { 12252 { 12253 BI opval = 0; 12254 CPU (h_zbit) = opval; 12255 written |= (1 << 9); 12256 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 12257 } 12258} 12259if (NESI (ANDSI (tmp_tmp, SLLSI (1, 3)), 0)) { 12260 { 12261 BI opval = 0; 12262 CPU (h_nbit) = opval; 12263 written |= (1 << 3); 12264 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 12265 } 12266} 12267if (NESI (ANDSI (tmp_tmp, SLLSI (1, 4)), 0)) { 12268 { 12269 BI opval = 0; 12270 CPU (h_xbit) = opval; 12271 written |= (1 << 8); 12272 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12273 } 12274} 12275if (NESI (ANDSI (tmp_tmp, SLLSI (1, 5)), 0)) { 12276 { 12277 BI opval = 0; 12278 SET_H_IBIT (opval); 12279 written |= (1 << 2); 12280 TRACE_RESULT (current_cpu, abuf, "ibit", 'x', opval); 12281 } 12282} 12283if (NESI (ANDSI (tmp_tmp, SLLSI (1, 6)), 0)) { 12284 { 12285 BI opval = 0; 12286 SET_H_UBIT (opval); 12287 written |= (1 << 6); 12288 TRACE_RESULT (current_cpu, abuf, "ubit", 'x', opval); 12289 } 12290} 12291if (NESI (ANDSI (tmp_tmp, SLLSI (1, 7)), 0)) { 12292 { 12293 BI opval = 0; 12294 CPU (h_pbit) = opval; 12295 written |= (1 << 4); 12296 TRACE_RESULT (current_cpu, abuf, "pbit", 'x', opval); 12297 } 12298} 12299{ 12300 { 12301 BI opval = 0; 12302 CPU (h_xbit) = opval; 12303 written |= (1 << 8); 12304 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12305 } 12306 { 12307 BI opval = 0; 12308 SET_H_INSN_PREFIXED_P (opval); 12309 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12310 } 12311} 12312} 12313 12314 abuf->written = written; 12315#undef FLD 12316} 12317 NEXT (vpc); 12318 12319 CASE (sem, INSN_RFE) : /* rfe */ 12320{ 12321 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12322 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12323#define FLD(f) abuf->fields.sfmt_rfe.f 12324 int UNUSED written = 0; 12325 IADDR UNUSED pc = abuf->addr; 12326 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12327 12328{ 12329 USI tmp_oldccs; 12330 USI tmp_samebits; 12331 USI tmp_shiftbits; 12332 USI tmp_keepmask; 12333 BI tmp_p1; 12334 tmp_oldccs = GET_H_SR (((UINT) 13)); 12335 tmp_keepmask = 0xc0000000; 12336 tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask); 12337 tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask)); 12338 tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072)); 12339 { 12340 SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128))); 12341 SET_H_SR (((UINT) 13), opval); 12342 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 12343 } 12344} 12345 12346#undef FLD 12347} 12348 NEXT (vpc); 12349 12350 CASE (sem, INSN_SFE) : /* sfe */ 12351{ 12352 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12353 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12354#define FLD(f) abuf->fields.sfmt_rfe.f 12355 int UNUSED written = 0; 12356 IADDR UNUSED pc = abuf->addr; 12357 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12358 12359{ 12360 SI tmp_oldccs; 12361 SI tmp_savemask; 12362 tmp_savemask = 0xc0000000; 12363 tmp_oldccs = GET_H_SR (((UINT) 13)); 12364 { 12365 SI opval = ORSI (ANDSI (tmp_savemask, tmp_oldccs), ANDSI (INVSI (tmp_savemask), SLLSI (tmp_oldccs, 10))); 12366 SET_H_SR (((UINT) 13), opval); 12367 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 12368 } 12369} 12370 12371#undef FLD 12372} 12373 NEXT (vpc); 12374 12375 CASE (sem, INSN_RFG) : /* rfg */ 12376{ 12377 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12378 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12379#define FLD(f) abuf->fields.fmt_empty.f 12380 int UNUSED written = 0; 12381 IADDR UNUSED pc = abuf->addr; 12382 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12383 12384crisv32f_rfg_handler (current_cpu, pc); 12385 12386#undef FLD 12387} 12388 NEXT (vpc); 12389 12390 CASE (sem, INSN_RFN) : /* rfn */ 12391{ 12392 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12393 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12394#define FLD(f) abuf->fields.sfmt_rfe.f 12395 int UNUSED written = 0; 12396 IADDR UNUSED pc = abuf->addr; 12397 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12398 12399{ 12400{ 12401 USI tmp_oldccs; 12402 USI tmp_samebits; 12403 USI tmp_shiftbits; 12404 USI tmp_keepmask; 12405 BI tmp_p1; 12406 tmp_oldccs = GET_H_SR (((UINT) 13)); 12407 tmp_keepmask = 0xc0000000; 12408 tmp_samebits = ANDSI (tmp_oldccs, tmp_keepmask); 12409 tmp_shiftbits = ANDSI (SRLSI (ANDSI (tmp_oldccs, 1073609728), 10), INVSI (tmp_keepmask)); 12410 tmp_p1 = NESI (0, ANDSI (tmp_oldccs, 131072)); 12411 { 12412 SI opval = ORSI (ORSI (tmp_samebits, tmp_shiftbits), ((ANDBI (CPU (h_rbit), NOTBI (tmp_p1))) ? (0) : (128))); 12413 SET_H_SR (((UINT) 13), opval); 12414 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 12415 } 12416} 12417 { 12418 BI opval = 1; 12419 SET_H_MBIT (opval); 12420 TRACE_RESULT (current_cpu, abuf, "mbit", 'x', opval); 12421 } 12422} 12423 12424#undef FLD 12425} 12426 NEXT (vpc); 12427 12428 CASE (sem, INSN_HALT) : /* halt */ 12429{ 12430 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12431 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12432#define FLD(f) abuf->fields.fmt_empty.f 12433 int UNUSED written = 0; 12434 IADDR UNUSED pc = abuf->addr; 12435 SEM_BRANCH_INIT 12436 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12437 12438 { 12439 USI opval = crisv32f_halt_handler (current_cpu, pc); 12440 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 12441 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 12442 } 12443 12444 SEM_BRANCH_FINI (vpc); 12445#undef FLD 12446} 12447 NEXT (vpc); 12448 12449 CASE (sem, INSN_BCC_B) : /* b${cc} ${o-pcrel} */ 12450{ 12451 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12452 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12453#define FLD(f) abuf->fields.sfmt_bcc_b.f 12454 int UNUSED written = 0; 12455 IADDR UNUSED pc = abuf->addr; 12456 SEM_BRANCH_INIT 12457 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12458 12459{ 12460 BI tmp_truthval; 12461 tmp_truthval = ({ SI tmp_tmpcond; 12462 BI tmp_condres; 12463 tmp_tmpcond = FLD (f_operand2); 12464; if (EQSI (tmp_tmpcond, 0)) { 12465 tmp_condres = NOTBI (CPU (h_cbit)); 12466} 12467 else if (EQSI (tmp_tmpcond, 1)) { 12468 tmp_condres = CPU (h_cbit); 12469} 12470 else if (EQSI (tmp_tmpcond, 2)) { 12471 tmp_condres = NOTBI (CPU (h_zbit)); 12472} 12473 else if (EQSI (tmp_tmpcond, 3)) { 12474 tmp_condres = CPU (h_zbit); 12475} 12476 else if (EQSI (tmp_tmpcond, 4)) { 12477 tmp_condres = NOTBI (CPU (h_vbit)); 12478} 12479 else if (EQSI (tmp_tmpcond, 5)) { 12480 tmp_condres = CPU (h_vbit); 12481} 12482 else if (EQSI (tmp_tmpcond, 6)) { 12483 tmp_condres = NOTBI (CPU (h_nbit)); 12484} 12485 else if (EQSI (tmp_tmpcond, 7)) { 12486 tmp_condres = CPU (h_nbit); 12487} 12488 else if (EQSI (tmp_tmpcond, 8)) { 12489 tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit)); 12490} 12491 else if (EQSI (tmp_tmpcond, 9)) { 12492 tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit))); 12493} 12494 else if (EQSI (tmp_tmpcond, 10)) { 12495 tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit))); 12496} 12497 else if (EQSI (tmp_tmpcond, 11)) { 12498 tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit)); 12499} 12500 else if (EQSI (tmp_tmpcond, 12)) { 12501 tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))); 12502} 12503 else if (EQSI (tmp_tmpcond, 13)) { 12504 tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)); 12505} 12506 else if (EQSI (tmp_tmpcond, 14)) { 12507 tmp_condres = 1; 12508} 12509 else if (EQSI (tmp_tmpcond, 15)) { 12510 tmp_condres = CPU (h_pbit); 12511} 12512; tmp_condres; }); 12513crisv32f_branch_taken (current_cpu, pc, FLD (i_o_pcrel), tmp_truthval); 12514{ 12515 { 12516 BI opval = 0; 12517 CPU (h_xbit) = opval; 12518 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12519 } 12520 { 12521 BI opval = 0; 12522 SET_H_INSN_PREFIXED_P (opval); 12523 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12524 } 12525} 12526if (tmp_truthval) { 12527{ 12528 { 12529 USI opval = FLD (i_o_pcrel); 12530 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 12531 written |= (1 << 8); 12532 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 12533 } 12534} 12535} 12536} 12537 12538 abuf->written = written; 12539 SEM_BRANCH_FINI (vpc); 12540#undef FLD 12541} 12542 NEXT (vpc); 12543 12544 CASE (sem, INSN_BA_B) : /* ba ${o-pcrel} */ 12545{ 12546 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12547 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12548#define FLD(f) abuf->fields.sfmt_bcc_b.f 12549 int UNUSED written = 0; 12550 IADDR UNUSED pc = abuf->addr; 12551 SEM_BRANCH_INIT 12552 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12553 12554{ 12555{ 12556 { 12557 BI opval = 0; 12558 CPU (h_xbit) = opval; 12559 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12560 } 12561 { 12562 BI opval = 0; 12563 SET_H_INSN_PREFIXED_P (opval); 12564 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12565 } 12566} 12567{ 12568 { 12569 USI opval = FLD (i_o_pcrel); 12570 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 12571 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 12572 } 12573} 12574} 12575 12576 SEM_BRANCH_FINI (vpc); 12577#undef FLD 12578} 12579 NEXT (vpc); 12580 12581 CASE (sem, INSN_BCC_W) : /* b${cc} ${o-word-pcrel} */ 12582{ 12583 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12584 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12585#define FLD(f) abuf->fields.sfmt_bcc_w.f 12586 int UNUSED written = 0; 12587 IADDR UNUSED pc = abuf->addr; 12588 SEM_BRANCH_INIT 12589 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 12590 12591{ 12592 BI tmp_truthval; 12593 tmp_truthval = ({ SI tmp_tmpcond; 12594 BI tmp_condres; 12595 tmp_tmpcond = FLD (f_operand2); 12596; if (EQSI (tmp_tmpcond, 0)) { 12597 tmp_condres = NOTBI (CPU (h_cbit)); 12598} 12599 else if (EQSI (tmp_tmpcond, 1)) { 12600 tmp_condres = CPU (h_cbit); 12601} 12602 else if (EQSI (tmp_tmpcond, 2)) { 12603 tmp_condres = NOTBI (CPU (h_zbit)); 12604} 12605 else if (EQSI (tmp_tmpcond, 3)) { 12606 tmp_condres = CPU (h_zbit); 12607} 12608 else if (EQSI (tmp_tmpcond, 4)) { 12609 tmp_condres = NOTBI (CPU (h_vbit)); 12610} 12611 else if (EQSI (tmp_tmpcond, 5)) { 12612 tmp_condres = CPU (h_vbit); 12613} 12614 else if (EQSI (tmp_tmpcond, 6)) { 12615 tmp_condres = NOTBI (CPU (h_nbit)); 12616} 12617 else if (EQSI (tmp_tmpcond, 7)) { 12618 tmp_condres = CPU (h_nbit); 12619} 12620 else if (EQSI (tmp_tmpcond, 8)) { 12621 tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit)); 12622} 12623 else if (EQSI (tmp_tmpcond, 9)) { 12624 tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit))); 12625} 12626 else if (EQSI (tmp_tmpcond, 10)) { 12627 tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit))); 12628} 12629 else if (EQSI (tmp_tmpcond, 11)) { 12630 tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit)); 12631} 12632 else if (EQSI (tmp_tmpcond, 12)) { 12633 tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))); 12634} 12635 else if (EQSI (tmp_tmpcond, 13)) { 12636 tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)); 12637} 12638 else if (EQSI (tmp_tmpcond, 14)) { 12639 tmp_condres = 1; 12640} 12641 else if (EQSI (tmp_tmpcond, 15)) { 12642 tmp_condres = CPU (h_pbit); 12643} 12644; tmp_condres; }); 12645crisv32f_branch_taken (current_cpu, pc, FLD (i_o_word_pcrel), tmp_truthval); 12646{ 12647 { 12648 BI opval = 0; 12649 CPU (h_xbit) = opval; 12650 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12651 } 12652 { 12653 BI opval = 0; 12654 SET_H_INSN_PREFIXED_P (opval); 12655 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12656 } 12657} 12658if (tmp_truthval) { 12659{ 12660 { 12661 USI opval = FLD (i_o_word_pcrel); 12662 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 12663 written |= (1 << 8); 12664 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 12665 } 12666} 12667} 12668} 12669 12670 abuf->written = written; 12671 SEM_BRANCH_FINI (vpc); 12672#undef FLD 12673} 12674 NEXT (vpc); 12675 12676 CASE (sem, INSN_BA_W) : /* ba ${o-word-pcrel} */ 12677{ 12678 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12679 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12680#define FLD(f) abuf->fields.sfmt_bcc_w.f 12681 int UNUSED written = 0; 12682 IADDR UNUSED pc = abuf->addr; 12683 SEM_BRANCH_INIT 12684 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 12685 12686{ 12687{ 12688 { 12689 BI opval = 0; 12690 CPU (h_xbit) = opval; 12691 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12692 } 12693 { 12694 BI opval = 0; 12695 SET_H_INSN_PREFIXED_P (opval); 12696 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12697 } 12698} 12699{ 12700 { 12701 USI opval = FLD (i_o_word_pcrel); 12702 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 12703 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 12704 } 12705} 12706} 12707 12708 SEM_BRANCH_FINI (vpc); 12709#undef FLD 12710} 12711 NEXT (vpc); 12712 12713 CASE (sem, INSN_JAS_R) : /* jas ${Rs},${Pd} */ 12714{ 12715 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12716 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12717#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f 12718 int UNUSED written = 0; 12719 IADDR UNUSED pc = abuf->addr; 12720 SEM_BRANCH_INIT 12721 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12722 12723{ 12724{ 12725 { 12726 BI opval = 0; 12727 CPU (h_xbit) = opval; 12728 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12729 } 12730 { 12731 BI opval = 0; 12732 SET_H_INSN_PREFIXED_P (opval); 12733 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12734 } 12735} 12736if (ANDIF (EQSI (FLD (f_operand1), 1), EQSI (FLD (f_operand2), 11))) { 12737cris_flush_simulator_decode_cache (current_cpu, pc); 12738} 12739{ 12740{ 12741 { 12742 SI opval = ADDSI (pc, 4); 12743 SET_H_SR (FLD (f_operand2), opval); 12744 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 12745 } 12746 { 12747 USI opval = GET_H_GR (FLD (f_operand1)); 12748 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 12749 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 12750 } 12751} 12752} 12753} 12754 12755 SEM_BRANCH_FINI (vpc); 12756#undef FLD 12757} 12758 NEXT (vpc); 12759 12760 CASE (sem, INSN_JAS_C) : /* jas ${const32},${Pd} */ 12761{ 12762 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12763 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12764#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 12765 int UNUSED written = 0; 12766 IADDR UNUSED pc = abuf->addr; 12767 SEM_BRANCH_INIT 12768 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 12769 12770{ 12771{ 12772 { 12773 BI opval = 0; 12774 CPU (h_xbit) = opval; 12775 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12776 } 12777 { 12778 BI opval = 0; 12779 SET_H_INSN_PREFIXED_P (opval); 12780 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12781 } 12782} 12783{ 12784{ 12785 { 12786 SI opval = ADDSI (pc, 8); 12787 SET_H_SR (FLD (f_operand2), opval); 12788 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 12789 } 12790 { 12791 USI opval = FLD (f_indir_pc__dword); 12792 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 12793 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 12794 } 12795} 12796} 12797} 12798 12799 SEM_BRANCH_FINI (vpc); 12800#undef FLD 12801} 12802 NEXT (vpc); 12803 12804 CASE (sem, INSN_JUMP_P) : /* jump ${Ps} */ 12805{ 12806 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12807 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12808#define FLD(f) abuf->fields.sfmt_mcp.f 12809 int UNUSED written = 0; 12810 IADDR UNUSED pc = abuf->addr; 12811 SEM_BRANCH_INIT 12812 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12813 12814{ 12815{ 12816 { 12817 BI opval = 0; 12818 CPU (h_xbit) = opval; 12819 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12820 } 12821 { 12822 BI opval = 0; 12823 SET_H_INSN_PREFIXED_P (opval); 12824 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12825 } 12826} 12827{ 12828 { 12829 USI opval = GET_H_SR (FLD (f_operand2)); 12830 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 12831 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 12832 } 12833} 12834} 12835 12836 SEM_BRANCH_FINI (vpc); 12837#undef FLD 12838} 12839 NEXT (vpc); 12840 12841 CASE (sem, INSN_BAS_C) : /* bas ${const32},${Pd} */ 12842{ 12843 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12844 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12845#define FLD(f) abuf->fields.sfmt_bas_c.f 12846 int UNUSED written = 0; 12847 IADDR UNUSED pc = abuf->addr; 12848 SEM_BRANCH_INIT 12849 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 12850 12851{ 12852{ 12853 { 12854 BI opval = 0; 12855 CPU (h_xbit) = opval; 12856 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12857 } 12858 { 12859 BI opval = 0; 12860 SET_H_INSN_PREFIXED_P (opval); 12861 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12862 } 12863} 12864{ 12865{ 12866 { 12867 SI opval = ADDSI (pc, 8); 12868 SET_H_SR (FLD (f_operand2), opval); 12869 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 12870 } 12871 { 12872 USI opval = FLD (i_const32_pcrel); 12873 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 12874 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 12875 } 12876} 12877} 12878} 12879 12880 SEM_BRANCH_FINI (vpc); 12881#undef FLD 12882} 12883 NEXT (vpc); 12884 12885 CASE (sem, INSN_JASC_R) : /* jasc ${Rs},${Pd} */ 12886{ 12887 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12888 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12889#define FLD(f) abuf->fields.sfmt_move_m_sprv32.f 12890 int UNUSED written = 0; 12891 IADDR UNUSED pc = abuf->addr; 12892 SEM_BRANCH_INIT 12893 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 12894 12895{ 12896{ 12897 { 12898 BI opval = 0; 12899 CPU (h_xbit) = opval; 12900 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12901 } 12902 { 12903 BI opval = 0; 12904 SET_H_INSN_PREFIXED_P (opval); 12905 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12906 } 12907} 12908{ 12909{ 12910 { 12911 SI opval = ADDSI (pc, 8); 12912 SET_H_SR (FLD (f_operand2), opval); 12913 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 12914 } 12915 { 12916 USI opval = GET_H_GR (FLD (f_operand1)); 12917 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 12918 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 12919 } 12920} 12921} 12922} 12923 12924 SEM_BRANCH_FINI (vpc); 12925#undef FLD 12926} 12927 NEXT (vpc); 12928 12929 CASE (sem, INSN_JASC_C) : /* jasc ${const32},${Pd} */ 12930{ 12931 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12932 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12933#define FLD(f) abuf->fields.sfmt_move_c_sprv32_p2.f 12934 int UNUSED written = 0; 12935 IADDR UNUSED pc = abuf->addr; 12936 SEM_BRANCH_INIT 12937 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 12938 12939{ 12940{ 12941 { 12942 BI opval = 0; 12943 CPU (h_xbit) = opval; 12944 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12945 } 12946 { 12947 BI opval = 0; 12948 SET_H_INSN_PREFIXED_P (opval); 12949 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12950 } 12951} 12952{ 12953{ 12954 { 12955 SI opval = ADDSI (pc, 12); 12956 SET_H_SR (FLD (f_operand2), opval); 12957 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 12958 } 12959 { 12960 USI opval = FLD (f_indir_pc__dword); 12961 SEM_BRANCH_VIA_CACHE (current_cpu, sem_arg, opval, vpc); 12962 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 12963 } 12964} 12965} 12966} 12967 12968 SEM_BRANCH_FINI (vpc); 12969#undef FLD 12970} 12971 NEXT (vpc); 12972 12973 CASE (sem, INSN_BASC_C) : /* basc ${const32},${Pd} */ 12974{ 12975 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 12976 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 12977#define FLD(f) abuf->fields.sfmt_bas_c.f 12978 int UNUSED written = 0; 12979 IADDR UNUSED pc = abuf->addr; 12980 SEM_BRANCH_INIT 12981 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 12982 12983{ 12984{ 12985 { 12986 BI opval = 0; 12987 CPU (h_xbit) = opval; 12988 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 12989 } 12990 { 12991 BI opval = 0; 12992 SET_H_INSN_PREFIXED_P (opval); 12993 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 12994 } 12995} 12996{ 12997{ 12998 { 12999 SI opval = ADDSI (pc, 12); 13000 SET_H_SR (FLD (f_operand2), opval); 13001 TRACE_RESULT (current_cpu, abuf, "sr", 'x', opval); 13002 } 13003 { 13004 USI opval = FLD (i_const32_pcrel); 13005 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 13006 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 13007 } 13008} 13009} 13010} 13011 13012 SEM_BRANCH_FINI (vpc); 13013#undef FLD 13014} 13015 NEXT (vpc); 13016 13017 CASE (sem, INSN_BREAK) : /* break $n */ 13018{ 13019 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13020 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13021#define FLD(f) abuf->fields.sfmt_break.f 13022 int UNUSED written = 0; 13023 IADDR UNUSED pc = abuf->addr; 13024 SEM_BRANCH_INIT 13025 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 13026 13027{ 13028{ 13029 { 13030 BI opval = 0; 13031 CPU (h_xbit) = opval; 13032 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 13033 } 13034 { 13035 BI opval = 0; 13036 SET_H_INSN_PREFIXED_P (opval); 13037 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13038 } 13039} 13040 { 13041 USI opval = crisv32f_break_handler (current_cpu, FLD (f_u4), pc); 13042 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 13043 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 13044 } 13045} 13046 13047 SEM_BRANCH_FINI (vpc); 13048#undef FLD 13049} 13050 NEXT (vpc); 13051 13052 CASE (sem, INSN_BOUND_R_B_R) : /* bound-r.b ${Rs},${Rd} */ 13053{ 13054 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13055 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13056#define FLD(f) abuf->fields.sfmt_muls_b.f 13057 int UNUSED written = 0; 13058 IADDR UNUSED pc = abuf->addr; 13059 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 13060 13061{ 13062 SI tmp_tmpopd; 13063 SI tmp_tmpops; 13064 SI tmp_newval; 13065 tmp_tmpops = ZEXTQISI (TRUNCSIQI (GET_H_GR (FLD (f_operand1)))); 13066 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 13067 tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd)); 13068 { 13069 SI opval = tmp_newval; 13070 SET_H_GR (FLD (f_operand2), opval); 13071 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 13072 } 13073{ 13074 { 13075 BI opval = LTSI (tmp_newval, 0); 13076 CPU (h_nbit) = opval; 13077 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 13078 } 13079 { 13080 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 13081 CPU (h_zbit) = opval; 13082 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 13083 } 13084SET_H_CBIT_MOVE (0); 13085SET_H_VBIT_MOVE (0); 13086{ 13087 { 13088 BI opval = 0; 13089 CPU (h_xbit) = opval; 13090 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 13091 } 13092 { 13093 BI opval = 0; 13094 SET_H_INSN_PREFIXED_P (opval); 13095 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13096 } 13097} 13098} 13099} 13100 13101#undef FLD 13102} 13103 NEXT (vpc); 13104 13105 CASE (sem, INSN_BOUND_R_W_R) : /* bound-r.w ${Rs},${Rd} */ 13106{ 13107 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13108 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13109#define FLD(f) abuf->fields.sfmt_muls_b.f 13110 int UNUSED written = 0; 13111 IADDR UNUSED pc = abuf->addr; 13112 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 13113 13114{ 13115 SI tmp_tmpopd; 13116 SI tmp_tmpops; 13117 SI tmp_newval; 13118 tmp_tmpops = ZEXTHISI (TRUNCSIHI (GET_H_GR (FLD (f_operand1)))); 13119 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 13120 tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd)); 13121 { 13122 SI opval = tmp_newval; 13123 SET_H_GR (FLD (f_operand2), opval); 13124 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 13125 } 13126{ 13127 { 13128 BI opval = LTSI (tmp_newval, 0); 13129 CPU (h_nbit) = opval; 13130 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 13131 } 13132 { 13133 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 13134 CPU (h_zbit) = opval; 13135 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 13136 } 13137SET_H_CBIT_MOVE (0); 13138SET_H_VBIT_MOVE (0); 13139{ 13140 { 13141 BI opval = 0; 13142 CPU (h_xbit) = opval; 13143 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 13144 } 13145 { 13146 BI opval = 0; 13147 SET_H_INSN_PREFIXED_P (opval); 13148 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13149 } 13150} 13151} 13152} 13153 13154#undef FLD 13155} 13156 NEXT (vpc); 13157 13158 CASE (sem, INSN_BOUND_R_D_R) : /* bound-r.d ${Rs},${Rd} */ 13159{ 13160 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13161 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13162#define FLD(f) abuf->fields.sfmt_muls_b.f 13163 int UNUSED written = 0; 13164 IADDR UNUSED pc = abuf->addr; 13165 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 13166 13167{ 13168 SI tmp_tmpopd; 13169 SI tmp_tmpops; 13170 SI tmp_newval; 13171 tmp_tmpops = TRUNCSISI (GET_H_GR (FLD (f_operand1))); 13172 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 13173 tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd)); 13174 { 13175 SI opval = tmp_newval; 13176 SET_H_GR (FLD (f_operand2), opval); 13177 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 13178 } 13179{ 13180 { 13181 BI opval = LTSI (tmp_newval, 0); 13182 CPU (h_nbit) = opval; 13183 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 13184 } 13185 { 13186 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 13187 CPU (h_zbit) = opval; 13188 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 13189 } 13190SET_H_CBIT_MOVE (0); 13191SET_H_VBIT_MOVE (0); 13192{ 13193 { 13194 BI opval = 0; 13195 CPU (h_xbit) = opval; 13196 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 13197 } 13198 { 13199 BI opval = 0; 13200 SET_H_INSN_PREFIXED_P (opval); 13201 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13202 } 13203} 13204} 13205} 13206 13207#undef FLD 13208} 13209 NEXT (vpc); 13210 13211 CASE (sem, INSN_BOUND_CB) : /* bound.b [PC+],${Rd} */ 13212{ 13213 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13214 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13215#define FLD(f) abuf->fields.sfmt_bound_cb.f 13216 int UNUSED written = 0; 13217 IADDR UNUSED pc = abuf->addr; 13218 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 13219 13220{ 13221 SI tmp_tmpopd; 13222 SI tmp_tmpops; 13223 SI tmp_newval; 13224 tmp_tmpops = ZEXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte))); 13225 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 13226 tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd)); 13227 { 13228 SI opval = tmp_newval; 13229 SET_H_GR (FLD (f_operand2), opval); 13230 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 13231 } 13232{ 13233 { 13234 BI opval = LTSI (tmp_newval, 0); 13235 CPU (h_nbit) = opval; 13236 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 13237 } 13238 { 13239 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 13240 CPU (h_zbit) = opval; 13241 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 13242 } 13243SET_H_CBIT_MOVE (0); 13244SET_H_VBIT_MOVE (0); 13245{ 13246 { 13247 BI opval = 0; 13248 CPU (h_xbit) = opval; 13249 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 13250 } 13251 { 13252 BI opval = 0; 13253 SET_H_INSN_PREFIXED_P (opval); 13254 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13255 } 13256} 13257} 13258} 13259 13260#undef FLD 13261} 13262 NEXT (vpc); 13263 13264 CASE (sem, INSN_BOUND_CW) : /* bound.w [PC+],${Rd} */ 13265{ 13266 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13267 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13268#define FLD(f) abuf->fields.sfmt_bound_cw.f 13269 int UNUSED written = 0; 13270 IADDR UNUSED pc = abuf->addr; 13271 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 13272 13273{ 13274 SI tmp_tmpopd; 13275 SI tmp_tmpops; 13276 SI tmp_newval; 13277 tmp_tmpops = ZEXTSISI (FLD (f_indir_pc__word)); 13278 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 13279 tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd)); 13280 { 13281 SI opval = tmp_newval; 13282 SET_H_GR (FLD (f_operand2), opval); 13283 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 13284 } 13285{ 13286 { 13287 BI opval = LTSI (tmp_newval, 0); 13288 CPU (h_nbit) = opval; 13289 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 13290 } 13291 { 13292 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 13293 CPU (h_zbit) = opval; 13294 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 13295 } 13296SET_H_CBIT_MOVE (0); 13297SET_H_VBIT_MOVE (0); 13298{ 13299 { 13300 BI opval = 0; 13301 CPU (h_xbit) = opval; 13302 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 13303 } 13304 { 13305 BI opval = 0; 13306 SET_H_INSN_PREFIXED_P (opval); 13307 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13308 } 13309} 13310} 13311} 13312 13313#undef FLD 13314} 13315 NEXT (vpc); 13316 13317 CASE (sem, INSN_BOUND_CD) : /* bound.d [PC+],${Rd} */ 13318{ 13319 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13320 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13321#define FLD(f) abuf->fields.sfmt_bound_cd.f 13322 int UNUSED written = 0; 13323 IADDR UNUSED pc = abuf->addr; 13324 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 13325 13326{ 13327 SI tmp_tmpopd; 13328 SI tmp_tmpops; 13329 SI tmp_newval; 13330 tmp_tmpops = FLD (f_indir_pc__dword); 13331 tmp_tmpopd = GET_H_GR (FLD (f_operand2)); 13332 tmp_newval = ((LTUSI (tmp_tmpops, tmp_tmpopd)) ? (tmp_tmpops) : (tmp_tmpopd)); 13333 { 13334 SI opval = tmp_newval; 13335 SET_H_GR (FLD (f_operand2), opval); 13336 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 13337 } 13338{ 13339 { 13340 BI opval = LTSI (tmp_newval, 0); 13341 CPU (h_nbit) = opval; 13342 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 13343 } 13344 { 13345 BI opval = ANDIF (EQSI (tmp_newval, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 13346 CPU (h_zbit) = opval; 13347 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 13348 } 13349SET_H_CBIT_MOVE (0); 13350SET_H_VBIT_MOVE (0); 13351{ 13352 { 13353 BI opval = 0; 13354 CPU (h_xbit) = opval; 13355 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 13356 } 13357 { 13358 BI opval = 0; 13359 SET_H_INSN_PREFIXED_P (opval); 13360 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13361 } 13362} 13363} 13364} 13365 13366#undef FLD 13367} 13368 NEXT (vpc); 13369 13370 CASE (sem, INSN_SCC) : /* s${cc} ${Rd-sfield} */ 13371{ 13372 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13373 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13374#define FLD(f) abuf->fields.sfmt_move_spr_mv32.f 13375 int UNUSED written = 0; 13376 IADDR UNUSED pc = abuf->addr; 13377 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 13378 13379{ 13380 BI tmp_truthval; 13381 tmp_truthval = ({ SI tmp_tmpcond; 13382 BI tmp_condres; 13383 tmp_tmpcond = FLD (f_operand2); 13384; if (EQSI (tmp_tmpcond, 0)) { 13385 tmp_condres = NOTBI (CPU (h_cbit)); 13386} 13387 else if (EQSI (tmp_tmpcond, 1)) { 13388 tmp_condres = CPU (h_cbit); 13389} 13390 else if (EQSI (tmp_tmpcond, 2)) { 13391 tmp_condres = NOTBI (CPU (h_zbit)); 13392} 13393 else if (EQSI (tmp_tmpcond, 3)) { 13394 tmp_condres = CPU (h_zbit); 13395} 13396 else if (EQSI (tmp_tmpcond, 4)) { 13397 tmp_condres = NOTBI (CPU (h_vbit)); 13398} 13399 else if (EQSI (tmp_tmpcond, 5)) { 13400 tmp_condres = CPU (h_vbit); 13401} 13402 else if (EQSI (tmp_tmpcond, 6)) { 13403 tmp_condres = NOTBI (CPU (h_nbit)); 13404} 13405 else if (EQSI (tmp_tmpcond, 7)) { 13406 tmp_condres = CPU (h_nbit); 13407} 13408 else if (EQSI (tmp_tmpcond, 8)) { 13409 tmp_condres = ORBI (CPU (h_cbit), CPU (h_zbit)); 13410} 13411 else if (EQSI (tmp_tmpcond, 9)) { 13412 tmp_condres = NOTBI (ORBI (CPU (h_cbit), CPU (h_zbit))); 13413} 13414 else if (EQSI (tmp_tmpcond, 10)) { 13415 tmp_condres = NOTBI (XORBI (CPU (h_vbit), CPU (h_nbit))); 13416} 13417 else if (EQSI (tmp_tmpcond, 11)) { 13418 tmp_condres = XORBI (CPU (h_vbit), CPU (h_nbit)); 13419} 13420 else if (EQSI (tmp_tmpcond, 12)) { 13421 tmp_condres = NOTBI (ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit))); 13422} 13423 else if (EQSI (tmp_tmpcond, 13)) { 13424 tmp_condres = ORBI (XORBI (CPU (h_vbit), CPU (h_nbit)), CPU (h_zbit)); 13425} 13426 else if (EQSI (tmp_tmpcond, 14)) { 13427 tmp_condres = 1; 13428} 13429 else if (EQSI (tmp_tmpcond, 15)) { 13430 tmp_condres = CPU (h_pbit); 13431} 13432; tmp_condres; }); 13433 { 13434 SI opval = ZEXTBISI (tmp_truthval); 13435 SET_H_GR (FLD (f_operand1), opval); 13436 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 13437 } 13438{ 13439 { 13440 BI opval = 0; 13441 CPU (h_xbit) = opval; 13442 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 13443 } 13444 { 13445 BI opval = 0; 13446 SET_H_INSN_PREFIXED_P (opval); 13447 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13448 } 13449} 13450} 13451 13452#undef FLD 13453} 13454 NEXT (vpc); 13455 13456 CASE (sem, INSN_LZ) : /* lz ${Rs},${Rd} */ 13457{ 13458 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13459 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13460#define FLD(f) abuf->fields.sfmt_muls_b.f 13461 int UNUSED written = 0; 13462 IADDR UNUSED pc = abuf->addr; 13463 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 13464 13465{ 13466 SI tmp_tmpd; 13467 SI tmp_tmp; 13468 tmp_tmp = GET_H_GR (FLD (f_operand1)); 13469 tmp_tmpd = 0; 13470{ 13471if (GESI (tmp_tmp, 0)) { 13472{ 13473 tmp_tmp = SLLSI (tmp_tmp, 1); 13474 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13475} 13476} 13477if (GESI (tmp_tmp, 0)) { 13478{ 13479 tmp_tmp = SLLSI (tmp_tmp, 1); 13480 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13481} 13482} 13483if (GESI (tmp_tmp, 0)) { 13484{ 13485 tmp_tmp = SLLSI (tmp_tmp, 1); 13486 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13487} 13488} 13489if (GESI (tmp_tmp, 0)) { 13490{ 13491 tmp_tmp = SLLSI (tmp_tmp, 1); 13492 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13493} 13494} 13495if (GESI (tmp_tmp, 0)) { 13496{ 13497 tmp_tmp = SLLSI (tmp_tmp, 1); 13498 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13499} 13500} 13501if (GESI (tmp_tmp, 0)) { 13502{ 13503 tmp_tmp = SLLSI (tmp_tmp, 1); 13504 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13505} 13506} 13507if (GESI (tmp_tmp, 0)) { 13508{ 13509 tmp_tmp = SLLSI (tmp_tmp, 1); 13510 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13511} 13512} 13513if (GESI (tmp_tmp, 0)) { 13514{ 13515 tmp_tmp = SLLSI (tmp_tmp, 1); 13516 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13517} 13518} 13519if (GESI (tmp_tmp, 0)) { 13520{ 13521 tmp_tmp = SLLSI (tmp_tmp, 1); 13522 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13523} 13524} 13525if (GESI (tmp_tmp, 0)) { 13526{ 13527 tmp_tmp = SLLSI (tmp_tmp, 1); 13528 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13529} 13530} 13531if (GESI (tmp_tmp, 0)) { 13532{ 13533 tmp_tmp = SLLSI (tmp_tmp, 1); 13534 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13535} 13536} 13537if (GESI (tmp_tmp, 0)) { 13538{ 13539 tmp_tmp = SLLSI (tmp_tmp, 1); 13540 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13541} 13542} 13543if (GESI (tmp_tmp, 0)) { 13544{ 13545 tmp_tmp = SLLSI (tmp_tmp, 1); 13546 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13547} 13548} 13549if (GESI (tmp_tmp, 0)) { 13550{ 13551 tmp_tmp = SLLSI (tmp_tmp, 1); 13552 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13553} 13554} 13555if (GESI (tmp_tmp, 0)) { 13556{ 13557 tmp_tmp = SLLSI (tmp_tmp, 1); 13558 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13559} 13560} 13561if (GESI (tmp_tmp, 0)) { 13562{ 13563 tmp_tmp = SLLSI (tmp_tmp, 1); 13564 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13565} 13566} 13567if (GESI (tmp_tmp, 0)) { 13568{ 13569 tmp_tmp = SLLSI (tmp_tmp, 1); 13570 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13571} 13572} 13573if (GESI (tmp_tmp, 0)) { 13574{ 13575 tmp_tmp = SLLSI (tmp_tmp, 1); 13576 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13577} 13578} 13579if (GESI (tmp_tmp, 0)) { 13580{ 13581 tmp_tmp = SLLSI (tmp_tmp, 1); 13582 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13583} 13584} 13585if (GESI (tmp_tmp, 0)) { 13586{ 13587 tmp_tmp = SLLSI (tmp_tmp, 1); 13588 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13589} 13590} 13591if (GESI (tmp_tmp, 0)) { 13592{ 13593 tmp_tmp = SLLSI (tmp_tmp, 1); 13594 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13595} 13596} 13597if (GESI (tmp_tmp, 0)) { 13598{ 13599 tmp_tmp = SLLSI (tmp_tmp, 1); 13600 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13601} 13602} 13603if (GESI (tmp_tmp, 0)) { 13604{ 13605 tmp_tmp = SLLSI (tmp_tmp, 1); 13606 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13607} 13608} 13609if (GESI (tmp_tmp, 0)) { 13610{ 13611 tmp_tmp = SLLSI (tmp_tmp, 1); 13612 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13613} 13614} 13615if (GESI (tmp_tmp, 0)) { 13616{ 13617 tmp_tmp = SLLSI (tmp_tmp, 1); 13618 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13619} 13620} 13621if (GESI (tmp_tmp, 0)) { 13622{ 13623 tmp_tmp = SLLSI (tmp_tmp, 1); 13624 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13625} 13626} 13627if (GESI (tmp_tmp, 0)) { 13628{ 13629 tmp_tmp = SLLSI (tmp_tmp, 1); 13630 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13631} 13632} 13633if (GESI (tmp_tmp, 0)) { 13634{ 13635 tmp_tmp = SLLSI (tmp_tmp, 1); 13636 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13637} 13638} 13639if (GESI (tmp_tmp, 0)) { 13640{ 13641 tmp_tmp = SLLSI (tmp_tmp, 1); 13642 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13643} 13644} 13645if (GESI (tmp_tmp, 0)) { 13646{ 13647 tmp_tmp = SLLSI (tmp_tmp, 1); 13648 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13649} 13650} 13651if (GESI (tmp_tmp, 0)) { 13652{ 13653 tmp_tmp = SLLSI (tmp_tmp, 1); 13654 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13655} 13656} 13657if (GESI (tmp_tmp, 0)) { 13658{ 13659 tmp_tmp = SLLSI (tmp_tmp, 1); 13660 tmp_tmpd = ADDSI (tmp_tmpd, 1); 13661} 13662} 13663} 13664 { 13665 SI opval = tmp_tmpd; 13666 SET_H_GR (FLD (f_operand2), opval); 13667 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 13668 } 13669{ 13670 { 13671 BI opval = LTSI (tmp_tmpd, 0); 13672 CPU (h_nbit) = opval; 13673 TRACE_RESULT (current_cpu, abuf, "nbit", 'x', opval); 13674 } 13675 { 13676 BI opval = ANDIF (EQSI (tmp_tmpd, 0), ((CPU (h_xbit)) ? (CPU (h_zbit)) : (1))); 13677 CPU (h_zbit) = opval; 13678 TRACE_RESULT (current_cpu, abuf, "zbit", 'x', opval); 13679 } 13680SET_H_CBIT_MOVE (0); 13681SET_H_VBIT_MOVE (0); 13682{ 13683 { 13684 BI opval = 0; 13685 CPU (h_xbit) = opval; 13686 TRACE_RESULT (current_cpu, abuf, "xbit", 'x', opval); 13687 } 13688 { 13689 BI opval = 0; 13690 SET_H_INSN_PREFIXED_P (opval); 13691 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13692 } 13693} 13694} 13695} 13696 13697#undef FLD 13698} 13699 NEXT (vpc); 13700 13701 CASE (sem, INSN_ADDOQ) : /* addoq $o,$Rs,ACR */ 13702{ 13703 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13704 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13705#define FLD(f) abuf->fields.sfmt_addoq.f 13706 int UNUSED written = 0; 13707 IADDR UNUSED pc = abuf->addr; 13708 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 13709 13710{ 13711 { 13712 SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_s8)); 13713 SET_H_PREFIXREG_V32 (opval); 13714 TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval); 13715 } 13716 { 13717 BI opval = 1; 13718 SET_H_INSN_PREFIXED_P (opval); 13719 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13720 } 13721} 13722 13723#undef FLD 13724} 13725 NEXT (vpc); 13726 13727 CASE (sem, INSN_ADDO_M_B_M) : /* addo-m.b [${Rs}${inc}],$Rd,ACR */ 13728{ 13729 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13730 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13731#define FLD(f) abuf->fields.sfmt_addc_m.f 13732 int UNUSED written = 0; 13733 IADDR UNUSED pc = abuf->addr; 13734 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 13735 13736{ 13737 QI tmp_tmps; 13738 tmp_tmps = ({ SI tmp_addr; 13739 QI tmp_tmp_mem; 13740 BI tmp_postinc; 13741 tmp_postinc = FLD (f_memmode); 13742; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 13743; tmp_tmp_mem = GETMEMQI (current_cpu, pc, tmp_addr); 13744; if (NEBI (tmp_postinc, 0)) { 13745{ 13746if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 13747 tmp_addr = ADDSI (tmp_addr, 1); 13748} 13749 { 13750 SI opval = tmp_addr; 13751 SET_H_GR (FLD (f_operand1), opval); 13752 written |= (1 << 6); 13753 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 13754 } 13755} 13756} 13757; tmp_tmp_mem; }); 13758 { 13759 SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (tmp_tmps)); 13760 SET_H_PREFIXREG_V32 (opval); 13761 TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval); 13762 } 13763 { 13764 BI opval = 1; 13765 SET_H_INSN_PREFIXED_P (opval); 13766 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13767 } 13768} 13769 13770 abuf->written = written; 13771#undef FLD 13772} 13773 NEXT (vpc); 13774 13775 CASE (sem, INSN_ADDO_M_W_M) : /* addo-m.w [${Rs}${inc}],$Rd,ACR */ 13776{ 13777 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13778 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13779#define FLD(f) abuf->fields.sfmt_addc_m.f 13780 int UNUSED written = 0; 13781 IADDR UNUSED pc = abuf->addr; 13782 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 13783 13784{ 13785 HI tmp_tmps; 13786 tmp_tmps = ({ SI tmp_addr; 13787 HI tmp_tmp_mem; 13788 BI tmp_postinc; 13789 tmp_postinc = FLD (f_memmode); 13790; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 13791; tmp_tmp_mem = GETMEMHI (current_cpu, pc, tmp_addr); 13792; if (NEBI (tmp_postinc, 0)) { 13793{ 13794if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 13795 tmp_addr = ADDSI (tmp_addr, 2); 13796} 13797 { 13798 SI opval = tmp_addr; 13799 SET_H_GR (FLD (f_operand1), opval); 13800 written |= (1 << 6); 13801 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 13802 } 13803} 13804} 13805; tmp_tmp_mem; }); 13806 { 13807 SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (tmp_tmps)); 13808 SET_H_PREFIXREG_V32 (opval); 13809 TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval); 13810 } 13811 { 13812 BI opval = 1; 13813 SET_H_INSN_PREFIXED_P (opval); 13814 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13815 } 13816} 13817 13818 abuf->written = written; 13819#undef FLD 13820} 13821 NEXT (vpc); 13822 13823 CASE (sem, INSN_ADDO_M_D_M) : /* addo-m.d [${Rs}${inc}],$Rd,ACR */ 13824{ 13825 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13826 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13827#define FLD(f) abuf->fields.sfmt_addc_m.f 13828 int UNUSED written = 0; 13829 IADDR UNUSED pc = abuf->addr; 13830 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 13831 13832{ 13833 SI tmp_tmps; 13834 tmp_tmps = ({ SI tmp_addr; 13835 SI tmp_tmp_mem; 13836 BI tmp_postinc; 13837 tmp_postinc = FLD (f_memmode); 13838; tmp_addr = ((EQBI (GET_H_INSN_PREFIXED_P (), 0)) ? (GET_H_GR (FLD (f_operand1))) : (GET_H_PREFIXREG_V32 ())); 13839; tmp_tmp_mem = GETMEMSI (current_cpu, pc, tmp_addr); 13840; if (NEBI (tmp_postinc, 0)) { 13841{ 13842if (EQBI (GET_H_INSN_PREFIXED_P (), 0)) { 13843 tmp_addr = ADDSI (tmp_addr, 4); 13844} 13845 { 13846 SI opval = tmp_addr; 13847 SET_H_GR (FLD (f_operand1), opval); 13848 written |= (1 << 6); 13849 TRACE_RESULT (current_cpu, abuf, "gr", 'x', opval); 13850 } 13851} 13852} 13853; tmp_tmp_mem; }); 13854 { 13855 SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), tmp_tmps); 13856 SET_H_PREFIXREG_V32 (opval); 13857 TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval); 13858 } 13859 { 13860 BI opval = 1; 13861 SET_H_INSN_PREFIXED_P (opval); 13862 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13863 } 13864} 13865 13866 abuf->written = written; 13867#undef FLD 13868} 13869 NEXT (vpc); 13870 13871 CASE (sem, INSN_ADDO_CB) : /* addo.b [PC+],$Rd,ACR */ 13872{ 13873 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13874 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13875#define FLD(f) abuf->fields.sfmt_bound_cb.f 13876 int UNUSED written = 0; 13877 IADDR UNUSED pc = abuf->addr; 13878 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 13879 13880{ 13881 { 13882 SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTQISI (TRUNCSIQI (FLD (f_indir_pc__byte)))); 13883 SET_H_PREFIXREG_V32 (opval); 13884 TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval); 13885 } 13886 { 13887 BI opval = 1; 13888 SET_H_INSN_PREFIXED_P (opval); 13889 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13890 } 13891} 13892 13893#undef FLD 13894} 13895 NEXT (vpc); 13896 13897 CASE (sem, INSN_ADDO_CW) : /* addo.w [PC+],$Rd,ACR */ 13898{ 13899 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13900 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13901#define FLD(f) abuf->fields.sfmt_bound_cw.f 13902 int UNUSED written = 0; 13903 IADDR UNUSED pc = abuf->addr; 13904 vpc = SEM_NEXT_VPC (sem_arg, pc, 4); 13905 13906{ 13907 { 13908 SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), EXTHISI (TRUNCSIHI (FLD (f_indir_pc__word)))); 13909 SET_H_PREFIXREG_V32 (opval); 13910 TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval); 13911 } 13912 { 13913 BI opval = 1; 13914 SET_H_INSN_PREFIXED_P (opval); 13915 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13916 } 13917} 13918 13919#undef FLD 13920} 13921 NEXT (vpc); 13922 13923 CASE (sem, INSN_ADDO_CD) : /* addo.d [PC+],$Rd,ACR */ 13924{ 13925 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13926 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13927#define FLD(f) abuf->fields.sfmt_bound_cd.f 13928 int UNUSED written = 0; 13929 IADDR UNUSED pc = abuf->addr; 13930 vpc = SEM_NEXT_VPC (sem_arg, pc, 6); 13931 13932{ 13933 { 13934 SI opval = ADDSI (GET_H_GR (FLD (f_operand2)), FLD (f_indir_pc__dword)); 13935 SET_H_PREFIXREG_V32 (opval); 13936 TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval); 13937 } 13938 { 13939 BI opval = 1; 13940 SET_H_INSN_PREFIXED_P (opval); 13941 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13942 } 13943} 13944 13945#undef FLD 13946} 13947 NEXT (vpc); 13948 13949 CASE (sem, INSN_ADDI_ACR_B_R) : /* addi-acr.b ${Rs-dfield}.m,${Rd-sfield},ACR */ 13950{ 13951 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13952 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13953#define FLD(f) abuf->fields.sfmt_muls_b.f 13954 int UNUSED written = 0; 13955 IADDR UNUSED pc = abuf->addr; 13956 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 13957 13958{ 13959 { 13960 SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 1)); 13961 SET_H_PREFIXREG_V32 (opval); 13962 TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval); 13963 } 13964 { 13965 BI opval = 1; 13966 SET_H_INSN_PREFIXED_P (opval); 13967 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13968 } 13969} 13970 13971#undef FLD 13972} 13973 NEXT (vpc); 13974 13975 CASE (sem, INSN_ADDI_ACR_W_R) : /* addi-acr.w ${Rs-dfield}.m,${Rd-sfield},ACR */ 13976{ 13977 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 13978 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 13979#define FLD(f) abuf->fields.sfmt_muls_b.f 13980 int UNUSED written = 0; 13981 IADDR UNUSED pc = abuf->addr; 13982 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 13983 13984{ 13985 { 13986 SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 2)); 13987 SET_H_PREFIXREG_V32 (opval); 13988 TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval); 13989 } 13990 { 13991 BI opval = 1; 13992 SET_H_INSN_PREFIXED_P (opval); 13993 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 13994 } 13995} 13996 13997#undef FLD 13998} 13999 NEXT (vpc); 14000 14001 CASE (sem, INSN_ADDI_ACR_D_R) : /* addi-acr.d ${Rs-dfield}.m,${Rd-sfield},ACR */ 14002{ 14003 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 14004 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 14005#define FLD(f) abuf->fields.sfmt_muls_b.f 14006 int UNUSED written = 0; 14007 IADDR UNUSED pc = abuf->addr; 14008 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 14009 14010{ 14011 { 14012 SI opval = ADDSI (GET_H_GR (FLD (f_operand1)), MULSI (GET_H_GR (FLD (f_operand2)), 4)); 14013 SET_H_PREFIXREG_V32 (opval); 14014 TRACE_RESULT (current_cpu, abuf, "prefixreg", 'x', opval); 14015 } 14016 { 14017 BI opval = 1; 14018 SET_H_INSN_PREFIXED_P (opval); 14019 TRACE_RESULT (current_cpu, abuf, "insn-prefixed-p", 'x', opval); 14020 } 14021} 14022 14023#undef FLD 14024} 14025 NEXT (vpc); 14026 14027 CASE (sem, INSN_FIDXI) : /* fidxi [$Rs] */ 14028{ 14029 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 14030 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 14031#define FLD(f) abuf->fields.sfmt_mcp.f 14032 int UNUSED written = 0; 14033 IADDR UNUSED pc = abuf->addr; 14034 SEM_BRANCH_INIT 14035 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 14036 14037 { 14038 USI opval = crisv32f_fidxi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1))); 14039 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 14040 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 14041 } 14042 14043 SEM_BRANCH_FINI (vpc); 14044#undef FLD 14045} 14046 NEXT (vpc); 14047 14048 CASE (sem, INSN_FTAGI) : /* fidxi [$Rs] */ 14049{ 14050 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 14051 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 14052#define FLD(f) abuf->fields.sfmt_mcp.f 14053 int UNUSED written = 0; 14054 IADDR UNUSED pc = abuf->addr; 14055 SEM_BRANCH_INIT 14056 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 14057 14058 { 14059 USI opval = crisv32f_ftagi_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1))); 14060 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 14061 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 14062 } 14063 14064 SEM_BRANCH_FINI (vpc); 14065#undef FLD 14066} 14067 NEXT (vpc); 14068 14069 CASE (sem, INSN_FIDXD) : /* fidxd [$Rs] */ 14070{ 14071 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 14072 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 14073#define FLD(f) abuf->fields.sfmt_mcp.f 14074 int UNUSED written = 0; 14075 IADDR UNUSED pc = abuf->addr; 14076 SEM_BRANCH_INIT 14077 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 14078 14079 { 14080 USI opval = crisv32f_fidxd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1))); 14081 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 14082 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 14083 } 14084 14085 SEM_BRANCH_FINI (vpc); 14086#undef FLD 14087} 14088 NEXT (vpc); 14089 14090 CASE (sem, INSN_FTAGD) : /* ftagd [$Rs] */ 14091{ 14092 SEM_ARG sem_arg = SEM_SEM_ARG (vpc, sc); 14093 ARGBUF *abuf = SEM_ARGBUF (sem_arg); 14094#define FLD(f) abuf->fields.sfmt_mcp.f 14095 int UNUSED written = 0; 14096 IADDR UNUSED pc = abuf->addr; 14097 SEM_BRANCH_INIT 14098 vpc = SEM_NEXT_VPC (sem_arg, pc, 2); 14099 14100 { 14101 USI opval = crisv32f_ftagd_handler (current_cpu, pc, GET_H_GR (FLD (f_operand1))); 14102 SEM_BRANCH_VIA_ADDR (current_cpu, sem_arg, opval, vpc); 14103 TRACE_RESULT (current_cpu, abuf, "pc", 'x', opval); 14104 } 14105 14106 SEM_BRANCH_FINI (vpc); 14107#undef FLD 14108} 14109 NEXT (vpc); 14110 14111 14112 } 14113 ENDSWITCH (sem) /* End of semantic switch. */ 14114 14115 /* At this point `vpc' contains the next insn to execute. */ 14116} 14117 14118#undef DEFINE_SWITCH 14119#endif /* DEFINE_SWITCH */ 14120