1/* Disassembler interface for targets using CGEN. -*- C -*- 2 CGEN: Cpu tools GENerator 3 4 THIS FILE IS MACHINE GENERATED WITH CGEN. 5 - the resultant file is machine generated, cgen-dis.in isn't 6 7 Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2005, 2007 8 Free Software Foundation, Inc. 9 10 This file is part of libopcodes. 11 12 This library is free software; you can redistribute it and/or modify 13 it under the terms of the GNU General Public License as published by 14 the Free Software Foundation; either version 3, or (at your option) 15 any later version. 16 17 It is distributed in the hope that it will be useful, but WITHOUT 18 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 19 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 20 License for more details. 21 22 You should have received a copy of the GNU General Public License 23 along with this program; if not, write to the Free Software Foundation, Inc., 24 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ 25 26/* ??? Eventually more and more of this stuff can go to cpu-independent files. 27 Keep that in mind. */ 28 29#include "sysdep.h" 30#include <stdio.h> 31#include "ansidecl.h" 32#include "dis-asm.h" 33#include "bfd.h" 34#include "symcat.h" 35#include "libiberty.h" 36#include "xstormy16-desc.h" 37#include "xstormy16-opc.h" 38#include "opintl.h" 39 40/* Default text to print if an instruction isn't recognized. */ 41#define UNKNOWN_INSN_MSG _("*unknown*") 42 43static void print_normal 44 (CGEN_CPU_DESC, void *, long, unsigned int, bfd_vma, int); 45static void print_address 46 (CGEN_CPU_DESC, void *, bfd_vma, unsigned int, bfd_vma, int) ATTRIBUTE_UNUSED; 47static void print_keyword 48 (CGEN_CPU_DESC, void *, CGEN_KEYWORD *, long, unsigned int) ATTRIBUTE_UNUSED; 49static void print_insn_normal 50 (CGEN_CPU_DESC, void *, const CGEN_INSN *, CGEN_FIELDS *, bfd_vma, int); 51static int print_insn 52 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, unsigned); 53static int default_print_insn 54 (CGEN_CPU_DESC, bfd_vma, disassemble_info *) ATTRIBUTE_UNUSED; 55static int read_insn 56 (CGEN_CPU_DESC, bfd_vma, disassemble_info *, bfd_byte *, int, CGEN_EXTRACT_INFO *, 57 unsigned long *); 58 59/* -- disassembler routines inserted here. */ 60 61 62void xstormy16_cgen_print_operand 63 (CGEN_CPU_DESC, int, PTR, CGEN_FIELDS *, void const *, bfd_vma, int); 64 65/* Main entry point for printing operands. 66 XINFO is a `void *' and not a `disassemble_info *' to not put a requirement 67 of dis-asm.h on cgen.h. 68 69 This function is basically just a big switch statement. Earlier versions 70 used tables to look up the function to use, but 71 - if the table contains both assembler and disassembler functions then 72 the disassembler contains much of the assembler and vice-versa, 73 - there's a lot of inlining possibilities as things grow, 74 - using a switch statement avoids the function call overhead. 75 76 This function could be moved into `print_insn_normal', but keeping it 77 separate makes clear the interface between `print_insn_normal' and each of 78 the handlers. */ 79 80void 81xstormy16_cgen_print_operand (CGEN_CPU_DESC cd, 82 int opindex, 83 void * xinfo, 84 CGEN_FIELDS *fields, 85 void const *attrs ATTRIBUTE_UNUSED, 86 bfd_vma pc, 87 int length) 88{ 89 disassemble_info *info = (disassemble_info *) xinfo; 90 91 switch (opindex) 92 { 93 case XSTORMY16_OPERAND_RB : 94 print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rb, 0); 95 break; 96 case XSTORMY16_OPERAND_RBJ : 97 print_keyword (cd, info, & xstormy16_cgen_opval_gr_Rb_names, fields->f_Rbj, 0); 98 break; 99 case XSTORMY16_OPERAND_RD : 100 print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rd, 0); 101 break; 102 case XSTORMY16_OPERAND_RDM : 103 print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rdm, 0); 104 break; 105 case XSTORMY16_OPERAND_RM : 106 print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rm, 0); 107 break; 108 case XSTORMY16_OPERAND_RS : 109 print_keyword (cd, info, & xstormy16_cgen_opval_gr_names, fields->f_Rs, 0); 110 break; 111 case XSTORMY16_OPERAND_ABS24 : 112 print_normal (cd, info, fields->f_abs24, 0|(1<<CGEN_OPERAND_ABS_ADDR)|(1<<CGEN_OPERAND_VIRTUAL), pc, length); 113 break; 114 case XSTORMY16_OPERAND_BCOND2 : 115 print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op2, 0); 116 break; 117 case XSTORMY16_OPERAND_BCOND5 : 118 print_keyword (cd, info, & xstormy16_cgen_opval_h_branchcond, fields->f_op5, 0); 119 break; 120 case XSTORMY16_OPERAND_HMEM8 : 121 print_normal (cd, info, fields->f_hmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); 122 break; 123 case XSTORMY16_OPERAND_IMM12 : 124 print_normal (cd, info, fields->f_imm12, 0|(1<<CGEN_OPERAND_SIGNED), pc, length); 125 break; 126 case XSTORMY16_OPERAND_IMM16 : 127 print_normal (cd, info, fields->f_imm16, 0|(1<<CGEN_OPERAND_SIGN_OPT), pc, length); 128 break; 129 case XSTORMY16_OPERAND_IMM2 : 130 print_normal (cd, info, fields->f_imm2, 0, pc, length); 131 break; 132 case XSTORMY16_OPERAND_IMM3 : 133 print_normal (cd, info, fields->f_imm3, 0, pc, length); 134 break; 135 case XSTORMY16_OPERAND_IMM3B : 136 print_normal (cd, info, fields->f_imm3b, 0, pc, length); 137 break; 138 case XSTORMY16_OPERAND_IMM4 : 139 print_normal (cd, info, fields->f_imm4, 0, pc, length); 140 break; 141 case XSTORMY16_OPERAND_IMM8 : 142 print_normal (cd, info, fields->f_imm8, 0, pc, length); 143 break; 144 case XSTORMY16_OPERAND_IMM8SMALL : 145 print_normal (cd, info, fields->f_imm8, 0, pc, length); 146 break; 147 case XSTORMY16_OPERAND_LMEM8 : 148 print_normal (cd, info, fields->f_lmem8, 0|(1<<CGEN_OPERAND_ABS_ADDR), pc, length); 149 break; 150 case XSTORMY16_OPERAND_REL12 : 151 print_normal (cd, info, fields->f_rel12, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 152 break; 153 case XSTORMY16_OPERAND_REL12A : 154 print_normal (cd, info, fields->f_rel12a, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 155 break; 156 case XSTORMY16_OPERAND_REL8_2 : 157 print_normal (cd, info, fields->f_rel8_2, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 158 break; 159 case XSTORMY16_OPERAND_REL8_4 : 160 print_normal (cd, info, fields->f_rel8_4, 0|(1<<CGEN_OPERAND_PCREL_ADDR), pc, length); 161 break; 162 case XSTORMY16_OPERAND_WS2 : 163 print_keyword (cd, info, & xstormy16_cgen_opval_h_wordsize, fields->f_op2m, 0); 164 break; 165 166 default : 167 /* xgettext:c-format */ 168 fprintf (stderr, _("Unrecognized field %d while printing insn.\n"), 169 opindex); 170 abort (); 171 } 172} 173 174cgen_print_fn * const xstormy16_cgen_print_handlers[] = 175{ 176 print_insn_normal, 177}; 178 179 180void 181xstormy16_cgen_init_dis (CGEN_CPU_DESC cd) 182{ 183 xstormy16_cgen_init_opcode_table (cd); 184 xstormy16_cgen_init_ibld_table (cd); 185 cd->print_handlers = & xstormy16_cgen_print_handlers[0]; 186 cd->print_operand = xstormy16_cgen_print_operand; 187} 188 189 190/* Default print handler. */ 191 192static void 193print_normal (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 194 void *dis_info, 195 long value, 196 unsigned int attrs, 197 bfd_vma pc ATTRIBUTE_UNUSED, 198 int length ATTRIBUTE_UNUSED) 199{ 200 disassemble_info *info = (disassemble_info *) dis_info; 201 202#ifdef CGEN_PRINT_NORMAL 203 CGEN_PRINT_NORMAL (cd, info, value, attrs, pc, length); 204#endif 205 206 /* Print the operand as directed by the attributes. */ 207 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 208 ; /* nothing to do */ 209 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 210 (*info->fprintf_func) (info->stream, "%ld", value); 211 else 212 (*info->fprintf_func) (info->stream, "0x%lx", value); 213} 214 215/* Default address handler. */ 216 217static void 218print_address (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 219 void *dis_info, 220 bfd_vma value, 221 unsigned int attrs, 222 bfd_vma pc ATTRIBUTE_UNUSED, 223 int length ATTRIBUTE_UNUSED) 224{ 225 disassemble_info *info = (disassemble_info *) dis_info; 226 227#ifdef CGEN_PRINT_ADDRESS 228 CGEN_PRINT_ADDRESS (cd, info, value, attrs, pc, length); 229#endif 230 231 /* Print the operand as directed by the attributes. */ 232 if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SEM_ONLY)) 233 ; /* Nothing to do. */ 234 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_PCREL_ADDR)) 235 (*info->print_address_func) (value, info); 236 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_ABS_ADDR)) 237 (*info->print_address_func) (value, info); 238 else if (CGEN_BOOL_ATTR (attrs, CGEN_OPERAND_SIGNED)) 239 (*info->fprintf_func) (info->stream, "%ld", (long) value); 240 else 241 (*info->fprintf_func) (info->stream, "0x%lx", (long) value); 242} 243 244/* Keyword print handler. */ 245 246static void 247print_keyword (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 248 void *dis_info, 249 CGEN_KEYWORD *keyword_table, 250 long value, 251 unsigned int attrs ATTRIBUTE_UNUSED) 252{ 253 disassemble_info *info = (disassemble_info *) dis_info; 254 const CGEN_KEYWORD_ENTRY *ke; 255 256 ke = cgen_keyword_lookup_value (keyword_table, value); 257 if (ke != NULL) 258 (*info->fprintf_func) (info->stream, "%s", ke->name); 259 else 260 (*info->fprintf_func) (info->stream, "???"); 261} 262 263/* Default insn printer. 264 265 DIS_INFO is defined as `void *' so the disassembler needn't know anything 266 about disassemble_info. */ 267 268static void 269print_insn_normal (CGEN_CPU_DESC cd, 270 void *dis_info, 271 const CGEN_INSN *insn, 272 CGEN_FIELDS *fields, 273 bfd_vma pc, 274 int length) 275{ 276 const CGEN_SYNTAX *syntax = CGEN_INSN_SYNTAX (insn); 277 disassemble_info *info = (disassemble_info *) dis_info; 278 const CGEN_SYNTAX_CHAR_TYPE *syn; 279 280 CGEN_INIT_PRINT (cd); 281 282 for (syn = CGEN_SYNTAX_STRING (syntax); *syn; ++syn) 283 { 284 if (CGEN_SYNTAX_MNEMONIC_P (*syn)) 285 { 286 (*info->fprintf_func) (info->stream, "%s", CGEN_INSN_MNEMONIC (insn)); 287 continue; 288 } 289 if (CGEN_SYNTAX_CHAR_P (*syn)) 290 { 291 (*info->fprintf_func) (info->stream, "%c", CGEN_SYNTAX_CHAR (*syn)); 292 continue; 293 } 294 295 /* We have an operand. */ 296 xstormy16_cgen_print_operand (cd, CGEN_SYNTAX_FIELD (*syn), info, 297 fields, CGEN_INSN_ATTRS (insn), pc, length); 298 } 299} 300 301/* Subroutine of print_insn. Reads an insn into the given buffers and updates 302 the extract info. 303 Returns 0 if all is well, non-zero otherwise. */ 304 305static int 306read_insn (CGEN_CPU_DESC cd ATTRIBUTE_UNUSED, 307 bfd_vma pc, 308 disassemble_info *info, 309 bfd_byte *buf, 310 int buflen, 311 CGEN_EXTRACT_INFO *ex_info, 312 unsigned long *insn_value) 313{ 314 int status = (*info->read_memory_func) (pc, buf, buflen, info); 315 316 if (status != 0) 317 { 318 (*info->memory_error_func) (status, pc, info); 319 return -1; 320 } 321 322 ex_info->dis_info = info; 323 ex_info->valid = (1 << buflen) - 1; 324 ex_info->insn_bytes = buf; 325 326 *insn_value = bfd_get_bits (buf, buflen * 8, info->endian == BFD_ENDIAN_BIG); 327 return 0; 328} 329 330/* Utility to print an insn. 331 BUF is the base part of the insn, target byte order, BUFLEN bytes long. 332 The result is the size of the insn in bytes or zero for an unknown insn 333 or -1 if an error occurs fetching data (memory_error_func will have 334 been called). */ 335 336static int 337print_insn (CGEN_CPU_DESC cd, 338 bfd_vma pc, 339 disassemble_info *info, 340 bfd_byte *buf, 341 unsigned int buflen) 342{ 343 CGEN_INSN_INT insn_value; 344 const CGEN_INSN_LIST *insn_list; 345 CGEN_EXTRACT_INFO ex_info; 346 int basesize; 347 348 /* Extract base part of instruction, just in case CGEN_DIS_* uses it. */ 349 basesize = cd->base_insn_bitsize < buflen * 8 ? 350 cd->base_insn_bitsize : buflen * 8; 351 insn_value = cgen_get_insn_value (cd, buf, basesize); 352 353 354 /* Fill in ex_info fields like read_insn would. Don't actually call 355 read_insn, since the incoming buffer is already read (and possibly 356 modified a la m32r). */ 357 ex_info.valid = (1 << buflen) - 1; 358 ex_info.dis_info = info; 359 ex_info.insn_bytes = buf; 360 361 /* The instructions are stored in hash lists. 362 Pick the first one and keep trying until we find the right one. */ 363 364 insn_list = CGEN_DIS_LOOKUP_INSN (cd, (char *) buf, insn_value); 365 while (insn_list != NULL) 366 { 367 const CGEN_INSN *insn = insn_list->insn; 368 CGEN_FIELDS fields; 369 int length; 370 unsigned long insn_value_cropped; 371 372#ifdef CGEN_VALIDATE_INSN_SUPPORTED 373 /* Not needed as insn shouldn't be in hash lists if not supported. */ 374 /* Supported by this cpu? */ 375 if (! xstormy16_cgen_insn_supported (cd, insn)) 376 { 377 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 378 continue; 379 } 380#endif 381 382 /* Basic bit mask must be correct. */ 383 /* ??? May wish to allow target to defer this check until the extract 384 handler. */ 385 386 /* Base size may exceed this instruction's size. Extract the 387 relevant part from the buffer. */ 388 if ((unsigned) (CGEN_INSN_BITSIZE (insn) / 8) < buflen && 389 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 390 insn_value_cropped = bfd_get_bits (buf, CGEN_INSN_BITSIZE (insn), 391 info->endian == BFD_ENDIAN_BIG); 392 else 393 insn_value_cropped = insn_value; 394 395 if ((insn_value_cropped & CGEN_INSN_BASE_MASK (insn)) 396 == CGEN_INSN_BASE_VALUE (insn)) 397 { 398 /* Printing is handled in two passes. The first pass parses the 399 machine insn and extracts the fields. The second pass prints 400 them. */ 401 402 /* Make sure the entire insn is loaded into insn_value, if it 403 can fit. */ 404 if (((unsigned) CGEN_INSN_BITSIZE (insn) > cd->base_insn_bitsize) && 405 (unsigned) (CGEN_INSN_BITSIZE (insn) / 8) <= sizeof (unsigned long)) 406 { 407 unsigned long full_insn_value; 408 int rc = read_insn (cd, pc, info, buf, 409 CGEN_INSN_BITSIZE (insn) / 8, 410 & ex_info, & full_insn_value); 411 if (rc != 0) 412 return rc; 413 length = CGEN_EXTRACT_FN (cd, insn) 414 (cd, insn, &ex_info, full_insn_value, &fields, pc); 415 } 416 else 417 length = CGEN_EXTRACT_FN (cd, insn) 418 (cd, insn, &ex_info, insn_value_cropped, &fields, pc); 419 420 /* Length < 0 -> error. */ 421 if (length < 0) 422 return length; 423 if (length > 0) 424 { 425 CGEN_PRINT_FN (cd, insn) (cd, info, insn, &fields, pc, length); 426 /* Length is in bits, result is in bytes. */ 427 return length / 8; 428 } 429 } 430 431 insn_list = CGEN_DIS_NEXT_INSN (insn_list); 432 } 433 434 return 0; 435} 436 437/* Default value for CGEN_PRINT_INSN. 438 The result is the size of the insn in bytes or zero for an unknown insn 439 or -1 if an error occured fetching bytes. */ 440 441#ifndef CGEN_PRINT_INSN 442#define CGEN_PRINT_INSN default_print_insn 443#endif 444 445static int 446default_print_insn (CGEN_CPU_DESC cd, bfd_vma pc, disassemble_info *info) 447{ 448 bfd_byte buf[CGEN_MAX_INSN_SIZE]; 449 int buflen; 450 int status; 451 452 /* Attempt to read the base part of the insn. */ 453 buflen = cd->base_insn_bitsize / 8; 454 status = (*info->read_memory_func) (pc, buf, buflen, info); 455 456 /* Try again with the minimum part, if min < base. */ 457 if (status != 0 && (cd->min_insn_bitsize < cd->base_insn_bitsize)) 458 { 459 buflen = cd->min_insn_bitsize / 8; 460 status = (*info->read_memory_func) (pc, buf, buflen, info); 461 } 462 463 if (status != 0) 464 { 465 (*info->memory_error_func) (status, pc, info); 466 return -1; 467 } 468 469 return print_insn (cd, pc, info, buf, buflen); 470} 471 472/* Main entry point. 473 Print one instruction from PC on INFO->STREAM. 474 Return the size of the instruction (in bytes). */ 475 476typedef struct cpu_desc_list 477{ 478 struct cpu_desc_list *next; 479 CGEN_BITSET *isa; 480 int mach; 481 int endian; 482 CGEN_CPU_DESC cd; 483} cpu_desc_list; 484 485int 486print_insn_xstormy16 (bfd_vma pc, disassemble_info *info) 487{ 488 static cpu_desc_list *cd_list = 0; 489 cpu_desc_list *cl = 0; 490 static CGEN_CPU_DESC cd = 0; 491 static CGEN_BITSET *prev_isa; 492 static int prev_mach; 493 static int prev_endian; 494 int length; 495 CGEN_BITSET *isa; 496 int mach; 497 int endian = (info->endian == BFD_ENDIAN_BIG 498 ? CGEN_ENDIAN_BIG 499 : CGEN_ENDIAN_LITTLE); 500 enum bfd_architecture arch; 501 502 /* ??? gdb will set mach but leave the architecture as "unknown" */ 503#ifndef CGEN_BFD_ARCH 504#define CGEN_BFD_ARCH bfd_arch_xstormy16 505#endif 506 arch = info->arch; 507 if (arch == bfd_arch_unknown) 508 arch = CGEN_BFD_ARCH; 509 510 /* There's no standard way to compute the machine or isa number 511 so we leave it to the target. */ 512#ifdef CGEN_COMPUTE_MACH 513 mach = CGEN_COMPUTE_MACH (info); 514#else 515 mach = info->mach; 516#endif 517 518#ifdef CGEN_COMPUTE_ISA 519 { 520 static CGEN_BITSET *permanent_isa; 521 522 if (!permanent_isa) 523 permanent_isa = cgen_bitset_create (MAX_ISAS); 524 isa = permanent_isa; 525 cgen_bitset_clear (isa); 526 cgen_bitset_add (isa, CGEN_COMPUTE_ISA (info)); 527 } 528#else 529 isa = info->insn_sets; 530#endif 531 532 /* If we've switched cpu's, try to find a handle we've used before */ 533 if (cd 534 && (cgen_bitset_compare (isa, prev_isa) != 0 535 || mach != prev_mach 536 || endian != prev_endian)) 537 { 538 cd = 0; 539 for (cl = cd_list; cl; cl = cl->next) 540 { 541 if (cgen_bitset_compare (cl->isa, isa) == 0 && 542 cl->mach == mach && 543 cl->endian == endian) 544 { 545 cd = cl->cd; 546 prev_isa = cd->isas; 547 break; 548 } 549 } 550 } 551 552 /* If we haven't initialized yet, initialize the opcode table. */ 553 if (! cd) 554 { 555 const bfd_arch_info_type *arch_type = bfd_lookup_arch (arch, mach); 556 const char *mach_name; 557 558 if (!arch_type) 559 abort (); 560 mach_name = arch_type->printable_name; 561 562 prev_isa = cgen_bitset_copy (isa); 563 prev_mach = mach; 564 prev_endian = endian; 565 cd = xstormy16_cgen_cpu_open (CGEN_CPU_OPEN_ISAS, prev_isa, 566 CGEN_CPU_OPEN_BFDMACH, mach_name, 567 CGEN_CPU_OPEN_ENDIAN, prev_endian, 568 CGEN_CPU_OPEN_END); 569 if (!cd) 570 abort (); 571 572 /* Save this away for future reference. */ 573 cl = xmalloc (sizeof (struct cpu_desc_list)); 574 cl->cd = cd; 575 cl->isa = prev_isa; 576 cl->mach = mach; 577 cl->endian = endian; 578 cl->next = cd_list; 579 cd_list = cl; 580 581 xstormy16_cgen_init_dis (cd); 582 } 583 584 /* We try to have as much common code as possible. 585 But at this point some targets need to take over. */ 586 /* ??? Some targets may need a hook elsewhere. Try to avoid this, 587 but if not possible try to move this hook elsewhere rather than 588 have two hooks. */ 589 length = CGEN_PRINT_INSN (cd, pc, info); 590 if (length > 0) 591 return length; 592 if (length < 0) 593 return -1; 594 595 (*info->fprintf_func) (info->stream, UNKNOWN_INSN_MSG); 596 return cd->default_insn_bitsize / 8; 597} 598