1/* CPU data header for m32r. 2 3THIS FILE IS MACHINE GENERATED WITH CGEN. 4 5Copyright 1996-2007 Free Software Foundation, Inc. 6 7This file is part of the GNU Binutils and/or GDB, the GNU debugger. 8 9 This file is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3, or (at your option) 12 any later version. 13 14 It is distributed in the hope that it will be useful, but WITHOUT 15 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY 16 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public 17 License for more details. 18 19 You should have received a copy of the GNU General Public License along 20 with this program; if not, write to the Free Software Foundation, Inc., 21 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. 22 23*/ 24 25#ifndef M32R_CPU_H 26#define M32R_CPU_H 27 28#include "opcode/cgen-bitset.h" 29 30#define CGEN_ARCH m32r 31 32/* Given symbol S, return m32r_cgen_<S>. */ 33#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE) 34#define CGEN_SYM(s) m32r##_cgen_##s 35#else 36#define CGEN_SYM(s) m32r/**/_cgen_/**/s 37#endif 38 39 40/* Selected cpu families. */ 41#define HAVE_CPU_M32RBF 42#define HAVE_CPU_M32RXF 43#define HAVE_CPU_M32R2F 44 45#define CGEN_INSN_LSB0_P 0 46 47/* Minimum size of any insn (in bytes). */ 48#define CGEN_MIN_INSN_SIZE 2 49 50/* Maximum size of any insn (in bytes). */ 51#define CGEN_MAX_INSN_SIZE 4 52 53#define CGEN_INT_INSN_P 1 54 55/* Maximum number of syntax elements in an instruction. */ 56#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15 57 58/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands. 59 e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands 60 we can't hash on everything up to the space. */ 61#define CGEN_MNEMONIC_OPERANDS 62 63/* Maximum number of fields in an instruction. */ 64#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7 65 66/* Enums. */ 67 68/* Enum declaration for insn format enums. */ 69typedef enum insn_op1 { 70 OP1_0, OP1_1, OP1_2, OP1_3 71 , OP1_4, OP1_5, OP1_6, OP1_7 72 , OP1_8, OP1_9, OP1_10, OP1_11 73 , OP1_12, OP1_13, OP1_14, OP1_15 74} INSN_OP1; 75 76/* Enum declaration for op2 enums. */ 77typedef enum insn_op2 { 78 OP2_0, OP2_1, OP2_2, OP2_3 79 , OP2_4, OP2_5, OP2_6, OP2_7 80 , OP2_8, OP2_9, OP2_10, OP2_11 81 , OP2_12, OP2_13, OP2_14, OP2_15 82} INSN_OP2; 83 84/* Enum declaration for . */ 85typedef enum gr_names { 86 H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0 87 , H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4 88 , H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8 89 , H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12 90 , H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15 91} GR_NAMES; 92 93/* Enum declaration for . */ 94typedef enum cr_names { 95 H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3 96 , H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_EVB = 5 97 , H_CR_CR0 = 0, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3 98 , H_CR_CR4 = 4, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7 99 , H_CR_CR8 = 8, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11 100 , H_CR_CR12 = 12, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15 101} CR_NAMES; 102 103/* Attributes. */ 104 105/* Enum declaration for machine type selection. */ 106typedef enum mach_attr { 107 MACH_BASE, MACH_M32R, MACH_M32RX, MACH_M32R2 108 , MACH_MAX 109} MACH_ATTR; 110 111/* Enum declaration for instruction set selection. */ 112typedef enum isa_attr { 113 ISA_M32R, ISA_MAX 114} ISA_ATTR; 115 116/* Enum declaration for parallel execution pipeline selection. */ 117typedef enum pipe_attr { 118 PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS 119 , PIPE_O_OS 120} PIPE_ATTR; 121 122/* Number of architecture variants. */ 123#define MAX_ISAS 1 124#define MAX_MACHS ((int) MACH_MAX) 125 126/* Ifield support. */ 127 128/* Ifield attribute indices. */ 129 130/* Enum declaration for cgen_ifld attrs. */ 131typedef enum cgen_ifld_attr { 132 CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED 133 , CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS 134 , CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS 135} CGEN_IFLD_ATTR; 136 137/* Number of non-boolean elements in cgen_ifld_attr. */ 138#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1) 139 140/* cgen_ifld attribute accessor macros. */ 141#define CGEN_ATTR_CGEN_IFLD_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_IFLD_MACH-CGEN_IFLD_START_NBOOLS-1].nonbitset) 142#define CGEN_ATTR_CGEN_IFLD_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_VIRTUAL)) != 0) 143#define CGEN_ATTR_CGEN_IFLD_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_PCREL_ADDR)) != 0) 144#define CGEN_ATTR_CGEN_IFLD_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_ABS_ADDR)) != 0) 145#define CGEN_ATTR_CGEN_IFLD_RESERVED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RESERVED)) != 0) 146#define CGEN_ATTR_CGEN_IFLD_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGN_OPT)) != 0) 147#define CGEN_ATTR_CGEN_IFLD_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_SIGNED)) != 0) 148#define CGEN_ATTR_CGEN_IFLD_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_IFLD_RELOC)) != 0) 149 150/* Enum declaration for m32r ifield types. */ 151typedef enum ifield_type { 152 M32R_F_NIL, M32R_F_ANYOF, M32R_F_OP1, M32R_F_OP2 153 , M32R_F_COND, M32R_F_R1, M32R_F_R2, M32R_F_SIMM8 154 , M32R_F_SIMM16, M32R_F_SHIFT_OP2, M32R_F_UIMM3, M32R_F_UIMM4 155 , M32R_F_UIMM5, M32R_F_UIMM8, M32R_F_UIMM16, M32R_F_UIMM24 156 , M32R_F_HI16, M32R_F_DISP8, M32R_F_DISP16, M32R_F_DISP24 157 , M32R_F_OP23, M32R_F_OP3, M32R_F_ACC, M32R_F_ACCS 158 , M32R_F_ACCD, M32R_F_BITS67, M32R_F_BIT4, M32R_F_BIT14 159 , M32R_F_IMM1, M32R_F_MAX 160} IFIELD_TYPE; 161 162#define MAX_IFLD ((int) M32R_F_MAX) 163 164/* Hardware attribute indices. */ 165 166/* Enum declaration for cgen_hw attrs. */ 167typedef enum cgen_hw_attr { 168 CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE 169 , CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS 170} CGEN_HW_ATTR; 171 172/* Number of non-boolean elements in cgen_hw_attr. */ 173#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1) 174 175/* cgen_hw attribute accessor macros. */ 176#define CGEN_ATTR_CGEN_HW_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_HW_MACH-CGEN_HW_START_NBOOLS-1].nonbitset) 177#define CGEN_ATTR_CGEN_HW_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_VIRTUAL)) != 0) 178#define CGEN_ATTR_CGEN_HW_CACHE_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_CACHE_ADDR)) != 0) 179#define CGEN_ATTR_CGEN_HW_PC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PC)) != 0) 180#define CGEN_ATTR_CGEN_HW_PROFILE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_HW_PROFILE)) != 0) 181 182/* Enum declaration for m32r hardware types. */ 183typedef enum cgen_hw_type { 184 HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR 185 , HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16 186 , HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM 187 , HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW 188 , HW_H_BBPSW, HW_H_LOCK, HW_MAX 189} CGEN_HW_TYPE; 190 191#define MAX_HW ((int) HW_MAX) 192 193/* Operand attribute indices. */ 194 195/* Enum declaration for cgen_operand attrs. */ 196typedef enum cgen_operand_attr { 197 CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT 198 , CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY 199 , CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31 200 , CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS 201} CGEN_OPERAND_ATTR; 202 203/* Number of non-boolean elements in cgen_operand_attr. */ 204#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1) 205 206/* cgen_operand attribute accessor macros. */ 207#define CGEN_ATTR_CGEN_OPERAND_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_OPERAND_MACH-CGEN_OPERAND_START_NBOOLS-1].nonbitset) 208#define CGEN_ATTR_CGEN_OPERAND_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_VIRTUAL)) != 0) 209#define CGEN_ATTR_CGEN_OPERAND_PCREL_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_PCREL_ADDR)) != 0) 210#define CGEN_ATTR_CGEN_OPERAND_ABS_ADDR_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_ABS_ADDR)) != 0) 211#define CGEN_ATTR_CGEN_OPERAND_SIGN_OPT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGN_OPT)) != 0) 212#define CGEN_ATTR_CGEN_OPERAND_SIGNED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SIGNED)) != 0) 213#define CGEN_ATTR_CGEN_OPERAND_NEGATIVE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_NEGATIVE)) != 0) 214#define CGEN_ATTR_CGEN_OPERAND_RELAX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELAX)) != 0) 215#define CGEN_ATTR_CGEN_OPERAND_SEM_ONLY_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_SEM_ONLY)) != 0) 216#define CGEN_ATTR_CGEN_OPERAND_RELOC_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_RELOC)) != 0) 217#define CGEN_ATTR_CGEN_OPERAND_HASH_PREFIX_VALUE(attrs) (((attrs)->bool & (1 << CGEN_OPERAND_HASH_PREFIX)) != 0) 218 219/* Enum declaration for m32r operand types. */ 220typedef enum cgen_operand_type { 221 M32R_OPERAND_PC, M32R_OPERAND_SR, M32R_OPERAND_DR, M32R_OPERAND_SRC1 222 , M32R_OPERAND_SRC2, M32R_OPERAND_SCR, M32R_OPERAND_DCR, M32R_OPERAND_SIMM8 223 , M32R_OPERAND_SIMM16, M32R_OPERAND_UIMM3, M32R_OPERAND_UIMM4, M32R_OPERAND_UIMM5 224 , M32R_OPERAND_UIMM8, M32R_OPERAND_UIMM16, M32R_OPERAND_IMM1, M32R_OPERAND_ACCD 225 , M32R_OPERAND_ACCS, M32R_OPERAND_ACC, M32R_OPERAND_HASH, M32R_OPERAND_HI16 226 , M32R_OPERAND_SLO16, M32R_OPERAND_ULO16, M32R_OPERAND_UIMM24, M32R_OPERAND_DISP8 227 , M32R_OPERAND_DISP16, M32R_OPERAND_DISP24, M32R_OPERAND_CONDBIT, M32R_OPERAND_ACCUM 228 , M32R_OPERAND_MAX 229} CGEN_OPERAND_TYPE; 230 231/* Number of operands types. */ 232#define MAX_OPERANDS 28 233 234/* Maximum number of operands referenced by any insn. */ 235#define MAX_OPERAND_INSTANCES 11 236 237/* Insn attribute indices. */ 238 239/* Enum declaration for cgen_insn attrs. */ 240typedef enum cgen_insn_attr { 241 CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI 242 , CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAXED 243 , CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL 244 , CGEN_INSN_SPECIAL_M32R, CGEN_INSN_SPECIAL_FLOAT, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31 245 , CGEN_INSN_MACH, CGEN_INSN_PIPE, CGEN_INSN_END_NBOOLS 246} CGEN_INSN_ATTR; 247 248/* Number of non-boolean elements in cgen_insn_attr. */ 249#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1) 250 251/* cgen_insn attribute accessor macros. */ 252#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset) 253#define CGEN_ATTR_CGEN_INSN_PIPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_PIPE-CGEN_INSN_START_NBOOLS-1].nonbitset) 254#define CGEN_ATTR_CGEN_INSN_ALIAS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_ALIAS)) != 0) 255#define CGEN_ATTR_CGEN_INSN_VIRTUAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_VIRTUAL)) != 0) 256#define CGEN_ATTR_CGEN_INSN_UNCOND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_UNCOND_CTI)) != 0) 257#define CGEN_ATTR_CGEN_INSN_COND_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_COND_CTI)) != 0) 258#define CGEN_ATTR_CGEN_INSN_SKIP_CTI_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SKIP_CTI)) != 0) 259#define CGEN_ATTR_CGEN_INSN_DELAY_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_DELAY_SLOT)) != 0) 260#define CGEN_ATTR_CGEN_INSN_RELAXABLE_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXABLE)) != 0) 261#define CGEN_ATTR_CGEN_INSN_RELAXED_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_RELAXED)) != 0) 262#define CGEN_ATTR_CGEN_INSN_NO_DIS_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_NO_DIS)) != 0) 263#define CGEN_ATTR_CGEN_INSN_PBB_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_PBB)) != 0) 264#define CGEN_ATTR_CGEN_INSN_FILL_SLOT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_FILL_SLOT)) != 0) 265#define CGEN_ATTR_CGEN_INSN_SPECIAL_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL)) != 0) 266#define CGEN_ATTR_CGEN_INSN_SPECIAL_M32R_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_M32R)) != 0) 267#define CGEN_ATTR_CGEN_INSN_SPECIAL_FLOAT_VALUE(attrs) (((attrs)->bool & (1 << CGEN_INSN_SPECIAL_FLOAT)) != 0) 268 269/* cgen.h uses things we just defined. */ 270#include "opcode/cgen.h" 271 272extern const struct cgen_ifld m32r_cgen_ifld_table[]; 273 274/* Attributes. */ 275extern const CGEN_ATTR_TABLE m32r_cgen_hardware_attr_table[]; 276extern const CGEN_ATTR_TABLE m32r_cgen_ifield_attr_table[]; 277extern const CGEN_ATTR_TABLE m32r_cgen_operand_attr_table[]; 278extern const CGEN_ATTR_TABLE m32r_cgen_insn_attr_table[]; 279 280/* Hardware decls. */ 281 282extern CGEN_KEYWORD m32r_cgen_opval_gr_names; 283extern CGEN_KEYWORD m32r_cgen_opval_cr_names; 284extern CGEN_KEYWORD m32r_cgen_opval_h_accums; 285 286extern const CGEN_HW_ENTRY m32r_cgen_hw_table[]; 287 288 289 290#endif /* M32R_CPU_H */ 291