1/* Target-dependent code for GDB, the GNU debugger. 2 3 Copyright (C) 1986, 1987, 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 4 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007 5 Free Software Foundation, Inc. 6 7 This file is part of GDB. 8 9 This program is free software; you can redistribute it and/or modify 10 it under the terms of the GNU General Public License as published by 11 the Free Software Foundation; either version 3 of the License, or 12 (at your option) any later version. 13 14 This program is distributed in the hope that it will be useful, 15 but WITHOUT ANY WARRANTY; without even the implied warranty of 16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 GNU General Public License for more details. 18 19 You should have received a copy of the GNU General Public License 20 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 21 22#include "defs.h" 23#include "frame.h" 24#include "inferior.h" 25#include "symtab.h" 26#include "target.h" 27#include "gdbcore.h" 28#include "gdbcmd.h" 29#include "objfiles.h" 30#include "arch-utils.h" 31#include "regcache.h" 32#include "regset.h" 33#include "doublest.h" 34#include "value.h" 35#include "parser-defs.h" 36#include "osabi.h" 37#include "infcall.h" 38#include "sim-regno.h" 39#include "gdb/sim-ppc.h" 40#include "reggroups.h" 41#include "dwarf2-frame.h" 42 43#include "libbfd.h" /* for bfd_default_set_arch_mach */ 44#include "coff/internal.h" /* for libcoff.h */ 45#include "libcoff.h" /* for xcoff_data */ 46#include "coff/xcoff.h" 47#include "libxcoff.h" 48 49#include "elf-bfd.h" 50 51#include "solib-svr4.h" 52#include "ppc-tdep.h" 53 54#include "gdb_assert.h" 55#include "dis-asm.h" 56 57#include "trad-frame.h" 58#include "frame-unwind.h" 59#include "frame-base.h" 60 61#include "rs6000-tdep.h" 62 63/* If the kernel has to deliver a signal, it pushes a sigcontext 64 structure on the stack and then calls the signal handler, passing 65 the address of the sigcontext in an argument register. Usually 66 the signal handler doesn't save this register, so we have to 67 access the sigcontext structure via an offset from the signal handler 68 frame. 69 The following constants were determined by experimentation on AIX 3.2. */ 70#define SIG_FRAME_PC_OFFSET 96 71#define SIG_FRAME_LR_OFFSET 108 72#define SIG_FRAME_FP_OFFSET 284 73 74/* To be used by skip_prologue. */ 75 76struct rs6000_framedata 77 { 78 int offset; /* total size of frame --- the distance 79 by which we decrement sp to allocate 80 the frame */ 81 int saved_gpr; /* smallest # of saved gpr */ 82 int saved_fpr; /* smallest # of saved fpr */ 83 int saved_vr; /* smallest # of saved vr */ 84 int saved_ev; /* smallest # of saved ev */ 85 int alloca_reg; /* alloca register number (frame ptr) */ 86 char frameless; /* true if frameless functions. */ 87 char nosavedpc; /* true if pc not saved. */ 88 int gpr_offset; /* offset of saved gprs from prev sp */ 89 int fpr_offset; /* offset of saved fprs from prev sp */ 90 int vr_offset; /* offset of saved vrs from prev sp */ 91 int ev_offset; /* offset of saved evs from prev sp */ 92 int lr_offset; /* offset of saved lr */ 93 int cr_offset; /* offset of saved cr */ 94 int vrsave_offset; /* offset of saved vrsave register */ 95 }; 96 97/* Description of a single register. */ 98 99struct reg 100 { 101 char *name; /* name of register */ 102 unsigned char sz32; /* size on 32-bit arch, 0 if nonexistent */ 103 unsigned char sz64; /* size on 64-bit arch, 0 if nonexistent */ 104 unsigned char fpr; /* whether register is floating-point */ 105 unsigned char pseudo; /* whether register is pseudo */ 106 int spr_num; /* PowerPC SPR number, or -1 if not an SPR. 107 This is an ISA SPR number, not a GDB 108 register number. */ 109 }; 110 111/* Hook for determining the TOC address when calling functions in the 112 inferior under AIX. The initialization code in rs6000-nat.c sets 113 this hook to point to find_toc_address. */ 114 115CORE_ADDR (*rs6000_find_toc_address_hook) (CORE_ADDR) = NULL; 116 117/* Static function prototypes */ 118 119static CORE_ADDR branch_dest (struct frame_info *frame, int opcode, 120 int instr, CORE_ADDR pc, CORE_ADDR safety); 121static CORE_ADDR skip_prologue (CORE_ADDR, CORE_ADDR, 122 struct rs6000_framedata *); 123 124/* Is REGNO an AltiVec register? Return 1 if so, 0 otherwise. */ 125int 126altivec_register_p (int regno) 127{ 128 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 129 if (tdep->ppc_vr0_regnum < 0 || tdep->ppc_vrsave_regnum < 0) 130 return 0; 131 else 132 return (regno >= tdep->ppc_vr0_regnum && regno <= tdep->ppc_vrsave_regnum); 133} 134 135 136/* Return true if REGNO is an SPE register, false otherwise. */ 137int 138spe_register_p (int regno) 139{ 140 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 141 142 /* Is it a reference to EV0 -- EV31, and do we have those? */ 143 if (tdep->ppc_ev0_regnum >= 0 144 && tdep->ppc_ev31_regnum >= 0 145 && tdep->ppc_ev0_regnum <= regno && regno <= tdep->ppc_ev31_regnum) 146 return 1; 147 148 /* Is it a reference to one of the raw upper GPR halves? */ 149 if (tdep->ppc_ev0_upper_regnum >= 0 150 && tdep->ppc_ev0_upper_regnum <= regno 151 && regno < tdep->ppc_ev0_upper_regnum + ppc_num_gprs) 152 return 1; 153 154 /* Is it a reference to the 64-bit accumulator, and do we have that? */ 155 if (tdep->ppc_acc_regnum >= 0 156 && tdep->ppc_acc_regnum == regno) 157 return 1; 158 159 /* Is it a reference to the SPE floating-point status and control register, 160 and do we have that? */ 161 if (tdep->ppc_spefscr_regnum >= 0 162 && tdep->ppc_spefscr_regnum == regno) 163 return 1; 164 165 return 0; 166} 167 168 169/* Return non-zero if the architecture described by GDBARCH has 170 floating-point registers (f0 --- f31 and fpscr). */ 171int 172ppc_floating_point_unit_p (struct gdbarch *gdbarch) 173{ 174 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 175 176 return (tdep->ppc_fp0_regnum >= 0 177 && tdep->ppc_fpscr_regnum >= 0); 178} 179 180 181/* Check that TABLE[GDB_REGNO] is not already initialized, and then 182 set it to SIM_REGNO. 183 184 This is a helper function for init_sim_regno_table, constructing 185 the table mapping GDB register numbers to sim register numbers; we 186 initialize every element in that table to -1 before we start 187 filling it in. */ 188static void 189set_sim_regno (int *table, int gdb_regno, int sim_regno) 190{ 191 /* Make sure we don't try to assign any given GDB register a sim 192 register number more than once. */ 193 gdb_assert (table[gdb_regno] == -1); 194 table[gdb_regno] = sim_regno; 195} 196 197 198/* Initialize ARCH->tdep->sim_regno, the table mapping GDB register 199 numbers to simulator register numbers, based on the values placed 200 in the ARCH->tdep->ppc_foo_regnum members. */ 201static void 202init_sim_regno_table (struct gdbarch *arch) 203{ 204 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 205 int total_regs = gdbarch_num_regs (arch) + gdbarch_num_pseudo_regs (arch); 206 const struct reg *regs = tdep->regs; 207 int *sim_regno = GDBARCH_OBSTACK_CALLOC (arch, total_regs, int); 208 int i; 209 210 /* Presume that all registers not explicitly mentioned below are 211 unavailable from the sim. */ 212 for (i = 0; i < total_regs; i++) 213 sim_regno[i] = -1; 214 215 /* General-purpose registers. */ 216 for (i = 0; i < ppc_num_gprs; i++) 217 set_sim_regno (sim_regno, tdep->ppc_gp0_regnum + i, sim_ppc_r0_regnum + i); 218 219 /* Floating-point registers. */ 220 if (tdep->ppc_fp0_regnum >= 0) 221 for (i = 0; i < ppc_num_fprs; i++) 222 set_sim_regno (sim_regno, 223 tdep->ppc_fp0_regnum + i, 224 sim_ppc_f0_regnum + i); 225 if (tdep->ppc_fpscr_regnum >= 0) 226 set_sim_regno (sim_regno, tdep->ppc_fpscr_regnum, sim_ppc_fpscr_regnum); 227 228 set_sim_regno (sim_regno, gdbarch_pc_regnum (arch), sim_ppc_pc_regnum); 229 set_sim_regno (sim_regno, tdep->ppc_ps_regnum, sim_ppc_ps_regnum); 230 set_sim_regno (sim_regno, tdep->ppc_cr_regnum, sim_ppc_cr_regnum); 231 232 /* Segment registers. */ 233 if (tdep->ppc_sr0_regnum >= 0) 234 for (i = 0; i < ppc_num_srs; i++) 235 set_sim_regno (sim_regno, 236 tdep->ppc_sr0_regnum + i, 237 sim_ppc_sr0_regnum + i); 238 239 /* Altivec registers. */ 240 if (tdep->ppc_vr0_regnum >= 0) 241 { 242 for (i = 0; i < ppc_num_vrs; i++) 243 set_sim_regno (sim_regno, 244 tdep->ppc_vr0_regnum + i, 245 sim_ppc_vr0_regnum + i); 246 247 /* FIXME: jimb/2004-07-15: when we have tdep->ppc_vscr_regnum, 248 we can treat this more like the other cases. */ 249 set_sim_regno (sim_regno, 250 tdep->ppc_vr0_regnum + ppc_num_vrs, 251 sim_ppc_vscr_regnum); 252 } 253 /* vsave is a special-purpose register, so the code below handles it. */ 254 255 /* SPE APU (E500) registers. */ 256 if (tdep->ppc_ev0_regnum >= 0) 257 for (i = 0; i < ppc_num_gprs; i++) 258 set_sim_regno (sim_regno, 259 tdep->ppc_ev0_regnum + i, 260 sim_ppc_ev0_regnum + i); 261 if (tdep->ppc_ev0_upper_regnum >= 0) 262 for (i = 0; i < ppc_num_gprs; i++) 263 set_sim_regno (sim_regno, 264 tdep->ppc_ev0_upper_regnum + i, 265 sim_ppc_rh0_regnum + i); 266 if (tdep->ppc_acc_regnum >= 0) 267 set_sim_regno (sim_regno, tdep->ppc_acc_regnum, sim_ppc_acc_regnum); 268 /* spefscr is a special-purpose register, so the code below handles it. */ 269 270 /* Now handle all special-purpose registers. Verify that they 271 haven't mistakenly been assigned numbers by any of the above 272 code). */ 273 for (i = 0; i < total_regs; i++) 274 if (regs[i].spr_num >= 0) 275 set_sim_regno (sim_regno, i, regs[i].spr_num + sim_ppc_spr0_regnum); 276 277 /* Drop the initialized array into place. */ 278 tdep->sim_regno = sim_regno; 279} 280 281 282/* Given a GDB register number REG, return the corresponding SIM 283 register number. */ 284static int 285rs6000_register_sim_regno (int reg) 286{ 287 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 288 int sim_regno; 289 290 gdb_assert (0 <= reg 291 && reg <= gdbarch_num_regs (current_gdbarch) 292 + gdbarch_num_pseudo_regs (current_gdbarch)); 293 sim_regno = tdep->sim_regno[reg]; 294 295 if (sim_regno >= 0) 296 return sim_regno; 297 else 298 return LEGACY_SIM_REGNO_IGNORE; 299} 300 301 302 303/* Register set support functions. */ 304 305/* REGS + OFFSET contains register REGNUM in a field REGSIZE wide. 306 Write the register to REGCACHE. */ 307 308static void 309ppc_supply_reg (struct regcache *regcache, int regnum, 310 const gdb_byte *regs, size_t offset, int regsize) 311{ 312 if (regnum != -1 && offset != -1) 313 { 314 if (regsize > 4) 315 { 316 struct gdbarch *gdbarch = get_regcache_arch (regcache); 317 int gdb_regsize = register_size (gdbarch, regnum); 318 if (gdb_regsize < regsize 319 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 320 offset += regsize - gdb_regsize; 321 } 322 regcache_raw_supply (regcache, regnum, regs + offset); 323 } 324} 325 326/* Read register REGNUM from REGCACHE and store to REGS + OFFSET 327 in a field REGSIZE wide. Zero pad as necessary. */ 328 329static void 330ppc_collect_reg (const struct regcache *regcache, int regnum, 331 gdb_byte *regs, size_t offset, int regsize) 332{ 333 if (regnum != -1 && offset != -1) 334 { 335 if (regsize > 4) 336 { 337 struct gdbarch *gdbarch = get_regcache_arch (regcache); 338 int gdb_regsize = register_size (gdbarch, regnum); 339 if (gdb_regsize < regsize) 340 { 341 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) 342 { 343 memset (regs + offset, 0, regsize - gdb_regsize); 344 offset += regsize - gdb_regsize; 345 } 346 else 347 memset (regs + offset + regsize - gdb_regsize, 0, 348 regsize - gdb_regsize); 349 } 350 } 351 regcache_raw_collect (regcache, regnum, regs + offset); 352 } 353} 354 355static int 356ppc_greg_offset (struct gdbarch *gdbarch, 357 struct gdbarch_tdep *tdep, 358 const struct ppc_reg_offsets *offsets, 359 int regnum, 360 int *regsize) 361{ 362 *regsize = offsets->gpr_size; 363 if (regnum >= tdep->ppc_gp0_regnum 364 && regnum < tdep->ppc_gp0_regnum + ppc_num_gprs) 365 return (offsets->r0_offset 366 + (regnum - tdep->ppc_gp0_regnum) * offsets->gpr_size); 367 368 if (regnum == gdbarch_pc_regnum (gdbarch)) 369 return offsets->pc_offset; 370 371 if (regnum == tdep->ppc_ps_regnum) 372 return offsets->ps_offset; 373 374 if (regnum == tdep->ppc_lr_regnum) 375 return offsets->lr_offset; 376 377 if (regnum == tdep->ppc_ctr_regnum) 378 return offsets->ctr_offset; 379 380 *regsize = offsets->xr_size; 381 if (regnum == tdep->ppc_cr_regnum) 382 return offsets->cr_offset; 383 384 if (regnum == tdep->ppc_xer_regnum) 385 return offsets->xer_offset; 386 387 if (regnum == tdep->ppc_mq_regnum) 388 return offsets->mq_offset; 389 390 return -1; 391} 392 393static int 394ppc_fpreg_offset (struct gdbarch_tdep *tdep, 395 const struct ppc_reg_offsets *offsets, 396 int regnum) 397{ 398 if (regnum >= tdep->ppc_fp0_regnum 399 && regnum < tdep->ppc_fp0_regnum + ppc_num_fprs) 400 return offsets->f0_offset + (regnum - tdep->ppc_fp0_regnum) * 8; 401 402 if (regnum == tdep->ppc_fpscr_regnum) 403 return offsets->fpscr_offset; 404 405 return -1; 406} 407 408/* Supply register REGNUM in the general-purpose register set REGSET 409 from the buffer specified by GREGS and LEN to register cache 410 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 411 412void 413ppc_supply_gregset (const struct regset *regset, struct regcache *regcache, 414 int regnum, const void *gregs, size_t len) 415{ 416 struct gdbarch *gdbarch = get_regcache_arch (regcache); 417 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 418 const struct ppc_reg_offsets *offsets = regset->descr; 419 size_t offset; 420 int regsize; 421 422 if (regnum == -1) 423 { 424 int i; 425 int gpr_size = offsets->gpr_size; 426 427 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; 428 i < tdep->ppc_gp0_regnum + ppc_num_gprs; 429 i++, offset += gpr_size) 430 ppc_supply_reg (regcache, i, gregs, offset, gpr_size); 431 432 ppc_supply_reg (regcache, gdbarch_pc_regnum (gdbarch), 433 gregs, offsets->pc_offset, gpr_size); 434 ppc_supply_reg (regcache, tdep->ppc_ps_regnum, 435 gregs, offsets->ps_offset, gpr_size); 436 ppc_supply_reg (regcache, tdep->ppc_lr_regnum, 437 gregs, offsets->lr_offset, gpr_size); 438 ppc_supply_reg (regcache, tdep->ppc_ctr_regnum, 439 gregs, offsets->ctr_offset, gpr_size); 440 ppc_supply_reg (regcache, tdep->ppc_cr_regnum, 441 gregs, offsets->cr_offset, offsets->xr_size); 442 ppc_supply_reg (regcache, tdep->ppc_xer_regnum, 443 gregs, offsets->xer_offset, offsets->xr_size); 444 ppc_supply_reg (regcache, tdep->ppc_mq_regnum, 445 gregs, offsets->mq_offset, offsets->xr_size); 446 return; 447 } 448 449 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); 450 ppc_supply_reg (regcache, regnum, gregs, offset, regsize); 451} 452 453/* Supply register REGNUM in the floating-point register set REGSET 454 from the buffer specified by FPREGS and LEN to register cache 455 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 456 457void 458ppc_supply_fpregset (const struct regset *regset, struct regcache *regcache, 459 int regnum, const void *fpregs, size_t len) 460{ 461 struct gdbarch *gdbarch = get_regcache_arch (regcache); 462 struct gdbarch_tdep *tdep; 463 const struct ppc_reg_offsets *offsets; 464 size_t offset; 465 466 if (!ppc_floating_point_unit_p (gdbarch)) 467 return; 468 469 tdep = gdbarch_tdep (gdbarch); 470 offsets = regset->descr; 471 if (regnum == -1) 472 { 473 int i; 474 475 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; 476 i < tdep->ppc_fp0_regnum + ppc_num_fprs; 477 i++, offset += 8) 478 ppc_supply_reg (regcache, i, fpregs, offset, 8); 479 480 ppc_supply_reg (regcache, tdep->ppc_fpscr_regnum, 481 fpregs, offsets->fpscr_offset, offsets->fpscr_size); 482 return; 483 } 484 485 offset = ppc_fpreg_offset (tdep, offsets, regnum); 486 ppc_supply_reg (regcache, regnum, fpregs, offset, 487 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); 488} 489 490/* Collect register REGNUM in the general-purpose register set 491 REGSET from register cache REGCACHE into the buffer specified by 492 GREGS and LEN. If REGNUM is -1, do this for all registers in 493 REGSET. */ 494 495void 496ppc_collect_gregset (const struct regset *regset, 497 const struct regcache *regcache, 498 int regnum, void *gregs, size_t len) 499{ 500 struct gdbarch *gdbarch = get_regcache_arch (regcache); 501 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 502 const struct ppc_reg_offsets *offsets = regset->descr; 503 size_t offset; 504 int regsize; 505 506 if (regnum == -1) 507 { 508 int i; 509 int gpr_size = offsets->gpr_size; 510 511 for (i = tdep->ppc_gp0_regnum, offset = offsets->r0_offset; 512 i < tdep->ppc_gp0_regnum + ppc_num_gprs; 513 i++, offset += gpr_size) 514 ppc_collect_reg (regcache, i, gregs, offset, gpr_size); 515 516 ppc_collect_reg (regcache, gdbarch_pc_regnum (gdbarch), 517 gregs, offsets->pc_offset, gpr_size); 518 ppc_collect_reg (regcache, tdep->ppc_ps_regnum, 519 gregs, offsets->ps_offset, gpr_size); 520 ppc_collect_reg (regcache, tdep->ppc_lr_regnum, 521 gregs, offsets->lr_offset, gpr_size); 522 ppc_collect_reg (regcache, tdep->ppc_ctr_regnum, 523 gregs, offsets->ctr_offset, gpr_size); 524 ppc_collect_reg (regcache, tdep->ppc_cr_regnum, 525 gregs, offsets->cr_offset, offsets->xr_size); 526 ppc_collect_reg (regcache, tdep->ppc_xer_regnum, 527 gregs, offsets->xer_offset, offsets->xr_size); 528 ppc_collect_reg (regcache, tdep->ppc_mq_regnum, 529 gregs, offsets->mq_offset, offsets->xr_size); 530 return; 531 } 532 533 offset = ppc_greg_offset (gdbarch, tdep, offsets, regnum, ®size); 534 ppc_collect_reg (regcache, regnum, gregs, offset, regsize); 535} 536 537/* Collect register REGNUM in the floating-point register set 538 REGSET from register cache REGCACHE into the buffer specified by 539 FPREGS and LEN. If REGNUM is -1, do this for all registers in 540 REGSET. */ 541 542void 543ppc_collect_fpregset (const struct regset *regset, 544 const struct regcache *regcache, 545 int regnum, void *fpregs, size_t len) 546{ 547 struct gdbarch *gdbarch = get_regcache_arch (regcache); 548 struct gdbarch_tdep *tdep; 549 const struct ppc_reg_offsets *offsets; 550 size_t offset; 551 552 if (!ppc_floating_point_unit_p (gdbarch)) 553 return; 554 555 tdep = gdbarch_tdep (gdbarch); 556 offsets = regset->descr; 557 if (regnum == -1) 558 { 559 int i; 560 561 for (i = tdep->ppc_fp0_regnum, offset = offsets->f0_offset; 562 i < tdep->ppc_fp0_regnum + ppc_num_fprs; 563 i++, offset += 8) 564 ppc_collect_reg (regcache, i, fpregs, offset, 8); 565 566 ppc_collect_reg (regcache, tdep->ppc_fpscr_regnum, 567 fpregs, offsets->fpscr_offset, offsets->fpscr_size); 568 return; 569 } 570 571 offset = ppc_fpreg_offset (tdep, offsets, regnum); 572 ppc_collect_reg (regcache, regnum, fpregs, offset, 573 regnum == tdep->ppc_fpscr_regnum ? offsets->fpscr_size : 8); 574} 575 576 577/* Read a LEN-byte address from debugged memory address MEMADDR. */ 578 579static CORE_ADDR 580read_memory_addr (CORE_ADDR memaddr, int len) 581{ 582 return read_memory_unsigned_integer (memaddr, len); 583} 584 585static CORE_ADDR 586rs6000_skip_prologue (CORE_ADDR pc) 587{ 588 struct rs6000_framedata frame; 589 CORE_ADDR limit_pc, func_addr; 590 591 /* See if we can determine the end of the prologue via the symbol table. 592 If so, then return either PC, or the PC after the prologue, whichever 593 is greater. */ 594 if (find_pc_partial_function (pc, NULL, &func_addr, NULL)) 595 { 596 CORE_ADDR post_prologue_pc = skip_prologue_using_sal (func_addr); 597 if (post_prologue_pc != 0) 598 return max (pc, post_prologue_pc); 599 } 600 601 /* Can't determine prologue from the symbol table, need to examine 602 instructions. */ 603 604 /* Find an upper limit on the function prologue using the debug 605 information. If the debug information could not be used to provide 606 that bound, then use an arbitrary large number as the upper bound. */ 607 limit_pc = skip_prologue_using_sal (pc); 608 if (limit_pc == 0) 609 limit_pc = pc + 100; /* Magic. */ 610 611 pc = skip_prologue (pc, limit_pc, &frame); 612 return pc; 613} 614 615static int 616insn_changes_sp_or_jumps (unsigned long insn) 617{ 618 int opcode = (insn >> 26) & 0x03f; 619 int sd = (insn >> 21) & 0x01f; 620 int a = (insn >> 16) & 0x01f; 621 int subcode = (insn >> 1) & 0x3ff; 622 623 /* Changes the stack pointer. */ 624 625 /* NOTE: There are many ways to change the value of a given register. 626 The ways below are those used when the register is R1, the SP, 627 in a funtion's epilogue. */ 628 629 if (opcode == 31 && subcode == 444 && a == 1) 630 return 1; /* mr R1,Rn */ 631 if (opcode == 14 && sd == 1) 632 return 1; /* addi R1,Rn,simm */ 633 if (opcode == 58 && sd == 1) 634 return 1; /* ld R1,ds(Rn) */ 635 636 /* Transfers control. */ 637 638 if (opcode == 18) 639 return 1; /* b */ 640 if (opcode == 16) 641 return 1; /* bc */ 642 if (opcode == 19 && subcode == 16) 643 return 1; /* bclr */ 644 if (opcode == 19 && subcode == 528) 645 return 1; /* bcctr */ 646 647 return 0; 648} 649 650/* Return true if we are in the function's epilogue, i.e. after the 651 instruction that destroyed the function's stack frame. 652 653 1) scan forward from the point of execution: 654 a) If you find an instruction that modifies the stack pointer 655 or transfers control (except a return), execution is not in 656 an epilogue, return. 657 b) Stop scanning if you find a return instruction or reach the 658 end of the function or reach the hard limit for the size of 659 an epilogue. 660 2) scan backward from the point of execution: 661 a) If you find an instruction that modifies the stack pointer, 662 execution *is* in an epilogue, return. 663 b) Stop scanning if you reach an instruction that transfers 664 control or the beginning of the function or reach the hard 665 limit for the size of an epilogue. */ 666 667static int 668rs6000_in_function_epilogue_p (struct gdbarch *gdbarch, CORE_ADDR pc) 669{ 670 bfd_byte insn_buf[PPC_INSN_SIZE]; 671 CORE_ADDR scan_pc, func_start, func_end, epilogue_start, epilogue_end; 672 unsigned long insn; 673 struct frame_info *curfrm; 674 675 /* Find the search limits based on function boundaries and hard limit. */ 676 677 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end)) 678 return 0; 679 680 epilogue_start = pc - PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; 681 if (epilogue_start < func_start) epilogue_start = func_start; 682 683 epilogue_end = pc + PPC_MAX_EPILOGUE_INSTRUCTIONS * PPC_INSN_SIZE; 684 if (epilogue_end > func_end) epilogue_end = func_end; 685 686 curfrm = get_current_frame (); 687 688 /* Scan forward until next 'blr'. */ 689 690 for (scan_pc = pc; scan_pc < epilogue_end; scan_pc += PPC_INSN_SIZE) 691 { 692 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) 693 return 0; 694 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE); 695 if (insn == 0x4e800020) 696 break; 697 if (insn_changes_sp_or_jumps (insn)) 698 return 0; 699 } 700 701 /* Scan backward until adjustment to stack pointer (R1). */ 702 703 for (scan_pc = pc - PPC_INSN_SIZE; 704 scan_pc >= epilogue_start; 705 scan_pc -= PPC_INSN_SIZE) 706 { 707 if (!safe_frame_unwind_memory (curfrm, scan_pc, insn_buf, PPC_INSN_SIZE)) 708 return 0; 709 insn = extract_unsigned_integer (insn_buf, PPC_INSN_SIZE); 710 if (insn_changes_sp_or_jumps (insn)) 711 return 1; 712 } 713 714 return 0; 715} 716 717/* Get the ith function argument for the current function. */ 718static CORE_ADDR 719rs6000_fetch_pointer_argument (struct frame_info *frame, int argi, 720 struct type *type) 721{ 722 return get_frame_register_unsigned (frame, 3 + argi); 723} 724 725/* Calculate the destination of a branch/jump. Return -1 if not a branch. */ 726 727static CORE_ADDR 728branch_dest (struct frame_info *frame, int opcode, int instr, 729 CORE_ADDR pc, CORE_ADDR safety) 730{ 731 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (frame)); 732 CORE_ADDR dest; 733 int immediate; 734 int absolute; 735 int ext_op; 736 737 absolute = (int) ((instr >> 1) & 1); 738 739 switch (opcode) 740 { 741 case 18: 742 immediate = ((instr & ~3) << 6) >> 6; /* br unconditional */ 743 if (absolute) 744 dest = immediate; 745 else 746 dest = pc + immediate; 747 break; 748 749 case 16: 750 immediate = ((instr & ~3) << 16) >> 16; /* br conditional */ 751 if (absolute) 752 dest = immediate; 753 else 754 dest = pc + immediate; 755 break; 756 757 case 19: 758 ext_op = (instr >> 1) & 0x3ff; 759 760 if (ext_op == 16) /* br conditional register */ 761 { 762 dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3; 763 764 /* If we are about to return from a signal handler, dest is 765 something like 0x3c90. The current frame is a signal handler 766 caller frame, upon completion of the sigreturn system call 767 execution will return to the saved PC in the frame. */ 768 if (dest < tdep->text_segment_base) 769 dest = read_memory_addr (get_frame_base (frame) + SIG_FRAME_PC_OFFSET, 770 tdep->wordsize); 771 } 772 773 else if (ext_op == 528) /* br cond to count reg */ 774 { 775 dest = get_frame_register_unsigned (frame, tdep->ppc_ctr_regnum) & ~3; 776 777 /* If we are about to execute a system call, dest is something 778 like 0x22fc or 0x3b00. Upon completion the system call 779 will return to the address in the link register. */ 780 if (dest < tdep->text_segment_base) 781 dest = get_frame_register_unsigned (frame, tdep->ppc_lr_regnum) & ~3; 782 } 783 else 784 return -1; 785 break; 786 787 default: 788 return -1; 789 } 790 return (dest < tdep->text_segment_base) ? safety : dest; 791} 792 793 794/* Sequence of bytes for breakpoint instruction. */ 795 796const static unsigned char * 797rs6000_breakpoint_from_pc (CORE_ADDR *bp_addr, int *bp_size) 798{ 799 static unsigned char big_breakpoint[] = { 0x7d, 0x82, 0x10, 0x08 }; 800 static unsigned char little_breakpoint[] = { 0x08, 0x10, 0x82, 0x7d }; 801 *bp_size = 4; 802 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) 803 return big_breakpoint; 804 else 805 return little_breakpoint; 806} 807 808 809/* Instruction masks used during single-stepping of atomic sequences. */ 810#define LWARX_MASK 0xfc0007fe 811#define LWARX_INSTRUCTION 0x7c000028 812#define LDARX_INSTRUCTION 0x7c0000A8 813#define STWCX_MASK 0xfc0007ff 814#define STWCX_INSTRUCTION 0x7c00012d 815#define STDCX_INSTRUCTION 0x7c0001ad 816#define BC_MASK 0xfc000000 817#define BC_INSTRUCTION 0x40000000 818 819/* Checks for an atomic sequence of instructions beginning with a LWARX/LDARX 820 instruction and ending with a STWCX/STDCX instruction. If such a sequence 821 is found, attempt to step through it. A breakpoint is placed at the end of 822 the sequence. */ 823 824static int 825deal_with_atomic_sequence (struct frame_info *frame) 826{ 827 CORE_ADDR pc = get_frame_pc (frame); 828 CORE_ADDR breaks[2] = {-1, -1}; 829 CORE_ADDR loc = pc; 830 CORE_ADDR branch_bp; /* Breakpoint at branch instruction's destination. */ 831 CORE_ADDR closing_insn; /* Instruction that closes the atomic sequence. */ 832 int insn = read_memory_integer (loc, PPC_INSN_SIZE); 833 int insn_count; 834 int index; 835 int last_breakpoint = 0; /* Defaults to 0 (no breakpoints placed). */ 836 const int atomic_sequence_length = 16; /* Instruction sequence length. */ 837 int opcode; /* Branch instruction's OPcode. */ 838 int bc_insn_count = 0; /* Conditional branch instruction count. */ 839 840 /* Assume all atomic sequences start with a lwarx/ldarx instruction. */ 841 if ((insn & LWARX_MASK) != LWARX_INSTRUCTION 842 && (insn & LWARX_MASK) != LDARX_INSTRUCTION) 843 return 0; 844 845 /* Assume that no atomic sequence is longer than "atomic_sequence_length" 846 instructions. */ 847 for (insn_count = 0; insn_count < atomic_sequence_length; ++insn_count) 848 { 849 loc += PPC_INSN_SIZE; 850 insn = read_memory_integer (loc, PPC_INSN_SIZE); 851 852 /* Assume that there is at most one conditional branch in the atomic 853 sequence. If a conditional branch is found, put a breakpoint in 854 its destination address. */ 855 if ((insn & BC_MASK) == BC_INSTRUCTION) 856 { 857 if (bc_insn_count >= 1) 858 return 0; /* More than one conditional branch found, fallback 859 to the standard single-step code. */ 860 861 opcode = insn >> 26; 862 branch_bp = branch_dest (frame, opcode, insn, pc, breaks[0]); 863 864 if (branch_bp != -1) 865 { 866 breaks[1] = branch_bp; 867 bc_insn_count++; 868 last_breakpoint++; 869 } 870 } 871 872 if ((insn & STWCX_MASK) == STWCX_INSTRUCTION 873 || (insn & STWCX_MASK) == STDCX_INSTRUCTION) 874 break; 875 } 876 877 /* Assume that the atomic sequence ends with a stwcx/stdcx instruction. */ 878 if ((insn & STWCX_MASK) != STWCX_INSTRUCTION 879 && (insn & STWCX_MASK) != STDCX_INSTRUCTION) 880 return 0; 881 882 closing_insn = loc; 883 loc += PPC_INSN_SIZE; 884 insn = read_memory_integer (loc, PPC_INSN_SIZE); 885 886 /* Insert a breakpoint right after the end of the atomic sequence. */ 887 breaks[0] = loc; 888 889 /* Check for duplicated breakpoints. Check also for a breakpoint 890 placed (branch instruction's destination) at the stwcx/stdcx 891 instruction, this resets the reservation and take us back to the 892 lwarx/ldarx instruction at the beginning of the atomic sequence. */ 893 if (last_breakpoint && ((breaks[1] == breaks[0]) 894 || (breaks[1] == closing_insn))) 895 last_breakpoint = 0; 896 897 /* Effectively inserts the breakpoints. */ 898 for (index = 0; index <= last_breakpoint; index++) 899 insert_single_step_breakpoint (breaks[index]); 900 901 return 1; 902} 903 904/* AIX does not support PT_STEP. Simulate it. */ 905 906int 907rs6000_software_single_step (struct frame_info *frame) 908{ 909 CORE_ADDR dummy; 910 int breakp_sz; 911 const gdb_byte *breakp = rs6000_breakpoint_from_pc (&dummy, &breakp_sz); 912 int ii, insn; 913 CORE_ADDR loc; 914 CORE_ADDR breaks[2]; 915 int opcode; 916 917 loc = get_frame_pc (frame); 918 919 insn = read_memory_integer (loc, 4); 920 921 if (deal_with_atomic_sequence (frame)) 922 return 1; 923 924 breaks[0] = loc + breakp_sz; 925 opcode = insn >> 26; 926 breaks[1] = branch_dest (frame, opcode, insn, loc, breaks[0]); 927 928 /* Don't put two breakpoints on the same address. */ 929 if (breaks[1] == breaks[0]) 930 breaks[1] = -1; 931 932 for (ii = 0; ii < 2; ++ii) 933 { 934 /* ignore invalid breakpoint. */ 935 if (breaks[ii] == -1) 936 continue; 937 insert_single_step_breakpoint (breaks[ii]); 938 } 939 940 errno = 0; /* FIXME, don't ignore errors! */ 941 /* What errors? {read,write}_memory call error(). */ 942 return 1; 943} 944 945 946/* return pc value after skipping a function prologue and also return 947 information about a function frame. 948 949 in struct rs6000_framedata fdata: 950 - frameless is TRUE, if function does not have a frame. 951 - nosavedpc is TRUE, if function does not save %pc value in its frame. 952 - offset is the initial size of this stack frame --- the amount by 953 which we decrement the sp to allocate the frame. 954 - saved_gpr is the number of the first saved gpr. 955 - saved_fpr is the number of the first saved fpr. 956 - saved_vr is the number of the first saved vr. 957 - saved_ev is the number of the first saved ev. 958 - alloca_reg is the number of the register used for alloca() handling. 959 Otherwise -1. 960 - gpr_offset is the offset of the first saved gpr from the previous frame. 961 - fpr_offset is the offset of the first saved fpr from the previous frame. 962 - vr_offset is the offset of the first saved vr from the previous frame. 963 - ev_offset is the offset of the first saved ev from the previous frame. 964 - lr_offset is the offset of the saved lr 965 - cr_offset is the offset of the saved cr 966 - vrsave_offset is the offset of the saved vrsave register 967 */ 968 969#define SIGNED_SHORT(x) \ 970 ((sizeof (short) == 2) \ 971 ? ((int)(short)(x)) \ 972 : ((int)((((x) & 0xffff) ^ 0x8000) - 0x8000))) 973 974#define GET_SRC_REG(x) (((x) >> 21) & 0x1f) 975 976/* Limit the number of skipped non-prologue instructions, as the examining 977 of the prologue is expensive. */ 978static int max_skip_non_prologue_insns = 10; 979 980/* Return nonzero if the given instruction OP can be part of the prologue 981 of a function and saves a parameter on the stack. FRAMEP should be 982 set if one of the previous instructions in the function has set the 983 Frame Pointer. */ 984 985static int 986store_param_on_stack_p (unsigned long op, int framep, int *r0_contains_arg) 987{ 988 /* Move parameters from argument registers to temporary register. */ 989 if ((op & 0xfc0007fe) == 0x7c000378) /* mr(.) Rx,Ry */ 990 { 991 /* Rx must be scratch register r0. */ 992 const int rx_regno = (op >> 16) & 31; 993 /* Ry: Only r3 - r10 are used for parameter passing. */ 994 const int ry_regno = GET_SRC_REG (op); 995 996 if (rx_regno == 0 && ry_regno >= 3 && ry_regno <= 10) 997 { 998 *r0_contains_arg = 1; 999 return 1; 1000 } 1001 else 1002 return 0; 1003 } 1004 1005 /* Save a General Purpose Register on stack. */ 1006 1007 if ((op & 0xfc1f0003) == 0xf8010000 || /* std Rx,NUM(r1) */ 1008 (op & 0xfc1f0000) == 0xd8010000) /* stfd Rx,NUM(r1) */ 1009 { 1010 /* Rx: Only r3 - r10 are used for parameter passing. */ 1011 const int rx_regno = GET_SRC_REG (op); 1012 1013 return (rx_regno >= 3 && rx_regno <= 10); 1014 } 1015 1016 /* Save a General Purpose Register on stack via the Frame Pointer. */ 1017 1018 if (framep && 1019 ((op & 0xfc1f0000) == 0x901f0000 || /* st rx,NUM(r31) */ 1020 (op & 0xfc1f0000) == 0x981f0000 || /* stb Rx,NUM(r31) */ 1021 (op & 0xfc1f0000) == 0xd81f0000)) /* stfd Rx,NUM(r31) */ 1022 { 1023 /* Rx: Usually, only r3 - r10 are used for parameter passing. 1024 However, the compiler sometimes uses r0 to hold an argument. */ 1025 const int rx_regno = GET_SRC_REG (op); 1026 1027 return ((rx_regno >= 3 && rx_regno <= 10) 1028 || (rx_regno == 0 && *r0_contains_arg)); 1029 } 1030 1031 if ((op & 0xfc1f0000) == 0xfc010000) /* frsp, fp?,NUM(r1) */ 1032 { 1033 /* Only f2 - f8 are used for parameter passing. */ 1034 const int src_regno = GET_SRC_REG (op); 1035 1036 return (src_regno >= 2 && src_regno <= 8); 1037 } 1038 1039 if (framep && ((op & 0xfc1f0000) == 0xfc1f0000)) /* frsp, fp?,NUM(r31) */ 1040 { 1041 /* Only f2 - f8 are used for parameter passing. */ 1042 const int src_regno = GET_SRC_REG (op); 1043 1044 return (src_regno >= 2 && src_regno <= 8); 1045 } 1046 1047 /* Not an insn that saves a parameter on stack. */ 1048 return 0; 1049} 1050 1051/* Assuming that INSN is a "bl" instruction located at PC, return 1052 nonzero if the destination of the branch is a "blrl" instruction. 1053 1054 This sequence is sometimes found in certain function prologues. 1055 It allows the function to load the LR register with a value that 1056 they can use to access PIC data using PC-relative offsets. */ 1057 1058static int 1059bl_to_blrl_insn_p (CORE_ADDR pc, int insn) 1060{ 1061 CORE_ADDR dest; 1062 int immediate; 1063 int absolute; 1064 int dest_insn; 1065 1066 absolute = (int) ((insn >> 1) & 1); 1067 immediate = ((insn & ~3) << 6) >> 6; 1068 if (absolute) 1069 dest = immediate; 1070 else 1071 dest = pc + immediate; 1072 1073 dest_insn = read_memory_integer (dest, 4); 1074 if ((dest_insn & 0xfc00ffff) == 0x4c000021) /* blrl */ 1075 return 1; 1076 1077 return 0; 1078} 1079 1080static CORE_ADDR 1081skip_prologue (CORE_ADDR pc, CORE_ADDR lim_pc, struct rs6000_framedata *fdata) 1082{ 1083 CORE_ADDR orig_pc = pc; 1084 CORE_ADDR last_prologue_pc = pc; 1085 CORE_ADDR li_found_pc = 0; 1086 gdb_byte buf[4]; 1087 unsigned long op; 1088 long offset = 0; 1089 long vr_saved_offset = 0; 1090 int lr_reg = -1; 1091 int cr_reg = -1; 1092 int vr_reg = -1; 1093 int ev_reg = -1; 1094 long ev_offset = 0; 1095 int vrsave_reg = -1; 1096 int reg; 1097 int framep = 0; 1098 int minimal_toc_loaded = 0; 1099 int prev_insn_was_prologue_insn = 1; 1100 int num_skip_non_prologue_insns = 0; 1101 int r0_contains_arg = 0; 1102 const struct bfd_arch_info *arch_info = gdbarch_bfd_arch_info (current_gdbarch); 1103 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1104 1105 memset (fdata, 0, sizeof (struct rs6000_framedata)); 1106 fdata->saved_gpr = -1; 1107 fdata->saved_fpr = -1; 1108 fdata->saved_vr = -1; 1109 fdata->saved_ev = -1; 1110 fdata->alloca_reg = -1; 1111 fdata->frameless = 1; 1112 fdata->nosavedpc = 1; 1113 1114 for (;; pc += 4) 1115 { 1116 /* Sometimes it isn't clear if an instruction is a prologue 1117 instruction or not. When we encounter one of these ambiguous 1118 cases, we'll set prev_insn_was_prologue_insn to 0 (false). 1119 Otherwise, we'll assume that it really is a prologue instruction. */ 1120 if (prev_insn_was_prologue_insn) 1121 last_prologue_pc = pc; 1122 1123 /* Stop scanning if we've hit the limit. */ 1124 if (pc >= lim_pc) 1125 break; 1126 1127 prev_insn_was_prologue_insn = 1; 1128 1129 /* Fetch the instruction and convert it to an integer. */ 1130 if (target_read_memory (pc, buf, 4)) 1131 break; 1132 op = extract_unsigned_integer (buf, 4); 1133 1134 if ((op & 0xfc1fffff) == 0x7c0802a6) 1135 { /* mflr Rx */ 1136 /* Since shared library / PIC code, which needs to get its 1137 address at runtime, can appear to save more than one link 1138 register vis: 1139 1140 *INDENT-OFF* 1141 stwu r1,-304(r1) 1142 mflr r3 1143 bl 0xff570d0 (blrl) 1144 stw r30,296(r1) 1145 mflr r30 1146 stw r31,300(r1) 1147 stw r3,308(r1); 1148 ... 1149 *INDENT-ON* 1150 1151 remember just the first one, but skip over additional 1152 ones. */ 1153 if (lr_reg == -1) 1154 lr_reg = (op & 0x03e00000); 1155 if (lr_reg == 0) 1156 r0_contains_arg = 0; 1157 continue; 1158 } 1159 else if ((op & 0xfc1fffff) == 0x7c000026) 1160 { /* mfcr Rx */ 1161 cr_reg = (op & 0x03e00000); 1162 if (cr_reg == 0) 1163 r0_contains_arg = 0; 1164 continue; 1165 1166 } 1167 else if ((op & 0xfc1f0000) == 0xd8010000) 1168 { /* stfd Rx,NUM(r1) */ 1169 reg = GET_SRC_REG (op); 1170 if (fdata->saved_fpr == -1 || fdata->saved_fpr > reg) 1171 { 1172 fdata->saved_fpr = reg; 1173 fdata->fpr_offset = SIGNED_SHORT (op) + offset; 1174 } 1175 continue; 1176 1177 } 1178 else if (((op & 0xfc1f0000) == 0xbc010000) || /* stm Rx, NUM(r1) */ 1179 (((op & 0xfc1f0000) == 0x90010000 || /* st rx,NUM(r1) */ 1180 (op & 0xfc1f0003) == 0xf8010000) && /* std rx,NUM(r1) */ 1181 (op & 0x03e00000) >= 0x01a00000)) /* rx >= r13 */ 1182 { 1183 1184 reg = GET_SRC_REG (op); 1185 if (fdata->saved_gpr == -1 || fdata->saved_gpr > reg) 1186 { 1187 fdata->saved_gpr = reg; 1188 if ((op & 0xfc1f0003) == 0xf8010000) 1189 op &= ~3UL; 1190 fdata->gpr_offset = SIGNED_SHORT (op) + offset; 1191 } 1192 continue; 1193 1194 } 1195 else if ((op & 0xffff0000) == 0x60000000) 1196 { 1197 /* nop */ 1198 /* Allow nops in the prologue, but do not consider them to 1199 be part of the prologue unless followed by other prologue 1200 instructions. */ 1201 prev_insn_was_prologue_insn = 0; 1202 continue; 1203 1204 } 1205 else if ((op & 0xffff0000) == 0x3c000000) 1206 { /* addis 0,0,NUM, used 1207 for >= 32k frames */ 1208 fdata->offset = (op & 0x0000ffff) << 16; 1209 fdata->frameless = 0; 1210 r0_contains_arg = 0; 1211 continue; 1212 1213 } 1214 else if ((op & 0xffff0000) == 0x60000000) 1215 { /* ori 0,0,NUM, 2nd ha 1216 lf of >= 32k frames */ 1217 fdata->offset |= (op & 0x0000ffff); 1218 fdata->frameless = 0; 1219 r0_contains_arg = 0; 1220 continue; 1221 1222 } 1223 else if (lr_reg >= 0 && 1224 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ 1225 (((op & 0xffff0000) == (lr_reg | 0xf8010000)) || 1226 /* stw Rx, NUM(r1) */ 1227 ((op & 0xffff0000) == (lr_reg | 0x90010000)) || 1228 /* stwu Rx, NUM(r1) */ 1229 ((op & 0xffff0000) == (lr_reg | 0x94010000)))) 1230 { /* where Rx == lr */ 1231 fdata->lr_offset = offset; 1232 fdata->nosavedpc = 0; 1233 /* Invalidate lr_reg, but don't set it to -1. 1234 That would mean that it had never been set. */ 1235 lr_reg = -2; 1236 if ((op & 0xfc000003) == 0xf8000000 || /* std */ 1237 (op & 0xfc000000) == 0x90000000) /* stw */ 1238 { 1239 /* Does not update r1, so add displacement to lr_offset. */ 1240 fdata->lr_offset += SIGNED_SHORT (op); 1241 } 1242 continue; 1243 1244 } 1245 else if (cr_reg >= 0 && 1246 /* std Rx, NUM(r1) || stdu Rx, NUM(r1) */ 1247 (((op & 0xffff0000) == (cr_reg | 0xf8010000)) || 1248 /* stw Rx, NUM(r1) */ 1249 ((op & 0xffff0000) == (cr_reg | 0x90010000)) || 1250 /* stwu Rx, NUM(r1) */ 1251 ((op & 0xffff0000) == (cr_reg | 0x94010000)))) 1252 { /* where Rx == cr */ 1253 fdata->cr_offset = offset; 1254 /* Invalidate cr_reg, but don't set it to -1. 1255 That would mean that it had never been set. */ 1256 cr_reg = -2; 1257 if ((op & 0xfc000003) == 0xf8000000 || 1258 (op & 0xfc000000) == 0x90000000) 1259 { 1260 /* Does not update r1, so add displacement to cr_offset. */ 1261 fdata->cr_offset += SIGNED_SHORT (op); 1262 } 1263 continue; 1264 1265 } 1266 else if ((op & 0xfe80ffff) == 0x42800005 && lr_reg != -1) 1267 { 1268 /* bcl 20,xx,.+4 is used to get the current PC, with or without 1269 prediction bits. If the LR has already been saved, we can 1270 skip it. */ 1271 continue; 1272 } 1273 else if (op == 0x48000005) 1274 { /* bl .+4 used in 1275 -mrelocatable */ 1276 continue; 1277 1278 } 1279 else if (op == 0x48000004) 1280 { /* b .+4 (xlc) */ 1281 break; 1282 1283 } 1284 else if ((op & 0xffff0000) == 0x3fc00000 || /* addis 30,0,foo@ha, used 1285 in V.4 -mminimal-toc */ 1286 (op & 0xffff0000) == 0x3bde0000) 1287 { /* addi 30,30,foo@l */ 1288 continue; 1289 1290 } 1291 else if ((op & 0xfc000001) == 0x48000001) 1292 { /* bl foo, 1293 to save fprs??? */ 1294 1295 fdata->frameless = 0; 1296 1297 /* If the return address has already been saved, we can skip 1298 calls to blrl (for PIC). */ 1299 if (lr_reg != -1 && bl_to_blrl_insn_p (pc, op)) 1300 continue; 1301 1302 /* Don't skip over the subroutine call if it is not within 1303 the first three instructions of the prologue and either 1304 we have no line table information or the line info tells 1305 us that the subroutine call is not part of the line 1306 associated with the prologue. */ 1307 if ((pc - orig_pc) > 8) 1308 { 1309 struct symtab_and_line prologue_sal = find_pc_line (orig_pc, 0); 1310 struct symtab_and_line this_sal = find_pc_line (pc, 0); 1311 1312 if ((prologue_sal.line == 0) || (prologue_sal.line != this_sal.line)) 1313 break; 1314 } 1315 1316 op = read_memory_integer (pc + 4, 4); 1317 1318 /* At this point, make sure this is not a trampoline 1319 function (a function that simply calls another functions, 1320 and nothing else). If the next is not a nop, this branch 1321 was part of the function prologue. */ 1322 1323 if (op == 0x4def7b82 || op == 0) /* crorc 15, 15, 15 */ 1324 break; /* don't skip over 1325 this branch */ 1326 continue; 1327 1328 } 1329 /* update stack pointer */ 1330 else if ((op & 0xfc1f0000) == 0x94010000) 1331 { /* stu rX,NUM(r1) || stwu rX,NUM(r1) */ 1332 fdata->frameless = 0; 1333 fdata->offset = SIGNED_SHORT (op); 1334 offset = fdata->offset; 1335 continue; 1336 } 1337 else if ((op & 0xfc1f016a) == 0x7c01016e) 1338 { /* stwux rX,r1,rY */ 1339 /* no way to figure out what r1 is going to be */ 1340 fdata->frameless = 0; 1341 offset = fdata->offset; 1342 continue; 1343 } 1344 else if ((op & 0xfc1f0003) == 0xf8010001) 1345 { /* stdu rX,NUM(r1) */ 1346 fdata->frameless = 0; 1347 fdata->offset = SIGNED_SHORT (op & ~3UL); 1348 offset = fdata->offset; 1349 continue; 1350 } 1351 else if ((op & 0xfc1f016a) == 0x7c01016a) 1352 { /* stdux rX,r1,rY */ 1353 /* no way to figure out what r1 is going to be */ 1354 fdata->frameless = 0; 1355 offset = fdata->offset; 1356 continue; 1357 } 1358 else if ((op & 0xffff0000) == 0x38210000) 1359 { /* addi r1,r1,SIMM */ 1360 fdata->frameless = 0; 1361 fdata->offset += SIGNED_SHORT (op); 1362 offset = fdata->offset; 1363 continue; 1364 } 1365 /* Load up minimal toc pointer. Do not treat an epilogue restore 1366 of r31 as a minimal TOC load. */ 1367 else if (((op >> 22) == 0x20f || /* l r31,... or l r30,... */ 1368 (op >> 22) == 0x3af) /* ld r31,... or ld r30,... */ 1369 && !framep 1370 && !minimal_toc_loaded) 1371 { 1372 minimal_toc_loaded = 1; 1373 continue; 1374 1375 /* move parameters from argument registers to local variable 1376 registers */ 1377 } 1378 else if ((op & 0xfc0007fe) == 0x7c000378 && /* mr(.) Rx,Ry */ 1379 (((op >> 21) & 31) >= 3) && /* R3 >= Ry >= R10 */ 1380 (((op >> 21) & 31) <= 10) && 1381 ((long) ((op >> 16) & 31) >= fdata->saved_gpr)) /* Rx: local var reg */ 1382 { 1383 continue; 1384 1385 /* store parameters in stack */ 1386 } 1387 /* Move parameters from argument registers to temporary register. */ 1388 else if (store_param_on_stack_p (op, framep, &r0_contains_arg)) 1389 { 1390 continue; 1391 1392 /* Set up frame pointer */ 1393 } 1394 else if (op == 0x603f0000 /* oril r31, r1, 0x0 */ 1395 || op == 0x7c3f0b78) 1396 { /* mr r31, r1 */ 1397 fdata->frameless = 0; 1398 framep = 1; 1399 fdata->alloca_reg = (tdep->ppc_gp0_regnum + 31); 1400 continue; 1401 1402 /* Another way to set up the frame pointer. */ 1403 } 1404 else if ((op & 0xfc1fffff) == 0x38010000) 1405 { /* addi rX, r1, 0x0 */ 1406 fdata->frameless = 0; 1407 framep = 1; 1408 fdata->alloca_reg = (tdep->ppc_gp0_regnum 1409 + ((op & ~0x38010000) >> 21)); 1410 continue; 1411 } 1412 /* AltiVec related instructions. */ 1413 /* Store the vrsave register (spr 256) in another register for 1414 later manipulation, or load a register into the vrsave 1415 register. 2 instructions are used: mfvrsave and 1416 mtvrsave. They are shorthand notation for mfspr Rn, SPR256 1417 and mtspr SPR256, Rn. */ 1418 /* mfspr Rn SPR256 == 011111 nnnnn 0000001000 01010100110 1419 mtspr SPR256 Rn == 011111 nnnnn 0000001000 01110100110 */ 1420 else if ((op & 0xfc1fffff) == 0x7c0042a6) /* mfvrsave Rn */ 1421 { 1422 vrsave_reg = GET_SRC_REG (op); 1423 continue; 1424 } 1425 else if ((op & 0xfc1fffff) == 0x7c0043a6) /* mtvrsave Rn */ 1426 { 1427 continue; 1428 } 1429 /* Store the register where vrsave was saved to onto the stack: 1430 rS is the register where vrsave was stored in a previous 1431 instruction. */ 1432 /* 100100 sssss 00001 dddddddd dddddddd */ 1433 else if ((op & 0xfc1f0000) == 0x90010000) /* stw rS, d(r1) */ 1434 { 1435 if (vrsave_reg == GET_SRC_REG (op)) 1436 { 1437 fdata->vrsave_offset = SIGNED_SHORT (op) + offset; 1438 vrsave_reg = -1; 1439 } 1440 continue; 1441 } 1442 /* Compute the new value of vrsave, by modifying the register 1443 where vrsave was saved to. */ 1444 else if (((op & 0xfc000000) == 0x64000000) /* oris Ra, Rs, UIMM */ 1445 || ((op & 0xfc000000) == 0x60000000))/* ori Ra, Rs, UIMM */ 1446 { 1447 continue; 1448 } 1449 /* li r0, SIMM (short for addi r0, 0, SIMM). This is the first 1450 in a pair of insns to save the vector registers on the 1451 stack. */ 1452 /* 001110 00000 00000 iiii iiii iiii iiii */ 1453 /* 001110 01110 00000 iiii iiii iiii iiii */ 1454 else if ((op & 0xffff0000) == 0x38000000 /* li r0, SIMM */ 1455 || (op & 0xffff0000) == 0x39c00000) /* li r14, SIMM */ 1456 { 1457 if ((op & 0xffff0000) == 0x38000000) 1458 r0_contains_arg = 0; 1459 li_found_pc = pc; 1460 vr_saved_offset = SIGNED_SHORT (op); 1461 1462 /* This insn by itself is not part of the prologue, unless 1463 if part of the pair of insns mentioned above. So do not 1464 record this insn as part of the prologue yet. */ 1465 prev_insn_was_prologue_insn = 0; 1466 } 1467 /* Store vector register S at (r31+r0) aligned to 16 bytes. */ 1468 /* 011111 sssss 11111 00000 00111001110 */ 1469 else if ((op & 0xfc1fffff) == 0x7c1f01ce) /* stvx Vs, R31, R0 */ 1470 { 1471 if (pc == (li_found_pc + 4)) 1472 { 1473 vr_reg = GET_SRC_REG (op); 1474 /* If this is the first vector reg to be saved, or if 1475 it has a lower number than others previously seen, 1476 reupdate the frame info. */ 1477 if (fdata->saved_vr == -1 || fdata->saved_vr > vr_reg) 1478 { 1479 fdata->saved_vr = vr_reg; 1480 fdata->vr_offset = vr_saved_offset + offset; 1481 } 1482 vr_saved_offset = -1; 1483 vr_reg = -1; 1484 li_found_pc = 0; 1485 } 1486 } 1487 /* End AltiVec related instructions. */ 1488 1489 /* Start BookE related instructions. */ 1490 /* Store gen register S at (r31+uimm). 1491 Any register less than r13 is volatile, so we don't care. */ 1492 /* 000100 sssss 11111 iiiii 01100100001 */ 1493 else if (arch_info->mach == bfd_mach_ppc_e500 1494 && (op & 0xfc1f07ff) == 0x101f0321) /* evstdd Rs,uimm(R31) */ 1495 { 1496 if ((op & 0x03e00000) >= 0x01a00000) /* Rs >= r13 */ 1497 { 1498 unsigned int imm; 1499 ev_reg = GET_SRC_REG (op); 1500 imm = (op >> 11) & 0x1f; 1501 ev_offset = imm * 8; 1502 /* If this is the first vector reg to be saved, or if 1503 it has a lower number than others previously seen, 1504 reupdate the frame info. */ 1505 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 1506 { 1507 fdata->saved_ev = ev_reg; 1508 fdata->ev_offset = ev_offset + offset; 1509 } 1510 } 1511 continue; 1512 } 1513 /* Store gen register rS at (r1+rB). */ 1514 /* 000100 sssss 00001 bbbbb 01100100000 */ 1515 else if (arch_info->mach == bfd_mach_ppc_e500 1516 && (op & 0xffe007ff) == 0x13e00320) /* evstddx RS,R1,Rb */ 1517 { 1518 if (pc == (li_found_pc + 4)) 1519 { 1520 ev_reg = GET_SRC_REG (op); 1521 /* If this is the first vector reg to be saved, or if 1522 it has a lower number than others previously seen, 1523 reupdate the frame info. */ 1524 /* We know the contents of rB from the previous instruction. */ 1525 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 1526 { 1527 fdata->saved_ev = ev_reg; 1528 fdata->ev_offset = vr_saved_offset + offset; 1529 } 1530 vr_saved_offset = -1; 1531 ev_reg = -1; 1532 li_found_pc = 0; 1533 } 1534 continue; 1535 } 1536 /* Store gen register r31 at (rA+uimm). */ 1537 /* 000100 11111 aaaaa iiiii 01100100001 */ 1538 else if (arch_info->mach == bfd_mach_ppc_e500 1539 && (op & 0xffe007ff) == 0x13e00321) /* evstdd R31,Ra,UIMM */ 1540 { 1541 /* Wwe know that the source register is 31 already, but 1542 it can't hurt to compute it. */ 1543 ev_reg = GET_SRC_REG (op); 1544 ev_offset = ((op >> 11) & 0x1f) * 8; 1545 /* If this is the first vector reg to be saved, or if 1546 it has a lower number than others previously seen, 1547 reupdate the frame info. */ 1548 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 1549 { 1550 fdata->saved_ev = ev_reg; 1551 fdata->ev_offset = ev_offset + offset; 1552 } 1553 1554 continue; 1555 } 1556 /* Store gen register S at (r31+r0). 1557 Store param on stack when offset from SP bigger than 4 bytes. */ 1558 /* 000100 sssss 11111 00000 01100100000 */ 1559 else if (arch_info->mach == bfd_mach_ppc_e500 1560 && (op & 0xfc1fffff) == 0x101f0320) /* evstddx Rs,R31,R0 */ 1561 { 1562 if (pc == (li_found_pc + 4)) 1563 { 1564 if ((op & 0x03e00000) >= 0x01a00000) 1565 { 1566 ev_reg = GET_SRC_REG (op); 1567 /* If this is the first vector reg to be saved, or if 1568 it has a lower number than others previously seen, 1569 reupdate the frame info. */ 1570 /* We know the contents of r0 from the previous 1571 instruction. */ 1572 if (fdata->saved_ev == -1 || fdata->saved_ev > ev_reg) 1573 { 1574 fdata->saved_ev = ev_reg; 1575 fdata->ev_offset = vr_saved_offset + offset; 1576 } 1577 ev_reg = -1; 1578 } 1579 vr_saved_offset = -1; 1580 li_found_pc = 0; 1581 continue; 1582 } 1583 } 1584 /* End BookE related instructions. */ 1585 1586 else 1587 { 1588 /* Not a recognized prologue instruction. 1589 Handle optimizer code motions into the prologue by continuing 1590 the search if we have no valid frame yet or if the return 1591 address is not yet saved in the frame. */ 1592 if (fdata->frameless == 0 && fdata->nosavedpc == 0) 1593 break; 1594 1595 if (op == 0x4e800020 /* blr */ 1596 || op == 0x4e800420) /* bctr */ 1597 /* Do not scan past epilogue in frameless functions or 1598 trampolines. */ 1599 break; 1600 if ((op & 0xf4000000) == 0x40000000) /* bxx */ 1601 /* Never skip branches. */ 1602 break; 1603 1604 if (num_skip_non_prologue_insns++ > max_skip_non_prologue_insns) 1605 /* Do not scan too many insns, scanning insns is expensive with 1606 remote targets. */ 1607 break; 1608 1609 /* Continue scanning. */ 1610 prev_insn_was_prologue_insn = 0; 1611 continue; 1612 } 1613 } 1614 1615#if 0 1616/* I have problems with skipping over __main() that I need to address 1617 * sometime. Previously, I used to use misc_function_vector which 1618 * didn't work as well as I wanted to be. -MGO */ 1619 1620 /* If the first thing after skipping a prolog is a branch to a function, 1621 this might be a call to an initializer in main(), introduced by gcc2. 1622 We'd like to skip over it as well. Fortunately, xlc does some extra 1623 work before calling a function right after a prologue, thus we can 1624 single out such gcc2 behaviour. */ 1625 1626 1627 if ((op & 0xfc000001) == 0x48000001) 1628 { /* bl foo, an initializer function? */ 1629 op = read_memory_integer (pc + 4, 4); 1630 1631 if (op == 0x4def7b82) 1632 { /* cror 0xf, 0xf, 0xf (nop) */ 1633 1634 /* Check and see if we are in main. If so, skip over this 1635 initializer function as well. */ 1636 1637 tmp = find_pc_misc_function (pc); 1638 if (tmp >= 0 1639 && strcmp (misc_function_vector[tmp].name, main_name ()) == 0) 1640 return pc + 8; 1641 } 1642 } 1643#endif /* 0 */ 1644 1645 fdata->offset = -fdata->offset; 1646 return last_prologue_pc; 1647} 1648 1649 1650/************************************************************************* 1651 Support for creating pushing a dummy frame into the stack, and popping 1652 frames, etc. 1653*************************************************************************/ 1654 1655 1656/* All the ABI's require 16 byte alignment. */ 1657static CORE_ADDR 1658rs6000_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr) 1659{ 1660 return (addr & -16); 1661} 1662 1663/* Pass the arguments in either registers, or in the stack. In RS/6000, 1664 the first eight words of the argument list (that might be less than 1665 eight parameters if some parameters occupy more than one word) are 1666 passed in r3..r10 registers. float and double parameters are 1667 passed in fpr's, in addition to that. Rest of the parameters if any 1668 are passed in user stack. There might be cases in which half of the 1669 parameter is copied into registers, the other half is pushed into 1670 stack. 1671 1672 Stack must be aligned on 64-bit boundaries when synthesizing 1673 function calls. 1674 1675 If the function is returning a structure, then the return address is passed 1676 in r3, then the first 7 words of the parameters can be passed in registers, 1677 starting from r4. */ 1678 1679static CORE_ADDR 1680rs6000_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 1681 struct regcache *regcache, CORE_ADDR bp_addr, 1682 int nargs, struct value **args, CORE_ADDR sp, 1683 int struct_return, CORE_ADDR struct_addr) 1684{ 1685 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1686 int ii; 1687 int len = 0; 1688 int argno; /* current argument number */ 1689 int argbytes; /* current argument byte */ 1690 gdb_byte tmp_buffer[50]; 1691 int f_argno = 0; /* current floating point argno */ 1692 int wordsize = gdbarch_tdep (current_gdbarch)->wordsize; 1693 CORE_ADDR func_addr = find_function_addr (function, NULL); 1694 1695 struct value *arg = 0; 1696 struct type *type; 1697 1698 ULONGEST saved_sp; 1699 1700 /* The calling convention this function implements assumes the 1701 processor has floating-point registers. We shouldn't be using it 1702 on PPC variants that lack them. */ 1703 gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); 1704 1705 /* The first eight words of ther arguments are passed in registers. 1706 Copy them appropriately. */ 1707 ii = 0; 1708 1709 /* If the function is returning a `struct', then the first word 1710 (which will be passed in r3) is used for struct return address. 1711 In that case we should advance one word and start from r4 1712 register to copy parameters. */ 1713 if (struct_return) 1714 { 1715 regcache_raw_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, 1716 struct_addr); 1717 ii++; 1718 } 1719 1720/* 1721 effectively indirect call... gcc does... 1722 1723 return_val example( float, int); 1724 1725 eabi: 1726 float in fp0, int in r3 1727 offset of stack on overflow 8/16 1728 for varargs, must go by type. 1729 power open: 1730 float in r3&r4, int in r5 1731 offset of stack on overflow different 1732 both: 1733 return in r3 or f0. If no float, must study how gcc emulates floats; 1734 pay attention to arg promotion. 1735 User may have to cast\args to handle promotion correctly 1736 since gdb won't know if prototype supplied or not. 1737 */ 1738 1739 for (argno = 0, argbytes = 0; argno < nargs && ii < 8; ++ii) 1740 { 1741 int reg_size = register_size (current_gdbarch, ii + 3); 1742 1743 arg = args[argno]; 1744 type = check_typedef (value_type (arg)); 1745 len = TYPE_LENGTH (type); 1746 1747 if (TYPE_CODE (type) == TYPE_CODE_FLT) 1748 { 1749 1750 /* Floating point arguments are passed in fpr's, as well as gpr's. 1751 There are 13 fpr's reserved for passing parameters. At this point 1752 there is no way we would run out of them. */ 1753 1754 gdb_assert (len <= 8); 1755 1756 regcache_cooked_write (regcache, 1757 tdep->ppc_fp0_regnum + 1 + f_argno, 1758 value_contents (arg)); 1759 ++f_argno; 1760 } 1761 1762 if (len > reg_size) 1763 { 1764 1765 /* Argument takes more than one register. */ 1766 while (argbytes < len) 1767 { 1768 gdb_byte word[MAX_REGISTER_SIZE]; 1769 memset (word, 0, reg_size); 1770 memcpy (word, 1771 ((char *) value_contents (arg)) + argbytes, 1772 (len - argbytes) > reg_size 1773 ? reg_size : len - argbytes); 1774 regcache_cooked_write (regcache, 1775 tdep->ppc_gp0_regnum + 3 + ii, 1776 word); 1777 ++ii, argbytes += reg_size; 1778 1779 if (ii >= 8) 1780 goto ran_out_of_registers_for_arguments; 1781 } 1782 argbytes = 0; 1783 --ii; 1784 } 1785 else 1786 { 1787 /* Argument can fit in one register. No problem. */ 1788 int adj = gdbarch_byte_order (current_gdbarch) 1789 == BFD_ENDIAN_BIG ? reg_size - len : 0; 1790 gdb_byte word[MAX_REGISTER_SIZE]; 1791 1792 memset (word, 0, reg_size); 1793 memcpy (word, value_contents (arg), len); 1794 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3 +ii, word); 1795 } 1796 ++argno; 1797 } 1798 1799ran_out_of_registers_for_arguments: 1800 1801 regcache_cooked_read_unsigned (regcache, 1802 gdbarch_sp_regnum (current_gdbarch), 1803 &saved_sp); 1804 1805 /* Location for 8 parameters are always reserved. */ 1806 sp -= wordsize * 8; 1807 1808 /* Another six words for back chain, TOC register, link register, etc. */ 1809 sp -= wordsize * 6; 1810 1811 /* Stack pointer must be quadword aligned. */ 1812 sp &= -16; 1813 1814 /* If there are more arguments, allocate space for them in 1815 the stack, then push them starting from the ninth one. */ 1816 1817 if ((argno < nargs) || argbytes) 1818 { 1819 int space = 0, jj; 1820 1821 if (argbytes) 1822 { 1823 space += ((len - argbytes + 3) & -4); 1824 jj = argno + 1; 1825 } 1826 else 1827 jj = argno; 1828 1829 for (; jj < nargs; ++jj) 1830 { 1831 struct value *val = args[jj]; 1832 space += ((TYPE_LENGTH (value_type (val))) + 3) & -4; 1833 } 1834 1835 /* Add location required for the rest of the parameters. */ 1836 space = (space + 15) & -16; 1837 sp -= space; 1838 1839 /* This is another instance we need to be concerned about 1840 securing our stack space. If we write anything underneath %sp 1841 (r1), we might conflict with the kernel who thinks he is free 1842 to use this area. So, update %sp first before doing anything 1843 else. */ 1844 1845 regcache_raw_write_signed (regcache, 1846 gdbarch_sp_regnum (current_gdbarch), sp); 1847 1848 /* If the last argument copied into the registers didn't fit there 1849 completely, push the rest of it into stack. */ 1850 1851 if (argbytes) 1852 { 1853 write_memory (sp + 24 + (ii * 4), 1854 value_contents (arg) + argbytes, 1855 len - argbytes); 1856 ++argno; 1857 ii += ((len - argbytes + 3) & -4) / 4; 1858 } 1859 1860 /* Push the rest of the arguments into stack. */ 1861 for (; argno < nargs; ++argno) 1862 { 1863 1864 arg = args[argno]; 1865 type = check_typedef (value_type (arg)); 1866 len = TYPE_LENGTH (type); 1867 1868 1869 /* Float types should be passed in fpr's, as well as in the 1870 stack. */ 1871 if (TYPE_CODE (type) == TYPE_CODE_FLT && f_argno < 13) 1872 { 1873 1874 gdb_assert (len <= 8); 1875 1876 regcache_cooked_write (regcache, 1877 tdep->ppc_fp0_regnum + 1 + f_argno, 1878 value_contents (arg)); 1879 ++f_argno; 1880 } 1881 1882 write_memory (sp + 24 + (ii * 4), value_contents (arg), len); 1883 ii += ((len + 3) & -4) / 4; 1884 } 1885 } 1886 1887 /* Set the stack pointer. According to the ABI, the SP is meant to 1888 be set _before_ the corresponding stack space is used. On AIX, 1889 this even applies when the target has been completely stopped! 1890 Not doing this can lead to conflicts with the kernel which thinks 1891 that it still has control over this not-yet-allocated stack 1892 region. */ 1893 regcache_raw_write_signed (regcache, gdbarch_sp_regnum (current_gdbarch), sp); 1894 1895 /* Set back chain properly. */ 1896 store_unsigned_integer (tmp_buffer, wordsize, saved_sp); 1897 write_memory (sp, tmp_buffer, wordsize); 1898 1899 /* Point the inferior function call's return address at the dummy's 1900 breakpoint. */ 1901 regcache_raw_write_signed (regcache, tdep->ppc_lr_regnum, bp_addr); 1902 1903 /* Set the TOC register, get the value from the objfile reader 1904 which, in turn, gets it from the VMAP table. */ 1905 if (rs6000_find_toc_address_hook != NULL) 1906 { 1907 CORE_ADDR tocvalue = (*rs6000_find_toc_address_hook) (func_addr); 1908 regcache_raw_write_signed (regcache, tdep->ppc_toc_regnum, tocvalue); 1909 } 1910 1911 target_store_registers (regcache, -1); 1912 return sp; 1913} 1914 1915static enum return_value_convention 1916rs6000_return_value (struct gdbarch *gdbarch, struct type *valtype, 1917 struct regcache *regcache, gdb_byte *readbuf, 1918 const gdb_byte *writebuf) 1919{ 1920 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 1921 gdb_byte buf[8]; 1922 1923 /* The calling convention this function implements assumes the 1924 processor has floating-point registers. We shouldn't be using it 1925 on PowerPC variants that lack them. */ 1926 gdb_assert (ppc_floating_point_unit_p (current_gdbarch)); 1927 1928 /* AltiVec extension: Functions that declare a vector data type as a 1929 return value place that return value in VR2. */ 1930 if (TYPE_CODE (valtype) == TYPE_CODE_ARRAY && TYPE_VECTOR (valtype) 1931 && TYPE_LENGTH (valtype) == 16) 1932 { 1933 if (readbuf) 1934 regcache_cooked_read (regcache, tdep->ppc_vr0_regnum + 2, readbuf); 1935 if (writebuf) 1936 regcache_cooked_write (regcache, tdep->ppc_vr0_regnum + 2, writebuf); 1937 1938 return RETURN_VALUE_REGISTER_CONVENTION; 1939 } 1940 1941 /* If the called subprogram returns an aggregate, there exists an 1942 implicit first argument, whose value is the address of a caller- 1943 allocated buffer into which the callee is assumed to store its 1944 return value. All explicit parameters are appropriately 1945 relabeled. */ 1946 if (TYPE_CODE (valtype) == TYPE_CODE_STRUCT 1947 || TYPE_CODE (valtype) == TYPE_CODE_UNION 1948 || TYPE_CODE (valtype) == TYPE_CODE_ARRAY) 1949 return RETURN_VALUE_STRUCT_CONVENTION; 1950 1951 /* Scalar floating-point values are returned in FPR1 for float or 1952 double, and in FPR1:FPR2 for quadword precision. Fortran 1953 complex*8 and complex*16 are returned in FPR1:FPR2, and 1954 complex*32 is returned in FPR1:FPR4. */ 1955 if (TYPE_CODE (valtype) == TYPE_CODE_FLT 1956 && (TYPE_LENGTH (valtype) == 4 || TYPE_LENGTH (valtype) == 8)) 1957 { 1958 struct type *regtype = register_type (gdbarch, tdep->ppc_fp0_regnum); 1959 gdb_byte regval[8]; 1960 1961 /* FIXME: kettenis/2007-01-01: Add support for quadword 1962 precision and complex. */ 1963 1964 if (readbuf) 1965 { 1966 regcache_cooked_read (regcache, tdep->ppc_fp0_regnum + 1, regval); 1967 convert_typed_floating (regval, regtype, readbuf, valtype); 1968 } 1969 if (writebuf) 1970 { 1971 convert_typed_floating (writebuf, valtype, regval, regtype); 1972 regcache_cooked_write (regcache, tdep->ppc_fp0_regnum + 1, regval); 1973 } 1974 1975 return RETURN_VALUE_REGISTER_CONVENTION; 1976 } 1977 1978 /* Values of the types int, long, short, pointer, and char (length 1979 is less than or equal to four bytes), as well as bit values of 1980 lengths less than or equal to 32 bits, must be returned right 1981 justified in GPR3 with signed values sign extended and unsigned 1982 values zero extended, as necessary. */ 1983 if (TYPE_LENGTH (valtype) <= tdep->wordsize) 1984 { 1985 if (readbuf) 1986 { 1987 ULONGEST regval; 1988 1989 /* For reading we don't have to worry about sign extension. */ 1990 regcache_cooked_read_unsigned (regcache, tdep->ppc_gp0_regnum + 3, 1991 ®val); 1992 store_unsigned_integer (readbuf, TYPE_LENGTH (valtype), regval); 1993 } 1994 if (writebuf) 1995 { 1996 /* For writing, use unpack_long since that should handle any 1997 required sign extension. */ 1998 regcache_cooked_write_unsigned (regcache, tdep->ppc_gp0_regnum + 3, 1999 unpack_long (valtype, writebuf)); 2000 } 2001 2002 return RETURN_VALUE_REGISTER_CONVENTION; 2003 } 2004 2005 /* Eight-byte non-floating-point scalar values must be returned in 2006 GPR3:GPR4. */ 2007 2008 if (TYPE_LENGTH (valtype) == 8) 2009 { 2010 gdb_assert (TYPE_CODE (valtype) != TYPE_CODE_FLT); 2011 gdb_assert (tdep->wordsize == 4); 2012 2013 if (readbuf) 2014 { 2015 gdb_byte regval[8]; 2016 2017 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 3, regval); 2018 regcache_cooked_read (regcache, tdep->ppc_gp0_regnum + 4, 2019 regval + 4); 2020 memcpy (readbuf, regval, 8); 2021 } 2022 if (writebuf) 2023 { 2024 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 3, writebuf); 2025 regcache_cooked_write (regcache, tdep->ppc_gp0_regnum + 4, 2026 writebuf + 4); 2027 } 2028 2029 return RETURN_VALUE_REGISTER_CONVENTION; 2030 } 2031 2032 return RETURN_VALUE_STRUCT_CONVENTION; 2033} 2034 2035/* Return whether handle_inferior_event() should proceed through code 2036 starting at PC in function NAME when stepping. 2037 2038 The AIX -bbigtoc linker option generates functions @FIX0, @FIX1, etc. to 2039 handle memory references that are too distant to fit in instructions 2040 generated by the compiler. For example, if 'foo' in the following 2041 instruction: 2042 2043 lwz r9,foo(r2) 2044 2045 is greater than 32767, the linker might replace the lwz with a branch to 2046 somewhere in @FIX1 that does the load in 2 instructions and then branches 2047 back to where execution should continue. 2048 2049 GDB should silently step over @FIX code, just like AIX dbx does. 2050 Unfortunately, the linker uses the "b" instruction for the 2051 branches, meaning that the link register doesn't get set. 2052 Therefore, GDB's usual step_over_function () mechanism won't work. 2053 2054 Instead, use the gdbarch_skip_trampoline_code and 2055 gdbarch_skip_trampoline_code hooks in handle_inferior_event() to skip past 2056 @FIX code. */ 2057 2058int 2059rs6000_in_solib_return_trampoline (CORE_ADDR pc, char *name) 2060{ 2061 return name && !strncmp (name, "@FIX", 4); 2062} 2063 2064/* Skip code that the user doesn't want to see when stepping: 2065 2066 1. Indirect function calls use a piece of trampoline code to do context 2067 switching, i.e. to set the new TOC table. Skip such code if we are on 2068 its first instruction (as when we have single-stepped to here). 2069 2070 2. Skip shared library trampoline code (which is different from 2071 indirect function call trampolines). 2072 2073 3. Skip bigtoc fixup code. 2074 2075 Result is desired PC to step until, or NULL if we are not in 2076 code that should be skipped. */ 2077 2078CORE_ADDR 2079rs6000_skip_trampoline_code (struct frame_info *frame, CORE_ADDR pc) 2080{ 2081 unsigned int ii, op; 2082 int rel; 2083 CORE_ADDR solib_target_pc; 2084 struct minimal_symbol *msymbol; 2085 2086 static unsigned trampoline_code[] = 2087 { 2088 0x800b0000, /* l r0,0x0(r11) */ 2089 0x90410014, /* st r2,0x14(r1) */ 2090 0x7c0903a6, /* mtctr r0 */ 2091 0x804b0004, /* l r2,0x4(r11) */ 2092 0x816b0008, /* l r11,0x8(r11) */ 2093 0x4e800420, /* bctr */ 2094 0x4e800020, /* br */ 2095 0 2096 }; 2097 2098 /* Check for bigtoc fixup code. */ 2099 msymbol = lookup_minimal_symbol_by_pc (pc); 2100 if (msymbol 2101 && rs6000_in_solib_return_trampoline (pc, 2102 DEPRECATED_SYMBOL_NAME (msymbol))) 2103 { 2104 /* Double-check that the third instruction from PC is relative "b". */ 2105 op = read_memory_integer (pc + 8, 4); 2106 if ((op & 0xfc000003) == 0x48000000) 2107 { 2108 /* Extract bits 6-29 as a signed 24-bit relative word address and 2109 add it to the containing PC. */ 2110 rel = ((int)(op << 6) >> 6); 2111 return pc + 8 + rel; 2112 } 2113 } 2114 2115 /* If pc is in a shared library trampoline, return its target. */ 2116 solib_target_pc = find_solib_trampoline_target (frame, pc); 2117 if (solib_target_pc) 2118 return solib_target_pc; 2119 2120 for (ii = 0; trampoline_code[ii]; ++ii) 2121 { 2122 op = read_memory_integer (pc + (ii * 4), 4); 2123 if (op != trampoline_code[ii]) 2124 return 0; 2125 } 2126 ii = get_frame_register_unsigned (frame, 11); /* r11 holds destination addr */ 2127 pc = read_memory_addr (ii, gdbarch_tdep (current_gdbarch)->wordsize); /* (r11) value */ 2128 return pc; 2129} 2130 2131/* ISA-specific vector types. */ 2132 2133static struct type * 2134rs6000_builtin_type_vec64 (struct gdbarch *gdbarch) 2135{ 2136 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2137 2138 if (!tdep->ppc_builtin_type_vec64) 2139 { 2140 /* The type we're building is this: */ 2141#if 0 2142 union __gdb_builtin_type_vec64 2143 { 2144 int64_t uint64; 2145 float v2_float[2]; 2146 int32_t v2_int32[2]; 2147 int16_t v4_int16[4]; 2148 int8_t v8_int8[8]; 2149 }; 2150#endif 2151 2152 struct type *t; 2153 2154 t = init_composite_type ("__ppc_builtin_type_vec64", TYPE_CODE_UNION); 2155 append_composite_type_field (t, "uint64", builtin_type_int64); 2156 append_composite_type_field (t, "v2_float", 2157 init_vector_type (builtin_type_float, 2)); 2158 append_composite_type_field (t, "v2_int32", 2159 init_vector_type (builtin_type_int32, 2)); 2160 append_composite_type_field (t, "v4_int16", 2161 init_vector_type (builtin_type_int16, 4)); 2162 append_composite_type_field (t, "v8_int8", 2163 init_vector_type (builtin_type_int8, 8)); 2164 2165 TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; 2166 TYPE_NAME (t) = "ppc_builtin_type_vec64"; 2167 tdep->ppc_builtin_type_vec64 = t; 2168 } 2169 2170 return tdep->ppc_builtin_type_vec64; 2171} 2172 2173static struct type * 2174rs6000_builtin_type_vec128 (struct gdbarch *gdbarch) 2175{ 2176 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2177 2178 if (!tdep->ppc_builtin_type_vec128) 2179 { 2180 /* The type we're building is this: */ 2181#if 0 2182 union __gdb_builtin_type_vec128 2183 { 2184 int128_t uint128; 2185 float v4_float[4]; 2186 int32_t v4_int32[4]; 2187 int16_t v8_int16[8]; 2188 int8_t v16_int8[16]; 2189 }; 2190#endif 2191 2192 struct type *t; 2193 2194 t = init_composite_type ("__ppc_builtin_type_vec128", TYPE_CODE_UNION); 2195 append_composite_type_field (t, "uint128", builtin_type_int128); 2196 append_composite_type_field (t, "v4_float", 2197 init_vector_type (builtin_type_float, 4)); 2198 append_composite_type_field (t, "v4_int32", 2199 init_vector_type (builtin_type_int32, 4)); 2200 append_composite_type_field (t, "v8_int16", 2201 init_vector_type (builtin_type_int16, 8)); 2202 append_composite_type_field (t, "v16_int8", 2203 init_vector_type (builtin_type_int8, 16)); 2204 2205 TYPE_FLAGS (t) |= TYPE_FLAG_VECTOR; 2206 TYPE_NAME (t) = "ppc_builtin_type_vec128"; 2207 tdep->ppc_builtin_type_vec128 = t; 2208 } 2209 2210 return tdep->ppc_builtin_type_vec128; 2211} 2212 2213/* Return the size of register REG when words are WORDSIZE bytes long. If REG 2214 isn't available with that word size, return 0. */ 2215 2216static int 2217regsize (const struct reg *reg, int wordsize) 2218{ 2219 return wordsize == 8 ? reg->sz64 : reg->sz32; 2220} 2221 2222/* Return the name of register number N, or null if no such register exists 2223 in the current architecture. */ 2224 2225static const char * 2226rs6000_register_name (int n) 2227{ 2228 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2229 const struct reg *reg = tdep->regs + n; 2230 2231 if (!regsize (reg, tdep->wordsize)) 2232 return NULL; 2233 return reg->name; 2234} 2235 2236/* Return the GDB type object for the "standard" data type 2237 of data in register N. */ 2238 2239static struct type * 2240rs6000_register_type (struct gdbarch *gdbarch, int n) 2241{ 2242 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2243 const struct reg *reg = tdep->regs + n; 2244 2245 if (reg->fpr) 2246 return builtin_type_double; 2247 else 2248 { 2249 int size = regsize (reg, tdep->wordsize); 2250 switch (size) 2251 { 2252 case 0: 2253 return builtin_type_int0; 2254 case 4: 2255 return builtin_type_uint32; 2256 case 8: 2257 if (tdep->ppc_ev0_regnum <= n && n <= tdep->ppc_ev31_regnum) 2258 return rs6000_builtin_type_vec64 (gdbarch); 2259 else 2260 return builtin_type_uint64; 2261 break; 2262 case 16: 2263 return rs6000_builtin_type_vec128 (gdbarch); 2264 break; 2265 default: 2266 internal_error (__FILE__, __LINE__, _("Register %d size %d unknown"), 2267 n, size); 2268 } 2269 } 2270} 2271 2272/* Is REGNUM a member of REGGROUP? */ 2273static int 2274rs6000_register_reggroup_p (struct gdbarch *gdbarch, int regnum, 2275 struct reggroup *group) 2276{ 2277 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2278 int float_p; 2279 int vector_p; 2280 int general_p; 2281 2282 if (gdbarch_register_name (current_gdbarch, regnum) == NULL 2283 || *gdbarch_register_name (current_gdbarch, regnum) == '\0') 2284 return 0; 2285 if (group == all_reggroup) 2286 return 1; 2287 2288 float_p = (regnum == tdep->ppc_fpscr_regnum 2289 || (regnum >= tdep->ppc_fp0_regnum 2290 && regnum < tdep->ppc_fp0_regnum + 32)); 2291 if (group == float_reggroup) 2292 return float_p; 2293 2294 vector_p = ((tdep->ppc_vr0_regnum >= 0 2295 && regnum >= tdep->ppc_vr0_regnum 2296 && regnum < tdep->ppc_vr0_regnum + 32) 2297 || (tdep->ppc_ev0_regnum >= 0 2298 && regnum >= tdep->ppc_ev0_regnum 2299 && regnum < tdep->ppc_ev0_regnum + 32) 2300 || regnum == tdep->ppc_vrsave_regnum - 1 /* vscr */ 2301 || regnum == tdep->ppc_vrsave_regnum 2302 || regnum == tdep->ppc_acc_regnum 2303 || regnum == tdep->ppc_spefscr_regnum); 2304 if (group == vector_reggroup) 2305 return vector_p; 2306 2307 /* Note that PS aka MSR isn't included - it's a system register (and 2308 besides, due to GCC's CFI foobar you do not want to restore 2309 it). */ 2310 general_p = ((regnum >= tdep->ppc_gp0_regnum 2311 && regnum < tdep->ppc_gp0_regnum + 32) 2312 || regnum == tdep->ppc_toc_regnum 2313 || regnum == tdep->ppc_cr_regnum 2314 || regnum == tdep->ppc_lr_regnum 2315 || regnum == tdep->ppc_ctr_regnum 2316 || regnum == tdep->ppc_xer_regnum 2317 || regnum == gdbarch_pc_regnum (current_gdbarch)); 2318 if (group == general_reggroup) 2319 return general_p; 2320 2321 if (group == save_reggroup || group == restore_reggroup) 2322 return general_p || vector_p || float_p; 2323 2324 return 0; 2325} 2326 2327/* The register format for RS/6000 floating point registers is always 2328 double, we need a conversion if the memory format is float. */ 2329 2330static int 2331rs6000_convert_register_p (int regnum, struct type *type) 2332{ 2333 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; 2334 2335 return (reg->fpr 2336 && TYPE_CODE (type) == TYPE_CODE_FLT 2337 && TYPE_LENGTH (type) != TYPE_LENGTH (builtin_type_double)); 2338} 2339 2340static void 2341rs6000_register_to_value (struct frame_info *frame, 2342 int regnum, 2343 struct type *type, 2344 gdb_byte *to) 2345{ 2346 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; 2347 gdb_byte from[MAX_REGISTER_SIZE]; 2348 2349 gdb_assert (reg->fpr); 2350 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); 2351 2352 get_frame_register (frame, regnum, from); 2353 convert_typed_floating (from, builtin_type_double, to, type); 2354} 2355 2356static void 2357rs6000_value_to_register (struct frame_info *frame, 2358 int regnum, 2359 struct type *type, 2360 const gdb_byte *from) 2361{ 2362 const struct reg *reg = gdbarch_tdep (current_gdbarch)->regs + regnum; 2363 gdb_byte to[MAX_REGISTER_SIZE]; 2364 2365 gdb_assert (reg->fpr); 2366 gdb_assert (TYPE_CODE (type) == TYPE_CODE_FLT); 2367 2368 convert_typed_floating (from, type, to, builtin_type_double); 2369 put_frame_register (frame, regnum, to); 2370} 2371 2372/* Move SPE vector register values between a 64-bit buffer and the two 2373 32-bit raw register halves in a regcache. This function handles 2374 both splitting a 64-bit value into two 32-bit halves, and joining 2375 two halves into a whole 64-bit value, depending on the function 2376 passed as the MOVE argument. 2377 2378 EV_REG must be the number of an SPE evN vector register --- a 2379 pseudoregister. REGCACHE must be a regcache, and BUFFER must be a 2380 64-bit buffer. 2381 2382 Call MOVE once for each 32-bit half of that register, passing 2383 REGCACHE, the number of the raw register corresponding to that 2384 half, and the address of the appropriate half of BUFFER. 2385 2386 For example, passing 'regcache_raw_read' as the MOVE function will 2387 fill BUFFER with the full 64-bit contents of EV_REG. Or, passing 2388 'regcache_raw_supply' will supply the contents of BUFFER to the 2389 appropriate pair of raw registers in REGCACHE. 2390 2391 You may need to cast away some 'const' qualifiers when passing 2392 MOVE, since this function can't tell at compile-time which of 2393 REGCACHE or BUFFER is acting as the source of the data. If C had 2394 co-variant type qualifiers, ... */ 2395static void 2396e500_move_ev_register (void (*move) (struct regcache *regcache, 2397 int regnum, gdb_byte *buf), 2398 struct regcache *regcache, int ev_reg, 2399 gdb_byte *buffer) 2400{ 2401 struct gdbarch *arch = get_regcache_arch (regcache); 2402 struct gdbarch_tdep *tdep = gdbarch_tdep (arch); 2403 int reg_index; 2404 gdb_byte *byte_buffer = buffer; 2405 2406 gdb_assert (tdep->ppc_ev0_regnum <= ev_reg 2407 && ev_reg < tdep->ppc_ev0_regnum + ppc_num_gprs); 2408 2409 reg_index = ev_reg - tdep->ppc_ev0_regnum; 2410 2411 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) 2412 { 2413 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer); 2414 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer + 4); 2415 } 2416 else 2417 { 2418 move (regcache, tdep->ppc_gp0_regnum + reg_index, byte_buffer); 2419 move (regcache, tdep->ppc_ev0_upper_regnum + reg_index, byte_buffer + 4); 2420 } 2421} 2422 2423static void 2424e500_pseudo_register_read (struct gdbarch *gdbarch, struct regcache *regcache, 2425 int reg_nr, gdb_byte *buffer) 2426{ 2427 struct gdbarch *regcache_arch = get_regcache_arch (regcache); 2428 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2429 2430 gdb_assert (regcache_arch == gdbarch); 2431 2432 if (tdep->ppc_ev0_regnum <= reg_nr 2433 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) 2434 e500_move_ev_register (regcache_raw_read, regcache, reg_nr, buffer); 2435 else 2436 internal_error (__FILE__, __LINE__, 2437 _("e500_pseudo_register_read: " 2438 "called on unexpected register '%s' (%d)"), 2439 gdbarch_register_name (gdbarch, reg_nr), reg_nr); 2440} 2441 2442static void 2443e500_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache, 2444 int reg_nr, const gdb_byte *buffer) 2445{ 2446 struct gdbarch *regcache_arch = get_regcache_arch (regcache); 2447 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2448 2449 gdb_assert (regcache_arch == gdbarch); 2450 2451 if (tdep->ppc_ev0_regnum <= reg_nr 2452 && reg_nr < tdep->ppc_ev0_regnum + ppc_num_gprs) 2453 e500_move_ev_register ((void (*) (struct regcache *, int, gdb_byte *)) 2454 regcache_raw_write, 2455 regcache, reg_nr, (gdb_byte *) buffer); 2456 else 2457 internal_error (__FILE__, __LINE__, 2458 _("e500_pseudo_register_read: " 2459 "called on unexpected register '%s' (%d)"), 2460 gdbarch_register_name (gdbarch, reg_nr), reg_nr); 2461} 2462 2463/* The E500 needs a custom reggroup function: it has anonymous raw 2464 registers, and default_register_reggroup_p assumes that anonymous 2465 registers are not members of any reggroup. */ 2466static int 2467e500_register_reggroup_p (struct gdbarch *gdbarch, 2468 int regnum, 2469 struct reggroup *group) 2470{ 2471 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 2472 2473 /* The save and restore register groups need to include the 2474 upper-half registers, even though they're anonymous. */ 2475 if ((group == save_reggroup 2476 || group == restore_reggroup) 2477 && (tdep->ppc_ev0_upper_regnum <= regnum 2478 && regnum < tdep->ppc_ev0_upper_regnum + ppc_num_gprs)) 2479 return 1; 2480 2481 /* In all other regards, the default reggroup definition is fine. */ 2482 return default_register_reggroup_p (gdbarch, regnum, group); 2483} 2484 2485/* Convert a DBX STABS register number to a GDB register number. */ 2486static int 2487rs6000_stab_reg_to_regnum (int num) 2488{ 2489 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2490 2491 if (0 <= num && num <= 31) 2492 return tdep->ppc_gp0_regnum + num; 2493 else if (32 <= num && num <= 63) 2494 /* FIXME: jimb/2004-05-05: What should we do when the debug info 2495 specifies registers the architecture doesn't have? Our 2496 callers don't check the value we return. */ 2497 return tdep->ppc_fp0_regnum + (num - 32); 2498 else if (77 <= num && num <= 108) 2499 return tdep->ppc_vr0_regnum + (num - 77); 2500 else if (1200 <= num && num < 1200 + 32) 2501 return tdep->ppc_ev0_regnum + (num - 1200); 2502 else 2503 switch (num) 2504 { 2505 case 64: 2506 return tdep->ppc_mq_regnum; 2507 case 65: 2508 return tdep->ppc_lr_regnum; 2509 case 66: 2510 return tdep->ppc_ctr_regnum; 2511 case 76: 2512 return tdep->ppc_xer_regnum; 2513 case 109: 2514 return tdep->ppc_vrsave_regnum; 2515 case 110: 2516 return tdep->ppc_vrsave_regnum - 1; /* vscr */ 2517 case 111: 2518 return tdep->ppc_acc_regnum; 2519 case 112: 2520 return tdep->ppc_spefscr_regnum; 2521 default: 2522 return num; 2523 } 2524} 2525 2526 2527/* Convert a Dwarf 2 register number to a GDB register number. */ 2528static int 2529rs6000_dwarf2_reg_to_regnum (int num) 2530{ 2531 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 2532 2533 if (0 <= num && num <= 31) 2534 return tdep->ppc_gp0_regnum + num; 2535 else if (32 <= num && num <= 63) 2536 /* FIXME: jimb/2004-05-05: What should we do when the debug info 2537 specifies registers the architecture doesn't have? Our 2538 callers don't check the value we return. */ 2539 return tdep->ppc_fp0_regnum + (num - 32); 2540 else if (1124 <= num && num < 1124 + 32) 2541 return tdep->ppc_vr0_regnum + (num - 1124); 2542 else if (1200 <= num && num < 1200 + 32) 2543 return tdep->ppc_ev0_regnum + (num - 1200); 2544 else 2545 switch (num) 2546 { 2547 case 64: 2548 return tdep->ppc_cr_regnum; 2549 case 67: 2550 return tdep->ppc_vrsave_regnum - 1; /* vscr */ 2551 case 99: 2552 return tdep->ppc_acc_regnum; 2553 case 100: 2554 return tdep->ppc_mq_regnum; 2555 case 101: 2556 return tdep->ppc_xer_regnum; 2557 case 108: 2558 return tdep->ppc_lr_regnum; 2559 case 109: 2560 return tdep->ppc_ctr_regnum; 2561 case 356: 2562 return tdep->ppc_vrsave_regnum; 2563 case 612: 2564 return tdep->ppc_spefscr_regnum; 2565 default: 2566 return num; 2567 } 2568} 2569 2570/* Translate a .eh_frame register to DWARF register, or adjust a 2571 .debug_frame register. */ 2572 2573static int 2574rs6000_adjust_frame_regnum (struct gdbarch *gdbarch, int num, int eh_frame_p) 2575{ 2576 /* GCC releases before 3.4 use GCC internal register numbering in 2577 .debug_frame (and .debug_info, et cetera). The numbering is 2578 different from the standard SysV numbering for everything except 2579 for GPRs and FPRs. We can not detect this problem in most cases 2580 - to get accurate debug info for variables living in lr, ctr, v0, 2581 et cetera, use a newer version of GCC. But we must detect 2582 one important case - lr is in column 65 in .debug_frame output, 2583 instead of 108. 2584 2585 GCC 3.4, and the "hammer" branch, have a related problem. They 2586 record lr register saves in .debug_frame as 108, but still record 2587 the return column as 65. We fix that up too. 2588 2589 We can do this because 65 is assigned to fpsr, and GCC never 2590 generates debug info referring to it. To add support for 2591 handwritten debug info that restores fpsr, we would need to add a 2592 producer version check to this. */ 2593 if (!eh_frame_p) 2594 { 2595 if (num == 65) 2596 return 108; 2597 else 2598 return num; 2599 } 2600 2601 /* .eh_frame is GCC specific. For binary compatibility, it uses GCC 2602 internal register numbering; translate that to the standard DWARF2 2603 register numbering. */ 2604 if (0 <= num && num <= 63) /* r0-r31,fp0-fp31 */ 2605 return num; 2606 else if (68 <= num && num <= 75) /* cr0-cr8 */ 2607 return num - 68 + 86; 2608 else if (77 <= num && num <= 108) /* vr0-vr31 */ 2609 return num - 77 + 1124; 2610 else 2611 switch (num) 2612 { 2613 case 64: /* mq */ 2614 return 100; 2615 case 65: /* lr */ 2616 return 108; 2617 case 66: /* ctr */ 2618 return 109; 2619 case 76: /* xer */ 2620 return 101; 2621 case 109: /* vrsave */ 2622 return 356; 2623 case 110: /* vscr */ 2624 return 67; 2625 case 111: /* spe_acc */ 2626 return 99; 2627 case 112: /* spefscr */ 2628 return 612; 2629 default: 2630 return num; 2631 } 2632} 2633 2634/* Support for CONVERT_FROM_FUNC_PTR_ADDR (ARCH, ADDR, TARG). 2635 2636 Usually a function pointer's representation is simply the address 2637 of the function. On the RS/6000 however, a function pointer is 2638 represented by a pointer to an OPD entry. This OPD entry contains 2639 three words, the first word is the address of the function, the 2640 second word is the TOC pointer (r2), and the third word is the 2641 static chain value. Throughout GDB it is currently assumed that a 2642 function pointer contains the address of the function, which is not 2643 easy to fix. In addition, the conversion of a function address to 2644 a function pointer would require allocation of an OPD entry in the 2645 inferior's memory space, with all its drawbacks. To be able to 2646 call C++ virtual methods in the inferior (which are called via 2647 function pointers), find_function_addr uses this function to get the 2648 function address from a function pointer. */ 2649 2650/* Return real function address if ADDR (a function pointer) is in the data 2651 space and is therefore a special function pointer. */ 2652 2653static CORE_ADDR 2654rs6000_convert_from_func_ptr_addr (struct gdbarch *gdbarch, 2655 CORE_ADDR addr, 2656 struct target_ops *targ) 2657{ 2658 struct obj_section *s; 2659 2660 s = find_pc_section (addr); 2661 if (s && s->the_bfd_section->flags & SEC_CODE) 2662 return addr; 2663 2664 /* ADDR is in the data space, so it's a special function pointer. */ 2665 return read_memory_addr (addr, gdbarch_tdep (gdbarch)->wordsize); 2666} 2667 2668 2669/* Handling the various POWER/PowerPC variants. */ 2670 2671 2672/* The arrays here called registers_MUMBLE hold information about available 2673 registers. 2674 2675 For each family of PPC variants, I've tried to isolate out the 2676 common registers and put them up front, so that as long as you get 2677 the general family right, GDB will correctly identify the registers 2678 common to that family. The common register sets are: 2679 2680 For the 60x family: hid0 hid1 iabr dabr pir 2681 2682 For the 505 and 860 family: eie eid nri 2683 2684 For the 403 and 403GC: icdbdr esr dear evpr cdbcr tsr tcr pit tbhi 2685 tblo srr2 srr3 dbsr dbcr iac1 iac2 dac1 dac2 dccr iccr pbl1 2686 pbu1 pbl2 pbu2 2687 2688 Most of these register groups aren't anything formal. I arrived at 2689 them by looking at the registers that occurred in more than one 2690 processor. 2691 2692 Note: kevinb/2002-04-30: Support for the fpscr register was added 2693 during April, 2002. Slot 70 is being used for PowerPC and slot 71 2694 for Power. For PowerPC, slot 70 was unused and was already in the 2695 PPC_UISA_SPRS which is ideally where fpscr should go. For Power, 2696 slot 70 was being used for "mq", so the next available slot (71) 2697 was chosen. It would have been nice to be able to make the 2698 register numbers the same across processor cores, but this wasn't 2699 possible without either 1) renumbering some registers for some 2700 processors or 2) assigning fpscr to a really high slot that's 2701 larger than any current register number. Doing (1) is bad because 2702 existing stubs would break. Doing (2) is undesirable because it 2703 would introduce a really large gap between fpscr and the rest of 2704 the registers for most processors. */ 2705 2706/* Convenience macros for populating register arrays. */ 2707 2708/* Within another macro, convert S to a string. */ 2709 2710#define STR(s) #s 2711 2712/* Return a struct reg defining register NAME that's 32 bits on 32-bit systems 2713 and 64 bits on 64-bit systems. */ 2714#define R(name) { STR(name), 4, 8, 0, 0, -1 } 2715 2716/* Return a struct reg defining register NAME that's 32 bits on all 2717 systems. */ 2718#define R4(name) { STR(name), 4, 4, 0, 0, -1 } 2719 2720/* Return a struct reg defining register NAME that's 64 bits on all 2721 systems. */ 2722#define R8(name) { STR(name), 8, 8, 0, 0, -1 } 2723 2724/* Return a struct reg defining register NAME that's 128 bits on all 2725 systems. */ 2726#define R16(name) { STR(name), 16, 16, 0, 0, -1 } 2727 2728/* Return a struct reg defining floating-point register NAME. */ 2729#define F(name) { STR(name), 8, 8, 1, 0, -1 } 2730 2731/* Return a struct reg defining a pseudo register NAME that is 64 bits 2732 long on all systems. */ 2733#define P8(name) { STR(name), 8, 8, 0, 1, -1 } 2734 2735/* Return a struct reg defining register NAME that's 32 bits on 32-bit 2736 systems and that doesn't exist on 64-bit systems. */ 2737#define R32(name) { STR(name), 4, 0, 0, 0, -1 } 2738 2739/* Return a struct reg defining register NAME that's 64 bits on 64-bit 2740 systems and that doesn't exist on 32-bit systems. */ 2741#define R64(name) { STR(name), 0, 8, 0, 0, -1 } 2742 2743/* Return a struct reg placeholder for a register that doesn't exist. */ 2744#define R0 { 0, 0, 0, 0, 0, -1 } 2745 2746/* Return a struct reg defining an anonymous raw register that's 32 2747 bits on all systems. */ 2748#define A4 { 0, 4, 4, 0, 0, -1 } 2749 2750/* Return a struct reg defining an SPR named NAME that is 32 bits on 2751 32-bit systems and 64 bits on 64-bit systems. */ 2752#define S(name) { STR(name), 4, 8, 0, 0, ppc_spr_ ## name } 2753 2754/* Return a struct reg defining an SPR named NAME that is 32 bits on 2755 all systems. */ 2756#define S4(name) { STR(name), 4, 4, 0, 0, ppc_spr_ ## name } 2757 2758/* Return a struct reg defining an SPR named NAME that is 32 bits on 2759 all systems, and whose SPR number is NUMBER. */ 2760#define SN4(name, number) { STR(name), 4, 4, 0, 0, (number) } 2761 2762/* Return a struct reg defining an SPR named NAME that's 64 bits on 2763 64-bit systems and that doesn't exist on 32-bit systems. */ 2764#define S64(name) { STR(name), 0, 8, 0, 0, ppc_spr_ ## name } 2765 2766/* UISA registers common across all architectures, including POWER. */ 2767 2768#define COMMON_UISA_REGS \ 2769 /* 0 */ R(r0), R(r1), R(r2), R(r3), R(r4), R(r5), R(r6), R(r7), \ 2770 /* 8 */ R(r8), R(r9), R(r10),R(r11),R(r12),R(r13),R(r14),R(r15), \ 2771 /* 16 */ R(r16),R(r17),R(r18),R(r19),R(r20),R(r21),R(r22),R(r23), \ 2772 /* 24 */ R(r24),R(r25),R(r26),R(r27),R(r28),R(r29),R(r30),R(r31), \ 2773 /* 32 */ F(f0), F(f1), F(f2), F(f3), F(f4), F(f5), F(f6), F(f7), \ 2774 /* 40 */ F(f8), F(f9), F(f10),F(f11),F(f12),F(f13),F(f14),F(f15), \ 2775 /* 48 */ F(f16),F(f17),F(f18),F(f19),F(f20),F(f21),F(f22),F(f23), \ 2776 /* 56 */ F(f24),F(f25),F(f26),F(f27),F(f28),F(f29),F(f30),F(f31), \ 2777 /* 64 */ R(pc), R(ps) 2778 2779/* UISA-level SPRs for PowerPC. */ 2780#define PPC_UISA_SPRS \ 2781 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R4(fpscr) 2782 2783/* UISA-level SPRs for PowerPC without floating point support. */ 2784#define PPC_UISA_NOFP_SPRS \ 2785 /* 66 */ R4(cr), S(lr), S(ctr), S4(xer), R0 2786 2787/* Segment registers, for PowerPC. */ 2788#define PPC_SEGMENT_REGS \ 2789 /* 71 */ R32(sr0), R32(sr1), R32(sr2), R32(sr3), \ 2790 /* 75 */ R32(sr4), R32(sr5), R32(sr6), R32(sr7), \ 2791 /* 79 */ R32(sr8), R32(sr9), R32(sr10), R32(sr11), \ 2792 /* 83 */ R32(sr12), R32(sr13), R32(sr14), R32(sr15) 2793 2794/* OEA SPRs for PowerPC. */ 2795#define PPC_OEA_SPRS \ 2796 /* 87 */ S4(pvr), \ 2797 /* 88 */ S(ibat0u), S(ibat0l), S(ibat1u), S(ibat1l), \ 2798 /* 92 */ S(ibat2u), S(ibat2l), S(ibat3u), S(ibat3l), \ 2799 /* 96 */ S(dbat0u), S(dbat0l), S(dbat1u), S(dbat1l), \ 2800 /* 100 */ S(dbat2u), S(dbat2l), S(dbat3u), S(dbat3l), \ 2801 /* 104 */ S(sdr1), S64(asr), S(dar), S4(dsisr), \ 2802 /* 108 */ S(sprg0), S(sprg1), S(sprg2), S(sprg3), \ 2803 /* 112 */ S(srr0), S(srr1), S(tbl), S(tbu), \ 2804 /* 116 */ S4(dec), S(dabr), S4(ear) 2805 2806/* AltiVec registers. */ 2807#define PPC_ALTIVEC_REGS \ 2808 /*119*/R16(vr0), R16(vr1), R16(vr2), R16(vr3), R16(vr4), R16(vr5), R16(vr6), R16(vr7), \ 2809 /*127*/R16(vr8), R16(vr9), R16(vr10),R16(vr11),R16(vr12),R16(vr13),R16(vr14),R16(vr15), \ 2810 /*135*/R16(vr16),R16(vr17),R16(vr18),R16(vr19),R16(vr20),R16(vr21),R16(vr22),R16(vr23), \ 2811 /*143*/R16(vr24),R16(vr25),R16(vr26),R16(vr27),R16(vr28),R16(vr29),R16(vr30),R16(vr31), \ 2812 /*151*/R4(vscr), R4(vrsave) 2813 2814 2815/* On machines supporting the SPE APU, the general-purpose registers 2816 are 64 bits long. There are SIMD vector instructions to treat them 2817 as pairs of floats, but the rest of the instruction set treats them 2818 as 32-bit registers, and only operates on their lower halves. 2819 2820 In the GDB regcache, we treat their high and low halves as separate 2821 registers. The low halves we present as the general-purpose 2822 registers, and then we have pseudo-registers that stitch together 2823 the upper and lower halves and present them as pseudo-registers. */ 2824 2825/* SPE GPR lower halves --- raw registers. */ 2826#define PPC_SPE_GP_REGS \ 2827 /* 0 */ R4(r0), R4(r1), R4(r2), R4(r3), R4(r4), R4(r5), R4(r6), R4(r7), \ 2828 /* 8 */ R4(r8), R4(r9), R4(r10),R4(r11),R4(r12),R4(r13),R4(r14),R4(r15), \ 2829 /* 16 */ R4(r16),R4(r17),R4(r18),R4(r19),R4(r20),R4(r21),R4(r22),R4(r23), \ 2830 /* 24 */ R4(r24),R4(r25),R4(r26),R4(r27),R4(r28),R4(r29),R4(r30),R4(r31) 2831 2832/* SPE GPR upper halves --- anonymous raw registers. */ 2833#define PPC_SPE_UPPER_GP_REGS \ 2834 /* 0 */ A4, A4, A4, A4, A4, A4, A4, A4, \ 2835 /* 8 */ A4, A4, A4, A4, A4, A4, A4, A4, \ 2836 /* 16 */ A4, A4, A4, A4, A4, A4, A4, A4, \ 2837 /* 24 */ A4, A4, A4, A4, A4, A4, A4, A4 2838 2839/* SPE GPR vector registers --- pseudo registers based on underlying 2840 gprs and the anonymous upper half raw registers. */ 2841#define PPC_EV_PSEUDO_REGS \ 2842/* 0*/P8(ev0), P8(ev1), P8(ev2), P8(ev3), P8(ev4), P8(ev5), P8(ev6), P8(ev7), \ 2843/* 8*/P8(ev8), P8(ev9), P8(ev10),P8(ev11),P8(ev12),P8(ev13),P8(ev14),P8(ev15),\ 2844/*16*/P8(ev16),P8(ev17),P8(ev18),P8(ev19),P8(ev20),P8(ev21),P8(ev22),P8(ev23),\ 2845/*24*/P8(ev24),P8(ev25),P8(ev26),P8(ev27),P8(ev28),P8(ev29),P8(ev30),P8(ev31) 2846 2847/* IBM POWER (pre-PowerPC) architecture, user-level view. We only cover 2848 user-level SPR's. */ 2849static const struct reg registers_power[] = 2850{ 2851 COMMON_UISA_REGS, 2852 /* 66 */ R4(cnd), S(lr), S(cnt), S4(xer), S4(mq), 2853 /* 71 */ R4(fpscr) 2854}; 2855 2856/* PowerPC UISA - a PPC processor as viewed by user-level code. A UISA-only 2857 view of the PowerPC. */ 2858static const struct reg registers_powerpc[] = 2859{ 2860 COMMON_UISA_REGS, 2861 PPC_UISA_SPRS, 2862 PPC_ALTIVEC_REGS 2863}; 2864 2865/* IBM PowerPC 403. 2866 2867 Some notes about the "tcr" special-purpose register: 2868 - On the 403 and 403GC, SPR 986 is named "tcr", and it controls the 2869 403's programmable interval timer, fixed interval timer, and 2870 watchdog timer. 2871 - On the 602, SPR 984 is named "tcr", and it controls the 602's 2872 watchdog timer, and nothing else. 2873 2874 Some of the fields are similar between the two, but they're not 2875 compatible with each other. Since the two variants have different 2876 registers, with different numbers, but the same name, we can't 2877 splice the register name to get the SPR number. */ 2878static const struct reg registers_403[] = 2879{ 2880 COMMON_UISA_REGS, 2881 PPC_UISA_SPRS, 2882 PPC_SEGMENT_REGS, 2883 PPC_OEA_SPRS, 2884 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), 2885 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), 2886 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), 2887 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), 2888 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), 2889 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2) 2890}; 2891 2892/* IBM PowerPC 403GC. 2893 See the comments about 'tcr' for the 403, above. */ 2894static const struct reg registers_403GC[] = 2895{ 2896 COMMON_UISA_REGS, 2897 PPC_UISA_SPRS, 2898 PPC_SEGMENT_REGS, 2899 PPC_OEA_SPRS, 2900 /* 119 */ S(icdbdr), S(esr), S(dear), S(evpr), 2901 /* 123 */ S(cdbcr), S(tsr), SN4(tcr, ppc_spr_403_tcr), S(pit), 2902 /* 127 */ S(tbhi), S(tblo), S(srr2), S(srr3), 2903 /* 131 */ S(dbsr), S(dbcr), S(iac1), S(iac2), 2904 /* 135 */ S(dac1), S(dac2), S(dccr), S(iccr), 2905 /* 139 */ S(pbl1), S(pbu1), S(pbl2), S(pbu2), 2906 /* 143 */ S(zpr), S(pid), S(sgr), S(dcwr), 2907 /* 147 */ S(tbhu), S(tblu) 2908}; 2909 2910/* Motorola PowerPC 505. */ 2911static const struct reg registers_505[] = 2912{ 2913 COMMON_UISA_REGS, 2914 PPC_UISA_SPRS, 2915 PPC_SEGMENT_REGS, 2916 PPC_OEA_SPRS, 2917 /* 119 */ S(eie), S(eid), S(nri) 2918}; 2919 2920/* Motorola PowerPC 860 or 850. */ 2921static const struct reg registers_860[] = 2922{ 2923 COMMON_UISA_REGS, 2924 PPC_UISA_SPRS, 2925 PPC_SEGMENT_REGS, 2926 PPC_OEA_SPRS, 2927 /* 119 */ S(eie), S(eid), S(nri), S(cmpa), 2928 /* 123 */ S(cmpb), S(cmpc), S(cmpd), S(icr), 2929 /* 127 */ S(der), S(counta), S(countb), S(cmpe), 2930 /* 131 */ S(cmpf), S(cmpg), S(cmph), S(lctrl1), 2931 /* 135 */ S(lctrl2), S(ictrl), S(bar), S(ic_cst), 2932 /* 139 */ S(ic_adr), S(ic_dat), S(dc_cst), S(dc_adr), 2933 /* 143 */ S(dc_dat), S(dpdr), S(dpir), S(immr), 2934 /* 147 */ S(mi_ctr), S(mi_ap), S(mi_epn), S(mi_twc), 2935 /* 151 */ S(mi_rpn), S(md_ctr), S(m_casid), S(md_ap), 2936 /* 155 */ S(md_epn), S(m_twb), S(md_twc), S(md_rpn), 2937 /* 159 */ S(m_tw), S(mi_dbcam), S(mi_dbram0), S(mi_dbram1), 2938 /* 163 */ S(md_dbcam), S(md_dbram0), S(md_dbram1) 2939}; 2940 2941/* Motorola PowerPC 601. Note that the 601 has different register numbers 2942 for reading and writing RTCU and RTCL. However, how one reads and writes a 2943 register is the stub's problem. */ 2944static const struct reg registers_601[] = 2945{ 2946 COMMON_UISA_REGS, 2947 PPC_UISA_SPRS, 2948 PPC_SEGMENT_REGS, 2949 PPC_OEA_SPRS, 2950 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), 2951 /* 123 */ S(pir), S(mq), S(rtcu), S(rtcl) 2952}; 2953 2954/* Motorola PowerPC 602. 2955 See the notes under the 403 about 'tcr'. */ 2956static const struct reg registers_602[] = 2957{ 2958 COMMON_UISA_REGS, 2959 PPC_UISA_SPRS, 2960 PPC_SEGMENT_REGS, 2961 PPC_OEA_SPRS, 2962 /* 119 */ S(hid0), S(hid1), S(iabr), R0, 2963 /* 123 */ R0, SN4(tcr, ppc_spr_602_tcr), S(ibr), S(esasrr), 2964 /* 127 */ S(sebr), S(ser), S(sp), S(lt) 2965}; 2966 2967/* Motorola/IBM PowerPC 603 or 603e. */ 2968static const struct reg registers_603[] = 2969{ 2970 COMMON_UISA_REGS, 2971 PPC_UISA_SPRS, 2972 PPC_SEGMENT_REGS, 2973 PPC_OEA_SPRS, 2974 /* 119 */ S(hid0), S(hid1), S(iabr), R0, 2975 /* 123 */ R0, S(dmiss), S(dcmp), S(hash1), 2976 /* 127 */ S(hash2), S(imiss), S(icmp), S(rpa) 2977}; 2978 2979/* Motorola PowerPC 604 or 604e. */ 2980static const struct reg registers_604[] = 2981{ 2982 COMMON_UISA_REGS, 2983 PPC_UISA_SPRS, 2984 PPC_SEGMENT_REGS, 2985 PPC_OEA_SPRS, 2986 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), 2987 /* 123 */ S(pir), S(mmcr0), S(pmc1), S(pmc2), 2988 /* 127 */ S(sia), S(sda) 2989}; 2990 2991/* Motorola/IBM PowerPC 750 or 740. */ 2992static const struct reg registers_750[] = 2993{ 2994 COMMON_UISA_REGS, 2995 PPC_UISA_SPRS, 2996 PPC_SEGMENT_REGS, 2997 PPC_OEA_SPRS, 2998 /* 119 */ S(hid0), S(hid1), S(iabr), S(dabr), 2999 /* 123 */ R0, S(ummcr0), S(upmc1), S(upmc2), 3000 /* 127 */ S(usia), S(ummcr1), S(upmc3), S(upmc4), 3001 /* 131 */ S(mmcr0), S(pmc1), S(pmc2), S(sia), 3002 /* 135 */ S(mmcr1), S(pmc3), S(pmc4), S(l2cr), 3003 /* 139 */ S(ictc), S(thrm1), S(thrm2), S(thrm3) 3004}; 3005 3006 3007/* Motorola PowerPC 7400. */ 3008static const struct reg registers_7400[] = 3009{ 3010 /* gpr0-gpr31, fpr0-fpr31 */ 3011 COMMON_UISA_REGS, 3012 /* cr, lr, ctr, xer, fpscr */ 3013 PPC_UISA_SPRS, 3014 /* sr0-sr15 */ 3015 PPC_SEGMENT_REGS, 3016 PPC_OEA_SPRS, 3017 /* vr0-vr31, vrsave, vscr */ 3018 PPC_ALTIVEC_REGS 3019 /* FIXME? Add more registers? */ 3020}; 3021 3022/* Motorola e500. */ 3023static const struct reg registers_e500[] = 3024{ 3025 /* 0 .. 31 */ PPC_SPE_GP_REGS, 3026 /* 32 .. 63 */ PPC_SPE_UPPER_GP_REGS, 3027 /* 64 .. 65 */ R(pc), R(ps), 3028 /* 66 .. 70 */ PPC_UISA_NOFP_SPRS, 3029 /* 71 .. 72 */ R8(acc), S4(spefscr), 3030 /* NOTE: Add new registers here the end of the raw register 3031 list and just before the first pseudo register. */ 3032 /* 73 .. 104 */ PPC_EV_PSEUDO_REGS 3033}; 3034 3035/* Information about a particular processor variant. */ 3036 3037struct variant 3038 { 3039 /* Name of this variant. */ 3040 char *name; 3041 3042 /* English description of the variant. */ 3043 char *description; 3044 3045 /* bfd_arch_info.arch corresponding to variant. */ 3046 enum bfd_architecture arch; 3047 3048 /* bfd_arch_info.mach corresponding to variant. */ 3049 unsigned long mach; 3050 3051 /* Number of real registers. */ 3052 int nregs; 3053 3054 /* Number of pseudo registers. */ 3055 int npregs; 3056 3057 /* Number of total registers (the sum of nregs and npregs). */ 3058 int num_tot_regs; 3059 3060 /* Table of register names; registers[R] is the name of the register 3061 number R. */ 3062 const struct reg *regs; 3063 }; 3064 3065#define tot_num_registers(list) (sizeof (list) / sizeof((list)[0])) 3066 3067static int 3068num_registers (const struct reg *reg_list, int num_tot_regs) 3069{ 3070 int i; 3071 int nregs = 0; 3072 3073 for (i = 0; i < num_tot_regs; i++) 3074 if (!reg_list[i].pseudo) 3075 nregs++; 3076 3077 return nregs; 3078} 3079 3080static int 3081num_pseudo_registers (const struct reg *reg_list, int num_tot_regs) 3082{ 3083 int i; 3084 int npregs = 0; 3085 3086 for (i = 0; i < num_tot_regs; i++) 3087 if (reg_list[i].pseudo) 3088 npregs ++; 3089 3090 return npregs; 3091} 3092 3093/* Information in this table comes from the following web sites: 3094 IBM: http://www.chips.ibm.com:80/products/embedded/ 3095 Motorola: http://www.mot.com/SPS/PowerPC/ 3096 3097 I'm sure I've got some of the variant descriptions not quite right. 3098 Please report any inaccuracies you find to GDB's maintainer. 3099 3100 If you add entries to this table, please be sure to allow the new 3101 value as an argument to the --with-cpu flag, in configure.in. */ 3102 3103static struct variant variants[] = 3104{ 3105 3106 {"powerpc", "PowerPC user-level", bfd_arch_powerpc, 3107 bfd_mach_ppc, -1, -1, tot_num_registers (registers_powerpc), 3108 registers_powerpc}, 3109 {"power", "POWER user-level", bfd_arch_rs6000, 3110 bfd_mach_rs6k, -1, -1, tot_num_registers (registers_power), 3111 registers_power}, 3112 {"403", "IBM PowerPC 403", bfd_arch_powerpc, 3113 bfd_mach_ppc_403, -1, -1, tot_num_registers (registers_403), 3114 registers_403}, 3115 {"601", "Motorola PowerPC 601", bfd_arch_powerpc, 3116 bfd_mach_ppc_601, -1, -1, tot_num_registers (registers_601), 3117 registers_601}, 3118 {"602", "Motorola PowerPC 602", bfd_arch_powerpc, 3119 bfd_mach_ppc_602, -1, -1, tot_num_registers (registers_602), 3120 registers_602}, 3121 {"603", "Motorola/IBM PowerPC 603 or 603e", bfd_arch_powerpc, 3122 bfd_mach_ppc_603, -1, -1, tot_num_registers (registers_603), 3123 registers_603}, 3124 {"604", "Motorola PowerPC 604 or 604e", bfd_arch_powerpc, 3125 604, -1, -1, tot_num_registers (registers_604), 3126 registers_604}, 3127 {"403GC", "IBM PowerPC 403GC", bfd_arch_powerpc, 3128 bfd_mach_ppc_403gc, -1, -1, tot_num_registers (registers_403GC), 3129 registers_403GC}, 3130 {"505", "Motorola PowerPC 505", bfd_arch_powerpc, 3131 bfd_mach_ppc_505, -1, -1, tot_num_registers (registers_505), 3132 registers_505}, 3133 {"860", "Motorola PowerPC 860 or 850", bfd_arch_powerpc, 3134 bfd_mach_ppc_860, -1, -1, tot_num_registers (registers_860), 3135 registers_860}, 3136 {"750", "Motorola/IBM PowerPC 750 or 740", bfd_arch_powerpc, 3137 bfd_mach_ppc_750, -1, -1, tot_num_registers (registers_750), 3138 registers_750}, 3139 {"7400", "Motorola/IBM PowerPC 7400 (G4)", bfd_arch_powerpc, 3140 bfd_mach_ppc_7400, -1, -1, tot_num_registers (registers_7400), 3141 registers_7400}, 3142 {"e500", "Motorola PowerPC e500", bfd_arch_powerpc, 3143 bfd_mach_ppc_e500, -1, -1, tot_num_registers (registers_e500), 3144 registers_e500}, 3145 3146 /* 64-bit */ 3147 {"powerpc64", "PowerPC 64-bit user-level", bfd_arch_powerpc, 3148 bfd_mach_ppc64, -1, -1, tot_num_registers (registers_powerpc), 3149 registers_powerpc}, 3150 {"620", "Motorola PowerPC 620", bfd_arch_powerpc, 3151 bfd_mach_ppc_620, -1, -1, tot_num_registers (registers_powerpc), 3152 registers_powerpc}, 3153 {"630", "Motorola PowerPC 630", bfd_arch_powerpc, 3154 bfd_mach_ppc_630, -1, -1, tot_num_registers (registers_powerpc), 3155 registers_powerpc}, 3156 {"a35", "PowerPC A35", bfd_arch_powerpc, 3157 bfd_mach_ppc_a35, -1, -1, tot_num_registers (registers_powerpc), 3158 registers_powerpc}, 3159 {"rs64ii", "PowerPC rs64ii", bfd_arch_powerpc, 3160 bfd_mach_ppc_rs64ii, -1, -1, tot_num_registers (registers_powerpc), 3161 registers_powerpc}, 3162 {"rs64iii", "PowerPC rs64iii", bfd_arch_powerpc, 3163 bfd_mach_ppc_rs64iii, -1, -1, tot_num_registers (registers_powerpc), 3164 registers_powerpc}, 3165 3166 /* FIXME: I haven't checked the register sets of the following. */ 3167 {"rs1", "IBM POWER RS1", bfd_arch_rs6000, 3168 bfd_mach_rs6k_rs1, -1, -1, tot_num_registers (registers_power), 3169 registers_power}, 3170 {"rsc", "IBM POWER RSC", bfd_arch_rs6000, 3171 bfd_mach_rs6k_rsc, -1, -1, tot_num_registers (registers_power), 3172 registers_power}, 3173 {"rs2", "IBM POWER RS2", bfd_arch_rs6000, 3174 bfd_mach_rs6k_rs2, -1, -1, tot_num_registers (registers_power), 3175 registers_power}, 3176 3177 {0, 0, 0, 0, 0, 0, 0, 0} 3178}; 3179 3180/* Initialize the number of registers and pseudo registers in each variant. */ 3181 3182static void 3183init_variants (void) 3184{ 3185 struct variant *v; 3186 3187 for (v = variants; v->name; v++) 3188 { 3189 if (v->nregs == -1) 3190 v->nregs = num_registers (v->regs, v->num_tot_regs); 3191 if (v->npregs == -1) 3192 v->npregs = num_pseudo_registers (v->regs, v->num_tot_regs); 3193 } 3194} 3195 3196/* Return the variant corresponding to architecture ARCH and machine number 3197 MACH. If no such variant exists, return null. */ 3198 3199static const struct variant * 3200find_variant_by_arch (enum bfd_architecture arch, unsigned long mach) 3201{ 3202 const struct variant *v; 3203 3204 for (v = variants; v->name; v++) 3205 if (arch == v->arch && mach == v->mach) 3206 return v; 3207 3208 return NULL; 3209} 3210 3211static int 3212gdb_print_insn_powerpc (bfd_vma memaddr, disassemble_info *info) 3213{ 3214 if (!info->disassembler_options) 3215 info->disassembler_options = "any"; 3216 3217 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) 3218 return print_insn_big_powerpc (memaddr, info); 3219 else 3220 return print_insn_little_powerpc (memaddr, info); 3221} 3222 3223static CORE_ADDR 3224rs6000_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 3225{ 3226 return frame_unwind_register_unsigned (next_frame, 3227 gdbarch_pc_regnum (current_gdbarch)); 3228} 3229 3230static struct frame_id 3231rs6000_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 3232{ 3233 return frame_id_build (frame_unwind_register_unsigned 3234 (next_frame, gdbarch_sp_regnum (current_gdbarch)), 3235 frame_pc_unwind (next_frame)); 3236} 3237 3238struct rs6000_frame_cache 3239{ 3240 CORE_ADDR base; 3241 CORE_ADDR initial_sp; 3242 struct trad_frame_saved_reg *saved_regs; 3243}; 3244 3245static struct rs6000_frame_cache * 3246rs6000_frame_cache (struct frame_info *next_frame, void **this_cache) 3247{ 3248 struct rs6000_frame_cache *cache; 3249 struct gdbarch *gdbarch = get_frame_arch (next_frame); 3250 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3251 struct rs6000_framedata fdata; 3252 int wordsize = tdep->wordsize; 3253 CORE_ADDR func, pc; 3254 3255 if ((*this_cache) != NULL) 3256 return (*this_cache); 3257 cache = FRAME_OBSTACK_ZALLOC (struct rs6000_frame_cache); 3258 (*this_cache) = cache; 3259 cache->saved_regs = trad_frame_alloc_saved_regs (next_frame); 3260 3261 func = frame_func_unwind (next_frame, NORMAL_FRAME); 3262 pc = frame_pc_unwind (next_frame); 3263 skip_prologue (func, pc, &fdata); 3264 3265 /* Figure out the parent's stack pointer. */ 3266 3267 /* NOTE: cagney/2002-04-14: The ->frame points to the inner-most 3268 address of the current frame. Things might be easier if the 3269 ->frame pointed to the outer-most address of the frame. In 3270 the mean time, the address of the prev frame is used as the 3271 base address of this frame. */ 3272 cache->base = frame_unwind_register_unsigned 3273 (next_frame, gdbarch_sp_regnum (current_gdbarch)); 3274 3275 /* If the function appears to be frameless, check a couple of likely 3276 indicators that we have simply failed to find the frame setup. 3277 Two common cases of this are missing symbols (i.e. 3278 frame_func_unwind returns the wrong address or 0), and assembly 3279 stubs which have a fast exit path but set up a frame on the slow 3280 path. 3281 3282 If the LR appears to return to this function, then presume that 3283 we have an ABI compliant frame that we failed to find. */ 3284 if (fdata.frameless && fdata.lr_offset == 0) 3285 { 3286 CORE_ADDR saved_lr; 3287 int make_frame = 0; 3288 3289 saved_lr = frame_unwind_register_unsigned (next_frame, 3290 tdep->ppc_lr_regnum); 3291 if (func == 0 && saved_lr == pc) 3292 make_frame = 1; 3293 else if (func != 0) 3294 { 3295 CORE_ADDR saved_func = get_pc_function_start (saved_lr); 3296 if (func == saved_func) 3297 make_frame = 1; 3298 } 3299 3300 if (make_frame) 3301 { 3302 fdata.frameless = 0; 3303 fdata.lr_offset = tdep->lr_frame_offset; 3304 } 3305 } 3306 3307 if (!fdata.frameless) 3308 /* Frameless really means stackless. */ 3309 cache->base = read_memory_addr (cache->base, wordsize); 3310 3311 trad_frame_set_value (cache->saved_regs, 3312 gdbarch_sp_regnum (current_gdbarch), cache->base); 3313 3314 /* if != -1, fdata.saved_fpr is the smallest number of saved_fpr. 3315 All fpr's from saved_fpr to fp31 are saved. */ 3316 3317 if (fdata.saved_fpr >= 0) 3318 { 3319 int i; 3320 CORE_ADDR fpr_addr = cache->base + fdata.fpr_offset; 3321 3322 /* If skip_prologue says floating-point registers were saved, 3323 but the current architecture has no floating-point registers, 3324 then that's strange. But we have no indices to even record 3325 the addresses under, so we just ignore it. */ 3326 if (ppc_floating_point_unit_p (gdbarch)) 3327 for (i = fdata.saved_fpr; i < ppc_num_fprs; i++) 3328 { 3329 cache->saved_regs[tdep->ppc_fp0_regnum + i].addr = fpr_addr; 3330 fpr_addr += 8; 3331 } 3332 } 3333 3334 /* if != -1, fdata.saved_gpr is the smallest number of saved_gpr. 3335 All gpr's from saved_gpr to gpr31 are saved. */ 3336 3337 if (fdata.saved_gpr >= 0) 3338 { 3339 int i; 3340 CORE_ADDR gpr_addr = cache->base + fdata.gpr_offset; 3341 for (i = fdata.saved_gpr; i < ppc_num_gprs; i++) 3342 { 3343 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = gpr_addr; 3344 gpr_addr += wordsize; 3345 } 3346 } 3347 3348 /* if != -1, fdata.saved_vr is the smallest number of saved_vr. 3349 All vr's from saved_vr to vr31 are saved. */ 3350 if (tdep->ppc_vr0_regnum != -1 && tdep->ppc_vrsave_regnum != -1) 3351 { 3352 if (fdata.saved_vr >= 0) 3353 { 3354 int i; 3355 CORE_ADDR vr_addr = cache->base + fdata.vr_offset; 3356 for (i = fdata.saved_vr; i < 32; i++) 3357 { 3358 cache->saved_regs[tdep->ppc_vr0_regnum + i].addr = vr_addr; 3359 vr_addr += register_size (gdbarch, tdep->ppc_vr0_regnum); 3360 } 3361 } 3362 } 3363 3364 /* if != -1, fdata.saved_ev is the smallest number of saved_ev. 3365 All vr's from saved_ev to ev31 are saved. ????? */ 3366 if (tdep->ppc_ev0_regnum != -1 && tdep->ppc_ev31_regnum != -1) 3367 { 3368 if (fdata.saved_ev >= 0) 3369 { 3370 int i; 3371 CORE_ADDR ev_addr = cache->base + fdata.ev_offset; 3372 for (i = fdata.saved_ev; i < ppc_num_gprs; i++) 3373 { 3374 cache->saved_regs[tdep->ppc_ev0_regnum + i].addr = ev_addr; 3375 cache->saved_regs[tdep->ppc_gp0_regnum + i].addr = ev_addr + 4; 3376 ev_addr += register_size (gdbarch, tdep->ppc_ev0_regnum); 3377 } 3378 } 3379 } 3380 3381 /* If != 0, fdata.cr_offset is the offset from the frame that 3382 holds the CR. */ 3383 if (fdata.cr_offset != 0) 3384 cache->saved_regs[tdep->ppc_cr_regnum].addr = cache->base + fdata.cr_offset; 3385 3386 /* If != 0, fdata.lr_offset is the offset from the frame that 3387 holds the LR. */ 3388 if (fdata.lr_offset != 0) 3389 cache->saved_regs[tdep->ppc_lr_regnum].addr = cache->base + fdata.lr_offset; 3390 /* The PC is found in the link register. */ 3391 cache->saved_regs[gdbarch_pc_regnum (current_gdbarch)] = 3392 cache->saved_regs[tdep->ppc_lr_regnum]; 3393 3394 /* If != 0, fdata.vrsave_offset is the offset from the frame that 3395 holds the VRSAVE. */ 3396 if (fdata.vrsave_offset != 0) 3397 cache->saved_regs[tdep->ppc_vrsave_regnum].addr = cache->base + fdata.vrsave_offset; 3398 3399 if (fdata.alloca_reg < 0) 3400 /* If no alloca register used, then fi->frame is the value of the 3401 %sp for this frame, and it is good enough. */ 3402 cache->initial_sp = frame_unwind_register_unsigned 3403 (next_frame, gdbarch_sp_regnum (current_gdbarch)); 3404 else 3405 cache->initial_sp = frame_unwind_register_unsigned (next_frame, 3406 fdata.alloca_reg); 3407 3408 return cache; 3409} 3410 3411static void 3412rs6000_frame_this_id (struct frame_info *next_frame, void **this_cache, 3413 struct frame_id *this_id) 3414{ 3415 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, 3416 this_cache); 3417 (*this_id) = frame_id_build (info->base, 3418 frame_func_unwind (next_frame, NORMAL_FRAME)); 3419} 3420 3421static void 3422rs6000_frame_prev_register (struct frame_info *next_frame, 3423 void **this_cache, 3424 int regnum, int *optimizedp, 3425 enum lval_type *lvalp, CORE_ADDR *addrp, 3426 int *realnump, gdb_byte *valuep) 3427{ 3428 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, 3429 this_cache); 3430 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, 3431 optimizedp, lvalp, addrp, realnump, valuep); 3432} 3433 3434static const struct frame_unwind rs6000_frame_unwind = 3435{ 3436 NORMAL_FRAME, 3437 rs6000_frame_this_id, 3438 rs6000_frame_prev_register 3439}; 3440 3441static const struct frame_unwind * 3442rs6000_frame_sniffer (struct frame_info *next_frame) 3443{ 3444 return &rs6000_frame_unwind; 3445} 3446 3447 3448 3449static CORE_ADDR 3450rs6000_frame_base_address (struct frame_info *next_frame, 3451 void **this_cache) 3452{ 3453 struct rs6000_frame_cache *info = rs6000_frame_cache (next_frame, 3454 this_cache); 3455 return info->initial_sp; 3456} 3457 3458static const struct frame_base rs6000_frame_base = { 3459 &rs6000_frame_unwind, 3460 rs6000_frame_base_address, 3461 rs6000_frame_base_address, 3462 rs6000_frame_base_address 3463}; 3464 3465static const struct frame_base * 3466rs6000_frame_base_sniffer (struct frame_info *next_frame) 3467{ 3468 return &rs6000_frame_base; 3469} 3470 3471/* DWARF-2 frame support. Used to handle the detection of 3472 clobbered registers during function calls. */ 3473 3474static void 3475ppc_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum, 3476 struct dwarf2_frame_state_reg *reg, 3477 struct frame_info *next_frame) 3478{ 3479 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 3480 3481 /* PPC32 and PPC64 ABI's are the same regarding volatile and 3482 non-volatile registers. We will use the same code for both. */ 3483 3484 /* Call-saved GP registers. */ 3485 if ((regnum >= tdep->ppc_gp0_regnum + 14 3486 && regnum <= tdep->ppc_gp0_regnum + 31) 3487 || (regnum == tdep->ppc_gp0_regnum + 1)) 3488 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 3489 3490 /* Call-clobbered GP registers. */ 3491 if ((regnum >= tdep->ppc_gp0_regnum + 3 3492 && regnum <= tdep->ppc_gp0_regnum + 12) 3493 || (regnum == tdep->ppc_gp0_regnum)) 3494 reg->how = DWARF2_FRAME_REG_UNDEFINED; 3495 3496 /* Deal with FP registers, if supported. */ 3497 if (tdep->ppc_fp0_regnum >= 0) 3498 { 3499 /* Call-saved FP registers. */ 3500 if ((regnum >= tdep->ppc_fp0_regnum + 14 3501 && regnum <= tdep->ppc_fp0_regnum + 31)) 3502 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 3503 3504 /* Call-clobbered FP registers. */ 3505 if ((regnum >= tdep->ppc_fp0_regnum 3506 && regnum <= tdep->ppc_fp0_regnum + 13)) 3507 reg->how = DWARF2_FRAME_REG_UNDEFINED; 3508 } 3509 3510 /* Deal with ALTIVEC registers, if supported. */ 3511 if (tdep->ppc_vr0_regnum > 0 && tdep->ppc_vrsave_regnum > 0) 3512 { 3513 /* Call-saved Altivec registers. */ 3514 if ((regnum >= tdep->ppc_vr0_regnum + 20 3515 && regnum <= tdep->ppc_vr0_regnum + 31) 3516 || regnum == tdep->ppc_vrsave_regnum) 3517 reg->how = DWARF2_FRAME_REG_SAME_VALUE; 3518 3519 /* Call-clobbered Altivec registers. */ 3520 if ((regnum >= tdep->ppc_vr0_regnum 3521 && regnum <= tdep->ppc_vr0_regnum + 19)) 3522 reg->how = DWARF2_FRAME_REG_UNDEFINED; 3523 } 3524 3525 /* Handle PC register and Stack Pointer correctly. */ 3526 if (regnum == gdbarch_pc_regnum (current_gdbarch)) 3527 reg->how = DWARF2_FRAME_REG_RA; 3528 else if (regnum == gdbarch_sp_regnum (current_gdbarch)) 3529 reg->how = DWARF2_FRAME_REG_CFA; 3530} 3531 3532 3533/* Initialize the current architecture based on INFO. If possible, re-use an 3534 architecture from ARCHES, which is a list of architectures already created 3535 during this debugging session. 3536 3537 Called e.g. at program startup, when reading a core file, and when reading 3538 a binary file. */ 3539 3540static struct gdbarch * 3541rs6000_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 3542{ 3543 struct gdbarch *gdbarch; 3544 struct gdbarch_tdep *tdep; 3545 int wordsize, from_xcoff_exec, from_elf_exec, i, off; 3546 struct reg *regs; 3547 const struct variant *v; 3548 enum bfd_architecture arch; 3549 unsigned long mach; 3550 bfd abfd; 3551 int sysv_abi; 3552 asection *sect; 3553 3554 from_xcoff_exec = info.abfd && info.abfd->format == bfd_object && 3555 bfd_get_flavour (info.abfd) == bfd_target_xcoff_flavour; 3556 3557 from_elf_exec = info.abfd && info.abfd->format == bfd_object && 3558 bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; 3559 3560 sysv_abi = info.abfd && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour; 3561 3562 /* Check word size. If INFO is from a binary file, infer it from 3563 that, else choose a likely default. */ 3564 if (from_xcoff_exec) 3565 { 3566 if (bfd_xcoff_is_xcoff64 (info.abfd)) 3567 wordsize = 8; 3568 else 3569 wordsize = 4; 3570 } 3571 else if (from_elf_exec) 3572 { 3573 if (elf_elfheader (info.abfd)->e_ident[EI_CLASS] == ELFCLASS64) 3574 wordsize = 8; 3575 else 3576 wordsize = 4; 3577 } 3578 else 3579 { 3580 if (info.bfd_arch_info != NULL && info.bfd_arch_info->bits_per_word != 0) 3581 wordsize = info.bfd_arch_info->bits_per_word / 3582 info.bfd_arch_info->bits_per_byte; 3583 else 3584 wordsize = 4; 3585 } 3586 3587 /* Find a candidate among extant architectures. */ 3588 for (arches = gdbarch_list_lookup_by_info (arches, &info); 3589 arches != NULL; 3590 arches = gdbarch_list_lookup_by_info (arches->next, &info)) 3591 { 3592 /* Word size in the various PowerPC bfd_arch_info structs isn't 3593 meaningful, because 64-bit CPUs can run in 32-bit mode. So, perform 3594 separate word size check. */ 3595 tdep = gdbarch_tdep (arches->gdbarch); 3596 if (tdep && tdep->wordsize == wordsize) 3597 return arches->gdbarch; 3598 } 3599 3600 /* None found, create a new architecture from INFO, whose bfd_arch_info 3601 validity depends on the source: 3602 - executable useless 3603 - rs6000_host_arch() good 3604 - core file good 3605 - "set arch" trust blindly 3606 - GDB startup useless but harmless */ 3607 3608 if (!from_xcoff_exec) 3609 { 3610 arch = info.bfd_arch_info->arch; 3611 mach = info.bfd_arch_info->mach; 3612 } 3613 else 3614 { 3615 arch = bfd_arch_powerpc; 3616 bfd_default_set_arch_mach (&abfd, arch, 0); 3617 info.bfd_arch_info = bfd_get_arch_info (&abfd); 3618 mach = info.bfd_arch_info->mach; 3619 } 3620 tdep = XCALLOC (1, struct gdbarch_tdep); 3621 tdep->wordsize = wordsize; 3622 3623 /* For e500 executables, the apuinfo section is of help here. Such 3624 section contains the identifier and revision number of each 3625 Application-specific Processing Unit that is present on the 3626 chip. The content of the section is determined by the assembler 3627 which looks at each instruction and determines which unit (and 3628 which version of it) can execute it. In our case we just look for 3629 the existance of the section. */ 3630 3631 if (info.abfd) 3632 { 3633 sect = bfd_get_section_by_name (info.abfd, ".PPC.EMB.apuinfo"); 3634 if (sect) 3635 { 3636 arch = info.bfd_arch_info->arch; 3637 mach = bfd_mach_ppc_e500; 3638 bfd_default_set_arch_mach (&abfd, arch, mach); 3639 info.bfd_arch_info = bfd_get_arch_info (&abfd); 3640 } 3641 } 3642 3643 gdbarch = gdbarch_alloc (&info, tdep); 3644 3645 /* Initialize the number of real and pseudo registers in each variant. */ 3646 init_variants (); 3647 3648 /* Choose variant. */ 3649 v = find_variant_by_arch (arch, mach); 3650 if (!v) 3651 return NULL; 3652 3653 tdep->regs = v->regs; 3654 3655 tdep->ppc_gp0_regnum = 0; 3656 tdep->ppc_toc_regnum = 2; 3657 tdep->ppc_ps_regnum = 65; 3658 tdep->ppc_cr_regnum = 66; 3659 tdep->ppc_lr_regnum = 67; 3660 tdep->ppc_ctr_regnum = 68; 3661 tdep->ppc_xer_regnum = 69; 3662 if (v->mach == bfd_mach_ppc_601) 3663 tdep->ppc_mq_regnum = 124; 3664 else if (arch == bfd_arch_rs6000) 3665 tdep->ppc_mq_regnum = 70; 3666 else 3667 tdep->ppc_mq_regnum = -1; 3668 tdep->ppc_fp0_regnum = 32; 3669 tdep->ppc_fpscr_regnum = (arch == bfd_arch_rs6000) ? 71 : 70; 3670 tdep->ppc_sr0_regnum = 71; 3671 tdep->ppc_vr0_regnum = -1; 3672 tdep->ppc_vrsave_regnum = -1; 3673 tdep->ppc_ev0_upper_regnum = -1; 3674 tdep->ppc_ev0_regnum = -1; 3675 tdep->ppc_ev31_regnum = -1; 3676 tdep->ppc_acc_regnum = -1; 3677 tdep->ppc_spefscr_regnum = -1; 3678 3679 set_gdbarch_pc_regnum (gdbarch, 64); 3680 set_gdbarch_sp_regnum (gdbarch, 1); 3681 set_gdbarch_deprecated_fp_regnum (gdbarch, 1); 3682 set_gdbarch_fp0_regnum (gdbarch, 32); 3683 set_gdbarch_register_sim_regno (gdbarch, rs6000_register_sim_regno); 3684 if (sysv_abi && wordsize == 8) 3685 set_gdbarch_return_value (gdbarch, ppc64_sysv_abi_return_value); 3686 else if (sysv_abi && wordsize == 4) 3687 set_gdbarch_return_value (gdbarch, ppc_sysv_abi_return_value); 3688 else 3689 set_gdbarch_return_value (gdbarch, rs6000_return_value); 3690 3691 /* Set lr_frame_offset. */ 3692 if (wordsize == 8) 3693 tdep->lr_frame_offset = 16; 3694 else if (sysv_abi) 3695 tdep->lr_frame_offset = 4; 3696 else 3697 tdep->lr_frame_offset = 8; 3698 3699 if (v->arch == bfd_arch_rs6000) 3700 tdep->ppc_sr0_regnum = -1; 3701 else if (v->arch == bfd_arch_powerpc) 3702 switch (v->mach) 3703 { 3704 case bfd_mach_ppc: 3705 tdep->ppc_sr0_regnum = -1; 3706 tdep->ppc_vr0_regnum = 71; 3707 tdep->ppc_vrsave_regnum = 104; 3708 break; 3709 case bfd_mach_ppc_7400: 3710 tdep->ppc_vr0_regnum = 119; 3711 tdep->ppc_vrsave_regnum = 152; 3712 break; 3713 case bfd_mach_ppc_e500: 3714 tdep->ppc_toc_regnum = -1; 3715 tdep->ppc_ev0_upper_regnum = 32; 3716 tdep->ppc_ev0_regnum = 73; 3717 tdep->ppc_ev31_regnum = 104; 3718 tdep->ppc_acc_regnum = 71; 3719 tdep->ppc_spefscr_regnum = 72; 3720 tdep->ppc_fp0_regnum = -1; 3721 tdep->ppc_fpscr_regnum = -1; 3722 tdep->ppc_sr0_regnum = -1; 3723 set_gdbarch_pseudo_register_read (gdbarch, e500_pseudo_register_read); 3724 set_gdbarch_pseudo_register_write (gdbarch, e500_pseudo_register_write); 3725 set_gdbarch_register_reggroup_p (gdbarch, e500_register_reggroup_p); 3726 break; 3727 3728 case bfd_mach_ppc64: 3729 case bfd_mach_ppc_620: 3730 case bfd_mach_ppc_630: 3731 case bfd_mach_ppc_a35: 3732 case bfd_mach_ppc_rs64ii: 3733 case bfd_mach_ppc_rs64iii: 3734 /* These processor's register sets don't have segment registers. */ 3735 tdep->ppc_sr0_regnum = -1; 3736 break; 3737 } 3738 else 3739 internal_error (__FILE__, __LINE__, 3740 _("rs6000_gdbarch_init: " 3741 "received unexpected BFD 'arch' value")); 3742 3743 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1); 3744 3745 /* Sanity check on registers. */ 3746 gdb_assert (strcmp (tdep->regs[tdep->ppc_gp0_regnum].name, "r0") == 0); 3747 3748 /* Select instruction printer. */ 3749 if (arch == bfd_arch_rs6000) 3750 set_gdbarch_print_insn (gdbarch, print_insn_rs6000); 3751 else 3752 set_gdbarch_print_insn (gdbarch, gdb_print_insn_powerpc); 3753 3754 set_gdbarch_num_regs (gdbarch, v->nregs); 3755 set_gdbarch_num_pseudo_regs (gdbarch, v->npregs); 3756 set_gdbarch_register_name (gdbarch, rs6000_register_name); 3757 set_gdbarch_register_type (gdbarch, rs6000_register_type); 3758 set_gdbarch_register_reggroup_p (gdbarch, rs6000_register_reggroup_p); 3759 3760 set_gdbarch_ptr_bit (gdbarch, wordsize * TARGET_CHAR_BIT); 3761 set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT); 3762 set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT); 3763 set_gdbarch_long_bit (gdbarch, wordsize * TARGET_CHAR_BIT); 3764 set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT); 3765 set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT); 3766 set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 3767 if (sysv_abi) 3768 set_gdbarch_long_double_bit (gdbarch, 16 * TARGET_CHAR_BIT); 3769 else 3770 set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT); 3771 set_gdbarch_char_signed (gdbarch, 0); 3772 3773 set_gdbarch_frame_align (gdbarch, rs6000_frame_align); 3774 if (sysv_abi && wordsize == 8) 3775 /* PPC64 SYSV. */ 3776 set_gdbarch_frame_red_zone_size (gdbarch, 288); 3777 else if (!sysv_abi && wordsize == 4) 3778 /* PowerOpen / AIX 32 bit. The saved area or red zone consists of 3779 19 4 byte GPRS + 18 8 byte FPRs giving a total of 220 bytes. 3780 Problem is, 220 isn't frame (16 byte) aligned. Round it up to 3781 224. */ 3782 set_gdbarch_frame_red_zone_size (gdbarch, 224); 3783 3784 set_gdbarch_convert_register_p (gdbarch, rs6000_convert_register_p); 3785 set_gdbarch_register_to_value (gdbarch, rs6000_register_to_value); 3786 set_gdbarch_value_to_register (gdbarch, rs6000_value_to_register); 3787 3788 set_gdbarch_stab_reg_to_regnum (gdbarch, rs6000_stab_reg_to_regnum); 3789 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, rs6000_dwarf2_reg_to_regnum); 3790 3791 if (sysv_abi && wordsize == 4) 3792 set_gdbarch_push_dummy_call (gdbarch, ppc_sysv_abi_push_dummy_call); 3793 else if (sysv_abi && wordsize == 8) 3794 set_gdbarch_push_dummy_call (gdbarch, ppc64_sysv_abi_push_dummy_call); 3795 else 3796 set_gdbarch_push_dummy_call (gdbarch, rs6000_push_dummy_call); 3797 3798 set_gdbarch_skip_prologue (gdbarch, rs6000_skip_prologue); 3799 set_gdbarch_in_function_epilogue_p (gdbarch, rs6000_in_function_epilogue_p); 3800 3801 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 3802 set_gdbarch_breakpoint_from_pc (gdbarch, rs6000_breakpoint_from_pc); 3803 3804 /* Handles single stepping of atomic sequences. */ 3805 set_gdbarch_software_single_step (gdbarch, deal_with_atomic_sequence); 3806 3807 /* Handle the 64-bit SVR4 minimal-symbol convention of using "FN" 3808 for the descriptor and ".FN" for the entry-point -- a user 3809 specifying "break FN" will unexpectedly end up with a breakpoint 3810 on the descriptor and not the function. This architecture method 3811 transforms any breakpoints on descriptors into breakpoints on the 3812 corresponding entry point. */ 3813 if (sysv_abi && wordsize == 8) 3814 set_gdbarch_adjust_breakpoint_address (gdbarch, ppc64_sysv_abi_adjust_breakpoint_address); 3815 3816 /* Not sure on this. FIXMEmgo */ 3817 set_gdbarch_frame_args_skip (gdbarch, 8); 3818 3819 if (!sysv_abi) 3820 { 3821 /* Handle RS/6000 function pointers (which are really function 3822 descriptors). */ 3823 set_gdbarch_convert_from_func_ptr_addr (gdbarch, 3824 rs6000_convert_from_func_ptr_addr); 3825 } 3826 3827 /* Helpers for function argument information. */ 3828 set_gdbarch_fetch_pointer_argument (gdbarch, rs6000_fetch_pointer_argument); 3829 3830 /* Trampoline. */ 3831 set_gdbarch_in_solib_return_trampoline 3832 (gdbarch, rs6000_in_solib_return_trampoline); 3833 set_gdbarch_skip_trampoline_code (gdbarch, rs6000_skip_trampoline_code); 3834 3835 /* Hook in the DWARF CFI frame unwinder. */ 3836 frame_unwind_append_sniffer (gdbarch, dwarf2_frame_sniffer); 3837 dwarf2_frame_set_adjust_regnum (gdbarch, rs6000_adjust_frame_regnum); 3838 3839 /* Frame handling. */ 3840 dwarf2_frame_set_init_reg (gdbarch, ppc_dwarf2_frame_init_reg); 3841 3842 /* Hook in ABI-specific overrides, if they have been registered. */ 3843 gdbarch_init_osabi (info, gdbarch); 3844 3845 switch (info.osabi) 3846 { 3847 case GDB_OSABI_LINUX: 3848 /* FIXME: pgilliam/2005-10-21: Assume all PowerPC 64-bit linux systems 3849 have altivec registers. If not, ptrace will fail the first time it's 3850 called to access one and will not be called again. This wart will 3851 be removed when Daniel Jacobowitz's proposal for autodetecting target 3852 registers is implemented. */ 3853 if ((v->arch == bfd_arch_powerpc) && ((v->mach)== bfd_mach_ppc64)) 3854 { 3855 tdep->ppc_vr0_regnum = 71; 3856 tdep->ppc_vrsave_regnum = 104; 3857 } 3858 /* Fall Thru */ 3859 case GDB_OSABI_NETBSD_AOUT: 3860 case GDB_OSABI_NETBSD_ELF: 3861 case GDB_OSABI_UNKNOWN: 3862 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); 3863 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); 3864 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); 3865 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); 3866 break; 3867 default: 3868 set_gdbarch_believe_pcc_promotion (gdbarch, 1); 3869 3870 set_gdbarch_unwind_pc (gdbarch, rs6000_unwind_pc); 3871 frame_unwind_append_sniffer (gdbarch, rs6000_frame_sniffer); 3872 set_gdbarch_unwind_dummy_id (gdbarch, rs6000_unwind_dummy_id); 3873 frame_base_append_sniffer (gdbarch, rs6000_frame_base_sniffer); 3874 } 3875 3876 init_sim_regno_table (gdbarch); 3877 3878 return gdbarch; 3879} 3880 3881static void 3882rs6000_dump_tdep (struct gdbarch *current_gdbarch, struct ui_file *file) 3883{ 3884 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 3885 3886 if (tdep == NULL) 3887 return; 3888 3889 /* FIXME: Dump gdbarch_tdep. */ 3890} 3891 3892/* Initialization code. */ 3893 3894extern initialize_file_ftype _initialize_rs6000_tdep; /* -Wmissing-prototypes */ 3895 3896void 3897_initialize_rs6000_tdep (void) 3898{ 3899 gdbarch_register (bfd_arch_rs6000, rs6000_gdbarch_init, rs6000_dump_tdep); 3900 gdbarch_register (bfd_arch_powerpc, rs6000_gdbarch_init, rs6000_dump_tdep); 3901} 3902