1/* Target-dependent code for Renesas M32R, for GDB. 2 3 Copyright (C) 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2007 4 Free Software Foundation, Inc. 5 6 This file is part of GDB. 7 8 This program is free software; you can redistribute it and/or modify 9 it under the terms of the GNU General Public License as published by 10 the Free Software Foundation; either version 3 of the License, or 11 (at your option) any later version. 12 13 This program is distributed in the hope that it will be useful, 14 but WITHOUT ANY WARRANTY; without even the implied warranty of 15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 GNU General Public License for more details. 17 18 You should have received a copy of the GNU General Public License 19 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 20 21#include "defs.h" 22#include "frame.h" 23#include "frame-unwind.h" 24#include "frame-base.h" 25#include "symtab.h" 26#include "gdbtypes.h" 27#include "gdbcmd.h" 28#include "gdbcore.h" 29#include "gdb_string.h" 30#include "value.h" 31#include "inferior.h" 32#include "symfile.h" 33#include "objfiles.h" 34#include "osabi.h" 35#include "language.h" 36#include "arch-utils.h" 37#include "regcache.h" 38#include "trad-frame.h" 39#include "dis-asm.h" 40 41#include "gdb_assert.h" 42 43#include "m32r-tdep.h" 44 45/* Local functions */ 46 47extern void _initialize_m32r_tdep (void); 48 49static CORE_ADDR 50m32r_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 51{ 52 /* Align to the size of an instruction (so that they can safely be 53 pushed onto the stack. */ 54 return sp & ~3; 55} 56 57 58/* Breakpoints 59 60 The little endian mode of M32R is unique. In most of architectures, 61 two 16-bit instructions, A and B, are placed as the following: 62 63 Big endian: 64 A0 A1 B0 B1 65 66 Little endian: 67 A1 A0 B1 B0 68 69 In M32R, they are placed like this: 70 71 Big endian: 72 A0 A1 B0 B1 73 74 Little endian: 75 B1 B0 A1 A0 76 77 This is because M32R always fetches instructions in 32-bit. 78 79 The following functions take care of this behavior. */ 80 81static int 82m32r_memory_insert_breakpoint (struct bp_target_info *bp_tgt) 83{ 84 CORE_ADDR addr = bp_tgt->placed_address; 85 int val; 86 gdb_byte buf[4]; 87 gdb_byte *contents_cache = bp_tgt->shadow_contents; 88 gdb_byte bp_entry[] = { 0x10, 0xf1 }; /* dpt */ 89 90 /* Save the memory contents. */ 91 val = target_read_memory (addr & 0xfffffffc, contents_cache, 4); 92 if (val != 0) 93 return val; /* return error */ 94 95 bp_tgt->placed_size = bp_tgt->shadow_len = 4; 96 97 /* Determine appropriate breakpoint contents and size for this address. */ 98 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) 99 { 100 if ((addr & 3) == 0) 101 { 102 buf[0] = bp_entry[0]; 103 buf[1] = bp_entry[1]; 104 buf[2] = contents_cache[2] & 0x7f; 105 buf[3] = contents_cache[3]; 106 } 107 else 108 { 109 buf[0] = contents_cache[0]; 110 buf[1] = contents_cache[1]; 111 buf[2] = bp_entry[0]; 112 buf[3] = bp_entry[1]; 113 } 114 } 115 else /* little-endian */ 116 { 117 if ((addr & 3) == 0) 118 { 119 buf[0] = contents_cache[0]; 120 buf[1] = contents_cache[1] & 0x7f; 121 buf[2] = bp_entry[1]; 122 buf[3] = bp_entry[0]; 123 } 124 else 125 { 126 buf[0] = bp_entry[1]; 127 buf[1] = bp_entry[0]; 128 buf[2] = contents_cache[2]; 129 buf[3] = contents_cache[3]; 130 } 131 } 132 133 /* Write the breakpoint. */ 134 val = target_write_memory (addr & 0xfffffffc, buf, 4); 135 return val; 136} 137 138static int 139m32r_memory_remove_breakpoint (struct bp_target_info *bp_tgt) 140{ 141 CORE_ADDR addr = bp_tgt->placed_address; 142 int val; 143 gdb_byte buf[4]; 144 gdb_byte *contents_cache = bp_tgt->shadow_contents; 145 146 buf[0] = contents_cache[0]; 147 buf[1] = contents_cache[1]; 148 buf[2] = contents_cache[2]; 149 buf[3] = contents_cache[3]; 150 151 /* Remove parallel bit. */ 152 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) 153 { 154 if ((buf[0] & 0x80) == 0 && (buf[2] & 0x80) != 0) 155 buf[2] &= 0x7f; 156 } 157 else /* little-endian */ 158 { 159 if ((buf[3] & 0x80) == 0 && (buf[1] & 0x80) != 0) 160 buf[1] &= 0x7f; 161 } 162 163 /* Write contents. */ 164 val = target_write_memory (addr & 0xfffffffc, buf, 4); 165 return val; 166} 167 168static const gdb_byte * 169m32r_breakpoint_from_pc (CORE_ADDR *pcptr, int *lenptr) 170{ 171 static gdb_byte be_bp_entry[] = { 0x10, 0xf1, 0x70, 0x00 }; /* dpt -> nop */ 172 static gdb_byte le_bp_entry[] = { 0x00, 0x70, 0xf1, 0x10 }; /* dpt -> nop */ 173 gdb_byte *bp; 174 175 /* Determine appropriate breakpoint. */ 176 if (gdbarch_byte_order (current_gdbarch) == BFD_ENDIAN_BIG) 177 { 178 if ((*pcptr & 3) == 0) 179 { 180 bp = be_bp_entry; 181 *lenptr = 4; 182 } 183 else 184 { 185 bp = be_bp_entry; 186 *lenptr = 2; 187 } 188 } 189 else 190 { 191 if ((*pcptr & 3) == 0) 192 { 193 bp = le_bp_entry; 194 *lenptr = 4; 195 } 196 else 197 { 198 bp = le_bp_entry + 2; 199 *lenptr = 2; 200 } 201 } 202 203 return bp; 204} 205 206 207char *m32r_register_names[] = { 208 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", 209 "r8", "r9", "r10", "r11", "r12", "fp", "lr", "sp", 210 "psw", "cbr", "spi", "spu", "bpc", "pc", "accl", "acch", 211 "evb" 212}; 213 214static const char * 215m32r_register_name (int reg_nr) 216{ 217 if (reg_nr < 0) 218 return NULL; 219 if (reg_nr >= M32R_NUM_REGS) 220 return NULL; 221 return m32r_register_names[reg_nr]; 222} 223 224 225/* Return the GDB type object for the "standard" data type 226 of data in register N. */ 227 228static struct type * 229m32r_register_type (struct gdbarch *gdbarch, int reg_nr) 230{ 231 if (reg_nr == M32R_PC_REGNUM) 232 return builtin_type_void_func_ptr; 233 else if (reg_nr == M32R_SP_REGNUM || reg_nr == M32R_FP_REGNUM) 234 return builtin_type_void_data_ptr; 235 else 236 return builtin_type_int32; 237} 238 239 240/* Write into appropriate registers a function return value 241 of type TYPE, given in virtual format. 242 243 Things always get returned in RET1_REGNUM, RET2_REGNUM. */ 244 245static void 246m32r_store_return_value (struct type *type, struct regcache *regcache, 247 const void *valbuf) 248{ 249 CORE_ADDR regval; 250 int len = TYPE_LENGTH (type); 251 252 regval = extract_unsigned_integer (valbuf, len > 4 ? 4 : len); 253 regcache_cooked_write_unsigned (regcache, RET1_REGNUM, regval); 254 255 if (len > 4) 256 { 257 regval = extract_unsigned_integer ((gdb_byte *) valbuf + 4, len - 4); 258 regcache_cooked_write_unsigned (regcache, RET1_REGNUM + 1, regval); 259 } 260} 261 262/* This is required by skip_prologue. The results of decoding a prologue 263 should be cached because this thrashing is getting nuts. */ 264 265static int 266decode_prologue (CORE_ADDR start_pc, CORE_ADDR scan_limit, 267 CORE_ADDR *pl_endptr, unsigned long *framelength) 268{ 269 unsigned long framesize; 270 int insn; 271 int op1; 272 CORE_ADDR after_prologue = 0; 273 CORE_ADDR after_push = 0; 274 CORE_ADDR after_stack_adjust = 0; 275 CORE_ADDR current_pc; 276 LONGEST return_value; 277 278 framesize = 0; 279 after_prologue = 0; 280 281 for (current_pc = start_pc; current_pc < scan_limit; current_pc += 2) 282 { 283 /* Check if current pc's location is readable. */ 284 if (!safe_read_memory_integer (current_pc, 2, &return_value)) 285 return -1; 286 287 insn = read_memory_unsigned_integer (current_pc, 2); 288 289 if (insn == 0x0000) 290 break; 291 292 /* If this is a 32 bit instruction, we dont want to examine its 293 immediate data as though it were an instruction */ 294 if (current_pc & 0x02) 295 { 296 /* decode this instruction further */ 297 insn &= 0x7fff; 298 } 299 else 300 { 301 if (insn & 0x8000) 302 { 303 if (current_pc == scan_limit) 304 scan_limit += 2; /* extend the search */ 305 306 current_pc += 2; /* skip the immediate data */ 307 308 /* Check if current pc's location is readable. */ 309 if (!safe_read_memory_integer (current_pc, 2, &return_value)) 310 return -1; 311 312 if (insn == 0x8faf) /* add3 sp, sp, xxxx */ 313 /* add 16 bit sign-extended offset */ 314 { 315 framesize += 316 -((short) read_memory_unsigned_integer (current_pc, 2)); 317 } 318 else 319 { 320 if (((insn >> 8) == 0xe4) /* ld24 r4, xxxxxx; sub sp, r4 */ 321 && safe_read_memory_integer (current_pc + 2, 2, 322 &return_value) 323 && read_memory_unsigned_integer (current_pc + 2, 324 2) == 0x0f24) 325 /* subtract 24 bit sign-extended negative-offset */ 326 { 327 insn = read_memory_unsigned_integer (current_pc - 2, 4); 328 if (insn & 0x00800000) /* sign extend */ 329 insn |= 0xff000000; /* negative */ 330 else 331 insn &= 0x00ffffff; /* positive */ 332 framesize += insn; 333 } 334 } 335 after_push = current_pc + 2; 336 continue; 337 } 338 } 339 op1 = insn & 0xf000; /* isolate just the first nibble */ 340 341 if ((insn & 0xf0ff) == 0x207f) 342 { /* st reg, @-sp */ 343 int regno; 344 framesize += 4; 345 regno = ((insn >> 8) & 0xf); 346 after_prologue = 0; 347 continue; 348 } 349 if ((insn >> 8) == 0x4f) /* addi sp, xx */ 350 /* add 8 bit sign-extended offset */ 351 { 352 int stack_adjust = (gdb_byte) (insn & 0xff); 353 354 /* there are probably two of these stack adjustments: 355 1) A negative one in the prologue, and 356 2) A positive one in the epilogue. 357 We are only interested in the first one. */ 358 359 if (stack_adjust < 0) 360 { 361 framesize -= stack_adjust; 362 after_prologue = 0; 363 /* A frameless function may have no "mv fp, sp". 364 In that case, this is the end of the prologue. */ 365 after_stack_adjust = current_pc + 2; 366 } 367 continue; 368 } 369 if (insn == 0x1d8f) 370 { /* mv fp, sp */ 371 after_prologue = current_pc + 2; 372 break; /* end of stack adjustments */ 373 } 374 375 /* Nop looks like a branch, continue explicitly */ 376 if (insn == 0x7000) 377 { 378 after_prologue = current_pc + 2; 379 continue; /* nop occurs between pushes */ 380 } 381 /* End of prolog if any of these are trap instructions */ 382 if ((insn & 0xfff0) == 0x10f0) 383 { 384 after_prologue = current_pc; 385 break; 386 } 387 /* End of prolog if any of these are branch instructions */ 388 if ((op1 == 0x7000) || (op1 == 0xb000) || (op1 == 0xf000)) 389 { 390 after_prologue = current_pc; 391 continue; 392 } 393 /* Some of the branch instructions are mixed with other types */ 394 if (op1 == 0x1000) 395 { 396 int subop = insn & 0x0ff0; 397 if ((subop == 0x0ec0) || (subop == 0x0fc0)) 398 { 399 after_prologue = current_pc; 400 continue; /* jmp , jl */ 401 } 402 } 403 } 404 405 if (framelength) 406 *framelength = framesize; 407 408 if (current_pc >= scan_limit) 409 { 410 if (pl_endptr) 411 { 412 if (after_stack_adjust != 0) 413 /* We did not find a "mv fp,sp", but we DID find 414 a stack_adjust. Is it safe to use that as the 415 end of the prologue? I just don't know. */ 416 { 417 *pl_endptr = after_stack_adjust; 418 } 419 else if (after_push != 0) 420 /* We did not find a "mv fp,sp", but we DID find 421 a push. Is it safe to use that as the 422 end of the prologue? I just don't know. */ 423 { 424 *pl_endptr = after_push; 425 } 426 else 427 /* We reached the end of the loop without finding the end 428 of the prologue. No way to win -- we should report failure. 429 The way we do that is to return the original start_pc. 430 GDB will set a breakpoint at the start of the function (etc.) */ 431 *pl_endptr = start_pc; 432 } 433 return 0; 434 } 435 436 if (after_prologue == 0) 437 after_prologue = current_pc; 438 439 if (pl_endptr) 440 *pl_endptr = after_prologue; 441 442 return 0; 443} /* decode_prologue */ 444 445/* Function: skip_prologue 446 Find end of function prologue */ 447 448#define DEFAULT_SEARCH_LIMIT 128 449 450CORE_ADDR 451m32r_skip_prologue (CORE_ADDR pc) 452{ 453 CORE_ADDR func_addr, func_end; 454 struct symtab_and_line sal; 455 LONGEST return_value; 456 457 /* See what the symbol table says */ 458 459 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end)) 460 { 461 sal = find_pc_line (func_addr, 0); 462 463 if (sal.line != 0 && sal.end <= func_end) 464 { 465 func_end = sal.end; 466 } 467 else 468 /* Either there's no line info, or the line after the prologue is after 469 the end of the function. In this case, there probably isn't a 470 prologue. */ 471 { 472 func_end = min (func_end, func_addr + DEFAULT_SEARCH_LIMIT); 473 } 474 } 475 else 476 func_end = pc + DEFAULT_SEARCH_LIMIT; 477 478 /* If pc's location is not readable, just quit. */ 479 if (!safe_read_memory_integer (pc, 4, &return_value)) 480 return pc; 481 482 /* Find the end of prologue. */ 483 if (decode_prologue (pc, func_end, &sal.end, NULL) < 0) 484 return pc; 485 486 return sal.end; 487} 488 489struct m32r_unwind_cache 490{ 491 /* The previous frame's inner most stack address. Used as this 492 frame ID's stack_addr. */ 493 CORE_ADDR prev_sp; 494 /* The frame's base, optionally used by the high-level debug info. */ 495 CORE_ADDR base; 496 int size; 497 /* How far the SP and r13 (FP) have been offset from the start of 498 the stack frame (as defined by the previous frame's stack 499 pointer). */ 500 LONGEST sp_offset; 501 LONGEST r13_offset; 502 int uses_frame; 503 /* Table indicating the location of each and every register. */ 504 struct trad_frame_saved_reg *saved_regs; 505}; 506 507/* Put here the code to store, into fi->saved_regs, the addresses of 508 the saved registers of frame described by FRAME_INFO. This 509 includes special registers such as pc and fp saved in special ways 510 in the stack frame. sp is even more special: the address we return 511 for it IS the sp for the next frame. */ 512 513static struct m32r_unwind_cache * 514m32r_frame_unwind_cache (struct frame_info *next_frame, 515 void **this_prologue_cache) 516{ 517 CORE_ADDR pc, scan_limit; 518 ULONGEST prev_sp; 519 ULONGEST this_base; 520 unsigned long op, op2; 521 int i; 522 struct m32r_unwind_cache *info; 523 524 525 if ((*this_prologue_cache)) 526 return (*this_prologue_cache); 527 528 info = FRAME_OBSTACK_ZALLOC (struct m32r_unwind_cache); 529 (*this_prologue_cache) = info; 530 info->saved_regs = trad_frame_alloc_saved_regs (next_frame); 531 532 info->size = 0; 533 info->sp_offset = 0; 534 info->uses_frame = 0; 535 536 scan_limit = frame_pc_unwind (next_frame); 537 for (pc = frame_func_unwind (next_frame, NORMAL_FRAME); 538 pc > 0 && pc < scan_limit; pc += 2) 539 { 540 if ((pc & 2) == 0) 541 { 542 op = get_frame_memory_unsigned (next_frame, pc, 4); 543 if ((op & 0x80000000) == 0x80000000) 544 { 545 /* 32-bit instruction */ 546 if ((op & 0xffff0000) == 0x8faf0000) 547 { 548 /* add3 sp,sp,xxxx */ 549 short n = op & 0xffff; 550 info->sp_offset += n; 551 } 552 else if (((op >> 8) == 0xe4) 553 && get_frame_memory_unsigned (next_frame, pc + 2, 554 2) == 0x0f24) 555 { 556 /* ld24 r4, xxxxxx; sub sp, r4 */ 557 unsigned long n = op & 0xffffff; 558 info->sp_offset += n; 559 pc += 2; /* skip sub instruction */ 560 } 561 562 if (pc == scan_limit) 563 scan_limit += 2; /* extend the search */ 564 pc += 2; /* skip the immediate data */ 565 continue; 566 } 567 } 568 569 /* 16-bit instructions */ 570 op = get_frame_memory_unsigned (next_frame, pc, 2) & 0x7fff; 571 if ((op & 0xf0ff) == 0x207f) 572 { 573 /* st rn, @-sp */ 574 int regno = ((op >> 8) & 0xf); 575 info->sp_offset -= 4; 576 info->saved_regs[regno].addr = info->sp_offset; 577 } 578 else if ((op & 0xff00) == 0x4f00) 579 { 580 /* addi sp, xx */ 581 int n = (gdb_byte) (op & 0xff); 582 info->sp_offset += n; 583 } 584 else if (op == 0x1d8f) 585 { 586 /* mv fp, sp */ 587 info->uses_frame = 1; 588 info->r13_offset = info->sp_offset; 589 break; /* end of stack adjustments */ 590 } 591 else if ((op & 0xfff0) == 0x10f0) 592 { 593 /* end of prologue if this is a trap instruction */ 594 break; /* end of stack adjustments */ 595 } 596 } 597 598 info->size = -info->sp_offset; 599 600 /* Compute the previous frame's stack pointer (which is also the 601 frame's ID's stack address), and this frame's base pointer. */ 602 if (info->uses_frame) 603 { 604 /* The SP was moved to the FP. This indicates that a new frame 605 was created. Get THIS frame's FP value by unwinding it from 606 the next frame. */ 607 this_base = frame_unwind_register_unsigned (next_frame, M32R_FP_REGNUM); 608 /* The FP points at the last saved register. Adjust the FP back 609 to before the first saved register giving the SP. */ 610 prev_sp = this_base + info->size; 611 } 612 else 613 { 614 /* Assume that the FP is this frame's SP but with that pushed 615 stack space added back. */ 616 this_base = frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); 617 prev_sp = this_base + info->size; 618 } 619 620 /* Convert that SP/BASE into real addresses. */ 621 info->prev_sp = prev_sp; 622 info->base = this_base; 623 624 /* Adjust all the saved registers so that they contain addresses and 625 not offsets. */ 626 for (i = 0; i < gdbarch_num_regs (current_gdbarch) - 1; i++) 627 if (trad_frame_addr_p (info->saved_regs, i)) 628 info->saved_regs[i].addr = (info->prev_sp + info->saved_regs[i].addr); 629 630 /* The call instruction moves the caller's PC in the callee's LR. 631 Since this is an unwind, do the reverse. Copy the location of LR 632 into PC (the address / regnum) so that a request for PC will be 633 converted into a request for the LR. */ 634 info->saved_regs[M32R_PC_REGNUM] = info->saved_regs[LR_REGNUM]; 635 636 /* The previous frame's SP needed to be computed. Save the computed 637 value. */ 638 trad_frame_set_value (info->saved_regs, M32R_SP_REGNUM, prev_sp); 639 640 return info; 641} 642 643static CORE_ADDR 644m32r_read_pc (struct regcache *regcache) 645{ 646 ULONGEST pc; 647 regcache_cooked_read_unsigned (regcache, M32R_PC_REGNUM, &pc); 648 return pc; 649} 650 651static void 652m32r_write_pc (struct regcache *regcache, CORE_ADDR val) 653{ 654 regcache_cooked_write_unsigned (regcache, M32R_PC_REGNUM, val); 655} 656 657static CORE_ADDR 658m32r_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame) 659{ 660 return frame_unwind_register_unsigned (next_frame, M32R_SP_REGNUM); 661} 662 663 664static CORE_ADDR 665m32r_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 666 struct regcache *regcache, CORE_ADDR bp_addr, int nargs, 667 struct value **args, CORE_ADDR sp, int struct_return, 668 CORE_ADDR struct_addr) 669{ 670 int stack_offset, stack_alloc; 671 int argreg = ARG1_REGNUM; 672 int argnum; 673 struct type *type; 674 enum type_code typecode; 675 CORE_ADDR regval; 676 gdb_byte *val; 677 gdb_byte valbuf[MAX_REGISTER_SIZE]; 678 int len; 679 int odd_sized_struct; 680 681 /* first force sp to a 4-byte alignment */ 682 sp = sp & ~3; 683 684 /* Set the return address. For the m32r, the return breakpoint is 685 always at BP_ADDR. */ 686 regcache_cooked_write_unsigned (regcache, LR_REGNUM, bp_addr); 687 688 /* If STRUCT_RETURN is true, then the struct return address (in 689 STRUCT_ADDR) will consume the first argument-passing register. 690 Both adjust the register count and store that value. */ 691 if (struct_return) 692 { 693 regcache_cooked_write_unsigned (regcache, argreg, struct_addr); 694 argreg++; 695 } 696 697 /* Now make sure there's space on the stack */ 698 for (argnum = 0, stack_alloc = 0; argnum < nargs; argnum++) 699 stack_alloc += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3); 700 sp -= stack_alloc; /* make room on stack for args */ 701 702 for (argnum = 0, stack_offset = 0; argnum < nargs; argnum++) 703 { 704 type = value_type (args[argnum]); 705 typecode = TYPE_CODE (type); 706 len = TYPE_LENGTH (type); 707 708 memset (valbuf, 0, sizeof (valbuf)); 709 710 /* Passes structures that do not fit in 2 registers by reference. */ 711 if (len > 8 712 && (typecode == TYPE_CODE_STRUCT || typecode == TYPE_CODE_UNION)) 713 { 714 store_unsigned_integer (valbuf, 4, VALUE_ADDRESS (args[argnum])); 715 typecode = TYPE_CODE_PTR; 716 len = 4; 717 val = valbuf; 718 } 719 else if (len < 4) 720 { 721 /* value gets right-justified in the register or stack word */ 722 memcpy (valbuf + (register_size (gdbarch, argreg) - len), 723 (gdb_byte *) value_contents (args[argnum]), len); 724 val = valbuf; 725 } 726 else 727 val = (gdb_byte *) value_contents (args[argnum]); 728 729 while (len > 0) 730 { 731 if (argreg > ARGN_REGNUM) 732 { 733 /* must go on the stack */ 734 write_memory (sp + stack_offset, val, 4); 735 stack_offset += 4; 736 } 737 else if (argreg <= ARGN_REGNUM) 738 { 739 /* there's room in a register */ 740 regval = 741 extract_unsigned_integer (val, 742 register_size (gdbarch, argreg)); 743 regcache_cooked_write_unsigned (regcache, argreg++, regval); 744 } 745 746 /* Store the value 4 bytes at a time. This means that things 747 larger than 4 bytes may go partly in registers and partly 748 on the stack. */ 749 len -= register_size (gdbarch, argreg); 750 val += register_size (gdbarch, argreg); 751 } 752 } 753 754 /* Finally, update the SP register. */ 755 regcache_cooked_write_unsigned (regcache, M32R_SP_REGNUM, sp); 756 757 return sp; 758} 759 760 761/* Given a return value in `regbuf' with a type `valtype', 762 extract and copy its value into `valbuf'. */ 763 764static void 765m32r_extract_return_value (struct type *type, struct regcache *regcache, 766 void *dst) 767{ 768 bfd_byte *valbuf = dst; 769 int len = TYPE_LENGTH (type); 770 ULONGEST tmp; 771 772 /* By using store_unsigned_integer we avoid having to do 773 anything special for small big-endian values. */ 774 regcache_cooked_read_unsigned (regcache, RET1_REGNUM, &tmp); 775 store_unsigned_integer (valbuf, (len > 4 ? len - 4 : len), tmp); 776 777 /* Ignore return values more than 8 bytes in size because the m32r 778 returns anything more than 8 bytes in the stack. */ 779 if (len > 4) 780 { 781 regcache_cooked_read_unsigned (regcache, RET1_REGNUM + 1, &tmp); 782 store_unsigned_integer (valbuf + len - 4, 4, tmp); 783 } 784} 785 786enum return_value_convention 787m32r_return_value (struct gdbarch *gdbarch, struct type *valtype, 788 struct regcache *regcache, gdb_byte *readbuf, 789 const gdb_byte *writebuf) 790{ 791 if (TYPE_LENGTH (valtype) > 8) 792 return RETURN_VALUE_STRUCT_CONVENTION; 793 else 794 { 795 if (readbuf != NULL) 796 m32r_extract_return_value (valtype, regcache, readbuf); 797 if (writebuf != NULL) 798 m32r_store_return_value (valtype, regcache, writebuf); 799 return RETURN_VALUE_REGISTER_CONVENTION; 800 } 801} 802 803 804 805static CORE_ADDR 806m32r_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame) 807{ 808 return frame_unwind_register_unsigned (next_frame, M32R_PC_REGNUM); 809} 810 811/* Given a GDB frame, determine the address of the calling function's 812 frame. This will be used to create a new GDB frame struct. */ 813 814static void 815m32r_frame_this_id (struct frame_info *next_frame, 816 void **this_prologue_cache, struct frame_id *this_id) 817{ 818 struct m32r_unwind_cache *info 819 = m32r_frame_unwind_cache (next_frame, this_prologue_cache); 820 CORE_ADDR base; 821 CORE_ADDR func; 822 struct minimal_symbol *msym_stack; 823 struct frame_id id; 824 825 /* The FUNC is easy. */ 826 func = frame_func_unwind (next_frame, NORMAL_FRAME); 827 828 /* Check if the stack is empty. */ 829 msym_stack = lookup_minimal_symbol ("_stack", NULL, NULL); 830 if (msym_stack && info->base == SYMBOL_VALUE_ADDRESS (msym_stack)) 831 return; 832 833 /* Hopefully the prologue analysis either correctly determined the 834 frame's base (which is the SP from the previous frame), or set 835 that base to "NULL". */ 836 base = info->prev_sp; 837 if (base == 0) 838 return; 839 840 id = frame_id_build (base, func); 841 (*this_id) = id; 842} 843 844static void 845m32r_frame_prev_register (struct frame_info *next_frame, 846 void **this_prologue_cache, 847 int regnum, int *optimizedp, 848 enum lval_type *lvalp, CORE_ADDR *addrp, 849 int *realnump, gdb_byte *bufferp) 850{ 851 struct m32r_unwind_cache *info 852 = m32r_frame_unwind_cache (next_frame, this_prologue_cache); 853 trad_frame_get_prev_register (next_frame, info->saved_regs, regnum, 854 optimizedp, lvalp, addrp, realnump, bufferp); 855} 856 857static const struct frame_unwind m32r_frame_unwind = { 858 NORMAL_FRAME, 859 m32r_frame_this_id, 860 m32r_frame_prev_register 861}; 862 863static const struct frame_unwind * 864m32r_frame_sniffer (struct frame_info *next_frame) 865{ 866 return &m32r_frame_unwind; 867} 868 869static CORE_ADDR 870m32r_frame_base_address (struct frame_info *next_frame, void **this_cache) 871{ 872 struct m32r_unwind_cache *info 873 = m32r_frame_unwind_cache (next_frame, this_cache); 874 return info->base; 875} 876 877static const struct frame_base m32r_frame_base = { 878 &m32r_frame_unwind, 879 m32r_frame_base_address, 880 m32r_frame_base_address, 881 m32r_frame_base_address 882}; 883 884/* Assuming NEXT_FRAME->prev is a dummy, return the frame ID of that 885 dummy frame. The frame ID's base needs to match the TOS value 886 saved by save_dummy_frame_tos(), and the PC match the dummy frame's 887 breakpoint. */ 888 889static struct frame_id 890m32r_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 891{ 892 return frame_id_build (m32r_unwind_sp (gdbarch, next_frame), 893 frame_pc_unwind (next_frame)); 894} 895 896 897static gdbarch_init_ftype m32r_gdbarch_init; 898 899static struct gdbarch * 900m32r_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches) 901{ 902 struct gdbarch *gdbarch; 903 struct gdbarch_tdep *tdep; 904 905 /* If there is already a candidate, use it. */ 906 arches = gdbarch_list_lookup_by_info (arches, &info); 907 if (arches != NULL) 908 return arches->gdbarch; 909 910 /* Allocate space for the new architecture. */ 911 tdep = XMALLOC (struct gdbarch_tdep); 912 gdbarch = gdbarch_alloc (&info, tdep); 913 914 set_gdbarch_read_pc (gdbarch, m32r_read_pc); 915 set_gdbarch_write_pc (gdbarch, m32r_write_pc); 916 set_gdbarch_unwind_sp (gdbarch, m32r_unwind_sp); 917 918 set_gdbarch_num_regs (gdbarch, M32R_NUM_REGS); 919 set_gdbarch_sp_regnum (gdbarch, M32R_SP_REGNUM); 920 set_gdbarch_register_name (gdbarch, m32r_register_name); 921 set_gdbarch_register_type (gdbarch, m32r_register_type); 922 923 set_gdbarch_push_dummy_call (gdbarch, m32r_push_dummy_call); 924 set_gdbarch_return_value (gdbarch, m32r_return_value); 925 926 set_gdbarch_skip_prologue (gdbarch, m32r_skip_prologue); 927 set_gdbarch_inner_than (gdbarch, core_addr_lessthan); 928 set_gdbarch_breakpoint_from_pc (gdbarch, m32r_breakpoint_from_pc); 929 set_gdbarch_memory_insert_breakpoint (gdbarch, 930 m32r_memory_insert_breakpoint); 931 set_gdbarch_memory_remove_breakpoint (gdbarch, 932 m32r_memory_remove_breakpoint); 933 934 set_gdbarch_frame_align (gdbarch, m32r_frame_align); 935 936 frame_base_set_default (gdbarch, &m32r_frame_base); 937 938 /* Methods for saving / extracting a dummy frame's ID. The ID's 939 stack address must match the SP value returned by 940 PUSH_DUMMY_CALL, and saved by generic_save_dummy_frame_tos. */ 941 set_gdbarch_unwind_dummy_id (gdbarch, m32r_unwind_dummy_id); 942 943 /* Return the unwound PC value. */ 944 set_gdbarch_unwind_pc (gdbarch, m32r_unwind_pc); 945 946 set_gdbarch_print_insn (gdbarch, print_insn_m32r); 947 948 /* Hook in ABI-specific overrides, if they have been registered. */ 949 gdbarch_init_osabi (info, gdbarch); 950 951 /* Hook in the default unwinders. */ 952 frame_unwind_append_sniffer (gdbarch, m32r_frame_sniffer); 953 954 /* Support simple overlay manager. */ 955 set_gdbarch_overlay_update (gdbarch, simple_overlay_update); 956 957 return gdbarch; 958} 959 960void 961_initialize_m32r_tdep (void) 962{ 963 register_gdbarch_init (bfd_arch_m32r, m32r_gdbarch_init); 964} 965