1/* GNU/Linux/CRIS specific low level interface, for the remote server for GDB. 2 Copyright (C) 1995, 1996, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 3 2007 Free Software Foundation, Inc. 4 5 This file is part of GDB. 6 7 This program is free software; you can redistribute it and/or modify 8 it under the terms of the GNU General Public License as published by 9 the Free Software Foundation; either version 3 of the License, or 10 (at your option) any later version. 11 12 This program is distributed in the hope that it will be useful, 13 but WITHOUT ANY WARRANTY; without even the implied warranty of 14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 GNU General Public License for more details. 16 17 You should have received a copy of the GNU General Public License 18 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 19 20#include "server.h" 21#include "linux-low.h" 22#include <sys/ptrace.h> 23 24/* CRISv32 */ 25#define cris_num_regs 49 26 27/* Note: Ignoring USP (having the stack pointer in two locations causes trouble 28 without any significant gain). */ 29 30/* Locations need to match <include/asm/arch/ptrace.h>. */ 31static int cris_regmap[] = { 32 1*4, 2*4, 3*4, 4*4, 33 5*4, 6*4, 7*4, 8*4, 34 9*4, 10*4, 11*4, 12*4, 35 13*4, 14*4, 24*4, 15*4, 36 37 -1, -1, -1, 16*4, 38 -1, 22*4, 23*4, 17*4, 39 -1, -1, 21*4, 20*4, 40 -1, 19*4, -1, 18*4, 41 42 25*4, 43 44 26*4, -1, -1, 29*4, 45 30*4, 31*4, 32*4, 33*4, 46 34*4, 35*4, 36*4, 37*4, 47 38*4, 39*4, 40*4, -1 48 49}; 50 51extern int debug_threads; 52 53static CORE_ADDR 54cris_get_pc (void) 55{ 56 unsigned long pc; 57 collect_register_by_name ("pc", &pc); 58 if (debug_threads) 59 fprintf (stderr, "stop pc is %08lx\n", pc); 60 return pc; 61} 62 63static void 64cris_set_pc (CORE_ADDR pc) 65{ 66 unsigned long newpc = pc; 67 supply_register_by_name ("pc", &newpc); 68} 69 70static const unsigned short cris_breakpoint = 0xe938; 71#define cris_breakpoint_len 2 72 73static int 74cris_breakpoint_at (CORE_ADDR where) 75{ 76 unsigned short insn; 77 78 (*the_target->read_memory) (where, (unsigned char *) &insn, 79 cris_breakpoint_len); 80 if (insn == cris_breakpoint) 81 return 1; 82 83 /* If necessary, recognize more trap instructions here. GDB only uses the 84 one. */ 85 return 0; 86} 87 88/* We only place breakpoints in empty marker functions, and thread locking 89 is outside of the function. So rather than importing software single-step, 90 we can just run until exit. */ 91 92/* FIXME: This function should not be needed, since we have PTRACE_SINGLESTEP 93 for CRISv32. Without it, td_ta_event_getmsg in thread_db_create_event 94 will fail when debugging multi-threaded applications. */ 95 96static CORE_ADDR 97cris_reinsert_addr (void) 98{ 99 unsigned long pc; 100 collect_register_by_name ("srp", &pc); 101 return pc; 102} 103 104static void 105cris_write_data_breakpoint (int bp, unsigned long start, unsigned long end) 106{ 107 switch (bp) 108 { 109 case 0: 110 supply_register_by_name ("s3", &start); 111 supply_register_by_name ("s4", &end); 112 break; 113 case 1: 114 supply_register_by_name ("s5", &start); 115 supply_register_by_name ("s6", &end); 116 break; 117 case 2: 118 supply_register_by_name ("s7", &start); 119 supply_register_by_name ("s8", &end); 120 break; 121 case 3: 122 supply_register_by_name ("s9", &start); 123 supply_register_by_name ("s10", &end); 124 break; 125 case 4: 126 supply_register_by_name ("s11", &start); 127 supply_register_by_name ("s12", &end); 128 break; 129 case 5: 130 supply_register_by_name ("s13", &start); 131 supply_register_by_name ("s14", &end); 132 break; 133 } 134} 135 136static int 137cris_insert_watchpoint (char type, CORE_ADDR addr, int len) 138{ 139 int bp; 140 unsigned long bp_ctrl; 141 unsigned long start, end; 142 unsigned long ccs; 143 144 /* Breakpoint/watchpoint types (GDB terminology): 145 0 = memory breakpoint for instructions 146 (not supported; done via memory write instead) 147 1 = hardware breakpoint for instructions (not supported) 148 2 = write watchpoint (supported) 149 3 = read watchpoint (supported) 150 4 = access watchpoint (supported). */ 151 152 if (type < '2' || type > '4') 153 { 154 /* Unsupported. */ 155 return 1; 156 } 157 158 /* Read watchpoints are set as access watchpoints, because of GDB's 159 inability to deal with pure read watchpoints. */ 160 if (type == '3') 161 type = '4'; 162 163 /* Get the configuration register. */ 164 collect_register_by_name ("s0", &bp_ctrl); 165 166 /* The watchpoint allocation scheme is the simplest possible. 167 For example, if a region is watched for read and 168 a write watch is requested, a new watchpoint will 169 be used. Also, if a watch for a region that is already 170 covered by one or more existing watchpoints, a new 171 watchpoint will be used. */ 172 173 /* First, find a free data watchpoint. */ 174 for (bp = 0; bp < 6; bp++) 175 { 176 /* Each data watchpoint's control registers occupy 2 bits 177 (hence the 3), starting at bit 2 for D0 (hence the 2) 178 with 4 bits between for each watchpoint (yes, the 4). */ 179 if (!(bp_ctrl & (0x3 << (2 + (bp * 4))))) 180 break; 181 } 182 183 if (bp > 5) 184 { 185 /* We're out of watchpoints. */ 186 return -1; 187 } 188 189 /* Configure the control register first. */ 190 if (type == '3' || type == '4') 191 { 192 /* Trigger on read. */ 193 bp_ctrl |= (1 << (2 + bp * 4)); 194 } 195 if (type == '2' || type == '4') 196 { 197 /* Trigger on write. */ 198 bp_ctrl |= (2 << (2 + bp * 4)); 199 } 200 201 /* Setup the configuration register. */ 202 supply_register_by_name ("s0", &bp_ctrl); 203 204 /* Setup the range. */ 205 start = addr; 206 end = addr + len - 1; 207 208 /* Configure the watchpoint register. */ 209 cris_write_data_breakpoint (bp, start, end); 210 211 collect_register_by_name ("ccs", &ccs); 212 /* Set the S1 flag to enable watchpoints. */ 213 ccs |= (1 << 19); 214 supply_register_by_name ("ccs", &ccs); 215 216 return 0; 217} 218 219static int 220cris_remove_watchpoint (char type, CORE_ADDR addr, int len) 221{ 222 int bp; 223 unsigned long bp_ctrl; 224 unsigned long start, end; 225 226 /* Breakpoint/watchpoint types: 227 0 = memory breakpoint for instructions 228 (not supported; done via memory write instead) 229 1 = hardware breakpoint for instructions (not supported) 230 2 = write watchpoint (supported) 231 3 = read watchpoint (supported) 232 4 = access watchpoint (supported). */ 233 if (type < '2' || type > '4') 234 return -1; 235 236 /* Read watchpoints are set as access watchpoints, because of GDB's 237 inability to deal with pure read watchpoints. */ 238 if (type == '3') 239 type = '4'; 240 241 /* Get the configuration register. */ 242 collect_register_by_name ("s0", &bp_ctrl); 243 244 /* Try to find a watchpoint that is configured for the 245 specified range, then check that read/write also matches. */ 246 247 /* Ugly pointer arithmetic, since I cannot rely on a 248 single switch (addr) as there may be several watchpoints with 249 the same start address for example. */ 250 251 unsigned long bp_d_regs[12]; 252 253 /* Get all range registers to simplify search. */ 254 collect_register_by_name ("s3", &bp_d_regs[0]); 255 collect_register_by_name ("s4", &bp_d_regs[1]); 256 collect_register_by_name ("s5", &bp_d_regs[2]); 257 collect_register_by_name ("s6", &bp_d_regs[3]); 258 collect_register_by_name ("s7", &bp_d_regs[4]); 259 collect_register_by_name ("s8", &bp_d_regs[5]); 260 collect_register_by_name ("s9", &bp_d_regs[6]); 261 collect_register_by_name ("s10", &bp_d_regs[7]); 262 collect_register_by_name ("s11", &bp_d_regs[8]); 263 collect_register_by_name ("s12", &bp_d_regs[9]); 264 collect_register_by_name ("s13", &bp_d_regs[10]); 265 collect_register_by_name ("s14", &bp_d_regs[11]); 266 267 for (bp = 0; bp < 6; bp++) 268 { 269 if (bp_d_regs[bp * 2] == addr 270 && bp_d_regs[bp * 2 + 1] == (addr + len - 1)) { 271 /* Matching range. */ 272 int bitpos = 2 + bp * 4; 273 int rw_bits; 274 275 /* Read/write bits for this BP. */ 276 rw_bits = (bp_ctrl & (0x3 << bitpos)) >> bitpos; 277 278 if ((type == '3' && rw_bits == 0x1) 279 || (type == '2' && rw_bits == 0x2) 280 || (type == '4' && rw_bits == 0x3)) 281 { 282 /* Read/write matched. */ 283 break; 284 } 285 } 286 } 287 288 if (bp > 5) 289 { 290 /* No watchpoint matched. */ 291 return -1; 292 } 293 294 /* Found a matching watchpoint. Now, deconfigure it by 295 both disabling read/write in bp_ctrl and zeroing its 296 start/end addresses. */ 297 bp_ctrl &= ~(3 << (2 + (bp * 4))); 298 /* Setup the configuration register. */ 299 supply_register_by_name ("s0", &bp_ctrl); 300 301 start = end = 0; 302 /* Configure the watchpoint register. */ 303 cris_write_data_breakpoint (bp, start, end); 304 305 /* Note that we don't clear the S1 flag here. It's done when continuing. */ 306 return 0; 307} 308 309static int 310cris_stopped_by_watchpoint (void) 311{ 312 unsigned long exs; 313 314 collect_register_by_name ("exs", &exs); 315 316 return (((exs & 0xff00) >> 8) == 0xc); 317} 318 319static CORE_ADDR 320cris_stopped_data_address (void) 321{ 322 unsigned long eda; 323 324 collect_register_by_name ("eda", &eda); 325 326 /* FIXME: Possibly adjust to match watched range. */ 327 return eda; 328} 329 330static void 331cris_fill_gregset (void *buf) 332{ 333 int i; 334 335 for (i = 0; i < cris_num_regs; i++) 336 { 337 if (cris_regmap[i] != -1) 338 collect_register (i, ((char *) buf) + cris_regmap[i]); 339 } 340} 341 342static void 343cris_store_gregset (const void *buf) 344{ 345 int i; 346 347 for (i = 0; i < cris_num_regs; i++) 348 { 349 if (cris_regmap[i] != -1) 350 supply_register (i, ((char *) buf) + cris_regmap[i]); 351 } 352} 353 354typedef unsigned long elf_gregset_t[cris_num_regs]; 355 356struct regset_info target_regsets[] = { 357 { PTRACE_GETREGS, PTRACE_SETREGS, sizeof (elf_gregset_t), 358 GENERAL_REGS, cris_fill_gregset, cris_store_gregset }, 359 { 0, 0, -1, -1, NULL, NULL } 360}; 361 362struct linux_target_ops the_low_target = { 363 -1, 364 NULL, 365 NULL, 366 NULL, 367 cris_get_pc, 368 cris_set_pc, 369 (const unsigned char *) &cris_breakpoint, 370 cris_breakpoint_len, 371 cris_reinsert_addr, 372 0, 373 cris_breakpoint_at, 374 cris_insert_watchpoint, 375 cris_remove_watchpoint, 376 cris_stopped_by_watchpoint, 377 cris_stopped_data_address, 378}; 379