1/* Target-dependent code for AMD64. 2 3 Copyright (C) 2001, 2002, 2003, 2004, 2005, 2006, 2007 4 Free Software Foundation, Inc. 5 6 Contributed by Jiri Smid, SuSE Labs. 7 8 This file is part of GDB. 9 10 This program is free software; you can redistribute it and/or modify 11 it under the terms of the GNU General Public License as published by 12 the Free Software Foundation; either version 3 of the License, or 13 (at your option) any later version. 14 15 This program is distributed in the hope that it will be useful, 16 but WITHOUT ANY WARRANTY; without even the implied warranty of 17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 18 GNU General Public License for more details. 19 20 You should have received a copy of the GNU General Public License 21 along with this program. If not, see <http://www.gnu.org/licenses/>. */ 22 23#include "defs.h" 24#include "arch-utils.h" 25#include "block.h" 26#include "dummy-frame.h" 27#include "frame.h" 28#include "frame-base.h" 29#include "frame-unwind.h" 30#include "inferior.h" 31#include "gdbcmd.h" 32#include "gdbcore.h" 33#include "objfiles.h" 34#include "regcache.h" 35#include "regset.h" 36#include "symfile.h" 37 38#include "gdb_assert.h" 39 40#include "amd64-tdep.h" 41#include "i387-tdep.h" 42 43/* Note that the AMD64 architecture was previously known as x86-64. 44 The latter is (forever) engraved into the canonical system name as 45 returned by config.guess, and used as the name for the AMD64 port 46 of GNU/Linux. The BSD's have renamed their ports to amd64; they 47 don't like to shout. For GDB we prefer the amd64_-prefix over the 48 x86_64_-prefix since it's so much easier to type. */ 49 50/* Register information. */ 51 52static const char *amd64_register_names[] = 53{ 54 "rax", "rbx", "rcx", "rdx", "rsi", "rdi", "rbp", "rsp", 55 56 /* %r8 is indeed register number 8. */ 57 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", 58 "rip", "eflags", "cs", "ss", "ds", "es", "fs", "gs", 59 60 /* %st0 is register number 24. */ 61 "st0", "st1", "st2", "st3", "st4", "st5", "st6", "st7", 62 "fctrl", "fstat", "ftag", "fiseg", "fioff", "foseg", "fooff", "fop", 63 64 /* %xmm0 is register number 40. */ 65 "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5", "xmm6", "xmm7", 66 "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13", "xmm14", "xmm15", 67 "mxcsr", 68}; 69 70/* Total number of registers. */ 71#define AMD64_NUM_REGS ARRAY_SIZE (amd64_register_names) 72 73/* Return the name of register REGNUM. */ 74 75const char * 76amd64_register_name (int regnum) 77{ 78 if (regnum >= 0 && regnum < AMD64_NUM_REGS) 79 return amd64_register_names[regnum]; 80 81 return NULL; 82} 83 84/* Return the GDB type object for the "standard" data type of data in 85 register REGNUM. */ 86 87struct type * 88amd64_register_type (struct gdbarch *gdbarch, int regnum) 89{ 90 if (regnum >= AMD64_RAX_REGNUM && regnum <= AMD64_RDI_REGNUM) 91 return builtin_type_int64; 92 if (regnum == AMD64_RBP_REGNUM || regnum == AMD64_RSP_REGNUM) 93 return builtin_type_void_data_ptr; 94 if (regnum >= AMD64_R8_REGNUM && regnum <= AMD64_R15_REGNUM) 95 return builtin_type_int64; 96 if (regnum == AMD64_RIP_REGNUM) 97 return builtin_type_void_func_ptr; 98 if (regnum == AMD64_EFLAGS_REGNUM) 99 return i386_eflags_type; 100 if (regnum >= AMD64_CS_REGNUM && regnum <= AMD64_GS_REGNUM) 101 return builtin_type_int32; 102 if (regnum >= AMD64_ST0_REGNUM && regnum <= AMD64_ST0_REGNUM + 7) 103 return builtin_type_i387_ext; 104 if (regnum >= AMD64_FCTRL_REGNUM && regnum <= AMD64_FCTRL_REGNUM + 7) 105 return builtin_type_int32; 106 if (regnum >= AMD64_XMM0_REGNUM && regnum <= AMD64_XMM0_REGNUM + 15) 107 return i386_sse_type (gdbarch); 108 if (regnum == AMD64_MXCSR_REGNUM) 109 return i386_mxcsr_type; 110 111 internal_error (__FILE__, __LINE__, _("invalid regnum")); 112} 113 114/* DWARF Register Number Mapping as defined in the System V psABI, 115 section 3.6. */ 116 117static int amd64_dwarf_regmap[] = 118{ 119 /* General Purpose Registers RAX, RDX, RCX, RBX, RSI, RDI. */ 120 AMD64_RAX_REGNUM, AMD64_RDX_REGNUM, 121 AMD64_RCX_REGNUM, AMD64_RBX_REGNUM, 122 AMD64_RSI_REGNUM, AMD64_RDI_REGNUM, 123 124 /* Frame Pointer Register RBP. */ 125 AMD64_RBP_REGNUM, 126 127 /* Stack Pointer Register RSP. */ 128 AMD64_RSP_REGNUM, 129 130 /* Extended Integer Registers 8 - 15. */ 131 8, 9, 10, 11, 12, 13, 14, 15, 132 133 /* Return Address RA. Mapped to RIP. */ 134 AMD64_RIP_REGNUM, 135 136 /* SSE Registers 0 - 7. */ 137 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 138 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 139 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 140 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 141 142 /* Extended SSE Registers 8 - 15. */ 143 AMD64_XMM0_REGNUM + 8, AMD64_XMM0_REGNUM + 9, 144 AMD64_XMM0_REGNUM + 10, AMD64_XMM0_REGNUM + 11, 145 AMD64_XMM0_REGNUM + 12, AMD64_XMM0_REGNUM + 13, 146 AMD64_XMM0_REGNUM + 14, AMD64_XMM0_REGNUM + 15, 147 148 /* Floating Point Registers 0-7. */ 149 AMD64_ST0_REGNUM + 0, AMD64_ST0_REGNUM + 1, 150 AMD64_ST0_REGNUM + 2, AMD64_ST0_REGNUM + 3, 151 AMD64_ST0_REGNUM + 4, AMD64_ST0_REGNUM + 5, 152 AMD64_ST0_REGNUM + 6, AMD64_ST0_REGNUM + 7, 153 154 /* Control and Status Flags Register. */ 155 AMD64_EFLAGS_REGNUM, 156 157 /* Selector Registers. */ 158 AMD64_ES_REGNUM, 159 AMD64_CS_REGNUM, 160 AMD64_SS_REGNUM, 161 AMD64_DS_REGNUM, 162 AMD64_FS_REGNUM, 163 AMD64_GS_REGNUM, 164 -1, 165 -1, 166 167 /* Segment Base Address Registers. */ 168 -1, 169 -1, 170 -1, 171 -1, 172 173 /* Special Selector Registers. */ 174 -1, 175 -1, 176 177 /* Floating Point Control Registers. */ 178 AMD64_MXCSR_REGNUM, 179 AMD64_FCTRL_REGNUM, 180 AMD64_FSTAT_REGNUM 181}; 182 183static const int amd64_dwarf_regmap_len = 184 (sizeof (amd64_dwarf_regmap) / sizeof (amd64_dwarf_regmap[0])); 185 186/* Convert DWARF register number REG to the appropriate register 187 number used by GDB. */ 188 189static int 190amd64_dwarf_reg_to_regnum (int reg) 191{ 192 int regnum = -1; 193 194 if (reg >= 0 && reg < amd64_dwarf_regmap_len) 195 regnum = amd64_dwarf_regmap[reg]; 196 197 if (regnum == -1) 198 warning (_("Unmapped DWARF Register #%d encountered."), reg); 199 200 return regnum; 201} 202 203/* Return nonzero if a value of type TYPE stored in register REGNUM 204 needs any special handling. */ 205 206static int 207amd64_convert_register_p (int regnum, struct type *type) 208{ 209 return i386_fp_regnum_p (regnum); 210} 211 212 213/* Register classes as defined in the psABI. */ 214 215enum amd64_reg_class 216{ 217 AMD64_INTEGER, 218 AMD64_SSE, 219 AMD64_SSEUP, 220 AMD64_X87, 221 AMD64_X87UP, 222 AMD64_COMPLEX_X87, 223 AMD64_NO_CLASS, 224 AMD64_MEMORY 225}; 226 227/* Return the union class of CLASS1 and CLASS2. See the psABI for 228 details. */ 229 230static enum amd64_reg_class 231amd64_merge_classes (enum amd64_reg_class class1, enum amd64_reg_class class2) 232{ 233 /* Rule (a): If both classes are equal, this is the resulting class. */ 234 if (class1 == class2) 235 return class1; 236 237 /* Rule (b): If one of the classes is NO_CLASS, the resulting class 238 is the other class. */ 239 if (class1 == AMD64_NO_CLASS) 240 return class2; 241 if (class2 == AMD64_NO_CLASS) 242 return class1; 243 244 /* Rule (c): If one of the classes is MEMORY, the result is MEMORY. */ 245 if (class1 == AMD64_MEMORY || class2 == AMD64_MEMORY) 246 return AMD64_MEMORY; 247 248 /* Rule (d): If one of the classes is INTEGER, the result is INTEGER. */ 249 if (class1 == AMD64_INTEGER || class2 == AMD64_INTEGER) 250 return AMD64_INTEGER; 251 252 /* Rule (e): If one of the classes is X87, X87UP, COMPLEX_X87 class, 253 MEMORY is used as class. */ 254 if (class1 == AMD64_X87 || class1 == AMD64_X87UP 255 || class1 == AMD64_COMPLEX_X87 || class2 == AMD64_X87 256 || class2 == AMD64_X87UP || class2 == AMD64_COMPLEX_X87) 257 return AMD64_MEMORY; 258 259 /* Rule (f): Otherwise class SSE is used. */ 260 return AMD64_SSE; 261} 262 263static void amd64_classify (struct type *type, enum amd64_reg_class class[2]); 264 265/* Return non-zero if TYPE is a non-POD structure or union type. */ 266 267static int 268amd64_non_pod_p (struct type *type) 269{ 270 /* ??? A class with a base class certainly isn't POD, but does this 271 catch all non-POD structure types? */ 272 if (TYPE_CODE (type) == TYPE_CODE_STRUCT && TYPE_N_BASECLASSES (type) > 0) 273 return 1; 274 275 return 0; 276} 277 278/* Classify TYPE according to the rules for aggregate (structures and 279 arrays) and union types, and store the result in CLASS. */ 280 281static void 282amd64_classify_aggregate (struct type *type, enum amd64_reg_class class[2]) 283{ 284 int len = TYPE_LENGTH (type); 285 286 /* 1. If the size of an object is larger than two eightbytes, or in 287 C++, is a non-POD structure or union type, or contains 288 unaligned fields, it has class memory. */ 289 if (len > 16 || amd64_non_pod_p (type)) 290 { 291 class[0] = class[1] = AMD64_MEMORY; 292 return; 293 } 294 295 /* 2. Both eightbytes get initialized to class NO_CLASS. */ 296 class[0] = class[1] = AMD64_NO_CLASS; 297 298 /* 3. Each field of an object is classified recursively so that 299 always two fields are considered. The resulting class is 300 calculated according to the classes of the fields in the 301 eightbyte: */ 302 303 if (TYPE_CODE (type) == TYPE_CODE_ARRAY) 304 { 305 struct type *subtype = check_typedef (TYPE_TARGET_TYPE (type)); 306 307 /* All fields in an array have the same type. */ 308 amd64_classify (subtype, class); 309 if (len > 8 && class[1] == AMD64_NO_CLASS) 310 class[1] = class[0]; 311 } 312 else 313 { 314 int i; 315 316 /* Structure or union. */ 317 gdb_assert (TYPE_CODE (type) == TYPE_CODE_STRUCT 318 || TYPE_CODE (type) == TYPE_CODE_UNION); 319 320 for (i = 0; i < TYPE_NFIELDS (type); i++) 321 { 322 struct type *subtype = check_typedef (TYPE_FIELD_TYPE (type, i)); 323 int pos = TYPE_FIELD_BITPOS (type, i) / 64; 324 enum amd64_reg_class subclass[2]; 325 326 /* Ignore static fields. */ 327 if (TYPE_FIELD_STATIC (type, i)) 328 continue; 329 330 gdb_assert (pos == 0 || pos == 1); 331 332 amd64_classify (subtype, subclass); 333 class[pos] = amd64_merge_classes (class[pos], subclass[0]); 334 if (pos == 0) 335 class[1] = amd64_merge_classes (class[1], subclass[1]); 336 } 337 } 338 339 /* 4. Then a post merger cleanup is done: */ 340 341 /* Rule (a): If one of the classes is MEMORY, the whole argument is 342 passed in memory. */ 343 if (class[0] == AMD64_MEMORY || class[1] == AMD64_MEMORY) 344 class[0] = class[1] = AMD64_MEMORY; 345 346 /* Rule (b): If SSEUP is not preceeded by SSE, it is converted to 347 SSE. */ 348 if (class[0] == AMD64_SSEUP) 349 class[0] = AMD64_SSE; 350 if (class[1] == AMD64_SSEUP && class[0] != AMD64_SSE) 351 class[1] = AMD64_SSE; 352} 353 354/* Classify TYPE, and store the result in CLASS. */ 355 356static void 357amd64_classify (struct type *type, enum amd64_reg_class class[2]) 358{ 359 enum type_code code = TYPE_CODE (type); 360 int len = TYPE_LENGTH (type); 361 362 class[0] = class[1] = AMD64_NO_CLASS; 363 364 /* Arguments of types (signed and unsigned) _Bool, char, short, int, 365 long, long long, and pointers are in the INTEGER class. Similarly, 366 range types, used by languages such as Ada, are also in the INTEGER 367 class. */ 368 if ((code == TYPE_CODE_INT || code == TYPE_CODE_ENUM 369 || code == TYPE_CODE_BOOL || code == TYPE_CODE_RANGE 370 || code == TYPE_CODE_PTR || code == TYPE_CODE_REF) 371 && (len == 1 || len == 2 || len == 4 || len == 8)) 372 class[0] = AMD64_INTEGER; 373 374 /* Arguments of types float, double and __m64 are in class SSE. */ 375 else if (code == TYPE_CODE_FLT && (len == 4 || len == 8)) 376 /* FIXME: __m64 . */ 377 class[0] = AMD64_SSE; 378 379 /* Arguments of types __float128 and __m128 are split into two 380 halves. The least significant ones belong to class SSE, the most 381 significant one to class SSEUP. */ 382 /* FIXME: __float128, __m128. */ 383 384 /* The 64-bit mantissa of arguments of type long double belongs to 385 class X87, the 16-bit exponent plus 6 bytes of padding belongs to 386 class X87UP. */ 387 else if (code == TYPE_CODE_FLT && len == 16) 388 /* Class X87 and X87UP. */ 389 class[0] = AMD64_X87, class[1] = AMD64_X87UP; 390 391 /* Aggregates. */ 392 else if (code == TYPE_CODE_ARRAY || code == TYPE_CODE_STRUCT 393 || code == TYPE_CODE_UNION) 394 amd64_classify_aggregate (type, class); 395} 396 397static enum return_value_convention 398amd64_return_value (struct gdbarch *gdbarch, struct type *type, 399 struct regcache *regcache, 400 gdb_byte *readbuf, const gdb_byte *writebuf) 401{ 402 enum amd64_reg_class class[2]; 403 int len = TYPE_LENGTH (type); 404 static int integer_regnum[] = { AMD64_RAX_REGNUM, AMD64_RDX_REGNUM }; 405 static int sse_regnum[] = { AMD64_XMM0_REGNUM, AMD64_XMM1_REGNUM }; 406 int integer_reg = 0; 407 int sse_reg = 0; 408 int i; 409 410 gdb_assert (!(readbuf && writebuf)); 411 412 /* 1. Classify the return type with the classification algorithm. */ 413 amd64_classify (type, class); 414 415 /* 2. If the type has class MEMORY, then the caller provides space 416 for the return value and passes the address of this storage in 417 %rdi as if it were the first argument to the function. In effect, 418 this address becomes a hidden first argument. 419 420 On return %rax will contain the address that has been passed in 421 by the caller in %rdi. */ 422 if (class[0] == AMD64_MEMORY) 423 { 424 /* As indicated by the comment above, the ABI guarantees that we 425 can always find the return value just after the function has 426 returned. */ 427 428 if (readbuf) 429 { 430 ULONGEST addr; 431 432 regcache_raw_read_unsigned (regcache, AMD64_RAX_REGNUM, &addr); 433 read_memory (addr, readbuf, TYPE_LENGTH (type)); 434 } 435 436 return RETURN_VALUE_ABI_RETURNS_ADDRESS; 437 } 438 439 gdb_assert (class[1] != AMD64_MEMORY); 440 gdb_assert (len <= 16); 441 442 for (i = 0; len > 0; i++, len -= 8) 443 { 444 int regnum = -1; 445 int offset = 0; 446 447 switch (class[i]) 448 { 449 case AMD64_INTEGER: 450 /* 3. If the class is INTEGER, the next available register 451 of the sequence %rax, %rdx is used. */ 452 regnum = integer_regnum[integer_reg++]; 453 break; 454 455 case AMD64_SSE: 456 /* 4. If the class is SSE, the next available SSE register 457 of the sequence %xmm0, %xmm1 is used. */ 458 regnum = sse_regnum[sse_reg++]; 459 break; 460 461 case AMD64_SSEUP: 462 /* 5. If the class is SSEUP, the eightbyte is passed in the 463 upper half of the last used SSE register. */ 464 gdb_assert (sse_reg > 0); 465 regnum = sse_regnum[sse_reg - 1]; 466 offset = 8; 467 break; 468 469 case AMD64_X87: 470 /* 6. If the class is X87, the value is returned on the X87 471 stack in %st0 as 80-bit x87 number. */ 472 regnum = AMD64_ST0_REGNUM; 473 if (writebuf) 474 i387_return_value (gdbarch, regcache); 475 break; 476 477 case AMD64_X87UP: 478 /* 7. If the class is X87UP, the value is returned together 479 with the previous X87 value in %st0. */ 480 gdb_assert (i > 0 && class[0] == AMD64_X87); 481 regnum = AMD64_ST0_REGNUM; 482 offset = 8; 483 len = 2; 484 break; 485 486 case AMD64_NO_CLASS: 487 continue; 488 489 default: 490 gdb_assert (!"Unexpected register class."); 491 } 492 493 gdb_assert (regnum != -1); 494 495 if (readbuf) 496 regcache_raw_read_part (regcache, regnum, offset, min (len, 8), 497 readbuf + i * 8); 498 if (writebuf) 499 regcache_raw_write_part (regcache, regnum, offset, min (len, 8), 500 writebuf + i * 8); 501 } 502 503 return RETURN_VALUE_REGISTER_CONVENTION; 504} 505 506 507static CORE_ADDR 508amd64_push_arguments (struct regcache *regcache, int nargs, 509 struct value **args, CORE_ADDR sp, int struct_return) 510{ 511 static int integer_regnum[] = 512 { 513 AMD64_RDI_REGNUM, /* %rdi */ 514 AMD64_RSI_REGNUM, /* %rsi */ 515 AMD64_RDX_REGNUM, /* %rdx */ 516 AMD64_RCX_REGNUM, /* %rcx */ 517 8, /* %r8 */ 518 9 /* %r9 */ 519 }; 520 static int sse_regnum[] = 521 { 522 /* %xmm0 ... %xmm7 */ 523 AMD64_XMM0_REGNUM + 0, AMD64_XMM1_REGNUM, 524 AMD64_XMM0_REGNUM + 2, AMD64_XMM0_REGNUM + 3, 525 AMD64_XMM0_REGNUM + 4, AMD64_XMM0_REGNUM + 5, 526 AMD64_XMM0_REGNUM + 6, AMD64_XMM0_REGNUM + 7, 527 }; 528 struct value **stack_args = alloca (nargs * sizeof (struct value *)); 529 int num_stack_args = 0; 530 int num_elements = 0; 531 int element = 0; 532 int integer_reg = 0; 533 int sse_reg = 0; 534 int i; 535 536 /* Reserve a register for the "hidden" argument. */ 537 if (struct_return) 538 integer_reg++; 539 540 for (i = 0; i < nargs; i++) 541 { 542 struct type *type = value_type (args[i]); 543 int len = TYPE_LENGTH (type); 544 enum amd64_reg_class class[2]; 545 int needed_integer_regs = 0; 546 int needed_sse_regs = 0; 547 int j; 548 549 /* Classify argument. */ 550 amd64_classify (type, class); 551 552 /* Calculate the number of integer and SSE registers needed for 553 this argument. */ 554 for (j = 0; j < 2; j++) 555 { 556 if (class[j] == AMD64_INTEGER) 557 needed_integer_regs++; 558 else if (class[j] == AMD64_SSE) 559 needed_sse_regs++; 560 } 561 562 /* Check whether enough registers are available, and if the 563 argument should be passed in registers at all. */ 564 if (integer_reg + needed_integer_regs > ARRAY_SIZE (integer_regnum) 565 || sse_reg + needed_sse_regs > ARRAY_SIZE (sse_regnum) 566 || (needed_integer_regs == 0 && needed_sse_regs == 0)) 567 { 568 /* The argument will be passed on the stack. */ 569 num_elements += ((len + 7) / 8); 570 stack_args[num_stack_args++] = args[i]; 571 } 572 else 573 { 574 /* The argument will be passed in registers. */ 575 const gdb_byte *valbuf = value_contents (args[i]); 576 gdb_byte buf[8]; 577 578 gdb_assert (len <= 16); 579 580 for (j = 0; len > 0; j++, len -= 8) 581 { 582 int regnum = -1; 583 int offset = 0; 584 585 switch (class[j]) 586 { 587 case AMD64_INTEGER: 588 regnum = integer_regnum[integer_reg++]; 589 break; 590 591 case AMD64_SSE: 592 regnum = sse_regnum[sse_reg++]; 593 break; 594 595 case AMD64_SSEUP: 596 gdb_assert (sse_reg > 0); 597 regnum = sse_regnum[sse_reg - 1]; 598 offset = 8; 599 break; 600 601 default: 602 gdb_assert (!"Unexpected register class."); 603 } 604 605 gdb_assert (regnum != -1); 606 memset (buf, 0, sizeof buf); 607 memcpy (buf, valbuf + j * 8, min (len, 8)); 608 regcache_raw_write_part (regcache, regnum, offset, 8, buf); 609 } 610 } 611 } 612 613 /* Allocate space for the arguments on the stack. */ 614 sp -= num_elements * 8; 615 616 /* The psABI says that "The end of the input argument area shall be 617 aligned on a 16 byte boundary." */ 618 sp &= ~0xf; 619 620 /* Write out the arguments to the stack. */ 621 for (i = 0; i < num_stack_args; i++) 622 { 623 struct type *type = value_type (stack_args[i]); 624 const gdb_byte *valbuf = value_contents (stack_args[i]); 625 int len = TYPE_LENGTH (type); 626 627 write_memory (sp + element * 8, valbuf, len); 628 element += ((len + 7) / 8); 629 } 630 631 /* The psABI says that "For calls that may call functions that use 632 varargs or stdargs (prototype-less calls or calls to functions 633 containing ellipsis (...) in the declaration) %al is used as 634 hidden argument to specify the number of SSE registers used. */ 635 regcache_raw_write_unsigned (regcache, AMD64_RAX_REGNUM, sse_reg); 636 return sp; 637} 638 639static CORE_ADDR 640amd64_push_dummy_call (struct gdbarch *gdbarch, struct value *function, 641 struct regcache *regcache, CORE_ADDR bp_addr, 642 int nargs, struct value **args, CORE_ADDR sp, 643 int struct_return, CORE_ADDR struct_addr) 644{ 645 gdb_byte buf[8]; 646 647 /* Pass arguments. */ 648 sp = amd64_push_arguments (regcache, nargs, args, sp, struct_return); 649 650 /* Pass "hidden" argument". */ 651 if (struct_return) 652 { 653 store_unsigned_integer (buf, 8, struct_addr); 654 regcache_cooked_write (regcache, AMD64_RDI_REGNUM, buf); 655 } 656 657 /* Store return address. */ 658 sp -= 8; 659 store_unsigned_integer (buf, 8, bp_addr); 660 write_memory (sp, buf, 8); 661 662 /* Finally, update the stack pointer... */ 663 store_unsigned_integer (buf, 8, sp); 664 regcache_cooked_write (regcache, AMD64_RSP_REGNUM, buf); 665 666 /* ...and fake a frame pointer. */ 667 regcache_cooked_write (regcache, AMD64_RBP_REGNUM, buf); 668 669 return sp + 16; 670} 671 672 673/* The maximum number of saved registers. This should include %rip. */ 674#define AMD64_NUM_SAVED_REGS AMD64_NUM_GREGS 675 676struct amd64_frame_cache 677{ 678 /* Base address. */ 679 CORE_ADDR base; 680 CORE_ADDR sp_offset; 681 CORE_ADDR pc; 682 683 /* Saved registers. */ 684 CORE_ADDR saved_regs[AMD64_NUM_SAVED_REGS]; 685 CORE_ADDR saved_sp; 686 687 /* Do we have a frame? */ 688 int frameless_p; 689}; 690 691/* Initialize a frame cache. */ 692 693static void 694amd64_init_frame_cache (struct amd64_frame_cache *cache) 695{ 696 int i; 697 698 /* Base address. */ 699 cache->base = 0; 700 cache->sp_offset = -8; 701 cache->pc = 0; 702 703 /* Saved registers. We initialize these to -1 since zero is a valid 704 offset (that's where %rbp is supposed to be stored). */ 705 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 706 cache->saved_regs[i] = -1; 707 cache->saved_sp = 0; 708 709 /* Frameless until proven otherwise. */ 710 cache->frameless_p = 1; 711} 712 713/* Allocate and initialize a frame cache. */ 714 715static struct amd64_frame_cache * 716amd64_alloc_frame_cache (void) 717{ 718 struct amd64_frame_cache *cache; 719 720 cache = FRAME_OBSTACK_ZALLOC (struct amd64_frame_cache); 721 amd64_init_frame_cache (cache); 722 return cache; 723} 724 725/* Do a limited analysis of the prologue at PC and update CACHE 726 accordingly. Bail out early if CURRENT_PC is reached. Return the 727 address where the analysis stopped. 728 729 We will handle only functions beginning with: 730 731 pushq %rbp 0x55 732 movq %rsp, %rbp 0x48 0x89 0xe5 733 734 Any function that doesn't start with this sequence will be assumed 735 to have no prologue and thus no valid frame pointer in %rbp. */ 736 737static CORE_ADDR 738amd64_analyze_prologue (CORE_ADDR pc, CORE_ADDR current_pc, 739 struct amd64_frame_cache *cache) 740{ 741 static gdb_byte proto[3] = { 0x48, 0x89, 0xe5 }; /* movq %rsp, %rbp */ 742 gdb_byte buf[3]; 743 gdb_byte op; 744 745 if (current_pc <= pc) 746 return current_pc; 747 748 op = read_memory_unsigned_integer (pc, 1); 749 750 if (op == 0x55) /* pushq %rbp */ 751 { 752 /* Take into account that we've executed the `pushq %rbp' that 753 starts this instruction sequence. */ 754 cache->saved_regs[AMD64_RBP_REGNUM] = 0; 755 cache->sp_offset += 8; 756 757 /* If that's all, return now. */ 758 if (current_pc <= pc + 1) 759 return current_pc; 760 761 /* Check for `movq %rsp, %rbp'. */ 762 read_memory (pc + 1, buf, 3); 763 if (memcmp (buf, proto, 3) != 0) 764 return pc + 1; 765 766 /* OK, we actually have a frame. */ 767 cache->frameless_p = 0; 768 return pc + 4; 769 } 770 771 return pc; 772} 773 774/* Return PC of first real instruction. */ 775 776static CORE_ADDR 777amd64_skip_prologue (CORE_ADDR start_pc) 778{ 779 struct amd64_frame_cache cache; 780 CORE_ADDR pc; 781 782 amd64_init_frame_cache (&cache); 783 pc = amd64_analyze_prologue (start_pc, 0xffffffffffffffffLL, &cache); 784 if (cache.frameless_p) 785 return start_pc; 786 787 return pc; 788} 789 790 791/* Normal frames. */ 792 793static struct amd64_frame_cache * 794amd64_frame_cache (struct frame_info *next_frame, void **this_cache) 795{ 796 struct amd64_frame_cache *cache; 797 gdb_byte buf[8]; 798 int i; 799 800 if (*this_cache) 801 return *this_cache; 802 803 cache = amd64_alloc_frame_cache (); 804 *this_cache = cache; 805 806 cache->pc = frame_func_unwind (next_frame, NORMAL_FRAME); 807 if (cache->pc != 0) 808 amd64_analyze_prologue (cache->pc, frame_pc_unwind (next_frame), cache); 809 810 if (cache->frameless_p) 811 { 812 /* We didn't find a valid frame. If we're at the start of a 813 function, or somewhere half-way its prologue, the function's 814 frame probably hasn't been fully setup yet. Try to 815 reconstruct the base address for the stack frame by looking 816 at the stack pointer. For truly "frameless" functions this 817 might work too. */ 818 819 frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf); 820 cache->base = extract_unsigned_integer (buf, 8) + cache->sp_offset; 821 } 822 else 823 { 824 frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf); 825 cache->base = extract_unsigned_integer (buf, 8); 826 } 827 828 /* Now that we have the base address for the stack frame we can 829 calculate the value of %rsp in the calling frame. */ 830 cache->saved_sp = cache->base + 16; 831 832 /* For normal frames, %rip is stored at 8(%rbp). If we don't have a 833 frame we find it at the same offset from the reconstructed base 834 address. */ 835 cache->saved_regs[AMD64_RIP_REGNUM] = 8; 836 837 /* Adjust all the saved registers such that they contain addresses 838 instead of offsets. */ 839 for (i = 0; i < AMD64_NUM_SAVED_REGS; i++) 840 if (cache->saved_regs[i] != -1) 841 cache->saved_regs[i] += cache->base; 842 843 return cache; 844} 845 846static void 847amd64_frame_this_id (struct frame_info *next_frame, void **this_cache, 848 struct frame_id *this_id) 849{ 850 struct amd64_frame_cache *cache = 851 amd64_frame_cache (next_frame, this_cache); 852 853 /* This marks the outermost frame. */ 854 if (cache->base == 0) 855 return; 856 857 (*this_id) = frame_id_build (cache->base + 16, cache->pc); 858} 859 860static void 861amd64_frame_prev_register (struct frame_info *next_frame, void **this_cache, 862 int regnum, int *optimizedp, 863 enum lval_type *lvalp, CORE_ADDR *addrp, 864 int *realnump, gdb_byte *valuep) 865{ 866 struct amd64_frame_cache *cache = 867 amd64_frame_cache (next_frame, this_cache); 868 869 gdb_assert (regnum >= 0); 870 871 if (regnum == gdbarch_sp_regnum (current_gdbarch) && cache->saved_sp) 872 { 873 *optimizedp = 0; 874 *lvalp = not_lval; 875 *addrp = 0; 876 *realnump = -1; 877 if (valuep) 878 { 879 /* Store the value. */ 880 store_unsigned_integer (valuep, 8, cache->saved_sp); 881 } 882 return; 883 } 884 885 if (regnum < AMD64_NUM_SAVED_REGS && cache->saved_regs[regnum] != -1) 886 { 887 *optimizedp = 0; 888 *lvalp = lval_memory; 889 *addrp = cache->saved_regs[regnum]; 890 *realnump = -1; 891 if (valuep) 892 { 893 /* Read the value in from memory. */ 894 read_memory (*addrp, valuep, 895 register_size (current_gdbarch, regnum)); 896 } 897 return; 898 } 899 900 *optimizedp = 0; 901 *lvalp = lval_register; 902 *addrp = 0; 903 *realnump = regnum; 904 if (valuep) 905 frame_unwind_register (next_frame, (*realnump), valuep); 906} 907 908static const struct frame_unwind amd64_frame_unwind = 909{ 910 NORMAL_FRAME, 911 amd64_frame_this_id, 912 amd64_frame_prev_register 913}; 914 915static const struct frame_unwind * 916amd64_frame_sniffer (struct frame_info *next_frame) 917{ 918 return &amd64_frame_unwind; 919} 920 921 922/* Signal trampolines. */ 923 924/* FIXME: kettenis/20030419: Perhaps, we can unify the 32-bit and 925 64-bit variants. This would require using identical frame caches 926 on both platforms. */ 927 928static struct amd64_frame_cache * 929amd64_sigtramp_frame_cache (struct frame_info *next_frame, void **this_cache) 930{ 931 struct amd64_frame_cache *cache; 932 struct gdbarch_tdep *tdep = gdbarch_tdep (current_gdbarch); 933 CORE_ADDR addr; 934 gdb_byte buf[8]; 935 int i; 936 937 if (*this_cache) 938 return *this_cache; 939 940 cache = amd64_alloc_frame_cache (); 941 942 frame_unwind_register (next_frame, AMD64_RSP_REGNUM, buf); 943 cache->base = extract_unsigned_integer (buf, 8) - 8; 944 945 addr = tdep->sigcontext_addr (next_frame); 946 gdb_assert (tdep->sc_reg_offset); 947 gdb_assert (tdep->sc_num_regs <= AMD64_NUM_SAVED_REGS); 948 for (i = 0; i < tdep->sc_num_regs; i++) 949 if (tdep->sc_reg_offset[i] != -1) 950 cache->saved_regs[i] = addr + tdep->sc_reg_offset[i]; 951 952 *this_cache = cache; 953 return cache; 954} 955 956static void 957amd64_sigtramp_frame_this_id (struct frame_info *next_frame, 958 void **this_cache, struct frame_id *this_id) 959{ 960 struct amd64_frame_cache *cache = 961 amd64_sigtramp_frame_cache (next_frame, this_cache); 962 963 (*this_id) = frame_id_build (cache->base + 16, frame_pc_unwind (next_frame)); 964} 965 966static void 967amd64_sigtramp_frame_prev_register (struct frame_info *next_frame, 968 void **this_cache, 969 int regnum, int *optimizedp, 970 enum lval_type *lvalp, CORE_ADDR *addrp, 971 int *realnump, gdb_byte *valuep) 972{ 973 /* Make sure we've initialized the cache. */ 974 amd64_sigtramp_frame_cache (next_frame, this_cache); 975 976 amd64_frame_prev_register (next_frame, this_cache, regnum, 977 optimizedp, lvalp, addrp, realnump, valuep); 978} 979 980static const struct frame_unwind amd64_sigtramp_frame_unwind = 981{ 982 SIGTRAMP_FRAME, 983 amd64_sigtramp_frame_this_id, 984 amd64_sigtramp_frame_prev_register 985}; 986 987static const struct frame_unwind * 988amd64_sigtramp_frame_sniffer (struct frame_info *next_frame) 989{ 990 struct gdbarch_tdep *tdep = gdbarch_tdep (get_frame_arch (next_frame)); 991 992 /* We shouldn't even bother if we don't have a sigcontext_addr 993 handler. */ 994 if (tdep->sigcontext_addr == NULL) 995 return NULL; 996 997 if (tdep->sigtramp_p != NULL) 998 { 999 if (tdep->sigtramp_p (next_frame)) 1000 return &amd64_sigtramp_frame_unwind; 1001 } 1002 1003 if (tdep->sigtramp_start != 0) 1004 { 1005 CORE_ADDR pc = frame_pc_unwind (next_frame); 1006 1007 gdb_assert (tdep->sigtramp_end != 0); 1008 if (pc >= tdep->sigtramp_start && pc < tdep->sigtramp_end) 1009 return &amd64_sigtramp_frame_unwind; 1010 } 1011 1012 return NULL; 1013} 1014 1015 1016static CORE_ADDR 1017amd64_frame_base_address (struct frame_info *next_frame, void **this_cache) 1018{ 1019 struct amd64_frame_cache *cache = 1020 amd64_frame_cache (next_frame, this_cache); 1021 1022 return cache->base; 1023} 1024 1025static const struct frame_base amd64_frame_base = 1026{ 1027 &amd64_frame_unwind, 1028 amd64_frame_base_address, 1029 amd64_frame_base_address, 1030 amd64_frame_base_address 1031}; 1032 1033static struct frame_id 1034amd64_unwind_dummy_id (struct gdbarch *gdbarch, struct frame_info *next_frame) 1035{ 1036 gdb_byte buf[8]; 1037 CORE_ADDR fp; 1038 1039 frame_unwind_register (next_frame, AMD64_RBP_REGNUM, buf); 1040 fp = extract_unsigned_integer (buf, 8); 1041 1042 return frame_id_build (fp + 16, frame_pc_unwind (next_frame)); 1043} 1044 1045/* 16 byte align the SP per frame requirements. */ 1046 1047static CORE_ADDR 1048amd64_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp) 1049{ 1050 return sp & -(CORE_ADDR)16; 1051} 1052 1053 1054/* Supply register REGNUM from the buffer specified by FPREGS and LEN 1055 in the floating-point register set REGSET to register cache 1056 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */ 1057 1058static void 1059amd64_supply_fpregset (const struct regset *regset, struct regcache *regcache, 1060 int regnum, const void *fpregs, size_t len) 1061{ 1062 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 1063 1064 gdb_assert (len == tdep->sizeof_fpregset); 1065 amd64_supply_fxsave (regcache, regnum, fpregs); 1066} 1067 1068/* Collect register REGNUM from the register cache REGCACHE and store 1069 it in the buffer specified by FPREGS and LEN as described by the 1070 floating-point register set REGSET. If REGNUM is -1, do this for 1071 all registers in REGSET. */ 1072 1073static void 1074amd64_collect_fpregset (const struct regset *regset, 1075 const struct regcache *regcache, 1076 int regnum, void *fpregs, size_t len) 1077{ 1078 const struct gdbarch_tdep *tdep = gdbarch_tdep (regset->arch); 1079 1080 gdb_assert (len == tdep->sizeof_fpregset); 1081 amd64_collect_fxsave (regcache, regnum, fpregs); 1082} 1083 1084/* Return the appropriate register set for the core section identified 1085 by SECT_NAME and SECT_SIZE. */ 1086 1087static const struct regset * 1088amd64_regset_from_core_section (struct gdbarch *gdbarch, 1089 const char *sect_name, size_t sect_size) 1090{ 1091 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1092 1093 if (strcmp (sect_name, ".reg2") == 0 && sect_size == tdep->sizeof_fpregset) 1094 { 1095 if (tdep->fpregset == NULL) 1096 tdep->fpregset = regset_alloc (gdbarch, amd64_supply_fpregset, 1097 amd64_collect_fpregset); 1098 1099 return tdep->fpregset; 1100 } 1101 1102 return i386_regset_from_core_section (gdbarch, sect_name, sect_size); 1103} 1104 1105 1106void 1107amd64_init_abi (struct gdbarch_info info, struct gdbarch *gdbarch) 1108{ 1109 struct gdbarch_tdep *tdep = gdbarch_tdep (gdbarch); 1110 1111 /* AMD64 generally uses `fxsave' instead of `fsave' for saving its 1112 floating-point registers. */ 1113 tdep->sizeof_fpregset = I387_SIZEOF_FXSAVE; 1114 1115 /* AMD64 has an FPU and 16 SSE registers. */ 1116 tdep->st0_regnum = AMD64_ST0_REGNUM; 1117 tdep->num_xmm_regs = 16; 1118 1119 /* This is what all the fuss is about. */ 1120 set_gdbarch_long_bit (gdbarch, 64); 1121 set_gdbarch_long_long_bit (gdbarch, 64); 1122 set_gdbarch_ptr_bit (gdbarch, 64); 1123 1124 /* In contrast to the i386, on AMD64 a `long double' actually takes 1125 up 128 bits, even though it's still based on the i387 extended 1126 floating-point format which has only 80 significant bits. */ 1127 set_gdbarch_long_double_bit (gdbarch, 128); 1128 1129 set_gdbarch_num_regs (gdbarch, AMD64_NUM_REGS); 1130 set_gdbarch_register_name (gdbarch, amd64_register_name); 1131 set_gdbarch_register_type (gdbarch, amd64_register_type); 1132 1133 /* Register numbers of various important registers. */ 1134 set_gdbarch_sp_regnum (gdbarch, AMD64_RSP_REGNUM); /* %rsp */ 1135 set_gdbarch_pc_regnum (gdbarch, AMD64_RIP_REGNUM); /* %rip */ 1136 set_gdbarch_ps_regnum (gdbarch, AMD64_EFLAGS_REGNUM); /* %eflags */ 1137 set_gdbarch_fp0_regnum (gdbarch, AMD64_ST0_REGNUM); /* %st(0) */ 1138 1139 /* The "default" register numbering scheme for AMD64 is referred to 1140 as the "DWARF Register Number Mapping" in the System V psABI. 1141 The preferred debugging format for all known AMD64 targets is 1142 actually DWARF2, and GCC doesn't seem to support DWARF (that is 1143 DWARF-1), but we provide the same mapping just in case. This 1144 mapping is also used for stabs, which GCC does support. */ 1145 set_gdbarch_stab_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 1146 set_gdbarch_dwarf_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 1147 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, amd64_dwarf_reg_to_regnum); 1148 1149 /* We don't override SDB_REG_RO_REGNUM, since COFF doesn't seem to 1150 be in use on any of the supported AMD64 targets. */ 1151 1152 /* Call dummy code. */ 1153 set_gdbarch_push_dummy_call (gdbarch, amd64_push_dummy_call); 1154 set_gdbarch_frame_align (gdbarch, amd64_frame_align); 1155 set_gdbarch_frame_red_zone_size (gdbarch, 128); 1156 1157 set_gdbarch_convert_register_p (gdbarch, amd64_convert_register_p); 1158 set_gdbarch_register_to_value (gdbarch, i387_register_to_value); 1159 set_gdbarch_value_to_register (gdbarch, i387_value_to_register); 1160 1161 set_gdbarch_return_value (gdbarch, amd64_return_value); 1162 1163 set_gdbarch_skip_prologue (gdbarch, amd64_skip_prologue); 1164 1165 /* Avoid wiring in the MMX registers for now. */ 1166 set_gdbarch_num_pseudo_regs (gdbarch, 0); 1167 tdep->mm0_regnum = -1; 1168 1169 set_gdbarch_unwind_dummy_id (gdbarch, amd64_unwind_dummy_id); 1170 1171 frame_unwind_append_sniffer (gdbarch, amd64_sigtramp_frame_sniffer); 1172 frame_unwind_append_sniffer (gdbarch, amd64_frame_sniffer); 1173 frame_base_set_default (gdbarch, &amd64_frame_base); 1174 1175 /* If we have a register mapping, enable the generic core file support. */ 1176 if (tdep->gregset_reg_offset) 1177 set_gdbarch_regset_from_core_section (gdbarch, 1178 amd64_regset_from_core_section); 1179} 1180 1181 1182#define I387_ST0_REGNUM AMD64_ST0_REGNUM 1183 1184/* The 64-bit FXSAVE format differs from the 32-bit format in the 1185 sense that the instruction pointer and data pointer are simply 1186 64-bit offsets into the code segment and the data segment instead 1187 of a selector offset pair. The functions below store the upper 32 1188 bits of these pointers (instead of just the 16-bits of the segment 1189 selector). */ 1190 1191/* Fill register REGNUM in REGCACHE with the appropriate 1192 floating-point or SSE register value from *FXSAVE. If REGNUM is 1193 -1, do this for all registers. This function masks off any of the 1194 reserved bits in *FXSAVE. */ 1195 1196void 1197amd64_supply_fxsave (struct regcache *regcache, int regnum, 1198 const void *fxsave) 1199{ 1200 i387_supply_fxsave (regcache, regnum, fxsave); 1201 1202 if (fxsave && gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) 1203 { 1204 const gdb_byte *regs = fxsave; 1205 1206 if (regnum == -1 || regnum == I387_FISEG_REGNUM) 1207 regcache_raw_supply (regcache, I387_FISEG_REGNUM, regs + 12); 1208 if (regnum == -1 || regnum == I387_FOSEG_REGNUM) 1209 regcache_raw_supply (regcache, I387_FOSEG_REGNUM, regs + 20); 1210 } 1211} 1212 1213/* Fill register REGNUM (if it is a floating-point or SSE register) in 1214 *FXSAVE with the value from REGCACHE. If REGNUM is -1, do this for 1215 all registers. This function doesn't touch any of the reserved 1216 bits in *FXSAVE. */ 1217 1218void 1219amd64_collect_fxsave (const struct regcache *regcache, int regnum, 1220 void *fxsave) 1221{ 1222 gdb_byte *regs = fxsave; 1223 1224 i387_collect_fxsave (regcache, regnum, fxsave); 1225 1226 if (gdbarch_ptr_bit (get_regcache_arch (regcache)) == 64) 1227 { 1228 if (regnum == -1 || regnum == I387_FISEG_REGNUM) 1229 regcache_raw_collect (regcache, I387_FISEG_REGNUM, regs + 12); 1230 if (regnum == -1 || regnum == I387_FOSEG_REGNUM) 1231 regcache_raw_collect (regcache, I387_FOSEG_REGNUM, regs + 20); 1232 } 1233} 1234