1/* 2 * ALSA SoC I2S (McBSP) Audio Layer for TI DAVINCI processor 3 * 4 * Author: Vladimir Barinov, <vbarinov@embeddedalley.com> 5 * Copyright: (C) 2007 MontaVista Software, Inc., <source@mvista.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License version 2 as 9 * published by the Free Software Foundation. 10 */ 11 12#include <linux/init.h> 13#include <linux/module.h> 14#include <linux/device.h> 15#include <linux/slab.h> 16#include <linux/delay.h> 17#include <linux/io.h> 18#include <linux/clk.h> 19 20#include <sound/core.h> 21#include <sound/pcm.h> 22#include <sound/pcm_params.h> 23#include <sound/initval.h> 24#include <sound/soc.h> 25 26#include <mach/asp.h> 27 28#include "davinci-pcm.h" 29#include "davinci-i2s.h" 30 31 32/* 33 * NOTE: terminology here is confusing. 34 * 35 * - This driver supports the "Audio Serial Port" (ASP), 36 * found on dm6446, dm355, and other DaVinci chips. 37 * 38 * - But it labels it a "Multi-channel Buffered Serial Port" 39 * (McBSP) as on older chips like the dm642 ... which was 40 * backward-compatible, possibly explaining that confusion. 41 * 42 * - OMAP chips have a controller called McBSP, which is 43 * incompatible with the DaVinci flavor of McBSP. 44 * 45 * - Newer DaVinci chips have a controller called McASP, 46 * incompatible with ASP and with either McBSP. 47 * 48 * In short: this uses ASP to implement I2S, not McBSP. 49 * And it won't be the only DaVinci implemention of I2S. 50 */ 51#define DAVINCI_MCBSP_DRR_REG 0x00 52#define DAVINCI_MCBSP_DXR_REG 0x04 53#define DAVINCI_MCBSP_SPCR_REG 0x08 54#define DAVINCI_MCBSP_RCR_REG 0x0c 55#define DAVINCI_MCBSP_XCR_REG 0x10 56#define DAVINCI_MCBSP_SRGR_REG 0x14 57#define DAVINCI_MCBSP_PCR_REG 0x24 58 59#define DAVINCI_MCBSP_SPCR_RRST (1 << 0) 60#define DAVINCI_MCBSP_SPCR_RINTM(v) ((v) << 4) 61#define DAVINCI_MCBSP_SPCR_XRST (1 << 16) 62#define DAVINCI_MCBSP_SPCR_XINTM(v) ((v) << 20) 63#define DAVINCI_MCBSP_SPCR_GRST (1 << 22) 64#define DAVINCI_MCBSP_SPCR_FRST (1 << 23) 65#define DAVINCI_MCBSP_SPCR_FREE (1 << 25) 66 67#define DAVINCI_MCBSP_RCR_RWDLEN1(v) ((v) << 5) 68#define DAVINCI_MCBSP_RCR_RFRLEN1(v) ((v) << 8) 69#define DAVINCI_MCBSP_RCR_RDATDLY(v) ((v) << 16) 70#define DAVINCI_MCBSP_RCR_RFIG (1 << 18) 71#define DAVINCI_MCBSP_RCR_RWDLEN2(v) ((v) << 21) 72#define DAVINCI_MCBSP_RCR_RFRLEN2(v) ((v) << 24) 73#define DAVINCI_MCBSP_RCR_RPHASE BIT(31) 74 75#define DAVINCI_MCBSP_XCR_XWDLEN1(v) ((v) << 5) 76#define DAVINCI_MCBSP_XCR_XFRLEN1(v) ((v) << 8) 77#define DAVINCI_MCBSP_XCR_XDATDLY(v) ((v) << 16) 78#define DAVINCI_MCBSP_XCR_XFIG (1 << 18) 79#define DAVINCI_MCBSP_XCR_XWDLEN2(v) ((v) << 21) 80#define DAVINCI_MCBSP_XCR_XFRLEN2(v) ((v) << 24) 81#define DAVINCI_MCBSP_XCR_XPHASE BIT(31) 82 83#define DAVINCI_MCBSP_SRGR_FWID(v) ((v) << 8) 84#define DAVINCI_MCBSP_SRGR_FPER(v) ((v) << 16) 85#define DAVINCI_MCBSP_SRGR_FSGM (1 << 28) 86#define DAVINCI_MCBSP_SRGR_CLKSM BIT(29) 87 88#define DAVINCI_MCBSP_PCR_CLKRP (1 << 0) 89#define DAVINCI_MCBSP_PCR_CLKXP (1 << 1) 90#define DAVINCI_MCBSP_PCR_FSRP (1 << 2) 91#define DAVINCI_MCBSP_PCR_FSXP (1 << 3) 92#define DAVINCI_MCBSP_PCR_SCLKME (1 << 7) 93#define DAVINCI_MCBSP_PCR_CLKRM (1 << 8) 94#define DAVINCI_MCBSP_PCR_CLKXM (1 << 9) 95#define DAVINCI_MCBSP_PCR_FSRM (1 << 10) 96#define DAVINCI_MCBSP_PCR_FSXM (1 << 11) 97 98enum { 99 DAVINCI_MCBSP_WORD_8 = 0, 100 DAVINCI_MCBSP_WORD_12, 101 DAVINCI_MCBSP_WORD_16, 102 DAVINCI_MCBSP_WORD_20, 103 DAVINCI_MCBSP_WORD_24, 104 DAVINCI_MCBSP_WORD_32, 105}; 106 107static const unsigned char data_type[SNDRV_PCM_FORMAT_S32_LE + 1] = { 108 [SNDRV_PCM_FORMAT_S8] = 1, 109 [SNDRV_PCM_FORMAT_S16_LE] = 2, 110 [SNDRV_PCM_FORMAT_S32_LE] = 4, 111}; 112 113static const unsigned char asp_word_length[SNDRV_PCM_FORMAT_S32_LE + 1] = { 114 [SNDRV_PCM_FORMAT_S8] = DAVINCI_MCBSP_WORD_8, 115 [SNDRV_PCM_FORMAT_S16_LE] = DAVINCI_MCBSP_WORD_16, 116 [SNDRV_PCM_FORMAT_S32_LE] = DAVINCI_MCBSP_WORD_32, 117}; 118 119static const unsigned char double_fmt[SNDRV_PCM_FORMAT_S32_LE + 1] = { 120 [SNDRV_PCM_FORMAT_S8] = SNDRV_PCM_FORMAT_S16_LE, 121 [SNDRV_PCM_FORMAT_S16_LE] = SNDRV_PCM_FORMAT_S32_LE, 122}; 123 124struct davinci_mcbsp_dev { 125 struct device *dev; 126 struct davinci_pcm_dma_params dma_params[2]; 127 void __iomem *base; 128#define MOD_DSP_A 0 129#define MOD_DSP_B 1 130 int mode; 131 u32 pcr; 132 struct clk *clk; 133 /* 134 * Combining both channels into 1 element will at least double the 135 * amount of time between servicing the dma channel, increase 136 * effiency, and reduce the chance of overrun/underrun. But, 137 * it will result in the left & right channels being swapped. 138 * 139 * If relabeling the left and right channels is not possible, 140 * you may want to let the codec know to swap them back. 141 * 142 * It may allow x10 the amount of time to service dma requests, 143 * if the codec is master and is using an unnecessarily fast bit clock 144 * (ie. tlvaic23b), independent of the sample rate. So, having an 145 * entire frame at once means it can be serviced at the sample rate 146 * instead of the bit clock rate. 147 * 148 * In the now unlikely case that an underrun still 149 * occurs, both the left and right samples will be repeated 150 * so that no pops are heard, and the left and right channels 151 * won't end up being swapped because of the underrun. 152 */ 153 unsigned enable_channel_combine:1; 154 155 unsigned int fmt; 156 int clk_div; 157 int clk_input_pin; 158 bool i2s_accurate_sck; 159}; 160 161static inline void davinci_mcbsp_write_reg(struct davinci_mcbsp_dev *dev, 162 int reg, u32 val) 163{ 164 __raw_writel(val, dev->base + reg); 165} 166 167static inline u32 davinci_mcbsp_read_reg(struct davinci_mcbsp_dev *dev, int reg) 168{ 169 return __raw_readl(dev->base + reg); 170} 171 172static void toggle_clock(struct davinci_mcbsp_dev *dev, int playback) 173{ 174 u32 m = playback ? DAVINCI_MCBSP_PCR_CLKXP : DAVINCI_MCBSP_PCR_CLKRP; 175 /* The clock needs to toggle to complete reset. 176 * So, fake it by toggling the clk polarity. 177 */ 178 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr ^ m); 179 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, dev->pcr); 180} 181 182static void davinci_mcbsp_start(struct davinci_mcbsp_dev *dev, 183 struct snd_pcm_substream *substream) 184{ 185 struct snd_soc_pcm_runtime *rtd = substream->private_data; 186 struct snd_soc_device *socdev = rtd->socdev; 187 struct snd_soc_platform *platform = socdev->card->platform; 188 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 189 u32 spcr; 190 u32 mask = playback ? DAVINCI_MCBSP_SPCR_XRST : DAVINCI_MCBSP_SPCR_RRST; 191 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); 192 if (spcr & mask) { 193 /* start off disabled */ 194 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, 195 spcr & ~mask); 196 toggle_clock(dev, playback); 197 } 198 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM | 199 DAVINCI_MCBSP_PCR_CLKXM | DAVINCI_MCBSP_PCR_CLKRM)) { 200 /* Start the sample generator */ 201 spcr |= DAVINCI_MCBSP_SPCR_GRST; 202 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); 203 } 204 205 if (playback) { 206 /* Stop the DMA to avoid data loss */ 207 /* while the transmitter is out of reset to handle XSYNCERR */ 208 if (platform->pcm_ops->trigger) { 209 int ret = platform->pcm_ops->trigger(substream, 210 SNDRV_PCM_TRIGGER_STOP); 211 if (ret < 0) 212 printk(KERN_DEBUG "Playback DMA stop failed\n"); 213 } 214 215 /* Enable the transmitter */ 216 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); 217 spcr |= DAVINCI_MCBSP_SPCR_XRST; 218 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); 219 220 /* wait for any unexpected frame sync error to occur */ 221 udelay(100); 222 223 /* Disable the transmitter to clear any outstanding XSYNCERR */ 224 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); 225 spcr &= ~DAVINCI_MCBSP_SPCR_XRST; 226 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); 227 toggle_clock(dev, playback); 228 229 /* Restart the DMA */ 230 if (platform->pcm_ops->trigger) { 231 int ret = platform->pcm_ops->trigger(substream, 232 SNDRV_PCM_TRIGGER_START); 233 if (ret < 0) 234 printk(KERN_DEBUG "Playback DMA start failed\n"); 235 } 236 } 237 238 /* Enable transmitter or receiver */ 239 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); 240 spcr |= mask; 241 242 if (dev->pcr & (DAVINCI_MCBSP_PCR_FSXM | DAVINCI_MCBSP_PCR_FSRM)) { 243 /* Start frame sync */ 244 spcr |= DAVINCI_MCBSP_SPCR_FRST; 245 } 246 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); 247} 248 249static void davinci_mcbsp_stop(struct davinci_mcbsp_dev *dev, int playback) 250{ 251 u32 spcr; 252 253 /* Reset transmitter/receiver and sample rate/frame sync generators */ 254 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); 255 spcr &= ~(DAVINCI_MCBSP_SPCR_GRST | DAVINCI_MCBSP_SPCR_FRST); 256 spcr &= playback ? ~DAVINCI_MCBSP_SPCR_XRST : ~DAVINCI_MCBSP_SPCR_RRST; 257 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); 258 toggle_clock(dev, playback); 259} 260 261#define DEFAULT_BITPERSAMPLE 16 262 263static int davinci_i2s_set_dai_fmt(struct snd_soc_dai *cpu_dai, 264 unsigned int fmt) 265{ 266 struct davinci_mcbsp_dev *dev = cpu_dai->private_data; 267 unsigned int pcr; 268 unsigned int srgr; 269 /* Attention srgr is updated by hw_params! */ 270 srgr = DAVINCI_MCBSP_SRGR_FSGM | 271 DAVINCI_MCBSP_SRGR_FPER(DEFAULT_BITPERSAMPLE * 2 - 1) | 272 DAVINCI_MCBSP_SRGR_FWID(DEFAULT_BITPERSAMPLE - 1); 273 274 dev->fmt = fmt; 275 /* set master/slave audio interface */ 276 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) { 277 case SND_SOC_DAIFMT_CBS_CFS: 278 /* cpu is master */ 279 pcr = DAVINCI_MCBSP_PCR_FSXM | 280 DAVINCI_MCBSP_PCR_FSRM | 281 DAVINCI_MCBSP_PCR_CLKXM | 282 DAVINCI_MCBSP_PCR_CLKRM; 283 break; 284 case SND_SOC_DAIFMT_CBM_CFS: 285 pcr = DAVINCI_MCBSP_PCR_FSRM | DAVINCI_MCBSP_PCR_FSXM; 286 /* 287 * Selection of the clock input pin that is the 288 * input for the Sample Rate Generator. 289 * McBSP FSR and FSX are driven by the Sample Rate 290 * Generator. 291 */ 292 switch (dev->clk_input_pin) { 293 case MCBSP_CLKS: 294 pcr |= DAVINCI_MCBSP_PCR_CLKXM | 295 DAVINCI_MCBSP_PCR_CLKRM; 296 break; 297 case MCBSP_CLKR: 298 pcr |= DAVINCI_MCBSP_PCR_SCLKME; 299 break; 300 default: 301 dev_err(dev->dev, "bad clk_input_pin\n"); 302 return -EINVAL; 303 } 304 305 break; 306 case SND_SOC_DAIFMT_CBM_CFM: 307 /* codec is master */ 308 pcr = 0; 309 break; 310 default: 311 printk(KERN_ERR "%s:bad master\n", __func__); 312 return -EINVAL; 313 } 314 315 /* interface format */ 316 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) { 317 case SND_SOC_DAIFMT_I2S: 318 /* Davinci doesn't support TRUE I2S, but some codecs will have 319 * the left and right channels contiguous. This allows 320 * dsp_a mode to be used with an inverted normal frame clk. 321 * If your codec is master and does not have contiguous 322 * channels, then you will have sound on only one channel. 323 * Try using a different mode, or codec as slave. 324 * 325 * The TLV320AIC33 is an example of a codec where this works. 326 * It has a variable bit clock frequency allowing it to have 327 * valid data on every bit clock. 328 * 329 * The TLV320AIC23 is an example of a codec where this does not 330 * work. It has a fixed bit clock frequency with progressively 331 * more empty bit clock slots between channels as the sample 332 * rate is lowered. 333 */ 334 fmt ^= SND_SOC_DAIFMT_NB_IF; 335 case SND_SOC_DAIFMT_DSP_A: 336 dev->mode = MOD_DSP_A; 337 break; 338 case SND_SOC_DAIFMT_DSP_B: 339 dev->mode = MOD_DSP_B; 340 break; 341 default: 342 printk(KERN_ERR "%s:bad format\n", __func__); 343 return -EINVAL; 344 } 345 346 switch (fmt & SND_SOC_DAIFMT_INV_MASK) { 347 case SND_SOC_DAIFMT_NB_NF: 348 /* CLKRP Receive clock polarity, 349 * 1 - sampled on rising edge of CLKR 350 * valid on rising edge 351 * CLKXP Transmit clock polarity, 352 * 1 - clocked on falling edge of CLKX 353 * valid on rising edge 354 * FSRP Receive frame sync pol, 0 - active high 355 * FSXP Transmit frame sync pol, 0 - active high 356 */ 357 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP); 358 break; 359 case SND_SOC_DAIFMT_IB_IF: 360 /* CLKRP Receive clock polarity, 361 * 0 - sampled on falling edge of CLKR 362 * valid on falling edge 363 * CLKXP Transmit clock polarity, 364 * 0 - clocked on rising edge of CLKX 365 * valid on falling edge 366 * FSRP Receive frame sync pol, 1 - active low 367 * FSXP Transmit frame sync pol, 1 - active low 368 */ 369 pcr |= (DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); 370 break; 371 case SND_SOC_DAIFMT_NB_IF: 372 /* CLKRP Receive clock polarity, 373 * 1 - sampled on rising edge of CLKR 374 * valid on rising edge 375 * CLKXP Transmit clock polarity, 376 * 1 - clocked on falling edge of CLKX 377 * valid on rising edge 378 * FSRP Receive frame sync pol, 1 - active low 379 * FSXP Transmit frame sync pol, 1 - active low 380 */ 381 pcr |= (DAVINCI_MCBSP_PCR_CLKXP | DAVINCI_MCBSP_PCR_CLKRP | 382 DAVINCI_MCBSP_PCR_FSXP | DAVINCI_MCBSP_PCR_FSRP); 383 break; 384 case SND_SOC_DAIFMT_IB_NF: 385 /* CLKRP Receive clock polarity, 386 * 0 - sampled on falling edge of CLKR 387 * valid on falling edge 388 * CLKXP Transmit clock polarity, 389 * 0 - clocked on rising edge of CLKX 390 * valid on falling edge 391 * FSRP Receive frame sync pol, 0 - active high 392 * FSXP Transmit frame sync pol, 0 - active high 393 */ 394 break; 395 default: 396 return -EINVAL; 397 } 398 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); 399 dev->pcr = pcr; 400 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_PCR_REG, pcr); 401 return 0; 402} 403 404static int davinci_i2s_dai_set_clkdiv(struct snd_soc_dai *cpu_dai, 405 int div_id, int div) 406{ 407 struct davinci_mcbsp_dev *dev = cpu_dai->private_data; 408 409 if (div_id != DAVINCI_MCBSP_CLKGDV) 410 return -ENODEV; 411 412 dev->clk_div = div; 413 return 0; 414} 415 416static int davinci_i2s_hw_params(struct snd_pcm_substream *substream, 417 struct snd_pcm_hw_params *params, 418 struct snd_soc_dai *dai) 419{ 420 struct davinci_mcbsp_dev *dev = dai->private_data; 421 struct davinci_pcm_dma_params *dma_params = 422 &dev->dma_params[substream->stream]; 423 struct snd_interval *i = NULL; 424 int mcbsp_word_length, master; 425 unsigned int rcr, xcr, srgr, clk_div, freq, framesize; 426 u32 spcr; 427 snd_pcm_format_t fmt; 428 unsigned element_cnt = 1; 429 430 /* general line settings */ 431 spcr = davinci_mcbsp_read_reg(dev, DAVINCI_MCBSP_SPCR_REG); 432 if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) { 433 spcr |= DAVINCI_MCBSP_SPCR_RINTM(3) | DAVINCI_MCBSP_SPCR_FREE; 434 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); 435 } else { 436 spcr |= DAVINCI_MCBSP_SPCR_XINTM(3) | DAVINCI_MCBSP_SPCR_FREE; 437 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SPCR_REG, spcr); 438 } 439 440 master = dev->fmt & SND_SOC_DAIFMT_MASTER_MASK; 441 fmt = params_format(params); 442 mcbsp_word_length = asp_word_length[fmt]; 443 444 switch (master) { 445 case SND_SOC_DAIFMT_CBS_CFS: 446 freq = clk_get_rate(dev->clk); 447 srgr = DAVINCI_MCBSP_SRGR_FSGM | 448 DAVINCI_MCBSP_SRGR_CLKSM; 449 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 450 8 - 1); 451 if (dev->i2s_accurate_sck) { 452 clk_div = 256; 453 do { 454 framesize = (freq / (--clk_div)) / 455 params->rate_num * 456 params->rate_den; 457 } while (((framesize < 33) || (framesize > 4095)) && 458 (clk_div)); 459 clk_div--; 460 srgr |= DAVINCI_MCBSP_SRGR_FPER(framesize - 1); 461 } else { 462 /* symmetric waveforms */ 463 clk_div = freq / (mcbsp_word_length * 16) / 464 params->rate_num * params->rate_den; 465 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 466 16 - 1); 467 } 468 clk_div &= 0xFF; 469 srgr |= clk_div; 470 break; 471 case SND_SOC_DAIFMT_CBM_CFS: 472 srgr = DAVINCI_MCBSP_SRGR_FSGM; 473 clk_div = dev->clk_div - 1; 474 srgr |= DAVINCI_MCBSP_SRGR_FWID(mcbsp_word_length * 8 - 1); 475 srgr |= DAVINCI_MCBSP_SRGR_FPER(mcbsp_word_length * 16 - 1); 476 clk_div &= 0xFF; 477 srgr |= clk_div; 478 break; 479 case SND_SOC_DAIFMT_CBM_CFM: 480 /* Clock and frame sync given from external sources */ 481 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_SAMPLE_BITS); 482 srgr = DAVINCI_MCBSP_SRGR_FSGM; 483 srgr |= DAVINCI_MCBSP_SRGR_FWID(snd_interval_value(i) - 1); 484 pr_debug("%s - %d FWID set: re-read srgr = %X\n", 485 __func__, __LINE__, snd_interval_value(i) - 1); 486 487 i = hw_param_interval(params, SNDRV_PCM_HW_PARAM_FRAME_BITS); 488 srgr |= DAVINCI_MCBSP_SRGR_FPER(snd_interval_value(i) - 1); 489 break; 490 default: 491 return -EINVAL; 492 } 493 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_SRGR_REG, srgr); 494 495 rcr = DAVINCI_MCBSP_RCR_RFIG; 496 xcr = DAVINCI_MCBSP_XCR_XFIG; 497 if (dev->mode == MOD_DSP_B) { 498 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(0); 499 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(0); 500 } else { 501 rcr |= DAVINCI_MCBSP_RCR_RDATDLY(1); 502 xcr |= DAVINCI_MCBSP_XCR_XDATDLY(1); 503 } 504 /* Determine xfer data type */ 505 fmt = params_format(params); 506 if ((fmt > SNDRV_PCM_FORMAT_S32_LE) || !data_type[fmt]) { 507 printk(KERN_WARNING "davinci-i2s: unsupported PCM format\n"); 508 return -EINVAL; 509 } 510 511 if (params_channels(params) == 2) { 512 element_cnt = 2; 513 if (double_fmt[fmt] && dev->enable_channel_combine) { 514 element_cnt = 1; 515 fmt = double_fmt[fmt]; 516 } 517 switch (master) { 518 case SND_SOC_DAIFMT_CBS_CFS: 519 case SND_SOC_DAIFMT_CBS_CFM: 520 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(0); 521 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(0); 522 rcr |= DAVINCI_MCBSP_RCR_RPHASE; 523 xcr |= DAVINCI_MCBSP_XCR_XPHASE; 524 break; 525 case SND_SOC_DAIFMT_CBM_CFM: 526 case SND_SOC_DAIFMT_CBM_CFS: 527 rcr |= DAVINCI_MCBSP_RCR_RFRLEN2(element_cnt - 1); 528 xcr |= DAVINCI_MCBSP_XCR_XFRLEN2(element_cnt - 1); 529 break; 530 default: 531 return -EINVAL; 532 } 533 } 534 dma_params->acnt = dma_params->data_type = data_type[fmt]; 535 dma_params->fifo_level = 0; 536 mcbsp_word_length = asp_word_length[fmt]; 537 538 switch (master) { 539 case SND_SOC_DAIFMT_CBS_CFS: 540 case SND_SOC_DAIFMT_CBS_CFM: 541 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(0); 542 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(0); 543 break; 544 case SND_SOC_DAIFMT_CBM_CFM: 545 case SND_SOC_DAIFMT_CBM_CFS: 546 rcr |= DAVINCI_MCBSP_RCR_RFRLEN1(element_cnt - 1); 547 xcr |= DAVINCI_MCBSP_XCR_XFRLEN1(element_cnt - 1); 548 break; 549 default: 550 return -EINVAL; 551 } 552 553 rcr |= DAVINCI_MCBSP_RCR_RWDLEN1(mcbsp_word_length) | 554 DAVINCI_MCBSP_RCR_RWDLEN2(mcbsp_word_length); 555 xcr |= DAVINCI_MCBSP_XCR_XWDLEN1(mcbsp_word_length) | 556 DAVINCI_MCBSP_XCR_XWDLEN2(mcbsp_word_length); 557 558 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) 559 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_XCR_REG, xcr); 560 else 561 davinci_mcbsp_write_reg(dev, DAVINCI_MCBSP_RCR_REG, rcr); 562 563 pr_debug("%s - %d srgr=%X\n", __func__, __LINE__, srgr); 564 pr_debug("%s - %d xcr=%X\n", __func__, __LINE__, xcr); 565 pr_debug("%s - %d rcr=%X\n", __func__, __LINE__, rcr); 566 return 0; 567} 568 569static int davinci_i2s_prepare(struct snd_pcm_substream *substream, 570 struct snd_soc_dai *dai) 571{ 572 struct davinci_mcbsp_dev *dev = dai->private_data; 573 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 574 davinci_mcbsp_stop(dev, playback); 575 if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) { 576 /* codec is master */ 577 davinci_mcbsp_start(dev, substream); 578 } 579 return 0; 580} 581 582static int davinci_i2s_trigger(struct snd_pcm_substream *substream, int cmd, 583 struct snd_soc_dai *dai) 584{ 585 struct davinci_mcbsp_dev *dev = dai->private_data; 586 int ret = 0; 587 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 588 if ((dev->pcr & DAVINCI_MCBSP_PCR_FSXM) == 0) 589 return 0; /* return if codec is master */ 590 591 switch (cmd) { 592 case SNDRV_PCM_TRIGGER_START: 593 case SNDRV_PCM_TRIGGER_RESUME: 594 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE: 595 davinci_mcbsp_start(dev, substream); 596 break; 597 case SNDRV_PCM_TRIGGER_STOP: 598 case SNDRV_PCM_TRIGGER_SUSPEND: 599 case SNDRV_PCM_TRIGGER_PAUSE_PUSH: 600 davinci_mcbsp_stop(dev, playback); 601 break; 602 default: 603 ret = -EINVAL; 604 } 605 return ret; 606} 607 608static void davinci_i2s_shutdown(struct snd_pcm_substream *substream, 609 struct snd_soc_dai *dai) 610{ 611 struct davinci_mcbsp_dev *dev = dai->private_data; 612 int playback = (substream->stream == SNDRV_PCM_STREAM_PLAYBACK); 613 davinci_mcbsp_stop(dev, playback); 614} 615 616#define DAVINCI_I2S_RATES SNDRV_PCM_RATE_8000_96000 617 618static struct snd_soc_dai_ops davinci_i2s_dai_ops = { 619 .shutdown = davinci_i2s_shutdown, 620 .prepare = davinci_i2s_prepare, 621 .trigger = davinci_i2s_trigger, 622 .hw_params = davinci_i2s_hw_params, 623 .set_fmt = davinci_i2s_set_dai_fmt, 624 .set_clkdiv = davinci_i2s_dai_set_clkdiv, 625 626}; 627 628struct snd_soc_dai davinci_i2s_dai = { 629 .name = "davinci-i2s", 630 .id = 0, 631 .playback = { 632 .channels_min = 2, 633 .channels_max = 2, 634 .rates = DAVINCI_I2S_RATES, 635 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 636 .capture = { 637 .channels_min = 2, 638 .channels_max = 2, 639 .rates = DAVINCI_I2S_RATES, 640 .formats = SNDRV_PCM_FMTBIT_S16_LE,}, 641 .ops = &davinci_i2s_dai_ops, 642 643}; 644EXPORT_SYMBOL_GPL(davinci_i2s_dai); 645 646static int davinci_i2s_probe(struct platform_device *pdev) 647{ 648 struct snd_platform_data *pdata = pdev->dev.platform_data; 649 struct davinci_mcbsp_dev *dev; 650 struct resource *mem, *ioarea, *res; 651 enum dma_event_q asp_chan_q = EVENTQ_0; 652 enum dma_event_q ram_chan_q = EVENTQ_1; 653 int ret; 654 655 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 656 if (!mem) { 657 dev_err(&pdev->dev, "no mem resource?\n"); 658 return -ENODEV; 659 } 660 661 ioarea = request_mem_region(mem->start, (mem->end - mem->start) + 1, 662 pdev->name); 663 if (!ioarea) { 664 dev_err(&pdev->dev, "McBSP region already claimed\n"); 665 return -EBUSY; 666 } 667 668 dev = kzalloc(sizeof(struct davinci_mcbsp_dev), GFP_KERNEL); 669 if (!dev) { 670 ret = -ENOMEM; 671 goto err_release_region; 672 } 673 if (pdata) { 674 dev->enable_channel_combine = pdata->enable_channel_combine; 675 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].sram_size = 676 pdata->sram_size_playback; 677 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].sram_size = 678 pdata->sram_size_capture; 679 dev->clk_input_pin = pdata->clk_input_pin; 680 dev->i2s_accurate_sck = pdata->i2s_accurate_sck; 681 asp_chan_q = pdata->asp_chan_q; 682 ram_chan_q = pdata->ram_chan_q; 683 } 684 685 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].asp_chan_q = asp_chan_q; 686 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].ram_chan_q = ram_chan_q; 687 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].asp_chan_q = asp_chan_q; 688 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].ram_chan_q = ram_chan_q; 689 690 dev->clk = clk_get(&pdev->dev, NULL); 691 if (IS_ERR(dev->clk)) { 692 ret = -ENODEV; 693 goto err_free_mem; 694 } 695 clk_enable(dev->clk); 696 697 dev->base = (void __iomem *)IO_ADDRESS(mem->start); 698 699 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].dma_addr = 700 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DXR_REG); 701 702 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].dma_addr = 703 (dma_addr_t)(io_v2p(dev->base) + DAVINCI_MCBSP_DRR_REG); 704 705 /* first TX, then RX */ 706 res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 707 if (!res) { 708 dev_err(&pdev->dev, "no DMA resource\n"); 709 ret = -ENXIO; 710 goto err_free_mem; 711 } 712 dev->dma_params[SNDRV_PCM_STREAM_PLAYBACK].channel = res->start; 713 714 res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 715 if (!res) { 716 dev_err(&pdev->dev, "no DMA resource\n"); 717 ret = -ENXIO; 718 goto err_free_mem; 719 } 720 dev->dma_params[SNDRV_PCM_STREAM_CAPTURE].channel = res->start; 721 dev->dev = &pdev->dev; 722 723 davinci_i2s_dai.private_data = dev; 724 davinci_i2s_dai.capture.dma_data = dev->dma_params; 725 davinci_i2s_dai.playback.dma_data = dev->dma_params; 726 ret = snd_soc_register_dai(&davinci_i2s_dai); 727 if (ret != 0) 728 goto err_free_mem; 729 730 return 0; 731 732err_free_mem: 733 kfree(dev); 734err_release_region: 735 release_mem_region(mem->start, (mem->end - mem->start) + 1); 736 737 return ret; 738} 739 740static int davinci_i2s_remove(struct platform_device *pdev) 741{ 742 struct davinci_mcbsp_dev *dev = davinci_i2s_dai.private_data; 743 struct resource *mem; 744 745 snd_soc_unregister_dai(&davinci_i2s_dai); 746 clk_disable(dev->clk); 747 clk_put(dev->clk); 748 dev->clk = NULL; 749 kfree(dev); 750 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 751 release_mem_region(mem->start, (mem->end - mem->start) + 1); 752 753 return 0; 754} 755 756static struct platform_driver davinci_mcbsp_driver = { 757 .probe = davinci_i2s_probe, 758 .remove = davinci_i2s_remove, 759 .driver = { 760 .name = "davinci-asp", 761 .owner = THIS_MODULE, 762 }, 763}; 764 765static int __init davinci_i2s_init(void) 766{ 767 return platform_driver_register(&davinci_mcbsp_driver); 768} 769module_init(davinci_i2s_init); 770 771static void __exit davinci_i2s_exit(void) 772{ 773 platform_driver_unregister(&davinci_mcbsp_driver); 774} 775module_exit(davinci_i2s_exit); 776 777MODULE_AUTHOR("Vladimir Barinov"); 778MODULE_DESCRIPTION("TI DAVINCI I2S (McBSP) SoC Interface"); 779MODULE_LICENSE("GPL"); 780