1/******************************************************************************* 2* 3* "swarm_cs4297a.c" -- Cirrus Logic-Crystal CS4297a linux audio driver. 4* 5* Copyright (C) 2001 Broadcom Corporation. 6* Copyright (C) 2000,2001 Cirrus Logic Corp. 7* -- adapted from drivers by Thomas Sailer, 8* -- but don't bug him; Problems should go to: 9* -- tom woller (twoller@crystal.cirrus.com) or 10* (audio@crystal.cirrus.com). 11* -- adapted from cs4281 PCI driver for cs4297a on 12* BCM1250 Synchronous Serial interface 13* (Kip Walker, Broadcom Corp.) 14* Copyright (C) 2004 Maciej W. Rozycki 15* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org) 16* 17* This program is free software; you can redistribute it and/or modify 18* it under the terms of the GNU General Public License as published by 19* the Free Software Foundation; either version 2 of the License, or 20* (at your option) any later version. 21* 22* This program is distributed in the hope that it will be useful, 23* but WITHOUT ANY WARRANTY; without even the implied warranty of 24* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25* GNU General Public License for more details. 26* 27* You should have received a copy of the GNU General Public License 28* along with this program; if not, write to the Free Software 29* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 30* 31* Module command line parameters: 32* none 33* 34* Supported devices: 35* /dev/dsp standard /dev/dsp device, (mostly) OSS compatible 36* /dev/mixer standard /dev/mixer device, (mostly) OSS compatible 37* /dev/midi simple MIDI UART interface, no ioctl 38* 39* Modification History 40* 08/20/00 trw - silence and no stopping DAC until release 41* 08/23/00 trw - added CS_DBG statements, fix interrupt hang issue on DAC stop. 42* 09/18/00 trw - added 16bit only record with conversion 43* 09/24/00 trw - added Enhanced Full duplex (separate simultaneous 44* capture/playback rates) 45* 10/03/00 trw - fixed mmap (fixed GRECORD and the XMMS mmap test plugin 46* libOSSm.so) 47* 10/11/00 trw - modified for 2.4.0-test9 kernel enhancements (NR_MAP removal) 48* 11/03/00 trw - fixed interrupt loss/stutter, added debug. 49* 11/10/00 bkz - added __devinit to cs4297a_hw_init() 50* 11/10/00 trw - fixed SMP and capture spinlock hang. 51* 12/04/00 trw - cleaned up CSDEBUG flags and added "defaultorder" moduleparm. 52* 12/05/00 trw - fixed polling (myth2), and added underrun swptr fix. 53* 12/08/00 trw - added PM support. 54* 12/14/00 trw - added wrapper code, builds under 2.4.0, 2.2.17-20, 2.2.17-8 55* (RH/Dell base), 2.2.18, 2.2.12. cleaned up code mods by ident. 56* 12/19/00 trw - added PM support for 2.2 base (apm_callback). other PM cleanup. 57* 12/21/00 trw - added fractional "defaultorder" inputs. if >100 then use 58* defaultorder-100 as power of 2 for the buffer size. example: 59* 106 = 2^(106-100) = 2^6 = 64 bytes for the buffer size. 60* 61*******************************************************************************/ 62 63#include <linux/list.h> 64#include <linux/module.h> 65#include <linux/string.h> 66#include <linux/ioport.h> 67#include <linux/sched.h> 68#include <linux/delay.h> 69#include <linux/sound.h> 70#include <linux/slab.h> 71#include <linux/smp_lock.h> 72#include <linux/soundcard.h> 73#include <linux/ac97_codec.h> 74#include <linux/pci.h> 75#include <linux/bitops.h> 76#include <linux/interrupt.h> 77#include <linux/init.h> 78#include <linux/poll.h> 79#include <linux/mutex.h> 80#include <linux/kernel.h> 81 82#include <asm/byteorder.h> 83#include <asm/dma.h> 84#include <asm/io.h> 85#include <asm/uaccess.h> 86 87#include <asm/sibyte/sb1250_regs.h> 88#include <asm/sibyte/sb1250_int.h> 89#include <asm/sibyte/sb1250_dma.h> 90#include <asm/sibyte/sb1250_scd.h> 91#include <asm/sibyte/sb1250_syncser.h> 92#include <asm/sibyte/sb1250_mac.h> 93#include <asm/sibyte/sb1250.h> 94 95struct cs4297a_state; 96 97static void stop_dac(struct cs4297a_state *s); 98static void stop_adc(struct cs4297a_state *s); 99static void start_dac(struct cs4297a_state *s); 100static void start_adc(struct cs4297a_state *s); 101#undef OSS_DOCUMENTED_MIXER_SEMANTICS 102 103// --------------------------------------------------------------------- 104 105#define CS4297a_MAGIC 0xf00beef1 106 107// buffer order determines the size of the dma buffer for the driver. 108// under Linux, a smaller buffer allows more responsiveness from many of the 109// applications (e.g. games). A larger buffer allows some of the apps (esound) 110// to not underrun the dma buffer as easily. As default, use 32k (order=3) 111// rather than 64k as some of the games work more responsively. 112// log base 2( buff sz = 32k). 113 114// 115// Turn on/off debugging compilation by commenting out "#define CSDEBUG" 116// 117#define CSDEBUG 0 118#if CSDEBUG 119#define CSDEBUG_INTERFACE 1 120#else 121#undef CSDEBUG_INTERFACE 122#endif 123// 124// cs_debugmask areas 125// 126#define CS_INIT 0x00000001 // initialization and probe functions 127#define CS_ERROR 0x00000002 // tmp debugging bit placeholder 128#define CS_INTERRUPT 0x00000004 // interrupt handler (separate from all other) 129#define CS_FUNCTION 0x00000008 // enter/leave functions 130#define CS_WAVE_WRITE 0x00000010 // write information for wave 131#define CS_WAVE_READ 0x00000020 // read information for wave 132#define CS_AC97 0x00000040 // AC97 register access 133#define CS_DESCR 0x00000080 // descriptor management 134#define CS_OPEN 0x00000400 // all open functions in the driver 135#define CS_RELEASE 0x00000800 // all release functions in the driver 136#define CS_PARMS 0x00001000 // functional and operational parameters 137#define CS_IOCTL 0x00002000 // ioctl (non-mixer) 138#define CS_TMP 0x10000000 // tmp debug mask bit 139 140// 141// CSDEBUG is usual mode is set to 1, then use the 142// cs_debuglevel and cs_debugmask to turn on or off debugging. 143// Debug level of 1 has been defined to be kernel errors and info 144// that should be printed on any released driver. 145// 146#if CSDEBUG 147#define CS_DBGOUT(mask,level,x) if((cs_debuglevel >= (level)) && ((mask) & cs_debugmask) ) {x;} 148#else 149#define CS_DBGOUT(mask,level,x) 150#endif 151 152#if CSDEBUG 153static unsigned long cs_debuglevel = 4; // levels range from 1-9 154static unsigned long cs_debugmask = CS_INIT /*| CS_IOCTL*/; 155module_param(cs_debuglevel, int, 0); 156module_param(cs_debugmask, int, 0); 157#endif 158#define CS_TRUE 1 159#define CS_FALSE 0 160 161#define CS_TYPE_ADC 0 162#define CS_TYPE_DAC 1 163 164#define SER_BASE (A_SER_BASE_1 + KSEG1) 165#define SS_CSR(t) (SER_BASE+t) 166#define SS_TXTBL(t) (SER_BASE+R_SER_TX_TABLE_BASE+(t*8)) 167#define SS_RXTBL(t) (SER_BASE+R_SER_RX_TABLE_BASE+(t*8)) 168 169#define FRAME_BYTES 32 170#define FRAME_SAMPLE_BYTES 4 171 172/* Should this be variable? */ 173#define SAMPLE_BUF_SIZE (16*1024) 174#define SAMPLE_FRAME_COUNT (SAMPLE_BUF_SIZE / FRAME_SAMPLE_BYTES) 175/* The driver can explode/shrink the frames to/from a smaller sample 176 buffer */ 177#define DMA_BLOAT_FACTOR 1 178#define DMA_DESCR (SAMPLE_FRAME_COUNT / DMA_BLOAT_FACTOR) 179#define DMA_BUF_SIZE (DMA_DESCR * FRAME_BYTES) 180 181/* Use the maxmium count (255 == 5.1 ms between interrupts) */ 182#define DMA_INT_CNT ((1 << S_DMA_INT_PKTCNT) - 1) 183 184/* Figure this out: how many TX DMAs ahead to schedule a reg access */ 185#define REG_LATENCY 150 186 187#define FRAME_TX_US 20 188 189#define SERDMA_NEXTBUF(d,f) (((d)->f+1) % (d)->ringsz) 190 191static const char invalid_magic[] = 192 KERN_CRIT "cs4297a: invalid magic value\n"; 193 194#define VALIDATE_STATE(s) \ 195({ \ 196 if (!(s) || (s)->magic != CS4297a_MAGIC) { \ 197 printk(invalid_magic); \ 198 return -ENXIO; \ 199 } \ 200}) 201 202struct list_head cs4297a_devs = { &cs4297a_devs, &cs4297a_devs }; 203 204typedef struct serdma_descr_s { 205 u64 descr_a; 206 u64 descr_b; 207} serdma_descr_t; 208 209typedef unsigned long paddr_t; 210 211typedef struct serdma_s { 212 unsigned ringsz; 213 serdma_descr_t *descrtab; 214 serdma_descr_t *descrtab_end; 215 paddr_t descrtab_phys; 216 217 serdma_descr_t *descr_add; 218 serdma_descr_t *descr_rem; 219 220 u64 *dma_buf; // buffer for DMA contents (frames) 221 paddr_t dma_buf_phys; 222 u16 *sample_buf; // tmp buffer for sample conversions 223 u16 *sb_swptr; 224 u16 *sb_hwptr; 225 u16 *sb_end; 226 227 dma_addr_t dmaaddr; 228// unsigned buforder; // Log base 2 of 'dma_buf' size in bytes.. 229 unsigned numfrag; // # of 'fragments' in the buffer. 230 unsigned fragshift; // Log base 2 of fragment size. 231 unsigned hwptr, swptr; 232 unsigned total_bytes; // # bytes process since open. 233 unsigned blocks; // last returned blocks value GETOPTR 234 unsigned wakeup; // interrupt occurred on block 235 int count; 236 unsigned underrun; // underrun flag 237 unsigned error; // over/underrun 238 wait_queue_head_t wait; 239 wait_queue_head_t reg_wait; 240 // redundant, but makes calculations easier 241 unsigned fragsize; // 2**fragshift.. 242 unsigned sbufsz; // 2**buforder. 243 unsigned fragsamples; 244 // OSS stuff 245 unsigned mapped:1; // Buffer mapped in cs4297a_mmap()? 246 unsigned ready:1; // prog_dmabuf_dac()/adc() successful? 247 unsigned endcleared:1; 248 unsigned type:1; // adc or dac buffer (CS_TYPE_XXX) 249 unsigned ossfragshift; 250 int ossmaxfrags; 251 unsigned subdivision; 252} serdma_t; 253 254struct cs4297a_state { 255 // magic 256 unsigned int magic; 257 258 struct list_head list; 259 260 // soundcore stuff 261 int dev_audio; 262 int dev_mixer; 263 264 // hardware resources 265 unsigned int irq; 266 267 struct { 268 unsigned int rx_ovrrn; /* FIFO */ 269 unsigned int rx_overflow; /* staging buffer */ 270 unsigned int tx_underrun; 271 unsigned int rx_bad; 272 unsigned int rx_good; 273 } stats; 274 275 // mixer registers 276 struct { 277 unsigned short vol[10]; 278 unsigned int recsrc; 279 unsigned int modcnt; 280 unsigned short micpreamp; 281 } mix; 282 283 // wave stuff 284 struct properties { 285 unsigned fmt; 286 unsigned fmt_original; // original requested format 287 unsigned channels; 288 unsigned rate; 289 } prop_dac, prop_adc; 290 unsigned conversion:1; // conversion from 16 to 8 bit in progress 291 unsigned ena; 292 spinlock_t lock; 293 struct mutex open_mutex; 294 struct mutex open_sem_adc; 295 struct mutex open_sem_dac; 296 fmode_t open_mode; 297 wait_queue_head_t open_wait; 298 wait_queue_head_t open_wait_adc; 299 wait_queue_head_t open_wait_dac; 300 301 dma_addr_t dmaaddr_sample_buf; 302 unsigned buforder_sample_buf; // Log base 2 of 'dma_buf' size in bytes.. 303 304 serdma_t dma_dac, dma_adc; 305 306 volatile u16 read_value; 307 volatile u16 read_reg; 308 volatile u64 reg_request; 309}; 310 311#define prog_codec(a,b) 312#define dealloc_dmabuf(a,b); 313 314static int prog_dmabuf_adc(struct cs4297a_state *s) 315{ 316 s->dma_adc.ready = 1; 317 return 0; 318} 319 320 321static int prog_dmabuf_dac(struct cs4297a_state *s) 322{ 323 s->dma_dac.ready = 1; 324 return 0; 325} 326 327static void clear_advance(void *buf, unsigned bsize, unsigned bptr, 328 unsigned len, unsigned char c) 329{ 330 if (bptr + len > bsize) { 331 unsigned x = bsize - bptr; 332 memset(((char *) buf) + bptr, c, x); 333 bptr = 0; 334 len -= x; 335 } 336 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO 337 "cs4297a: clear_advance(): memset %d at 0x%.8x for %d size \n", 338 (unsigned)c, (unsigned)((char *) buf) + bptr, len)); 339 memset(((char *) buf) + bptr, c, len); 340} 341 342#if CSDEBUG 343 344// DEBUG ROUTINES 345 346#define SOUND_MIXER_CS_GETDBGLEVEL _SIOWR('M',120, int) 347#define SOUND_MIXER_CS_SETDBGLEVEL _SIOWR('M',121, int) 348#define SOUND_MIXER_CS_GETDBGMASK _SIOWR('M',122, int) 349#define SOUND_MIXER_CS_SETDBGMASK _SIOWR('M',123, int) 350 351static void cs_printioctl(unsigned int x) 352{ 353 unsigned int i; 354 unsigned char vidx; 355 // Index of mixtable1[] member is Device ID 356 // and must be <= SOUND_MIXER_NRDEVICES. 357 // Value of array member is index into s->mix.vol[] 358 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = { 359 [SOUND_MIXER_PCM] = 1, // voice 360 [SOUND_MIXER_LINE1] = 2, // AUX 361 [SOUND_MIXER_CD] = 3, // CD 362 [SOUND_MIXER_LINE] = 4, // Line 363 [SOUND_MIXER_SYNTH] = 5, // FM 364 [SOUND_MIXER_MIC] = 6, // Mic 365 [SOUND_MIXER_SPEAKER] = 7, // Speaker 366 [SOUND_MIXER_RECLEV] = 8, // Recording level 367 [SOUND_MIXER_VOLUME] = 9 // Master Volume 368 }; 369 370 switch (x) { 371 case SOUND_MIXER_CS_GETDBGMASK: 372 CS_DBGOUT(CS_IOCTL, 4, 373 printk("SOUND_MIXER_CS_GETDBGMASK:\n")); 374 break; 375 case SOUND_MIXER_CS_GETDBGLEVEL: 376 CS_DBGOUT(CS_IOCTL, 4, 377 printk("SOUND_MIXER_CS_GETDBGLEVEL:\n")); 378 break; 379 case SOUND_MIXER_CS_SETDBGMASK: 380 CS_DBGOUT(CS_IOCTL, 4, 381 printk("SOUND_MIXER_CS_SETDBGMASK:\n")); 382 break; 383 case SOUND_MIXER_CS_SETDBGLEVEL: 384 CS_DBGOUT(CS_IOCTL, 4, 385 printk("SOUND_MIXER_CS_SETDBGLEVEL:\n")); 386 break; 387 case OSS_GETVERSION: 388 CS_DBGOUT(CS_IOCTL, 4, printk("OSS_GETVERSION:\n")); 389 break; 390 case SNDCTL_DSP_SYNC: 391 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SYNC:\n")); 392 break; 393 case SNDCTL_DSP_SETDUPLEX: 394 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETDUPLEX:\n")); 395 break; 396 case SNDCTL_DSP_GETCAPS: 397 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETCAPS:\n")); 398 break; 399 case SNDCTL_DSP_RESET: 400 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_RESET:\n")); 401 break; 402 case SNDCTL_DSP_SPEED: 403 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SPEED:\n")); 404 break; 405 case SNDCTL_DSP_STEREO: 406 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_STEREO:\n")); 407 break; 408 case SNDCTL_DSP_CHANNELS: 409 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_CHANNELS:\n")); 410 break; 411 case SNDCTL_DSP_GETFMTS: 412 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETFMTS:\n")); 413 break; 414 case SNDCTL_DSP_SETFMT: 415 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETFMT:\n")); 416 break; 417 case SNDCTL_DSP_POST: 418 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_POST:\n")); 419 break; 420 case SNDCTL_DSP_GETTRIGGER: 421 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETTRIGGER:\n")); 422 break; 423 case SNDCTL_DSP_SETTRIGGER: 424 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETTRIGGER:\n")); 425 break; 426 case SNDCTL_DSP_GETOSPACE: 427 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOSPACE:\n")); 428 break; 429 case SNDCTL_DSP_GETISPACE: 430 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETISPACE:\n")); 431 break; 432 case SNDCTL_DSP_NONBLOCK: 433 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_NONBLOCK:\n")); 434 break; 435 case SNDCTL_DSP_GETODELAY: 436 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETODELAY:\n")); 437 break; 438 case SNDCTL_DSP_GETIPTR: 439 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETIPTR:\n")); 440 break; 441 case SNDCTL_DSP_GETOPTR: 442 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETOPTR:\n")); 443 break; 444 case SNDCTL_DSP_GETBLKSIZE: 445 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_GETBLKSIZE:\n")); 446 break; 447 case SNDCTL_DSP_SETFRAGMENT: 448 CS_DBGOUT(CS_IOCTL, 4, 449 printk("SNDCTL_DSP_SETFRAGMENT:\n")); 450 break; 451 case SNDCTL_DSP_SUBDIVIDE: 452 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SUBDIVIDE:\n")); 453 break; 454 case SOUND_PCM_READ_RATE: 455 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_RATE:\n")); 456 break; 457 case SOUND_PCM_READ_CHANNELS: 458 CS_DBGOUT(CS_IOCTL, 4, 459 printk("SOUND_PCM_READ_CHANNELS:\n")); 460 break; 461 case SOUND_PCM_READ_BITS: 462 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_BITS:\n")); 463 break; 464 case SOUND_PCM_WRITE_FILTER: 465 CS_DBGOUT(CS_IOCTL, 4, 466 printk("SOUND_PCM_WRITE_FILTER:\n")); 467 break; 468 case SNDCTL_DSP_SETSYNCRO: 469 CS_DBGOUT(CS_IOCTL, 4, printk("SNDCTL_DSP_SETSYNCRO:\n")); 470 break; 471 case SOUND_PCM_READ_FILTER: 472 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_PCM_READ_FILTER:\n")); 473 break; 474 case SOUND_MIXER_PRIVATE1: 475 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE1:\n")); 476 break; 477 case SOUND_MIXER_PRIVATE2: 478 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE2:\n")); 479 break; 480 case SOUND_MIXER_PRIVATE3: 481 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE3:\n")); 482 break; 483 case SOUND_MIXER_PRIVATE4: 484 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE4:\n")); 485 break; 486 case SOUND_MIXER_PRIVATE5: 487 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_PRIVATE5:\n")); 488 break; 489 case SOUND_MIXER_INFO: 490 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_INFO:\n")); 491 break; 492 case SOUND_OLD_MIXER_INFO: 493 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_OLD_MIXER_INFO:\n")); 494 break; 495 496 default: 497 switch (_IOC_NR(x)) { 498 case SOUND_MIXER_VOLUME: 499 CS_DBGOUT(CS_IOCTL, 4, 500 printk("SOUND_MIXER_VOLUME:\n")); 501 break; 502 case SOUND_MIXER_SPEAKER: 503 CS_DBGOUT(CS_IOCTL, 4, 504 printk("SOUND_MIXER_SPEAKER:\n")); 505 break; 506 case SOUND_MIXER_RECLEV: 507 CS_DBGOUT(CS_IOCTL, 4, 508 printk("SOUND_MIXER_RECLEV:\n")); 509 break; 510 case SOUND_MIXER_MIC: 511 CS_DBGOUT(CS_IOCTL, 4, 512 printk("SOUND_MIXER_MIC:\n")); 513 break; 514 case SOUND_MIXER_SYNTH: 515 CS_DBGOUT(CS_IOCTL, 4, 516 printk("SOUND_MIXER_SYNTH:\n")); 517 break; 518 case SOUND_MIXER_RECSRC: 519 CS_DBGOUT(CS_IOCTL, 4, 520 printk("SOUND_MIXER_RECSRC:\n")); 521 break; 522 case SOUND_MIXER_DEVMASK: 523 CS_DBGOUT(CS_IOCTL, 4, 524 printk("SOUND_MIXER_DEVMASK:\n")); 525 break; 526 case SOUND_MIXER_RECMASK: 527 CS_DBGOUT(CS_IOCTL, 4, 528 printk("SOUND_MIXER_RECMASK:\n")); 529 break; 530 case SOUND_MIXER_STEREODEVS: 531 CS_DBGOUT(CS_IOCTL, 4, 532 printk("SOUND_MIXER_STEREODEVS:\n")); 533 break; 534 case SOUND_MIXER_CAPS: 535 CS_DBGOUT(CS_IOCTL, 4, printk("SOUND_MIXER_CAPS:\n")); 536 break; 537 default: 538 i = _IOC_NR(x); 539 if (i >= SOUND_MIXER_NRDEVICES 540 || !(vidx = mixtable1[i])) { 541 CS_DBGOUT(CS_IOCTL, 4, printk 542 ("UNKNOWN IOCTL: 0x%.8x NR=%d\n", 543 x, i)); 544 } else { 545 CS_DBGOUT(CS_IOCTL, 4, printk 546 ("SOUND_MIXER_IOCTL AC9x: 0x%.8x NR=%d\n", 547 x, i)); 548 } 549 break; 550 } 551 } 552} 553#endif 554 555 556static int ser_init(struct cs4297a_state *s) 557{ 558 int i; 559 560 CS_DBGOUT(CS_INIT, 2, 561 printk(KERN_INFO "cs4297a: Setting up serial parameters\n")); 562 563 __raw_writeq(M_SYNCSER_CMD_RX_RESET | M_SYNCSER_CMD_TX_RESET, SS_CSR(R_SER_CMD)); 564 565 __raw_writeq(M_SYNCSER_MSB_FIRST, SS_CSR(R_SER_MODE)); 566 __raw_writeq(32, SS_CSR(R_SER_MINFRM_SZ)); 567 __raw_writeq(32, SS_CSR(R_SER_MAXFRM_SZ)); 568 569 __raw_writeq(1, SS_CSR(R_SER_TX_RD_THRSH)); 570 __raw_writeq(4, SS_CSR(R_SER_TX_WR_THRSH)); 571 __raw_writeq(8, SS_CSR(R_SER_RX_RD_THRSH)); 572 573 /* This looks good from experimentation */ 574 __raw_writeq((M_SYNCSER_TXSYNC_INT | V_SYNCSER_TXSYNC_DLY(0) | M_SYNCSER_TXCLK_EXT | 575 M_SYNCSER_RXSYNC_INT | V_SYNCSER_RXSYNC_DLY(1) | M_SYNCSER_RXCLK_EXT | M_SYNCSER_RXSYNC_EDGE), 576 SS_CSR(R_SER_LINE_MODE)); 577 578 /* This looks good from experimentation */ 579 __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE, 580 SS_TXTBL(0)); 581 __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, 582 SS_TXTBL(1)); 583 __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, 584 SS_TXTBL(2)); 585 __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | 586 M_SYNCSER_SEQ_STROBE | M_SYNCSER_SEQ_LAST, SS_TXTBL(3)); 587 588 __raw_writeq(V_SYNCSER_SEQ_COUNT(14) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE, 589 SS_RXTBL(0)); 590 __raw_writeq(V_SYNCSER_SEQ_COUNT(15) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, 591 SS_RXTBL(1)); 592 __raw_writeq(V_SYNCSER_SEQ_COUNT(13) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_BYTE, 593 SS_RXTBL(2)); 594 __raw_writeq(V_SYNCSER_SEQ_COUNT( 0) | M_SYNCSER_SEQ_ENABLE | M_SYNCSER_SEQ_STROBE | 595 M_SYNCSER_SEQ_LAST, SS_RXTBL(3)); 596 597 for (i=4; i<16; i++) { 598 /* Just in case... */ 599 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_TXTBL(i)); 600 __raw_writeq(M_SYNCSER_SEQ_LAST, SS_RXTBL(i)); 601 } 602 603 return 0; 604} 605 606static int init_serdma(serdma_t *dma) 607{ 608 CS_DBGOUT(CS_INIT, 2, 609 printk(KERN_ERR "cs4297a: desc - %d sbufsize - %d dbufsize - %d\n", 610 DMA_DESCR, SAMPLE_BUF_SIZE, DMA_BUF_SIZE)); 611 612 /* Descriptors */ 613 dma->ringsz = DMA_DESCR; 614 dma->descrtab = kzalloc(dma->ringsz * sizeof(serdma_descr_t), GFP_KERNEL); 615 if (!dma->descrtab) { 616 printk(KERN_ERR "cs4297a: kzalloc descrtab failed\n"); 617 return -1; 618 } 619 dma->descrtab_end = dma->descrtab + dma->ringsz; 620 dma->descrtab_phys = CPHYSADDR((long)dma->descrtab); 621 dma->descr_add = dma->descr_rem = dma->descrtab; 622 623 /* Frame buffer area */ 624 dma->dma_buf = kzalloc(DMA_BUF_SIZE, GFP_KERNEL); 625 if (!dma->dma_buf) { 626 printk(KERN_ERR "cs4297a: kzalloc dma_buf failed\n"); 627 kfree(dma->descrtab); 628 return -1; 629 } 630 dma->dma_buf_phys = CPHYSADDR((long)dma->dma_buf); 631 632 /* Samples buffer area */ 633 dma->sbufsz = SAMPLE_BUF_SIZE; 634 dma->sample_buf = kmalloc(dma->sbufsz, GFP_KERNEL); 635 if (!dma->sample_buf) { 636 printk(KERN_ERR "cs4297a: kmalloc sample_buf failed\n"); 637 kfree(dma->descrtab); 638 kfree(dma->dma_buf); 639 return -1; 640 } 641 dma->sb_swptr = dma->sb_hwptr = dma->sample_buf; 642 dma->sb_end = (u16 *)((void *)dma->sample_buf + dma->sbufsz); 643 dma->fragsize = dma->sbufsz >> 1; 644 645 CS_DBGOUT(CS_INIT, 4, 646 printk(KERN_ERR "cs4297a: descrtab - %08x dma_buf - %x sample_buf - %x\n", 647 (int)dma->descrtab, (int)dma->dma_buf, 648 (int)dma->sample_buf)); 649 650 return 0; 651} 652 653static int dma_init(struct cs4297a_state *s) 654{ 655 int i; 656 657 CS_DBGOUT(CS_INIT, 2, 658 printk(KERN_INFO "cs4297a: Setting up DMA\n")); 659 660 if (init_serdma(&s->dma_adc) || 661 init_serdma(&s->dma_dac)) 662 return -1; 663 664 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))|| 665 __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) { 666 panic("DMA state corrupted?!"); 667 } 668 669 /* Initialize now - the descr/buffer pairings will never 670 change... */ 671 for (i=0; i<DMA_DESCR; i++) { 672 s->dma_dac.descrtab[i].descr_a = M_DMA_SERRX_SOP | V_DMA_DSCRA_A_SIZE(1) | 673 (s->dma_dac.dma_buf_phys + i*FRAME_BYTES); 674 s->dma_dac.descrtab[i].descr_b = V_DMA_DSCRB_PKT_SIZE(FRAME_BYTES); 675 s->dma_adc.descrtab[i].descr_a = V_DMA_DSCRA_A_SIZE(1) | 676 (s->dma_adc.dma_buf_phys + i*FRAME_BYTES); 677 s->dma_adc.descrtab[i].descr_b = 0; 678 } 679 680 __raw_writeq((M_DMA_EOP_INT_EN | V_DMA_INT_PKTCNT(DMA_INT_CNT) | 681 V_DMA_RINGSZ(DMA_DESCR) | M_DMA_TDX_EN), 682 SS_CSR(R_SER_DMA_CONFIG0_RX)); 683 __raw_writeq(M_DMA_L2CA, SS_CSR(R_SER_DMA_CONFIG1_RX)); 684 __raw_writeq(s->dma_adc.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_RX)); 685 686 __raw_writeq(V_DMA_RINGSZ(DMA_DESCR), SS_CSR(R_SER_DMA_CONFIG0_TX)); 687 __raw_writeq(M_DMA_L2CA | M_DMA_NO_DSCR_UPDT, SS_CSR(R_SER_DMA_CONFIG1_TX)); 688 __raw_writeq(s->dma_dac.descrtab_phys, SS_CSR(R_SER_DMA_DSCR_BASE_TX)); 689 690 /* Prep the receive DMA descriptor ring */ 691 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); 692 693 __raw_writeq(M_SYNCSER_DMA_RX_EN | M_SYNCSER_DMA_TX_EN, SS_CSR(R_SER_DMA_ENABLE)); 694 695 __raw_writeq((M_SYNCSER_RX_SYNC_ERR | M_SYNCSER_RX_OVERRUN | M_SYNCSER_RX_EOP_COUNT), 696 SS_CSR(R_SER_INT_MASK)); 697 698 /* Enable the rx/tx; let the codec warm up to the sync and 699 start sending good frames before the receive FIFO is 700 enabled */ 701 __raw_writeq(M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD)); 702 udelay(1000); 703 __raw_writeq(M_SYNCSER_CMD_RX_EN | M_SYNCSER_CMD_TX_EN, SS_CSR(R_SER_CMD)); 704 705 /* XXXKW is this magic? (the "1" part) */ 706 while ((__raw_readq(SS_CSR(R_SER_STATUS)) & 0xf1) != 1) 707 ; 708 709 CS_DBGOUT(CS_INIT, 4, 710 printk(KERN_INFO "cs4297a: status: %08x\n", 711 (unsigned int)(__raw_readq(SS_CSR(R_SER_STATUS)) & 0xffffffff))); 712 713 return 0; 714} 715 716static int serdma_reg_access(struct cs4297a_state *s, u64 data) 717{ 718 serdma_t *d = &s->dma_dac; 719 u64 *data_p; 720 unsigned swptr; 721 unsigned long flags; 722 serdma_descr_t *descr; 723 724 if (s->reg_request) { 725 printk(KERN_ERR "cs4297a: attempt to issue multiple reg_access\n"); 726 return -1; 727 } 728 729 if (s->ena & FMODE_WRITE) { 730 /* Since a writer has the DSP open, we have to mux the 731 request in */ 732 s->reg_request = data; 733 interruptible_sleep_on(&s->dma_dac.reg_wait); 734 /* XXXKW how can I deal with the starvation case where 735 the opener isn't writing? */ 736 } else { 737 /* Be safe when changing ring pointers */ 738 spin_lock_irqsave(&s->lock, flags); 739 if (d->hwptr != d->swptr) { 740 printk(KERN_ERR "cs4297a: reg access found bookkeeping error (hw/sw = %d/%d\n", 741 d->hwptr, d->swptr); 742 spin_unlock_irqrestore(&s->lock, flags); 743 return -1; 744 } 745 swptr = d->swptr; 746 d->hwptr = d->swptr = (d->swptr + 1) % d->ringsz; 747 spin_unlock_irqrestore(&s->lock, flags); 748 749 descr = &d->descrtab[swptr]; 750 data_p = &d->dma_buf[swptr * 4]; 751 *data_p = cpu_to_be64(data); 752 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_TX)); 753 CS_DBGOUT(CS_DESCR, 4, 754 printk(KERN_INFO "cs4297a: add_tx %p (%x -> %x)\n", 755 data_p, swptr, d->hwptr)); 756 } 757 758 CS_DBGOUT(CS_FUNCTION, 6, 759 printk(KERN_INFO "cs4297a: serdma_reg_access()-\n")); 760 761 return 0; 762} 763 764//**************************************************************************** 765// "cs4297a_read_ac97" -- Reads an AC97 register 766//**************************************************************************** 767static int cs4297a_read_ac97(struct cs4297a_state *s, u32 offset, 768 u32 * value) 769{ 770 CS_DBGOUT(CS_AC97, 1, 771 printk(KERN_INFO "cs4297a: read reg %2x\n", offset)); 772 if (serdma_reg_access(s, (0xCLL << 60) | (1LL << 47) | ((u64)(offset & 0x7F) << 40))) 773 return -1; 774 775 interruptible_sleep_on(&s->dma_adc.reg_wait); 776 *value = s->read_value; 777 CS_DBGOUT(CS_AC97, 2, 778 printk(KERN_INFO "cs4297a: rdr reg %x -> %x\n", s->read_reg, s->read_value)); 779 780 return 0; 781} 782 783 784//**************************************************************************** 785// "cs4297a_write_ac97()"-- writes an AC97 register 786//**************************************************************************** 787static int cs4297a_write_ac97(struct cs4297a_state *s, u32 offset, 788 u32 value) 789{ 790 CS_DBGOUT(CS_AC97, 1, 791 printk(KERN_INFO "cs4297a: write reg %2x -> %04x\n", offset, value)); 792 return (serdma_reg_access(s, (0xELL << 60) | ((u64)(offset & 0x7F) << 40) | ((value & 0xffff) << 12))); 793} 794 795static void stop_dac(struct cs4297a_state *s) 796{ 797 unsigned long flags; 798 799 CS_DBGOUT(CS_WAVE_WRITE, 3, printk(KERN_INFO "cs4297a: stop_dac():\n")); 800 spin_lock_irqsave(&s->lock, flags); 801 s->ena &= ~FMODE_WRITE; 802 803 spin_unlock_irqrestore(&s->lock, flags); 804} 805 806 807static void start_dac(struct cs4297a_state *s) 808{ 809 unsigned long flags; 810 811 CS_DBGOUT(CS_FUNCTION, 3, printk(KERN_INFO "cs4297a: start_dac()+\n")); 812 spin_lock_irqsave(&s->lock, flags); 813 if (!(s->ena & FMODE_WRITE) && (s->dma_dac.mapped || 814 (s->dma_dac.count > 0 815 && s->dma_dac.ready))) { 816 s->ena |= FMODE_WRITE; 817 /* XXXKW what do I really want here? My theory for 818 now is that I just flip the "ena" bit, and the 819 interrupt handler will start processing the xmit 820 channel */ 821 822 CS_DBGOUT(CS_WAVE_WRITE | CS_PARMS, 8, printk(KERN_INFO 823 "cs4297a: start_dac(): start dma\n")); 824 825 } 826 spin_unlock_irqrestore(&s->lock, flags); 827 CS_DBGOUT(CS_FUNCTION, 3, 828 printk(KERN_INFO "cs4297a: start_dac()-\n")); 829} 830 831 832static void stop_adc(struct cs4297a_state *s) 833{ 834 unsigned long flags; 835 836 CS_DBGOUT(CS_FUNCTION, 3, 837 printk(KERN_INFO "cs4297a: stop_adc()+\n")); 838 839 spin_lock_irqsave(&s->lock, flags); 840 s->ena &= ~FMODE_READ; 841 842 if (s->conversion == 1) { 843 s->conversion = 0; 844 s->prop_adc.fmt = s->prop_adc.fmt_original; 845 } 846 /* Nothing to do really, I need to keep the DMA going 847 XXXKW when do I get here, and is there more I should do? */ 848 spin_unlock_irqrestore(&s->lock, flags); 849 CS_DBGOUT(CS_FUNCTION, 3, 850 printk(KERN_INFO "cs4297a: stop_adc()-\n")); 851} 852 853 854static void start_adc(struct cs4297a_state *s) 855{ 856 unsigned long flags; 857 858 CS_DBGOUT(CS_FUNCTION, 2, 859 printk(KERN_INFO "cs4297a: start_adc()+\n")); 860 861 if (!(s->ena & FMODE_READ) && 862 (s->dma_adc.mapped || s->dma_adc.count <= 863 (signed) (s->dma_adc.sbufsz - 2 * s->dma_adc.fragsize)) 864 && s->dma_adc.ready) { 865 if (s->prop_adc.fmt & AFMT_S8 || s->prop_adc.fmt & AFMT_U8) { 866 // 867 // now only use 16 bit capture, due to truncation issue 868 // in the chip, noticable distortion occurs. 869 // allocate buffer and then convert from 16 bit to 870 // 8 bit for the user buffer. 871 // 872 s->prop_adc.fmt_original = s->prop_adc.fmt; 873 if (s->prop_adc.fmt & AFMT_S8) { 874 s->prop_adc.fmt &= ~AFMT_S8; 875 s->prop_adc.fmt |= AFMT_S16_LE; 876 } 877 if (s->prop_adc.fmt & AFMT_U8) { 878 s->prop_adc.fmt &= ~AFMT_U8; 879 s->prop_adc.fmt |= AFMT_U16_LE; 880 } 881 // 882 // prog_dmabuf_adc performs a stop_adc() but that is 883 // ok since we really haven't started the DMA yet. 884 // 885 prog_codec(s, CS_TYPE_ADC); 886 887 prog_dmabuf_adc(s); 888 s->conversion = 1; 889 } 890 spin_lock_irqsave(&s->lock, flags); 891 s->ena |= FMODE_READ; 892 /* Nothing to do really, I am probably already 893 DMAing... XXXKW when do I get here, and is there 894 more I should do? */ 895 spin_unlock_irqrestore(&s->lock, flags); 896 897 CS_DBGOUT(CS_PARMS, 6, printk(KERN_INFO 898 "cs4297a: start_adc(): start adc\n")); 899 } 900 CS_DBGOUT(CS_FUNCTION, 2, 901 printk(KERN_INFO "cs4297a: start_adc()-\n")); 902 903} 904 905 906// call with spinlock held! 907static void cs4297a_update_ptr(struct cs4297a_state *s, int intflag) 908{ 909 int good_diff, diff, diff2; 910 u64 *data_p, data; 911 u32 *s_ptr; 912 unsigned hwptr; 913 u32 status; 914 serdma_t *d; 915 serdma_descr_t *descr; 916 917 // update ADC pointer 918 status = intflag ? __raw_readq(SS_CSR(R_SER_STATUS)) : 0; 919 920 if ((s->ena & FMODE_READ) || (status & (M_SYNCSER_RX_EOP_COUNT))) { 921 d = &s->dma_adc; 922 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - 923 d->descrtab_phys) / sizeof(serdma_descr_t)); 924 925 if (s->ena & FMODE_READ) { 926 CS_DBGOUT(CS_FUNCTION, 2, 927 printk(KERN_INFO "cs4297a: upd_rcv sw->hw->hw %x/%x/%x (int-%d)n", 928 d->swptr, d->hwptr, hwptr, intflag)); 929 /* Number of DMA buffers available for software: */ 930 diff2 = diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz; 931 d->hwptr = hwptr; 932 good_diff = 0; 933 s_ptr = (u32 *)&(d->dma_buf[d->swptr*4]); 934 descr = &d->descrtab[d->swptr]; 935 while (diff2--) { 936 u64 data = be64_to_cpu(*(u64 *)s_ptr); 937 u64 descr_a; 938 u16 left, right; 939 descr_a = descr->descr_a; 940 descr->descr_a &= ~M_DMA_SERRX_SOP; 941 if ((descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)s_ptr)) { 942 printk(KERN_ERR "cs4297a: RX Bad address (read)\n"); 943 } 944 if (((data & 0x9800000000000000) != 0x9800000000000000) || 945 (!(descr_a & M_DMA_SERRX_SOP)) || 946 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) { 947 s->stats.rx_bad++; 948 printk(KERN_DEBUG "cs4297a: RX Bad attributes (read)\n"); 949 continue; 950 } 951 s->stats.rx_good++; 952 if ((data >> 61) == 7) { 953 s->read_value = (data >> 12) & 0xffff; 954 s->read_reg = (data >> 40) & 0x7f; 955 wake_up(&d->reg_wait); 956 } 957 if (d->count && (d->sb_hwptr == d->sb_swptr)) { 958 s->stats.rx_overflow++; 959 printk(KERN_DEBUG "cs4297a: RX overflow\n"); 960 continue; 961 } 962 good_diff++; 963 left = ((be32_to_cpu(s_ptr[1]) & 0xff) << 8) | 964 ((be32_to_cpu(s_ptr[2]) >> 24) & 0xff); 965 right = (be32_to_cpu(s_ptr[2]) >> 4) & 0xffff; 966 *d->sb_hwptr++ = cpu_to_be16(left); 967 *d->sb_hwptr++ = cpu_to_be16(right); 968 if (d->sb_hwptr == d->sb_end) 969 d->sb_hwptr = d->sample_buf; 970 descr++; 971 if (descr == d->descrtab_end) { 972 descr = d->descrtab; 973 s_ptr = (u32 *)s->dma_adc.dma_buf; 974 } else { 975 s_ptr += 8; 976 } 977 } 978 d->total_bytes += good_diff * FRAME_SAMPLE_BYTES; 979 d->count += good_diff * FRAME_SAMPLE_BYTES; 980 if (d->count > d->sbufsz) { 981 printk(KERN_ERR "cs4297a: bogus receive overflow!!\n"); 982 } 983 d->swptr = (d->swptr + diff) % d->ringsz; 984 __raw_writeq(diff, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); 985 if (d->mapped) { 986 if (d->count >= (signed) d->fragsize) 987 wake_up(&d->wait); 988 } else { 989 if (d->count > 0) { 990 CS_DBGOUT(CS_WAVE_READ, 4, 991 printk(KERN_INFO 992 "cs4297a: update count -> %d\n", d->count)); 993 wake_up(&d->wait); 994 } 995 } 996 } else { 997 /* Receive is going even if no one is 998 listening (for register accesses and to 999 avoid FIFO overrun) */ 1000 diff2 = diff = (hwptr + d->ringsz - d->hwptr) % d->ringsz; 1001 if (!diff) { 1002 printk(KERN_ERR "cs4297a: RX full or empty?\n"); 1003 } 1004 1005 descr = &d->descrtab[d->swptr]; 1006 data_p = &d->dma_buf[d->swptr*4]; 1007 1008 /* Force this to happen at least once; I got 1009 here because of an interrupt, so there must 1010 be a buffer to process. */ 1011 do { 1012 data = be64_to_cpu(*data_p); 1013 if ((descr->descr_a & M_DMA_DSCRA_A_ADDR) != CPHYSADDR((long)data_p)) { 1014 printk(KERN_ERR "cs4297a: RX Bad address %d (%llx %lx)\n", d->swptr, 1015 (long long)(descr->descr_a & M_DMA_DSCRA_A_ADDR), 1016 (long)CPHYSADDR((long)data_p)); 1017 } 1018 if (!(data & (1LL << 63)) || 1019 !(descr->descr_a & M_DMA_SERRX_SOP) || 1020 (G_DMA_DSCRB_PKT_SIZE(descr->descr_b) != FRAME_BYTES)) { 1021 s->stats.rx_bad++; 1022 printk(KERN_DEBUG "cs4297a: RX Bad attributes\n"); 1023 } else { 1024 s->stats.rx_good++; 1025 if ((data >> 61) == 7) { 1026 s->read_value = (data >> 12) & 0xffff; 1027 s->read_reg = (data >> 40) & 0x7f; 1028 wake_up(&d->reg_wait); 1029 } 1030 } 1031 descr->descr_a &= ~M_DMA_SERRX_SOP; 1032 descr++; 1033 d->swptr++; 1034 data_p += 4; 1035 if (descr == d->descrtab_end) { 1036 descr = d->descrtab; 1037 d->swptr = 0; 1038 data_p = d->dma_buf; 1039 } 1040 __raw_writeq(1, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); 1041 } while (--diff); 1042 d->hwptr = hwptr; 1043 1044 CS_DBGOUT(CS_DESCR, 6, 1045 printk(KERN_INFO "cs4297a: hw/sw %x/%x\n", d->hwptr, d->swptr)); 1046 } 1047 1048 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO 1049 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n", 1050 (unsigned)s, d->hwptr, 1051 d->total_bytes, d->count)); 1052 } 1053 1054 /* XXXKW worry about s->reg_request -- there is a starvation 1055 case if s->ena has FMODE_WRITE on, but the client isn't 1056 doing writes */ 1057 1058 // update DAC pointer 1059 // 1060 // check for end of buffer, means that we are going to wait for another interrupt 1061 // to allow silence to fill the fifos on the part, to keep pops down to a minimum. 1062 // 1063 if (s->ena & FMODE_WRITE) { 1064 serdma_t *d = &s->dma_dac; 1065 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - 1066 d->descrtab_phys) / sizeof(serdma_descr_t)); 1067 diff = (d->ringsz + hwptr - d->hwptr) % d->ringsz; 1068 CS_DBGOUT(CS_WAVE_WRITE, 4, printk(KERN_INFO 1069 "cs4297a: cs4297a_update_ptr(): hw/hw/sw %x/%x/%x diff %d count %d\n", 1070 d->hwptr, hwptr, d->swptr, diff, d->count)); 1071 d->hwptr = hwptr; 1072 /* XXXKW stereo? conversion? Just assume 2 16-bit samples for now */ 1073 d->total_bytes += diff * FRAME_SAMPLE_BYTES; 1074 if (d->mapped) { 1075 d->count += diff * FRAME_SAMPLE_BYTES; 1076 if (d->count >= d->fragsize) { 1077 d->wakeup = 1; 1078 wake_up(&d->wait); 1079 if (d->count > d->sbufsz) 1080 d->count &= d->sbufsz - 1; 1081 } 1082 } else { 1083 d->count -= diff * FRAME_SAMPLE_BYTES; 1084 if (d->count <= 0) { 1085 // 1086 // fill with silence, and do not shut down the DAC. 1087 // Continue to play silence until the _release. 1088 // 1089 CS_DBGOUT(CS_WAVE_WRITE, 6, printk(KERN_INFO 1090 "cs4297a: cs4297a_update_ptr(): memset %d at 0x%.8x for %d size \n", 1091 (unsigned)(s->prop_dac.fmt & 1092 (AFMT_U8 | AFMT_U16_LE)) ? 0x80 : 0, 1093 (unsigned)d->dma_buf, 1094 d->ringsz)); 1095 memset(d->dma_buf, 0, d->ringsz * FRAME_BYTES); 1096 if (d->count < 0) { 1097 d->underrun = 1; 1098 s->stats.tx_underrun++; 1099 d->count = 0; 1100 CS_DBGOUT(CS_ERROR, 9, printk(KERN_INFO 1101 "cs4297a: cs4297a_update_ptr(): underrun\n")); 1102 } 1103 } else if (d->count <= 1104 (signed) d->fragsize 1105 && !d->endcleared) { 1106 /* XXXKW what is this for? */ 1107 clear_advance(d->dma_buf, 1108 d->sbufsz, 1109 d->swptr, 1110 d->fragsize, 1111 0); 1112 d->endcleared = 1; 1113 } 1114 if ( (d->count <= (signed) d->sbufsz/2) || intflag) 1115 { 1116 CS_DBGOUT(CS_WAVE_WRITE, 4, 1117 printk(KERN_INFO 1118 "cs4297a: update count -> %d\n", d->count)); 1119 wake_up(&d->wait); 1120 } 1121 } 1122 CS_DBGOUT(CS_PARMS, 8, printk(KERN_INFO 1123 "cs4297a: cs4297a_update_ptr(): s=0x%.8x hwptr=%d total_bytes=%d count=%d \n", 1124 (unsigned) s, d->hwptr, 1125 d->total_bytes, d->count)); 1126 } 1127} 1128 1129static int mixer_ioctl(struct cs4297a_state *s, unsigned int cmd, 1130 unsigned long arg) 1131{ 1132 // Index to mixer_src[] is value of AC97 Input Mux Select Reg. 1133 // Value of array member is recording source Device ID Mask. 1134 static const unsigned int mixer_src[8] = { 1135 SOUND_MASK_MIC, SOUND_MASK_CD, 0, SOUND_MASK_LINE1, 1136 SOUND_MASK_LINE, SOUND_MASK_VOLUME, 0, 0 1137 }; 1138 1139 // Index of mixtable1[] member is Device ID 1140 // and must be <= SOUND_MIXER_NRDEVICES. 1141 // Value of array member is index into s->mix.vol[] 1142 static const unsigned char mixtable1[SOUND_MIXER_NRDEVICES] = { 1143 [SOUND_MIXER_PCM] = 1, // voice 1144 [SOUND_MIXER_LINE1] = 2, // AUX 1145 [SOUND_MIXER_CD] = 3, // CD 1146 [SOUND_MIXER_LINE] = 4, // Line 1147 [SOUND_MIXER_SYNTH] = 5, // FM 1148 [SOUND_MIXER_MIC] = 6, // Mic 1149 [SOUND_MIXER_SPEAKER] = 7, // Speaker 1150 [SOUND_MIXER_RECLEV] = 8, // Recording level 1151 [SOUND_MIXER_VOLUME] = 9 // Master Volume 1152 }; 1153 1154 static const unsigned mixreg[] = { 1155 AC97_PCMOUT_VOL, 1156 AC97_AUX_VOL, 1157 AC97_CD_VOL, 1158 AC97_LINEIN_VOL 1159 }; 1160 unsigned char l, r, rl, rr, vidx; 1161 unsigned char attentbl[11] = 1162 { 63, 42, 26, 17, 14, 11, 8, 6, 4, 2, 0 }; 1163 unsigned temp1; 1164 int i, val; 1165 1166 VALIDATE_STATE(s); 1167 CS_DBGOUT(CS_FUNCTION, 4, printk(KERN_INFO 1168 "cs4297a: mixer_ioctl(): s=0x%.8x cmd=0x%.8x\n", 1169 (unsigned) s, cmd)); 1170#if CSDEBUG 1171 cs_printioctl(cmd); 1172#endif 1173#if CSDEBUG_INTERFACE 1174 1175 if ((cmd == SOUND_MIXER_CS_GETDBGMASK) || 1176 (cmd == SOUND_MIXER_CS_SETDBGMASK) || 1177 (cmd == SOUND_MIXER_CS_GETDBGLEVEL) || 1178 (cmd == SOUND_MIXER_CS_SETDBGLEVEL)) 1179 { 1180 switch (cmd) { 1181 1182 case SOUND_MIXER_CS_GETDBGMASK: 1183 return put_user(cs_debugmask, 1184 (unsigned long *) arg); 1185 1186 case SOUND_MIXER_CS_GETDBGLEVEL: 1187 return put_user(cs_debuglevel, 1188 (unsigned long *) arg); 1189 1190 case SOUND_MIXER_CS_SETDBGMASK: 1191 if (get_user(val, (unsigned long *) arg)) 1192 return -EFAULT; 1193 cs_debugmask = val; 1194 return 0; 1195 1196 case SOUND_MIXER_CS_SETDBGLEVEL: 1197 if (get_user(val, (unsigned long *) arg)) 1198 return -EFAULT; 1199 cs_debuglevel = val; 1200 return 0; 1201 default: 1202 CS_DBGOUT(CS_ERROR, 1, printk(KERN_INFO 1203 "cs4297a: mixer_ioctl(): ERROR unknown debug cmd\n")); 1204 return 0; 1205 } 1206 } 1207#endif 1208 1209 if (cmd == SOUND_MIXER_PRIVATE1) { 1210 return -EINVAL; 1211 } 1212 if (cmd == SOUND_MIXER_PRIVATE2) { 1213 // enable/disable/query spatializer 1214 if (get_user(val, (int *) arg)) 1215 return -EFAULT; 1216 if (val != -1) { 1217 temp1 = (val & 0x3f) >> 2; 1218 cs4297a_write_ac97(s, AC97_3D_CONTROL, temp1); 1219 cs4297a_read_ac97(s, AC97_GENERAL_PURPOSE, 1220 &temp1); 1221 cs4297a_write_ac97(s, AC97_GENERAL_PURPOSE, 1222 temp1 | 0x2000); 1223 } 1224 cs4297a_read_ac97(s, AC97_3D_CONTROL, &temp1); 1225 return put_user((temp1 << 2) | 3, (int *) arg); 1226 } 1227 if (cmd == SOUND_MIXER_INFO) { 1228 mixer_info info; 1229 memset(&info, 0, sizeof(info)); 1230 strlcpy(info.id, "CS4297a", sizeof(info.id)); 1231 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name)); 1232 info.modify_counter = s->mix.modcnt; 1233 if (copy_to_user((void *) arg, &info, sizeof(info))) 1234 return -EFAULT; 1235 return 0; 1236 } 1237 if (cmd == SOUND_OLD_MIXER_INFO) { 1238 _old_mixer_info info; 1239 memset(&info, 0, sizeof(info)); 1240 strlcpy(info.id, "CS4297a", sizeof(info.id)); 1241 strlcpy(info.name, "Crystal CS4297a", sizeof(info.name)); 1242 if (copy_to_user((void *) arg, &info, sizeof(info))) 1243 return -EFAULT; 1244 return 0; 1245 } 1246 if (cmd == OSS_GETVERSION) 1247 return put_user(SOUND_VERSION, (int *) arg); 1248 1249 if (_IOC_TYPE(cmd) != 'M' || _SIOC_SIZE(cmd) != sizeof(int)) 1250 return -EINVAL; 1251 1252 // If ioctl has only the SIOC_READ bit(bit 31) 1253 // on, process the only-read commands. 1254 if (_SIOC_DIR(cmd) == _SIOC_READ) { 1255 switch (_IOC_NR(cmd)) { 1256 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source 1257 cs4297a_read_ac97(s, AC97_RECORD_SELECT, 1258 &temp1); 1259 return put_user(mixer_src[temp1 & 7], (int *) arg); 1260 1261 case SOUND_MIXER_DEVMASK: // Arg contains a bit for each supported device 1262 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE | 1263 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV, 1264 (int *) arg); 1265 1266 case SOUND_MIXER_RECMASK: // Arg contains a bit for each supported recording source 1267 return put_user(SOUND_MASK_LINE | SOUND_MASK_VOLUME, 1268 (int *) arg); 1269 1270 case SOUND_MIXER_STEREODEVS: // Mixer channels supporting stereo 1271 return put_user(SOUND_MASK_PCM | SOUND_MASK_LINE | 1272 SOUND_MASK_VOLUME | SOUND_MASK_RECLEV, 1273 (int *) arg); 1274 1275 case SOUND_MIXER_CAPS: 1276 return put_user(SOUND_CAP_EXCL_INPUT, (int *) arg); 1277 1278 default: 1279 i = _IOC_NR(cmd); 1280 if (i >= SOUND_MIXER_NRDEVICES 1281 || !(vidx = mixtable1[i])) 1282 return -EINVAL; 1283 return put_user(s->mix.vol[vidx - 1], (int *) arg); 1284 } 1285 } 1286 // If ioctl doesn't have both the SIOC_READ and 1287 // the SIOC_WRITE bit set, return invalid. 1288 if (_SIOC_DIR(cmd) != (_SIOC_READ | _SIOC_WRITE)) 1289 return -EINVAL; 1290 1291 // Increment the count of volume writes. 1292 s->mix.modcnt++; 1293 1294 // Isolate the command; it must be a write. 1295 switch (_IOC_NR(cmd)) { 1296 1297 case SOUND_MIXER_RECSRC: // Arg contains a bit for each recording source 1298 if (get_user(val, (int *) arg)) 1299 return -EFAULT; 1300 i = hweight32(val); // i = # bits on in val. 1301 if (i != 1) // One & only 1 bit must be on. 1302 return 0; 1303 for (i = 0; i < sizeof(mixer_src) / sizeof(int); i++) { 1304 if (val == mixer_src[i]) { 1305 temp1 = (i << 8) | i; 1306 cs4297a_write_ac97(s, 1307 AC97_RECORD_SELECT, 1308 temp1); 1309 return 0; 1310 } 1311 } 1312 return 0; 1313 1314 case SOUND_MIXER_VOLUME: 1315 if (get_user(val, (int *) arg)) 1316 return -EFAULT; 1317 l = val & 0xff; 1318 if (l > 100) 1319 l = 100; // Max soundcard.h vol is 100. 1320 if (l < 6) { 1321 rl = 63; 1322 l = 0; 1323 } else 1324 rl = attentbl[(10 * l) / 100]; // Convert 0-100 vol to 63-0 atten. 1325 1326 r = (val >> 8) & 0xff; 1327 if (r > 100) 1328 r = 100; // Max right volume is 100, too 1329 if (r < 6) { 1330 rr = 63; 1331 r = 0; 1332 } else 1333 rr = attentbl[(10 * r) / 100]; // Convert volume to attenuation. 1334 1335 if ((rl > 60) && (rr > 60)) // If both l & r are 'low', 1336 temp1 = 0x8000; // turn on the mute bit. 1337 else 1338 temp1 = 0; 1339 1340 temp1 |= (rl << 8) | rr; 1341 1342 cs4297a_write_ac97(s, AC97_MASTER_VOL_STEREO, temp1); 1343 cs4297a_write_ac97(s, AC97_PHONE_VOL, temp1); 1344 1345#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1346 s->mix.vol[8] = ((unsigned int) r << 8) | l; 1347#else 1348 s->mix.vol[8] = val; 1349#endif 1350 return put_user(s->mix.vol[8], (int *) arg); 1351 1352 case SOUND_MIXER_SPEAKER: 1353 if (get_user(val, (int *) arg)) 1354 return -EFAULT; 1355 l = val & 0xff; 1356 if (l > 100) 1357 l = 100; 1358 if (l < 3) { 1359 rl = 0; 1360 l = 0; 1361 } else { 1362 rl = (l * 2 - 5) / 13; // Convert 0-100 range to 0-15. 1363 l = (rl * 13 + 5) / 2; 1364 } 1365 1366 if (rl < 3) { 1367 temp1 = 0x8000; 1368 rl = 0; 1369 } else 1370 temp1 = 0; 1371 rl = 15 - rl; // Convert volume to attenuation. 1372 temp1 |= rl << 1; 1373 cs4297a_write_ac97(s, AC97_PCBEEP_VOL, temp1); 1374 1375#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1376 s->mix.vol[6] = l << 8; 1377#else 1378 s->mix.vol[6] = val; 1379#endif 1380 return put_user(s->mix.vol[6], (int *) arg); 1381 1382 case SOUND_MIXER_RECLEV: 1383 if (get_user(val, (int *) arg)) 1384 return -EFAULT; 1385 l = val & 0xff; 1386 if (l > 100) 1387 l = 100; 1388 r = (val >> 8) & 0xff; 1389 if (r > 100) 1390 r = 100; 1391 rl = (l * 2 - 5) / 13; // Convert 0-100 scale to 0-15. 1392 rr = (r * 2 - 5) / 13; 1393 if (rl < 3 && rr < 3) 1394 temp1 = 0x8000; 1395 else 1396 temp1 = 0; 1397 1398 temp1 = temp1 | (rl << 8) | rr; 1399 cs4297a_write_ac97(s, AC97_RECORD_GAIN, temp1); 1400 1401#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1402 s->mix.vol[7] = ((unsigned int) r << 8) | l; 1403#else 1404 s->mix.vol[7] = val; 1405#endif 1406 return put_user(s->mix.vol[7], (int *) arg); 1407 1408 case SOUND_MIXER_MIC: 1409 if (get_user(val, (int *) arg)) 1410 return -EFAULT; 1411 l = val & 0xff; 1412 if (l > 100) 1413 l = 100; 1414 if (l < 1) { 1415 l = 0; 1416 rl = 0; 1417 } else { 1418 rl = ((unsigned) l * 5 - 4) / 16; // Convert 0-100 range to 0-31. 1419 l = (rl * 16 + 4) / 5; 1420 } 1421 cs4297a_read_ac97(s, AC97_MIC_VOL, &temp1); 1422 temp1 &= 0x40; // Isolate 20db gain bit. 1423 if (rl < 3) { 1424 temp1 |= 0x8000; 1425 rl = 0; 1426 } 1427 rl = 31 - rl; // Convert volume to attenuation. 1428 temp1 |= rl; 1429 cs4297a_write_ac97(s, AC97_MIC_VOL, temp1); 1430 1431#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1432 s->mix.vol[5] = val << 8; 1433#else 1434 s->mix.vol[5] = val; 1435#endif 1436 return put_user(s->mix.vol[5], (int *) arg); 1437 1438 1439 case SOUND_MIXER_SYNTH: 1440 if (get_user(val, (int *) arg)) 1441 return -EFAULT; 1442 l = val & 0xff; 1443 if (l > 100) 1444 l = 100; 1445 if (get_user(val, (int *) arg)) 1446 return -EFAULT; 1447 r = (val >> 8) & 0xff; 1448 if (r > 100) 1449 r = 100; 1450 rl = (l * 2 - 11) / 3; // Convert 0-100 range to 0-63. 1451 rr = (r * 2 - 11) / 3; 1452 if (rl < 3) // If l is low, turn on 1453 temp1 = 0x0080; // the mute bit. 1454 else 1455 temp1 = 0; 1456 1457 rl = 63 - rl; // Convert vol to attenuation. 1458// writel(temp1 | rl, s->pBA0 + FMLVC); 1459 if (rr < 3) // If rr is low, turn on 1460 temp1 = 0x0080; // the mute bit. 1461 else 1462 temp1 = 0; 1463 rr = 63 - rr; // Convert vol to attenuation. 1464// writel(temp1 | rr, s->pBA0 + FMRVC); 1465 1466#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1467 s->mix.vol[4] = (r << 8) | l; 1468#else 1469 s->mix.vol[4] = val; 1470#endif 1471 return put_user(s->mix.vol[4], (int *) arg); 1472 1473 1474 default: 1475 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO 1476 "cs4297a: mixer_ioctl(): default\n")); 1477 1478 i = _IOC_NR(cmd); 1479 if (i >= SOUND_MIXER_NRDEVICES || !(vidx = mixtable1[i])) 1480 return -EINVAL; 1481 if (get_user(val, (int *) arg)) 1482 return -EFAULT; 1483 l = val & 0xff; 1484 if (l > 100) 1485 l = 100; 1486 if (l < 1) { 1487 l = 0; 1488 rl = 31; 1489 } else 1490 rl = (attentbl[(l * 10) / 100]) >> 1; 1491 1492 r = (val >> 8) & 0xff; 1493 if (r > 100) 1494 r = 100; 1495 if (r < 1) { 1496 r = 0; 1497 rr = 31; 1498 } else 1499 rr = (attentbl[(r * 10) / 100]) >> 1; 1500 if ((rl > 30) && (rr > 30)) 1501 temp1 = 0x8000; 1502 else 1503 temp1 = 0; 1504 temp1 = temp1 | (rl << 8) | rr; 1505 cs4297a_write_ac97(s, mixreg[vidx - 1], temp1); 1506 1507#ifdef OSS_DOCUMENTED_MIXER_SEMANTICS 1508 s->mix.vol[vidx - 1] = ((unsigned int) r << 8) | l; 1509#else 1510 s->mix.vol[vidx - 1] = val; 1511#endif 1512 return put_user(s->mix.vol[vidx - 1], (int *) arg); 1513 } 1514} 1515 1516 1517// --------------------------------------------------------------------- 1518 1519static int cs4297a_open_mixdev(struct inode *inode, struct file *file) 1520{ 1521 int minor = iminor(inode); 1522 struct cs4297a_state *s=NULL; 1523 struct list_head *entry; 1524 1525 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4, 1526 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()+\n")); 1527 1528 lock_kernel(); 1529 list_for_each(entry, &cs4297a_devs) 1530 { 1531 s = list_entry(entry, struct cs4297a_state, list); 1532 if(s->dev_mixer == minor) 1533 break; 1534 } 1535 if (!s) 1536 { 1537 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, 1538 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- -ENODEV\n")); 1539 1540 unlock_kernel(); 1541 return -ENODEV; 1542 } 1543 VALIDATE_STATE(s); 1544 file->private_data = s; 1545 1546 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 4, 1547 printk(KERN_INFO "cs4297a: cs4297a_open_mixdev()- 0\n")); 1548 unlock_kernel(); 1549 1550 return nonseekable_open(inode, file); 1551} 1552 1553 1554static int cs4297a_release_mixdev(struct inode *inode, struct file *file) 1555{ 1556 struct cs4297a_state *s = 1557 (struct cs4297a_state *) file->private_data; 1558 1559 VALIDATE_STATE(s); 1560 return 0; 1561} 1562 1563 1564static int cs4297a_ioctl_mixdev(struct file *file, 1565 unsigned int cmd, unsigned long arg) 1566{ 1567 int ret; 1568 lock_kernel(); 1569 ret = mixer_ioctl((struct cs4297a_state *) file->private_data, cmd, 1570 arg); 1571 unlock_kernel(); 1572 return ret; 1573} 1574 1575 1576// ****************************************************************************************** 1577// Mixer file operations struct. 1578// ****************************************************************************************** 1579static const struct file_operations cs4297a_mixer_fops = { 1580 .owner = THIS_MODULE, 1581 .llseek = no_llseek, 1582 .unlocked_ioctl = cs4297a_ioctl_mixdev, 1583 .open = cs4297a_open_mixdev, 1584 .release = cs4297a_release_mixdev, 1585}; 1586 1587// --------------------------------------------------------------------- 1588 1589 1590static int drain_adc(struct cs4297a_state *s, int nonblock) 1591{ 1592 /* This routine serves no purpose currently - any samples 1593 sitting in the receive queue will just be processed by the 1594 background consumer. This would be different if DMA 1595 actually stopped when there were no clients. */ 1596 return 0; 1597} 1598 1599static int drain_dac(struct cs4297a_state *s, int nonblock) 1600{ 1601 DECLARE_WAITQUEUE(wait, current); 1602 unsigned long flags; 1603 unsigned hwptr; 1604 unsigned tmo; 1605 int count; 1606 1607 if (s->dma_dac.mapped) 1608 return 0; 1609 if (nonblock) 1610 return -EBUSY; 1611 add_wait_queue(&s->dma_dac.wait, &wait); 1612 while ((count = __raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) || 1613 (s->dma_dac.count > 0)) { 1614 if (!signal_pending(current)) { 1615 set_current_state(TASK_INTERRUPTIBLE); 1616 /* XXXKW is this calculation working? */ 1617 tmo = ((count * FRAME_TX_US) * HZ) / 1000000; 1618 schedule_timeout(tmo + 1); 1619 } else { 1620 /* XXXKW do I care if there is a signal pending? */ 1621 } 1622 } 1623 spin_lock_irqsave(&s->lock, flags); 1624 /* Reset the bookkeeping */ 1625 hwptr = (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - 1626 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t)); 1627 s->dma_dac.hwptr = s->dma_dac.swptr = hwptr; 1628 spin_unlock_irqrestore(&s->lock, flags); 1629 remove_wait_queue(&s->dma_dac.wait, &wait); 1630 current->state = TASK_RUNNING; 1631 return 0; 1632} 1633 1634 1635// --------------------------------------------------------------------- 1636 1637static ssize_t cs4297a_read(struct file *file, char *buffer, size_t count, 1638 loff_t * ppos) 1639{ 1640 struct cs4297a_state *s = 1641 (struct cs4297a_state *) file->private_data; 1642 ssize_t ret; 1643 unsigned long flags; 1644 int cnt, count_fr, cnt_by; 1645 unsigned copied = 0; 1646 1647 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2, 1648 printk(KERN_INFO "cs4297a: cs4297a_read()+ %d \n", count)); 1649 1650 VALIDATE_STATE(s); 1651 if (s->dma_adc.mapped) 1652 return -ENXIO; 1653 if (!s->dma_adc.ready && (ret = prog_dmabuf_adc(s))) 1654 return ret; 1655 if (!access_ok(VERIFY_WRITE, buffer, count)) 1656 return -EFAULT; 1657 ret = 0; 1658// 1659// "count" is the amount of bytes to read (from app), is decremented each loop 1660// by the amount of bytes that have been returned to the user buffer. 1661// "cnt" is the running total of each read from the buffer (changes each loop) 1662// "buffer" points to the app's buffer 1663// "ret" keeps a running total of the amount of bytes that have been copied 1664// to the user buffer. 1665// "copied" is the total bytes copied into the user buffer for each loop. 1666// 1667 while (count > 0) { 1668 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO 1669 "_read() count>0 count=%d .count=%d .swptr=%d .hwptr=%d \n", 1670 count, s->dma_adc.count, 1671 s->dma_adc.swptr, s->dma_adc.hwptr)); 1672 spin_lock_irqsave(&s->lock, flags); 1673 1674 /* cnt will be the number of available samples (16-bit 1675 stereo); it starts out as the maxmimum consequetive 1676 samples */ 1677 cnt = (s->dma_adc.sb_end - s->dma_adc.sb_swptr) / 2; 1678 count_fr = s->dma_adc.count / FRAME_SAMPLE_BYTES; 1679 1680 // dma_adc.count is the current total bytes that have not been read. 1681 // if the amount of unread bytes from the current sw pointer to the 1682 // end of the buffer is greater than the current total bytes that 1683 // have not been read, then set the "cnt" (unread bytes) to the 1684 // amount of unread bytes. 1685 1686 if (count_fr < cnt) 1687 cnt = count_fr; 1688 cnt_by = cnt * FRAME_SAMPLE_BYTES; 1689 spin_unlock_irqrestore(&s->lock, flags); 1690 // 1691 // if we are converting from 8/16 then we need to copy 1692 // twice the number of 16 bit bytes then 8 bit bytes. 1693 // 1694 if (s->conversion) { 1695 if (cnt_by > (count * 2)) { 1696 cnt = (count * 2) / FRAME_SAMPLE_BYTES; 1697 cnt_by = count * 2; 1698 } 1699 } else { 1700 if (cnt_by > count) { 1701 cnt = count / FRAME_SAMPLE_BYTES; 1702 cnt_by = count; 1703 } 1704 } 1705 // 1706 // "cnt" NOW is the smaller of the amount that will be read, 1707 // and the amount that is requested in this read (or partial). 1708 // if there are no bytes in the buffer to read, then start the 1709 // ADC and wait for the interrupt handler to wake us up. 1710 // 1711 if (cnt <= 0) { 1712 1713 // start up the dma engine and then continue back to the top of 1714 // the loop when wake up occurs. 1715 start_adc(s); 1716 if (file->f_flags & O_NONBLOCK) 1717 return ret ? ret : -EAGAIN; 1718 interruptible_sleep_on(&s->dma_adc.wait); 1719 if (signal_pending(current)) 1720 return ret ? ret : -ERESTARTSYS; 1721 continue; 1722 } 1723 // there are bytes in the buffer to read. 1724 // copy from the hw buffer over to the user buffer. 1725 // user buffer is designated by "buffer" 1726 // virtual address to copy from is dma_buf+swptr 1727 // the "cnt" is the number of bytes to read. 1728 1729 CS_DBGOUT(CS_WAVE_READ, 2, printk(KERN_INFO 1730 "_read() copy_to cnt=%d count=%d ", cnt_by, count)); 1731 CS_DBGOUT(CS_WAVE_READ, 8, printk(KERN_INFO 1732 " .sbufsz=%d .count=%d buffer=0x%.8x ret=%d\n", 1733 s->dma_adc.sbufsz, s->dma_adc.count, 1734 (unsigned) buffer, ret)); 1735 1736 if (copy_to_user (buffer, ((void *)s->dma_adc.sb_swptr), cnt_by)) 1737 return ret ? ret : -EFAULT; 1738 copied = cnt_by; 1739 1740 /* Return the descriptors */ 1741 spin_lock_irqsave(&s->lock, flags); 1742 CS_DBGOUT(CS_FUNCTION, 2, 1743 printk(KERN_INFO "cs4297a: upd_rcv sw->hw %x/%x\n", s->dma_adc.swptr, s->dma_adc.hwptr)); 1744 s->dma_adc.count -= cnt_by; 1745 s->dma_adc.sb_swptr += cnt * 2; 1746 if (s->dma_adc.sb_swptr == s->dma_adc.sb_end) 1747 s->dma_adc.sb_swptr = s->dma_adc.sample_buf; 1748 spin_unlock_irqrestore(&s->lock, flags); 1749 count -= copied; 1750 buffer += copied; 1751 ret += copied; 1752 start_adc(s); 1753 } 1754 CS_DBGOUT(CS_FUNCTION | CS_WAVE_READ, 2, 1755 printk(KERN_INFO "cs4297a: cs4297a_read()- %d\n", ret)); 1756 return ret; 1757} 1758 1759 1760static ssize_t cs4297a_write(struct file *file, const char *buffer, 1761 size_t count, loff_t * ppos) 1762{ 1763 struct cs4297a_state *s = 1764 (struct cs4297a_state *) file->private_data; 1765 ssize_t ret; 1766 unsigned long flags; 1767 unsigned swptr, hwptr; 1768 int cnt; 1769 1770 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2, 1771 printk(KERN_INFO "cs4297a: cs4297a_write()+ count=%d\n", 1772 count)); 1773 VALIDATE_STATE(s); 1774 1775 if (s->dma_dac.mapped) 1776 return -ENXIO; 1777 if (!s->dma_dac.ready && (ret = prog_dmabuf_dac(s))) 1778 return ret; 1779 if (!access_ok(VERIFY_READ, buffer, count)) 1780 return -EFAULT; 1781 ret = 0; 1782 while (count > 0) { 1783 serdma_t *d = &s->dma_dac; 1784 int copy_cnt; 1785 u32 *s_tmpl; 1786 u32 *t_tmpl; 1787 u32 left, right; 1788 int swap = (s->prop_dac.fmt == AFMT_S16_LE) || (s->prop_dac.fmt == AFMT_U16_LE); 1789 1790 /* XXXXXX this is broken for BLOAT_FACTOR */ 1791 spin_lock_irqsave(&s->lock, flags); 1792 if (d->count < 0) { 1793 d->count = 0; 1794 d->swptr = d->hwptr; 1795 } 1796 if (d->underrun) { 1797 d->underrun = 0; 1798 hwptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - 1799 d->descrtab_phys) / sizeof(serdma_descr_t)); 1800 d->swptr = d->hwptr = hwptr; 1801 } 1802 swptr = d->swptr; 1803 cnt = d->sbufsz - (swptr * FRAME_SAMPLE_BYTES); 1804 /* Will this write fill up the buffer? */ 1805 if (d->count + cnt > d->sbufsz) 1806 cnt = d->sbufsz - d->count; 1807 spin_unlock_irqrestore(&s->lock, flags); 1808 if (cnt > count) 1809 cnt = count; 1810 if (cnt <= 0) { 1811 start_dac(s); 1812 if (file->f_flags & O_NONBLOCK) 1813 return ret ? ret : -EAGAIN; 1814 interruptible_sleep_on(&d->wait); 1815 if (signal_pending(current)) 1816 return ret ? ret : -ERESTARTSYS; 1817 continue; 1818 } 1819 if (copy_from_user(d->sample_buf, buffer, cnt)) 1820 return ret ? ret : -EFAULT; 1821 1822 copy_cnt = cnt; 1823 s_tmpl = (u32 *)d->sample_buf; 1824 t_tmpl = (u32 *)(d->dma_buf + (swptr * 4)); 1825 1826 /* XXXKW assuming 16-bit stereo! */ 1827 do { 1828 u32 tmp; 1829 1830 t_tmpl[0] = cpu_to_be32(0x98000000); 1831 1832 tmp = be32_to_cpu(s_tmpl[0]); 1833 left = tmp & 0xffff; 1834 right = tmp >> 16; 1835 if (swap) { 1836 left = swab16(left); 1837 right = swab16(right); 1838 } 1839 t_tmpl[1] = cpu_to_be32(left >> 8); 1840 t_tmpl[2] = cpu_to_be32(((left & 0xff) << 24) | 1841 (right << 4)); 1842 1843 s_tmpl++; 1844 t_tmpl += 8; 1845 copy_cnt -= 4; 1846 } while (copy_cnt); 1847 1848 /* Mux in any pending read/write accesses */ 1849 if (s->reg_request) { 1850 *(u64 *)(d->dma_buf + (swptr * 4)) |= 1851 cpu_to_be64(s->reg_request); 1852 s->reg_request = 0; 1853 wake_up(&s->dma_dac.reg_wait); 1854 } 1855 1856 CS_DBGOUT(CS_WAVE_WRITE, 4, 1857 printk(KERN_INFO 1858 "cs4297a: copy in %d to swptr %x\n", cnt, swptr)); 1859 1860 swptr = (swptr + (cnt/FRAME_SAMPLE_BYTES)) % d->ringsz; 1861 __raw_writeq(cnt/FRAME_SAMPLE_BYTES, SS_CSR(R_SER_DMA_DSCR_COUNT_TX)); 1862 spin_lock_irqsave(&s->lock, flags); 1863 d->swptr = swptr; 1864 d->count += cnt; 1865 d->endcleared = 0; 1866 spin_unlock_irqrestore(&s->lock, flags); 1867 count -= cnt; 1868 buffer += cnt; 1869 ret += cnt; 1870 start_dac(s); 1871 } 1872 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE, 2, 1873 printk(KERN_INFO "cs4297a: cs4297a_write()- %d\n", ret)); 1874 return ret; 1875} 1876 1877 1878static unsigned int cs4297a_poll(struct file *file, 1879 struct poll_table_struct *wait) 1880{ 1881 struct cs4297a_state *s = 1882 (struct cs4297a_state *) file->private_data; 1883 unsigned long flags; 1884 unsigned int mask = 0; 1885 1886 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, 1887 printk(KERN_INFO "cs4297a: cs4297a_poll()+\n")); 1888 VALIDATE_STATE(s); 1889 if (file->f_mode & FMODE_WRITE) { 1890 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, 1891 printk(KERN_INFO 1892 "cs4297a: cs4297a_poll() wait on FMODE_WRITE\n")); 1893 if(!s->dma_dac.ready && prog_dmabuf_dac(s)) 1894 return 0; 1895 poll_wait(file, &s->dma_dac.wait, wait); 1896 } 1897 if (file->f_mode & FMODE_READ) { 1898 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, 1899 printk(KERN_INFO 1900 "cs4297a: cs4297a_poll() wait on FMODE_READ\n")); 1901 if(!s->dma_dac.ready && prog_dmabuf_adc(s)) 1902 return 0; 1903 poll_wait(file, &s->dma_adc.wait, wait); 1904 } 1905 spin_lock_irqsave(&s->lock, flags); 1906 cs4297a_update_ptr(s,CS_FALSE); 1907 if (file->f_mode & FMODE_WRITE) { 1908 if (s->dma_dac.mapped) { 1909 if (s->dma_dac.count >= 1910 (signed) s->dma_dac.fragsize) { 1911 if (s->dma_dac.wakeup) 1912 mask |= POLLOUT | POLLWRNORM; 1913 else 1914 mask = 0; 1915 s->dma_dac.wakeup = 0; 1916 } 1917 } else { 1918 if ((signed) (s->dma_dac.sbufsz/2) >= s->dma_dac.count) 1919 mask |= POLLOUT | POLLWRNORM; 1920 } 1921 } else if (file->f_mode & FMODE_READ) { 1922 if (s->dma_adc.mapped) { 1923 if (s->dma_adc.count >= (signed) s->dma_adc.fragsize) 1924 mask |= POLLIN | POLLRDNORM; 1925 } else { 1926 if (s->dma_adc.count > 0) 1927 mask |= POLLIN | POLLRDNORM; 1928 } 1929 } 1930 spin_unlock_irqrestore(&s->lock, flags); 1931 CS_DBGOUT(CS_FUNCTION | CS_WAVE_WRITE | CS_WAVE_READ, 4, 1932 printk(KERN_INFO "cs4297a: cs4297a_poll()- 0x%.8x\n", 1933 mask)); 1934 return mask; 1935} 1936 1937 1938static int cs4297a_mmap(struct file *file, struct vm_area_struct *vma) 1939{ 1940 /* XXXKW currently no mmap support */ 1941 return -EINVAL; 1942 return 0; 1943} 1944 1945 1946static int cs4297a_ioctl(struct file *file, 1947 unsigned int cmd, unsigned long arg) 1948{ 1949 struct cs4297a_state *s = 1950 (struct cs4297a_state *) file->private_data; 1951 unsigned long flags; 1952 audio_buf_info abinfo; 1953 count_info cinfo; 1954 int val, mapped, ret; 1955 1956 CS_DBGOUT(CS_FUNCTION|CS_IOCTL, 4, printk(KERN_INFO 1957 "cs4297a: cs4297a_ioctl(): file=0x%.8x cmd=0x%.8x\n", 1958 (unsigned) file, cmd)); 1959#if CSDEBUG 1960 cs_printioctl(cmd); 1961#endif 1962 VALIDATE_STATE(s); 1963 mapped = ((file->f_mode & FMODE_WRITE) && s->dma_dac.mapped) || 1964 ((file->f_mode & FMODE_READ) && s->dma_adc.mapped); 1965 switch (cmd) { 1966 case OSS_GETVERSION: 1967 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 1968 "cs4297a: cs4297a_ioctl(): SOUND_VERSION=0x%.8x\n", 1969 SOUND_VERSION)); 1970 return put_user(SOUND_VERSION, (int *) arg); 1971 1972 case SNDCTL_DSP_SYNC: 1973 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO 1974 "cs4297a: cs4297a_ioctl(): DSP_SYNC\n")); 1975 if (file->f_mode & FMODE_WRITE) 1976 return drain_dac(s, 1977 0 /*file->f_flags & O_NONBLOCK */ 1978 ); 1979 return 0; 1980 1981 case SNDCTL_DSP_SETDUPLEX: 1982 return 0; 1983 1984 case SNDCTL_DSP_GETCAPS: 1985 return put_user(DSP_CAP_DUPLEX | DSP_CAP_REALTIME | 1986 DSP_CAP_TRIGGER | DSP_CAP_MMAP, 1987 (int *) arg); 1988 1989 case SNDCTL_DSP_RESET: 1990 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO 1991 "cs4297a: cs4297a_ioctl(): DSP_RESET\n")); 1992 if (file->f_mode & FMODE_WRITE) { 1993 stop_dac(s); 1994 synchronize_irq(s->irq); 1995 s->dma_dac.count = s->dma_dac.total_bytes = 1996 s->dma_dac.blocks = s->dma_dac.wakeup = 0; 1997 s->dma_dac.swptr = s->dma_dac.hwptr = 1998 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_TX)) & M_DMA_CURDSCR_ADDR) - 1999 s->dma_dac.descrtab_phys) / sizeof(serdma_descr_t)); 2000 } 2001 if (file->f_mode & FMODE_READ) { 2002 stop_adc(s); 2003 synchronize_irq(s->irq); 2004 s->dma_adc.count = s->dma_adc.total_bytes = 2005 s->dma_adc.blocks = s->dma_dac.wakeup = 0; 2006 s->dma_adc.swptr = s->dma_adc.hwptr = 2007 (int)(((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - 2008 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t)); 2009 } 2010 return 0; 2011 2012 case SNDCTL_DSP_SPEED: 2013 if (get_user(val, (int *) arg)) 2014 return -EFAULT; 2015 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2016 "cs4297a: cs4297a_ioctl(): DSP_SPEED val=%d -> 48000\n", val)); 2017 val = 48000; 2018 return put_user(val, (int *) arg); 2019 2020 case SNDCTL_DSP_STEREO: 2021 if (get_user(val, (int *) arg)) 2022 return -EFAULT; 2023 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2024 "cs4297a: cs4297a_ioctl(): DSP_STEREO val=%d\n", val)); 2025 if (file->f_mode & FMODE_READ) { 2026 stop_adc(s); 2027 s->dma_adc.ready = 0; 2028 s->prop_adc.channels = val ? 2 : 1; 2029 } 2030 if (file->f_mode & FMODE_WRITE) { 2031 stop_dac(s); 2032 s->dma_dac.ready = 0; 2033 s->prop_dac.channels = val ? 2 : 1; 2034 } 2035 return 0; 2036 2037 case SNDCTL_DSP_CHANNELS: 2038 if (get_user(val, (int *) arg)) 2039 return -EFAULT; 2040 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2041 "cs4297a: cs4297a_ioctl(): DSP_CHANNELS val=%d\n", 2042 val)); 2043 if (val != 0) { 2044 if (file->f_mode & FMODE_READ) { 2045 stop_adc(s); 2046 s->dma_adc.ready = 0; 2047 if (val >= 2) 2048 s->prop_adc.channels = 2; 2049 else 2050 s->prop_adc.channels = 1; 2051 } 2052 if (file->f_mode & FMODE_WRITE) { 2053 stop_dac(s); 2054 s->dma_dac.ready = 0; 2055 if (val >= 2) 2056 s->prop_dac.channels = 2; 2057 else 2058 s->prop_dac.channels = 1; 2059 } 2060 } 2061 2062 if (file->f_mode & FMODE_WRITE) 2063 val = s->prop_dac.channels; 2064 else if (file->f_mode & FMODE_READ) 2065 val = s->prop_adc.channels; 2066 2067 return put_user(val, (int *) arg); 2068 2069 case SNDCTL_DSP_GETFMTS: // Returns a mask 2070 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2071 "cs4297a: cs4297a_ioctl(): DSP_GETFMT val=0x%.8x\n", 2072 AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 | 2073 AFMT_U8)); 2074 return put_user(AFMT_S16_LE | AFMT_U16_LE | AFMT_S8 | 2075 AFMT_U8, (int *) arg); 2076 2077 case SNDCTL_DSP_SETFMT: 2078 if (get_user(val, (int *) arg)) 2079 return -EFAULT; 2080 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2081 "cs4297a: cs4297a_ioctl(): DSP_SETFMT val=0x%.8x\n", 2082 val)); 2083 if (val != AFMT_QUERY) { 2084 if (file->f_mode & FMODE_READ) { 2085 stop_adc(s); 2086 s->dma_adc.ready = 0; 2087 if (val != AFMT_S16_LE 2088 && val != AFMT_U16_LE && val != AFMT_S8 2089 && val != AFMT_U8) 2090 val = AFMT_U8; 2091 s->prop_adc.fmt = val; 2092 s->prop_adc.fmt_original = s->prop_adc.fmt; 2093 } 2094 if (file->f_mode & FMODE_WRITE) { 2095 stop_dac(s); 2096 s->dma_dac.ready = 0; 2097 if (val != AFMT_S16_LE 2098 && val != AFMT_U16_LE && val != AFMT_S8 2099 && val != AFMT_U8) 2100 val = AFMT_U8; 2101 s->prop_dac.fmt = val; 2102 s->prop_dac.fmt_original = s->prop_dac.fmt; 2103 } 2104 } else { 2105 if (file->f_mode & FMODE_WRITE) 2106 val = s->prop_dac.fmt_original; 2107 else if (file->f_mode & FMODE_READ) 2108 val = s->prop_adc.fmt_original; 2109 } 2110 CS_DBGOUT(CS_IOCTL | CS_PARMS, 4, printk(KERN_INFO 2111 "cs4297a: cs4297a_ioctl(): DSP_SETFMT return val=0x%.8x\n", 2112 val)); 2113 return put_user(val, (int *) arg); 2114 2115 case SNDCTL_DSP_POST: 2116 CS_DBGOUT(CS_IOCTL, 4, printk(KERN_INFO 2117 "cs4297a: cs4297a_ioctl(): DSP_POST\n")); 2118 return 0; 2119 2120 case SNDCTL_DSP_GETTRIGGER: 2121 val = 0; 2122 if (file->f_mode & s->ena & FMODE_READ) 2123 val |= PCM_ENABLE_INPUT; 2124 if (file->f_mode & s->ena & FMODE_WRITE) 2125 val |= PCM_ENABLE_OUTPUT; 2126 return put_user(val, (int *) arg); 2127 2128 case SNDCTL_DSP_SETTRIGGER: 2129 if (get_user(val, (int *) arg)) 2130 return -EFAULT; 2131 if (file->f_mode & FMODE_READ) { 2132 if (val & PCM_ENABLE_INPUT) { 2133 if (!s->dma_adc.ready 2134 && (ret = prog_dmabuf_adc(s))) 2135 return ret; 2136 start_adc(s); 2137 } else 2138 stop_adc(s); 2139 } 2140 if (file->f_mode & FMODE_WRITE) { 2141 if (val & PCM_ENABLE_OUTPUT) { 2142 if (!s->dma_dac.ready 2143 && (ret = prog_dmabuf_dac(s))) 2144 return ret; 2145 start_dac(s); 2146 } else 2147 stop_dac(s); 2148 } 2149 return 0; 2150 2151 case SNDCTL_DSP_GETOSPACE: 2152 if (!(file->f_mode & FMODE_WRITE)) 2153 return -EINVAL; 2154 if (!s->dma_dac.ready && (val = prog_dmabuf_dac(s))) 2155 return val; 2156 spin_lock_irqsave(&s->lock, flags); 2157 cs4297a_update_ptr(s,CS_FALSE); 2158 abinfo.fragsize = s->dma_dac.fragsize; 2159 if (s->dma_dac.mapped) 2160 abinfo.bytes = s->dma_dac.sbufsz; 2161 else 2162 abinfo.bytes = 2163 s->dma_dac.sbufsz - s->dma_dac.count; 2164 abinfo.fragstotal = s->dma_dac.numfrag; 2165 abinfo.fragments = abinfo.bytes >> s->dma_dac.fragshift; 2166 CS_DBGOUT(CS_FUNCTION | CS_PARMS, 4, printk(KERN_INFO 2167 "cs4297a: cs4297a_ioctl(): GETOSPACE .fragsize=%d .bytes=%d .fragstotal=%d .fragments=%d\n", 2168 abinfo.fragsize,abinfo.bytes,abinfo.fragstotal, 2169 abinfo.fragments)); 2170 spin_unlock_irqrestore(&s->lock, flags); 2171 return copy_to_user((void *) arg, &abinfo, 2172 sizeof(abinfo)) ? -EFAULT : 0; 2173 2174 case SNDCTL_DSP_GETISPACE: 2175 if (!(file->f_mode & FMODE_READ)) 2176 return -EINVAL; 2177 if (!s->dma_adc.ready && (val = prog_dmabuf_adc(s))) 2178 return val; 2179 spin_lock_irqsave(&s->lock, flags); 2180 cs4297a_update_ptr(s,CS_FALSE); 2181 if (s->conversion) { 2182 abinfo.fragsize = s->dma_adc.fragsize / 2; 2183 abinfo.bytes = s->dma_adc.count / 2; 2184 abinfo.fragstotal = s->dma_adc.numfrag; 2185 abinfo.fragments = 2186 abinfo.bytes >> (s->dma_adc.fragshift - 1); 2187 } else { 2188 abinfo.fragsize = s->dma_adc.fragsize; 2189 abinfo.bytes = s->dma_adc.count; 2190 abinfo.fragstotal = s->dma_adc.numfrag; 2191 abinfo.fragments = 2192 abinfo.bytes >> s->dma_adc.fragshift; 2193 } 2194 spin_unlock_irqrestore(&s->lock, flags); 2195 return copy_to_user((void *) arg, &abinfo, 2196 sizeof(abinfo)) ? -EFAULT : 0; 2197 2198 case SNDCTL_DSP_NONBLOCK: 2199 spin_lock(&file->f_lock); 2200 file->f_flags |= O_NONBLOCK; 2201 spin_unlock(&file->f_lock); 2202 return 0; 2203 2204 case SNDCTL_DSP_GETODELAY: 2205 if (!(file->f_mode & FMODE_WRITE)) 2206 return -EINVAL; 2207 if(!s->dma_dac.ready && prog_dmabuf_dac(s)) 2208 return 0; 2209 spin_lock_irqsave(&s->lock, flags); 2210 cs4297a_update_ptr(s,CS_FALSE); 2211 val = s->dma_dac.count; 2212 spin_unlock_irqrestore(&s->lock, flags); 2213 return put_user(val, (int *) arg); 2214 2215 case SNDCTL_DSP_GETIPTR: 2216 if (!(file->f_mode & FMODE_READ)) 2217 return -EINVAL; 2218 if(!s->dma_adc.ready && prog_dmabuf_adc(s)) 2219 return 0; 2220 spin_lock_irqsave(&s->lock, flags); 2221 cs4297a_update_ptr(s,CS_FALSE); 2222 cinfo.bytes = s->dma_adc.total_bytes; 2223 if (s->dma_adc.mapped) { 2224 cinfo.blocks = 2225 (cinfo.bytes >> s->dma_adc.fragshift) - 2226 s->dma_adc.blocks; 2227 s->dma_adc.blocks = 2228 cinfo.bytes >> s->dma_adc.fragshift; 2229 } else { 2230 if (s->conversion) { 2231 cinfo.blocks = 2232 s->dma_adc.count / 2233 2 >> (s->dma_adc.fragshift - 1); 2234 } else 2235 cinfo.blocks = 2236 s->dma_adc.count >> s->dma_adc. 2237 fragshift; 2238 } 2239 if (s->conversion) 2240 cinfo.ptr = s->dma_adc.hwptr / 2; 2241 else 2242 cinfo.ptr = s->dma_adc.hwptr; 2243 if (s->dma_adc.mapped) 2244 s->dma_adc.count &= s->dma_adc.fragsize - 1; 2245 spin_unlock_irqrestore(&s->lock, flags); 2246 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0; 2247 2248 case SNDCTL_DSP_GETOPTR: 2249 if (!(file->f_mode & FMODE_WRITE)) 2250 return -EINVAL; 2251 if(!s->dma_dac.ready && prog_dmabuf_dac(s)) 2252 return 0; 2253 spin_lock_irqsave(&s->lock, flags); 2254 cs4297a_update_ptr(s,CS_FALSE); 2255 cinfo.bytes = s->dma_dac.total_bytes; 2256 if (s->dma_dac.mapped) { 2257 cinfo.blocks = 2258 (cinfo.bytes >> s->dma_dac.fragshift) - 2259 s->dma_dac.blocks; 2260 s->dma_dac.blocks = 2261 cinfo.bytes >> s->dma_dac.fragshift; 2262 } else { 2263 cinfo.blocks = 2264 s->dma_dac.count >> s->dma_dac.fragshift; 2265 } 2266 cinfo.ptr = s->dma_dac.hwptr; 2267 if (s->dma_dac.mapped) 2268 s->dma_dac.count &= s->dma_dac.fragsize - 1; 2269 spin_unlock_irqrestore(&s->lock, flags); 2270 return copy_to_user((void *) arg, &cinfo, sizeof(cinfo)) ? -EFAULT : 0; 2271 2272 case SNDCTL_DSP_GETBLKSIZE: 2273 if (file->f_mode & FMODE_WRITE) { 2274 if ((val = prog_dmabuf_dac(s))) 2275 return val; 2276 return put_user(s->dma_dac.fragsize, (int *) arg); 2277 } 2278 if ((val = prog_dmabuf_adc(s))) 2279 return val; 2280 if (s->conversion) 2281 return put_user(s->dma_adc.fragsize / 2, 2282 (int *) arg); 2283 else 2284 return put_user(s->dma_adc.fragsize, (int *) arg); 2285 2286 case SNDCTL_DSP_SETFRAGMENT: 2287 if (get_user(val, (int *) arg)) 2288 return -EFAULT; 2289 return 0; // Say OK, but do nothing. 2290 2291 case SNDCTL_DSP_SUBDIVIDE: 2292 if ((file->f_mode & FMODE_READ && s->dma_adc.subdivision) 2293 || (file->f_mode & FMODE_WRITE 2294 && s->dma_dac.subdivision)) return -EINVAL; 2295 if (get_user(val, (int *) arg)) 2296 return -EFAULT; 2297 if (val != 1 && val != 2 && val != 4) 2298 return -EINVAL; 2299 if (file->f_mode & FMODE_READ) 2300 s->dma_adc.subdivision = val; 2301 else if (file->f_mode & FMODE_WRITE) 2302 s->dma_dac.subdivision = val; 2303 return 0; 2304 2305 case SOUND_PCM_READ_RATE: 2306 if (file->f_mode & FMODE_READ) 2307 return put_user(s->prop_adc.rate, (int *) arg); 2308 else if (file->f_mode & FMODE_WRITE) 2309 return put_user(s->prop_dac.rate, (int *) arg); 2310 2311 case SOUND_PCM_READ_CHANNELS: 2312 if (file->f_mode & FMODE_READ) 2313 return put_user(s->prop_adc.channels, (int *) arg); 2314 else if (file->f_mode & FMODE_WRITE) 2315 return put_user(s->prop_dac.channels, (int *) arg); 2316 2317 case SOUND_PCM_READ_BITS: 2318 if (file->f_mode & FMODE_READ) 2319 return 2320 put_user( 2321 (s->prop_adc. 2322 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16, 2323 (int *) arg); 2324 else if (file->f_mode & FMODE_WRITE) 2325 return 2326 put_user( 2327 (s->prop_dac. 2328 fmt & (AFMT_S8 | AFMT_U8)) ? 8 : 16, 2329 (int *) arg); 2330 2331 case SOUND_PCM_WRITE_FILTER: 2332 case SNDCTL_DSP_SETSYNCRO: 2333 case SOUND_PCM_READ_FILTER: 2334 return -EINVAL; 2335 } 2336 return mixer_ioctl(s, cmd, arg); 2337} 2338 2339static long cs4297a_unlocked_ioctl(struct file *file, u_int cmd, u_long arg) 2340{ 2341 int ret; 2342 2343 lock_kernel(); 2344 ret = cs4297a_ioctl(file, cmd, arg); 2345 unlock_kernel(); 2346 2347 return ret; 2348} 2349 2350static int cs4297a_release(struct inode *inode, struct file *file) 2351{ 2352 struct cs4297a_state *s = 2353 (struct cs4297a_state *) file->private_data; 2354 2355 CS_DBGOUT(CS_FUNCTION | CS_RELEASE, 2, printk(KERN_INFO 2356 "cs4297a: cs4297a_release(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n", 2357 (unsigned) inode, (unsigned) file, file->f_mode)); 2358 VALIDATE_STATE(s); 2359 2360 if (file->f_mode & FMODE_WRITE) { 2361 drain_dac(s, file->f_flags & O_NONBLOCK); 2362 mutex_lock(&s->open_sem_dac); 2363 stop_dac(s); 2364 dealloc_dmabuf(s, &s->dma_dac); 2365 s->open_mode &= ~FMODE_WRITE; 2366 mutex_unlock(&s->open_sem_dac); 2367 wake_up(&s->open_wait_dac); 2368 } 2369 if (file->f_mode & FMODE_READ) { 2370 drain_adc(s, file->f_flags & O_NONBLOCK); 2371 mutex_lock(&s->open_sem_adc); 2372 stop_adc(s); 2373 dealloc_dmabuf(s, &s->dma_adc); 2374 s->open_mode &= ~FMODE_READ; 2375 mutex_unlock(&s->open_sem_adc); 2376 wake_up(&s->open_wait_adc); 2377 } 2378 return 0; 2379} 2380 2381static int cs4297a_locked_open(struct inode *inode, struct file *file) 2382{ 2383 int minor = iminor(inode); 2384 struct cs4297a_state *s=NULL; 2385 struct list_head *entry; 2386 2387 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO 2388 "cs4297a: cs4297a_open(): inode=0x%.8x file=0x%.8x f_mode=0x%x\n", 2389 (unsigned) inode, (unsigned) file, file->f_mode)); 2390 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO 2391 "cs4297a: status = %08x\n", (int)__raw_readq(SS_CSR(R_SER_STATUS_DEBUG)))); 2392 2393 list_for_each(entry, &cs4297a_devs) 2394 { 2395 s = list_entry(entry, struct cs4297a_state, list); 2396 2397 if (!((s->dev_audio ^ minor) & ~0xf)) 2398 break; 2399 } 2400 if (entry == &cs4297a_devs) 2401 return -ENODEV; 2402 if (!s) { 2403 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, printk(KERN_INFO 2404 "cs4297a: cs4297a_open(): Error - unable to find audio state struct\n")); 2405 return -ENODEV; 2406 } 2407 VALIDATE_STATE(s); 2408 file->private_data = s; 2409 2410 // wait for device to become free 2411 if (!(file->f_mode & (FMODE_WRITE | FMODE_READ))) { 2412 CS_DBGOUT(CS_FUNCTION | CS_OPEN | CS_ERROR, 2, printk(KERN_INFO 2413 "cs4297a: cs4297a_open(): Error - must open READ and/or WRITE\n")); 2414 return -ENODEV; 2415 } 2416 if (file->f_mode & FMODE_WRITE) { 2417 if (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX)) != 0) { 2418 printk(KERN_ERR "cs4297a: TX pipe needs to drain\n"); 2419 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_TX))) 2420 ; 2421 } 2422 2423 mutex_lock(&s->open_sem_dac); 2424 while (s->open_mode & FMODE_WRITE) { 2425 if (file->f_flags & O_NONBLOCK) { 2426 mutex_unlock(&s->open_sem_dac); 2427 return -EBUSY; 2428 } 2429 mutex_unlock(&s->open_sem_dac); 2430 interruptible_sleep_on(&s->open_wait_dac); 2431 2432 if (signal_pending(current)) { 2433 printk("open - sig pending\n"); 2434 return -ERESTARTSYS; 2435 } 2436 mutex_lock(&s->open_sem_dac); 2437 } 2438 } 2439 if (file->f_mode & FMODE_READ) { 2440 mutex_lock(&s->open_sem_adc); 2441 while (s->open_mode & FMODE_READ) { 2442 if (file->f_flags & O_NONBLOCK) { 2443 mutex_unlock(&s->open_sem_adc); 2444 return -EBUSY; 2445 } 2446 mutex_unlock(&s->open_sem_adc); 2447 interruptible_sleep_on(&s->open_wait_adc); 2448 2449 if (signal_pending(current)) { 2450 printk("open - sig pending\n"); 2451 return -ERESTARTSYS; 2452 } 2453 mutex_lock(&s->open_sem_adc); 2454 } 2455 } 2456 s->open_mode |= file->f_mode & (FMODE_READ | FMODE_WRITE); 2457 if (file->f_mode & FMODE_READ) { 2458 s->prop_adc.fmt = AFMT_S16_BE; 2459 s->prop_adc.fmt_original = s->prop_adc.fmt; 2460 s->prop_adc.channels = 2; 2461 s->prop_adc.rate = 48000; 2462 s->conversion = 0; 2463 s->ena &= ~FMODE_READ; 2464 s->dma_adc.ossfragshift = s->dma_adc.ossmaxfrags = 2465 s->dma_adc.subdivision = 0; 2466 mutex_unlock(&s->open_sem_adc); 2467 2468 if (prog_dmabuf_adc(s)) { 2469 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR 2470 "cs4297a: adc Program dmabufs failed.\n")); 2471 cs4297a_release(inode, file); 2472 return -ENOMEM; 2473 } 2474 } 2475 if (file->f_mode & FMODE_WRITE) { 2476 s->prop_dac.fmt = AFMT_S16_BE; 2477 s->prop_dac.fmt_original = s->prop_dac.fmt; 2478 s->prop_dac.channels = 2; 2479 s->prop_dac.rate = 48000; 2480 s->conversion = 0; 2481 s->ena &= ~FMODE_WRITE; 2482 s->dma_dac.ossfragshift = s->dma_dac.ossmaxfrags = 2483 s->dma_dac.subdivision = 0; 2484 mutex_unlock(&s->open_sem_dac); 2485 2486 if (prog_dmabuf_dac(s)) { 2487 CS_DBGOUT(CS_OPEN | CS_ERROR, 2, printk(KERN_ERR 2488 "cs4297a: dac Program dmabufs failed.\n")); 2489 cs4297a_release(inode, file); 2490 return -ENOMEM; 2491 } 2492 } 2493 CS_DBGOUT(CS_FUNCTION | CS_OPEN, 2, 2494 printk(KERN_INFO "cs4297a: cs4297a_open()- 0\n")); 2495 return nonseekable_open(inode, file); 2496} 2497 2498static int cs4297a_open(struct inode *inode, struct file *file) 2499{ 2500 int ret; 2501 2502 lock_kernel(); 2503 ret = cs4297a_open(inode, file); 2504 unlock_kernel(); 2505 2506 return ret; 2507} 2508 2509// ****************************************************************************************** 2510// Wave (audio) file operations struct. 2511// ****************************************************************************************** 2512static const struct file_operations cs4297a_audio_fops = { 2513 .owner = THIS_MODULE, 2514 .llseek = no_llseek, 2515 .read = cs4297a_read, 2516 .write = cs4297a_write, 2517 .poll = cs4297a_poll, 2518 .unlocked_ioctl = cs4297a_unlocked_ioctl, 2519 .mmap = cs4297a_mmap, 2520 .open = cs4297a_open, 2521 .release = cs4297a_release, 2522}; 2523 2524static void cs4297a_interrupt(int irq, void *dev_id) 2525{ 2526 struct cs4297a_state *s = (struct cs4297a_state *) dev_id; 2527 u32 status; 2528 2529 status = __raw_readq(SS_CSR(R_SER_STATUS_DEBUG)); 2530 2531 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO 2532 "cs4297a: cs4297a_interrupt() HISR=0x%.8x\n", status)); 2533 2534 2535 if (status & M_SYNCSER_RX_SYNC_ERR) { 2536 status = __raw_readq(SS_CSR(R_SER_STATUS)); 2537 printk(KERN_ERR "cs4297a: rx sync error (status %08x)\n", status); 2538 return; 2539 } 2540 2541 if (status & M_SYNCSER_RX_OVERRUN) { 2542 int newptr, i; 2543 s->stats.rx_ovrrn++; 2544 printk(KERN_ERR "cs4297a: receive FIFO overrun\n"); 2545 2546 /* Fix things up: get the receive descriptor pool 2547 clean and give them back to the hardware */ 2548 while (__raw_readq(SS_CSR(R_SER_DMA_DSCR_COUNT_RX))) 2549 ; 2550 newptr = (unsigned) (((__raw_readq(SS_CSR(R_SER_DMA_CUR_DSCR_ADDR_RX)) & M_DMA_CURDSCR_ADDR) - 2551 s->dma_adc.descrtab_phys) / sizeof(serdma_descr_t)); 2552 for (i=0; i<DMA_DESCR; i++) { 2553 s->dma_adc.descrtab[i].descr_a &= ~M_DMA_SERRX_SOP; 2554 } 2555 s->dma_adc.swptr = s->dma_adc.hwptr = newptr; 2556 s->dma_adc.count = 0; 2557 s->dma_adc.sb_swptr = s->dma_adc.sb_hwptr = s->dma_adc.sample_buf; 2558 __raw_writeq(DMA_DESCR, SS_CSR(R_SER_DMA_DSCR_COUNT_RX)); 2559 } 2560 2561 spin_lock(&s->lock); 2562 cs4297a_update_ptr(s,CS_TRUE); 2563 spin_unlock(&s->lock); 2564 2565 CS_DBGOUT(CS_INTERRUPT, 6, printk(KERN_INFO 2566 "cs4297a: cs4297a_interrupt()-\n")); 2567} 2568 2569 2570static int __init cs4297a_init(void) 2571{ 2572 struct cs4297a_state *s; 2573 u32 pwr, id; 2574 mm_segment_t fs; 2575 int rval; 2576#ifndef CONFIG_BCM_CS4297A_CSWARM 2577 u64 cfg; 2578 int mdio_val; 2579#endif 2580 2581 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, printk(KERN_INFO 2582 "cs4297a: cs4297a_init_module()+ \n")); 2583 2584#ifndef CONFIG_BCM_CS4297A_CSWARM 2585 mdio_val = __raw_readq(KSEG1 + A_MAC_REGISTER(2, R_MAC_MDIO)) & 2586 (M_MAC_MDIO_DIR|M_MAC_MDIO_OUT); 2587 2588 /* Check syscfg for synchronous serial on port 1 */ 2589 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG); 2590 if (!(cfg & M_SYS_SER1_ENABLE)) { 2591 __raw_writeq(cfg | M_SYS_SER1_ENABLE, KSEG1+A_SCD_SYSTEM_CFG); 2592 cfg = __raw_readq(KSEG1 + A_SCD_SYSTEM_CFG); 2593 if (!(cfg & M_SYS_SER1_ENABLE)) { 2594 printk(KERN_INFO "cs4297a: serial port 1 not configured for synchronous operation\n"); 2595 return -1; 2596 } 2597 2598 printk(KERN_INFO "cs4297a: serial port 1 switching to synchronous operation\n"); 2599 2600 /* Force the codec (on SWARM) to reset by clearing 2601 GENO, preserving MDIO (no effect on CSWARM) */ 2602 __raw_writeq(mdio_val, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO)); 2603 udelay(10); 2604 } 2605 2606 /* Now set GENO */ 2607 __raw_writeq(mdio_val | M_MAC_GENC, KSEG1+A_MAC_REGISTER(2, R_MAC_MDIO)); 2608 /* Give the codec some time to finish resetting (start the bit clock) */ 2609 udelay(100); 2610#endif 2611 2612 if (!(s = kzalloc(sizeof(struct cs4297a_state), GFP_KERNEL))) { 2613 CS_DBGOUT(CS_ERROR, 1, printk(KERN_ERR 2614 "cs4297a: probe() no memory for state struct.\n")); 2615 return -1; 2616 } 2617 s->magic = CS4297a_MAGIC; 2618 init_waitqueue_head(&s->dma_adc.wait); 2619 init_waitqueue_head(&s->dma_dac.wait); 2620 init_waitqueue_head(&s->dma_adc.reg_wait); 2621 init_waitqueue_head(&s->dma_dac.reg_wait); 2622 init_waitqueue_head(&s->open_wait); 2623 init_waitqueue_head(&s->open_wait_adc); 2624 init_waitqueue_head(&s->open_wait_dac); 2625 mutex_init(&s->open_sem_adc); 2626 mutex_init(&s->open_sem_dac); 2627 spin_lock_init(&s->lock); 2628 2629 s->irq = K_INT_SER_1; 2630 2631 if (request_irq 2632 (s->irq, cs4297a_interrupt, 0, "Crystal CS4297a", s)) { 2633 CS_DBGOUT(CS_INIT | CS_ERROR, 1, 2634 printk(KERN_ERR "cs4297a: irq %u in use\n", s->irq)); 2635 goto err_irq; 2636 } 2637 if ((s->dev_audio = register_sound_dsp(&cs4297a_audio_fops, -1)) < 2638 0) { 2639 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR 2640 "cs4297a: probe() register_sound_dsp() failed.\n")); 2641 goto err_dev1; 2642 } 2643 if ((s->dev_mixer = register_sound_mixer(&cs4297a_mixer_fops, -1)) < 2644 0) { 2645 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR 2646 "cs4297a: probe() register_sound_mixer() failed.\n")); 2647 goto err_dev2; 2648 } 2649 2650 if (ser_init(s) || dma_init(s)) { 2651 CS_DBGOUT(CS_INIT | CS_ERROR, 1, printk(KERN_ERR 2652 "cs4297a: ser_init failed.\n")); 2653 goto err_dev3; 2654 } 2655 2656 do { 2657 udelay(4000); 2658 rval = cs4297a_read_ac97(s, AC97_POWER_CONTROL, &pwr); 2659 } while (!rval && (pwr != 0xf)); 2660 2661 if (!rval) { 2662 char *sb1250_duart_present; 2663 2664 fs = get_fs(); 2665 set_fs(KERNEL_DS); 2666 // cs4297a_write_ac97(s, 0x5e, 0x180); 2667 cs4297a_write_ac97(s, 0x02, 0x0808); 2668 cs4297a_write_ac97(s, 0x18, 0x0808); 2669 set_fs(fs); 2670 2671 list_add(&s->list, &cs4297a_devs); 2672 2673 cs4297a_read_ac97(s, AC97_VENDOR_ID1, &id); 2674 2675 sb1250_duart_present = symbol_get(sb1250_duart_present); 2676 if (sb1250_duart_present) 2677 sb1250_duart_present[1] = 0; 2678 2679 printk(KERN_INFO "cs4297a: initialized (vendor id = %x)\n", id); 2680 2681 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, 2682 printk(KERN_INFO "cs4297a: cs4297a_init_module()-\n")); 2683 2684 return 0; 2685 } 2686 2687 err_dev3: 2688 unregister_sound_mixer(s->dev_mixer); 2689 err_dev2: 2690 unregister_sound_dsp(s->dev_audio); 2691 err_dev1: 2692 free_irq(s->irq, s); 2693 err_irq: 2694 kfree(s); 2695 2696 printk(KERN_INFO "cs4297a: initialization failed\n"); 2697 2698 return -1; 2699} 2700 2701static void __exit cs4297a_cleanup(void) 2702{ 2703 /* 2704 XXXKW 2705 disable_irq, free_irq 2706 drain DMA queue 2707 disable DMA 2708 disable TX/RX 2709 free memory 2710 */ 2711 CS_DBGOUT(CS_INIT | CS_FUNCTION, 2, 2712 printk(KERN_INFO "cs4297a: cleanup_cs4297a() finished\n")); 2713} 2714 2715// --------------------------------------------------------------------- 2716 2717MODULE_AUTHOR("Kip Walker, Broadcom Corp."); 2718MODULE_DESCRIPTION("Cirrus Logic CS4297a Driver for Broadcom SWARM board"); 2719 2720// --------------------------------------------------------------------- 2721 2722module_init(cs4297a_init); 2723module_exit(cs4297a_cleanup); 2724