1/* 2 * intelfb 3 * 4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips. 5 * 6 * Copyright �� 2002, 2003 David Dawes <dawes@xfree86.org> 7 * 2004 Sylvain Meyer 8 * 9 * This driver consists of two parts. The first part (intelfbdrv.c) provides 10 * the basic fbdev interfaces, is derived in part from the radeonfb and 11 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c) 12 * provides the code to program the hardware. Most of it is derived from 13 * the i810/i830 XFree86 driver. The HW-specific code is covered here 14 * under a dual license (GPL and MIT/XFree86 license). 15 * 16 * Author: David Dawes 17 * 18 */ 19 20/* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */ 21 22#include <linux/module.h> 23#include <linux/kernel.h> 24#include <linux/errno.h> 25#include <linux/string.h> 26#include <linux/mm.h> 27#include <linux/delay.h> 28#include <linux/fb.h> 29#include <linux/ioport.h> 30#include <linux/init.h> 31#include <linux/pci.h> 32#include <linux/vmalloc.h> 33#include <linux/pagemap.h> 34#include <linux/interrupt.h> 35 36#include <asm/io.h> 37 38#include "intelfb.h" 39#include "intelfbhw.h" 40 41struct pll_min_max { 42 int min_m, max_m, min_m1, max_m1; 43 int min_m2, max_m2, min_n, max_n; 44 int min_p, max_p, min_p1, max_p1; 45 int min_vco, max_vco, p_transition_clk, ref_clk; 46 int p_inc_lo, p_inc_hi; 47}; 48 49#define PLLS_I8xx 0 50#define PLLS_I9xx 1 51#define PLLS_MAX 2 52 53static struct pll_min_max plls[PLLS_MAX] = { 54 { 108, 140, 18, 26, 55 6, 16, 3, 16, 56 4, 128, 0, 31, 57 930000, 1400000, 165000, 48000, 58 4, 2 }, /* I8xx */ 59 60 { 75, 120, 10, 20, 61 5, 9, 4, 7, 62 5, 80, 1, 8, 63 1400000, 2800000, 200000, 96000, 64 10, 5 } /* I9xx */ 65}; 66 67int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo) 68{ 69 u32 tmp; 70 if (!pdev || !dinfo) 71 return 1; 72 73 switch (pdev->device) { 74 case PCI_DEVICE_ID_INTEL_830M: 75 dinfo->name = "Intel(R) 830M"; 76 dinfo->chipset = INTEL_830M; 77 dinfo->mobile = 1; 78 dinfo->pll_index = PLLS_I8xx; 79 return 0; 80 case PCI_DEVICE_ID_INTEL_845G: 81 dinfo->name = "Intel(R) 845G"; 82 dinfo->chipset = INTEL_845G; 83 dinfo->mobile = 0; 84 dinfo->pll_index = PLLS_I8xx; 85 return 0; 86 case PCI_DEVICE_ID_INTEL_854: 87 dinfo->mobile = 1; 88 dinfo->name = "Intel(R) 854"; 89 dinfo->chipset = INTEL_854; 90 return 0; 91 case PCI_DEVICE_ID_INTEL_85XGM: 92 tmp = 0; 93 dinfo->mobile = 1; 94 dinfo->pll_index = PLLS_I8xx; 95 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp); 96 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) & 97 INTEL_85X_VARIANT_MASK) { 98 case INTEL_VAR_855GME: 99 dinfo->name = "Intel(R) 855GME"; 100 dinfo->chipset = INTEL_855GME; 101 return 0; 102 case INTEL_VAR_855GM: 103 dinfo->name = "Intel(R) 855GM"; 104 dinfo->chipset = INTEL_855GM; 105 return 0; 106 case INTEL_VAR_852GME: 107 dinfo->name = "Intel(R) 852GME"; 108 dinfo->chipset = INTEL_852GME; 109 return 0; 110 case INTEL_VAR_852GM: 111 dinfo->name = "Intel(R) 852GM"; 112 dinfo->chipset = INTEL_852GM; 113 return 0; 114 default: 115 dinfo->name = "Intel(R) 852GM/855GM"; 116 dinfo->chipset = INTEL_85XGM; 117 return 0; 118 } 119 break; 120 case PCI_DEVICE_ID_INTEL_865G: 121 dinfo->name = "Intel(R) 865G"; 122 dinfo->chipset = INTEL_865G; 123 dinfo->mobile = 0; 124 dinfo->pll_index = PLLS_I8xx; 125 return 0; 126 case PCI_DEVICE_ID_INTEL_915G: 127 dinfo->name = "Intel(R) 915G"; 128 dinfo->chipset = INTEL_915G; 129 dinfo->mobile = 0; 130 dinfo->pll_index = PLLS_I9xx; 131 return 0; 132 case PCI_DEVICE_ID_INTEL_915GM: 133 dinfo->name = "Intel(R) 915GM"; 134 dinfo->chipset = INTEL_915GM; 135 dinfo->mobile = 1; 136 dinfo->pll_index = PLLS_I9xx; 137 return 0; 138 case PCI_DEVICE_ID_INTEL_945G: 139 dinfo->name = "Intel(R) 945G"; 140 dinfo->chipset = INTEL_945G; 141 dinfo->mobile = 0; 142 dinfo->pll_index = PLLS_I9xx; 143 return 0; 144 case PCI_DEVICE_ID_INTEL_945GM: 145 dinfo->name = "Intel(R) 945GM"; 146 dinfo->chipset = INTEL_945GM; 147 dinfo->mobile = 1; 148 dinfo->pll_index = PLLS_I9xx; 149 return 0; 150 case PCI_DEVICE_ID_INTEL_945GME: 151 dinfo->name = "Intel(R) 945GME"; 152 dinfo->chipset = INTEL_945GME; 153 dinfo->mobile = 1; 154 dinfo->pll_index = PLLS_I9xx; 155 return 0; 156 case PCI_DEVICE_ID_INTEL_965G: 157 dinfo->name = "Intel(R) 965G"; 158 dinfo->chipset = INTEL_965G; 159 dinfo->mobile = 0; 160 dinfo->pll_index = PLLS_I9xx; 161 return 0; 162 case PCI_DEVICE_ID_INTEL_965GM: 163 dinfo->name = "Intel(R) 965GM"; 164 dinfo->chipset = INTEL_965GM; 165 dinfo->mobile = 1; 166 dinfo->pll_index = PLLS_I9xx; 167 return 0; 168 default: 169 return 1; 170 } 171} 172 173int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size, 174 int *stolen_size) 175{ 176 struct pci_dev *bridge_dev; 177 u16 tmp; 178 int stolen_overhead; 179 180 if (!pdev || !aperture_size || !stolen_size) 181 return 1; 182 183 /* Find the bridge device. It is always 0:0.0 */ 184 if (!(bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)))) { 185 ERR_MSG("cannot find bridge device\n"); 186 return 1; 187 } 188 189 /* Get the fb aperture size and "stolen" memory amount. */ 190 tmp = 0; 191 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp); 192 pci_dev_put(bridge_dev); 193 194 switch (pdev->device) { 195 case PCI_DEVICE_ID_INTEL_915G: 196 case PCI_DEVICE_ID_INTEL_915GM: 197 case PCI_DEVICE_ID_INTEL_945G: 198 case PCI_DEVICE_ID_INTEL_945GM: 199 case PCI_DEVICE_ID_INTEL_945GME: 200 case PCI_DEVICE_ID_INTEL_965G: 201 case PCI_DEVICE_ID_INTEL_965GM: 202 /* 915, 945 and 965 chipsets support a 256MB aperture. 203 Aperture size is determined by inspected the 204 base address of the aperture. */ 205 if (pci_resource_start(pdev, 2) & 0x08000000) 206 *aperture_size = MB(128); 207 else 208 *aperture_size = MB(256); 209 break; 210 default: 211 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M) 212 *aperture_size = MB(64); 213 else 214 *aperture_size = MB(128); 215 break; 216 } 217 218 /* Stolen memory size is reduced by the GTT and the popup. 219 GTT is 1K per MB of aperture size, and popup is 4K. */ 220 stolen_overhead = (*aperture_size / MB(1)) + 4; 221 switch(pdev->device) { 222 case PCI_DEVICE_ID_INTEL_830M: 223 case PCI_DEVICE_ID_INTEL_845G: 224 switch (tmp & INTEL_830_GMCH_GMS_MASK) { 225 case INTEL_830_GMCH_GMS_STOLEN_512: 226 *stolen_size = KB(512) - KB(stolen_overhead); 227 return 0; 228 case INTEL_830_GMCH_GMS_STOLEN_1024: 229 *stolen_size = MB(1) - KB(stolen_overhead); 230 return 0; 231 case INTEL_830_GMCH_GMS_STOLEN_8192: 232 *stolen_size = MB(8) - KB(stolen_overhead); 233 return 0; 234 case INTEL_830_GMCH_GMS_LOCAL: 235 ERR_MSG("only local memory found\n"); 236 return 1; 237 case INTEL_830_GMCH_GMS_DISABLED: 238 ERR_MSG("video memory is disabled\n"); 239 return 1; 240 default: 241 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n", 242 tmp & INTEL_830_GMCH_GMS_MASK); 243 return 1; 244 } 245 break; 246 default: 247 switch (tmp & INTEL_855_GMCH_GMS_MASK) { 248 case INTEL_855_GMCH_GMS_STOLEN_1M: 249 *stolen_size = MB(1) - KB(stolen_overhead); 250 return 0; 251 case INTEL_855_GMCH_GMS_STOLEN_4M: 252 *stolen_size = MB(4) - KB(stolen_overhead); 253 return 0; 254 case INTEL_855_GMCH_GMS_STOLEN_8M: 255 *stolen_size = MB(8) - KB(stolen_overhead); 256 return 0; 257 case INTEL_855_GMCH_GMS_STOLEN_16M: 258 *stolen_size = MB(16) - KB(stolen_overhead); 259 return 0; 260 case INTEL_855_GMCH_GMS_STOLEN_32M: 261 *stolen_size = MB(32) - KB(stolen_overhead); 262 return 0; 263 case INTEL_915G_GMCH_GMS_STOLEN_48M: 264 *stolen_size = MB(48) - KB(stolen_overhead); 265 return 0; 266 case INTEL_915G_GMCH_GMS_STOLEN_64M: 267 *stolen_size = MB(64) - KB(stolen_overhead); 268 return 0; 269 case INTEL_855_GMCH_GMS_DISABLED: 270 ERR_MSG("video memory is disabled\n"); 271 return 0; 272 default: 273 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n", 274 tmp & INTEL_855_GMCH_GMS_MASK); 275 return 1; 276 } 277 } 278} 279 280int intelfbhw_check_non_crt(struct intelfb_info *dinfo) 281{ 282 int dvo = 0; 283 284 if (INREG(LVDS) & PORT_ENABLE) 285 dvo |= LVDS_PORT; 286 if (INREG(DVOA) & PORT_ENABLE) 287 dvo |= DVOA_PORT; 288 if (INREG(DVOB) & PORT_ENABLE) 289 dvo |= DVOB_PORT; 290 if (INREG(DVOC) & PORT_ENABLE) 291 dvo |= DVOC_PORT; 292 293 return dvo; 294} 295 296const char * intelfbhw_dvo_to_string(int dvo) 297{ 298 if (dvo & DVOA_PORT) 299 return "DVO port A"; 300 else if (dvo & DVOB_PORT) 301 return "DVO port B"; 302 else if (dvo & DVOC_PORT) 303 return "DVO port C"; 304 else if (dvo & LVDS_PORT) 305 return "LVDS port"; 306 else 307 return NULL; 308} 309 310 311int intelfbhw_validate_mode(struct intelfb_info *dinfo, 312 struct fb_var_screeninfo *var) 313{ 314 int bytes_per_pixel; 315 int tmp; 316 317#if VERBOSE > 0 318 DBG_MSG("intelfbhw_validate_mode\n"); 319#endif 320 321 bytes_per_pixel = var->bits_per_pixel / 8; 322 if (bytes_per_pixel == 3) 323 bytes_per_pixel = 4; 324 325 /* Check if enough video memory. */ 326 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel; 327 if (tmp > dinfo->fb.size) { 328 WRN_MSG("Not enough video ram for mode " 329 "(%d KByte vs %d KByte).\n", 330 BtoKB(tmp), BtoKB(dinfo->fb.size)); 331 return 1; 332 } 333 334 /* Check if x/y limits are OK. */ 335 if (var->xres - 1 > HACTIVE_MASK) { 336 WRN_MSG("X resolution too large (%d vs %d).\n", 337 var->xres, HACTIVE_MASK + 1); 338 return 1; 339 } 340 if (var->yres - 1 > VACTIVE_MASK) { 341 WRN_MSG("Y resolution too large (%d vs %d).\n", 342 var->yres, VACTIVE_MASK + 1); 343 return 1; 344 } 345 if (var->xres < 4) { 346 WRN_MSG("X resolution too small (%d vs 4).\n", var->xres); 347 return 1; 348 } 349 if (var->yres < 4) { 350 WRN_MSG("Y resolution too small (%d vs 4).\n", var->yres); 351 return 1; 352 } 353 354 /* Check for doublescan modes. */ 355 if (var->vmode & FB_VMODE_DOUBLE) { 356 WRN_MSG("Mode is double-scan.\n"); 357 return 1; 358 } 359 360 if ((var->vmode & FB_VMODE_INTERLACED) && (var->yres & 1)) { 361 WRN_MSG("Odd number of lines in interlaced mode\n"); 362 return 1; 363 } 364 365 /* Check if clock is OK. */ 366 tmp = 1000000000 / var->pixclock; 367 if (tmp < MIN_CLOCK) { 368 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n", 369 (tmp + 500) / 1000, MIN_CLOCK / 1000); 370 return 1; 371 } 372 if (tmp > MAX_CLOCK) { 373 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n", 374 (tmp + 500) / 1000, MAX_CLOCK / 1000); 375 return 1; 376 } 377 378 return 0; 379} 380 381int intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info) 382{ 383 struct intelfb_info *dinfo = GET_DINFO(info); 384 u32 offset, xoffset, yoffset; 385 386#if VERBOSE > 0 387 DBG_MSG("intelfbhw_pan_display\n"); 388#endif 389 390 xoffset = ROUND_DOWN_TO(var->xoffset, 8); 391 yoffset = var->yoffset; 392 393 if ((xoffset + var->xres > var->xres_virtual) || 394 (yoffset + var->yres > var->yres_virtual)) 395 return -EINVAL; 396 397 offset = (yoffset * dinfo->pitch) + 398 (xoffset * var->bits_per_pixel) / 8; 399 400 offset += dinfo->fb.offset << 12; 401 402 dinfo->vsync.pan_offset = offset; 403 if ((var->activate & FB_ACTIVATE_VBL) && 404 !intelfbhw_enable_irq(dinfo)) 405 dinfo->vsync.pan_display = 1; 406 else { 407 dinfo->vsync.pan_display = 0; 408 OUTREG(DSPABASE, offset); 409 } 410 411 return 0; 412} 413 414/* Blank the screen. */ 415void intelfbhw_do_blank(int blank, struct fb_info *info) 416{ 417 struct intelfb_info *dinfo = GET_DINFO(info); 418 u32 tmp; 419 420#if VERBOSE > 0 421 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank); 422#endif 423 424 /* Turn plane A on or off */ 425 tmp = INREG(DSPACNTR); 426 if (blank) 427 tmp &= ~DISPPLANE_PLANE_ENABLE; 428 else 429 tmp |= DISPPLANE_PLANE_ENABLE; 430 OUTREG(DSPACNTR, tmp); 431 /* Flush */ 432 tmp = INREG(DSPABASE); 433 OUTREG(DSPABASE, tmp); 434 435 /* Turn off/on the HW cursor */ 436#if VERBOSE > 0 437 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on); 438#endif 439 if (dinfo->cursor_on) { 440 if (blank) 441 intelfbhw_cursor_hide(dinfo); 442 else 443 intelfbhw_cursor_show(dinfo); 444 dinfo->cursor_on = 1; 445 } 446 dinfo->cursor_blanked = blank; 447 448 /* Set DPMS level */ 449 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK; 450 switch (blank) { 451 case FB_BLANK_UNBLANK: 452 case FB_BLANK_NORMAL: 453 tmp |= ADPA_DPMS_D0; 454 break; 455 case FB_BLANK_VSYNC_SUSPEND: 456 tmp |= ADPA_DPMS_D1; 457 break; 458 case FB_BLANK_HSYNC_SUSPEND: 459 tmp |= ADPA_DPMS_D2; 460 break; 461 case FB_BLANK_POWERDOWN: 462 tmp |= ADPA_DPMS_D3; 463 break; 464 } 465 OUTREG(ADPA, tmp); 466 467 return; 468} 469 470 471/* Check which pipe is connected to an active display plane. */ 472int intelfbhw_active_pipe(const struct intelfb_hwstate *hw) 473{ 474 int pipe = -1; 475 476 /* keep old default behaviour - prefer PIPE_A */ 477 if (hw->disp_b_ctrl & DISPPLANE_PLANE_ENABLE) { 478 pipe = (hw->disp_b_ctrl >> DISPPLANE_SEL_PIPE_SHIFT); 479 pipe &= PIPE_MASK; 480 if (unlikely(pipe == PIPE_A)) 481 return PIPE_A; 482 } 483 if (hw->disp_a_ctrl & DISPPLANE_PLANE_ENABLE) { 484 pipe = (hw->disp_a_ctrl >> DISPPLANE_SEL_PIPE_SHIFT); 485 pipe &= PIPE_MASK; 486 if (likely(pipe == PIPE_A)) 487 return PIPE_A; 488 } 489 /* Impossible that no pipe is selected - return PIPE_A */ 490 WARN_ON(pipe == -1); 491 if (unlikely(pipe == -1)) 492 pipe = PIPE_A; 493 494 return pipe; 495} 496 497void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno, 498 unsigned red, unsigned green, unsigned blue, 499 unsigned transp) 500{ 501 u32 palette_reg = (dinfo->pipe == PIPE_A) ? 502 PALETTE_A : PALETTE_B; 503 504#if VERBOSE > 0 505 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n", 506 regno, red, green, blue); 507#endif 508 509 OUTREG(palette_reg + (regno << 2), 510 (red << PALETTE_8_RED_SHIFT) | 511 (green << PALETTE_8_GREEN_SHIFT) | 512 (blue << PALETTE_8_BLUE_SHIFT)); 513} 514 515 516int intelfbhw_read_hw_state(struct intelfb_info *dinfo, 517 struct intelfb_hwstate *hw, int flag) 518{ 519 int i; 520 521#if VERBOSE > 0 522 DBG_MSG("intelfbhw_read_hw_state\n"); 523#endif 524 525 if (!hw || !dinfo) 526 return -1; 527 528 /* Read in as much of the HW state as possible. */ 529 hw->vga0_divisor = INREG(VGA0_DIVISOR); 530 hw->vga1_divisor = INREG(VGA1_DIVISOR); 531 hw->vga_pd = INREG(VGAPD); 532 hw->dpll_a = INREG(DPLL_A); 533 hw->dpll_b = INREG(DPLL_B); 534 hw->fpa0 = INREG(FPA0); 535 hw->fpa1 = INREG(FPA1); 536 hw->fpb0 = INREG(FPB0); 537 hw->fpb1 = INREG(FPB1); 538 539 if (flag == 1) 540 return flag; 541 542 543 if (flag == 2) 544 return flag; 545 546 hw->htotal_a = INREG(HTOTAL_A); 547 hw->hblank_a = INREG(HBLANK_A); 548 hw->hsync_a = INREG(HSYNC_A); 549 hw->vtotal_a = INREG(VTOTAL_A); 550 hw->vblank_a = INREG(VBLANK_A); 551 hw->vsync_a = INREG(VSYNC_A); 552 hw->src_size_a = INREG(SRC_SIZE_A); 553 hw->bclrpat_a = INREG(BCLRPAT_A); 554 hw->htotal_b = INREG(HTOTAL_B); 555 hw->hblank_b = INREG(HBLANK_B); 556 hw->hsync_b = INREG(HSYNC_B); 557 hw->vtotal_b = INREG(VTOTAL_B); 558 hw->vblank_b = INREG(VBLANK_B); 559 hw->vsync_b = INREG(VSYNC_B); 560 hw->src_size_b = INREG(SRC_SIZE_B); 561 hw->bclrpat_b = INREG(BCLRPAT_B); 562 563 if (flag == 3) 564 return flag; 565 566 hw->adpa = INREG(ADPA); 567 hw->dvoa = INREG(DVOA); 568 hw->dvob = INREG(DVOB); 569 hw->dvoc = INREG(DVOC); 570 hw->dvoa_srcdim = INREG(DVOA_SRCDIM); 571 hw->dvob_srcdim = INREG(DVOB_SRCDIM); 572 hw->dvoc_srcdim = INREG(DVOC_SRCDIM); 573 hw->lvds = INREG(LVDS); 574 575 if (flag == 4) 576 return flag; 577 578 hw->pipe_a_conf = INREG(PIPEACONF); 579 hw->pipe_b_conf = INREG(PIPEBCONF); 580 hw->disp_arb = INREG(DISPARB); 581 582 if (flag == 5) 583 return flag; 584 585 hw->cursor_a_control = INREG(CURSOR_A_CONTROL); 586 hw->cursor_b_control = INREG(CURSOR_B_CONTROL); 587 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR); 588 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR); 589 590 if (flag == 6) 591 return flag; 592 593 for (i = 0; i < 4; i++) { 594 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2)); 595 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2)); 596 } 597 598 if (flag == 7) 599 return flag; 600 601 hw->cursor_size = INREG(CURSOR_SIZE); 602 603 if (flag == 8) 604 return flag; 605 606 hw->disp_a_ctrl = INREG(DSPACNTR); 607 hw->disp_b_ctrl = INREG(DSPBCNTR); 608 hw->disp_a_base = INREG(DSPABASE); 609 hw->disp_b_base = INREG(DSPBBASE); 610 hw->disp_a_stride = INREG(DSPASTRIDE); 611 hw->disp_b_stride = INREG(DSPBSTRIDE); 612 613 if (flag == 9) 614 return flag; 615 616 hw->vgacntrl = INREG(VGACNTRL); 617 618 if (flag == 10) 619 return flag; 620 621 hw->add_id = INREG(ADD_ID); 622 623 if (flag == 11) 624 return flag; 625 626 for (i = 0; i < 7; i++) { 627 hw->swf0x[i] = INREG(SWF00 + (i << 2)); 628 hw->swf1x[i] = INREG(SWF10 + (i << 2)); 629 if (i < 3) 630 hw->swf3x[i] = INREG(SWF30 + (i << 2)); 631 } 632 633 for (i = 0; i < 8; i++) 634 hw->fence[i] = INREG(FENCE + (i << 2)); 635 636 hw->instpm = INREG(INSTPM); 637 hw->mem_mode = INREG(MEM_MODE); 638 hw->fw_blc_0 = INREG(FW_BLC_0); 639 hw->fw_blc_1 = INREG(FW_BLC_1); 640 641 hw->hwstam = INREG16(HWSTAM); 642 hw->ier = INREG16(IER); 643 hw->iir = INREG16(IIR); 644 hw->imr = INREG16(IMR); 645 646 return 0; 647} 648 649 650static int calc_vclock3(int index, int m, int n, int p) 651{ 652 if (p == 0 || n == 0) 653 return 0; 654 return plls[index].ref_clk * m / n / p; 655} 656 657static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, 658 int lvds) 659{ 660 struct pll_min_max *pll = &plls[index]; 661 u32 m, vco, p; 662 663 m = (5 * (m1 + 2)) + (m2 + 2); 664 n += 2; 665 vco = pll->ref_clk * m / n; 666 667 if (index == PLLS_I8xx) 668 p = ((p1 + 2) * (1 << (p2 + 1))); 669 else 670 p = ((p1) * (p2 ? 5 : 10)); 671 return vco / p; 672} 673 674#if REGDUMP 675static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, 676 int *o_p1, int *o_p2) 677{ 678 int p1, p2; 679 680 if (IS_I9XX(dinfo)) { 681 if (dpll & DPLL_P1_FORCE_DIV2) 682 p1 = 1; 683 else 684 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff; 685 686 p1 = ffs(p1); 687 688 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK; 689 } else { 690 if (dpll & DPLL_P1_FORCE_DIV2) 691 p1 = 0; 692 else 693 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK; 694 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK; 695 } 696 697 *o_p1 = p1; 698 *o_p2 = p2; 699} 700#endif 701 702 703void intelfbhw_print_hw_state(struct intelfb_info *dinfo, 704 struct intelfb_hwstate *hw) 705{ 706#if REGDUMP 707 int i, m1, m2, n, p1, p2; 708 int index = dinfo->pll_index; 709 DBG_MSG("intelfbhw_print_hw_state\n"); 710 711 if (!hw) 712 return; 713 /* Read in as much of the HW state as possible. */ 714 printk("hw state dump start\n"); 715 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor); 716 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor); 717 printk(" VGAPD: 0x%08x\n", hw->vga_pd); 718 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 719 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 720 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 721 722 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2); 723 724 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", 725 m1, m2, n, p1, p2); 726 printk(" VGA0: clock is %d\n", 727 calc_vclock(index, m1, m2, n, p1, p2, 0)); 728 729 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 730 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 731 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 732 733 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2); 734 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", 735 m1, m2, n, p1, p2); 736 printk(" VGA1: clock is %d\n", 737 calc_vclock(index, m1, m2, n, p1, p2, 0)); 738 739 printk(" DPLL_A: 0x%08x\n", hw->dpll_a); 740 printk(" DPLL_B: 0x%08x\n", hw->dpll_b); 741 printk(" FPA0: 0x%08x\n", hw->fpa0); 742 printk(" FPA1: 0x%08x\n", hw->fpa1); 743 printk(" FPB0: 0x%08x\n", hw->fpb0); 744 printk(" FPB1: 0x%08x\n", hw->fpb1); 745 746 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 747 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 748 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 749 750 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2); 751 752 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", 753 m1, m2, n, p1, p2); 754 printk(" PLLA0: clock is %d\n", 755 calc_vclock(index, m1, m2, n, p1, p2, 0)); 756 757 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 758 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 759 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK; 760 761 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2); 762 763 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n", 764 m1, m2, n, p1, p2); 765 printk(" PLLA1: clock is %d\n", 766 calc_vclock(index, m1, m2, n, p1, p2, 0)); 767 768 769 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a); 770 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a); 771 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a); 772 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a); 773 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a); 774 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a); 775 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a); 776 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a); 777 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b); 778 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b); 779 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b); 780 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b); 781 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b); 782 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b); 783 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b); 784 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b); 785 786 printk(" ADPA: 0x%08x\n", hw->adpa); 787 printk(" DVOA: 0x%08x\n", hw->dvoa); 788 printk(" DVOB: 0x%08x\n", hw->dvob); 789 printk(" DVOC: 0x%08x\n", hw->dvoc); 790 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim); 791 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim); 792 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim); 793 printk(" LVDS: 0x%08x\n", hw->lvds); 794 795 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf); 796 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf); 797 printk(" DISPARB: 0x%08x\n", hw->disp_arb); 798 799 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control); 800 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control); 801 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base); 802 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base); 803 804 printk(" CURSOR_A_PALETTE: "); 805 for (i = 0; i < 4; i++) { 806 printk("0x%08x", hw->cursor_a_palette[i]); 807 if (i < 3) 808 printk(", "); 809 } 810 printk("\n"); 811 printk(" CURSOR_B_PALETTE: "); 812 for (i = 0; i < 4; i++) { 813 printk("0x%08x", hw->cursor_b_palette[i]); 814 if (i < 3) 815 printk(", "); 816 } 817 printk("\n"); 818 819 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size); 820 821 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl); 822 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl); 823 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base); 824 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base); 825 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride); 826 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride); 827 828 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl); 829 printk(" ADD_ID: 0x%08x\n", hw->add_id); 830 831 for (i = 0; i < 7; i++) { 832 printk(" SWF0%d 0x%08x\n", i, 833 hw->swf0x[i]); 834 } 835 for (i = 0; i < 7; i++) { 836 printk(" SWF1%d 0x%08x\n", i, 837 hw->swf1x[i]); 838 } 839 for (i = 0; i < 3; i++) { 840 printk(" SWF3%d 0x%08x\n", i, 841 hw->swf3x[i]); 842 } 843 for (i = 0; i < 8; i++) 844 printk(" FENCE%d 0x%08x\n", i, 845 hw->fence[i]); 846 847 printk(" INSTPM 0x%08x\n", hw->instpm); 848 printk(" MEM_MODE 0x%08x\n", hw->mem_mode); 849 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0); 850 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1); 851 852 printk(" HWSTAM 0x%04x\n", hw->hwstam); 853 printk(" IER 0x%04x\n", hw->ier); 854 printk(" IIR 0x%04x\n", hw->iir); 855 printk(" IMR 0x%04x\n", hw->imr); 856 printk("hw state dump end\n"); 857#endif 858} 859 860 861 862/* Split the M parameter into M1 and M2. */ 863static int splitm(int index, unsigned int m, unsigned int *retm1, 864 unsigned int *retm2) 865{ 866 int m1, m2; 867 int testm; 868 struct pll_min_max *pll = &plls[index]; 869 870 /* no point optimising too much - brute force m */ 871 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) { 872 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) { 873 testm = (5 * (m1 + 2)) + (m2 + 2); 874 if (testm == m) { 875 *retm1 = (unsigned int)m1; 876 *retm2 = (unsigned int)m2; 877 return 0; 878 } 879 } 880 } 881 return 1; 882} 883 884/* Split the P parameter into P1 and P2. */ 885static int splitp(int index, unsigned int p, unsigned int *retp1, 886 unsigned int *retp2) 887{ 888 int p1, p2; 889 struct pll_min_max *pll = &plls[index]; 890 891 if (index == PLLS_I9xx) { 892 p2 = (p % 10) ? 1 : 0; 893 894 p1 = p / (p2 ? 5 : 10); 895 896 *retp1 = (unsigned int)p1; 897 *retp2 = (unsigned int)p2; 898 return 0; 899 } 900 901 if (p % 4 == 0) 902 p2 = 1; 903 else 904 p2 = 0; 905 p1 = (p / (1 << (p2 + 1))) - 2; 906 if (p % 4 == 0 && p1 < pll->min_p1) { 907 p2 = 0; 908 p1 = (p / (1 << (p2 + 1))) - 2; 909 } 910 if (p1 < pll->min_p1 || p1 > pll->max_p1 || 911 (p1 + 2) * (1 << (p2 + 1)) != p) { 912 return 1; 913 } else { 914 *retp1 = (unsigned int)p1; 915 *retp2 = (unsigned int)p2; 916 return 0; 917 } 918} 919 920static int calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, 921 u32 *retn, u32 *retp1, u32 *retp2, u32 *retclock) 922{ 923 u32 m1, m2, n, p1, p2, n1, testm; 924 u32 f_vco, p, p_best = 0, m, f_out = 0; 925 u32 err_max, err_target, err_best = 10000000; 926 u32 n_best = 0, m_best = 0, f_best, f_err; 927 u32 p_min, p_max, p_inc, div_max; 928 struct pll_min_max *pll = &plls[index]; 929 930 /* Accept 0.5% difference, but aim for 0.1% */ 931 err_max = 5 * clock / 1000; 932 err_target = clock / 1000; 933 934 DBG_MSG("Clock is %d\n", clock); 935 936 div_max = pll->max_vco / clock; 937 938 p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi; 939 p_min = p_inc; 940 p_max = ROUND_DOWN_TO(div_max, p_inc); 941 if (p_min < pll->min_p) 942 p_min = pll->min_p; 943 if (p_max > pll->max_p) 944 p_max = pll->max_p; 945 946 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc); 947 948 p = p_min; 949 do { 950 if (splitp(index, p, &p1, &p2)) { 951 WRN_MSG("cannot split p = %d\n", p); 952 p += p_inc; 953 continue; 954 } 955 n = pll->min_n; 956 f_vco = clock * p; 957 958 do { 959 m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk; 960 if (m < pll->min_m) 961 m = pll->min_m + 1; 962 if (m > pll->max_m) 963 m = pll->max_m - 1; 964 for (testm = m - 1; testm <= m; testm++) { 965 f_out = calc_vclock3(index, testm, n, p); 966 if (splitm(index, testm, &m1, &m2)) { 967 WRN_MSG("cannot split m = %d\n", 968 testm); 969 continue; 970 } 971 if (clock > f_out) 972 f_err = clock - f_out; 973 else/* slightly bias the error for bigger clocks */ 974 f_err = f_out - clock + 1; 975 976 if (f_err < err_best) { 977 m_best = testm; 978 n_best = n; 979 p_best = p; 980 f_best = f_out; 981 err_best = f_err; 982 } 983 } 984 n++; 985 } while ((n <= pll->max_n) && (f_out >= clock)); 986 p += p_inc; 987 } while ((p <= p_max)); 988 989 if (!m_best) { 990 WRN_MSG("cannot find parameters for clock %d\n", clock); 991 return 1; 992 } 993 m = m_best; 994 n = n_best; 995 p = p_best; 996 splitm(index, m, &m1, &m2); 997 splitp(index, p, &p1, &p2); 998 n1 = n - 2; 999 1000 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), " 1001 "f: %d (%d), VCO: %d\n", 1002 m, m1, m2, n, n1, p, p1, p2, 1003 calc_vclock3(index, m, n, p), 1004 calc_vclock(index, m1, m2, n1, p1, p2, 0), 1005 calc_vclock3(index, m, n, p) * p); 1006 *retm1 = m1; 1007 *retm2 = m2; 1008 *retn = n1; 1009 *retp1 = p1; 1010 *retp2 = p2; 1011 *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0); 1012 1013 return 0; 1014} 1015 1016static __inline__ int check_overflow(u32 value, u32 limit, 1017 const char *description) 1018{ 1019 if (value > limit) { 1020 WRN_MSG("%s value %d exceeds limit %d\n", 1021 description, value, limit); 1022 return 1; 1023 } 1024 return 0; 1025} 1026 1027/* It is assumed that hw is filled in with the initial state information. */ 1028int intelfbhw_mode_to_hw(struct intelfb_info *dinfo, 1029 struct intelfb_hwstate *hw, 1030 struct fb_var_screeninfo *var) 1031{ 1032 int pipe = intelfbhw_active_pipe(hw); 1033 u32 *dpll, *fp0, *fp1; 1034 u32 m1, m2, n, p1, p2, clock_target, clock; 1035 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive; 1036 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive; 1037 u32 vsync_pol, hsync_pol; 1038 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf; 1039 u32 stride_alignment; 1040 1041 DBG_MSG("intelfbhw_mode_to_hw\n"); 1042 1043 /* Disable VGA */ 1044 hw->vgacntrl |= VGA_DISABLE; 1045 1046 /* Set which pipe's registers will be set. */ 1047 if (pipe == PIPE_B) { 1048 dpll = &hw->dpll_b; 1049 fp0 = &hw->fpb0; 1050 fp1 = &hw->fpb1; 1051 hs = &hw->hsync_b; 1052 hb = &hw->hblank_b; 1053 ht = &hw->htotal_b; 1054 vs = &hw->vsync_b; 1055 vb = &hw->vblank_b; 1056 vt = &hw->vtotal_b; 1057 ss = &hw->src_size_b; 1058 pipe_conf = &hw->pipe_b_conf; 1059 } else { 1060 dpll = &hw->dpll_a; 1061 fp0 = &hw->fpa0; 1062 fp1 = &hw->fpa1; 1063 hs = &hw->hsync_a; 1064 hb = &hw->hblank_a; 1065 ht = &hw->htotal_a; 1066 vs = &hw->vsync_a; 1067 vb = &hw->vblank_a; 1068 vt = &hw->vtotal_a; 1069 ss = &hw->src_size_a; 1070 pipe_conf = &hw->pipe_a_conf; 1071 } 1072 1073 /* Use ADPA register for sync control. */ 1074 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY; 1075 1076 /* sync polarity */ 1077 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ? 1078 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW; 1079 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ? 1080 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW; 1081 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) | 1082 (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT)); 1083 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) | 1084 (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT); 1085 1086 /* Connect correct pipe to the analog port DAC */ 1087 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT); 1088 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT); 1089 1090 /* Set DPMS state to D0 (on) */ 1091 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK; 1092 hw->adpa |= ADPA_DPMS_D0; 1093 1094 hw->adpa |= ADPA_DAC_ENABLE; 1095 1096 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE); 1097 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK); 1098 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0); 1099 1100 /* Desired clock in kHz */ 1101 clock_target = 1000000000 / var->pixclock; 1102 1103 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2, 1104 &n, &p1, &p2, &clock)) { 1105 WRN_MSG("calc_pll_params failed\n"); 1106 return 1; 1107 } 1108 1109 /* Check for overflow. */ 1110 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter")) 1111 return 1; 1112 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter")) 1113 return 1; 1114 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter")) 1115 return 1; 1116 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter")) 1117 return 1; 1118 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter")) 1119 return 1; 1120 1121 *dpll &= ~DPLL_P1_FORCE_DIV2; 1122 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) | 1123 (DPLL_P1_MASK << DPLL_P1_SHIFT)); 1124 1125 if (IS_I9XX(dinfo)) { 1126 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT); 1127 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT; 1128 } else 1129 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT); 1130 1131 *fp0 = (n << FP_N_DIVISOR_SHIFT) | 1132 (m1 << FP_M1_DIVISOR_SHIFT) | 1133 (m2 << FP_M2_DIVISOR_SHIFT); 1134 *fp1 = *fp0; 1135 1136 hw->dvob &= ~PORT_ENABLE; 1137 hw->dvoc &= ~PORT_ENABLE; 1138 1139 /* Use display plane A. */ 1140 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE; 1141 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE; 1142 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK; 1143 switch (intelfb_var_to_depth(var)) { 1144 case 8: 1145 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE; 1146 break; 1147 case 15: 1148 hw->disp_a_ctrl |= DISPPLANE_15_16BPP; 1149 break; 1150 case 16: 1151 hw->disp_a_ctrl |= DISPPLANE_16BPP; 1152 break; 1153 case 24: 1154 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA; 1155 break; 1156 } 1157 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT); 1158 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT); 1159 1160 /* Set CRTC registers. */ 1161 hactive = var->xres; 1162 hsync_start = hactive + var->right_margin; 1163 hsync_end = hsync_start + var->hsync_len; 1164 htotal = hsync_end + var->left_margin; 1165 hblank_start = hactive; 1166 hblank_end = htotal; 1167 1168 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n", 1169 hactive, hsync_start, hsync_end, htotal, hblank_start, 1170 hblank_end); 1171 1172 vactive = var->yres; 1173 if (var->vmode & FB_VMODE_INTERLACED) 1174 vactive--; /* the chip adds 2 halflines automatically */ 1175 vsync_start = vactive + var->lower_margin; 1176 vsync_end = vsync_start + var->vsync_len; 1177 vtotal = vsync_end + var->upper_margin; 1178 vblank_start = vactive; 1179 vblank_end = vtotal; 1180 vblank_end = vsync_end + 1; 1181 1182 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n", 1183 vactive, vsync_start, vsync_end, vtotal, vblank_start, 1184 vblank_end); 1185 1186 /* Adjust for register values, and check for overflow. */ 1187 hactive--; 1188 if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive")) 1189 return 1; 1190 hsync_start--; 1191 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start")) 1192 return 1; 1193 hsync_end--; 1194 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end")) 1195 return 1; 1196 htotal--; 1197 if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal")) 1198 return 1; 1199 hblank_start--; 1200 if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start")) 1201 return 1; 1202 hblank_end--; 1203 if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end")) 1204 return 1; 1205 1206 vactive--; 1207 if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive")) 1208 return 1; 1209 vsync_start--; 1210 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start")) 1211 return 1; 1212 vsync_end--; 1213 if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end")) 1214 return 1; 1215 vtotal--; 1216 if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal")) 1217 return 1; 1218 vblank_start--; 1219 if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start")) 1220 return 1; 1221 vblank_end--; 1222 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end")) 1223 return 1; 1224 1225 *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT); 1226 *hb = (hblank_start << HBLANKSTART_SHIFT) | 1227 (hblank_end << HSYNCEND_SHIFT); 1228 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT); 1229 1230 *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT); 1231 *vb = (vblank_start << VBLANKSTART_SHIFT) | 1232 (vblank_end << VSYNCEND_SHIFT); 1233 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT); 1234 *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) | 1235 (vactive << SRC_SIZE_VERT_SHIFT); 1236 1237 hw->disp_a_stride = dinfo->pitch; 1238 DBG_MSG("pitch is %d\n", hw->disp_a_stride); 1239 1240 hw->disp_a_base = hw->disp_a_stride * var->yoffset + 1241 var->xoffset * var->bits_per_pixel / 8; 1242 1243 hw->disp_a_base += dinfo->fb.offset << 12; 1244 1245 /* Check stride alignment. */ 1246 stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX : 1247 STRIDE_ALIGNMENT; 1248 if (hw->disp_a_stride % stride_alignment != 0) { 1249 WRN_MSG("display stride %d has bad alignment %d\n", 1250 hw->disp_a_stride, stride_alignment); 1251 return 1; 1252 } 1253 1254 /* Set the palette to 8-bit mode. */ 1255 *pipe_conf &= ~PIPECONF_GAMMA; 1256 1257 if (var->vmode & FB_VMODE_INTERLACED) 1258 *pipe_conf |= PIPECONF_INTERLACE_W_FIELD_INDICATION; 1259 else 1260 *pipe_conf &= ~PIPECONF_INTERLACE_MASK; 1261 1262 return 0; 1263} 1264 1265/* Program a (non-VGA) video mode. */ 1266int intelfbhw_program_mode(struct intelfb_info *dinfo, 1267 const struct intelfb_hwstate *hw, int blank) 1268{ 1269 u32 tmp; 1270 const u32 *dpll, *fp0, *fp1, *pipe_conf; 1271 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss; 1272 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg, pipe_stat_reg; 1273 u32 hsync_reg, htotal_reg, hblank_reg; 1274 u32 vsync_reg, vtotal_reg, vblank_reg; 1275 u32 src_size_reg; 1276 u32 count, tmp_val[3]; 1277 1278 /* Assume single pipe */ 1279 1280#if VERBOSE > 0 1281 DBG_MSG("intelfbhw_program_mode\n"); 1282#endif 1283 1284 /* Disable VGA */ 1285 tmp = INREG(VGACNTRL); 1286 tmp |= VGA_DISABLE; 1287 OUTREG(VGACNTRL, tmp); 1288 1289 dinfo->pipe = intelfbhw_active_pipe(hw); 1290 1291 if (dinfo->pipe == PIPE_B) { 1292 dpll = &hw->dpll_b; 1293 fp0 = &hw->fpb0; 1294 fp1 = &hw->fpb1; 1295 pipe_conf = &hw->pipe_b_conf; 1296 hs = &hw->hsync_b; 1297 hb = &hw->hblank_b; 1298 ht = &hw->htotal_b; 1299 vs = &hw->vsync_b; 1300 vb = &hw->vblank_b; 1301 vt = &hw->vtotal_b; 1302 ss = &hw->src_size_b; 1303 dpll_reg = DPLL_B; 1304 fp0_reg = FPB0; 1305 fp1_reg = FPB1; 1306 pipe_conf_reg = PIPEBCONF; 1307 pipe_stat_reg = PIPEBSTAT; 1308 hsync_reg = HSYNC_B; 1309 htotal_reg = HTOTAL_B; 1310 hblank_reg = HBLANK_B; 1311 vsync_reg = VSYNC_B; 1312 vtotal_reg = VTOTAL_B; 1313 vblank_reg = VBLANK_B; 1314 src_size_reg = SRC_SIZE_B; 1315 } else { 1316 dpll = &hw->dpll_a; 1317 fp0 = &hw->fpa0; 1318 fp1 = &hw->fpa1; 1319 pipe_conf = &hw->pipe_a_conf; 1320 hs = &hw->hsync_a; 1321 hb = &hw->hblank_a; 1322 ht = &hw->htotal_a; 1323 vs = &hw->vsync_a; 1324 vb = &hw->vblank_a; 1325 vt = &hw->vtotal_a; 1326 ss = &hw->src_size_a; 1327 dpll_reg = DPLL_A; 1328 fp0_reg = FPA0; 1329 fp1_reg = FPA1; 1330 pipe_conf_reg = PIPEACONF; 1331 pipe_stat_reg = PIPEASTAT; 1332 hsync_reg = HSYNC_A; 1333 htotal_reg = HTOTAL_A; 1334 hblank_reg = HBLANK_A; 1335 vsync_reg = VSYNC_A; 1336 vtotal_reg = VTOTAL_A; 1337 vblank_reg = VBLANK_A; 1338 src_size_reg = SRC_SIZE_A; 1339 } 1340 1341 /* turn off pipe */ 1342 tmp = INREG(pipe_conf_reg); 1343 tmp &= ~PIPECONF_ENABLE; 1344 OUTREG(pipe_conf_reg, tmp); 1345 1346 count = 0; 1347 do { 1348 tmp_val[count % 3] = INREG(PIPEA_DSL); 1349 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1] == tmp_val[2])) 1350 break; 1351 count++; 1352 udelay(1); 1353 if (count % 200 == 0) { 1354 tmp = INREG(pipe_conf_reg); 1355 tmp &= ~PIPECONF_ENABLE; 1356 OUTREG(pipe_conf_reg, tmp); 1357 } 1358 } while (count < 2000); 1359 1360 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE); 1361 1362 /* Disable planes A and B. */ 1363 tmp = INREG(DSPACNTR); 1364 tmp &= ~DISPPLANE_PLANE_ENABLE; 1365 OUTREG(DSPACNTR, tmp); 1366 tmp = INREG(DSPBCNTR); 1367 tmp &= ~DISPPLANE_PLANE_ENABLE; 1368 OUTREG(DSPBCNTR, tmp); 1369 1370 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */ 1371 mdelay(20); 1372 1373 OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE); 1374 OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE); 1375 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE); 1376 1377 /* Disable Sync */ 1378 tmp = INREG(ADPA); 1379 tmp &= ~ADPA_DPMS_CONTROL_MASK; 1380 tmp |= ADPA_DPMS_D3; 1381 OUTREG(ADPA, tmp); 1382 1383 /* do some funky magic - xyzzy */ 1384 OUTREG(0x61204, 0xabcd0000); 1385 1386 /* turn off PLL */ 1387 tmp = INREG(dpll_reg); 1388 tmp &= ~DPLL_VCO_ENABLE; 1389 OUTREG(dpll_reg, tmp); 1390 1391 /* Set PLL parameters */ 1392 OUTREG(fp0_reg, *fp0); 1393 OUTREG(fp1_reg, *fp1); 1394 1395 /* Enable PLL */ 1396 OUTREG(dpll_reg, *dpll); 1397 1398 /* Set DVOs B/C */ 1399 OUTREG(DVOB, hw->dvob); 1400 OUTREG(DVOC, hw->dvoc); 1401 1402 /* undo funky magic */ 1403 OUTREG(0x61204, 0x00000000); 1404 1405 /* Set ADPA */ 1406 OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE); 1407 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3); 1408 1409 /* Set pipe parameters */ 1410 OUTREG(hsync_reg, *hs); 1411 OUTREG(hblank_reg, *hb); 1412 OUTREG(htotal_reg, *ht); 1413 OUTREG(vsync_reg, *vs); 1414 OUTREG(vblank_reg, *vb); 1415 OUTREG(vtotal_reg, *vt); 1416 OUTREG(src_size_reg, *ss); 1417 1418 switch (dinfo->info->var.vmode & (FB_VMODE_INTERLACED | 1419 FB_VMODE_ODD_FLD_FIRST)) { 1420 case FB_VMODE_INTERLACED | FB_VMODE_ODD_FLD_FIRST: 1421 OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_ODD_EN); 1422 break; 1423 case FB_VMODE_INTERLACED: /* even lines first */ 1424 OUTREG(pipe_stat_reg, 0xFFFF | PIPESTAT_FLD_EVT_EVEN_EN); 1425 break; 1426 default: /* non-interlaced */ 1427 OUTREG(pipe_stat_reg, 0xFFFF); /* clear all status bits only */ 1428 } 1429 /* Enable pipe */ 1430 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE); 1431 1432 /* Enable sync */ 1433 tmp = INREG(ADPA); 1434 tmp &= ~ADPA_DPMS_CONTROL_MASK; 1435 tmp |= ADPA_DPMS_D0; 1436 OUTREG(ADPA, tmp); 1437 1438 /* setup display plane */ 1439 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) { 1440 /* 1441 * i830M errata: the display plane must be enabled 1442 * to allow writes to the other bits in the plane 1443 * control register. 1444 */ 1445 tmp = INREG(DSPACNTR); 1446 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) { 1447 tmp |= DISPPLANE_PLANE_ENABLE; 1448 OUTREG(DSPACNTR, tmp); 1449 OUTREG(DSPACNTR, 1450 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE); 1451 mdelay(1); 1452 } 1453 } 1454 1455 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE); 1456 OUTREG(DSPASTRIDE, hw->disp_a_stride); 1457 OUTREG(DSPABASE, hw->disp_a_base); 1458 1459 /* Enable plane */ 1460 if (!blank) { 1461 tmp = INREG(DSPACNTR); 1462 tmp |= DISPPLANE_PLANE_ENABLE; 1463 OUTREG(DSPACNTR, tmp); 1464 OUTREG(DSPABASE, hw->disp_a_base); 1465 } 1466 1467 return 0; 1468} 1469 1470/* forward declarations */ 1471static void refresh_ring(struct intelfb_info *dinfo); 1472static void reset_state(struct intelfb_info *dinfo); 1473static void do_flush(struct intelfb_info *dinfo); 1474 1475static u32 get_ring_space(struct intelfb_info *dinfo) 1476{ 1477 u32 ring_space; 1478 1479 if (dinfo->ring_tail >= dinfo->ring_head) 1480 ring_space = dinfo->ring.size - 1481 (dinfo->ring_tail - dinfo->ring_head); 1482 else 1483 ring_space = dinfo->ring_head - dinfo->ring_tail; 1484 1485 if (ring_space > RING_MIN_FREE) 1486 ring_space -= RING_MIN_FREE; 1487 else 1488 ring_space = 0; 1489 1490 return ring_space; 1491} 1492 1493static int wait_ring(struct intelfb_info *dinfo, int n) 1494{ 1495 int i = 0; 1496 unsigned long end; 1497 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; 1498 1499#if VERBOSE > 0 1500 DBG_MSG("wait_ring: %d\n", n); 1501#endif 1502 1503 end = jiffies + (HZ * 3); 1504 while (dinfo->ring_space < n) { 1505 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; 1506 dinfo->ring_space = get_ring_space(dinfo); 1507 1508 if (dinfo->ring_head != last_head) { 1509 end = jiffies + (HZ * 3); 1510 last_head = dinfo->ring_head; 1511 } 1512 i++; 1513 if (time_before(end, jiffies)) { 1514 if (!i) { 1515 /* Try again */ 1516 reset_state(dinfo); 1517 refresh_ring(dinfo); 1518 do_flush(dinfo); 1519 end = jiffies + (HZ * 3); 1520 i = 1; 1521 } else { 1522 WRN_MSG("ring buffer : space: %d wanted %d\n", 1523 dinfo->ring_space, n); 1524 WRN_MSG("lockup - turning off hardware " 1525 "acceleration\n"); 1526 dinfo->ring_lockup = 1; 1527 break; 1528 } 1529 } 1530 udelay(1); 1531 } 1532 return i; 1533} 1534 1535static void do_flush(struct intelfb_info *dinfo) 1536{ 1537 START_RING(2); 1538 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE); 1539 OUT_RING(MI_NOOP); 1540 ADVANCE_RING(); 1541} 1542 1543void intelfbhw_do_sync(struct intelfb_info *dinfo) 1544{ 1545#if VERBOSE > 0 1546 DBG_MSG("intelfbhw_do_sync\n"); 1547#endif 1548 1549 if (!dinfo->accel) 1550 return; 1551 1552 /* 1553 * Send a flush, then wait until the ring is empty. This is what 1554 * the XFree86 driver does, and actually it doesn't seem a lot worse 1555 * than the recommended method (both have problems). 1556 */ 1557 do_flush(dinfo); 1558 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE); 1559 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE; 1560} 1561 1562static void refresh_ring(struct intelfb_info *dinfo) 1563{ 1564#if VERBOSE > 0 1565 DBG_MSG("refresh_ring\n"); 1566#endif 1567 1568 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK; 1569 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK; 1570 dinfo->ring_space = get_ring_space(dinfo); 1571} 1572 1573static void reset_state(struct intelfb_info *dinfo) 1574{ 1575 int i; 1576 u32 tmp; 1577 1578#if VERBOSE > 0 1579 DBG_MSG("reset_state\n"); 1580#endif 1581 1582 for (i = 0; i < FENCE_NUM; i++) 1583 OUTREG(FENCE + (i << 2), 0); 1584 1585 /* Flush the ring buffer if it's enabled. */ 1586 tmp = INREG(PRI_RING_LENGTH); 1587 if (tmp & RING_ENABLE) { 1588#if VERBOSE > 0 1589 DBG_MSG("reset_state: ring was enabled\n"); 1590#endif 1591 refresh_ring(dinfo); 1592 intelfbhw_do_sync(dinfo); 1593 DO_RING_IDLE(); 1594 } 1595 1596 OUTREG(PRI_RING_LENGTH, 0); 1597 OUTREG(PRI_RING_HEAD, 0); 1598 OUTREG(PRI_RING_TAIL, 0); 1599 OUTREG(PRI_RING_START, 0); 1600} 1601 1602/* Stop the 2D engine, and turn off the ring buffer. */ 1603void intelfbhw_2d_stop(struct intelfb_info *dinfo) 1604{ 1605#if VERBOSE > 0 1606 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", 1607 dinfo->accel, dinfo->ring_active); 1608#endif 1609 1610 if (!dinfo->accel) 1611 return; 1612 1613 dinfo->ring_active = 0; 1614 reset_state(dinfo); 1615} 1616 1617/* 1618 * Enable the ring buffer, and initialise the 2D engine. 1619 * It is assumed that the graphics engine has been stopped by previously 1620 * calling intelfb_2d_stop(). 1621 */ 1622void intelfbhw_2d_start(struct intelfb_info *dinfo) 1623{ 1624#if VERBOSE > 0 1625 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n", 1626 dinfo->accel, dinfo->ring_active); 1627#endif 1628 1629 if (!dinfo->accel) 1630 return; 1631 1632 /* Initialise the primary ring buffer. */ 1633 OUTREG(PRI_RING_LENGTH, 0); 1634 OUTREG(PRI_RING_TAIL, 0); 1635 OUTREG(PRI_RING_HEAD, 0); 1636 1637 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK); 1638 OUTREG(PRI_RING_LENGTH, 1639 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) | 1640 RING_NO_REPORT | RING_ENABLE); 1641 refresh_ring(dinfo); 1642 dinfo->ring_active = 1; 1643} 1644 1645/* 2D fillrect (solid fill or invert) */ 1646void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, 1647 u32 h, u32 color, u32 pitch, u32 bpp, u32 rop) 1648{ 1649 u32 br00, br09, br13, br14, br16; 1650 1651#if VERBOSE > 0 1652 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, " 1653 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop); 1654#endif 1655 1656 br00 = COLOR_BLT_CMD; 1657 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8)); 1658 br13 = (rop << ROP_SHIFT) | pitch; 1659 br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT); 1660 br16 = color; 1661 1662 switch (bpp) { 1663 case 8: 1664 br13 |= COLOR_DEPTH_8; 1665 break; 1666 case 16: 1667 br13 |= COLOR_DEPTH_16; 1668 break; 1669 case 32: 1670 br13 |= COLOR_DEPTH_32; 1671 br00 |= WRITE_ALPHA | WRITE_RGB; 1672 break; 1673 } 1674 1675 START_RING(6); 1676 OUT_RING(br00); 1677 OUT_RING(br13); 1678 OUT_RING(br14); 1679 OUT_RING(br09); 1680 OUT_RING(br16); 1681 OUT_RING(MI_NOOP); 1682 ADVANCE_RING(); 1683 1684#if VERBOSE > 0 1685 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head, 1686 dinfo->ring_tail, dinfo->ring_space); 1687#endif 1688} 1689 1690void 1691intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury, 1692 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp) 1693{ 1694 u32 br00, br09, br11, br12, br13, br22, br23, br26; 1695 1696#if VERBOSE > 0 1697 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n", 1698 curx, cury, dstx, dsty, w, h, pitch, bpp); 1699#endif 1700 1701 br00 = XY_SRC_COPY_BLT_CMD; 1702 br09 = dinfo->fb_start; 1703 br11 = (pitch << PITCH_SHIFT); 1704 br12 = dinfo->fb_start; 1705 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT); 1706 br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT); 1707 br23 = ((dstx + w) << WIDTH_SHIFT) | 1708 ((dsty + h) << HEIGHT_SHIFT); 1709 br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT); 1710 1711 switch (bpp) { 1712 case 8: 1713 br13 |= COLOR_DEPTH_8; 1714 break; 1715 case 16: 1716 br13 |= COLOR_DEPTH_16; 1717 break; 1718 case 32: 1719 br13 |= COLOR_DEPTH_32; 1720 br00 |= WRITE_ALPHA | WRITE_RGB; 1721 break; 1722 } 1723 1724 START_RING(8); 1725 OUT_RING(br00); 1726 OUT_RING(br13); 1727 OUT_RING(br22); 1728 OUT_RING(br23); 1729 OUT_RING(br09); 1730 OUT_RING(br26); 1731 OUT_RING(br11); 1732 OUT_RING(br12); 1733 ADVANCE_RING(); 1734} 1735 1736int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w, 1737 u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, 1738 u32 bpp) 1739{ 1740 int nbytes, ndwords, pad, tmp; 1741 u32 br00, br09, br13, br18, br19, br22, br23; 1742 int dat, ix, iy, iw; 1743 int i, j; 1744 1745#if VERBOSE > 0 1746 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h); 1747#endif 1748 1749 /* size in bytes of a padded scanline */ 1750 nbytes = ROUND_UP_TO(w, 16) / 8; 1751 1752 /* Total bytes of padded scanline data to write out. */ 1753 nbytes = nbytes * h; 1754 1755 /* 1756 * Check if the glyph data exceeds the immediate mode limit. 1757 * It would take a large font (1K pixels) to hit this limit. 1758 */ 1759 if (nbytes > MAX_MONO_IMM_SIZE) 1760 return 0; 1761 1762 /* Src data is packaged a dword (32-bit) at a time. */ 1763 ndwords = ROUND_UP_TO(nbytes, 4) / 4; 1764 1765 /* 1766 * Ring has to be padded to a quad word. But because the command starts 1767 with 7 bytes, pad only if there is an even number of ndwords 1768 */ 1769 pad = !(ndwords % 2); 1770 1771 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords; 1772 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp; 1773 br09 = dinfo->fb_start; 1774 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT); 1775 br18 = bg; 1776 br19 = fg; 1777 br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT); 1778 br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT); 1779 1780 switch (bpp) { 1781 case 8: 1782 br13 |= COLOR_DEPTH_8; 1783 break; 1784 case 16: 1785 br13 |= COLOR_DEPTH_16; 1786 break; 1787 case 32: 1788 br13 |= COLOR_DEPTH_32; 1789 br00 |= WRITE_ALPHA | WRITE_RGB; 1790 break; 1791 } 1792 1793 START_RING(8 + ndwords); 1794 OUT_RING(br00); 1795 OUT_RING(br13); 1796 OUT_RING(br22); 1797 OUT_RING(br23); 1798 OUT_RING(br09); 1799 OUT_RING(br18); 1800 OUT_RING(br19); 1801 ix = iy = 0; 1802 iw = ROUND_UP_TO(w, 8) / 8; 1803 while (ndwords--) { 1804 dat = 0; 1805 for (j = 0; j < 2; ++j) { 1806 for (i = 0; i < 2; ++i) { 1807 if (ix != iw || i == 0) 1808 dat |= cdat[iy*iw + ix++] << (i+j*2)*8; 1809 } 1810 if (ix == iw && iy != (h-1)) { 1811 ix = 0; 1812 ++iy; 1813 } 1814 } 1815 OUT_RING(dat); 1816 } 1817 if (pad) 1818 OUT_RING(MI_NOOP); 1819 ADVANCE_RING(); 1820 1821 return 1; 1822} 1823 1824/* HW cursor functions. */ 1825void intelfbhw_cursor_init(struct intelfb_info *dinfo) 1826{ 1827 u32 tmp; 1828 1829#if VERBOSE > 0 1830 DBG_MSG("intelfbhw_cursor_init\n"); 1831#endif 1832 1833 if (dinfo->mobile || IS_I9XX(dinfo)) { 1834 if (!dinfo->cursor.physical) 1835 return; 1836 tmp = INREG(CURSOR_A_CONTROL); 1837 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE | 1838 CURSOR_MEM_TYPE_LOCAL | 1839 (1 << CURSOR_PIPE_SELECT_SHIFT)); 1840 tmp |= CURSOR_MODE_DISABLE; 1841 OUTREG(CURSOR_A_CONTROL, tmp); 1842 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); 1843 } else { 1844 tmp = INREG(CURSOR_CONTROL); 1845 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE | 1846 CURSOR_ENABLE | CURSOR_STRIDE_MASK); 1847 tmp = CURSOR_FORMAT_3C; 1848 OUTREG(CURSOR_CONTROL, tmp); 1849 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12); 1850 tmp = (64 << CURSOR_SIZE_H_SHIFT) | 1851 (64 << CURSOR_SIZE_V_SHIFT); 1852 OUTREG(CURSOR_SIZE, tmp); 1853 } 1854} 1855 1856void intelfbhw_cursor_hide(struct intelfb_info *dinfo) 1857{ 1858 u32 tmp; 1859 1860#if VERBOSE > 0 1861 DBG_MSG("intelfbhw_cursor_hide\n"); 1862#endif 1863 1864 dinfo->cursor_on = 0; 1865 if (dinfo->mobile || IS_I9XX(dinfo)) { 1866 if (!dinfo->cursor.physical) 1867 return; 1868 tmp = INREG(CURSOR_A_CONTROL); 1869 tmp &= ~CURSOR_MODE_MASK; 1870 tmp |= CURSOR_MODE_DISABLE; 1871 OUTREG(CURSOR_A_CONTROL, tmp); 1872 /* Flush changes */ 1873 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); 1874 } else { 1875 tmp = INREG(CURSOR_CONTROL); 1876 tmp &= ~CURSOR_ENABLE; 1877 OUTREG(CURSOR_CONTROL, tmp); 1878 } 1879} 1880 1881void intelfbhw_cursor_show(struct intelfb_info *dinfo) 1882{ 1883 u32 tmp; 1884 1885#if VERBOSE > 0 1886 DBG_MSG("intelfbhw_cursor_show\n"); 1887#endif 1888 1889 dinfo->cursor_on = 1; 1890 1891 if (dinfo->cursor_blanked) 1892 return; 1893 1894 if (dinfo->mobile || IS_I9XX(dinfo)) { 1895 if (!dinfo->cursor.physical) 1896 return; 1897 tmp = INREG(CURSOR_A_CONTROL); 1898 tmp &= ~CURSOR_MODE_MASK; 1899 tmp |= CURSOR_MODE_64_4C_AX; 1900 OUTREG(CURSOR_A_CONTROL, tmp); 1901 /* Flush changes */ 1902 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); 1903 } else { 1904 tmp = INREG(CURSOR_CONTROL); 1905 tmp |= CURSOR_ENABLE; 1906 OUTREG(CURSOR_CONTROL, tmp); 1907 } 1908} 1909 1910void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y) 1911{ 1912 u32 tmp; 1913 1914#if VERBOSE > 0 1915 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y); 1916#endif 1917 1918 /* 1919 * Sets the position. The coordinates are assumed to already 1920 * have any offset adjusted. Assume that the cursor is never 1921 * completely off-screen, and that x, y are always >= 0. 1922 */ 1923 1924 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) | 1925 ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT); 1926 OUTREG(CURSOR_A_POSITION, tmp); 1927 1928 if (IS_I9XX(dinfo)) 1929 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical); 1930} 1931 1932void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg) 1933{ 1934#if VERBOSE > 0 1935 DBG_MSG("intelfbhw_cursor_setcolor\n"); 1936#endif 1937 1938 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK); 1939 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK); 1940 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK); 1941 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK); 1942} 1943 1944void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height, 1945 u8 *data) 1946{ 1947 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual; 1948 int i, j, w = width / 8; 1949 int mod = width % 8, t_mask, d_mask; 1950 1951#if VERBOSE > 0 1952 DBG_MSG("intelfbhw_cursor_load\n"); 1953#endif 1954 1955 if (!dinfo->cursor.virtual) 1956 return; 1957 1958 t_mask = 0xff >> mod; 1959 d_mask = ~(0xff >> mod); 1960 for (i = height; i--; ) { 1961 for (j = 0; j < w; j++) { 1962 writeb(0x00, addr + j); 1963 writeb(*(data++), addr + j+8); 1964 } 1965 if (mod) { 1966 writeb(t_mask, addr + j); 1967 writeb(*(data++) & d_mask, addr + j+8); 1968 } 1969 addr += 16; 1970 } 1971} 1972 1973void intelfbhw_cursor_reset(struct intelfb_info *dinfo) 1974{ 1975 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual; 1976 int i, j; 1977 1978#if VERBOSE > 0 1979 DBG_MSG("intelfbhw_cursor_reset\n"); 1980#endif 1981 1982 if (!dinfo->cursor.virtual) 1983 return; 1984 1985 for (i = 64; i--; ) { 1986 for (j = 0; j < 8; j++) { 1987 writeb(0xff, addr + j+0); 1988 writeb(0x00, addr + j+8); 1989 } 1990 addr += 16; 1991 } 1992} 1993 1994static irqreturn_t intelfbhw_irq(int irq, void *dev_id) 1995{ 1996 u16 tmp; 1997 struct intelfb_info *dinfo = dev_id; 1998 1999 spin_lock(&dinfo->int_lock); 2000 2001 tmp = INREG16(IIR); 2002 if (dinfo->info->var.vmode & FB_VMODE_INTERLACED) 2003 tmp &= PIPE_A_EVENT_INTERRUPT; 2004 else 2005 tmp &= VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */ 2006 2007 if (tmp == 0) { 2008 spin_unlock(&dinfo->int_lock); 2009 return IRQ_RETVAL(0); /* not us */ 2010 } 2011 2012 /* clear status bits 0-15 ASAP and don't touch bits 16-31 */ 2013 OUTREG(PIPEASTAT, INREG(PIPEASTAT)); 2014 2015 OUTREG16(IIR, tmp); 2016 if (dinfo->vsync.pan_display) { 2017 dinfo->vsync.pan_display = 0; 2018 OUTREG(DSPABASE, dinfo->vsync.pan_offset); 2019 } 2020 2021 dinfo->vsync.count++; 2022 wake_up_interruptible(&dinfo->vsync.wait); 2023 2024 spin_unlock(&dinfo->int_lock); 2025 2026 return IRQ_RETVAL(1); 2027} 2028 2029int intelfbhw_enable_irq(struct intelfb_info *dinfo) 2030{ 2031 u16 tmp; 2032 if (!test_and_set_bit(0, &dinfo->irq_flags)) { 2033 if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED, 2034 "intelfb", dinfo)) { 2035 clear_bit(0, &dinfo->irq_flags); 2036 return -EINVAL; 2037 } 2038 2039 spin_lock_irq(&dinfo->int_lock); 2040 OUTREG16(HWSTAM, 0xfffe); /* i830 DRM uses ffff */ 2041 OUTREG16(IMR, 0); 2042 } else 2043 spin_lock_irq(&dinfo->int_lock); 2044 2045 if (dinfo->info->var.vmode & FB_VMODE_INTERLACED) 2046 tmp = PIPE_A_EVENT_INTERRUPT; 2047 else 2048 tmp = VSYNC_PIPE_A_INTERRUPT; /* non-interlaced */ 2049 if (tmp != INREG16(IER)) { 2050 DBG_MSG("changing IER to 0x%X\n", tmp); 2051 OUTREG16(IER, tmp); 2052 } 2053 2054 spin_unlock_irq(&dinfo->int_lock); 2055 return 0; 2056} 2057 2058void intelfbhw_disable_irq(struct intelfb_info *dinfo) 2059{ 2060 if (test_and_clear_bit(0, &dinfo->irq_flags)) { 2061 if (dinfo->vsync.pan_display) { 2062 dinfo->vsync.pan_display = 0; 2063 OUTREG(DSPABASE, dinfo->vsync.pan_offset); 2064 } 2065 spin_lock_irq(&dinfo->int_lock); 2066 OUTREG16(HWSTAM, 0xffff); 2067 OUTREG16(IMR, 0xffff); 2068 OUTREG16(IER, 0x0); 2069 2070 OUTREG16(IIR, INREG16(IIR)); /* clear IRQ requests */ 2071 spin_unlock_irq(&dinfo->int_lock); 2072 2073 free_irq(dinfo->pdev->irq, dinfo); 2074 } 2075} 2076 2077int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe) 2078{ 2079 struct intelfb_vsync *vsync; 2080 unsigned int count; 2081 int ret; 2082 2083 switch (pipe) { 2084 case 0: 2085 vsync = &dinfo->vsync; 2086 break; 2087 default: 2088 return -ENODEV; 2089 } 2090 2091 ret = intelfbhw_enable_irq(dinfo); 2092 if (ret) 2093 return ret; 2094 2095 count = vsync->count; 2096 ret = wait_event_interruptible_timeout(vsync->wait, 2097 count != vsync->count, HZ / 10); 2098 if (ret < 0) 2099 return ret; 2100 if (ret == 0) { 2101 DBG_MSG("wait_for_vsync timed out!\n"); 2102 return -ETIMEDOUT; 2103 } 2104 2105 return 0; 2106} 2107