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  • only in /asuswrt-rt-n18u-9.0.0.4.380.2695/release/src-rt-6.x.4708/linux/linux-2.6/drivers/staging/dream/include/mach/qdsp5/
1#ifndef QDSP5AUDPPMSG_H
2#define QDSP5AUDPPMSG_H
3
4/*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*
5
6       Q D S P 5  A U D I O   P O S T   P R O C E S S I N G   M S G
7
8GENERAL DESCRIPTION
9  Messages sent by AUDPPTASK to ARM
10
11REFERENCES
12  None
13
14EXTERNALIZED FUNCTIONS
15  None
16
17Copyright(c) 1992 - 2009 by QUALCOMM, Incorporated.
18
19This software is licensed under the terms of the GNU General Public
20License version 2, as published by the Free Software Foundation, and
21may be copied, distributed, and modified under those terms.
22
23This program is distributed in the hope that it will be useful,
24but WITHOUT ANY WARRANTY; without even the implied warranty of
25MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
26GNU General Public License for more details.
27
28*====*====*====*====*====*====*====*====*====*====*====*====*====*====*====*/
29/*===========================================================================
30
31                      EDIT HISTORY FOR FILE
32
33This section contains comments describing changes made to this file.
34Notice that changes are listed in reverse chronological order.
35
36 $Header: //source/qcom/qct/multimedia2/Audio/drivers/QDSP5Driver/QDSP5Interface/main/latest/qdsp5audppmsg.h#4 $
37
38===========================================================================*/
39
40/*
41 * AUDPPTASK uses audPPuPRlist to send messages to the ARM
42 * Location : MEMA
43 * Buffer Size : 45
44 * No of Buffers in a queue : 5 for gaming audio and 1 for other images
45 */
46
47/*
48 * MSG to Informs the ARM os Success/Failure of bringing up the decoder
49 */
50
51#define AUDPP_MSG_STATUS_MSG		0x0001
52#define AUDPP_MSG_STATUS_MSG_LEN	\
53	sizeof(audpp_msg_status_msg)
54
55#define AUDPP_MSG_STATUS_SLEEP		0x0000
56#define AUDPP_MSG__STATUS_INIT		0x0001
57#define AUDPP_MSG_MSG_STATUS_CFG	0x0002
58#define AUDPP_MSG_STATUS_PLAY		0x0003
59
60#define AUDPP_MSG_REASON_MIPS	0x0000
61#define AUDPP_MSG_REASON_MEM	0x0001
62
63typedef struct{
64	unsigned short dec_id;
65	unsigned short status;
66	unsigned short reason;
67} __attribute__((packed)) audpp_msg_status_msg;
68
69/*
70 * MSG to communicate the spectrum analyzer output bands to the ARM
71 */
72#define AUDPP_MSG_SPA_BANDS		0x0002
73#define AUDPP_MSG_SPA_BANDS_LEN	\
74	sizeof(audpp_msg_spa_bands)
75
76typedef struct {
77	unsigned short			current_object;
78	unsigned short			spa_band_1;
79	unsigned short			spa_band_2;
80	unsigned short			spa_band_3;
81	unsigned short			spa_band_4;
82	unsigned short			spa_band_5;
83	unsigned short			spa_band_6;
84	unsigned short			spa_band_7;
85	unsigned short			spa_band_8;
86	unsigned short			spa_band_9;
87	unsigned short			spa_band_10;
88	unsigned short			spa_band_11;
89	unsigned short			spa_band_12;
90	unsigned short			spa_band_13;
91	unsigned short			spa_band_14;
92	unsigned short			spa_band_15;
93	unsigned short			spa_band_16;
94	unsigned short			spa_band_17;
95	unsigned short			spa_band_18;
96	unsigned short			spa_band_19;
97	unsigned short			spa_band_20;
98	unsigned short			spa_band_21;
99	unsigned short			spa_band_22;
100	unsigned short			spa_band_23;
101	unsigned short			spa_band_24;
102	unsigned short			spa_band_25;
103	unsigned short			spa_band_26;
104	unsigned short			spa_band_27;
105	unsigned short			spa_band_28;
106	unsigned short			spa_band_29;
107	unsigned short			spa_band_30;
108	unsigned short			spa_band_31;
109	unsigned short			spa_band_32;
110} __attribute__((packed)) audpp_msg_spa_bands;
111
112/*
113 * MSG to communicate the PCM I/O buffer status to ARM
114 */
115#define  AUDPP_MSG_HOST_PCM_INTF_MSG		0x0003
116#define  AUDPP_MSG_HOST_PCM_INTF_MSG_LEN	\
117	sizeof(audpp_msg_host_pcm_intf_msg)
118
119#define AUDPP_MSG_HOSTPCM_ID_TX_ARM	0x0000
120#define AUDPP_MSG_HOSTPCM_ID_ARM_TX	0x0001
121#define AUDPP_MSG_HOSTPCM_ID_RX_ARM	0x0002
122#define AUDPP_MSG_HOSTPCM_ID_ARM_RX	0x0003
123
124#define AUDPP_MSG_SAMP_FREQ_INDX_96000	0x0000
125#define AUDPP_MSG_SAMP_FREQ_INDX_88200	0x0001
126#define AUDPP_MSG_SAMP_FREQ_INDX_64000	0x0002
127#define AUDPP_MSG_SAMP_FREQ_INDX_48000	0x0003
128#define AUDPP_MSG_SAMP_FREQ_INDX_44100	0x0004
129#define AUDPP_MSG_SAMP_FREQ_INDX_32000	0x0005
130#define AUDPP_MSG_SAMP_FREQ_INDX_24000	0x0006
131#define AUDPP_MSG_SAMP_FREQ_INDX_22050	0x0007
132#define AUDPP_MSG_SAMP_FREQ_INDX_16000	0x0008
133#define AUDPP_MSG_SAMP_FREQ_INDX_12000	0x0009
134#define AUDPP_MSG_SAMP_FREQ_INDX_11025	0x000A
135#define AUDPP_MSG_SAMP_FREQ_INDX_8000	0x000B
136
137#define AUDPP_MSG_CHANNEL_MODE_MONO		0x0001
138#define AUDPP_MSG_CHANNEL_MODE_STEREO	0x0002
139
140typedef struct{
141	unsigned short obj_num;
142	unsigned short numbers_of_samples;
143	unsigned short host_pcm_id;
144	unsigned short buf_indx;
145	unsigned short samp_freq_indx;
146	unsigned short channel_mode;
147} __attribute__((packed)) audpp_msg_host_pcm_intf_msg;
148
149
150/*
151 * MSG to communicate 3D position of the source and listener , source volume
152 * source rolloff, source orientation
153 */
154
155#define AUDPP_MSG_QAFX_POS		0x0004
156#define AUDPP_MSG_QAFX_POS_LEN		\
157	sizeof(audpp_msg_qafx_pos)
158
159typedef struct {
160	unsigned short	current_object;
161	unsigned short	x_pos_lis_msw;
162	unsigned short	x_pos_lis_lsw;
163	unsigned short	y_pos_lis_msw;
164	unsigned short	y_pos_lis_lsw;
165	unsigned short	z_pos_lis_msw;
166	unsigned short	z_pos_lis_lsw;
167	unsigned short	x_fwd_msw;
168	unsigned short	x_fwd_lsw;
169	unsigned short	y_fwd_msw;
170	unsigned short	y_fwd_lsw;
171	unsigned short	z_fwd_msw;
172	unsigned short	z_fwd_lsw;
173	unsigned short 	x_up_msw;
174	unsigned short	x_up_lsw;
175	unsigned short 	y_up_msw;
176	unsigned short	y_up_lsw;
177	unsigned short 	z_up_msw;
178	unsigned short	z_up_lsw;
179	unsigned short 	x_vel_lis_msw;
180	unsigned short 	x_vel_lis_lsw;
181	unsigned short 	y_vel_lis_msw;
182	unsigned short 	y_vel_lis_lsw;
183	unsigned short 	z_vel_lis_msw;
184	unsigned short 	z_vel_lis_lsw;
185	unsigned short	threed_enable_flag;
186	unsigned short 	volume;
187	unsigned short	x_pos_source_msw;
188	unsigned short	x_pos_source_lsw;
189	unsigned short	y_pos_source_msw;
190	unsigned short	y_pos_source_lsw;
191	unsigned short	z_pos_source_msw;
192	unsigned short	z_pos_source_lsw;
193	unsigned short	max_dist_0_msw;
194	unsigned short	max_dist_0_lsw;
195	unsigned short	min_dist_0_msw;
196	unsigned short	min_dist_0_lsw;
197	unsigned short	roll_off_factor;
198	unsigned short	mute_after_max_flag;
199	unsigned short	x_vel_source_msw;
200	unsigned short	x_vel_source_lsw;
201	unsigned short	y_vel_source_msw;
202	unsigned short	y_vel_source_lsw;
203	unsigned short	z_vel_source_msw;
204	unsigned short	z_vel_source_lsw;
205} __attribute__((packed)) audpp_msg_qafx_pos;
206
207/*
208 * MSG to provide AVSYNC feedback from DSP to ARM
209 */
210
211#define AUDPP_MSG_AVSYNC_MSG		0x0005
212#define AUDPP_MSG_AVSYNC_MSG_LEN	\
213	sizeof(audpp_msg_avsync_msg)
214
215typedef struct {
216	unsigned short	active_flag;
217	unsigned short	num_samples_counter0_HSW;
218	unsigned short	num_samples_counter0_MSW;
219	unsigned short	num_samples_counter0_LSW;
220	unsigned short	num_bytes_counter0_HSW;
221	unsigned short	num_bytes_counter0_MSW;
222	unsigned short	num_bytes_counter0_LSW;
223	unsigned short	samp_freq_obj_0;
224	unsigned short	samp_freq_obj_1;
225	unsigned short	samp_freq_obj_2;
226	unsigned short	samp_freq_obj_3;
227	unsigned short	samp_freq_obj_4;
228	unsigned short	samp_freq_obj_5;
229	unsigned short	samp_freq_obj_6;
230	unsigned short	samp_freq_obj_7;
231	unsigned short	samp_freq_obj_8;
232	unsigned short	samp_freq_obj_9;
233	unsigned short	samp_freq_obj_10;
234	unsigned short	samp_freq_obj_11;
235	unsigned short	samp_freq_obj_12;
236	unsigned short	samp_freq_obj_13;
237	unsigned short	samp_freq_obj_14;
238	unsigned short	samp_freq_obj_15;
239	unsigned short	num_samples_counter4_HSW;
240	unsigned short	num_samples_counter4_MSW;
241	unsigned short	num_samples_counter4_LSW;
242	unsigned short	num_bytes_counter4_HSW;
243	unsigned short	num_bytes_counter4_MSW;
244	unsigned short	num_bytes_counter4_LSW;
245} __attribute__((packed)) audpp_msg_avsync_msg;
246
247/*
248 * MSG to provide PCM DMA Missed feedback from the DSP to ARM
249 */
250
251#define  AUDPP_MSG_PCMDMAMISSED	0x0006
252#define  AUDPP_MSG_PCMDMAMISSED_LEN	\
253	sizeof(audpp_msg_pcmdmamissed);
254
255typedef struct{
256	/*
257	** Bit 0	0 = PCM DMA not missed for object 0
258	**        1 = PCM DMA missed for object0
259	** Bit 1	0 = PCM DMA not missed for object 1
260	**        1 = PCM DMA missed for object1
261	** Bit 2	0 = PCM DMA not missed for object 2
262	**        1 = PCM DMA missed for object2
263	** Bit 3	0 = PCM DMA not missed for object 3
264	**        1 = PCM DMA missed for object3
265	** Bit 4	0 = PCM DMA not missed for object 4
266	**        1 = PCM DMA missed for object4
267	*/
268	unsigned short pcmdmamissed;
269} __attribute__((packed)) audpp_msg_pcmdmamissed;
270
271/*
272 * MSG to AUDPP enable or disable feedback form DSP to ARM
273 */
274
275#define AUDPP_MSG_CFG_MSG	0x0007
276#define AUDPP_MSG_CFG_MSG_LEN	\
277    sizeof(audpp_msg_cfg_msg)
278
279#define AUDPP_MSG_ENA_ENA	0xFFFF
280#define AUDPP_MSG_ENA_DIS	0x0000
281
282typedef struct{
283	/*   Enabled  - 0xffff
284	**  Disabled - 0
285	*/
286	unsigned short enabled;
287} __attribute__((packed)) audpp_msg_cfg_msg;
288
289/*
290 * MSG to communicate the reverb  per object volume
291 */
292
293#define AUDPP_MSG_QREVERB_VOLUME	0x0008
294#define AUDPP_MSG_QREVERB_VOLUME_LEN	\
295	sizeof(audpp_msg_qreverb_volume)
296
297
298typedef struct {
299	unsigned short	obj_0_gain;
300	unsigned short	obj_1_gain;
301	unsigned short	obj_2_gain;
302	unsigned short	obj_3_gain;
303	unsigned short	obj_4_gain;
304	unsigned short	hpcm_obj_volume;
305} __attribute__((packed)) audpp_msg_qreverb_volume;
306
307#define AUDPP_MSG_ROUTING_ACK 0x0009
308#define AUDPP_MSG_ROUTING_ACK_LEN \
309  sizeof(struct audpp_msg_routing_ack)
310
311struct audpp_msg_routing_ack {
312	unsigned short dec_id;
313	unsigned short routing_mode;
314} __attribute__((packed));
315
316#define AUDPP_MSG_FLUSH_ACK 0x000A
317
318#endif /* QDSP5AUDPPMSG_H */
319