1/* sunsab.c: ASYNC Driver for the SIEMENS SAB82532 DUSCC. 2 * 3 * Copyright (C) 1997 Eddie C. Dost (ecd@skynet.be) 4 * Copyright (C) 2002, 2006 David S. Miller (davem@davemloft.net) 5 * 6 * Rewrote buffer handling to use CIRC(Circular Buffer) macros. 7 * Maxim Krasnyanskiy <maxk@qualcomm.com> 8 * 9 * Fixed to use tty_get_baud_rate, and to allow for arbitrary baud 10 * rates to be programmed into the UART. Also eliminated a lot of 11 * duplicated code in the console setup. 12 * Theodore Ts'o <tytso@mit.edu>, 2001-Oct-12 13 * 14 * Ported to new 2.5.x UART layer. 15 * David S. Miller <davem@davemloft.net> 16 */ 17 18#include <linux/module.h> 19#include <linux/kernel.h> 20#include <linux/errno.h> 21#include <linux/tty.h> 22#include <linux/tty_flip.h> 23#include <linux/major.h> 24#include <linux/string.h> 25#include <linux/ptrace.h> 26#include <linux/ioport.h> 27#include <linux/circ_buf.h> 28#include <linux/serial.h> 29#include <linux/sysrq.h> 30#include <linux/console.h> 31#include <linux/spinlock.h> 32#include <linux/slab.h> 33#include <linux/delay.h> 34#include <linux/init.h> 35#include <linux/of_device.h> 36 37#include <asm/io.h> 38#include <asm/irq.h> 39#include <asm/prom.h> 40 41#if defined(CONFIG_SERIAL_SUNSAB_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 42#define SUPPORT_SYSRQ 43#endif 44 45#include <linux/serial_core.h> 46 47#include "suncore.h" 48#include "sunsab.h" 49 50struct uart_sunsab_port { 51 struct uart_port port; /* Generic UART port */ 52 union sab82532_async_regs __iomem *regs; /* Chip registers */ 53 unsigned long irqflags; /* IRQ state flags */ 54 int dsr; /* Current DSR state */ 55 unsigned int cec_timeout; /* Chip poll timeout... */ 56 unsigned int tec_timeout; /* likewise */ 57 unsigned char interrupt_mask0;/* ISR0 masking */ 58 unsigned char interrupt_mask1;/* ISR1 masking */ 59 unsigned char pvr_dtr_bit; /* Which PVR bit is DTR */ 60 unsigned char pvr_dsr_bit; /* Which PVR bit is DSR */ 61 unsigned int gis_shift; 62 int type; /* SAB82532 version */ 63 64 /* Setting configuration bits while the transmitter is active 65 * can cause garbage characters to get emitted by the chip. 66 * Therefore, we cache such writes here and do the real register 67 * write the next time the transmitter becomes idle. 68 */ 69 unsigned int cached_ebrg; 70 unsigned char cached_mode; 71 unsigned char cached_pvr; 72 unsigned char cached_dafo; 73}; 74 75/* 76 * This assumes you have a 29.4912 MHz clock for your UART. 77 */ 78#define SAB_BASE_BAUD ( 29491200 / 16 ) 79 80static char *sab82532_version[16] = { 81 "V1.0", "V2.0", "V3.2", "V(0x03)", 82 "V(0x04)", "V(0x05)", "V(0x06)", "V(0x07)", 83 "V(0x08)", "V(0x09)", "V(0x0a)", "V(0x0b)", 84 "V(0x0c)", "V(0x0d)", "V(0x0e)", "V(0x0f)" 85}; 86 87#define SAB82532_MAX_TEC_TIMEOUT 200000 /* 1 character time (at 50 baud) */ 88#define SAB82532_MAX_CEC_TIMEOUT 50000 /* 2.5 TX CLKs (at 50 baud) */ 89 90#define SAB82532_RECV_FIFO_SIZE 32 /* Standard async fifo sizes */ 91#define SAB82532_XMIT_FIFO_SIZE 32 92 93static __inline__ void sunsab_tec_wait(struct uart_sunsab_port *up) 94{ 95 int timeout = up->tec_timeout; 96 97 while ((readb(&up->regs->r.star) & SAB82532_STAR_TEC) && --timeout) 98 udelay(1); 99} 100 101static __inline__ void sunsab_cec_wait(struct uart_sunsab_port *up) 102{ 103 int timeout = up->cec_timeout; 104 105 while ((readb(&up->regs->r.star) & SAB82532_STAR_CEC) && --timeout) 106 udelay(1); 107} 108 109static struct tty_struct * 110receive_chars(struct uart_sunsab_port *up, 111 union sab82532_irq_status *stat) 112{ 113 struct tty_struct *tty = NULL; 114 unsigned char buf[32]; 115 int saw_console_brk = 0; 116 int free_fifo = 0; 117 int count = 0; 118 int i; 119 120 if (up->port.state != NULL) /* Unopened serial console */ 121 tty = up->port.state->port.tty; 122 123 /* Read number of BYTES (Character + Status) available. */ 124 if (stat->sreg.isr0 & SAB82532_ISR0_RPF) { 125 count = SAB82532_RECV_FIFO_SIZE; 126 free_fifo++; 127 } 128 129 if (stat->sreg.isr0 & SAB82532_ISR0_TCD) { 130 count = readb(&up->regs->r.rbcl) & (SAB82532_RECV_FIFO_SIZE - 1); 131 free_fifo++; 132 } 133 134 /* Issue a FIFO read command in case we where idle. */ 135 if (stat->sreg.isr0 & SAB82532_ISR0_TIME) { 136 sunsab_cec_wait(up); 137 writeb(SAB82532_CMDR_RFRD, &up->regs->w.cmdr); 138 return tty; 139 } 140 141 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 142 free_fifo++; 143 144 /* Read the FIFO. */ 145 for (i = 0; i < count; i++) 146 buf[i] = readb(&up->regs->r.rfifo[i]); 147 148 /* Issue Receive Message Complete command. */ 149 if (free_fifo) { 150 sunsab_cec_wait(up); 151 writeb(SAB82532_CMDR_RMC, &up->regs->w.cmdr); 152 } 153 154 /* Count may be zero for BRK, so we check for it here */ 155 if ((stat->sreg.isr1 & SAB82532_ISR1_BRK) && 156 (up->port.line == up->port.cons->index)) 157 saw_console_brk = 1; 158 159 for (i = 0; i < count; i++) { 160 unsigned char ch = buf[i], flag; 161 162 if (tty == NULL) { 163 uart_handle_sysrq_char(&up->port, ch); 164 continue; 165 } 166 167 flag = TTY_NORMAL; 168 up->port.icount.rx++; 169 170 if (unlikely(stat->sreg.isr0 & (SAB82532_ISR0_PERR | 171 SAB82532_ISR0_FERR | 172 SAB82532_ISR0_RFO)) || 173 unlikely(stat->sreg.isr1 & SAB82532_ISR1_BRK)) { 174 /* 175 * For statistics only 176 */ 177 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) { 178 stat->sreg.isr0 &= ~(SAB82532_ISR0_PERR | 179 SAB82532_ISR0_FERR); 180 up->port.icount.brk++; 181 /* 182 * We do the SysRQ and SAK checking 183 * here because otherwise the break 184 * may get masked by ignore_status_mask 185 * or read_status_mask. 186 */ 187 if (uart_handle_break(&up->port)) 188 continue; 189 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR) 190 up->port.icount.parity++; 191 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR) 192 up->port.icount.frame++; 193 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 194 up->port.icount.overrun++; 195 196 /* 197 * Mask off conditions which should be ingored. 198 */ 199 stat->sreg.isr0 &= (up->port.read_status_mask & 0xff); 200 stat->sreg.isr1 &= ((up->port.read_status_mask >> 8) & 0xff); 201 202 if (stat->sreg.isr1 & SAB82532_ISR1_BRK) { 203 flag = TTY_BREAK; 204 } else if (stat->sreg.isr0 & SAB82532_ISR0_PERR) 205 flag = TTY_PARITY; 206 else if (stat->sreg.isr0 & SAB82532_ISR0_FERR) 207 flag = TTY_FRAME; 208 } 209 210 if (uart_handle_sysrq_char(&up->port, ch)) 211 continue; 212 213 if ((stat->sreg.isr0 & (up->port.ignore_status_mask & 0xff)) == 0 && 214 (stat->sreg.isr1 & ((up->port.ignore_status_mask >> 8) & 0xff)) == 0) 215 tty_insert_flip_char(tty, ch, flag); 216 if (stat->sreg.isr0 & SAB82532_ISR0_RFO) 217 tty_insert_flip_char(tty, 0, TTY_OVERRUN); 218 } 219 220 if (saw_console_brk) 221 sun_do_break(); 222 223 return tty; 224} 225 226static void sunsab_stop_tx(struct uart_port *); 227static void sunsab_tx_idle(struct uart_sunsab_port *); 228 229static void transmit_chars(struct uart_sunsab_port *up, 230 union sab82532_irq_status *stat) 231{ 232 struct circ_buf *xmit = &up->port.state->xmit; 233 int i; 234 235 if (stat->sreg.isr1 & SAB82532_ISR1_ALLS) { 236 up->interrupt_mask1 |= SAB82532_IMR1_ALLS; 237 writeb(up->interrupt_mask1, &up->regs->w.imr1); 238 set_bit(SAB82532_ALLS, &up->irqflags); 239 } 240 241 242 if (!(readb(&up->regs->r.star) & SAB82532_STAR_XFW)) 243 return; 244 245 set_bit(SAB82532_XPR, &up->irqflags); 246 sunsab_tx_idle(up); 247 248 if (uart_circ_empty(xmit) || uart_tx_stopped(&up->port)) { 249 up->interrupt_mask1 |= SAB82532_IMR1_XPR; 250 writeb(up->interrupt_mask1, &up->regs->w.imr1); 251 return; 252 } 253 254 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR); 255 writeb(up->interrupt_mask1, &up->regs->w.imr1); 256 clear_bit(SAB82532_ALLS, &up->irqflags); 257 258 /* Stuff 32 bytes into Transmit FIFO. */ 259 clear_bit(SAB82532_XPR, &up->irqflags); 260 for (i = 0; i < up->port.fifosize; i++) { 261 writeb(xmit->buf[xmit->tail], 262 &up->regs->w.xfifo[i]); 263 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 264 up->port.icount.tx++; 265 if (uart_circ_empty(xmit)) 266 break; 267 } 268 269 /* Issue a Transmit Frame command. */ 270 sunsab_cec_wait(up); 271 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr); 272 273 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 274 uart_write_wakeup(&up->port); 275 276 if (uart_circ_empty(xmit)) 277 sunsab_stop_tx(&up->port); 278} 279 280static void check_status(struct uart_sunsab_port *up, 281 union sab82532_irq_status *stat) 282{ 283 if (stat->sreg.isr0 & SAB82532_ISR0_CDSC) 284 uart_handle_dcd_change(&up->port, 285 !(readb(&up->regs->r.vstr) & SAB82532_VSTR_CD)); 286 287 if (stat->sreg.isr1 & SAB82532_ISR1_CSC) 288 uart_handle_cts_change(&up->port, 289 (readb(&up->regs->r.star) & SAB82532_STAR_CTS)); 290 291 if ((readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ^ up->dsr) { 292 up->dsr = (readb(&up->regs->r.pvr) & up->pvr_dsr_bit) ? 0 : 1; 293 up->port.icount.dsr++; 294 } 295 296 wake_up_interruptible(&up->port.state->port.delta_msr_wait); 297} 298 299static irqreturn_t sunsab_interrupt(int irq, void *dev_id) 300{ 301 struct uart_sunsab_port *up = dev_id; 302 struct tty_struct *tty; 303 union sab82532_irq_status status; 304 unsigned long flags; 305 unsigned char gis; 306 307 spin_lock_irqsave(&up->port.lock, flags); 308 309 status.stat = 0; 310 gis = readb(&up->regs->r.gis) >> up->gis_shift; 311 if (gis & 1) 312 status.sreg.isr0 = readb(&up->regs->r.isr0); 313 if (gis & 2) 314 status.sreg.isr1 = readb(&up->regs->r.isr1); 315 316 tty = NULL; 317 if (status.stat) { 318 if ((status.sreg.isr0 & (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME | 319 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF)) || 320 (status.sreg.isr1 & SAB82532_ISR1_BRK)) 321 tty = receive_chars(up, &status); 322 if ((status.sreg.isr0 & SAB82532_ISR0_CDSC) || 323 (status.sreg.isr1 & SAB82532_ISR1_CSC)) 324 check_status(up, &status); 325 if (status.sreg.isr1 & (SAB82532_ISR1_ALLS | SAB82532_ISR1_XPR)) 326 transmit_chars(up, &status); 327 } 328 329 spin_unlock_irqrestore(&up->port.lock, flags); 330 331 if (tty) 332 tty_flip_buffer_push(tty); 333 334 return IRQ_HANDLED; 335} 336 337/* port->lock is not held. */ 338static unsigned int sunsab_tx_empty(struct uart_port *port) 339{ 340 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 341 int ret; 342 343 /* Do not need a lock for a state test like this. */ 344 if (test_bit(SAB82532_ALLS, &up->irqflags)) 345 ret = TIOCSER_TEMT; 346 else 347 ret = 0; 348 349 return ret; 350} 351 352/* port->lock held by caller. */ 353static void sunsab_set_mctrl(struct uart_port *port, unsigned int mctrl) 354{ 355 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 356 357 if (mctrl & TIOCM_RTS) { 358 up->cached_mode &= ~SAB82532_MODE_FRTS; 359 up->cached_mode |= SAB82532_MODE_RTS; 360 } else { 361 up->cached_mode |= (SAB82532_MODE_FRTS | 362 SAB82532_MODE_RTS); 363 } 364 if (mctrl & TIOCM_DTR) { 365 up->cached_pvr &= ~(up->pvr_dtr_bit); 366 } else { 367 up->cached_pvr |= up->pvr_dtr_bit; 368 } 369 370 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 371 if (test_bit(SAB82532_XPR, &up->irqflags)) 372 sunsab_tx_idle(up); 373} 374 375/* port->lock is held by caller and interrupts are disabled. */ 376static unsigned int sunsab_get_mctrl(struct uart_port *port) 377{ 378 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 379 unsigned char val; 380 unsigned int result; 381 382 result = 0; 383 384 val = readb(&up->regs->r.pvr); 385 result |= (val & up->pvr_dsr_bit) ? 0 : TIOCM_DSR; 386 387 val = readb(&up->regs->r.vstr); 388 result |= (val & SAB82532_VSTR_CD) ? 0 : TIOCM_CAR; 389 390 val = readb(&up->regs->r.star); 391 result |= (val & SAB82532_STAR_CTS) ? TIOCM_CTS : 0; 392 393 return result; 394} 395 396/* port->lock held by caller. */ 397static void sunsab_stop_tx(struct uart_port *port) 398{ 399 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 400 401 up->interrupt_mask1 |= SAB82532_IMR1_XPR; 402 writeb(up->interrupt_mask1, &up->regs->w.imr1); 403} 404 405/* port->lock held by caller. */ 406static void sunsab_tx_idle(struct uart_sunsab_port *up) 407{ 408 if (test_bit(SAB82532_REGS_PENDING, &up->irqflags)) { 409 u8 tmp; 410 411 clear_bit(SAB82532_REGS_PENDING, &up->irqflags); 412 writeb(up->cached_mode, &up->regs->rw.mode); 413 writeb(up->cached_pvr, &up->regs->rw.pvr); 414 writeb(up->cached_dafo, &up->regs->w.dafo); 415 416 writeb(up->cached_ebrg & 0xff, &up->regs->w.bgr); 417 tmp = readb(&up->regs->rw.ccr2); 418 tmp &= ~0xc0; 419 tmp |= (up->cached_ebrg >> 2) & 0xc0; 420 writeb(tmp, &up->regs->rw.ccr2); 421 } 422} 423 424/* port->lock held by caller. */ 425static void sunsab_start_tx(struct uart_port *port) 426{ 427 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 428 struct circ_buf *xmit = &up->port.state->xmit; 429 int i; 430 431 up->interrupt_mask1 &= ~(SAB82532_IMR1_ALLS|SAB82532_IMR1_XPR); 432 writeb(up->interrupt_mask1, &up->regs->w.imr1); 433 434 if (!test_bit(SAB82532_XPR, &up->irqflags)) 435 return; 436 437 clear_bit(SAB82532_ALLS, &up->irqflags); 438 clear_bit(SAB82532_XPR, &up->irqflags); 439 440 for (i = 0; i < up->port.fifosize; i++) { 441 writeb(xmit->buf[xmit->tail], 442 &up->regs->w.xfifo[i]); 443 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 444 up->port.icount.tx++; 445 if (uart_circ_empty(xmit)) 446 break; 447 } 448 449 /* Issue a Transmit Frame command. */ 450 sunsab_cec_wait(up); 451 writeb(SAB82532_CMDR_XF, &up->regs->w.cmdr); 452} 453 454/* port->lock is not held. */ 455static void sunsab_send_xchar(struct uart_port *port, char ch) 456{ 457 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 458 unsigned long flags; 459 460 spin_lock_irqsave(&up->port.lock, flags); 461 462 sunsab_tec_wait(up); 463 writeb(ch, &up->regs->w.tic); 464 465 spin_unlock_irqrestore(&up->port.lock, flags); 466} 467 468/* port->lock held by caller. */ 469static void sunsab_stop_rx(struct uart_port *port) 470{ 471 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 472 473 up->interrupt_mask0 |= SAB82532_IMR0_TCD; 474 writeb(up->interrupt_mask1, &up->regs->w.imr0); 475} 476 477/* port->lock held by caller. */ 478static void sunsab_enable_ms(struct uart_port *port) 479{ 480 /* For now we always receive these interrupts. */ 481} 482 483/* port->lock is not held. */ 484static void sunsab_break_ctl(struct uart_port *port, int break_state) 485{ 486 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 487 unsigned long flags; 488 unsigned char val; 489 490 spin_lock_irqsave(&up->port.lock, flags); 491 492 val = up->cached_dafo; 493 if (break_state) 494 val |= SAB82532_DAFO_XBRK; 495 else 496 val &= ~SAB82532_DAFO_XBRK; 497 up->cached_dafo = val; 498 499 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 500 if (test_bit(SAB82532_XPR, &up->irqflags)) 501 sunsab_tx_idle(up); 502 503 spin_unlock_irqrestore(&up->port.lock, flags); 504} 505 506/* port->lock is not held. */ 507static int sunsab_startup(struct uart_port *port) 508{ 509 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 510 unsigned long flags; 511 unsigned char tmp; 512 int err = request_irq(up->port.irq, sunsab_interrupt, 513 IRQF_SHARED, "sab", up); 514 if (err) 515 return err; 516 517 spin_lock_irqsave(&up->port.lock, flags); 518 519 /* 520 * Wait for any commands or immediate characters 521 */ 522 sunsab_cec_wait(up); 523 sunsab_tec_wait(up); 524 525 /* 526 * Clear the FIFO buffers. 527 */ 528 writeb(SAB82532_CMDR_RRES, &up->regs->w.cmdr); 529 sunsab_cec_wait(up); 530 writeb(SAB82532_CMDR_XRES, &up->regs->w.cmdr); 531 532 /* 533 * Clear the interrupt registers. 534 */ 535 (void) readb(&up->regs->r.isr0); 536 (void) readb(&up->regs->r.isr1); 537 538 /* 539 * Now, initialize the UART 540 */ 541 writeb(0, &up->regs->w.ccr0); /* power-down */ 542 writeb(SAB82532_CCR0_MCE | SAB82532_CCR0_SC_NRZ | 543 SAB82532_CCR0_SM_ASYNC, &up->regs->w.ccr0); 544 writeb(SAB82532_CCR1_ODS | SAB82532_CCR1_BCR | 7, &up->regs->w.ccr1); 545 writeb(SAB82532_CCR2_BDF | SAB82532_CCR2_SSEL | 546 SAB82532_CCR2_TOE, &up->regs->w.ccr2); 547 writeb(0, &up->regs->w.ccr3); 548 writeb(SAB82532_CCR4_MCK4 | SAB82532_CCR4_EBRG, &up->regs->w.ccr4); 549 up->cached_mode = (SAB82532_MODE_RTS | SAB82532_MODE_FCTS | 550 SAB82532_MODE_RAC); 551 writeb(up->cached_mode, &up->regs->w.mode); 552 writeb(SAB82532_RFC_DPS|SAB82532_RFC_RFTH_32, &up->regs->w.rfc); 553 554 tmp = readb(&up->regs->rw.ccr0); 555 tmp |= SAB82532_CCR0_PU; /* power-up */ 556 writeb(tmp, &up->regs->rw.ccr0); 557 558 /* 559 * Finally, enable interrupts 560 */ 561 up->interrupt_mask0 = (SAB82532_IMR0_PERR | SAB82532_IMR0_FERR | 562 SAB82532_IMR0_PLLA); 563 writeb(up->interrupt_mask0, &up->regs->w.imr0); 564 up->interrupt_mask1 = (SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS | 565 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN | 566 SAB82532_IMR1_CSC | SAB82532_IMR1_XON | 567 SAB82532_IMR1_XPR); 568 writeb(up->interrupt_mask1, &up->regs->w.imr1); 569 set_bit(SAB82532_ALLS, &up->irqflags); 570 set_bit(SAB82532_XPR, &up->irqflags); 571 572 spin_unlock_irqrestore(&up->port.lock, flags); 573 574 return 0; 575} 576 577/* port->lock is not held. */ 578static void sunsab_shutdown(struct uart_port *port) 579{ 580 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 581 unsigned long flags; 582 583 spin_lock_irqsave(&up->port.lock, flags); 584 585 /* Disable Interrupts */ 586 up->interrupt_mask0 = 0xff; 587 writeb(up->interrupt_mask0, &up->regs->w.imr0); 588 up->interrupt_mask1 = 0xff; 589 writeb(up->interrupt_mask1, &up->regs->w.imr1); 590 591 /* Disable break condition */ 592 up->cached_dafo = readb(&up->regs->rw.dafo); 593 up->cached_dafo &= ~SAB82532_DAFO_XBRK; 594 writeb(up->cached_dafo, &up->regs->rw.dafo); 595 596 /* Disable Receiver */ 597 up->cached_mode &= ~SAB82532_MODE_RAC; 598 writeb(up->cached_mode, &up->regs->rw.mode); 599 600 601 spin_unlock_irqrestore(&up->port.lock, flags); 602 free_irq(up->port.irq, up); 603} 604 605/* 606 * This is used to figure out the divisor speeds. 607 * 608 * The formula is: Baud = SAB_BASE_BAUD / ((N + 1) * (1 << M)), 609 * 610 * with 0 <= N < 64 and 0 <= M < 16 611 */ 612 613static void calc_ebrg(int baud, int *n_ret, int *m_ret) 614{ 615 int n, m; 616 617 if (baud == 0) { 618 *n_ret = 0; 619 *m_ret = 0; 620 return; 621 } 622 623 /* 624 * We scale numbers by 10 so that we get better accuracy 625 * without having to use floating point. Here we increment m 626 * until n is within the valid range. 627 */ 628 n = (SAB_BASE_BAUD * 10) / baud; 629 m = 0; 630 while (n >= 640) { 631 n = n / 2; 632 m++; 633 } 634 n = (n+5) / 10; 635 /* 636 * We try very hard to avoid speeds with M == 0 since they may 637 * not work correctly for XTAL frequences above 10 MHz. 638 */ 639 if ((m == 0) && ((n & 1) == 0)) { 640 n = n / 2; 641 m++; 642 } 643 *n_ret = n - 1; 644 *m_ret = m; 645} 646 647/* Internal routine, port->lock is held and local interrupts are disabled. */ 648static void sunsab_convert_to_sab(struct uart_sunsab_port *up, unsigned int cflag, 649 unsigned int iflag, unsigned int baud, 650 unsigned int quot) 651{ 652 unsigned char dafo; 653 int bits, n, m; 654 655 /* Byte size and parity */ 656 switch (cflag & CSIZE) { 657 case CS5: dafo = SAB82532_DAFO_CHL5; bits = 7; break; 658 case CS6: dafo = SAB82532_DAFO_CHL6; bits = 8; break; 659 case CS7: dafo = SAB82532_DAFO_CHL7; bits = 9; break; 660 case CS8: dafo = SAB82532_DAFO_CHL8; bits = 10; break; 661 /* Never happens, but GCC is too dumb to figure it out */ 662 default: dafo = SAB82532_DAFO_CHL5; bits = 7; break; 663 } 664 665 if (cflag & CSTOPB) { 666 dafo |= SAB82532_DAFO_STOP; 667 bits++; 668 } 669 670 if (cflag & PARENB) { 671 dafo |= SAB82532_DAFO_PARE; 672 bits++; 673 } 674 675 if (cflag & PARODD) { 676 dafo |= SAB82532_DAFO_PAR_ODD; 677 } else { 678 dafo |= SAB82532_DAFO_PAR_EVEN; 679 } 680 up->cached_dafo = dafo; 681 682 calc_ebrg(baud, &n, &m); 683 684 up->cached_ebrg = n | (m << 6); 685 686 up->tec_timeout = (10 * 1000000) / baud; 687 up->cec_timeout = up->tec_timeout >> 2; 688 689 /* CTS flow control flags */ 690 /* We encode read_status_mask and ignore_status_mask like so: 691 * 692 * --------------------- 693 * | ... | ISR1 | ISR0 | 694 * --------------------- 695 * .. 15 8 7 0 696 */ 697 698 up->port.read_status_mask = (SAB82532_ISR0_TCD | SAB82532_ISR0_TIME | 699 SAB82532_ISR0_RFO | SAB82532_ISR0_RPF | 700 SAB82532_ISR0_CDSC); 701 up->port.read_status_mask |= (SAB82532_ISR1_CSC | 702 SAB82532_ISR1_ALLS | 703 SAB82532_ISR1_XPR) << 8; 704 if (iflag & INPCK) 705 up->port.read_status_mask |= (SAB82532_ISR0_PERR | 706 SAB82532_ISR0_FERR); 707 if (iflag & (BRKINT | PARMRK)) 708 up->port.read_status_mask |= (SAB82532_ISR1_BRK << 8); 709 710 /* 711 * Characteres to ignore 712 */ 713 up->port.ignore_status_mask = 0; 714 if (iflag & IGNPAR) 715 up->port.ignore_status_mask |= (SAB82532_ISR0_PERR | 716 SAB82532_ISR0_FERR); 717 if (iflag & IGNBRK) { 718 up->port.ignore_status_mask |= (SAB82532_ISR1_BRK << 8); 719 /* 720 * If we're ignoring parity and break indicators, 721 * ignore overruns too (for real raw support). 722 */ 723 if (iflag & IGNPAR) 724 up->port.ignore_status_mask |= SAB82532_ISR0_RFO; 725 } 726 727 /* 728 * ignore all characters if CREAD is not set 729 */ 730 if ((cflag & CREAD) == 0) 731 up->port.ignore_status_mask |= (SAB82532_ISR0_RPF | 732 SAB82532_ISR0_TCD); 733 734 uart_update_timeout(&up->port, cflag, 735 (up->port.uartclk / (16 * quot))); 736 737 /* Now schedule a register update when the chip's 738 * transmitter is idle. 739 */ 740 up->cached_mode |= SAB82532_MODE_RAC; 741 set_bit(SAB82532_REGS_PENDING, &up->irqflags); 742 if (test_bit(SAB82532_XPR, &up->irqflags)) 743 sunsab_tx_idle(up); 744} 745 746/* port->lock is not held. */ 747static void sunsab_set_termios(struct uart_port *port, struct ktermios *termios, 748 struct ktermios *old) 749{ 750 struct uart_sunsab_port *up = (struct uart_sunsab_port *) port; 751 unsigned long flags; 752 unsigned int baud = uart_get_baud_rate(port, termios, old, 0, 4000000); 753 unsigned int quot = uart_get_divisor(port, baud); 754 755 spin_lock_irqsave(&up->port.lock, flags); 756 sunsab_convert_to_sab(up, termios->c_cflag, termios->c_iflag, baud, quot); 757 spin_unlock_irqrestore(&up->port.lock, flags); 758} 759 760static const char *sunsab_type(struct uart_port *port) 761{ 762 struct uart_sunsab_port *up = (void *)port; 763 static char buf[36]; 764 765 sprintf(buf, "SAB82532 %s", sab82532_version[up->type]); 766 return buf; 767} 768 769static void sunsab_release_port(struct uart_port *port) 770{ 771} 772 773static int sunsab_request_port(struct uart_port *port) 774{ 775 return 0; 776} 777 778static void sunsab_config_port(struct uart_port *port, int flags) 779{ 780} 781 782static int sunsab_verify_port(struct uart_port *port, struct serial_struct *ser) 783{ 784 return -EINVAL; 785} 786 787static struct uart_ops sunsab_pops = { 788 .tx_empty = sunsab_tx_empty, 789 .set_mctrl = sunsab_set_mctrl, 790 .get_mctrl = sunsab_get_mctrl, 791 .stop_tx = sunsab_stop_tx, 792 .start_tx = sunsab_start_tx, 793 .send_xchar = sunsab_send_xchar, 794 .stop_rx = sunsab_stop_rx, 795 .enable_ms = sunsab_enable_ms, 796 .break_ctl = sunsab_break_ctl, 797 .startup = sunsab_startup, 798 .shutdown = sunsab_shutdown, 799 .set_termios = sunsab_set_termios, 800 .type = sunsab_type, 801 .release_port = sunsab_release_port, 802 .request_port = sunsab_request_port, 803 .config_port = sunsab_config_port, 804 .verify_port = sunsab_verify_port, 805}; 806 807static struct uart_driver sunsab_reg = { 808 .owner = THIS_MODULE, 809 .driver_name = "sunsab", 810 .dev_name = "ttyS", 811 .major = TTY_MAJOR, 812}; 813 814static struct uart_sunsab_port *sunsab_ports; 815 816#ifdef CONFIG_SERIAL_SUNSAB_CONSOLE 817 818static void sunsab_console_putchar(struct uart_port *port, int c) 819{ 820 struct uart_sunsab_port *up = (struct uart_sunsab_port *)port; 821 822 sunsab_tec_wait(up); 823 writeb(c, &up->regs->w.tic); 824} 825 826static void sunsab_console_write(struct console *con, const char *s, unsigned n) 827{ 828 struct uart_sunsab_port *up = &sunsab_ports[con->index]; 829 unsigned long flags; 830 int locked = 1; 831 832 local_irq_save(flags); 833 if (up->port.sysrq) { 834 locked = 0; 835 } else if (oops_in_progress) { 836 locked = spin_trylock(&up->port.lock); 837 } else 838 spin_lock(&up->port.lock); 839 840 uart_console_write(&up->port, s, n, sunsab_console_putchar); 841 sunsab_tec_wait(up); 842 843 if (locked) 844 spin_unlock(&up->port.lock); 845 local_irq_restore(flags); 846} 847 848static int sunsab_console_setup(struct console *con, char *options) 849{ 850 struct uart_sunsab_port *up = &sunsab_ports[con->index]; 851 unsigned long flags; 852 unsigned int baud, quot; 853 854 /* 855 * The console framework calls us for each and every port 856 * registered. Defer the console setup until the requested 857 * port has been properly discovered. A bit of a hack, 858 * though... 859 */ 860 if (up->port.type != PORT_SUNSAB) 861 return -1; 862 863 printk("Console: ttyS%d (SAB82532)\n", 864 (sunsab_reg.minor - 64) + con->index); 865 866 sunserial_console_termios(con, up->port.dev->of_node); 867 868 switch (con->cflag & CBAUD) { 869 case B150: baud = 150; break; 870 case B300: baud = 300; break; 871 case B600: baud = 600; break; 872 case B1200: baud = 1200; break; 873 case B2400: baud = 2400; break; 874 case B4800: baud = 4800; break; 875 default: case B9600: baud = 9600; break; 876 case B19200: baud = 19200; break; 877 case B38400: baud = 38400; break; 878 case B57600: baud = 57600; break; 879 case B115200: baud = 115200; break; 880 case B230400: baud = 230400; break; 881 case B460800: baud = 460800; break; 882 }; 883 884 /* 885 * Temporary fix. 886 */ 887 spin_lock_init(&up->port.lock); 888 889 /* 890 * Initialize the hardware 891 */ 892 sunsab_startup(&up->port); 893 894 spin_lock_irqsave(&up->port.lock, flags); 895 896 /* 897 * Finally, enable interrupts 898 */ 899 up->interrupt_mask0 = SAB82532_IMR0_PERR | SAB82532_IMR0_FERR | 900 SAB82532_IMR0_PLLA | SAB82532_IMR0_CDSC; 901 writeb(up->interrupt_mask0, &up->regs->w.imr0); 902 up->interrupt_mask1 = SAB82532_IMR1_BRKT | SAB82532_IMR1_ALLS | 903 SAB82532_IMR1_XOFF | SAB82532_IMR1_TIN | 904 SAB82532_IMR1_CSC | SAB82532_IMR1_XON | 905 SAB82532_IMR1_XPR; 906 writeb(up->interrupt_mask1, &up->regs->w.imr1); 907 908 quot = uart_get_divisor(&up->port, baud); 909 sunsab_convert_to_sab(up, con->cflag, 0, baud, quot); 910 sunsab_set_mctrl(&up->port, TIOCM_DTR | TIOCM_RTS); 911 912 spin_unlock_irqrestore(&up->port.lock, flags); 913 914 return 0; 915} 916 917static struct console sunsab_console = { 918 .name = "ttyS", 919 .write = sunsab_console_write, 920 .device = uart_console_device, 921 .setup = sunsab_console_setup, 922 .flags = CON_PRINTBUFFER, 923 .index = -1, 924 .data = &sunsab_reg, 925}; 926 927static inline struct console *SUNSAB_CONSOLE(void) 928{ 929 return &sunsab_console; 930} 931#else 932#define SUNSAB_CONSOLE() (NULL) 933#define sunsab_console_init() do { } while (0) 934#endif 935 936static int __devinit sunsab_init_one(struct uart_sunsab_port *up, 937 struct platform_device *op, 938 unsigned long offset, 939 int line) 940{ 941 up->port.line = line; 942 up->port.dev = &op->dev; 943 944 up->port.mapbase = op->resource[0].start + offset; 945 up->port.membase = of_ioremap(&op->resource[0], offset, 946 sizeof(union sab82532_async_regs), 947 "sab"); 948 if (!up->port.membase) 949 return -ENOMEM; 950 up->regs = (union sab82532_async_regs __iomem *) up->port.membase; 951 952 up->port.irq = op->archdata.irqs[0]; 953 954 up->port.fifosize = SAB82532_XMIT_FIFO_SIZE; 955 up->port.iotype = UPIO_MEM; 956 957 writeb(SAB82532_IPC_IC_ACT_LOW, &up->regs->w.ipc); 958 959 up->port.ops = &sunsab_pops; 960 up->port.type = PORT_SUNSAB; 961 up->port.uartclk = SAB_BASE_BAUD; 962 963 up->type = readb(&up->regs->r.vstr) & 0x0f; 964 writeb(~((1 << 1) | (1 << 2) | (1 << 4)), &up->regs->w.pcr); 965 writeb(0xff, &up->regs->w.pim); 966 if ((up->port.line & 0x1) == 0) { 967 up->pvr_dsr_bit = (1 << 0); 968 up->pvr_dtr_bit = (1 << 1); 969 up->gis_shift = 2; 970 } else { 971 up->pvr_dsr_bit = (1 << 3); 972 up->pvr_dtr_bit = (1 << 2); 973 up->gis_shift = 0; 974 } 975 up->cached_pvr = (1 << 1) | (1 << 2) | (1 << 4); 976 writeb(up->cached_pvr, &up->regs->w.pvr); 977 up->cached_mode = readb(&up->regs->rw.mode); 978 up->cached_mode |= SAB82532_MODE_FRTS; 979 writeb(up->cached_mode, &up->regs->rw.mode); 980 up->cached_mode |= SAB82532_MODE_RTS; 981 writeb(up->cached_mode, &up->regs->rw.mode); 982 983 up->tec_timeout = SAB82532_MAX_TEC_TIMEOUT; 984 up->cec_timeout = SAB82532_MAX_CEC_TIMEOUT; 985 986 return 0; 987} 988 989static int __devinit sab_probe(struct platform_device *op, const struct of_device_id *match) 990{ 991 static int inst; 992 struct uart_sunsab_port *up; 993 int err; 994 995 up = &sunsab_ports[inst * 2]; 996 997 err = sunsab_init_one(&up[0], op, 998 0, 999 (inst * 2) + 0); 1000 if (err) 1001 goto out; 1002 1003 err = sunsab_init_one(&up[1], op, 1004 sizeof(union sab82532_async_regs), 1005 (inst * 2) + 1); 1006 if (err) 1007 goto out1; 1008 1009 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node, 1010 &sunsab_reg, up[0].port.line, 1011 false); 1012 1013 sunserial_console_match(SUNSAB_CONSOLE(), op->dev.of_node, 1014 &sunsab_reg, up[1].port.line, 1015 false); 1016 1017 err = uart_add_one_port(&sunsab_reg, &up[0].port); 1018 if (err) 1019 goto out2; 1020 1021 err = uart_add_one_port(&sunsab_reg, &up[1].port); 1022 if (err) 1023 goto out3; 1024 1025 dev_set_drvdata(&op->dev, &up[0]); 1026 1027 inst++; 1028 1029 return 0; 1030 1031out3: 1032 uart_remove_one_port(&sunsab_reg, &up[0].port); 1033out2: 1034 of_iounmap(&op->resource[0], 1035 up[1].port.membase, 1036 sizeof(union sab82532_async_regs)); 1037out1: 1038 of_iounmap(&op->resource[0], 1039 up[0].port.membase, 1040 sizeof(union sab82532_async_regs)); 1041out: 1042 return err; 1043} 1044 1045static int __devexit sab_remove(struct platform_device *op) 1046{ 1047 struct uart_sunsab_port *up = dev_get_drvdata(&op->dev); 1048 1049 uart_remove_one_port(&sunsab_reg, &up[1].port); 1050 uart_remove_one_port(&sunsab_reg, &up[0].port); 1051 of_iounmap(&op->resource[0], 1052 up[1].port.membase, 1053 sizeof(union sab82532_async_regs)); 1054 of_iounmap(&op->resource[0], 1055 up[0].port.membase, 1056 sizeof(union sab82532_async_regs)); 1057 1058 dev_set_drvdata(&op->dev, NULL); 1059 1060 return 0; 1061} 1062 1063static const struct of_device_id sab_match[] = { 1064 { 1065 .name = "se", 1066 }, 1067 { 1068 .name = "serial", 1069 .compatible = "sab82532", 1070 }, 1071 {}, 1072}; 1073MODULE_DEVICE_TABLE(of, sab_match); 1074 1075static struct of_platform_driver sab_driver = { 1076 .driver = { 1077 .name = "sab", 1078 .owner = THIS_MODULE, 1079 .of_match_table = sab_match, 1080 }, 1081 .probe = sab_probe, 1082 .remove = __devexit_p(sab_remove), 1083}; 1084 1085static int __init sunsab_init(void) 1086{ 1087 struct device_node *dp; 1088 int err; 1089 int num_channels = 0; 1090 1091 for_each_node_by_name(dp, "se") 1092 num_channels += 2; 1093 for_each_node_by_name(dp, "serial") { 1094 if (of_device_is_compatible(dp, "sab82532")) 1095 num_channels += 2; 1096 } 1097 1098 if (num_channels) { 1099 sunsab_ports = kzalloc(sizeof(struct uart_sunsab_port) * 1100 num_channels, GFP_KERNEL); 1101 if (!sunsab_ports) 1102 return -ENOMEM; 1103 1104 err = sunserial_register_minors(&sunsab_reg, num_channels); 1105 if (err) { 1106 kfree(sunsab_ports); 1107 sunsab_ports = NULL; 1108 1109 return err; 1110 } 1111 } 1112 1113 return of_register_platform_driver(&sab_driver); 1114} 1115 1116static void __exit sunsab_exit(void) 1117{ 1118 of_unregister_platform_driver(&sab_driver); 1119 if (sunsab_reg.nr) { 1120 sunserial_unregister_minors(&sunsab_reg, sunsab_reg.nr); 1121 } 1122 1123 kfree(sunsab_ports); 1124 sunsab_ports = NULL; 1125} 1126 1127module_init(sunsab_init); 1128module_exit(sunsab_exit); 1129 1130MODULE_AUTHOR("Eddie C. Dost and David S. Miller"); 1131MODULE_DESCRIPTION("Sun SAB82532 serial port driver"); 1132MODULE_LICENSE("GPL"); 1133