1/* linux/drivers/serial/s3c2412.c 2 * 3 * Driver for Samsung S3C2412 and S3C2413 SoC onboard UARTs. 4 * 5 * Ben Dooks, Copyright (c) 2003-2008 Simtec Electronics 6 * http://armlinux.simtec.co.uk/ 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 as 10 * published by the Free Software Foundation. 11*/ 12 13#include <linux/module.h> 14#include <linux/ioport.h> 15#include <linux/io.h> 16#include <linux/platform_device.h> 17#include <linux/init.h> 18#include <linux/serial_core.h> 19#include <linux/serial.h> 20 21#include <asm/irq.h> 22#include <mach/hardware.h> 23 24#include <plat/regs-serial.h> 25#include <mach/regs-gpio.h> 26 27#include "samsung.h" 28 29static int s3c2412_serial_setsource(struct uart_port *port, 30 struct s3c24xx_uart_clksrc *clk) 31{ 32 unsigned long ucon = rd_regl(port, S3C2410_UCON); 33 34 ucon &= ~S3C2412_UCON_CLKMASK; 35 36 if (strcmp(clk->name, "uclk") == 0) 37 ucon |= S3C2440_UCON_UCLK; 38 else if (strcmp(clk->name, "pclk") == 0) 39 ucon |= S3C2440_UCON_PCLK; 40 else if (strcmp(clk->name, "usysclk") == 0) 41 ucon |= S3C2412_UCON_USYSCLK; 42 else { 43 printk(KERN_ERR "unknown clock source %s\n", clk->name); 44 return -EINVAL; 45 } 46 47 wr_regl(port, S3C2410_UCON, ucon); 48 return 0; 49} 50 51 52static int s3c2412_serial_getsource(struct uart_port *port, 53 struct s3c24xx_uart_clksrc *clk) 54{ 55 unsigned long ucon = rd_regl(port, S3C2410_UCON); 56 57 switch (ucon & S3C2412_UCON_CLKMASK) { 58 case S3C2412_UCON_UCLK: 59 clk->divisor = 1; 60 clk->name = "uclk"; 61 break; 62 63 case S3C2412_UCON_PCLK: 64 case S3C2412_UCON_PCLK2: 65 clk->divisor = 1; 66 clk->name = "pclk"; 67 break; 68 69 case S3C2412_UCON_USYSCLK: 70 clk->divisor = 1; 71 clk->name = "usysclk"; 72 break; 73 } 74 75 return 0; 76} 77 78static int s3c2412_serial_resetport(struct uart_port *port, 79 struct s3c2410_uartcfg *cfg) 80{ 81 unsigned long ucon = rd_regl(port, S3C2410_UCON); 82 83 dbg("%s: port=%p (%08lx), cfg=%p\n", 84 __func__, port, port->mapbase, cfg); 85 86 /* ensure we don't change the clock settings... */ 87 88 ucon &= S3C2412_UCON_CLKMASK; 89 90 wr_regl(port, S3C2410_UCON, ucon | cfg->ucon); 91 wr_regl(port, S3C2410_ULCON, cfg->ulcon); 92 93 /* reset both fifos */ 94 95 wr_regl(port, S3C2410_UFCON, cfg->ufcon | S3C2410_UFCON_RESETBOTH); 96 wr_regl(port, S3C2410_UFCON, cfg->ufcon); 97 98 return 0; 99} 100 101static struct s3c24xx_uart_info s3c2412_uart_inf = { 102 .name = "Samsung S3C2412 UART", 103 .type = PORT_S3C2412, 104 .fifosize = 64, 105 .has_divslot = 1, 106 .rx_fifomask = S3C2440_UFSTAT_RXMASK, 107 .rx_fifoshift = S3C2440_UFSTAT_RXSHIFT, 108 .rx_fifofull = S3C2440_UFSTAT_RXFULL, 109 .tx_fifofull = S3C2440_UFSTAT_TXFULL, 110 .tx_fifomask = S3C2440_UFSTAT_TXMASK, 111 .tx_fifoshift = S3C2440_UFSTAT_TXSHIFT, 112 .get_clksrc = s3c2412_serial_getsource, 113 .set_clksrc = s3c2412_serial_setsource, 114 .reset_port = s3c2412_serial_resetport, 115}; 116 117/* device management */ 118 119static int s3c2412_serial_probe(struct platform_device *dev) 120{ 121 dbg("s3c2440_serial_probe: dev=%p\n", dev); 122 return s3c24xx_serial_probe(dev, &s3c2412_uart_inf); 123} 124 125static struct platform_driver s3c2412_serial_driver = { 126 .probe = s3c2412_serial_probe, 127 .remove = __devexit_p(s3c24xx_serial_remove), 128 .driver = { 129 .name = "s3c2412-uart", 130 .owner = THIS_MODULE, 131 }, 132}; 133 134s3c24xx_console_init(&s3c2412_serial_driver, &s3c2412_uart_inf); 135 136static inline int s3c2412_serial_init(void) 137{ 138 return s3c24xx_serial_init(&s3c2412_serial_driver, &s3c2412_uart_inf); 139} 140 141static inline void s3c2412_serial_exit(void) 142{ 143 platform_driver_unregister(&s3c2412_serial_driver); 144} 145 146module_init(s3c2412_serial_init); 147module_exit(s3c2412_serial_exit); 148 149MODULE_DESCRIPTION("Samsung S3C2412,S3C2413 SoC Serial port driver"); 150MODULE_AUTHOR("Ben Dooks <ben@simtec.co.uk>"); 151MODULE_LICENSE("GPL v2"); 152MODULE_ALIAS("platform:s3c2412-uart"); 153