1/* 2 * linux/drivers/char/amba.c 3 * 4 * Driver for AMBA serial ports 5 * 6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o. 7 * 8 * Copyright 1999 ARM Limited 9 * Copyright (C) 2000 Deep Blue Solutions Ltd. 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 * 16 * This program is distributed in the hope that it will be useful, 17 * but WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 19 * GNU General Public License for more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program; if not, write to the Free Software 23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 24 * 25 * This is a generic driver for ARM AMBA-type serial ports. They 26 * have a lot of 16550-like features, but are not register compatible. 27 * Note that although they do have CTS, DCD and DSR inputs, they do 28 * not have an RI input, nor do they have DTR or RTS outputs. If 29 * required, these have to be supplied via some other means (eg, GPIO) 30 * and hooked into this driver. 31 */ 32 33#if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ) 34#define SUPPORT_SYSRQ 35#endif 36 37#include <linux/module.h> 38#include <linux/ioport.h> 39#include <linux/init.h> 40#include <linux/console.h> 41#include <linux/sysrq.h> 42#include <linux/device.h> 43#include <linux/tty.h> 44#include <linux/tty_flip.h> 45#include <linux/serial_core.h> 46#include <linux/serial.h> 47#include <linux/amba/bus.h> 48#include <linux/amba/serial.h> 49#include <linux/clk.h> 50#include <linux/slab.h> 51 52#include <asm/io.h> 53 54#define UART_NR 8 55 56#define SERIAL_AMBA_MAJOR 204 57#define SERIAL_AMBA_MINOR 16 58#define SERIAL_AMBA_NR UART_NR 59 60#define AMBA_ISR_PASS_LIMIT 256 61 62#define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0) 63#define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0) 64 65#define UART_DUMMY_RSR_RX 256 66#define UART_PORT_SIZE 64 67 68/* 69 * We wrap our port structure around the generic uart_port. 70 */ 71struct uart_amba_port { 72 struct uart_port port; 73 struct clk *clk; 74 struct amba_device *dev; 75 struct amba_pl010_data *data; 76 unsigned int old_status; 77}; 78 79static void pl010_stop_tx(struct uart_port *port) 80{ 81 struct uart_amba_port *uap = (struct uart_amba_port *)port; 82 unsigned int cr; 83 84 cr = readb(uap->port.membase + UART010_CR); 85 cr &= ~UART010_CR_TIE; 86 writel(cr, uap->port.membase + UART010_CR); 87} 88 89static void pl010_start_tx(struct uart_port *port) 90{ 91 struct uart_amba_port *uap = (struct uart_amba_port *)port; 92 unsigned int cr; 93 94 cr = readb(uap->port.membase + UART010_CR); 95 cr |= UART010_CR_TIE; 96 writel(cr, uap->port.membase + UART010_CR); 97} 98 99static void pl010_stop_rx(struct uart_port *port) 100{ 101 struct uart_amba_port *uap = (struct uart_amba_port *)port; 102 unsigned int cr; 103 104 cr = readb(uap->port.membase + UART010_CR); 105 cr &= ~(UART010_CR_RIE | UART010_CR_RTIE); 106 writel(cr, uap->port.membase + UART010_CR); 107} 108 109static void pl010_enable_ms(struct uart_port *port) 110{ 111 struct uart_amba_port *uap = (struct uart_amba_port *)port; 112 unsigned int cr; 113 114 cr = readb(uap->port.membase + UART010_CR); 115 cr |= UART010_CR_MSIE; 116 writel(cr, uap->port.membase + UART010_CR); 117} 118 119static void pl010_rx_chars(struct uart_amba_port *uap) 120{ 121 struct tty_struct *tty = uap->port.state->port.tty; 122 unsigned int status, ch, flag, rsr, max_count = 256; 123 124 status = readb(uap->port.membase + UART01x_FR); 125 while (UART_RX_DATA(status) && max_count--) { 126 ch = readb(uap->port.membase + UART01x_DR); 127 flag = TTY_NORMAL; 128 129 uap->port.icount.rx++; 130 131 /* 132 * Note that the error handling code is 133 * out of the main execution path 134 */ 135 rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX; 136 if (unlikely(rsr & UART01x_RSR_ANY)) { 137 writel(0, uap->port.membase + UART01x_ECR); 138 139 if (rsr & UART01x_RSR_BE) { 140 rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE); 141 uap->port.icount.brk++; 142 if (uart_handle_break(&uap->port)) 143 goto ignore_char; 144 } else if (rsr & UART01x_RSR_PE) 145 uap->port.icount.parity++; 146 else if (rsr & UART01x_RSR_FE) 147 uap->port.icount.frame++; 148 if (rsr & UART01x_RSR_OE) 149 uap->port.icount.overrun++; 150 151 rsr &= uap->port.read_status_mask; 152 153 if (rsr & UART01x_RSR_BE) 154 flag = TTY_BREAK; 155 else if (rsr & UART01x_RSR_PE) 156 flag = TTY_PARITY; 157 else if (rsr & UART01x_RSR_FE) 158 flag = TTY_FRAME; 159 } 160 161 if (uart_handle_sysrq_char(&uap->port, ch)) 162 goto ignore_char; 163 164 uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag); 165 166 ignore_char: 167 status = readb(uap->port.membase + UART01x_FR); 168 } 169 spin_unlock(&uap->port.lock); 170 tty_flip_buffer_push(tty); 171 spin_lock(&uap->port.lock); 172} 173 174static void pl010_tx_chars(struct uart_amba_port *uap) 175{ 176 struct circ_buf *xmit = &uap->port.state->xmit; 177 int count; 178 179 if (uap->port.x_char) { 180 writel(uap->port.x_char, uap->port.membase + UART01x_DR); 181 uap->port.icount.tx++; 182 uap->port.x_char = 0; 183 return; 184 } 185 if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) { 186 pl010_stop_tx(&uap->port); 187 return; 188 } 189 190 count = uap->port.fifosize >> 1; 191 do { 192 writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR); 193 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1); 194 uap->port.icount.tx++; 195 if (uart_circ_empty(xmit)) 196 break; 197 } while (--count > 0); 198 199 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS) 200 uart_write_wakeup(&uap->port); 201 202 if (uart_circ_empty(xmit)) 203 pl010_stop_tx(&uap->port); 204} 205 206static void pl010_modem_status(struct uart_amba_port *uap) 207{ 208 unsigned int status, delta; 209 210 writel(0, uap->port.membase + UART010_ICR); 211 212 status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 213 214 delta = status ^ uap->old_status; 215 uap->old_status = status; 216 217 if (!delta) 218 return; 219 220 if (delta & UART01x_FR_DCD) 221 uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD); 222 223 if (delta & UART01x_FR_DSR) 224 uap->port.icount.dsr++; 225 226 if (delta & UART01x_FR_CTS) 227 uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS); 228 229 wake_up_interruptible(&uap->port.state->port.delta_msr_wait); 230} 231 232static irqreturn_t pl010_int(int irq, void *dev_id) 233{ 234 struct uart_amba_port *uap = dev_id; 235 unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT; 236 int handled = 0; 237 238 spin_lock(&uap->port.lock); 239 240 status = readb(uap->port.membase + UART010_IIR); 241 if (status) { 242 do { 243 if (status & (UART010_IIR_RTIS | UART010_IIR_RIS)) 244 pl010_rx_chars(uap); 245 if (status & UART010_IIR_MIS) 246 pl010_modem_status(uap); 247 if (status & UART010_IIR_TIS) 248 pl010_tx_chars(uap); 249 250 if (pass_counter-- == 0) 251 break; 252 253 status = readb(uap->port.membase + UART010_IIR); 254 } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS | 255 UART010_IIR_TIS)); 256 handled = 1; 257 } 258 259 spin_unlock(&uap->port.lock); 260 261 return IRQ_RETVAL(handled); 262} 263 264static unsigned int pl010_tx_empty(struct uart_port *port) 265{ 266 struct uart_amba_port *uap = (struct uart_amba_port *)port; 267 unsigned int status = readb(uap->port.membase + UART01x_FR); 268 return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT; 269} 270 271static unsigned int pl010_get_mctrl(struct uart_port *port) 272{ 273 struct uart_amba_port *uap = (struct uart_amba_port *)port; 274 unsigned int result = 0; 275 unsigned int status; 276 277 status = readb(uap->port.membase + UART01x_FR); 278 if (status & UART01x_FR_DCD) 279 result |= TIOCM_CAR; 280 if (status & UART01x_FR_DSR) 281 result |= TIOCM_DSR; 282 if (status & UART01x_FR_CTS) 283 result |= TIOCM_CTS; 284 285 return result; 286} 287 288static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl) 289{ 290 struct uart_amba_port *uap = (struct uart_amba_port *)port; 291 292 if (uap->data) 293 uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl); 294} 295 296static void pl010_break_ctl(struct uart_port *port, int break_state) 297{ 298 struct uart_amba_port *uap = (struct uart_amba_port *)port; 299 unsigned long flags; 300 unsigned int lcr_h; 301 302 spin_lock_irqsave(&uap->port.lock, flags); 303 lcr_h = readb(uap->port.membase + UART010_LCRH); 304 if (break_state == -1) 305 lcr_h |= UART01x_LCRH_BRK; 306 else 307 lcr_h &= ~UART01x_LCRH_BRK; 308 writel(lcr_h, uap->port.membase + UART010_LCRH); 309 spin_unlock_irqrestore(&uap->port.lock, flags); 310} 311 312static int pl010_startup(struct uart_port *port) 313{ 314 struct uart_amba_port *uap = (struct uart_amba_port *)port; 315 int retval; 316 317 /* 318 * Try to enable the clock producer. 319 */ 320 retval = clk_enable(uap->clk); 321 if (retval) 322 goto out; 323 324 uap->port.uartclk = clk_get_rate(uap->clk); 325 326 /* 327 * Allocate the IRQ 328 */ 329 retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap); 330 if (retval) 331 goto clk_dis; 332 333 /* 334 * initialise the old status of the modem signals 335 */ 336 uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY; 337 338 /* 339 * Finally, enable interrupts 340 */ 341 writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE, 342 uap->port.membase + UART010_CR); 343 344 return 0; 345 346 clk_dis: 347 clk_disable(uap->clk); 348 out: 349 return retval; 350} 351 352static void pl010_shutdown(struct uart_port *port) 353{ 354 struct uart_amba_port *uap = (struct uart_amba_port *)port; 355 356 /* 357 * Free the interrupt 358 */ 359 free_irq(uap->port.irq, uap); 360 361 /* 362 * disable all interrupts, disable the port 363 */ 364 writel(0, uap->port.membase + UART010_CR); 365 366 /* disable break condition and fifos */ 367 writel(readb(uap->port.membase + UART010_LCRH) & 368 ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN), 369 uap->port.membase + UART010_LCRH); 370 371 /* 372 * Shut down the clock producer 373 */ 374 clk_disable(uap->clk); 375} 376 377static void 378pl010_set_termios(struct uart_port *port, struct ktermios *termios, 379 struct ktermios *old) 380{ 381 struct uart_amba_port *uap = (struct uart_amba_port *)port; 382 unsigned int lcr_h, old_cr; 383 unsigned long flags; 384 unsigned int baud, quot; 385 386 /* 387 * Ask the core to calculate the divisor for us. 388 */ 389 baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16); 390 quot = uart_get_divisor(port, baud); 391 392 switch (termios->c_cflag & CSIZE) { 393 case CS5: 394 lcr_h = UART01x_LCRH_WLEN_5; 395 break; 396 case CS6: 397 lcr_h = UART01x_LCRH_WLEN_6; 398 break; 399 case CS7: 400 lcr_h = UART01x_LCRH_WLEN_7; 401 break; 402 default: // CS8 403 lcr_h = UART01x_LCRH_WLEN_8; 404 break; 405 } 406 if (termios->c_cflag & CSTOPB) 407 lcr_h |= UART01x_LCRH_STP2; 408 if (termios->c_cflag & PARENB) { 409 lcr_h |= UART01x_LCRH_PEN; 410 if (!(termios->c_cflag & PARODD)) 411 lcr_h |= UART01x_LCRH_EPS; 412 } 413 if (uap->port.fifosize > 1) 414 lcr_h |= UART01x_LCRH_FEN; 415 416 spin_lock_irqsave(&uap->port.lock, flags); 417 418 /* 419 * Update the per-port timeout. 420 */ 421 uart_update_timeout(port, termios->c_cflag, baud); 422 423 uap->port.read_status_mask = UART01x_RSR_OE; 424 if (termios->c_iflag & INPCK) 425 uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 426 if (termios->c_iflag & (BRKINT | PARMRK)) 427 uap->port.read_status_mask |= UART01x_RSR_BE; 428 429 /* 430 * Characters to ignore 431 */ 432 uap->port.ignore_status_mask = 0; 433 if (termios->c_iflag & IGNPAR) 434 uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE; 435 if (termios->c_iflag & IGNBRK) { 436 uap->port.ignore_status_mask |= UART01x_RSR_BE; 437 /* 438 * If we're ignoring parity and break indicators, 439 * ignore overruns too (for real raw support). 440 */ 441 if (termios->c_iflag & IGNPAR) 442 uap->port.ignore_status_mask |= UART01x_RSR_OE; 443 } 444 445 /* 446 * Ignore all characters if CREAD is not set. 447 */ 448 if ((termios->c_cflag & CREAD) == 0) 449 uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX; 450 451 /* first, disable everything */ 452 old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE; 453 454 if (UART_ENABLE_MS(port, termios->c_cflag)) 455 old_cr |= UART010_CR_MSIE; 456 457 writel(0, uap->port.membase + UART010_CR); 458 459 /* Set baud rate */ 460 quot -= 1; 461 writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM); 462 writel(quot & 0xff, uap->port.membase + UART010_LCRL); 463 464 /* 465 * ----------v----------v----------v----------v----- 466 * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L 467 * ----------^----------^----------^----------^----- 468 */ 469 writel(lcr_h, uap->port.membase + UART010_LCRH); 470 writel(old_cr, uap->port.membase + UART010_CR); 471 472 spin_unlock_irqrestore(&uap->port.lock, flags); 473} 474 475static void pl010_set_ldisc(struct uart_port *port, int new) 476{ 477 if (new == N_PPS) { 478 port->flags |= UPF_HARDPPS_CD; 479 pl010_enable_ms(port); 480 } else 481 port->flags &= ~UPF_HARDPPS_CD; 482} 483 484static const char *pl010_type(struct uart_port *port) 485{ 486 return port->type == PORT_AMBA ? "AMBA" : NULL; 487} 488 489/* 490 * Release the memory region(s) being used by 'port' 491 */ 492static void pl010_release_port(struct uart_port *port) 493{ 494 release_mem_region(port->mapbase, UART_PORT_SIZE); 495} 496 497/* 498 * Request the memory region(s) being used by 'port' 499 */ 500static int pl010_request_port(struct uart_port *port) 501{ 502 return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010") 503 != NULL ? 0 : -EBUSY; 504} 505 506/* 507 * Configure/autoconfigure the port. 508 */ 509static void pl010_config_port(struct uart_port *port, int flags) 510{ 511 if (flags & UART_CONFIG_TYPE) { 512 port->type = PORT_AMBA; 513 pl010_request_port(port); 514 } 515} 516 517/* 518 * verify the new serial_struct (for TIOCSSERIAL). 519 */ 520static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser) 521{ 522 int ret = 0; 523 if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA) 524 ret = -EINVAL; 525 if (ser->irq < 0 || ser->irq >= nr_irqs) 526 ret = -EINVAL; 527 if (ser->baud_base < 9600) 528 ret = -EINVAL; 529 return ret; 530} 531 532static struct uart_ops amba_pl010_pops = { 533 .tx_empty = pl010_tx_empty, 534 .set_mctrl = pl010_set_mctrl, 535 .get_mctrl = pl010_get_mctrl, 536 .stop_tx = pl010_stop_tx, 537 .start_tx = pl010_start_tx, 538 .stop_rx = pl010_stop_rx, 539 .enable_ms = pl010_enable_ms, 540 .break_ctl = pl010_break_ctl, 541 .startup = pl010_startup, 542 .shutdown = pl010_shutdown, 543 .set_termios = pl010_set_termios, 544 .set_ldisc = pl010_set_ldisc, 545 .type = pl010_type, 546 .release_port = pl010_release_port, 547 .request_port = pl010_request_port, 548 .config_port = pl010_config_port, 549 .verify_port = pl010_verify_port, 550}; 551 552static struct uart_amba_port *amba_ports[UART_NR]; 553 554#ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE 555 556static void pl010_console_putchar(struct uart_port *port, int ch) 557{ 558 struct uart_amba_port *uap = (struct uart_amba_port *)port; 559 unsigned int status; 560 561 do { 562 status = readb(uap->port.membase + UART01x_FR); 563 barrier(); 564 } while (!UART_TX_READY(status)); 565 writel(ch, uap->port.membase + UART01x_DR); 566} 567 568static void 569pl010_console_write(struct console *co, const char *s, unsigned int count) 570{ 571 struct uart_amba_port *uap = amba_ports[co->index]; 572 unsigned int status, old_cr; 573 574 clk_enable(uap->clk); 575 576 /* 577 * First save the CR then disable the interrupts 578 */ 579 old_cr = readb(uap->port.membase + UART010_CR); 580 writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR); 581 582 uart_console_write(&uap->port, s, count, pl010_console_putchar); 583 584 /* 585 * Finally, wait for transmitter to become empty 586 * and restore the TCR 587 */ 588 do { 589 status = readb(uap->port.membase + UART01x_FR); 590 barrier(); 591 } while (status & UART01x_FR_BUSY); 592 writel(old_cr, uap->port.membase + UART010_CR); 593 594 clk_disable(uap->clk); 595} 596 597static void __init 598pl010_console_get_options(struct uart_amba_port *uap, int *baud, 599 int *parity, int *bits) 600{ 601 if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) { 602 unsigned int lcr_h, quot; 603 lcr_h = readb(uap->port.membase + UART010_LCRH); 604 605 *parity = 'n'; 606 if (lcr_h & UART01x_LCRH_PEN) { 607 if (lcr_h & UART01x_LCRH_EPS) 608 *parity = 'e'; 609 else 610 *parity = 'o'; 611 } 612 613 if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7) 614 *bits = 7; 615 else 616 *bits = 8; 617 618 quot = readb(uap->port.membase + UART010_LCRL) | 619 readb(uap->port.membase + UART010_LCRM) << 8; 620 *baud = uap->port.uartclk / (16 * (quot + 1)); 621 } 622} 623 624static int __init pl010_console_setup(struct console *co, char *options) 625{ 626 struct uart_amba_port *uap; 627 int baud = 38400; 628 int bits = 8; 629 int parity = 'n'; 630 int flow = 'n'; 631 632 /* 633 * Check whether an invalid uart number has been specified, and 634 * if so, search for the first available port that does have 635 * console support. 636 */ 637 if (co->index >= UART_NR) 638 co->index = 0; 639 uap = amba_ports[co->index]; 640 if (!uap) 641 return -ENODEV; 642 643 uap->port.uartclk = clk_get_rate(uap->clk); 644 645 if (options) 646 uart_parse_options(options, &baud, &parity, &bits, &flow); 647 else 648 pl010_console_get_options(uap, &baud, &parity, &bits); 649 650 return uart_set_options(&uap->port, co, baud, parity, bits, flow); 651} 652 653static struct uart_driver amba_reg; 654static struct console amba_console = { 655 .name = "ttyAM", 656 .write = pl010_console_write, 657 .device = uart_console_device, 658 .setup = pl010_console_setup, 659 .flags = CON_PRINTBUFFER, 660 .index = -1, 661 .data = &amba_reg, 662}; 663 664#define AMBA_CONSOLE &amba_console 665#else 666#define AMBA_CONSOLE NULL 667#endif 668 669static struct uart_driver amba_reg = { 670 .owner = THIS_MODULE, 671 .driver_name = "ttyAM", 672 .dev_name = "ttyAM", 673 .major = SERIAL_AMBA_MAJOR, 674 .minor = SERIAL_AMBA_MINOR, 675 .nr = UART_NR, 676 .cons = AMBA_CONSOLE, 677}; 678 679static int pl010_probe(struct amba_device *dev, struct amba_id *id) 680{ 681 struct uart_amba_port *uap; 682 void __iomem *base; 683 int i, ret; 684 685 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 686 if (amba_ports[i] == NULL) 687 break; 688 689 if (i == ARRAY_SIZE(amba_ports)) { 690 ret = -EBUSY; 691 goto out; 692 } 693 694 uap = kzalloc(sizeof(struct uart_amba_port), GFP_KERNEL); 695 if (!uap) { 696 ret = -ENOMEM; 697 goto out; 698 } 699 700 base = ioremap(dev->res.start, resource_size(&dev->res)); 701 if (!base) { 702 ret = -ENOMEM; 703 goto free; 704 } 705 706 uap->clk = clk_get(&dev->dev, NULL); 707 if (IS_ERR(uap->clk)) { 708 ret = PTR_ERR(uap->clk); 709 goto unmap; 710 } 711 712 uap->port.dev = &dev->dev; 713 uap->port.mapbase = dev->res.start; 714 uap->port.membase = base; 715 uap->port.iotype = UPIO_MEM; 716 uap->port.irq = dev->irq[0]; 717 uap->port.fifosize = 16; 718 uap->port.ops = &amba_pl010_pops; 719 uap->port.flags = UPF_BOOT_AUTOCONF; 720 uap->port.line = i; 721 uap->dev = dev; 722 uap->data = dev->dev.platform_data; 723 724 amba_ports[i] = uap; 725 726 amba_set_drvdata(dev, uap); 727 ret = uart_add_one_port(&amba_reg, &uap->port); 728 if (ret) { 729 amba_set_drvdata(dev, NULL); 730 amba_ports[i] = NULL; 731 clk_put(uap->clk); 732 unmap: 733 iounmap(base); 734 free: 735 kfree(uap); 736 } 737 out: 738 return ret; 739} 740 741static int pl010_remove(struct amba_device *dev) 742{ 743 struct uart_amba_port *uap = amba_get_drvdata(dev); 744 int i; 745 746 amba_set_drvdata(dev, NULL); 747 748 uart_remove_one_port(&amba_reg, &uap->port); 749 750 for (i = 0; i < ARRAY_SIZE(amba_ports); i++) 751 if (amba_ports[i] == uap) 752 amba_ports[i] = NULL; 753 754 iounmap(uap->port.membase); 755 clk_put(uap->clk); 756 kfree(uap); 757 return 0; 758} 759 760static int pl010_suspend(struct amba_device *dev, pm_message_t state) 761{ 762 struct uart_amba_port *uap = amba_get_drvdata(dev); 763 764 if (uap) 765 uart_suspend_port(&amba_reg, &uap->port); 766 767 return 0; 768} 769 770static int pl010_resume(struct amba_device *dev) 771{ 772 struct uart_amba_port *uap = amba_get_drvdata(dev); 773 774 if (uap) 775 uart_resume_port(&amba_reg, &uap->port); 776 777 return 0; 778} 779 780static struct amba_id pl010_ids[] = { 781 { 782 .id = 0x00041010, 783 .mask = 0x000fffff, 784 }, 785 { 0, 0 }, 786}; 787 788static struct amba_driver pl010_driver = { 789 .drv = { 790 .name = "uart-pl010", 791 }, 792 .id_table = pl010_ids, 793 .probe = pl010_probe, 794 .remove = pl010_remove, 795 .suspend = pl010_suspend, 796 .resume = pl010_resume, 797}; 798 799static int __init pl010_init(void) 800{ 801 int ret; 802 803 printk(KERN_INFO "Serial: AMBA driver\n"); 804 805 ret = uart_register_driver(&amba_reg); 806 if (ret == 0) { 807 ret = amba_driver_register(&pl010_driver); 808 if (ret) 809 uart_unregister_driver(&amba_reg); 810 } 811 return ret; 812} 813 814static void __exit pl010_exit(void) 815{ 816 amba_driver_unregister(&pl010_driver); 817 uart_unregister_driver(&amba_reg); 818} 819 820module_init(pl010_init); 821module_exit(pl010_exit); 822 823MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd"); 824MODULE_DESCRIPTION("ARM AMBA serial port driver"); 825MODULE_LICENSE("GPL"); 826