1/* 2******************************************************************************* 3** O.S : Linux 4** FILE NAME : arcmsr.h 5** BY : Erich Chen 6** Description: SCSI RAID Device Driver for 7** ARECA RAID Host adapter 8******************************************************************************* 9** Copyright (C) 2002 - 2005, Areca Technology Corporation All rights reserved. 10** 11** Web site: www.areca.com.tw 12** E-mail: support@areca.com.tw 13** 14** This program is free software; you can redistribute it and/or modify 15** it under the terms of the GNU General Public License version 2 as 16** published by the Free Software Foundation. 17** This program is distributed in the hope that it will be useful, 18** but WITHOUT ANY WARRANTY; without even the implied warranty of 19** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20** GNU General Public License for more details. 21******************************************************************************* 22** Redistribution and use in source and binary forms, with or without 23** modification, are permitted provided that the following conditions 24** are met: 25** 1. Redistributions of source code must retain the above copyright 26** notice, this list of conditions and the following disclaimer. 27** 2. Redistributions in binary form must reproduce the above copyright 28** notice, this list of conditions and the following disclaimer in the 29** documentation and/or other materials provided with the distribution. 30** 3. The name of the author may not be used to endorse or promote products 31** derived from this software without specific prior written permission. 32** 33** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 34** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 35** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 36** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 37** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 38** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 39** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 40** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 41**(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 42** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 43******************************************************************************* 44*/ 45#include <linux/interrupt.h> 46struct device_attribute; 47/*The limit of outstanding scsi command that firmware can handle*/ 48#define ARCMSR_MAX_OUTSTANDING_CMD 256 49#define ARCMSR_MAX_FREECCB_NUM 320 50#define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.15 2010/02/02" 51#define ARCMSR_SCSI_INITIATOR_ID 255 52#define ARCMSR_MAX_XFER_SECTORS 512 53#define ARCMSR_MAX_XFER_SECTORS_B 4096 54#define ARCMSR_MAX_XFER_SECTORS_C 304 55#define ARCMSR_MAX_TARGETID 17 56#define ARCMSR_MAX_TARGETLUN 8 57#define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 58#define ARCMSR_MAX_QBUFFER 4096 59#define ARCMSR_DEFAULT_SG_ENTRIES 38 60#define ARCMSR_MAX_HBB_POSTQUEUE 264 61#define ARCMSR_MAX_XFER_LEN 0x26000 /* 152K */ 62#define ARCMSR_CDB_SG_PAGE_LENGTH 256 63#define SCSI_CMD_ARECA_SPECIFIC 0xE1 64#ifndef PCI_DEVICE_ID_ARECA_1880 65#define PCI_DEVICE_ID_ARECA_1880 0x1880 66 #endif 67/* 68********************************************************************************** 69** 70********************************************************************************** 71*/ 72#define ARC_SUCCESS 0 73#define ARC_FAILURE 1 74/* 75******************************************************************************* 76** split 64bits dma addressing 77******************************************************************************* 78*/ 79#define dma_addr_hi32(addr) (uint32_t) ((addr>>16)>>16) 80#define dma_addr_lo32(addr) (uint32_t) (addr & 0xffffffff) 81/* 82******************************************************************************* 83** MESSAGE CONTROL CODE 84******************************************************************************* 85*/ 86struct CMD_MESSAGE 87{ 88 uint32_t HeaderLength; 89 uint8_t Signature[8]; 90 uint32_t Timeout; 91 uint32_t ControlCode; 92 uint32_t ReturnCode; 93 uint32_t Length; 94}; 95/* 96******************************************************************************* 97** IOP Message Transfer Data for user space 98******************************************************************************* 99*/ 100struct CMD_MESSAGE_FIELD 101{ 102 struct CMD_MESSAGE cmdmessage; 103 uint8_t messagedatabuffer[1032]; 104}; 105/* IOP message transfer */ 106#define ARCMSR_MESSAGE_FAIL 0x0001 107/* DeviceType */ 108#define ARECA_SATA_RAID 0x90000000 109/* FunctionCode */ 110#define FUNCTION_READ_RQBUFFER 0x0801 111#define FUNCTION_WRITE_WQBUFFER 0x0802 112#define FUNCTION_CLEAR_RQBUFFER 0x0803 113#define FUNCTION_CLEAR_WQBUFFER 0x0804 114#define FUNCTION_CLEAR_ALLQBUFFER 0x0805 115#define FUNCTION_RETURN_CODE_3F 0x0806 116#define FUNCTION_SAY_HELLO 0x0807 117#define FUNCTION_SAY_GOODBYE 0x0808 118#define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 119#define FUNCTION_GET_FIRMWARE_STATUS 0x080A 120#define FUNCTION_HARDWARE_RESET 0x080B 121/* ARECA IO CONTROL CODE*/ 122#define ARCMSR_MESSAGE_READ_RQBUFFER \ 123 ARECA_SATA_RAID | FUNCTION_READ_RQBUFFER 124#define ARCMSR_MESSAGE_WRITE_WQBUFFER \ 125 ARECA_SATA_RAID | FUNCTION_WRITE_WQBUFFER 126#define ARCMSR_MESSAGE_CLEAR_RQBUFFER \ 127 ARECA_SATA_RAID | FUNCTION_CLEAR_RQBUFFER 128#define ARCMSR_MESSAGE_CLEAR_WQBUFFER \ 129 ARECA_SATA_RAID | FUNCTION_CLEAR_WQBUFFER 130#define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER \ 131 ARECA_SATA_RAID | FUNCTION_CLEAR_ALLQBUFFER 132#define ARCMSR_MESSAGE_RETURN_CODE_3F \ 133 ARECA_SATA_RAID | FUNCTION_RETURN_CODE_3F 134#define ARCMSR_MESSAGE_SAY_HELLO \ 135 ARECA_SATA_RAID | FUNCTION_SAY_HELLO 136#define ARCMSR_MESSAGE_SAY_GOODBYE \ 137 ARECA_SATA_RAID | FUNCTION_SAY_GOODBYE 138#define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE \ 139 ARECA_SATA_RAID | FUNCTION_FLUSH_ADAPTER_CACHE 140/* ARECA IOCTL ReturnCode */ 141#define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 142#define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 143#define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 144#define ARCMSR_MESSAGE_RETURNCODE_BUS_HANG_ON 0x00000088 145/* 146************************************************************* 147** structure for holding DMA address data 148************************************************************* 149*/ 150#define IS_DMA64 (sizeof(dma_addr_t) == 8) 151#define IS_SG64_ADDR 0x01000000 /* bit24 */ 152struct SG32ENTRY 153{ 154 __le32 length; 155 __le32 address; 156}__attribute__ ((packed)); 157struct SG64ENTRY 158{ 159 __le32 length; 160 __le32 address; 161 __le32 addresshigh; 162}__attribute__ ((packed)); 163/* 164******************************************************************** 165** Q Buffer of IOP Message Transfer 166******************************************************************** 167*/ 168struct QBUFFER 169{ 170 uint32_t data_len; 171 uint8_t data[124]; 172}; 173/* 174******************************************************************************* 175** FIRMWARE INFO for Intel IOP R 80331 processor (Type A) 176******************************************************************************* 177*/ 178struct FIRMWARE_INFO 179{ 180 uint32_t signature; /*0, 00-03*/ 181 uint32_t request_len; /*1, 04-07*/ 182 uint32_t numbers_queue; /*2, 08-11*/ 183 uint32_t sdram_size; /*3, 12-15*/ 184 uint32_t ide_channels; /*4, 16-19*/ 185 char vendor[40]; /*5, 20-59*/ 186 char model[8]; /*15, 60-67*/ 187 char firmware_ver[16]; /*17, 68-83*/ 188 char device_map[16]; /*21, 84-99*/ 189 uint32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 190 uint8_t cfgSerial[16]; /*26,104-119*/ 191 uint32_t cfgPicStatus; /*30,120-123*/ 192}; 193/* signature of set and get firmware config */ 194#define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 195#define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 196/* message code of inbound message register */ 197#define ARCMSR_INBOUND_MESG0_NOP 0x00000000 198#define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 199#define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 200#define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 201#define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 202#define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 203#define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 204#define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 205#define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 206/* doorbell interrupt generator */ 207#define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 208#define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 209#define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 210#define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 211/* ccb areca cdb flag */ 212#define ARCMSR_CCBPOST_FLAG_SGL_BSIZE 0x80000000 213#define ARCMSR_CCBPOST_FLAG_IAM_BIOS 0x40000000 214#define ARCMSR_CCBREPLY_FLAG_IAM_BIOS 0x40000000 215#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE0 0x10000000 216#define ARCMSR_CCBREPLY_FLAG_ERROR_MODE1 0x00000001 217/* outbound firmware ok */ 218#define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 219/* ARC-1680 Bus Reset*/ 220#define ARCMSR_ARC1680_BUS_RESET 0x00000003 221/* ARC-1880 Bus Reset*/ 222#define ARCMSR_ARC1880_RESET_ADAPTER 0x00000024 223#define ARCMSR_ARC1880_DiagWrite_ENABLE 0x00000080 224 225/* 226************************************************************************ 227** SPEC. for Areca Type B adapter 228************************************************************************ 229*/ 230/* ARECA HBB COMMAND for its FIRMWARE */ 231/* window of "instruction flags" from driver to iop */ 232#define ARCMSR_DRV2IOP_DOORBELL 0x00020400 233#define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 234/* window of "instruction flags" from iop to driver */ 235#define ARCMSR_IOP2DRV_DOORBELL 0x00020408 236#define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 237/* ARECA FLAG LANGUAGE */ 238/* ioctl transfer */ 239#define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 240/* ioctl transfer */ 241#define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 242#define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 243#define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 244 245#define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 246#define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 247#define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 248/* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 249#define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 250/* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 251#define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 252/* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 253#define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 254/* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 255#define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 256/* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 257#define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 258/* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 259#define ARCMSR_MESSAGE_START_BGRB 0x00060008 260#define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 261#define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 262#define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 263/* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 264#define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 265/* ioctl transfer */ 266#define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 267/* ioctl transfer */ 268#define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 269#define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 270#define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 271#define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 272 273/* data tunnel buffer between user space program and its firmware */ 274/* user space data to iop 128bytes */ 275#define ARCMSR_MESSAGE_WBUFFER 0x0000fe00 276/* iop data to user space 128bytes */ 277#define ARCMSR_MESSAGE_RBUFFER 0x0000ff00 278/* iop message_rwbuffer for message command */ 279#define ARCMSR_MESSAGE_RWBUFFER 0x0000fa00 280/* 281************************************************************************ 282** SPEC. for Areca HBC adapter 283************************************************************************ 284*/ 285#define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 286#define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 287/* Host Interrupt Mask */ 288#define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 289#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 290#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 291#define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 292/* Host Interrupt Status */ 293#define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 294 /* 295 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 296 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 297 */ 298#define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 299 /* 300 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 301 ** value. This bit clears only when Outbound Doorbell bits 302 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 303 ** Clear register clears bits in the Outbound Doorbell register. 304 */ 305#define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 306 /* 307 ** Set whenever the Outbound Post List Producer/Consumer 308 ** Register (FIFO) is not empty. It clears when the Outbound 309 ** Post List FIFO is empty. 310 */ 311#define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 312 /* 313 ** This bit indicates a SAS interrupt from a source external to 314 ** the PCIe core. This bit is not maskable. 315 */ 316 /* DoorBell*/ 317#define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002 318#define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004 319 /*inbound message 0 ready*/ 320#define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 321 /*more than 12 request completed in a time*/ 322#define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010 323#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002 324 /*outbound DATA WRITE isr door bell clear*/ 325#define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002 326#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004 327 /*outbound DATA READ isr door bell clear*/ 328#define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004 329 /*outbound message 0 ready*/ 330#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 331 /*outbound message cmd isr door bell clear*/ 332#define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008 333 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 334#define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000 335/* 336******************************************************************************* 337** ARECA SCSI COMMAND DESCRIPTOR BLOCK size 0x1F8 (504) 338******************************************************************************* 339*/ 340struct ARCMSR_CDB 341{ 342 uint8_t Bus; 343 uint8_t TargetID; 344 uint8_t LUN; 345 uint8_t Function; 346 uint8_t CdbLength; 347 uint8_t sgcount; 348 uint8_t Flags; 349#define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 350#define ARCMSR_CDB_FLAG_BIOS 0x02 351#define ARCMSR_CDB_FLAG_WRITE 0x04 352#define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 353#define ARCMSR_CDB_FLAG_HEADQ 0x08 354#define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 355 356 uint8_t msgPages; 357 uint32_t Context; 358 uint32_t DataLength; 359 uint8_t Cdb[16]; 360 uint8_t DeviceStatus; 361#define ARCMSR_DEV_CHECK_CONDITION 0x02 362#define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 363#define ARCMSR_DEV_ABORTED 0xF1 364#define ARCMSR_DEV_INIT_FAIL 0xF2 365 366 uint8_t SenseData[15]; 367 union 368 { 369 struct SG32ENTRY sg32entry[1]; 370 struct SG64ENTRY sg64entry[1]; 371 } u; 372}; 373/* 374******************************************************************************* 375** Messaging Unit (MU) of the Intel R 80331 I/O processor(Type A) and Type B processor 376******************************************************************************* 377*/ 378struct MessageUnit_A 379{ 380 uint32_t resrved0[4]; /*0000 000F*/ 381 uint32_t inbound_msgaddr0; /*0010 0013*/ 382 uint32_t inbound_msgaddr1; /*0014 0017*/ 383 uint32_t outbound_msgaddr0; /*0018 001B*/ 384 uint32_t outbound_msgaddr1; /*001C 001F*/ 385 uint32_t inbound_doorbell; /*0020 0023*/ 386 uint32_t inbound_intstatus; /*0024 0027*/ 387 uint32_t inbound_intmask; /*0028 002B*/ 388 uint32_t outbound_doorbell; /*002C 002F*/ 389 uint32_t outbound_intstatus; /*0030 0033*/ 390 uint32_t outbound_intmask; /*0034 0037*/ 391 uint32_t reserved1[2]; /*0038 003F*/ 392 uint32_t inbound_queueport; /*0040 0043*/ 393 uint32_t outbound_queueport; /*0044 0047*/ 394 uint32_t reserved2[2]; /*0048 004F*/ 395 uint32_t reserved3[492]; /*0050 07FF 492*/ 396 uint32_t reserved4[128]; /*0800 09FF 128*/ 397 uint32_t message_rwbuffer[256]; /*0a00 0DFF 256*/ 398 uint32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 399 uint32_t reserved5[32]; /*0E80 0EFF 32*/ 400 uint32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 401 uint32_t reserved6[32]; /*0F80 0FFF 32*/ 402}; 403 404struct MessageUnit_B 405{ 406 uint32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 407 uint32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; 408 uint32_t postq_index; 409 uint32_t doneq_index; 410 uint32_t __iomem *drv2iop_doorbell; 411 uint32_t __iomem *drv2iop_doorbell_mask; 412 uint32_t __iomem *iop2drv_doorbell; 413 uint32_t __iomem *iop2drv_doorbell_mask; 414 uint32_t __iomem *message_rwbuffer; 415 uint32_t __iomem *message_wbuffer; 416 uint32_t __iomem *message_rbuffer; 417}; 418/* 419********************************************************************* 420** LSI 421********************************************************************* 422*/ 423struct MessageUnit_C{ 424 uint32_t message_unit_status; /*0000 0003*/ 425 uint32_t slave_error_attribute; /*0004 0007*/ 426 uint32_t slave_error_address; /*0008 000B*/ 427 uint32_t posted_outbound_doorbell; /*000C 000F*/ 428 uint32_t master_error_attribute; /*0010 0013*/ 429 uint32_t master_error_address_low; /*0014 0017*/ 430 uint32_t master_error_address_high; /*0018 001B*/ 431 uint32_t hcb_size; /*001C 001F*/ 432 uint32_t inbound_doorbell; /*0020 0023*/ 433 uint32_t diagnostic_rw_data; /*0024 0027*/ 434 uint32_t diagnostic_rw_address_low; /*0028 002B*/ 435 uint32_t diagnostic_rw_address_high; /*002C 002F*/ 436 uint32_t host_int_status; /*0030 0033*/ 437 uint32_t host_int_mask; /*0034 0037*/ 438 uint32_t dcr_data; /*0038 003B*/ 439 uint32_t dcr_address; /*003C 003F*/ 440 uint32_t inbound_queueport; /*0040 0043*/ 441 uint32_t outbound_queueport; /*0044 0047*/ 442 uint32_t hcb_pci_address_low; /*0048 004B*/ 443 uint32_t hcb_pci_address_high; /*004C 004F*/ 444 uint32_t iop_int_status; /*0050 0053*/ 445 uint32_t iop_int_mask; /*0054 0057*/ 446 uint32_t iop_inbound_queue_port; /*0058 005B*/ 447 uint32_t iop_outbound_queue_port; /*005C 005F*/ 448 uint32_t inbound_free_list_index; /*0060 0063*/ 449 uint32_t inbound_post_list_index; /*0064 0067*/ 450 uint32_t outbound_free_list_index; /*0068 006B*/ 451 uint32_t outbound_post_list_index; /*006C 006F*/ 452 uint32_t inbound_doorbell_clear; /*0070 0073*/ 453 uint32_t i2o_message_unit_control; /*0074 0077*/ 454 uint32_t last_used_message_source_address_low; /*0078 007B*/ 455 uint32_t last_used_message_source_address_high; /*007C 007F*/ 456 uint32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 457 uint32_t message_dest_address_index; /*0090 0093*/ 458 uint32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 459 uint32_t utility_A_int_counter_timer; /*0098 009B*/ 460 uint32_t outbound_doorbell; /*009C 009F*/ 461 uint32_t outbound_doorbell_clear; /*00A0 00A3*/ 462 uint32_t message_source_address_index; /*00A4 00A7*/ 463 uint32_t message_done_queue_index; /*00A8 00AB*/ 464 uint32_t reserved0; /*00AC 00AF*/ 465 uint32_t inbound_msgaddr0; /*00B0 00B3*/ 466 uint32_t inbound_msgaddr1; /*00B4 00B7*/ 467 uint32_t outbound_msgaddr0; /*00B8 00BB*/ 468 uint32_t outbound_msgaddr1; /*00BC 00BF*/ 469 uint32_t inbound_queueport_low; /*00C0 00C3*/ 470 uint32_t inbound_queueport_high; /*00C4 00C7*/ 471 uint32_t outbound_queueport_low; /*00C8 00CB*/ 472 uint32_t outbound_queueport_high; /*00CC 00CF*/ 473 uint32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 474 uint32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 475 uint32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 476 uint32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 477 uint32_t message_dest_queue_port_low; /*00E0 00E3*/ 478 uint32_t message_dest_queue_port_high; /*00E4 00E7*/ 479 uint32_t last_used_message_dest_address_low; /*00E8 00EB*/ 480 uint32_t last_used_message_dest_address_high; /*00EC 00EF*/ 481 uint32_t message_done_queue_base_address_low; /*00F0 00F3*/ 482 uint32_t message_done_queue_base_address_high; /*00F4 00F7*/ 483 uint32_t host_diagnostic; /*00F8 00FB*/ 484 uint32_t write_sequence; /*00FC 00FF*/ 485 uint32_t reserved1[34]; /*0100 0187*/ 486 uint32_t reserved2[1950]; /*0188 1FFF*/ 487 uint32_t message_wbuffer[32]; /*2000 207F*/ 488 uint32_t reserved3[32]; /*2080 20FF*/ 489 uint32_t message_rbuffer[32]; /*2100 217F*/ 490 uint32_t reserved4[32]; /*2180 21FF*/ 491 uint32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 492}; 493/* 494******************************************************************************* 495** Adapter Control Block 496******************************************************************************* 497*/ 498struct AdapterControlBlock 499{ 500 uint32_t adapter_type; /* adapter A,B..... */ 501 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ 502 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ 503 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc P IOP */ 504 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */ 505 struct pci_dev * pdev; 506 struct Scsi_Host * host; 507 unsigned long vir2phy_offset; 508 /* Offset is used in making arc cdb physical to virtual calculations */ 509 uint32_t outbound_int_enable; 510 uint32_t cdb_phyaddr_hi32; 511 uint32_t reg_mu_acc_handle0; 512 spinlock_t eh_lock; 513 spinlock_t ccblist_lock; 514 union { 515 struct MessageUnit_A __iomem *pmuA; 516 struct MessageUnit_B *pmuB; 517 struct MessageUnit_C __iomem *pmuC; 518 }; 519 /* message unit ATU inbound base address0 */ 520 void __iomem *mem_base0; 521 void __iomem *mem_base1; 522 uint32_t acb_flags; 523 u16 dev_id; 524 uint8_t adapter_index; 525 #define ACB_F_SCSISTOPADAPTER 0x0001 526 #define ACB_F_MSG_STOP_BGRB 0x0002 527 /* stop RAID background rebuild */ 528 #define ACB_F_MSG_START_BGRB 0x0004 529 /* stop RAID background rebuild */ 530 #define ACB_F_IOPDATA_OVERFLOW 0x0008 531 /* iop message data rqbuffer overflow */ 532 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 533 /* message clear wqbuffer */ 534 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 535 /* message clear rqbuffer */ 536 #define ACB_F_MESSAGE_WQBUFFER_READED 0x0040 537 #define ACB_F_BUS_RESET 0x0080 538 #define ACB_F_BUS_HANG_ON 0x0800/* need hardware reset bus */ 539 540 #define ACB_F_IOP_INITED 0x0100 541 /* iop init */ 542 #define ACB_F_ABORT 0x0200 543 #define ACB_F_FIRMWARE_TRAP 0x0400 544 struct CommandControlBlock * pccb_pool[ARCMSR_MAX_FREECCB_NUM]; 545 /* used for memory free */ 546 struct list_head ccb_free_list; 547 /* head of free ccb list */ 548 549 atomic_t ccboutstandingcount; 550 /*The present outstanding command number that in the IOP that 551 waiting for being handled by FW*/ 552 553 void * dma_coherent; 554 /* dma_coherent used for memory free */ 555 dma_addr_t dma_coherent_handle; 556 /* dma_coherent_handle used for memory free */ 557 dma_addr_t dma_coherent_handle_hbb_mu; 558 unsigned int uncache_size; 559 uint8_t rqbuffer[ARCMSR_MAX_QBUFFER]; 560 /* data collection buffer for read from 80331 */ 561 int32_t rqbuf_firstindex; 562 /* first of read buffer */ 563 int32_t rqbuf_lastindex; 564 /* last of read buffer */ 565 uint8_t wqbuffer[ARCMSR_MAX_QBUFFER]; 566 /* data collection buffer for write to 80331 */ 567 int32_t wqbuf_firstindex; 568 /* first of write buffer */ 569 int32_t wqbuf_lastindex; 570 /* last of write buffer */ 571 uint8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; 572 /* id0 ..... id15, lun0...lun7 */ 573#define ARECA_RAID_GONE 0x55 574#define ARECA_RAID_GOOD 0xaa 575 uint32_t num_resets; 576 uint32_t num_aborts; 577 uint32_t signature; 578 uint32_t firm_request_len; 579 uint32_t firm_numbers_queue; 580 uint32_t firm_sdram_size; 581 uint32_t firm_hd_channels; 582 uint32_t firm_cfg_version; 583 char firm_model[12]; 584 char firm_version[20]; 585 char device_map[20]; /*21,84-99*/ 586 struct work_struct arcmsr_do_message_isr_bh; 587 struct timer_list eternal_timer; 588 unsigned short fw_flag; 589 #define FW_NORMAL 0x0000 590 #define FW_BOG 0x0001 591 #define FW_DEADLOCK 0x0010 592 atomic_t rq_map_token; 593 atomic_t ante_token_value; 594};/* HW_DEVICE_EXTENSION */ 595/* 596******************************************************************************* 597** Command Control Block 598** this CCB length must be 32 bytes boundary 599******************************************************************************* 600*/ 601struct CommandControlBlock{ 602 /*x32:sizeof struct_CCB=(32+60)byte, x64:sizeof struct_CCB=(64+60)byte*/ 603 struct list_head list; /*x32: 8byte, x64: 16byte*/ 604 struct scsi_cmnd *pcmd; /*8 bytes pointer of linux scsi command */ 605 struct AdapterControlBlock *acb; /*x32: 4byte, x64: 8byte*/ 606 uint32_t cdb_phyaddr_pattern; /*x32: 4byte, x64: 4byte*/ 607 uint32_t arc_cdb_size; /*x32:4byte,x64:4byte*/ 608 uint16_t ccb_flags; /*x32: 2byte, x64: 2byte*/ 609 #define CCB_FLAG_READ 0x0000 610 #define CCB_FLAG_WRITE 0x0001 611 #define CCB_FLAG_ERROR 0x0002 612 #define CCB_FLAG_FLUSHCACHE 0x0004 613 #define CCB_FLAG_MASTER_ABORTED 0x0008 614 uint16_t startdone; /*x32:2byte,x32:2byte*/ 615 #define ARCMSR_CCB_DONE 0x0000 616 #define ARCMSR_CCB_START 0x55AA 617 #define ARCMSR_CCB_ABORTED 0xAA55 618 #define ARCMSR_CCB_ILLEGAL 0xFFFF 619 #if BITS_PER_LONG == 64 620 /* ======================512+64 bytes======================== */ 621 uint32_t reserved[5]; /*24 byte*/ 622 #else 623 /* ======================512+32 bytes======================== */ 624 uint32_t reserved; /*8 byte*/ 625 #endif 626 /* ======================================================= */ 627 struct ARCMSR_CDB arcmsr_cdb; 628}; 629/* 630******************************************************************************* 631** ARECA SCSI sense data 632******************************************************************************* 633*/ 634struct SENSE_DATA 635{ 636 uint8_t ErrorCode:7; 637#define SCSI_SENSE_CURRENT_ERRORS 0x70 638#define SCSI_SENSE_DEFERRED_ERRORS 0x71 639 uint8_t Valid:1; 640 uint8_t SegmentNumber; 641 uint8_t SenseKey:4; 642 uint8_t Reserved:1; 643 uint8_t IncorrectLength:1; 644 uint8_t EndOfMedia:1; 645 uint8_t FileMark:1; 646 uint8_t Information[4]; 647 uint8_t AdditionalSenseLength; 648 uint8_t CommandSpecificInformation[4]; 649 uint8_t AdditionalSenseCode; 650 uint8_t AdditionalSenseCodeQualifier; 651 uint8_t FieldReplaceableUnitCode; 652 uint8_t SenseKeySpecific[3]; 653}; 654/* 655******************************************************************************* 656** Outbound Interrupt Status Register - OISR 657******************************************************************************* 658*/ 659#define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 660#define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 661#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 662#define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 663#define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 664#define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 665#define ARCMSR_MU_OUTBOUND_HANDLE_INT \ 666 (ARCMSR_MU_OUTBOUND_MESSAGE0_INT \ 667 |ARCMSR_MU_OUTBOUND_MESSAGE1_INT \ 668 |ARCMSR_MU_OUTBOUND_DOORBELL_INT \ 669 |ARCMSR_MU_OUTBOUND_POSTQUEUE_INT \ 670 |ARCMSR_MU_OUTBOUND_PCI_INT) 671/* 672******************************************************************************* 673** Outbound Interrupt Mask Register - OIMR 674******************************************************************************* 675*/ 676#define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 677#define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 678#define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 679#define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 680#define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 681#define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 682#define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 683 684extern void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *); 685extern void arcmsr_iop_message_read(struct AdapterControlBlock *); 686extern struct QBUFFER __iomem *arcmsr_get_iop_rqbuffer(struct AdapterControlBlock *); 687extern struct device_attribute *arcmsr_host_attrs[]; 688extern int arcmsr_alloc_sysfs_attr(struct AdapterControlBlock *); 689void arcmsr_free_sysfs_attr(struct AdapterControlBlock *acb); 690