1#define DRV_NAME "advansys" 2#define ASC_VERSION "3.4" /* AdvanSys Driver Version */ 3 4/* 5 * advansys.c - Linux Host Driver for AdvanSys SCSI Adapters 6 * 7 * Copyright (c) 1995-2000 Advanced System Products, Inc. 8 * Copyright (c) 2000-2001 ConnectCom Solutions, Inc. 9 * Copyright (c) 2007 Matthew Wilcox <matthew@wil.cx> 10 * All Rights Reserved. 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 */ 17 18/* 19 * As of March 8, 2000 Advanced System Products, Inc. (AdvanSys) 20 * changed its name to ConnectCom Solutions, Inc. 21 * On June 18, 2001 Initio Corp. acquired ConnectCom's SCSI assets 22 */ 23 24#include <linux/module.h> 25#include <linux/string.h> 26#include <linux/kernel.h> 27#include <linux/types.h> 28#include <linux/ioport.h> 29#include <linux/interrupt.h> 30#include <linux/delay.h> 31#include <linux/slab.h> 32#include <linux/mm.h> 33#include <linux/proc_fs.h> 34#include <linux/init.h> 35#include <linux/blkdev.h> 36#include <linux/isa.h> 37#include <linux/eisa.h> 38#include <linux/pci.h> 39#include <linux/spinlock.h> 40#include <linux/dma-mapping.h> 41#include <linux/firmware.h> 42 43#include <asm/io.h> 44#include <asm/system.h> 45#include <asm/dma.h> 46 47#include <scsi/scsi_cmnd.h> 48#include <scsi/scsi_device.h> 49#include <scsi/scsi_tcq.h> 50#include <scsi/scsi.h> 51#include <scsi/scsi_host.h> 52 53#warning this driver is still not properly converted to the DMA API 54 55/* Enable driver /proc statistics. */ 56#define ADVANSYS_STATS 57 58/* Enable driver tracing. */ 59#undef ADVANSYS_DEBUG 60 61/* 62 * Portable Data Types 63 * 64 * Any instance where a 32-bit long or pointer type is assumed 65 * for precision or HW defined structures, the following define 66 * types must be used. In Linux the char, short, and int types 67 * are all consistent at 8, 16, and 32 bits respectively. Pointers 68 * and long types are 64 bits on Alpha and UltraSPARC. 69 */ 70#define ASC_PADDR __u32 /* Physical/Bus address data type. */ 71#define ASC_VADDR __u32 /* Virtual address data type. */ 72#define ASC_DCNT __u32 /* Unsigned Data count type. */ 73#define ASC_SDCNT __s32 /* Signed Data count type. */ 74 75typedef unsigned char uchar; 76 77#ifndef TRUE 78#define TRUE (1) 79#endif 80#ifndef FALSE 81#define FALSE (0) 82#endif 83 84#define ERR (-1) 85#define UW_ERR (uint)(0xFFFF) 86#define isodd_word(val) ((((uint)val) & (uint)0x0001) != 0) 87 88#define PCI_VENDOR_ID_ASP 0x10cd 89#define PCI_DEVICE_ID_ASP_1200A 0x1100 90#define PCI_DEVICE_ID_ASP_ABP940 0x1200 91#define PCI_DEVICE_ID_ASP_ABP940U 0x1300 92#define PCI_DEVICE_ID_ASP_ABP940UW 0x2300 93#define PCI_DEVICE_ID_38C0800_REV1 0x2500 94#define PCI_DEVICE_ID_38C1600_REV1 0x2700 95 96/* 97 * Enable CC_VERY_LONG_SG_LIST to support up to 64K element SG lists. 98 * The SRB structure will have to be changed and the ASC_SRB2SCSIQ() 99 * macro re-defined to be able to obtain a ASC_SCSI_Q pointer from the 100 * SRB structure. 101 */ 102#define CC_VERY_LONG_SG_LIST 0 103#define ASC_SRB2SCSIQ(srb_ptr) (srb_ptr) 104 105#define PortAddr unsigned int /* port address size */ 106#define inp(port) inb(port) 107#define outp(port, byte) outb((byte), (port)) 108 109#define inpw(port) inw(port) 110#define outpw(port, word) outw((word), (port)) 111 112#define ASC_MAX_SG_QUEUE 7 113#define ASC_MAX_SG_LIST 255 114 115#define ASC_CS_TYPE unsigned short 116 117#define ASC_IS_ISA (0x0001) 118#define ASC_IS_ISAPNP (0x0081) 119#define ASC_IS_EISA (0x0002) 120#define ASC_IS_PCI (0x0004) 121#define ASC_IS_PCI_ULTRA (0x0104) 122#define ASC_IS_PCMCIA (0x0008) 123#define ASC_IS_MCA (0x0020) 124#define ASC_IS_VL (0x0040) 125#define ASC_IS_WIDESCSI_16 (0x0100) 126#define ASC_IS_WIDESCSI_32 (0x0200) 127#define ASC_IS_BIG_ENDIAN (0x8000) 128 129#define ASC_CHIP_MIN_VER_VL (0x01) 130#define ASC_CHIP_MAX_VER_VL (0x07) 131#define ASC_CHIP_MIN_VER_PCI (0x09) 132#define ASC_CHIP_MAX_VER_PCI (0x0F) 133#define ASC_CHIP_VER_PCI_BIT (0x08) 134#define ASC_CHIP_MIN_VER_ISA (0x11) 135#define ASC_CHIP_MIN_VER_ISA_PNP (0x21) 136#define ASC_CHIP_MAX_VER_ISA (0x27) 137#define ASC_CHIP_VER_ISA_BIT (0x30) 138#define ASC_CHIP_VER_ISAPNP_BIT (0x20) 139#define ASC_CHIP_VER_ASYN_BUG (0x21) 140#define ASC_CHIP_VER_PCI 0x08 141#define ASC_CHIP_VER_PCI_ULTRA_3150 (ASC_CHIP_VER_PCI | 0x02) 142#define ASC_CHIP_VER_PCI_ULTRA_3050 (ASC_CHIP_VER_PCI | 0x03) 143#define ASC_CHIP_MIN_VER_EISA (0x41) 144#define ASC_CHIP_MAX_VER_EISA (0x47) 145#define ASC_CHIP_VER_EISA_BIT (0x40) 146#define ASC_CHIP_LATEST_VER_EISA ((ASC_CHIP_MIN_VER_EISA - 1) + 3) 147#define ASC_MAX_VL_DMA_COUNT (0x07FFFFFFL) 148#define ASC_MAX_PCI_DMA_COUNT (0xFFFFFFFFL) 149#define ASC_MAX_ISA_DMA_COUNT (0x00FFFFFFL) 150 151#define ASC_SCSI_ID_BITS 3 152#define ASC_SCSI_TIX_TYPE uchar 153#define ASC_ALL_DEVICE_BIT_SET 0xFF 154#define ASC_SCSI_BIT_ID_TYPE uchar 155#define ASC_MAX_TID 7 156#define ASC_MAX_LUN 7 157#define ASC_SCSI_WIDTH_BIT_SET 0xFF 158#define ASC_MAX_SENSE_LEN 32 159#define ASC_MIN_SENSE_LEN 14 160#define ASC_SCSI_RESET_HOLD_TIME_US 60 161 162/* 163 * Narrow boards only support 12-byte commands, while wide boards 164 * extend to 16-byte commands. 165 */ 166#define ASC_MAX_CDB_LEN 12 167#define ADV_MAX_CDB_LEN 16 168 169#define MS_SDTR_LEN 0x03 170#define MS_WDTR_LEN 0x02 171 172#define ASC_SG_LIST_PER_Q 7 173#define QS_FREE 0x00 174#define QS_READY 0x01 175#define QS_DISC1 0x02 176#define QS_DISC2 0x04 177#define QS_BUSY 0x08 178#define QS_ABORTED 0x40 179#define QS_DONE 0x80 180#define QC_NO_CALLBACK 0x01 181#define QC_SG_SWAP_QUEUE 0x02 182#define QC_SG_HEAD 0x04 183#define QC_DATA_IN 0x08 184#define QC_DATA_OUT 0x10 185#define QC_URGENT 0x20 186#define QC_MSG_OUT 0x40 187#define QC_REQ_SENSE 0x80 188#define QCSG_SG_XFER_LIST 0x02 189#define QCSG_SG_XFER_MORE 0x04 190#define QCSG_SG_XFER_END 0x08 191#define QD_IN_PROGRESS 0x00 192#define QD_NO_ERROR 0x01 193#define QD_ABORTED_BY_HOST 0x02 194#define QD_WITH_ERROR 0x04 195#define QD_INVALID_REQUEST 0x80 196#define QD_INVALID_HOST_NUM 0x81 197#define QD_INVALID_DEVICE 0x82 198#define QD_ERR_INTERNAL 0xFF 199#define QHSTA_NO_ERROR 0x00 200#define QHSTA_M_SEL_TIMEOUT 0x11 201#define QHSTA_M_DATA_OVER_RUN 0x12 202#define QHSTA_M_DATA_UNDER_RUN 0x12 203#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 204#define QHSTA_M_BAD_BUS_PHASE_SEQ 0x14 205#define QHSTA_D_QDONE_SG_LIST_CORRUPTED 0x21 206#define QHSTA_D_ASC_DVC_ERROR_CODE_SET 0x22 207#define QHSTA_D_HOST_ABORT_FAILED 0x23 208#define QHSTA_D_EXE_SCSI_Q_FAILED 0x24 209#define QHSTA_D_EXE_SCSI_Q_BUSY_TIMEOUT 0x25 210#define QHSTA_D_ASPI_NO_BUF_POOL 0x26 211#define QHSTA_M_WTM_TIMEOUT 0x41 212#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 213#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 214#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 215#define QHSTA_M_TARGET_STATUS_BUSY 0x45 216#define QHSTA_M_BAD_TAG_CODE 0x46 217#define QHSTA_M_BAD_QUEUE_FULL_OR_BUSY 0x47 218#define QHSTA_M_HUNG_REQ_SCSI_BUS_RESET 0x48 219#define QHSTA_D_LRAM_CMP_ERROR 0x81 220#define QHSTA_M_MICRO_CODE_ERROR_HALT 0xA1 221#define ASC_FLAG_SCSIQ_REQ 0x01 222#define ASC_FLAG_BIOS_SCSIQ_REQ 0x02 223#define ASC_FLAG_BIOS_ASYNC_IO 0x04 224#define ASC_FLAG_SRB_LINEAR_ADDR 0x08 225#define ASC_FLAG_WIN16 0x10 226#define ASC_FLAG_WIN32 0x20 227#define ASC_FLAG_ISA_OVER_16MB 0x40 228#define ASC_FLAG_DOS_VM_CALLBACK 0x80 229#define ASC_TAG_FLAG_EXTRA_BYTES 0x10 230#define ASC_TAG_FLAG_DISABLE_DISCONNECT 0x04 231#define ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX 0x08 232#define ASC_TAG_FLAG_DISABLE_CHK_COND_INT_HOST 0x40 233#define ASC_SCSIQ_CPY_BEG 4 234#define ASC_SCSIQ_SGHD_CPY_BEG 2 235#define ASC_SCSIQ_B_FWD 0 236#define ASC_SCSIQ_B_BWD 1 237#define ASC_SCSIQ_B_STATUS 2 238#define ASC_SCSIQ_B_QNO 3 239#define ASC_SCSIQ_B_CNTL 4 240#define ASC_SCSIQ_B_SG_QUEUE_CNT 5 241#define ASC_SCSIQ_D_DATA_ADDR 8 242#define ASC_SCSIQ_D_DATA_CNT 12 243#define ASC_SCSIQ_B_SENSE_LEN 20 244#define ASC_SCSIQ_DONE_INFO_BEG 22 245#define ASC_SCSIQ_D_SRBPTR 22 246#define ASC_SCSIQ_B_TARGET_IX 26 247#define ASC_SCSIQ_B_CDB_LEN 28 248#define ASC_SCSIQ_B_TAG_CODE 29 249#define ASC_SCSIQ_W_VM_ID 30 250#define ASC_SCSIQ_DONE_STATUS 32 251#define ASC_SCSIQ_HOST_STATUS 33 252#define ASC_SCSIQ_SCSI_STATUS 34 253#define ASC_SCSIQ_CDB_BEG 36 254#define ASC_SCSIQ_DW_REMAIN_XFER_ADDR 56 255#define ASC_SCSIQ_DW_REMAIN_XFER_CNT 60 256#define ASC_SCSIQ_B_FIRST_SG_WK_QP 48 257#define ASC_SCSIQ_B_SG_WK_QP 49 258#define ASC_SCSIQ_B_SG_WK_IX 50 259#define ASC_SCSIQ_W_ALT_DC1 52 260#define ASC_SCSIQ_B_LIST_CNT 6 261#define ASC_SCSIQ_B_CUR_LIST_CNT 7 262#define ASC_SGQ_B_SG_CNTL 4 263#define ASC_SGQ_B_SG_HEAD_QP 5 264#define ASC_SGQ_B_SG_LIST_CNT 6 265#define ASC_SGQ_B_SG_CUR_LIST_CNT 7 266#define ASC_SGQ_LIST_BEG 8 267#define ASC_DEF_SCSI1_QNG 4 268#define ASC_MAX_SCSI1_QNG 4 269#define ASC_DEF_SCSI2_QNG 16 270#define ASC_MAX_SCSI2_QNG 32 271#define ASC_TAG_CODE_MASK 0x23 272#define ASC_STOP_REQ_RISC_STOP 0x01 273#define ASC_STOP_ACK_RISC_STOP 0x03 274#define ASC_STOP_CLEAN_UP_BUSY_Q 0x10 275#define ASC_STOP_CLEAN_UP_DISC_Q 0x20 276#define ASC_STOP_HOST_REQ_RISC_HALT 0x40 277#define ASC_TIDLUN_TO_IX(tid, lun) (ASC_SCSI_TIX_TYPE)((tid) + ((lun)<<ASC_SCSI_ID_BITS)) 278#define ASC_TID_TO_TARGET_ID(tid) (ASC_SCSI_BIT_ID_TYPE)(0x01 << (tid)) 279#define ASC_TIX_TO_TARGET_ID(tix) (0x01 << ((tix) & ASC_MAX_TID)) 280#define ASC_TIX_TO_TID(tix) ((tix) & ASC_MAX_TID) 281#define ASC_TID_TO_TIX(tid) ((tid) & ASC_MAX_TID) 282#define ASC_TIX_TO_LUN(tix) (((tix) >> ASC_SCSI_ID_BITS) & ASC_MAX_LUN) 283#define ASC_QNO_TO_QADDR(q_no) ((ASC_QADR_BEG)+((int)(q_no) << 6)) 284 285typedef struct asc_scsiq_1 { 286 uchar status; 287 uchar q_no; 288 uchar cntl; 289 uchar sg_queue_cnt; 290 uchar target_id; 291 uchar target_lun; 292 ASC_PADDR data_addr; 293 ASC_DCNT data_cnt; 294 ASC_PADDR sense_addr; 295 uchar sense_len; 296 uchar extra_bytes; 297} ASC_SCSIQ_1; 298 299typedef struct asc_scsiq_2 { 300 ASC_VADDR srb_ptr; 301 uchar target_ix; 302 uchar flag; 303 uchar cdb_len; 304 uchar tag_code; 305 ushort vm_id; 306} ASC_SCSIQ_2; 307 308typedef struct asc_scsiq_3 { 309 uchar done_stat; 310 uchar host_stat; 311 uchar scsi_stat; 312 uchar scsi_msg; 313} ASC_SCSIQ_3; 314 315typedef struct asc_scsiq_4 { 316 uchar cdb[ASC_MAX_CDB_LEN]; 317 uchar y_first_sg_list_qp; 318 uchar y_working_sg_qp; 319 uchar y_working_sg_ix; 320 uchar y_res; 321 ushort x_req_count; 322 ushort x_reconnect_rtn; 323 ASC_PADDR x_saved_data_addr; 324 ASC_DCNT x_saved_data_cnt; 325} ASC_SCSIQ_4; 326 327typedef struct asc_q_done_info { 328 ASC_SCSIQ_2 d2; 329 ASC_SCSIQ_3 d3; 330 uchar q_status; 331 uchar q_no; 332 uchar cntl; 333 uchar sense_len; 334 uchar extra_bytes; 335 uchar res; 336 ASC_DCNT remain_bytes; 337} ASC_QDONE_INFO; 338 339typedef struct asc_sg_list { 340 ASC_PADDR addr; 341 ASC_DCNT bytes; 342} ASC_SG_LIST; 343 344typedef struct asc_sg_head { 345 ushort entry_cnt; 346 ushort queue_cnt; 347 ushort entry_to_copy; 348 ushort res; 349 ASC_SG_LIST sg_list[0]; 350} ASC_SG_HEAD; 351 352typedef struct asc_scsi_q { 353 ASC_SCSIQ_1 q1; 354 ASC_SCSIQ_2 q2; 355 uchar *cdbptr; 356 ASC_SG_HEAD *sg_head; 357 ushort remain_sg_entry_cnt; 358 ushort next_sg_index; 359} ASC_SCSI_Q; 360 361typedef struct asc_scsi_req_q { 362 ASC_SCSIQ_1 r1; 363 ASC_SCSIQ_2 r2; 364 uchar *cdbptr; 365 ASC_SG_HEAD *sg_head; 366 uchar *sense_ptr; 367 ASC_SCSIQ_3 r3; 368 uchar cdb[ASC_MAX_CDB_LEN]; 369 uchar sense[ASC_MIN_SENSE_LEN]; 370} ASC_SCSI_REQ_Q; 371 372typedef struct asc_scsi_bios_req_q { 373 ASC_SCSIQ_1 r1; 374 ASC_SCSIQ_2 r2; 375 uchar *cdbptr; 376 ASC_SG_HEAD *sg_head; 377 uchar *sense_ptr; 378 ASC_SCSIQ_3 r3; 379 uchar cdb[ASC_MAX_CDB_LEN]; 380 uchar sense[ASC_MIN_SENSE_LEN]; 381} ASC_SCSI_BIOS_REQ_Q; 382 383typedef struct asc_risc_q { 384 uchar fwd; 385 uchar bwd; 386 ASC_SCSIQ_1 i1; 387 ASC_SCSIQ_2 i2; 388 ASC_SCSIQ_3 i3; 389 ASC_SCSIQ_4 i4; 390} ASC_RISC_Q; 391 392typedef struct asc_sg_list_q { 393 uchar seq_no; 394 uchar q_no; 395 uchar cntl; 396 uchar sg_head_qp; 397 uchar sg_list_cnt; 398 uchar sg_cur_list_cnt; 399} ASC_SG_LIST_Q; 400 401typedef struct asc_risc_sg_list_q { 402 uchar fwd; 403 uchar bwd; 404 ASC_SG_LIST_Q sg; 405 ASC_SG_LIST sg_list[7]; 406} ASC_RISC_SG_LIST_Q; 407 408#define ASCQ_ERR_Q_STATUS 0x0D 409#define ASCQ_ERR_CUR_QNG 0x17 410#define ASCQ_ERR_SG_Q_LINKS 0x18 411#define ASCQ_ERR_ISR_RE_ENTRY 0x1A 412#define ASCQ_ERR_CRITICAL_RE_ENTRY 0x1B 413#define ASCQ_ERR_ISR_ON_CRITICAL 0x1C 414 415/* 416 * Warning code values are set in ASC_DVC_VAR 'warn_code'. 417 */ 418#define ASC_WARN_NO_ERROR 0x0000 419#define ASC_WARN_IO_PORT_ROTATE 0x0001 420#define ASC_WARN_EEPROM_CHKSUM 0x0002 421#define ASC_WARN_IRQ_MODIFIED 0x0004 422#define ASC_WARN_AUTO_CONFIG 0x0008 423#define ASC_WARN_CMD_QNG_CONFLICT 0x0010 424#define ASC_WARN_EEPROM_RECOVER 0x0020 425#define ASC_WARN_CFG_MSW_RECOVER 0x0040 426 427/* 428 * Error code values are set in {ASC/ADV}_DVC_VAR 'err_code'. 429 */ 430#define ASC_IERR_NO_CARRIER 0x0001 /* No more carrier memory */ 431#define ASC_IERR_MCODE_CHKSUM 0x0002 /* micro code check sum error */ 432#define ASC_IERR_SET_PC_ADDR 0x0004 433#define ASC_IERR_START_STOP_CHIP 0x0008 /* start/stop chip failed */ 434#define ASC_IERR_ILLEGAL_CONNECTION 0x0010 /* Illegal cable connection */ 435#define ASC_IERR_SINGLE_END_DEVICE 0x0020 /* SE device on DIFF bus */ 436#define ASC_IERR_REVERSED_CABLE 0x0040 /* Narrow flat cable reversed */ 437#define ASC_IERR_SET_SCSI_ID 0x0080 /* set SCSI ID failed */ 438#define ASC_IERR_HVD_DEVICE 0x0100 /* HVD device on LVD port */ 439#define ASC_IERR_BAD_SIGNATURE 0x0200 /* signature not found */ 440#define ASC_IERR_NO_BUS_TYPE 0x0400 441#define ASC_IERR_BIST_PRE_TEST 0x0800 /* BIST pre-test error */ 442#define ASC_IERR_BIST_RAM_TEST 0x1000 /* BIST RAM test error */ 443#define ASC_IERR_BAD_CHIPTYPE 0x2000 /* Invalid chip_type setting */ 444 445#define ASC_DEF_MAX_TOTAL_QNG (0xF0) 446#define ASC_MIN_TAG_Q_PER_DVC (0x04) 447#define ASC_MIN_FREE_Q (0x02) 448#define ASC_MIN_TOTAL_QNG ((ASC_MAX_SG_QUEUE)+(ASC_MIN_FREE_Q)) 449#define ASC_MAX_TOTAL_QNG 240 450#define ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG 16 451#define ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG 8 452#define ASC_MAX_PCI_INRAM_TOTAL_QNG 20 453#define ASC_MAX_INRAM_TAG_QNG 16 454#define ASC_IOADR_GAP 0x10 455#define ASC_SYN_MAX_OFFSET 0x0F 456#define ASC_DEF_SDTR_OFFSET 0x0F 457#define ASC_SDTR_ULTRA_PCI_10MB_INDEX 0x02 458#define ASYN_SDTR_DATA_FIX_PCI_REV_AB 0x41 459 460/* The narrow chip only supports a limited selection of transfer rates. 461 * These are encoded in the range 0..7 or 0..15 depending whether the chip 462 * is Ultra-capable or not. These tables let us convert from one to the other. 463 */ 464static const unsigned char asc_syn_xfer_period[8] = { 465 25, 30, 35, 40, 50, 60, 70, 85 466}; 467 468static const unsigned char asc_syn_ultra_xfer_period[16] = { 469 12, 19, 25, 32, 38, 44, 50, 57, 63, 69, 75, 82, 88, 94, 100, 107 470}; 471 472typedef struct ext_msg { 473 uchar msg_type; 474 uchar msg_len; 475 uchar msg_req; 476 union { 477 struct { 478 uchar sdtr_xfer_period; 479 uchar sdtr_req_ack_offset; 480 } sdtr; 481 struct { 482 uchar wdtr_width; 483 } wdtr; 484 struct { 485 uchar mdp_b3; 486 uchar mdp_b2; 487 uchar mdp_b1; 488 uchar mdp_b0; 489 } mdp; 490 } u_ext_msg; 491 uchar res; 492} EXT_MSG; 493 494#define xfer_period u_ext_msg.sdtr.sdtr_xfer_period 495#define req_ack_offset u_ext_msg.sdtr.sdtr_req_ack_offset 496#define wdtr_width u_ext_msg.wdtr.wdtr_width 497#define mdp_b3 u_ext_msg.mdp_b3 498#define mdp_b2 u_ext_msg.mdp_b2 499#define mdp_b1 u_ext_msg.mdp_b1 500#define mdp_b0 u_ext_msg.mdp_b0 501 502typedef struct asc_dvc_cfg { 503 ASC_SCSI_BIT_ID_TYPE can_tagged_qng; 504 ASC_SCSI_BIT_ID_TYPE cmd_qng_enabled; 505 ASC_SCSI_BIT_ID_TYPE disc_enable; 506 ASC_SCSI_BIT_ID_TYPE sdtr_enable; 507 uchar chip_scsi_id; 508 uchar isa_dma_speed; 509 uchar isa_dma_channel; 510 uchar chip_version; 511 ushort mcode_date; 512 ushort mcode_version; 513 uchar max_tag_qng[ASC_MAX_TID + 1]; 514 uchar sdtr_period_offset[ASC_MAX_TID + 1]; 515 uchar adapter_info[6]; 516} ASC_DVC_CFG; 517 518#define ASC_DEF_DVC_CNTL 0xFFFF 519#define ASC_DEF_CHIP_SCSI_ID 7 520#define ASC_DEF_ISA_DMA_SPEED 4 521#define ASC_INIT_STATE_BEG_GET_CFG 0x0001 522#define ASC_INIT_STATE_END_GET_CFG 0x0002 523#define ASC_INIT_STATE_BEG_SET_CFG 0x0004 524#define ASC_INIT_STATE_END_SET_CFG 0x0008 525#define ASC_INIT_STATE_BEG_LOAD_MC 0x0010 526#define ASC_INIT_STATE_END_LOAD_MC 0x0020 527#define ASC_INIT_STATE_BEG_INQUIRY 0x0040 528#define ASC_INIT_STATE_END_INQUIRY 0x0080 529#define ASC_INIT_RESET_SCSI_DONE 0x0100 530#define ASC_INIT_STATE_WITHOUT_EEP 0x8000 531#define ASC_BUG_FIX_IF_NOT_DWB 0x0001 532#define ASC_BUG_FIX_ASYN_USE_SYN 0x0002 533#define ASC_MIN_TAGGED_CMD 7 534#define ASC_MAX_SCSI_RESET_WAIT 30 535#define ASC_OVERRUN_BSIZE 64 536 537struct asc_dvc_var; /* Forward Declaration. */ 538 539typedef struct asc_dvc_var { 540 PortAddr iop_base; 541 ushort err_code; 542 ushort dvc_cntl; 543 ushort bug_fix_cntl; 544 ushort bus_type; 545 ASC_SCSI_BIT_ID_TYPE init_sdtr; 546 ASC_SCSI_BIT_ID_TYPE sdtr_done; 547 ASC_SCSI_BIT_ID_TYPE use_tagged_qng; 548 ASC_SCSI_BIT_ID_TYPE unit_not_ready; 549 ASC_SCSI_BIT_ID_TYPE queue_full_or_busy; 550 ASC_SCSI_BIT_ID_TYPE start_motor; 551 uchar *overrun_buf; 552 dma_addr_t overrun_dma; 553 uchar scsi_reset_wait; 554 uchar chip_no; 555 char is_in_int; 556 uchar max_total_qng; 557 uchar cur_total_qng; 558 uchar in_critical_cnt; 559 uchar last_q_shortage; 560 ushort init_state; 561 uchar cur_dvc_qng[ASC_MAX_TID + 1]; 562 uchar max_dvc_qng[ASC_MAX_TID + 1]; 563 ASC_SCSI_Q *scsiq_busy_head[ASC_MAX_TID + 1]; 564 ASC_SCSI_Q *scsiq_busy_tail[ASC_MAX_TID + 1]; 565 const uchar *sdtr_period_tbl; 566 ASC_DVC_CFG *cfg; 567 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer_always; 568 char redo_scam; 569 ushort res2; 570 uchar dos_int13_table[ASC_MAX_TID + 1]; 571 ASC_DCNT max_dma_count; 572 ASC_SCSI_BIT_ID_TYPE no_scam; 573 ASC_SCSI_BIT_ID_TYPE pci_fix_asyn_xfer; 574 uchar min_sdtr_index; 575 uchar max_sdtr_index; 576 struct asc_board *drv_ptr; 577 int ptr_map_count; 578 void **ptr_map; 579 ASC_DCNT uc_break; 580} ASC_DVC_VAR; 581 582typedef struct asc_dvc_inq_info { 583 uchar type[ASC_MAX_TID + 1][ASC_MAX_LUN + 1]; 584} ASC_DVC_INQ_INFO; 585 586typedef struct asc_cap_info { 587 ASC_DCNT lba; 588 ASC_DCNT blk_size; 589} ASC_CAP_INFO; 590 591typedef struct asc_cap_info_array { 592 ASC_CAP_INFO cap_info[ASC_MAX_TID + 1][ASC_MAX_LUN + 1]; 593} ASC_CAP_INFO_ARRAY; 594 595#define ASC_MCNTL_NO_SEL_TIMEOUT (ushort)0x0001 596#define ASC_MCNTL_NULL_TARGET (ushort)0x0002 597#define ASC_CNTL_INITIATOR (ushort)0x0001 598#define ASC_CNTL_BIOS_GT_1GB (ushort)0x0002 599#define ASC_CNTL_BIOS_GT_2_DISK (ushort)0x0004 600#define ASC_CNTL_BIOS_REMOVABLE (ushort)0x0008 601#define ASC_CNTL_NO_SCAM (ushort)0x0010 602#define ASC_CNTL_INT_MULTI_Q (ushort)0x0080 603#define ASC_CNTL_NO_LUN_SUPPORT (ushort)0x0040 604#define ASC_CNTL_NO_VERIFY_COPY (ushort)0x0100 605#define ASC_CNTL_RESET_SCSI (ushort)0x0200 606#define ASC_CNTL_INIT_INQUIRY (ushort)0x0400 607#define ASC_CNTL_INIT_VERBOSE (ushort)0x0800 608#define ASC_CNTL_SCSI_PARITY (ushort)0x1000 609#define ASC_CNTL_BURST_MODE (ushort)0x2000 610#define ASC_CNTL_SDTR_ENABLE_ULTRA (ushort)0x4000 611#define ASC_EEP_DVC_CFG_BEG_VL 2 612#define ASC_EEP_MAX_DVC_ADDR_VL 15 613#define ASC_EEP_DVC_CFG_BEG 32 614#define ASC_EEP_MAX_DVC_ADDR 45 615#define ASC_EEP_MAX_RETRY 20 616 617/* 618 * These macros keep the chip SCSI id and ISA DMA speed 619 * bitfields in board order. C bitfields aren't portable 620 * between big and little-endian platforms so they are 621 * not used. 622 */ 623 624#define ASC_EEP_GET_CHIP_ID(cfg) ((cfg)->id_speed & 0x0f) 625#define ASC_EEP_GET_DMA_SPD(cfg) (((cfg)->id_speed & 0xf0) >> 4) 626#define ASC_EEP_SET_CHIP_ID(cfg, sid) \ 627 ((cfg)->id_speed = ((cfg)->id_speed & 0xf0) | ((sid) & ASC_MAX_TID)) 628#define ASC_EEP_SET_DMA_SPD(cfg, spd) \ 629 ((cfg)->id_speed = ((cfg)->id_speed & 0x0f) | ((spd) & 0x0f) << 4) 630 631typedef struct asceep_config { 632 ushort cfg_lsw; 633 ushort cfg_msw; 634 uchar init_sdtr; 635 uchar disc_enable; 636 uchar use_cmd_qng; 637 uchar start_motor; 638 uchar max_total_qng; 639 uchar max_tag_qng; 640 uchar bios_scan; 641 uchar power_up_wait; 642 uchar no_scam; 643 uchar id_speed; /* low order 4 bits is chip scsi id */ 644 /* high order 4 bits is isa dma speed */ 645 uchar dos_int13_table[ASC_MAX_TID + 1]; 646 uchar adapter_info[6]; 647 ushort cntl; 648 ushort chksum; 649} ASCEEP_CONFIG; 650 651#define ASC_EEP_CMD_READ 0x80 652#define ASC_EEP_CMD_WRITE 0x40 653#define ASC_EEP_CMD_WRITE_ABLE 0x30 654#define ASC_EEP_CMD_WRITE_DISABLE 0x00 655#define ASCV_MSGOUT_BEG 0x0000 656#define ASCV_MSGOUT_SDTR_PERIOD (ASCV_MSGOUT_BEG+3) 657#define ASCV_MSGOUT_SDTR_OFFSET (ASCV_MSGOUT_BEG+4) 658#define ASCV_BREAK_SAVED_CODE (ushort)0x0006 659#define ASCV_MSGIN_BEG (ASCV_MSGOUT_BEG+8) 660#define ASCV_MSGIN_SDTR_PERIOD (ASCV_MSGIN_BEG+3) 661#define ASCV_MSGIN_SDTR_OFFSET (ASCV_MSGIN_BEG+4) 662#define ASCV_SDTR_DATA_BEG (ASCV_MSGIN_BEG+8) 663#define ASCV_SDTR_DONE_BEG (ASCV_SDTR_DATA_BEG+8) 664#define ASCV_MAX_DVC_QNG_BEG (ushort)0x0020 665#define ASCV_BREAK_ADDR (ushort)0x0028 666#define ASCV_BREAK_NOTIFY_COUNT (ushort)0x002A 667#define ASCV_BREAK_CONTROL (ushort)0x002C 668#define ASCV_BREAK_HIT_COUNT (ushort)0x002E 669 670#define ASCV_ASCDVC_ERR_CODE_W (ushort)0x0030 671#define ASCV_MCODE_CHKSUM_W (ushort)0x0032 672#define ASCV_MCODE_SIZE_W (ushort)0x0034 673#define ASCV_STOP_CODE_B (ushort)0x0036 674#define ASCV_DVC_ERR_CODE_B (ushort)0x0037 675#define ASCV_OVERRUN_PADDR_D (ushort)0x0038 676#define ASCV_OVERRUN_BSIZE_D (ushort)0x003C 677#define ASCV_HALTCODE_W (ushort)0x0040 678#define ASCV_CHKSUM_W (ushort)0x0042 679#define ASCV_MC_DATE_W (ushort)0x0044 680#define ASCV_MC_VER_W (ushort)0x0046 681#define ASCV_NEXTRDY_B (ushort)0x0048 682#define ASCV_DONENEXT_B (ushort)0x0049 683#define ASCV_USE_TAGGED_QNG_B (ushort)0x004A 684#define ASCV_SCSIBUSY_B (ushort)0x004B 685#define ASCV_Q_DONE_IN_PROGRESS_B (ushort)0x004C 686#define ASCV_CURCDB_B (ushort)0x004D 687#define ASCV_RCLUN_B (ushort)0x004E 688#define ASCV_BUSY_QHEAD_B (ushort)0x004F 689#define ASCV_DISC1_QHEAD_B (ushort)0x0050 690#define ASCV_DISC_ENABLE_B (ushort)0x0052 691#define ASCV_CAN_TAGGED_QNG_B (ushort)0x0053 692#define ASCV_HOSTSCSI_ID_B (ushort)0x0055 693#define ASCV_MCODE_CNTL_B (ushort)0x0056 694#define ASCV_NULL_TARGET_B (ushort)0x0057 695#define ASCV_FREE_Q_HEAD_W (ushort)0x0058 696#define ASCV_DONE_Q_TAIL_W (ushort)0x005A 697#define ASCV_FREE_Q_HEAD_B (ushort)(ASCV_FREE_Q_HEAD_W+1) 698#define ASCV_DONE_Q_TAIL_B (ushort)(ASCV_DONE_Q_TAIL_W+1) 699#define ASCV_HOST_FLAG_B (ushort)0x005D 700#define ASCV_TOTAL_READY_Q_B (ushort)0x0064 701#define ASCV_VER_SERIAL_B (ushort)0x0065 702#define ASCV_HALTCODE_SAVED_W (ushort)0x0066 703#define ASCV_WTM_FLAG_B (ushort)0x0068 704#define ASCV_RISC_FLAG_B (ushort)0x006A 705#define ASCV_REQ_SG_LIST_QP (ushort)0x006B 706#define ASC_HOST_FLAG_IN_ISR 0x01 707#define ASC_HOST_FLAG_ACK_INT 0x02 708#define ASC_RISC_FLAG_GEN_INT 0x01 709#define ASC_RISC_FLAG_REQ_SG_LIST 0x02 710#define IOP_CTRL (0x0F) 711#define IOP_STATUS (0x0E) 712#define IOP_INT_ACK IOP_STATUS 713#define IOP_REG_IFC (0x0D) 714#define IOP_SYN_OFFSET (0x0B) 715#define IOP_EXTRA_CONTROL (0x0D) 716#define IOP_REG_PC (0x0C) 717#define IOP_RAM_ADDR (0x0A) 718#define IOP_RAM_DATA (0x08) 719#define IOP_EEP_DATA (0x06) 720#define IOP_EEP_CMD (0x07) 721#define IOP_VERSION (0x03) 722#define IOP_CONFIG_HIGH (0x04) 723#define IOP_CONFIG_LOW (0x02) 724#define IOP_SIG_BYTE (0x01) 725#define IOP_SIG_WORD (0x00) 726#define IOP_REG_DC1 (0x0E) 727#define IOP_REG_DC0 (0x0C) 728#define IOP_REG_SB (0x0B) 729#define IOP_REG_DA1 (0x0A) 730#define IOP_REG_DA0 (0x08) 731#define IOP_REG_SC (0x09) 732#define IOP_DMA_SPEED (0x07) 733#define IOP_REG_FLAG (0x07) 734#define IOP_FIFO_H (0x06) 735#define IOP_FIFO_L (0x04) 736#define IOP_REG_ID (0x05) 737#define IOP_REG_QP (0x03) 738#define IOP_REG_IH (0x02) 739#define IOP_REG_IX (0x01) 740#define IOP_REG_AX (0x00) 741#define IFC_REG_LOCK (0x00) 742#define IFC_REG_UNLOCK (0x09) 743#define IFC_WR_EN_FILTER (0x10) 744#define IFC_RD_NO_EEPROM (0x10) 745#define IFC_SLEW_RATE (0x20) 746#define IFC_ACT_NEG (0x40) 747#define IFC_INP_FILTER (0x80) 748#define IFC_INIT_DEFAULT (IFC_ACT_NEG | IFC_REG_UNLOCK) 749#define SC_SEL (uchar)(0x80) 750#define SC_BSY (uchar)(0x40) 751#define SC_ACK (uchar)(0x20) 752#define SC_REQ (uchar)(0x10) 753#define SC_ATN (uchar)(0x08) 754#define SC_IO (uchar)(0x04) 755#define SC_CD (uchar)(0x02) 756#define SC_MSG (uchar)(0x01) 757#define SEC_SCSI_CTL (uchar)(0x80) 758#define SEC_ACTIVE_NEGATE (uchar)(0x40) 759#define SEC_SLEW_RATE (uchar)(0x20) 760#define SEC_ENABLE_FILTER (uchar)(0x10) 761#define ASC_HALT_EXTMSG_IN (ushort)0x8000 762#define ASC_HALT_CHK_CONDITION (ushort)0x8100 763#define ASC_HALT_SS_QUEUE_FULL (ushort)0x8200 764#define ASC_HALT_DISABLE_ASYN_USE_SYN_FIX (ushort)0x8300 765#define ASC_HALT_ENABLE_ASYN_USE_SYN_FIX (ushort)0x8400 766#define ASC_HALT_SDTR_REJECTED (ushort)0x4000 767#define ASC_HALT_HOST_COPY_SG_LIST_TO_RISC ( ushort )0x2000 768#define ASC_MAX_QNO 0xF8 769#define ASC_DATA_SEC_BEG (ushort)0x0080 770#define ASC_DATA_SEC_END (ushort)0x0080 771#define ASC_CODE_SEC_BEG (ushort)0x0080 772#define ASC_CODE_SEC_END (ushort)0x0080 773#define ASC_QADR_BEG (0x4000) 774#define ASC_QADR_USED (ushort)(ASC_MAX_QNO * 64) 775#define ASC_QADR_END (ushort)0x7FFF 776#define ASC_QLAST_ADR (ushort)0x7FC0 777#define ASC_QBLK_SIZE 0x40 778#define ASC_BIOS_DATA_QBEG 0xF8 779#define ASC_MIN_ACTIVE_QNO 0x01 780#define ASC_QLINK_END 0xFF 781#define ASC_EEPROM_WORDS 0x10 782#define ASC_MAX_MGS_LEN 0x10 783#define ASC_BIOS_ADDR_DEF 0xDC00 784#define ASC_BIOS_SIZE 0x3800 785#define ASC_BIOS_RAM_OFF 0x3800 786#define ASC_BIOS_RAM_SIZE 0x800 787#define ASC_BIOS_MIN_ADDR 0xC000 788#define ASC_BIOS_MAX_ADDR 0xEC00 789#define ASC_BIOS_BANK_SIZE 0x0400 790#define ASC_MCODE_START_ADDR 0x0080 791#define ASC_CFG0_HOST_INT_ON 0x0020 792#define ASC_CFG0_BIOS_ON 0x0040 793#define ASC_CFG0_VERA_BURST_ON 0x0080 794#define ASC_CFG0_SCSI_PARITY_ON 0x0800 795#define ASC_CFG1_SCSI_TARGET_ON 0x0080 796#define ASC_CFG1_LRAM_8BITS_ON 0x0800 797#define ASC_CFG_MSW_CLR_MASK 0x3080 798#define CSW_TEST1 (ASC_CS_TYPE)0x8000 799#define CSW_AUTO_CONFIG (ASC_CS_TYPE)0x4000 800#define CSW_RESERVED1 (ASC_CS_TYPE)0x2000 801#define CSW_IRQ_WRITTEN (ASC_CS_TYPE)0x1000 802#define CSW_33MHZ_SELECTED (ASC_CS_TYPE)0x0800 803#define CSW_TEST2 (ASC_CS_TYPE)0x0400 804#define CSW_TEST3 (ASC_CS_TYPE)0x0200 805#define CSW_RESERVED2 (ASC_CS_TYPE)0x0100 806#define CSW_DMA_DONE (ASC_CS_TYPE)0x0080 807#define CSW_FIFO_RDY (ASC_CS_TYPE)0x0040 808#define CSW_EEP_READ_DONE (ASC_CS_TYPE)0x0020 809#define CSW_HALTED (ASC_CS_TYPE)0x0010 810#define CSW_SCSI_RESET_ACTIVE (ASC_CS_TYPE)0x0008 811#define CSW_PARITY_ERR (ASC_CS_TYPE)0x0004 812#define CSW_SCSI_RESET_LATCH (ASC_CS_TYPE)0x0002 813#define CSW_INT_PENDING (ASC_CS_TYPE)0x0001 814#define CIW_CLR_SCSI_RESET_INT (ASC_CS_TYPE)0x1000 815#define CIW_INT_ACK (ASC_CS_TYPE)0x0100 816#define CIW_TEST1 (ASC_CS_TYPE)0x0200 817#define CIW_TEST2 (ASC_CS_TYPE)0x0400 818#define CIW_SEL_33MHZ (ASC_CS_TYPE)0x0800 819#define CIW_IRQ_ACT (ASC_CS_TYPE)0x1000 820#define CC_CHIP_RESET (uchar)0x80 821#define CC_SCSI_RESET (uchar)0x40 822#define CC_HALT (uchar)0x20 823#define CC_SINGLE_STEP (uchar)0x10 824#define CC_DMA_ABLE (uchar)0x08 825#define CC_TEST (uchar)0x04 826#define CC_BANK_ONE (uchar)0x02 827#define CC_DIAG (uchar)0x01 828#define ASC_1000_ID0W 0x04C1 829#define ASC_1000_ID0W_FIX 0x00C1 830#define ASC_1000_ID1B 0x25 831#define ASC_EISA_REV_IOP_MASK (0x0C83) 832#define ASC_EISA_CFG_IOP_MASK (0x0C86) 833#define ASC_GET_EISA_SLOT(iop) (PortAddr)((iop) & 0xF000) 834#define INS_HALTINT (ushort)0x6281 835#define INS_HALT (ushort)0x6280 836#define INS_SINT (ushort)0x6200 837#define INS_RFLAG_WTM (ushort)0x7380 838#define ASC_MC_SAVE_CODE_WSIZE 0x500 839#define ASC_MC_SAVE_DATA_WSIZE 0x40 840 841typedef struct asc_mc_saved { 842 ushort data[ASC_MC_SAVE_DATA_WSIZE]; 843 ushort code[ASC_MC_SAVE_CODE_WSIZE]; 844} ASC_MC_SAVED; 845 846#define AscGetQDoneInProgress(port) AscReadLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B) 847#define AscPutQDoneInProgress(port, val) AscWriteLramByte((port), ASCV_Q_DONE_IN_PROGRESS_B, val) 848#define AscGetVarFreeQHead(port) AscReadLramWord((port), ASCV_FREE_Q_HEAD_W) 849#define AscGetVarDoneQTail(port) AscReadLramWord((port), ASCV_DONE_Q_TAIL_W) 850#define AscPutVarFreeQHead(port, val) AscWriteLramWord((port), ASCV_FREE_Q_HEAD_W, val) 851#define AscPutVarDoneQTail(port, val) AscWriteLramWord((port), ASCV_DONE_Q_TAIL_W, val) 852#define AscGetRiscVarFreeQHead(port) AscReadLramByte((port), ASCV_NEXTRDY_B) 853#define AscGetRiscVarDoneQTail(port) AscReadLramByte((port), ASCV_DONENEXT_B) 854#define AscPutRiscVarFreeQHead(port, val) AscWriteLramByte((port), ASCV_NEXTRDY_B, val) 855#define AscPutRiscVarDoneQTail(port, val) AscWriteLramByte((port), ASCV_DONENEXT_B, val) 856#define AscPutMCodeSDTRDoneAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id), (data)) 857#define AscGetMCodeSDTRDoneAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DONE_BEG+(ushort)id)) 858#define AscPutMCodeInitSDTRAtID(port, id, data) AscWriteLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id), data) 859#define AscGetMCodeInitSDTRAtID(port, id) AscReadLramByte((port), (ushort)((ushort)ASCV_SDTR_DATA_BEG+(ushort)id)) 860#define AscGetChipSignatureByte(port) (uchar)inp((port)+IOP_SIG_BYTE) 861#define AscGetChipSignatureWord(port) (ushort)inpw((port)+IOP_SIG_WORD) 862#define AscGetChipVerNo(port) (uchar)inp((port)+IOP_VERSION) 863#define AscGetChipCfgLsw(port) (ushort)inpw((port)+IOP_CONFIG_LOW) 864#define AscGetChipCfgMsw(port) (ushort)inpw((port)+IOP_CONFIG_HIGH) 865#define AscSetChipCfgLsw(port, data) outpw((port)+IOP_CONFIG_LOW, data) 866#define AscSetChipCfgMsw(port, data) outpw((port)+IOP_CONFIG_HIGH, data) 867#define AscGetChipEEPCmd(port) (uchar)inp((port)+IOP_EEP_CMD) 868#define AscSetChipEEPCmd(port, data) outp((port)+IOP_EEP_CMD, data) 869#define AscGetChipEEPData(port) (ushort)inpw((port)+IOP_EEP_DATA) 870#define AscSetChipEEPData(port, data) outpw((port)+IOP_EEP_DATA, data) 871#define AscGetChipLramAddr(port) (ushort)inpw((PortAddr)((port)+IOP_RAM_ADDR)) 872#define AscSetChipLramAddr(port, addr) outpw((PortAddr)((port)+IOP_RAM_ADDR), addr) 873#define AscGetChipLramData(port) (ushort)inpw((port)+IOP_RAM_DATA) 874#define AscSetChipLramData(port, data) outpw((port)+IOP_RAM_DATA, data) 875#define AscGetChipIFC(port) (uchar)inp((port)+IOP_REG_IFC) 876#define AscSetChipIFC(port, data) outp((port)+IOP_REG_IFC, data) 877#define AscGetChipStatus(port) (ASC_CS_TYPE)inpw((port)+IOP_STATUS) 878#define AscSetChipStatus(port, cs_val) outpw((port)+IOP_STATUS, cs_val) 879#define AscGetChipControl(port) (uchar)inp((port)+IOP_CTRL) 880#define AscSetChipControl(port, cc_val) outp((port)+IOP_CTRL, cc_val) 881#define AscGetChipSyn(port) (uchar)inp((port)+IOP_SYN_OFFSET) 882#define AscSetChipSyn(port, data) outp((port)+IOP_SYN_OFFSET, data) 883#define AscSetPCAddr(port, data) outpw((port)+IOP_REG_PC, data) 884#define AscGetPCAddr(port) (ushort)inpw((port)+IOP_REG_PC) 885#define AscIsIntPending(port) (AscGetChipStatus(port) & (CSW_INT_PENDING | CSW_SCSI_RESET_LATCH)) 886#define AscGetChipScsiID(port) ((AscGetChipCfgLsw(port) >> 8) & ASC_MAX_TID) 887#define AscGetExtraControl(port) (uchar)inp((port)+IOP_EXTRA_CONTROL) 888#define AscSetExtraControl(port, data) outp((port)+IOP_EXTRA_CONTROL, data) 889#define AscReadChipAX(port) (ushort)inpw((port)+IOP_REG_AX) 890#define AscWriteChipAX(port, data) outpw((port)+IOP_REG_AX, data) 891#define AscReadChipIX(port) (uchar)inp((port)+IOP_REG_IX) 892#define AscWriteChipIX(port, data) outp((port)+IOP_REG_IX, data) 893#define AscReadChipIH(port) (ushort)inpw((port)+IOP_REG_IH) 894#define AscWriteChipIH(port, data) outpw((port)+IOP_REG_IH, data) 895#define AscReadChipQP(port) (uchar)inp((port)+IOP_REG_QP) 896#define AscWriteChipQP(port, data) outp((port)+IOP_REG_QP, data) 897#define AscReadChipFIFO_L(port) (ushort)inpw((port)+IOP_REG_FIFO_L) 898#define AscWriteChipFIFO_L(port, data) outpw((port)+IOP_REG_FIFO_L, data) 899#define AscReadChipFIFO_H(port) (ushort)inpw((port)+IOP_REG_FIFO_H) 900#define AscWriteChipFIFO_H(port, data) outpw((port)+IOP_REG_FIFO_H, data) 901#define AscReadChipDmaSpeed(port) (uchar)inp((port)+IOP_DMA_SPEED) 902#define AscWriteChipDmaSpeed(port, data) outp((port)+IOP_DMA_SPEED, data) 903#define AscReadChipDA0(port) (ushort)inpw((port)+IOP_REG_DA0) 904#define AscWriteChipDA0(port) outpw((port)+IOP_REG_DA0, data) 905#define AscReadChipDA1(port) (ushort)inpw((port)+IOP_REG_DA1) 906#define AscWriteChipDA1(port) outpw((port)+IOP_REG_DA1, data) 907#define AscReadChipDC0(port) (ushort)inpw((port)+IOP_REG_DC0) 908#define AscWriteChipDC0(port) outpw((port)+IOP_REG_DC0, data) 909#define AscReadChipDC1(port) (ushort)inpw((port)+IOP_REG_DC1) 910#define AscWriteChipDC1(port) outpw((port)+IOP_REG_DC1, data) 911#define AscReadChipDvcID(port) (uchar)inp((port)+IOP_REG_ID) 912#define AscWriteChipDvcID(port, data) outp((port)+IOP_REG_ID, data) 913 914/* 915 * Portable Data Types 916 * 917 * Any instance where a 32-bit long or pointer type is assumed 918 * for precision or HW defined structures, the following define 919 * types must be used. In Linux the char, short, and int types 920 * are all consistent at 8, 16, and 32 bits respectively. Pointers 921 * and long types are 64 bits on Alpha and UltraSPARC. 922 */ 923#define ADV_PADDR __u32 /* Physical address data type. */ 924#define ADV_VADDR __u32 /* Virtual address data type. */ 925#define ADV_DCNT __u32 /* Unsigned Data count type. */ 926#define ADV_SDCNT __s32 /* Signed Data count type. */ 927 928/* 929 * These macros are used to convert a virtual address to a 930 * 32-bit value. This currently can be used on Linux Alpha 931 * which uses 64-bit virtual address but a 32-bit bus address. 932 * This is likely to break in the future, but doing this now 933 * will give us time to change the HW and FW to handle 64-bit 934 * addresses. 935 */ 936#define ADV_VADDR_TO_U32 virt_to_bus 937#define ADV_U32_TO_VADDR bus_to_virt 938 939#define AdvPortAddr void __iomem * /* Virtual memory address size */ 940 941/* 942 * Define Adv Library required memory access macros. 943 */ 944#define ADV_MEM_READB(addr) readb(addr) 945#define ADV_MEM_READW(addr) readw(addr) 946#define ADV_MEM_WRITEB(addr, byte) writeb(byte, addr) 947#define ADV_MEM_WRITEW(addr, word) writew(word, addr) 948#define ADV_MEM_WRITEDW(addr, dword) writel(dword, addr) 949 950#define ADV_CARRIER_COUNT (ASC_DEF_MAX_HOST_QNG + 15) 951 952/* 953 * Define total number of simultaneous maximum element scatter-gather 954 * request blocks per wide adapter. ASC_DEF_MAX_HOST_QNG (253) is the 955 * maximum number of outstanding commands per wide host adapter. Each 956 * command uses one or more ADV_SG_BLOCK each with 15 scatter-gather 957 * elements. Allow each command to have at least one ADV_SG_BLOCK structure. 958 * This allows about 15 commands to have the maximum 17 ADV_SG_BLOCK 959 * structures or 255 scatter-gather elements. 960 */ 961#define ADV_TOT_SG_BLOCK ASC_DEF_MAX_HOST_QNG 962 963/* 964 * Define maximum number of scatter-gather elements per request. 965 */ 966#define ADV_MAX_SG_LIST 255 967#define NO_OF_SG_PER_BLOCK 15 968 969#define ADV_EEP_DVC_CFG_BEGIN (0x00) 970#define ADV_EEP_DVC_CFG_END (0x15) 971#define ADV_EEP_DVC_CTL_BEGIN (0x16) /* location of OEM name */ 972#define ADV_EEP_MAX_WORD_ADDR (0x1E) 973 974#define ADV_EEP_DELAY_MS 100 975 976#define ADV_EEPROM_BIG_ENDIAN 0x8000 /* EEPROM Bit 15 */ 977#define ADV_EEPROM_BIOS_ENABLE 0x4000 /* EEPROM Bit 14 */ 978/* 979 * For the ASC3550 Bit 13 is Termination Polarity control bit. 980 * For later ICs Bit 13 controls whether the CIS (Card Information 981 * Service Section) is loaded from EEPROM. 982 */ 983#define ADV_EEPROM_TERM_POL 0x2000 /* EEPROM Bit 13 */ 984#define ADV_EEPROM_CIS_LD 0x2000 /* EEPROM Bit 13 */ 985/* 986 * ASC38C1600 Bit 11 987 * 988 * If EEPROM Bit 11 is 0 for Function 0, then Function 0 will specify 989 * INT A in the PCI Configuration Space Int Pin field. If it is 1, then 990 * Function 0 will specify INT B. 991 * 992 * If EEPROM Bit 11 is 0 for Function 1, then Function 1 will specify 993 * INT B in the PCI Configuration Space Int Pin field. If it is 1, then 994 * Function 1 will specify INT A. 995 */ 996#define ADV_EEPROM_INTAB 0x0800 /* EEPROM Bit 11 */ 997 998typedef struct adveep_3550_config { 999 /* Word Offset, Description */ 1000 1001 ushort cfg_lsw; /* 00 power up initialization */ 1002 /* bit 13 set - Term Polarity Control */ 1003 /* bit 14 set - BIOS Enable */ 1004 /* bit 15 set - Big Endian Mode */ 1005 ushort cfg_msw; /* 01 unused */ 1006 ushort disc_enable; /* 02 disconnect enable */ 1007 ushort wdtr_able; /* 03 Wide DTR able */ 1008 ushort sdtr_able; /* 04 Synchronous DTR able */ 1009 ushort start_motor; /* 05 send start up motor */ 1010 ushort tagqng_able; /* 06 tag queuing able */ 1011 ushort bios_scan; /* 07 BIOS device control */ 1012 ushort scam_tolerant; /* 08 no scam */ 1013 1014 uchar adapter_scsi_id; /* 09 Host Adapter ID */ 1015 uchar bios_boot_delay; /* power up wait */ 1016 1017 uchar scsi_reset_delay; /* 10 reset delay */ 1018 uchar bios_id_lun; /* first boot device scsi id & lun */ 1019 /* high nibble is lun */ 1020 /* low nibble is scsi id */ 1021 1022 uchar termination; /* 11 0 - automatic */ 1023 /* 1 - low off / high off */ 1024 /* 2 - low off / high on */ 1025 /* 3 - low on / high on */ 1026 /* There is no low on / high off */ 1027 1028 uchar reserved1; /* reserved byte (not used) */ 1029 1030 ushort bios_ctrl; /* 12 BIOS control bits */ 1031 /* bit 0 BIOS don't act as initiator. */ 1032 /* bit 1 BIOS > 1 GB support */ 1033 /* bit 2 BIOS > 2 Disk Support */ 1034 /* bit 3 BIOS don't support removables */ 1035 /* bit 4 BIOS support bootable CD */ 1036 /* bit 5 BIOS scan enabled */ 1037 /* bit 6 BIOS support multiple LUNs */ 1038 /* bit 7 BIOS display of message */ 1039 /* bit 8 SCAM disabled */ 1040 /* bit 9 Reset SCSI bus during init. */ 1041 /* bit 10 */ 1042 /* bit 11 No verbose initialization. */ 1043 /* bit 12 SCSI parity enabled */ 1044 /* bit 13 */ 1045 /* bit 14 */ 1046 /* bit 15 */ 1047 ushort ultra_able; /* 13 ULTRA speed able */ 1048 ushort reserved2; /* 14 reserved */ 1049 uchar max_host_qng; /* 15 maximum host queuing */ 1050 uchar max_dvc_qng; /* maximum per device queuing */ 1051 ushort dvc_cntl; /* 16 control bit for driver */ 1052 ushort bug_fix; /* 17 control bit for bug fix */ 1053 ushort serial_number_word1; /* 18 Board serial number word 1 */ 1054 ushort serial_number_word2; /* 19 Board serial number word 2 */ 1055 ushort serial_number_word3; /* 20 Board serial number word 3 */ 1056 ushort check_sum; /* 21 EEP check sum */ 1057 uchar oem_name[16]; /* 22 OEM name */ 1058 ushort dvc_err_code; /* 30 last device driver error code */ 1059 ushort adv_err_code; /* 31 last uc and Adv Lib error code */ 1060 ushort adv_err_addr; /* 32 last uc error address */ 1061 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ 1062 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 1063 ushort saved_adv_err_addr; /* 35 saved last uc error address */ 1064 ushort num_of_err; /* 36 number of error */ 1065} ADVEEP_3550_CONFIG; 1066 1067typedef struct adveep_38C0800_config { 1068 /* Word Offset, Description */ 1069 1070 ushort cfg_lsw; /* 00 power up initialization */ 1071 /* bit 13 set - Load CIS */ 1072 /* bit 14 set - BIOS Enable */ 1073 /* bit 15 set - Big Endian Mode */ 1074 ushort cfg_msw; /* 01 unused */ 1075 ushort disc_enable; /* 02 disconnect enable */ 1076 ushort wdtr_able; /* 03 Wide DTR able */ 1077 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 1078 ushort start_motor; /* 05 send start up motor */ 1079 ushort tagqng_able; /* 06 tag queuing able */ 1080 ushort bios_scan; /* 07 BIOS device control */ 1081 ushort scam_tolerant; /* 08 no scam */ 1082 1083 uchar adapter_scsi_id; /* 09 Host Adapter ID */ 1084 uchar bios_boot_delay; /* power up wait */ 1085 1086 uchar scsi_reset_delay; /* 10 reset delay */ 1087 uchar bios_id_lun; /* first boot device scsi id & lun */ 1088 /* high nibble is lun */ 1089 /* low nibble is scsi id */ 1090 1091 uchar termination_se; /* 11 0 - automatic */ 1092 /* 1 - low off / high off */ 1093 /* 2 - low off / high on */ 1094 /* 3 - low on / high on */ 1095 /* There is no low on / high off */ 1096 1097 uchar termination_lvd; /* 11 0 - automatic */ 1098 /* 1 - low off / high off */ 1099 /* 2 - low off / high on */ 1100 /* 3 - low on / high on */ 1101 /* There is no low on / high off */ 1102 1103 ushort bios_ctrl; /* 12 BIOS control bits */ 1104 /* bit 0 BIOS don't act as initiator. */ 1105 /* bit 1 BIOS > 1 GB support */ 1106 /* bit 2 BIOS > 2 Disk Support */ 1107 /* bit 3 BIOS don't support removables */ 1108 /* bit 4 BIOS support bootable CD */ 1109 /* bit 5 BIOS scan enabled */ 1110 /* bit 6 BIOS support multiple LUNs */ 1111 /* bit 7 BIOS display of message */ 1112 /* bit 8 SCAM disabled */ 1113 /* bit 9 Reset SCSI bus during init. */ 1114 /* bit 10 */ 1115 /* bit 11 No verbose initialization. */ 1116 /* bit 12 SCSI parity enabled */ 1117 /* bit 13 */ 1118 /* bit 14 */ 1119 /* bit 15 */ 1120 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 1121 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 1122 uchar max_host_qng; /* 15 maximum host queueing */ 1123 uchar max_dvc_qng; /* maximum per device queuing */ 1124 ushort dvc_cntl; /* 16 control bit for driver */ 1125 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 1126 ushort serial_number_word1; /* 18 Board serial number word 1 */ 1127 ushort serial_number_word2; /* 19 Board serial number word 2 */ 1128 ushort serial_number_word3; /* 20 Board serial number word 3 */ 1129 ushort check_sum; /* 21 EEP check sum */ 1130 uchar oem_name[16]; /* 22 OEM name */ 1131 ushort dvc_err_code; /* 30 last device driver error code */ 1132 ushort adv_err_code; /* 31 last uc and Adv Lib error code */ 1133 ushort adv_err_addr; /* 32 last uc error address */ 1134 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ 1135 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 1136 ushort saved_adv_err_addr; /* 35 saved last uc error address */ 1137 ushort reserved36; /* 36 reserved */ 1138 ushort reserved37; /* 37 reserved */ 1139 ushort reserved38; /* 38 reserved */ 1140 ushort reserved39; /* 39 reserved */ 1141 ushort reserved40; /* 40 reserved */ 1142 ushort reserved41; /* 41 reserved */ 1143 ushort reserved42; /* 42 reserved */ 1144 ushort reserved43; /* 43 reserved */ 1145 ushort reserved44; /* 44 reserved */ 1146 ushort reserved45; /* 45 reserved */ 1147 ushort reserved46; /* 46 reserved */ 1148 ushort reserved47; /* 47 reserved */ 1149 ushort reserved48; /* 48 reserved */ 1150 ushort reserved49; /* 49 reserved */ 1151 ushort reserved50; /* 50 reserved */ 1152 ushort reserved51; /* 51 reserved */ 1153 ushort reserved52; /* 52 reserved */ 1154 ushort reserved53; /* 53 reserved */ 1155 ushort reserved54; /* 54 reserved */ 1156 ushort reserved55; /* 55 reserved */ 1157 ushort cisptr_lsw; /* 56 CIS PTR LSW */ 1158 ushort cisprt_msw; /* 57 CIS PTR MSW */ 1159 ushort subsysvid; /* 58 SubSystem Vendor ID */ 1160 ushort subsysid; /* 59 SubSystem ID */ 1161 ushort reserved60; /* 60 reserved */ 1162 ushort reserved61; /* 61 reserved */ 1163 ushort reserved62; /* 62 reserved */ 1164 ushort reserved63; /* 63 reserved */ 1165} ADVEEP_38C0800_CONFIG; 1166 1167typedef struct adveep_38C1600_config { 1168 /* Word Offset, Description */ 1169 1170 ushort cfg_lsw; /* 00 power up initialization */ 1171 /* bit 11 set - Func. 0 INTB, Func. 1 INTA */ 1172 /* clear - Func. 0 INTA, Func. 1 INTB */ 1173 /* bit 13 set - Load CIS */ 1174 /* bit 14 set - BIOS Enable */ 1175 /* bit 15 set - Big Endian Mode */ 1176 ushort cfg_msw; /* 01 unused */ 1177 ushort disc_enable; /* 02 disconnect enable */ 1178 ushort wdtr_able; /* 03 Wide DTR able */ 1179 ushort sdtr_speed1; /* 04 SDTR Speed TID 0-3 */ 1180 ushort start_motor; /* 05 send start up motor */ 1181 ushort tagqng_able; /* 06 tag queuing able */ 1182 ushort bios_scan; /* 07 BIOS device control */ 1183 ushort scam_tolerant; /* 08 no scam */ 1184 1185 uchar adapter_scsi_id; /* 09 Host Adapter ID */ 1186 uchar bios_boot_delay; /* power up wait */ 1187 1188 uchar scsi_reset_delay; /* 10 reset delay */ 1189 uchar bios_id_lun; /* first boot device scsi id & lun */ 1190 /* high nibble is lun */ 1191 /* low nibble is scsi id */ 1192 1193 uchar termination_se; /* 11 0 - automatic */ 1194 /* 1 - low off / high off */ 1195 /* 2 - low off / high on */ 1196 /* 3 - low on / high on */ 1197 /* There is no low on / high off */ 1198 1199 uchar termination_lvd; /* 11 0 - automatic */ 1200 /* 1 - low off / high off */ 1201 /* 2 - low off / high on */ 1202 /* 3 - low on / high on */ 1203 /* There is no low on / high off */ 1204 1205 ushort bios_ctrl; /* 12 BIOS control bits */ 1206 /* bit 0 BIOS don't act as initiator. */ 1207 /* bit 1 BIOS > 1 GB support */ 1208 /* bit 2 BIOS > 2 Disk Support */ 1209 /* bit 3 BIOS don't support removables */ 1210 /* bit 4 BIOS support bootable CD */ 1211 /* bit 5 BIOS scan enabled */ 1212 /* bit 6 BIOS support multiple LUNs */ 1213 /* bit 7 BIOS display of message */ 1214 /* bit 8 SCAM disabled */ 1215 /* bit 9 Reset SCSI bus during init. */ 1216 /* bit 10 Basic Integrity Checking disabled */ 1217 /* bit 11 No verbose initialization. */ 1218 /* bit 12 SCSI parity enabled */ 1219 /* bit 13 AIPP (Asyn. Info. Ph. Prot.) dis. */ 1220 /* bit 14 */ 1221 /* bit 15 */ 1222 ushort sdtr_speed2; /* 13 SDTR speed TID 4-7 */ 1223 ushort sdtr_speed3; /* 14 SDTR speed TID 8-11 */ 1224 uchar max_host_qng; /* 15 maximum host queueing */ 1225 uchar max_dvc_qng; /* maximum per device queuing */ 1226 ushort dvc_cntl; /* 16 control bit for driver */ 1227 ushort sdtr_speed4; /* 17 SDTR speed 4 TID 12-15 */ 1228 ushort serial_number_word1; /* 18 Board serial number word 1 */ 1229 ushort serial_number_word2; /* 19 Board serial number word 2 */ 1230 ushort serial_number_word3; /* 20 Board serial number word 3 */ 1231 ushort check_sum; /* 21 EEP check sum */ 1232 uchar oem_name[16]; /* 22 OEM name */ 1233 ushort dvc_err_code; /* 30 last device driver error code */ 1234 ushort adv_err_code; /* 31 last uc and Adv Lib error code */ 1235 ushort adv_err_addr; /* 32 last uc error address */ 1236 ushort saved_dvc_err_code; /* 33 saved last dev. driver error code */ 1237 ushort saved_adv_err_code; /* 34 saved last uc and Adv Lib error code */ 1238 ushort saved_adv_err_addr; /* 35 saved last uc error address */ 1239 ushort reserved36; /* 36 reserved */ 1240 ushort reserved37; /* 37 reserved */ 1241 ushort reserved38; /* 38 reserved */ 1242 ushort reserved39; /* 39 reserved */ 1243 ushort reserved40; /* 40 reserved */ 1244 ushort reserved41; /* 41 reserved */ 1245 ushort reserved42; /* 42 reserved */ 1246 ushort reserved43; /* 43 reserved */ 1247 ushort reserved44; /* 44 reserved */ 1248 ushort reserved45; /* 45 reserved */ 1249 ushort reserved46; /* 46 reserved */ 1250 ushort reserved47; /* 47 reserved */ 1251 ushort reserved48; /* 48 reserved */ 1252 ushort reserved49; /* 49 reserved */ 1253 ushort reserved50; /* 50 reserved */ 1254 ushort reserved51; /* 51 reserved */ 1255 ushort reserved52; /* 52 reserved */ 1256 ushort reserved53; /* 53 reserved */ 1257 ushort reserved54; /* 54 reserved */ 1258 ushort reserved55; /* 55 reserved */ 1259 ushort cisptr_lsw; /* 56 CIS PTR LSW */ 1260 ushort cisprt_msw; /* 57 CIS PTR MSW */ 1261 ushort subsysvid; /* 58 SubSystem Vendor ID */ 1262 ushort subsysid; /* 59 SubSystem ID */ 1263 ushort reserved60; /* 60 reserved */ 1264 ushort reserved61; /* 61 reserved */ 1265 ushort reserved62; /* 62 reserved */ 1266 ushort reserved63; /* 63 reserved */ 1267} ADVEEP_38C1600_CONFIG; 1268 1269/* 1270 * EEPROM Commands 1271 */ 1272#define ASC_EEP_CMD_DONE 0x0200 1273 1274/* bios_ctrl */ 1275#define BIOS_CTRL_BIOS 0x0001 1276#define BIOS_CTRL_EXTENDED_XLAT 0x0002 1277#define BIOS_CTRL_GT_2_DISK 0x0004 1278#define BIOS_CTRL_BIOS_REMOVABLE 0x0008 1279#define BIOS_CTRL_BOOTABLE_CD 0x0010 1280#define BIOS_CTRL_MULTIPLE_LUN 0x0040 1281#define BIOS_CTRL_DISPLAY_MSG 0x0080 1282#define BIOS_CTRL_NO_SCAM 0x0100 1283#define BIOS_CTRL_RESET_SCSI_BUS 0x0200 1284#define BIOS_CTRL_INIT_VERBOSE 0x0800 1285#define BIOS_CTRL_SCSI_PARITY 0x1000 1286#define BIOS_CTRL_AIPP_DIS 0x2000 1287 1288#define ADV_3550_MEMSIZE 0x2000 /* 8 KB Internal Memory */ 1289 1290#define ADV_38C0800_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 1291 1292#define ADV_38C1600_MEMSIZE 0x4000 /* 16 KB Internal Memory */ 1293 1294/* 1295 * Byte I/O register address from base of 'iop_base'. 1296 */ 1297#define IOPB_INTR_STATUS_REG 0x00 1298#define IOPB_CHIP_ID_1 0x01 1299#define IOPB_INTR_ENABLES 0x02 1300#define IOPB_CHIP_TYPE_REV 0x03 1301#define IOPB_RES_ADDR_4 0x04 1302#define IOPB_RES_ADDR_5 0x05 1303#define IOPB_RAM_DATA 0x06 1304#define IOPB_RES_ADDR_7 0x07 1305#define IOPB_FLAG_REG 0x08 1306#define IOPB_RES_ADDR_9 0x09 1307#define IOPB_RISC_CSR 0x0A 1308#define IOPB_RES_ADDR_B 0x0B 1309#define IOPB_RES_ADDR_C 0x0C 1310#define IOPB_RES_ADDR_D 0x0D 1311#define IOPB_SOFT_OVER_WR 0x0E 1312#define IOPB_RES_ADDR_F 0x0F 1313#define IOPB_MEM_CFG 0x10 1314#define IOPB_RES_ADDR_11 0x11 1315#define IOPB_GPIO_DATA 0x12 1316#define IOPB_RES_ADDR_13 0x13 1317#define IOPB_FLASH_PAGE 0x14 1318#define IOPB_RES_ADDR_15 0x15 1319#define IOPB_GPIO_CNTL 0x16 1320#define IOPB_RES_ADDR_17 0x17 1321#define IOPB_FLASH_DATA 0x18 1322#define IOPB_RES_ADDR_19 0x19 1323#define IOPB_RES_ADDR_1A 0x1A 1324#define IOPB_RES_ADDR_1B 0x1B 1325#define IOPB_RES_ADDR_1C 0x1C 1326#define IOPB_RES_ADDR_1D 0x1D 1327#define IOPB_RES_ADDR_1E 0x1E 1328#define IOPB_RES_ADDR_1F 0x1F 1329#define IOPB_DMA_CFG0 0x20 1330#define IOPB_DMA_CFG1 0x21 1331#define IOPB_TICKLE 0x22 1332#define IOPB_DMA_REG_WR 0x23 1333#define IOPB_SDMA_STATUS 0x24 1334#define IOPB_SCSI_BYTE_CNT 0x25 1335#define IOPB_HOST_BYTE_CNT 0x26 1336#define IOPB_BYTE_LEFT_TO_XFER 0x27 1337#define IOPB_BYTE_TO_XFER_0 0x28 1338#define IOPB_BYTE_TO_XFER_1 0x29 1339#define IOPB_BYTE_TO_XFER_2 0x2A 1340#define IOPB_BYTE_TO_XFER_3 0x2B 1341#define IOPB_ACC_GRP 0x2C 1342#define IOPB_RES_ADDR_2D 0x2D 1343#define IOPB_DEV_ID 0x2E 1344#define IOPB_RES_ADDR_2F 0x2F 1345#define IOPB_SCSI_DATA 0x30 1346#define IOPB_RES_ADDR_31 0x31 1347#define IOPB_RES_ADDR_32 0x32 1348#define IOPB_SCSI_DATA_HSHK 0x33 1349#define IOPB_SCSI_CTRL 0x34 1350#define IOPB_RES_ADDR_35 0x35 1351#define IOPB_RES_ADDR_36 0x36 1352#define IOPB_RES_ADDR_37 0x37 1353#define IOPB_RAM_BIST 0x38 1354#define IOPB_PLL_TEST 0x39 1355#define IOPB_PCI_INT_CFG 0x3A 1356#define IOPB_RES_ADDR_3B 0x3B 1357#define IOPB_RFIFO_CNT 0x3C 1358#define IOPB_RES_ADDR_3D 0x3D 1359#define IOPB_RES_ADDR_3E 0x3E 1360#define IOPB_RES_ADDR_3F 0x3F 1361 1362/* 1363 * Word I/O register address from base of 'iop_base'. 1364 */ 1365#define IOPW_CHIP_ID_0 0x00 /* CID0 */ 1366#define IOPW_CTRL_REG 0x02 /* CC */ 1367#define IOPW_RAM_ADDR 0x04 /* LA */ 1368#define IOPW_RAM_DATA 0x06 /* LD */ 1369#define IOPW_RES_ADDR_08 0x08 1370#define IOPW_RISC_CSR 0x0A /* CSR */ 1371#define IOPW_SCSI_CFG0 0x0C /* CFG0 */ 1372#define IOPW_SCSI_CFG1 0x0E /* CFG1 */ 1373#define IOPW_RES_ADDR_10 0x10 1374#define IOPW_SEL_MASK 0x12 /* SM */ 1375#define IOPW_RES_ADDR_14 0x14 1376#define IOPW_FLASH_ADDR 0x16 /* FA */ 1377#define IOPW_RES_ADDR_18 0x18 1378#define IOPW_EE_CMD 0x1A /* EC */ 1379#define IOPW_EE_DATA 0x1C /* ED */ 1380#define IOPW_SFIFO_CNT 0x1E /* SFC */ 1381#define IOPW_RES_ADDR_20 0x20 1382#define IOPW_Q_BASE 0x22 /* QB */ 1383#define IOPW_QP 0x24 /* QP */ 1384#define IOPW_IX 0x26 /* IX */ 1385#define IOPW_SP 0x28 /* SP */ 1386#define IOPW_PC 0x2A /* PC */ 1387#define IOPW_RES_ADDR_2C 0x2C 1388#define IOPW_RES_ADDR_2E 0x2E 1389#define IOPW_SCSI_DATA 0x30 /* SD */ 1390#define IOPW_SCSI_DATA_HSHK 0x32 /* SDH */ 1391#define IOPW_SCSI_CTRL 0x34 /* SC */ 1392#define IOPW_HSHK_CFG 0x36 /* HCFG */ 1393#define IOPW_SXFR_STATUS 0x36 /* SXS */ 1394#define IOPW_SXFR_CNTL 0x38 /* SXL */ 1395#define IOPW_SXFR_CNTH 0x3A /* SXH */ 1396#define IOPW_RES_ADDR_3C 0x3C 1397#define IOPW_RFIFO_DATA 0x3E /* RFD */ 1398 1399/* 1400 * Doubleword I/O register address from base of 'iop_base'. 1401 */ 1402#define IOPDW_RES_ADDR_0 0x00 1403#define IOPDW_RAM_DATA 0x04 1404#define IOPDW_RES_ADDR_8 0x08 1405#define IOPDW_RES_ADDR_C 0x0C 1406#define IOPDW_RES_ADDR_10 0x10 1407#define IOPDW_COMMA 0x14 1408#define IOPDW_COMMB 0x18 1409#define IOPDW_RES_ADDR_1C 0x1C 1410#define IOPDW_SDMA_ADDR0 0x20 1411#define IOPDW_SDMA_ADDR1 0x24 1412#define IOPDW_SDMA_COUNT 0x28 1413#define IOPDW_SDMA_ERROR 0x2C 1414#define IOPDW_RDMA_ADDR0 0x30 1415#define IOPDW_RDMA_ADDR1 0x34 1416#define IOPDW_RDMA_COUNT 0x38 1417#define IOPDW_RDMA_ERROR 0x3C 1418 1419#define ADV_CHIP_ID_BYTE 0x25 1420#define ADV_CHIP_ID_WORD 0x04C1 1421 1422#define ADV_INTR_ENABLE_HOST_INTR 0x01 1423#define ADV_INTR_ENABLE_SEL_INTR 0x02 1424#define ADV_INTR_ENABLE_DPR_INTR 0x04 1425#define ADV_INTR_ENABLE_RTA_INTR 0x08 1426#define ADV_INTR_ENABLE_RMA_INTR 0x10 1427#define ADV_INTR_ENABLE_RST_INTR 0x20 1428#define ADV_INTR_ENABLE_DPE_INTR 0x40 1429#define ADV_INTR_ENABLE_GLOBAL_INTR 0x80 1430 1431#define ADV_INTR_STATUS_INTRA 0x01 1432#define ADV_INTR_STATUS_INTRB 0x02 1433#define ADV_INTR_STATUS_INTRC 0x04 1434 1435#define ADV_RISC_CSR_STOP (0x0000) 1436#define ADV_RISC_TEST_COND (0x2000) 1437#define ADV_RISC_CSR_RUN (0x4000) 1438#define ADV_RISC_CSR_SINGLE_STEP (0x8000) 1439 1440#define ADV_CTRL_REG_HOST_INTR 0x0100 1441#define ADV_CTRL_REG_SEL_INTR 0x0200 1442#define ADV_CTRL_REG_DPR_INTR 0x0400 1443#define ADV_CTRL_REG_RTA_INTR 0x0800 1444#define ADV_CTRL_REG_RMA_INTR 0x1000 1445#define ADV_CTRL_REG_RES_BIT14 0x2000 1446#define ADV_CTRL_REG_DPE_INTR 0x4000 1447#define ADV_CTRL_REG_POWER_DONE 0x8000 1448#define ADV_CTRL_REG_ANY_INTR 0xFF00 1449 1450#define ADV_CTRL_REG_CMD_RESET 0x00C6 1451#define ADV_CTRL_REG_CMD_WR_IO_REG 0x00C5 1452#define ADV_CTRL_REG_CMD_RD_IO_REG 0x00C4 1453#define ADV_CTRL_REG_CMD_WR_PCI_CFG_SPACE 0x00C3 1454#define ADV_CTRL_REG_CMD_RD_PCI_CFG_SPACE 0x00C2 1455 1456#define ADV_TICKLE_NOP 0x00 1457#define ADV_TICKLE_A 0x01 1458#define ADV_TICKLE_B 0x02 1459#define ADV_TICKLE_C 0x03 1460 1461#define AdvIsIntPending(port) \ 1462 (AdvReadWordRegister(port, IOPW_CTRL_REG) & ADV_CTRL_REG_HOST_INTR) 1463 1464/* 1465 * SCSI_CFG0 Register bit definitions 1466 */ 1467#define TIMER_MODEAB 0xC000 /* Watchdog, Second, and Select. Timer Ctrl. */ 1468#define PARITY_EN 0x2000 /* Enable SCSI Parity Error detection */ 1469#define EVEN_PARITY 0x1000 /* Select Even Parity */ 1470#define WD_LONG 0x0800 /* Watchdog Interval, 1: 57 min, 0: 13 sec */ 1471#define QUEUE_128 0x0400 /* Queue Size, 1: 128 byte, 0: 64 byte */ 1472#define PRIM_MODE 0x0100 /* Primitive SCSI mode */ 1473#define SCAM_EN 0x0080 /* Enable SCAM selection */ 1474#define SEL_TMO_LONG 0x0040 /* Sel/Resel Timeout, 1: 400 ms, 0: 1.6 ms */ 1475#define CFRM_ID 0x0020 /* SCAM id sel. confirm., 1: fast, 0: 6.4 ms */ 1476#define OUR_ID_EN 0x0010 /* Enable OUR_ID bits */ 1477#define OUR_ID 0x000F /* SCSI ID */ 1478 1479/* 1480 * SCSI_CFG1 Register bit definitions 1481 */ 1482#define BIG_ENDIAN 0x8000 /* Enable Big Endian Mode MIO:15, EEP:15 */ 1483#define TERM_POL 0x2000 /* Terminator Polarity Ctrl. MIO:13, EEP:13 */ 1484#define SLEW_RATE 0x1000 /* SCSI output buffer slew rate */ 1485#define FILTER_SEL 0x0C00 /* Filter Period Selection */ 1486#define FLTR_DISABLE 0x0000 /* Input Filtering Disabled */ 1487#define FLTR_11_TO_20NS 0x0800 /* Input Filtering 11ns to 20ns */ 1488#define FLTR_21_TO_39NS 0x0C00 /* Input Filtering 21ns to 39ns */ 1489#define ACTIVE_DBL 0x0200 /* Disable Active Negation */ 1490#define DIFF_MODE 0x0100 /* SCSI differential Mode (Read-Only) */ 1491#define DIFF_SENSE 0x0080 /* 1: No SE cables, 0: SE cable (Read-Only) */ 1492#define TERM_CTL_SEL 0x0040 /* Enable TERM_CTL_H and TERM_CTL_L */ 1493#define TERM_CTL 0x0030 /* External SCSI Termination Bits */ 1494#define TERM_CTL_H 0x0020 /* Enable External SCSI Upper Termination */ 1495#define TERM_CTL_L 0x0010 /* Enable External SCSI Lower Termination */ 1496#define CABLE_DETECT 0x000F /* External SCSI Cable Connection Status */ 1497 1498/* 1499 * Addendum for ASC-38C0800 Chip 1500 * 1501 * The ASC-38C1600 Chip uses the same definitions except that the 1502 * bus mode override bits [12:10] have been moved to byte register 1503 * offset 0xE (IOPB_SOFT_OVER_WR) bits [12:10]. The [12:10] bits in 1504 * SCSI_CFG1 are read-only and always available. Bit 14 (DIS_TERM_DRV) 1505 * is not needed. The [12:10] bits in IOPB_SOFT_OVER_WR are write-only. 1506 * Also each ASC-38C1600 function or channel uses only cable bits [5:4] 1507 * and [1:0]. Bits [14], [7:6], [3:2] are unused. 1508 */ 1509#define DIS_TERM_DRV 0x4000 /* 1: Read c_det[3:0], 0: cannot read */ 1510#define HVD_LVD_SE 0x1C00 /* Device Detect Bits */ 1511#define HVD 0x1000 /* HVD Device Detect */ 1512#define LVD 0x0800 /* LVD Device Detect */ 1513#define SE 0x0400 /* SE Device Detect */ 1514#define TERM_LVD 0x00C0 /* LVD Termination Bits */ 1515#define TERM_LVD_HI 0x0080 /* Enable LVD Upper Termination */ 1516#define TERM_LVD_LO 0x0040 /* Enable LVD Lower Termination */ 1517#define TERM_SE 0x0030 /* SE Termination Bits */ 1518#define TERM_SE_HI 0x0020 /* Enable SE Upper Termination */ 1519#define TERM_SE_LO 0x0010 /* Enable SE Lower Termination */ 1520#define C_DET_LVD 0x000C /* LVD Cable Detect Bits */ 1521#define C_DET3 0x0008 /* Cable Detect for LVD External Wide */ 1522#define C_DET2 0x0004 /* Cable Detect for LVD Internal Wide */ 1523#define C_DET_SE 0x0003 /* SE Cable Detect Bits */ 1524#define C_DET1 0x0002 /* Cable Detect for SE Internal Wide */ 1525#define C_DET0 0x0001 /* Cable Detect for SE Internal Narrow */ 1526 1527#define CABLE_ILLEGAL_A 0x7 1528 /* x 0 0 0 | on on | Illegal (all 3 connectors are used) */ 1529 1530#define CABLE_ILLEGAL_B 0xB 1531 /* 0 x 0 0 | on on | Illegal (all 3 connectors are used) */ 1532 1533/* 1534 * MEM_CFG Register bit definitions 1535 */ 1536#define BIOS_EN 0x40 /* BIOS Enable MIO:14,EEP:14 */ 1537#define FAST_EE_CLK 0x20 /* Diagnostic Bit */ 1538#define RAM_SZ 0x1C /* Specify size of RAM to RISC */ 1539#define RAM_SZ_2KB 0x00 /* 2 KB */ 1540#define RAM_SZ_4KB 0x04 /* 4 KB */ 1541#define RAM_SZ_8KB 0x08 /* 8 KB */ 1542#define RAM_SZ_16KB 0x0C /* 16 KB */ 1543#define RAM_SZ_32KB 0x10 /* 32 KB */ 1544#define RAM_SZ_64KB 0x14 /* 64 KB */ 1545 1546/* 1547 * DMA_CFG0 Register bit definitions 1548 * 1549 * This register is only accessible to the host. 1550 */ 1551#define BC_THRESH_ENB 0x80 /* PCI DMA Start Conditions */ 1552#define FIFO_THRESH 0x70 /* PCI DMA FIFO Threshold */ 1553#define FIFO_THRESH_16B 0x00 /* 16 bytes */ 1554#define FIFO_THRESH_32B 0x20 /* 32 bytes */ 1555#define FIFO_THRESH_48B 0x30 /* 48 bytes */ 1556#define FIFO_THRESH_64B 0x40 /* 64 bytes */ 1557#define FIFO_THRESH_80B 0x50 /* 80 bytes (default) */ 1558#define FIFO_THRESH_96B 0x60 /* 96 bytes */ 1559#define FIFO_THRESH_112B 0x70 /* 112 bytes */ 1560#define START_CTL 0x0C /* DMA start conditions */ 1561#define START_CTL_TH 0x00 /* Wait threshold level (default) */ 1562#define START_CTL_ID 0x04 /* Wait SDMA/SBUS idle */ 1563#define START_CTL_THID 0x08 /* Wait threshold and SDMA/SBUS idle */ 1564#define START_CTL_EMFU 0x0C /* Wait SDMA FIFO empty/full */ 1565#define READ_CMD 0x03 /* Memory Read Method */ 1566#define READ_CMD_MR 0x00 /* Memory Read */ 1567#define READ_CMD_MRL 0x02 /* Memory Read Long */ 1568#define READ_CMD_MRM 0x03 /* Memory Read Multiple (default) */ 1569 1570/* 1571 * ASC-38C0800 RAM BIST Register bit definitions 1572 */ 1573#define RAM_TEST_MODE 0x80 1574#define PRE_TEST_MODE 0x40 1575#define NORMAL_MODE 0x00 1576#define RAM_TEST_DONE 0x10 1577#define RAM_TEST_STATUS 0x0F 1578#define RAM_TEST_HOST_ERROR 0x08 1579#define RAM_TEST_INTRAM_ERROR 0x04 1580#define RAM_TEST_RISC_ERROR 0x02 1581#define RAM_TEST_SCSI_ERROR 0x01 1582#define RAM_TEST_SUCCESS 0x00 1583#define PRE_TEST_VALUE 0x05 1584#define NORMAL_VALUE 0x00 1585 1586/* 1587 * ASC38C1600 Definitions 1588 * 1589 * IOPB_PCI_INT_CFG Bit Field Definitions 1590 */ 1591 1592#define INTAB_LD 0x80 /* Value loaded from EEPROM Bit 11. */ 1593 1594/* 1595 * Bit 1 can be set to change the interrupt for the Function to operate in 1596 * Totem Pole mode. By default Bit 1 is 0 and the interrupt operates in 1597 * Open Drain mode. Both functions of the ASC38C1600 must be set to the same 1598 * mode, otherwise the operating mode is undefined. 1599 */ 1600#define TOTEMPOLE 0x02 1601 1602/* 1603 * Bit 0 can be used to change the Int Pin for the Function. The value is 1604 * 0 by default for both Functions with Function 0 using INT A and Function 1605 * B using INT B. For Function 0 if set, INT B is used. For Function 1 if set, 1606 * INT A is used. 1607 * 1608 * EEPROM Word 0 Bit 11 for each Function may change the initial Int Pin 1609 * value specified in the PCI Configuration Space. 1610 */ 1611#define INTAB 0x01 1612 1613/* 1614 * Adv Library Status Definitions 1615 */ 1616#define ADV_TRUE 1 1617#define ADV_FALSE 0 1618#define ADV_SUCCESS 1 1619#define ADV_BUSY 0 1620#define ADV_ERROR (-1) 1621 1622/* 1623 * ADV_DVC_VAR 'warn_code' values 1624 */ 1625#define ASC_WARN_BUSRESET_ERROR 0x0001 /* SCSI Bus Reset error */ 1626#define ASC_WARN_EEPROM_CHKSUM 0x0002 /* EEP check sum error */ 1627#define ASC_WARN_EEPROM_TERMINATION 0x0004 /* EEP termination bad field */ 1628#define ASC_WARN_ERROR 0xFFFF /* ADV_ERROR return */ 1629 1630#define ADV_MAX_TID 15 /* max. target identifier */ 1631#define ADV_MAX_LUN 7 /* max. logical unit number */ 1632 1633/* 1634 * Fixed locations of microcode operating variables. 1635 */ 1636#define ASC_MC_CODE_BEGIN_ADDR 0x0028 /* microcode start address */ 1637#define ASC_MC_CODE_END_ADDR 0x002A /* microcode end address */ 1638#define ASC_MC_CODE_CHK_SUM 0x002C /* microcode code checksum */ 1639#define ASC_MC_VERSION_DATE 0x0038 /* microcode version */ 1640#define ASC_MC_VERSION_NUM 0x003A /* microcode number */ 1641#define ASC_MC_BIOSMEM 0x0040 /* BIOS RISC Memory Start */ 1642#define ASC_MC_BIOSLEN 0x0050 /* BIOS RISC Memory Length */ 1643#define ASC_MC_BIOS_SIGNATURE 0x0058 /* BIOS Signature 0x55AA */ 1644#define ASC_MC_BIOS_VERSION 0x005A /* BIOS Version (2 bytes) */ 1645#define ASC_MC_SDTR_SPEED1 0x0090 /* SDTR Speed for TID 0-3 */ 1646#define ASC_MC_SDTR_SPEED2 0x0092 /* SDTR Speed for TID 4-7 */ 1647#define ASC_MC_SDTR_SPEED3 0x0094 /* SDTR Speed for TID 8-11 */ 1648#define ASC_MC_SDTR_SPEED4 0x0096 /* SDTR Speed for TID 12-15 */ 1649#define ASC_MC_CHIP_TYPE 0x009A 1650#define ASC_MC_INTRB_CODE 0x009B 1651#define ASC_MC_WDTR_ABLE 0x009C 1652#define ASC_MC_SDTR_ABLE 0x009E 1653#define ASC_MC_TAGQNG_ABLE 0x00A0 1654#define ASC_MC_DISC_ENABLE 0x00A2 1655#define ASC_MC_IDLE_CMD_STATUS 0x00A4 1656#define ASC_MC_IDLE_CMD 0x00A6 1657#define ASC_MC_IDLE_CMD_PARAMETER 0x00A8 1658#define ASC_MC_DEFAULT_SCSI_CFG0 0x00AC 1659#define ASC_MC_DEFAULT_SCSI_CFG1 0x00AE 1660#define ASC_MC_DEFAULT_MEM_CFG 0x00B0 1661#define ASC_MC_DEFAULT_SEL_MASK 0x00B2 1662#define ASC_MC_SDTR_DONE 0x00B6 1663#define ASC_MC_NUMBER_OF_QUEUED_CMD 0x00C0 1664#define ASC_MC_NUMBER_OF_MAX_CMD 0x00D0 1665#define ASC_MC_DEVICE_HSHK_CFG_TABLE 0x0100 1666#define ASC_MC_CONTROL_FLAG 0x0122 /* Microcode control flag. */ 1667#define ASC_MC_WDTR_DONE 0x0124 1668#define ASC_MC_CAM_MODE_MASK 0x015E /* CAM mode TID bitmask. */ 1669#define ASC_MC_ICQ 0x0160 1670#define ASC_MC_IRQ 0x0164 1671#define ASC_MC_PPR_ABLE 0x017A 1672 1673/* 1674 * BIOS LRAM variable absolute offsets. 1675 */ 1676#define BIOS_CODESEG 0x54 1677#define BIOS_CODELEN 0x56 1678#define BIOS_SIGNATURE 0x58 1679#define BIOS_VERSION 0x5A 1680 1681/* 1682 * Microcode Control Flags 1683 * 1684 * Flags set by the Adv Library in RISC variable 'control_flag' (0x122) 1685 * and handled by the microcode. 1686 */ 1687#define CONTROL_FLAG_IGNORE_PERR 0x0001 /* Ignore DMA Parity Errors */ 1688#define CONTROL_FLAG_ENABLE_AIPP 0x0002 /* Enabled AIPP checking. */ 1689 1690/* 1691 * ASC_MC_DEVICE_HSHK_CFG_TABLE microcode table or HSHK_CFG register format 1692 */ 1693#define HSHK_CFG_WIDE_XFR 0x8000 1694#define HSHK_CFG_RATE 0x0F00 1695#define HSHK_CFG_OFFSET 0x001F 1696 1697#define ASC_DEF_MAX_HOST_QNG 0xFD /* Max. number of host commands (253) */ 1698#define ASC_DEF_MIN_HOST_QNG 0x10 /* Min. number of host commands (16) */ 1699#define ASC_DEF_MAX_DVC_QNG 0x3F /* Max. number commands per device (63) */ 1700#define ASC_DEF_MIN_DVC_QNG 0x04 /* Min. number commands per device (4) */ 1701 1702#define ASC_QC_DATA_CHECK 0x01 /* Require ASC_QC_DATA_OUT set or clear. */ 1703#define ASC_QC_DATA_OUT 0x02 /* Data out DMA transfer. */ 1704#define ASC_QC_START_MOTOR 0x04 /* Send auto-start motor before request. */ 1705#define ASC_QC_NO_OVERRUN 0x08 /* Don't report overrun. */ 1706#define ASC_QC_FREEZE_TIDQ 0x10 1707 1708#define ASC_QSC_NO_DISC 0x01 /* Don't allow disconnect for request. */ 1709#define ASC_QSC_NO_TAGMSG 0x02 /* Don't allow tag queuing for request. */ 1710#define ASC_QSC_NO_SYNC 0x04 /* Don't use Synch. transfer on request. */ 1711#define ASC_QSC_NO_WIDE 0x08 /* Don't use Wide transfer on request. */ 1712#define ASC_QSC_REDO_DTR 0x10 /* Renegotiate WDTR/SDTR before request. */ 1713/* 1714 * Note: If a Tag Message is to be sent and neither ASC_QSC_HEAD_TAG or 1715 * ASC_QSC_ORDERED_TAG is set, then a Simple Tag Message (0x20) is used. 1716 */ 1717#define ASC_QSC_HEAD_TAG 0x40 /* Use Head Tag Message (0x21). */ 1718#define ASC_QSC_ORDERED_TAG 0x80 /* Use Ordered Tag Message (0x22). */ 1719 1720/* 1721 * All fields here are accessed by the board microcode and need to be 1722 * little-endian. 1723 */ 1724typedef struct adv_carr_t { 1725 ADV_VADDR carr_va; /* Carrier Virtual Address */ 1726 ADV_PADDR carr_pa; /* Carrier Physical Address */ 1727 ADV_VADDR areq_vpa; /* ASC_SCSI_REQ_Q Virtual or Physical Address */ 1728 /* 1729 * next_vpa [31:4] Carrier Virtual or Physical Next Pointer 1730 * 1731 * next_vpa [3:1] Reserved Bits 1732 * next_vpa [0] Done Flag set in Response Queue. 1733 */ 1734 ADV_VADDR next_vpa; 1735} ADV_CARR_T; 1736 1737/* 1738 * Mask used to eliminate low 4 bits of carrier 'next_vpa' field. 1739 */ 1740#define ASC_NEXT_VPA_MASK 0xFFFFFFF0 1741 1742#define ASC_RQ_DONE 0x00000001 1743#define ASC_RQ_GOOD 0x00000002 1744#define ASC_CQ_STOPPER 0x00000000 1745 1746#define ASC_GET_CARRP(carrp) ((carrp) & ASC_NEXT_VPA_MASK) 1747 1748#define ADV_CARRIER_NUM_PAGE_CROSSING \ 1749 (((ADV_CARRIER_COUNT * sizeof(ADV_CARR_T)) + (PAGE_SIZE - 1))/PAGE_SIZE) 1750 1751#define ADV_CARRIER_BUFSIZE \ 1752 ((ADV_CARRIER_COUNT + ADV_CARRIER_NUM_PAGE_CROSSING) * sizeof(ADV_CARR_T)) 1753 1754/* 1755 * ASC_SCSI_REQ_Q 'a_flag' definitions 1756 * 1757 * The Adv Library should limit use to the lower nibble (4 bits) of 1758 * a_flag. Drivers are free to use the upper nibble (4 bits) of a_flag. 1759 */ 1760#define ADV_POLL_REQUEST 0x01 /* poll for request completion */ 1761#define ADV_SCSIQ_DONE 0x02 /* request done */ 1762#define ADV_DONT_RETRY 0x08 /* don't do retry */ 1763 1764#define ADV_CHIP_ASC3550 0x01 /* Ultra-Wide IC */ 1765#define ADV_CHIP_ASC38C0800 0x02 /* Ultra2-Wide/LVD IC */ 1766#define ADV_CHIP_ASC38C1600 0x03 /* Ultra3-Wide/LVD2 IC */ 1767 1768/* 1769 * Adapter temporary configuration structure 1770 * 1771 * This structure can be discarded after initialization. Don't add 1772 * fields here needed after initialization. 1773 * 1774 * Field naming convention: 1775 * 1776 * *_enable indicates the field enables or disables a feature. The 1777 * value of the field is never reset. 1778 */ 1779typedef struct adv_dvc_cfg { 1780 ushort disc_enable; /* enable disconnection */ 1781 uchar chip_version; /* chip version */ 1782 uchar termination; /* Term. Ctrl. bits 6-5 of SCSI_CFG1 register */ 1783 ushort control_flag; /* Microcode Control Flag */ 1784 ushort mcode_date; /* Microcode date */ 1785 ushort mcode_version; /* Microcode version */ 1786 ushort serial1; /* EEPROM serial number word 1 */ 1787 ushort serial2; /* EEPROM serial number word 2 */ 1788 ushort serial3; /* EEPROM serial number word 3 */ 1789} ADV_DVC_CFG; 1790 1791struct adv_dvc_var; 1792struct adv_scsi_req_q; 1793 1794typedef struct asc_sg_block { 1795 uchar reserved1; 1796 uchar reserved2; 1797 uchar reserved3; 1798 uchar sg_cnt; /* Valid entries in block. */ 1799 ADV_PADDR sg_ptr; /* Pointer to next sg block. */ 1800 struct { 1801 ADV_PADDR sg_addr; /* SG element address. */ 1802 ADV_DCNT sg_count; /* SG element count. */ 1803 } sg_list[NO_OF_SG_PER_BLOCK]; 1804} ADV_SG_BLOCK; 1805 1806/* 1807 * ADV_SCSI_REQ_Q - microcode request structure 1808 * 1809 * All fields in this structure up to byte 60 are used by the microcode. 1810 * The microcode makes assumptions about the size and ordering of fields 1811 * in this structure. Do not change the structure definition here without 1812 * coordinating the change with the microcode. 1813 * 1814 * All fields accessed by microcode must be maintained in little_endian 1815 * order. 1816 */ 1817typedef struct adv_scsi_req_q { 1818 uchar cntl; /* Ucode flags and state (ASC_MC_QC_*). */ 1819 uchar target_cmd; 1820 uchar target_id; /* Device target identifier. */ 1821 uchar target_lun; /* Device target logical unit number. */ 1822 ADV_PADDR data_addr; /* Data buffer physical address. */ 1823 ADV_DCNT data_cnt; /* Data count. Ucode sets to residual. */ 1824 ADV_PADDR sense_addr; 1825 ADV_PADDR carr_pa; 1826 uchar mflag; 1827 uchar sense_len; 1828 uchar cdb_len; /* SCSI CDB length. Must <= 16 bytes. */ 1829 uchar scsi_cntl; 1830 uchar done_status; /* Completion status. */ 1831 uchar scsi_status; /* SCSI status byte. */ 1832 uchar host_status; /* Ucode host status. */ 1833 uchar sg_working_ix; 1834 uchar cdb[12]; /* SCSI CDB bytes 0-11. */ 1835 ADV_PADDR sg_real_addr; /* SG list physical address. */ 1836 ADV_PADDR scsiq_rptr; 1837 uchar cdb16[4]; /* SCSI CDB bytes 12-15. */ 1838 ADV_VADDR scsiq_ptr; 1839 ADV_VADDR carr_va; 1840 /* 1841 * End of microcode structure - 60 bytes. The rest of the structure 1842 * is used by the Adv Library and ignored by the microcode. 1843 */ 1844 ADV_VADDR srb_ptr; 1845 ADV_SG_BLOCK *sg_list_ptr; /* SG list virtual address. */ 1846 char *vdata_addr; /* Data buffer virtual address. */ 1847 uchar a_flag; 1848 uchar pad[2]; /* Pad out to a word boundary. */ 1849} ADV_SCSI_REQ_Q; 1850 1851/* 1852 * The following two structures are used to process Wide Board requests. 1853 * 1854 * The ADV_SCSI_REQ_Q structure in adv_req_t is passed to the Adv Library 1855 * and microcode with the ADV_SCSI_REQ_Q field 'srb_ptr' pointing to the 1856 * adv_req_t. The adv_req_t structure 'cmndp' field in turn points to the 1857 * Mid-Level SCSI request structure. 1858 * 1859 * Zero or more ADV_SG_BLOCK are used with each ADV_SCSI_REQ_Q. Each 1860 * ADV_SG_BLOCK structure holds 15 scatter-gather elements. Under Linux 1861 * up to 255 scatter-gather elements may be used per request or 1862 * ADV_SCSI_REQ_Q. 1863 * 1864 * Both structures must be 32 byte aligned. 1865 */ 1866typedef struct adv_sgblk { 1867 ADV_SG_BLOCK sg_block; /* Sgblock structure. */ 1868 uchar align[32]; /* Sgblock structure padding. */ 1869 struct adv_sgblk *next_sgblkp; /* Next scatter-gather structure. */ 1870} adv_sgblk_t; 1871 1872typedef struct adv_req { 1873 ADV_SCSI_REQ_Q scsi_req_q; /* Adv Library request structure. */ 1874 uchar align[32]; /* Request structure padding. */ 1875 struct scsi_cmnd *cmndp; /* Mid-Level SCSI command pointer. */ 1876 adv_sgblk_t *sgblkp; /* Adv Library scatter-gather pointer. */ 1877 struct adv_req *next_reqp; /* Next Request Structure. */ 1878} adv_req_t; 1879 1880/* 1881 * Adapter operation variable structure. 1882 * 1883 * One structure is required per host adapter. 1884 * 1885 * Field naming convention: 1886 * 1887 * *_able indicates both whether a feature should be enabled or disabled 1888 * and whether a device isi capable of the feature. At initialization 1889 * this field may be set, but later if a device is found to be incapable 1890 * of the feature, the field is cleared. 1891 */ 1892typedef struct adv_dvc_var { 1893 AdvPortAddr iop_base; /* I/O port address */ 1894 ushort err_code; /* fatal error code */ 1895 ushort bios_ctrl; /* BIOS control word, EEPROM word 12 */ 1896 ushort wdtr_able; /* try WDTR for a device */ 1897 ushort sdtr_able; /* try SDTR for a device */ 1898 ushort ultra_able; /* try SDTR Ultra speed for a device */ 1899 ushort sdtr_speed1; /* EEPROM SDTR Speed for TID 0-3 */ 1900 ushort sdtr_speed2; /* EEPROM SDTR Speed for TID 4-7 */ 1901 ushort sdtr_speed3; /* EEPROM SDTR Speed for TID 8-11 */ 1902 ushort sdtr_speed4; /* EEPROM SDTR Speed for TID 12-15 */ 1903 ushort tagqng_able; /* try tagged queuing with a device */ 1904 ushort ppr_able; /* PPR message capable per TID bitmask. */ 1905 uchar max_dvc_qng; /* maximum number of tagged commands per device */ 1906 ushort start_motor; /* start motor command allowed */ 1907 uchar scsi_reset_wait; /* delay in seconds after scsi bus reset */ 1908 uchar chip_no; /* should be assigned by caller */ 1909 uchar max_host_qng; /* maximum number of Q'ed command allowed */ 1910 ushort no_scam; /* scam_tolerant of EEPROM */ 1911 struct asc_board *drv_ptr; /* driver pointer to private structure */ 1912 uchar chip_scsi_id; /* chip SCSI target ID */ 1913 uchar chip_type; 1914 uchar bist_err_code; 1915 ADV_CARR_T *carrier_buf; 1916 ADV_CARR_T *carr_freelist; /* Carrier free list. */ 1917 ADV_CARR_T *icq_sp; /* Initiator command queue stopper pointer. */ 1918 ADV_CARR_T *irq_sp; /* Initiator response queue stopper pointer. */ 1919 ushort carr_pending_cnt; /* Count of pending carriers. */ 1920 struct adv_req *orig_reqp; /* adv_req_t memory block. */ 1921 /* 1922 * Note: The following fields will not be used after initialization. The 1923 * driver may discard the buffer after initialization is done. 1924 */ 1925 ADV_DVC_CFG *cfg; /* temporary configuration structure */ 1926} ADV_DVC_VAR; 1927 1928/* 1929 * Microcode idle loop commands 1930 */ 1931#define IDLE_CMD_COMPLETED 0 1932#define IDLE_CMD_STOP_CHIP 0x0001 1933#define IDLE_CMD_STOP_CHIP_SEND_INT 0x0002 1934#define IDLE_CMD_SEND_INT 0x0004 1935#define IDLE_CMD_ABORT 0x0008 1936#define IDLE_CMD_DEVICE_RESET 0x0010 1937#define IDLE_CMD_SCSI_RESET_START 0x0020 /* Assert SCSI Bus Reset */ 1938#define IDLE_CMD_SCSI_RESET_END 0x0040 /* Deassert SCSI Bus Reset */ 1939#define IDLE_CMD_SCSIREQ 0x0080 1940 1941#define IDLE_CMD_STATUS_SUCCESS 0x0001 1942#define IDLE_CMD_STATUS_FAILURE 0x0002 1943 1944/* 1945 * AdvSendIdleCmd() flag definitions. 1946 */ 1947#define ADV_NOWAIT 0x01 1948 1949/* 1950 * Wait loop time out values. 1951 */ 1952#define SCSI_WAIT_100_MSEC 100UL /* 100 milliseconds */ 1953#define SCSI_US_PER_MSEC 1000 /* microseconds per millisecond */ 1954#define SCSI_MAX_RETRY 10 /* retry count */ 1955 1956#define ADV_ASYNC_RDMA_FAILURE 0x01 /* Fatal RDMA failure. */ 1957#define ADV_ASYNC_SCSI_BUS_RESET_DET 0x02 /* Detected SCSI Bus Reset. */ 1958#define ADV_ASYNC_CARRIER_READY_FAILURE 0x03 /* Carrier Ready failure. */ 1959#define ADV_RDMA_IN_CARR_AND_Q_INVALID 0x04 /* RDMAed-in data invalid. */ 1960 1961#define ADV_HOST_SCSI_BUS_RESET 0x80 /* Host Initiated SCSI Bus Reset. */ 1962 1963/* Read byte from a register. */ 1964#define AdvReadByteRegister(iop_base, reg_off) \ 1965 (ADV_MEM_READB((iop_base) + (reg_off))) 1966 1967/* Write byte to a register. */ 1968#define AdvWriteByteRegister(iop_base, reg_off, byte) \ 1969 (ADV_MEM_WRITEB((iop_base) + (reg_off), (byte))) 1970 1971/* Read word (2 bytes) from a register. */ 1972#define AdvReadWordRegister(iop_base, reg_off) \ 1973 (ADV_MEM_READW((iop_base) + (reg_off))) 1974 1975/* Write word (2 bytes) to a register. */ 1976#define AdvWriteWordRegister(iop_base, reg_off, word) \ 1977 (ADV_MEM_WRITEW((iop_base) + (reg_off), (word))) 1978 1979/* Write dword (4 bytes) to a register. */ 1980#define AdvWriteDWordRegister(iop_base, reg_off, dword) \ 1981 (ADV_MEM_WRITEDW((iop_base) + (reg_off), (dword))) 1982 1983/* Read byte from LRAM. */ 1984#define AdvReadByteLram(iop_base, addr, byte) \ 1985do { \ 1986 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \ 1987 (byte) = ADV_MEM_READB((iop_base) + IOPB_RAM_DATA); \ 1988} while (0) 1989 1990/* Write byte to LRAM. */ 1991#define AdvWriteByteLram(iop_base, addr, byte) \ 1992 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ 1993 ADV_MEM_WRITEB((iop_base) + IOPB_RAM_DATA, (byte))) 1994 1995/* Read word (2 bytes) from LRAM. */ 1996#define AdvReadWordLram(iop_base, addr, word) \ 1997do { \ 1998 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)); \ 1999 (word) = (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)); \ 2000} while (0) 2001 2002/* Write word (2 bytes) to LRAM. */ 2003#define AdvWriteWordLram(iop_base, addr, word) \ 2004 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ 2005 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word))) 2006 2007/* Write little-endian double word (4 bytes) to LRAM */ 2008/* Because of unspecified C language ordering don't use auto-increment. */ 2009#define AdvWriteDWordLramNoSwap(iop_base, addr, dword) \ 2010 ((ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr)), \ 2011 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \ 2012 cpu_to_le16((ushort) ((dword) & 0xFFFF)))), \ 2013 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_ADDR, (addr) + 2), \ 2014 ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, \ 2015 cpu_to_le16((ushort) ((dword >> 16) & 0xFFFF))))) 2016 2017/* Read word (2 bytes) from LRAM assuming that the address is already set. */ 2018#define AdvReadWordAutoIncLram(iop_base) \ 2019 (ADV_MEM_READW((iop_base) + IOPW_RAM_DATA)) 2020 2021/* Write word (2 bytes) to LRAM assuming that the address is already set. */ 2022#define AdvWriteWordAutoIncLram(iop_base, word) \ 2023 (ADV_MEM_WRITEW((iop_base) + IOPW_RAM_DATA, (word))) 2024 2025/* 2026 * Define macro to check for Condor signature. 2027 * 2028 * Evaluate to ADV_TRUE if a Condor chip is found the specified port 2029 * address 'iop_base'. Otherwise evalue to ADV_FALSE. 2030 */ 2031#define AdvFindSignature(iop_base) \ 2032 (((AdvReadByteRegister((iop_base), IOPB_CHIP_ID_1) == \ 2033 ADV_CHIP_ID_BYTE) && \ 2034 (AdvReadWordRegister((iop_base), IOPW_CHIP_ID_0) == \ 2035 ADV_CHIP_ID_WORD)) ? ADV_TRUE : ADV_FALSE) 2036 2037/* 2038 * Define macro to Return the version number of the chip at 'iop_base'. 2039 * 2040 * The second parameter 'bus_type' is currently unused. 2041 */ 2042#define AdvGetChipVersion(iop_base, bus_type) \ 2043 AdvReadByteRegister((iop_base), IOPB_CHIP_TYPE_REV) 2044 2045/* 2046 * Abort an SRB in the chip's RISC Memory. The 'srb_ptr' argument must 2047 * match the ASC_SCSI_REQ_Q 'srb_ptr' field. 2048 * 2049 * If the request has not yet been sent to the device it will simply be 2050 * aborted from RISC memory. If the request is disconnected it will be 2051 * aborted on reselection by sending an Abort Message to the target ID. 2052 * 2053 * Return value: 2054 * ADV_TRUE(1) - Queue was successfully aborted. 2055 * ADV_FALSE(0) - Queue was not found on the active queue list. 2056 */ 2057#define AdvAbortQueue(asc_dvc, scsiq) \ 2058 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_ABORT, \ 2059 (ADV_DCNT) (scsiq)) 2060 2061/* 2062 * Send a Bus Device Reset Message to the specified target ID. 2063 * 2064 * All outstanding commands will be purged if sending the 2065 * Bus Device Reset Message is successful. 2066 * 2067 * Return Value: 2068 * ADV_TRUE(1) - All requests on the target are purged. 2069 * ADV_FALSE(0) - Couldn't issue Bus Device Reset Message; Requests 2070 * are not purged. 2071 */ 2072#define AdvResetDevice(asc_dvc, target_id) \ 2073 AdvSendIdleCmd((asc_dvc), (ushort) IDLE_CMD_DEVICE_RESET, \ 2074 (ADV_DCNT) (target_id)) 2075 2076/* 2077 * SCSI Wide Type definition. 2078 */ 2079#define ADV_SCSI_BIT_ID_TYPE ushort 2080 2081/* 2082 * AdvInitScsiTarget() 'cntl_flag' options. 2083 */ 2084#define ADV_SCAN_LUN 0x01 2085#define ADV_CAPINFO_NOLUN 0x02 2086 2087/* 2088 * Convert target id to target id bit mask. 2089 */ 2090#define ADV_TID_TO_TIDMASK(tid) (0x01 << ((tid) & ADV_MAX_TID)) 2091 2092/* 2093 * ASC_SCSI_REQ_Q 'done_status' and 'host_status' return values. 2094 */ 2095 2096#define QD_NO_STATUS 0x00 /* Request not completed yet. */ 2097#define QD_NO_ERROR 0x01 2098#define QD_ABORTED_BY_HOST 0x02 2099#define QD_WITH_ERROR 0x04 2100 2101#define QHSTA_NO_ERROR 0x00 2102#define QHSTA_M_SEL_TIMEOUT 0x11 2103#define QHSTA_M_DATA_OVER_RUN 0x12 2104#define QHSTA_M_UNEXPECTED_BUS_FREE 0x13 2105#define QHSTA_M_QUEUE_ABORTED 0x15 2106#define QHSTA_M_SXFR_SDMA_ERR 0x16 /* SXFR_STATUS SCSI DMA Error */ 2107#define QHSTA_M_SXFR_SXFR_PERR 0x17 /* SXFR_STATUS SCSI Bus Parity Error */ 2108#define QHSTA_M_RDMA_PERR 0x18 /* RISC PCI DMA parity error */ 2109#define QHSTA_M_SXFR_OFF_UFLW 0x19 /* SXFR_STATUS Offset Underflow */ 2110#define QHSTA_M_SXFR_OFF_OFLW 0x20 /* SXFR_STATUS Offset Overflow */ 2111#define QHSTA_M_SXFR_WD_TMO 0x21 /* SXFR_STATUS Watchdog Timeout */ 2112#define QHSTA_M_SXFR_DESELECTED 0x22 /* SXFR_STATUS Deselected */ 2113/* Note: QHSTA_M_SXFR_XFR_OFLW is identical to QHSTA_M_DATA_OVER_RUN. */ 2114#define QHSTA_M_SXFR_XFR_OFLW 0x12 /* SXFR_STATUS Transfer Overflow */ 2115#define QHSTA_M_SXFR_XFR_PH_ERR 0x24 /* SXFR_STATUS Transfer Phase Error */ 2116#define QHSTA_M_SXFR_UNKNOWN_ERROR 0x25 /* SXFR_STATUS Unknown Error */ 2117#define QHSTA_M_SCSI_BUS_RESET 0x30 /* Request aborted from SBR */ 2118#define QHSTA_M_SCSI_BUS_RESET_UNSOL 0x31 /* Request aborted from unsol. SBR */ 2119#define QHSTA_M_BUS_DEVICE_RESET 0x32 /* Request aborted from BDR */ 2120#define QHSTA_M_DIRECTION_ERR 0x35 /* Data Phase mismatch */ 2121#define QHSTA_M_DIRECTION_ERR_HUNG 0x36 /* Data Phase mismatch and bus hang */ 2122#define QHSTA_M_WTM_TIMEOUT 0x41 2123#define QHSTA_M_BAD_CMPL_STATUS_IN 0x42 2124#define QHSTA_M_NO_AUTO_REQ_SENSE 0x43 2125#define QHSTA_M_AUTO_REQ_SENSE_FAIL 0x44 2126#define QHSTA_M_INVALID_DEVICE 0x45 /* Bad target ID */ 2127#define QHSTA_M_FROZEN_TIDQ 0x46 /* TID Queue frozen. */ 2128#define QHSTA_M_SGBACKUP_ERROR 0x47 /* Scatter-Gather backup error */ 2129 2130/* Return the address that is aligned at the next doubleword >= to 'addr'. */ 2131#define ADV_8BALIGN(addr) (((ulong) (addr) + 0x7) & ~0x7) 2132#define ADV_16BALIGN(addr) (((ulong) (addr) + 0xF) & ~0xF) 2133#define ADV_32BALIGN(addr) (((ulong) (addr) + 0x1F) & ~0x1F) 2134 2135/* 2136 * Total contiguous memory needed for driver SG blocks. 2137 * 2138 * ADV_MAX_SG_LIST must be defined by a driver. It is the maximum 2139 * number of scatter-gather elements the driver supports in a 2140 * single request. 2141 */ 2142 2143#define ADV_SG_LIST_MAX_BYTE_SIZE \ 2144 (sizeof(ADV_SG_BLOCK) * \ 2145 ((ADV_MAX_SG_LIST + (NO_OF_SG_PER_BLOCK - 1))/NO_OF_SG_PER_BLOCK)) 2146 2147/* struct asc_board flags */ 2148#define ASC_IS_WIDE_BOARD 0x04 /* AdvanSys Wide Board */ 2149 2150#define ASC_NARROW_BOARD(boardp) (((boardp)->flags & ASC_IS_WIDE_BOARD) == 0) 2151 2152#define NO_ISA_DMA 0xff /* No ISA DMA Channel Used */ 2153 2154#define ASC_INFO_SIZE 128 /* advansys_info() line size */ 2155 2156#ifdef CONFIG_PROC_FS 2157/* /proc/scsi/advansys/[0...] related definitions */ 2158#define ASC_PRTBUF_SIZE 2048 2159#define ASC_PRTLINE_SIZE 160 2160 2161#define ASC_PRT_NEXT() \ 2162 if (cp) { \ 2163 totlen += len; \ 2164 leftlen -= len; \ 2165 if (leftlen == 0) { \ 2166 return totlen; \ 2167 } \ 2168 cp += len; \ 2169 } 2170#endif /* CONFIG_PROC_FS */ 2171 2172/* Asc Library return codes */ 2173#define ASC_TRUE 1 2174#define ASC_FALSE 0 2175#define ASC_NOERROR 1 2176#define ASC_BUSY 0 2177#define ASC_ERROR (-1) 2178 2179/* struct scsi_cmnd function return codes */ 2180#define STATUS_BYTE(byte) (byte) 2181#define MSG_BYTE(byte) ((byte) << 8) 2182#define HOST_BYTE(byte) ((byte) << 16) 2183#define DRIVER_BYTE(byte) ((byte) << 24) 2184 2185#define ASC_STATS(shost, counter) ASC_STATS_ADD(shost, counter, 1) 2186#ifndef ADVANSYS_STATS 2187#define ASC_STATS_ADD(shost, counter, count) 2188#else /* ADVANSYS_STATS */ 2189#define ASC_STATS_ADD(shost, counter, count) \ 2190 (((struct asc_board *) shost_priv(shost))->asc_stats.counter += (count)) 2191#endif /* ADVANSYS_STATS */ 2192 2193/* If the result wraps when calculating tenths, return 0. */ 2194#define ASC_TENTHS(num, den) \ 2195 (((10 * ((num)/(den))) > (((num) * 10)/(den))) ? \ 2196 0 : ((((num) * 10)/(den)) - (10 * ((num)/(den))))) 2197 2198/* 2199 * Display a message to the console. 2200 */ 2201#define ASC_PRINT(s) \ 2202 { \ 2203 printk("advansys: "); \ 2204 printk(s); \ 2205 } 2206 2207#define ASC_PRINT1(s, a1) \ 2208 { \ 2209 printk("advansys: "); \ 2210 printk((s), (a1)); \ 2211 } 2212 2213#define ASC_PRINT2(s, a1, a2) \ 2214 { \ 2215 printk("advansys: "); \ 2216 printk((s), (a1), (a2)); \ 2217 } 2218 2219#define ASC_PRINT3(s, a1, a2, a3) \ 2220 { \ 2221 printk("advansys: "); \ 2222 printk((s), (a1), (a2), (a3)); \ 2223 } 2224 2225#define ASC_PRINT4(s, a1, a2, a3, a4) \ 2226 { \ 2227 printk("advansys: "); \ 2228 printk((s), (a1), (a2), (a3), (a4)); \ 2229 } 2230 2231#ifndef ADVANSYS_DEBUG 2232 2233#define ASC_DBG(lvl, s...) 2234#define ASC_DBG_PRT_SCSI_HOST(lvl, s) 2235#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) 2236#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) 2237#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) 2238#define ADV_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) 2239#define ASC_DBG_PRT_HEX(lvl, name, start, length) 2240#define ASC_DBG_PRT_CDB(lvl, cdb, len) 2241#define ASC_DBG_PRT_SENSE(lvl, sense, len) 2242#define ASC_DBG_PRT_INQUIRY(lvl, inq, len) 2243 2244#else /* ADVANSYS_DEBUG */ 2245 2246/* 2247 * Debugging Message Levels: 2248 * 0: Errors Only 2249 * 1: High-Level Tracing 2250 * 2-N: Verbose Tracing 2251 */ 2252 2253#define ASC_DBG(lvl, format, arg...) { \ 2254 if (asc_dbglvl >= (lvl)) \ 2255 printk(KERN_DEBUG "%s: %s: " format, DRV_NAME, \ 2256 __func__ , ## arg); \ 2257} 2258 2259#define ASC_DBG_PRT_SCSI_HOST(lvl, s) \ 2260 { \ 2261 if (asc_dbglvl >= (lvl)) { \ 2262 asc_prt_scsi_host(s); \ 2263 } \ 2264 } 2265 2266#define ASC_DBG_PRT_ASC_SCSI_Q(lvl, scsiqp) \ 2267 { \ 2268 if (asc_dbglvl >= (lvl)) { \ 2269 asc_prt_asc_scsi_q(scsiqp); \ 2270 } \ 2271 } 2272 2273#define ASC_DBG_PRT_ASC_QDONE_INFO(lvl, qdone) \ 2274 { \ 2275 if (asc_dbglvl >= (lvl)) { \ 2276 asc_prt_asc_qdone_info(qdone); \ 2277 } \ 2278 } 2279 2280#define ASC_DBG_PRT_ADV_SCSI_REQ_Q(lvl, scsiqp) \ 2281 { \ 2282 if (asc_dbglvl >= (lvl)) { \ 2283 asc_prt_adv_scsi_req_q(scsiqp); \ 2284 } \ 2285 } 2286 2287#define ASC_DBG_PRT_HEX(lvl, name, start, length) \ 2288 { \ 2289 if (asc_dbglvl >= (lvl)) { \ 2290 asc_prt_hex((name), (start), (length)); \ 2291 } \ 2292 } 2293 2294#define ASC_DBG_PRT_CDB(lvl, cdb, len) \ 2295 ASC_DBG_PRT_HEX((lvl), "CDB", (uchar *) (cdb), (len)); 2296 2297#define ASC_DBG_PRT_SENSE(lvl, sense, len) \ 2298 ASC_DBG_PRT_HEX((lvl), "SENSE", (uchar *) (sense), (len)); 2299 2300#define ASC_DBG_PRT_INQUIRY(lvl, inq, len) \ 2301 ASC_DBG_PRT_HEX((lvl), "INQUIRY", (uchar *) (inq), (len)); 2302#endif /* ADVANSYS_DEBUG */ 2303 2304#ifdef ADVANSYS_STATS 2305 2306/* Per board statistics structure */ 2307struct asc_stats { 2308 /* Driver Entrypoint Statistics */ 2309 ADV_DCNT queuecommand; /* # calls to advansys_queuecommand() */ 2310 ADV_DCNT reset; /* # calls to advansys_eh_bus_reset() */ 2311 ADV_DCNT biosparam; /* # calls to advansys_biosparam() */ 2312 ADV_DCNT interrupt; /* # advansys_interrupt() calls */ 2313 ADV_DCNT callback; /* # calls to asc/adv_isr_callback() */ 2314 ADV_DCNT done; /* # calls to request's scsi_done function */ 2315 ADV_DCNT build_error; /* # asc/adv_build_req() ASC_ERROR returns. */ 2316 ADV_DCNT adv_build_noreq; /* # adv_build_req() adv_req_t alloc. fail. */ 2317 ADV_DCNT adv_build_nosg; /* # adv_build_req() adv_sgblk_t alloc. fail. */ 2318 /* AscExeScsiQueue()/AdvExeScsiQueue() Statistics */ 2319 ADV_DCNT exe_noerror; /* # ASC_NOERROR returns. */ 2320 ADV_DCNT exe_busy; /* # ASC_BUSY returns. */ 2321 ADV_DCNT exe_error; /* # ASC_ERROR returns. */ 2322 ADV_DCNT exe_unknown; /* # unknown returns. */ 2323 /* Data Transfer Statistics */ 2324 ADV_DCNT xfer_cnt; /* # I/O requests received */ 2325 ADV_DCNT xfer_elem; /* # scatter-gather elements */ 2326 ADV_DCNT xfer_sect; /* # 512-byte blocks */ 2327}; 2328#endif /* ADVANSYS_STATS */ 2329 2330/* 2331 * Structure allocated for each board. 2332 * 2333 * This structure is allocated by scsi_host_alloc() at the end 2334 * of the 'Scsi_Host' structure starting at the 'hostdata' 2335 * field. It is guaranteed to be allocated from DMA-able memory. 2336 */ 2337struct asc_board { 2338 struct device *dev; 2339 uint flags; /* Board flags */ 2340 unsigned int irq; 2341 union { 2342 ASC_DVC_VAR asc_dvc_var; /* Narrow board */ 2343 ADV_DVC_VAR adv_dvc_var; /* Wide board */ 2344 } dvc_var; 2345 union { 2346 ASC_DVC_CFG asc_dvc_cfg; /* Narrow board */ 2347 ADV_DVC_CFG adv_dvc_cfg; /* Wide board */ 2348 } dvc_cfg; 2349 ushort asc_n_io_port; /* Number I/O ports. */ 2350 ADV_SCSI_BIT_ID_TYPE init_tidmask; /* Target init./valid mask */ 2351 ushort reqcnt[ADV_MAX_TID + 1]; /* Starvation request count */ 2352 ADV_SCSI_BIT_ID_TYPE queue_full; /* Queue full mask */ 2353 ushort queue_full_cnt[ADV_MAX_TID + 1]; /* Queue full count */ 2354 union { 2355 ASCEEP_CONFIG asc_eep; /* Narrow EEPROM config. */ 2356 ADVEEP_3550_CONFIG adv_3550_eep; /* 3550 EEPROM config. */ 2357 ADVEEP_38C0800_CONFIG adv_38C0800_eep; /* 38C0800 EEPROM config. */ 2358 ADVEEP_38C1600_CONFIG adv_38C1600_eep; /* 38C1600 EEPROM config. */ 2359 } eep_config; 2360 ulong last_reset; /* Saved last reset time */ 2361 /* /proc/scsi/advansys/[0...] */ 2362 char *prtbuf; /* /proc print buffer */ 2363#ifdef ADVANSYS_STATS 2364 struct asc_stats asc_stats; /* Board statistics */ 2365#endif /* ADVANSYS_STATS */ 2366 /* 2367 * The following fields are used only for Narrow Boards. 2368 */ 2369 uchar sdtr_data[ASC_MAX_TID + 1]; /* SDTR information */ 2370 /* 2371 * The following fields are used only for Wide Boards. 2372 */ 2373 void __iomem *ioremap_addr; /* I/O Memory remap address. */ 2374 ushort ioport; /* I/O Port address. */ 2375 adv_req_t *adv_reqp; /* Request structures. */ 2376 adv_sgblk_t *adv_sgblkp; /* Scatter-gather structures. */ 2377 ushort bios_signature; /* BIOS Signature. */ 2378 ushort bios_version; /* BIOS Version. */ 2379 ushort bios_codeseg; /* BIOS Code Segment. */ 2380 ushort bios_codelen; /* BIOS Code Segment Length. */ 2381}; 2382 2383#define asc_dvc_to_board(asc_dvc) container_of(asc_dvc, struct asc_board, \ 2384 dvc_var.asc_dvc_var) 2385#define adv_dvc_to_board(adv_dvc) container_of(adv_dvc, struct asc_board, \ 2386 dvc_var.adv_dvc_var) 2387#define adv_dvc_to_pdev(adv_dvc) to_pci_dev(adv_dvc_to_board(adv_dvc)->dev) 2388 2389#ifdef ADVANSYS_DEBUG 2390static int asc_dbglvl = 3; 2391 2392/* 2393 * asc_prt_asc_dvc_var() 2394 */ 2395static void asc_prt_asc_dvc_var(ASC_DVC_VAR *h) 2396{ 2397 printk("ASC_DVC_VAR at addr 0x%lx\n", (ulong)h); 2398 2399 printk(" iop_base 0x%x, err_code 0x%x, dvc_cntl 0x%x, bug_fix_cntl " 2400 "%d,\n", h->iop_base, h->err_code, h->dvc_cntl, h->bug_fix_cntl); 2401 2402 printk(" bus_type %d, init_sdtr 0x%x,\n", h->bus_type, 2403 (unsigned)h->init_sdtr); 2404 2405 printk(" sdtr_done 0x%x, use_tagged_qng 0x%x, unit_not_ready 0x%x, " 2406 "chip_no 0x%x,\n", (unsigned)h->sdtr_done, 2407 (unsigned)h->use_tagged_qng, (unsigned)h->unit_not_ready, 2408 (unsigned)h->chip_no); 2409 2410 printk(" queue_full_or_busy 0x%x, start_motor 0x%x, scsi_reset_wait " 2411 "%u,\n", (unsigned)h->queue_full_or_busy, 2412 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait); 2413 2414 printk(" is_in_int %u, max_total_qng %u, cur_total_qng %u, " 2415 "in_critical_cnt %u,\n", (unsigned)h->is_in_int, 2416 (unsigned)h->max_total_qng, (unsigned)h->cur_total_qng, 2417 (unsigned)h->in_critical_cnt); 2418 2419 printk(" last_q_shortage %u, init_state 0x%x, no_scam 0x%x, " 2420 "pci_fix_asyn_xfer 0x%x,\n", (unsigned)h->last_q_shortage, 2421 (unsigned)h->init_state, (unsigned)h->no_scam, 2422 (unsigned)h->pci_fix_asyn_xfer); 2423 2424 printk(" cfg 0x%lx\n", (ulong)h->cfg); 2425} 2426 2427/* 2428 * asc_prt_asc_dvc_cfg() 2429 */ 2430static void asc_prt_asc_dvc_cfg(ASC_DVC_CFG *h) 2431{ 2432 printk("ASC_DVC_CFG at addr 0x%lx\n", (ulong)h); 2433 2434 printk(" can_tagged_qng 0x%x, cmd_qng_enabled 0x%x,\n", 2435 h->can_tagged_qng, h->cmd_qng_enabled); 2436 printk(" disc_enable 0x%x, sdtr_enable 0x%x,\n", 2437 h->disc_enable, h->sdtr_enable); 2438 2439 printk(" chip_scsi_id %d, isa_dma_speed %d, isa_dma_channel %d, " 2440 "chip_version %d,\n", h->chip_scsi_id, h->isa_dma_speed, 2441 h->isa_dma_channel, h->chip_version); 2442 2443 printk(" mcode_date 0x%x, mcode_version %d\n", 2444 h->mcode_date, h->mcode_version); 2445} 2446 2447/* 2448 * asc_prt_adv_dvc_var() 2449 * 2450 * Display an ADV_DVC_VAR structure. 2451 */ 2452static void asc_prt_adv_dvc_var(ADV_DVC_VAR *h) 2453{ 2454 printk(" ADV_DVC_VAR at addr 0x%lx\n", (ulong)h); 2455 2456 printk(" iop_base 0x%lx, err_code 0x%x, ultra_able 0x%x\n", 2457 (ulong)h->iop_base, h->err_code, (unsigned)h->ultra_able); 2458 2459 printk(" sdtr_able 0x%x, wdtr_able 0x%x\n", 2460 (unsigned)h->sdtr_able, (unsigned)h->wdtr_able); 2461 2462 printk(" start_motor 0x%x, scsi_reset_wait 0x%x\n", 2463 (unsigned)h->start_motor, (unsigned)h->scsi_reset_wait); 2464 2465 printk(" max_host_qng %u, max_dvc_qng %u, carr_freelist 0x%lxn\n", 2466 (unsigned)h->max_host_qng, (unsigned)h->max_dvc_qng, 2467 (ulong)h->carr_freelist); 2468 2469 printk(" icq_sp 0x%lx, irq_sp 0x%lx\n", 2470 (ulong)h->icq_sp, (ulong)h->irq_sp); 2471 2472 printk(" no_scam 0x%x, tagqng_able 0x%x\n", 2473 (unsigned)h->no_scam, (unsigned)h->tagqng_able); 2474 2475 printk(" chip_scsi_id 0x%x, cfg 0x%lx\n", 2476 (unsigned)h->chip_scsi_id, (ulong)h->cfg); 2477} 2478 2479/* 2480 * asc_prt_adv_dvc_cfg() 2481 * 2482 * Display an ADV_DVC_CFG structure. 2483 */ 2484static void asc_prt_adv_dvc_cfg(ADV_DVC_CFG *h) 2485{ 2486 printk(" ADV_DVC_CFG at addr 0x%lx\n", (ulong)h); 2487 2488 printk(" disc_enable 0x%x, termination 0x%x\n", 2489 h->disc_enable, h->termination); 2490 2491 printk(" chip_version 0x%x, mcode_date 0x%x\n", 2492 h->chip_version, h->mcode_date); 2493 2494 printk(" mcode_version 0x%x, control_flag 0x%x\n", 2495 h->mcode_version, h->control_flag); 2496} 2497 2498/* 2499 * asc_prt_scsi_host() 2500 */ 2501static void asc_prt_scsi_host(struct Scsi_Host *s) 2502{ 2503 struct asc_board *boardp = shost_priv(s); 2504 2505 printk("Scsi_Host at addr 0x%p, device %s\n", s, dev_name(boardp->dev)); 2506 printk(" host_busy %u, host_no %d, last_reset %d,\n", 2507 s->host_busy, s->host_no, (unsigned)s->last_reset); 2508 2509 printk(" base 0x%lx, io_port 0x%lx, irq %d,\n", 2510 (ulong)s->base, (ulong)s->io_port, boardp->irq); 2511 2512 printk(" dma_channel %d, this_id %d, can_queue %d,\n", 2513 s->dma_channel, s->this_id, s->can_queue); 2514 2515 printk(" cmd_per_lun %d, sg_tablesize %d, unchecked_isa_dma %d\n", 2516 s->cmd_per_lun, s->sg_tablesize, s->unchecked_isa_dma); 2517 2518 if (ASC_NARROW_BOARD(boardp)) { 2519 asc_prt_asc_dvc_var(&boardp->dvc_var.asc_dvc_var); 2520 asc_prt_asc_dvc_cfg(&boardp->dvc_cfg.asc_dvc_cfg); 2521 } else { 2522 asc_prt_adv_dvc_var(&boardp->dvc_var.adv_dvc_var); 2523 asc_prt_adv_dvc_cfg(&boardp->dvc_cfg.adv_dvc_cfg); 2524 } 2525} 2526 2527/* 2528 * asc_prt_hex() 2529 * 2530 * Print hexadecimal output in 4 byte groupings 32 bytes 2531 * or 8 double-words per line. 2532 */ 2533static void asc_prt_hex(char *f, uchar *s, int l) 2534{ 2535 int i; 2536 int j; 2537 int k; 2538 int m; 2539 2540 printk("%s: (%d bytes)\n", f, l); 2541 2542 for (i = 0; i < l; i += 32) { 2543 2544 /* Display a maximum of 8 double-words per line. */ 2545 if ((k = (l - i) / 4) >= 8) { 2546 k = 8; 2547 m = 0; 2548 } else { 2549 m = (l - i) % 4; 2550 } 2551 2552 for (j = 0; j < k; j++) { 2553 printk(" %2.2X%2.2X%2.2X%2.2X", 2554 (unsigned)s[i + (j * 4)], 2555 (unsigned)s[i + (j * 4) + 1], 2556 (unsigned)s[i + (j * 4) + 2], 2557 (unsigned)s[i + (j * 4) + 3]); 2558 } 2559 2560 switch (m) { 2561 case 0: 2562 default: 2563 break; 2564 case 1: 2565 printk(" %2.2X", (unsigned)s[i + (j * 4)]); 2566 break; 2567 case 2: 2568 printk(" %2.2X%2.2X", 2569 (unsigned)s[i + (j * 4)], 2570 (unsigned)s[i + (j * 4) + 1]); 2571 break; 2572 case 3: 2573 printk(" %2.2X%2.2X%2.2X", 2574 (unsigned)s[i + (j * 4) + 1], 2575 (unsigned)s[i + (j * 4) + 2], 2576 (unsigned)s[i + (j * 4) + 3]); 2577 break; 2578 } 2579 2580 printk("\n"); 2581 } 2582} 2583 2584/* 2585 * asc_prt_asc_scsi_q() 2586 */ 2587static void asc_prt_asc_scsi_q(ASC_SCSI_Q *q) 2588{ 2589 ASC_SG_HEAD *sgp; 2590 int i; 2591 2592 printk("ASC_SCSI_Q at addr 0x%lx\n", (ulong)q); 2593 2594 printk 2595 (" target_ix 0x%x, target_lun %u, srb_ptr 0x%lx, tag_code 0x%x,\n", 2596 q->q2.target_ix, q->q1.target_lun, (ulong)q->q2.srb_ptr, 2597 q->q2.tag_code); 2598 2599 printk 2600 (" data_addr 0x%lx, data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n", 2601 (ulong)le32_to_cpu(q->q1.data_addr), 2602 (ulong)le32_to_cpu(q->q1.data_cnt), 2603 (ulong)le32_to_cpu(q->q1.sense_addr), q->q1.sense_len); 2604 2605 printk(" cdbptr 0x%lx, cdb_len %u, sg_head 0x%lx, sg_queue_cnt %u\n", 2606 (ulong)q->cdbptr, q->q2.cdb_len, 2607 (ulong)q->sg_head, q->q1.sg_queue_cnt); 2608 2609 if (q->sg_head) { 2610 sgp = q->sg_head; 2611 printk("ASC_SG_HEAD at addr 0x%lx\n", (ulong)sgp); 2612 printk(" entry_cnt %u, queue_cnt %u\n", sgp->entry_cnt, 2613 sgp->queue_cnt); 2614 for (i = 0; i < sgp->entry_cnt; i++) { 2615 printk(" [%u]: addr 0x%lx, bytes %lu\n", 2616 i, (ulong)le32_to_cpu(sgp->sg_list[i].addr), 2617 (ulong)le32_to_cpu(sgp->sg_list[i].bytes)); 2618 } 2619 2620 } 2621} 2622 2623/* 2624 * asc_prt_asc_qdone_info() 2625 */ 2626static void asc_prt_asc_qdone_info(ASC_QDONE_INFO *q) 2627{ 2628 printk("ASC_QDONE_INFO at addr 0x%lx\n", (ulong)q); 2629 printk(" srb_ptr 0x%lx, target_ix %u, cdb_len %u, tag_code %u,\n", 2630 (ulong)q->d2.srb_ptr, q->d2.target_ix, q->d2.cdb_len, 2631 q->d2.tag_code); 2632 printk 2633 (" done_stat 0x%x, host_stat 0x%x, scsi_stat 0x%x, scsi_msg 0x%x\n", 2634 q->d3.done_stat, q->d3.host_stat, q->d3.scsi_stat, q->d3.scsi_msg); 2635} 2636 2637/* 2638 * asc_prt_adv_sgblock() 2639 * 2640 * Display an ADV_SG_BLOCK structure. 2641 */ 2642static void asc_prt_adv_sgblock(int sgblockno, ADV_SG_BLOCK *b) 2643{ 2644 int i; 2645 2646 printk(" ASC_SG_BLOCK at addr 0x%lx (sgblockno %d)\n", 2647 (ulong)b, sgblockno); 2648 printk(" sg_cnt %u, sg_ptr 0x%lx\n", 2649 b->sg_cnt, (ulong)le32_to_cpu(b->sg_ptr)); 2650 BUG_ON(b->sg_cnt > NO_OF_SG_PER_BLOCK); 2651 if (b->sg_ptr != 0) 2652 BUG_ON(b->sg_cnt != NO_OF_SG_PER_BLOCK); 2653 for (i = 0; i < b->sg_cnt; i++) { 2654 printk(" [%u]: sg_addr 0x%lx, sg_count 0x%lx\n", 2655 i, (ulong)b->sg_list[i].sg_addr, 2656 (ulong)b->sg_list[i].sg_count); 2657 } 2658} 2659 2660/* 2661 * asc_prt_adv_scsi_req_q() 2662 * 2663 * Display an ADV_SCSI_REQ_Q structure. 2664 */ 2665static void asc_prt_adv_scsi_req_q(ADV_SCSI_REQ_Q *q) 2666{ 2667 int sg_blk_cnt; 2668 struct asc_sg_block *sg_ptr; 2669 2670 printk("ADV_SCSI_REQ_Q at addr 0x%lx\n", (ulong)q); 2671 2672 printk(" target_id %u, target_lun %u, srb_ptr 0x%lx, a_flag 0x%x\n", 2673 q->target_id, q->target_lun, (ulong)q->srb_ptr, q->a_flag); 2674 2675 printk(" cntl 0x%x, data_addr 0x%lx, vdata_addr 0x%lx\n", 2676 q->cntl, (ulong)le32_to_cpu(q->data_addr), (ulong)q->vdata_addr); 2677 2678 printk(" data_cnt %lu, sense_addr 0x%lx, sense_len %u,\n", 2679 (ulong)le32_to_cpu(q->data_cnt), 2680 (ulong)le32_to_cpu(q->sense_addr), q->sense_len); 2681 2682 printk 2683 (" cdb_len %u, done_status 0x%x, host_status 0x%x, scsi_status 0x%x\n", 2684 q->cdb_len, q->done_status, q->host_status, q->scsi_status); 2685 2686 printk(" sg_working_ix 0x%x, target_cmd %u\n", 2687 q->sg_working_ix, q->target_cmd); 2688 2689 printk(" scsiq_rptr 0x%lx, sg_real_addr 0x%lx, sg_list_ptr 0x%lx\n", 2690 (ulong)le32_to_cpu(q->scsiq_rptr), 2691 (ulong)le32_to_cpu(q->sg_real_addr), (ulong)q->sg_list_ptr); 2692 2693 /* Display the request's ADV_SG_BLOCK structures. */ 2694 if (q->sg_list_ptr != NULL) { 2695 sg_blk_cnt = 0; 2696 while (1) { 2697 sg_ptr = 2698 &(((ADV_SG_BLOCK *)(q->sg_list_ptr))[sg_blk_cnt]); 2699 asc_prt_adv_sgblock(sg_blk_cnt, sg_ptr); 2700 if (sg_ptr->sg_ptr == 0) { 2701 break; 2702 } 2703 sg_blk_cnt++; 2704 } 2705 } 2706} 2707#endif /* ADVANSYS_DEBUG */ 2708 2709/* 2710 * The advansys chip/microcode contains a 32-bit identifier for each command 2711 * known as the 'srb'. I don't know what it stands for. The driver used 2712 * to encode the scsi_cmnd pointer by calling virt_to_bus and retrieve it 2713 * with bus_to_virt. Now the driver keeps a per-host map of integers to 2714 * pointers. It auto-expands when full, unless it can't allocate memory. 2715 * Note that an srb of 0 is treated specially by the chip/firmware, hence 2716 * the return of i+1 in this routine, and the corresponding subtraction in 2717 * the inverse routine. 2718 */ 2719#define BAD_SRB 0 2720static u32 advansys_ptr_to_srb(struct asc_dvc_var *asc_dvc, void *ptr) 2721{ 2722 int i; 2723 void **new_ptr; 2724 2725 for (i = 0; i < asc_dvc->ptr_map_count; i++) { 2726 if (!asc_dvc->ptr_map[i]) 2727 goto out; 2728 } 2729 2730 if (asc_dvc->ptr_map_count == 0) 2731 asc_dvc->ptr_map_count = 1; 2732 else 2733 asc_dvc->ptr_map_count *= 2; 2734 2735 new_ptr = krealloc(asc_dvc->ptr_map, 2736 asc_dvc->ptr_map_count * sizeof(void *), GFP_ATOMIC); 2737 if (!new_ptr) 2738 return BAD_SRB; 2739 asc_dvc->ptr_map = new_ptr; 2740 out: 2741 ASC_DBG(3, "Putting ptr %p into array offset %d\n", ptr, i); 2742 asc_dvc->ptr_map[i] = ptr; 2743 return i + 1; 2744} 2745 2746static void * advansys_srb_to_ptr(struct asc_dvc_var *asc_dvc, u32 srb) 2747{ 2748 void *ptr; 2749 2750 srb--; 2751 if (srb >= asc_dvc->ptr_map_count) { 2752 printk("advansys: bad SRB %u, max %u\n", srb, 2753 asc_dvc->ptr_map_count); 2754 return NULL; 2755 } 2756 ptr = asc_dvc->ptr_map[srb]; 2757 asc_dvc->ptr_map[srb] = NULL; 2758 ASC_DBG(3, "Returning ptr %p from array offset %d\n", ptr, srb); 2759 return ptr; 2760} 2761 2762/* 2763 * advansys_info() 2764 * 2765 * Return suitable for printing on the console with the argument 2766 * adapter's configuration information. 2767 * 2768 * Note: The information line should not exceed ASC_INFO_SIZE bytes, 2769 * otherwise the static 'info' array will be overrun. 2770 */ 2771static const char *advansys_info(struct Scsi_Host *shost) 2772{ 2773 static char info[ASC_INFO_SIZE]; 2774 struct asc_board *boardp = shost_priv(shost); 2775 ASC_DVC_VAR *asc_dvc_varp; 2776 ADV_DVC_VAR *adv_dvc_varp; 2777 char *busname; 2778 char *widename = NULL; 2779 2780 if (ASC_NARROW_BOARD(boardp)) { 2781 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; 2782 ASC_DBG(1, "begin\n"); 2783 if (asc_dvc_varp->bus_type & ASC_IS_ISA) { 2784 if ((asc_dvc_varp->bus_type & ASC_IS_ISAPNP) == 2785 ASC_IS_ISAPNP) { 2786 busname = "ISA PnP"; 2787 } else { 2788 busname = "ISA"; 2789 } 2790 sprintf(info, 2791 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X, DMA 0x%X", 2792 ASC_VERSION, busname, 2793 (ulong)shost->io_port, 2794 (ulong)shost->io_port + ASC_IOADR_GAP - 1, 2795 boardp->irq, shost->dma_channel); 2796 } else { 2797 if (asc_dvc_varp->bus_type & ASC_IS_VL) { 2798 busname = "VL"; 2799 } else if (asc_dvc_varp->bus_type & ASC_IS_EISA) { 2800 busname = "EISA"; 2801 } else if (asc_dvc_varp->bus_type & ASC_IS_PCI) { 2802 if ((asc_dvc_varp->bus_type & ASC_IS_PCI_ULTRA) 2803 == ASC_IS_PCI_ULTRA) { 2804 busname = "PCI Ultra"; 2805 } else { 2806 busname = "PCI"; 2807 } 2808 } else { 2809 busname = "?"; 2810 shost_printk(KERN_ERR, shost, "unknown bus " 2811 "type %d\n", asc_dvc_varp->bus_type); 2812 } 2813 sprintf(info, 2814 "AdvanSys SCSI %s: %s: IO 0x%lX-0x%lX, IRQ 0x%X", 2815 ASC_VERSION, busname, (ulong)shost->io_port, 2816 (ulong)shost->io_port + ASC_IOADR_GAP - 1, 2817 boardp->irq); 2818 } 2819 } else { 2820 /* 2821 * Wide Adapter Information 2822 * 2823 * Memory-mapped I/O is used instead of I/O space to access 2824 * the adapter, but display the I/O Port range. The Memory 2825 * I/O address is displayed through the driver /proc file. 2826 */ 2827 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; 2828 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 2829 widename = "Ultra-Wide"; 2830 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 2831 widename = "Ultra2-Wide"; 2832 } else { 2833 widename = "Ultra3-Wide"; 2834 } 2835 sprintf(info, 2836 "AdvanSys SCSI %s: PCI %s: PCIMEM 0x%lX-0x%lX, IRQ 0x%X", 2837 ASC_VERSION, widename, (ulong)adv_dvc_varp->iop_base, 2838 (ulong)adv_dvc_varp->iop_base + boardp->asc_n_io_port - 1, boardp->irq); 2839 } 2840 BUG_ON(strlen(info) >= ASC_INFO_SIZE); 2841 ASC_DBG(1, "end\n"); 2842 return info; 2843} 2844 2845#ifdef CONFIG_PROC_FS 2846/* 2847 * asc_prt_line() 2848 * 2849 * If 'cp' is NULL print to the console, otherwise print to a buffer. 2850 * 2851 * Return 0 if printing to the console, otherwise return the number of 2852 * bytes written to the buffer. 2853 * 2854 * Note: If any single line is greater than ASC_PRTLINE_SIZE bytes the stack 2855 * will be corrupted. 's[]' is defined to be ASC_PRTLINE_SIZE bytes. 2856 */ 2857static int asc_prt_line(char *buf, int buflen, char *fmt, ...) 2858{ 2859 va_list args; 2860 int ret; 2861 char s[ASC_PRTLINE_SIZE]; 2862 2863 va_start(args, fmt); 2864 ret = vsprintf(s, fmt, args); 2865 BUG_ON(ret >= ASC_PRTLINE_SIZE); 2866 if (buf == NULL) { 2867 (void)printk(s); 2868 ret = 0; 2869 } else { 2870 ret = min(buflen, ret); 2871 memcpy(buf, s, ret); 2872 } 2873 va_end(args); 2874 return ret; 2875} 2876 2877/* 2878 * asc_prt_board_devices() 2879 * 2880 * Print driver information for devices attached to the board. 2881 * 2882 * Note: no single line should be greater than ASC_PRTLINE_SIZE, 2883 * cf. asc_prt_line(). 2884 * 2885 * Return the number of characters copied into 'cp'. No more than 2886 * 'cplen' characters will be copied to 'cp'. 2887 */ 2888static int asc_prt_board_devices(struct Scsi_Host *shost, char *cp, int cplen) 2889{ 2890 struct asc_board *boardp = shost_priv(shost); 2891 int leftlen; 2892 int totlen; 2893 int len; 2894 int chip_scsi_id; 2895 int i; 2896 2897 leftlen = cplen; 2898 totlen = len = 0; 2899 2900 len = asc_prt_line(cp, leftlen, 2901 "\nDevice Information for AdvanSys SCSI Host %d:\n", 2902 shost->host_no); 2903 ASC_PRT_NEXT(); 2904 2905 if (ASC_NARROW_BOARD(boardp)) { 2906 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id; 2907 } else { 2908 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id; 2909 } 2910 2911 len = asc_prt_line(cp, leftlen, "Target IDs Detected:"); 2912 ASC_PRT_NEXT(); 2913 for (i = 0; i <= ADV_MAX_TID; i++) { 2914 if (boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) { 2915 len = asc_prt_line(cp, leftlen, " %X,", i); 2916 ASC_PRT_NEXT(); 2917 } 2918 } 2919 len = asc_prt_line(cp, leftlen, " (%X=Host Adapter)\n", chip_scsi_id); 2920 ASC_PRT_NEXT(); 2921 2922 return totlen; 2923} 2924 2925/* 2926 * Display Wide Board BIOS Information. 2927 */ 2928static int asc_prt_adv_bios(struct Scsi_Host *shost, char *cp, int cplen) 2929{ 2930 struct asc_board *boardp = shost_priv(shost); 2931 int leftlen; 2932 int totlen; 2933 int len; 2934 ushort major, minor, letter; 2935 2936 leftlen = cplen; 2937 totlen = len = 0; 2938 2939 len = asc_prt_line(cp, leftlen, "\nROM BIOS Version: "); 2940 ASC_PRT_NEXT(); 2941 2942 /* 2943 * If the BIOS saved a valid signature, then fill in 2944 * the BIOS code segment base address. 2945 */ 2946 if (boardp->bios_signature != 0x55AA) { 2947 len = asc_prt_line(cp, leftlen, "Disabled or Pre-3.1\n"); 2948 ASC_PRT_NEXT(); 2949 len = asc_prt_line(cp, leftlen, 2950 "BIOS either disabled or Pre-3.1. If it is pre-3.1, then a newer version\n"); 2951 ASC_PRT_NEXT(); 2952 len = asc_prt_line(cp, leftlen, 2953 "can be found at the ConnectCom FTP site: ftp://ftp.connectcom.net/pub\n"); 2954 ASC_PRT_NEXT(); 2955 } else { 2956 major = (boardp->bios_version >> 12) & 0xF; 2957 minor = (boardp->bios_version >> 8) & 0xF; 2958 letter = (boardp->bios_version & 0xFF); 2959 2960 len = asc_prt_line(cp, leftlen, "%d.%d%c\n", 2961 major, minor, 2962 letter >= 26 ? '?' : letter + 'A'); 2963 ASC_PRT_NEXT(); 2964 2965 /* 2966 * Current available ROM BIOS release is 3.1I for UW 2967 * and 3.2I for U2W. This code doesn't differentiate 2968 * UW and U2W boards. 2969 */ 2970 if (major < 3 || (major <= 3 && minor < 1) || 2971 (major <= 3 && minor <= 1 && letter < ('I' - 'A'))) { 2972 len = asc_prt_line(cp, leftlen, 2973 "Newer version of ROM BIOS is available at the ConnectCom FTP site:\n"); 2974 ASC_PRT_NEXT(); 2975 len = asc_prt_line(cp, leftlen, 2976 "ftp://ftp.connectcom.net/pub\n"); 2977 ASC_PRT_NEXT(); 2978 } 2979 } 2980 2981 return totlen; 2982} 2983 2984/* 2985 * Add serial number to information bar if signature AAh 2986 * is found in at bit 15-9 (7 bits) of word 1. 2987 * 2988 * Serial Number consists fo 12 alpha-numeric digits. 2989 * 2990 * 1 - Product type (A,B,C,D..) Word0: 15-13 (3 bits) 2991 * 2 - MFG Location (A,B,C,D..) Word0: 12-10 (3 bits) 2992 * 3-4 - Product ID (0-99) Word0: 9-0 (10 bits) 2993 * 5 - Product revision (A-J) Word0: " " 2994 * 2995 * Signature Word1: 15-9 (7 bits) 2996 * 6 - Year (0-9) Word1: 8-6 (3 bits) & Word2: 15 (1 bit) 2997 * 7-8 - Week of the year (1-52) Word1: 5-0 (6 bits) 2998 * 2999 * 9-12 - Serial Number (A001-Z999) Word2: 14-0 (15 bits) 3000 * 3001 * Note 1: Only production cards will have a serial number. 3002 * 3003 * Note 2: Signature is most significant 7 bits (0xFE). 3004 * 3005 * Returns ASC_TRUE if serial number found, otherwise returns ASC_FALSE. 3006 */ 3007static int asc_get_eeprom_string(ushort *serialnum, uchar *cp) 3008{ 3009 ushort w, num; 3010 3011 if ((serialnum[1] & 0xFE00) != ((ushort)0xAA << 8)) { 3012 return ASC_FALSE; 3013 } else { 3014 /* 3015 * First word - 6 digits. 3016 */ 3017 w = serialnum[0]; 3018 3019 /* Product type - 1st digit. */ 3020 if ((*cp = 'A' + ((w & 0xE000) >> 13)) == 'H') { 3021 /* Product type is P=Prototype */ 3022 *cp += 0x8; 3023 } 3024 cp++; 3025 3026 /* Manufacturing location - 2nd digit. */ 3027 *cp++ = 'A' + ((w & 0x1C00) >> 10); 3028 3029 /* Product ID - 3rd, 4th digits. */ 3030 num = w & 0x3FF; 3031 *cp++ = '0' + (num / 100); 3032 num %= 100; 3033 *cp++ = '0' + (num / 10); 3034 3035 /* Product revision - 5th digit. */ 3036 *cp++ = 'A' + (num % 10); 3037 3038 /* 3039 * Second word 3040 */ 3041 w = serialnum[1]; 3042 3043 /* 3044 * Year - 6th digit. 3045 * 3046 * If bit 15 of third word is set, then the 3047 * last digit of the year is greater than 7. 3048 */ 3049 if (serialnum[2] & 0x8000) { 3050 *cp++ = '8' + ((w & 0x1C0) >> 6); 3051 } else { 3052 *cp++ = '0' + ((w & 0x1C0) >> 6); 3053 } 3054 3055 /* Week of year - 7th, 8th digits. */ 3056 num = w & 0x003F; 3057 *cp++ = '0' + num / 10; 3058 num %= 10; 3059 *cp++ = '0' + num; 3060 3061 /* 3062 * Third word 3063 */ 3064 w = serialnum[2] & 0x7FFF; 3065 3066 /* Serial number - 9th digit. */ 3067 *cp++ = 'A' + (w / 1000); 3068 3069 /* 10th, 11th, 12th digits. */ 3070 num = w % 1000; 3071 *cp++ = '0' + num / 100; 3072 num %= 100; 3073 *cp++ = '0' + num / 10; 3074 num %= 10; 3075 *cp++ = '0' + num; 3076 3077 *cp = '\0'; /* Null Terminate the string. */ 3078 return ASC_TRUE; 3079 } 3080} 3081 3082/* 3083 * asc_prt_asc_board_eeprom() 3084 * 3085 * Print board EEPROM configuration. 3086 * 3087 * Note: no single line should be greater than ASC_PRTLINE_SIZE, 3088 * cf. asc_prt_line(). 3089 * 3090 * Return the number of characters copied into 'cp'. No more than 3091 * 'cplen' characters will be copied to 'cp'. 3092 */ 3093static int asc_prt_asc_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen) 3094{ 3095 struct asc_board *boardp = shost_priv(shost); 3096 ASC_DVC_VAR *asc_dvc_varp; 3097 int leftlen; 3098 int totlen; 3099 int len; 3100 ASCEEP_CONFIG *ep; 3101 int i; 3102#ifdef CONFIG_ISA 3103 int isa_dma_speed[] = { 10, 8, 7, 6, 5, 4, 3, 2 }; 3104#endif /* CONFIG_ISA */ 3105 uchar serialstr[13]; 3106 3107 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; 3108 ep = &boardp->eep_config.asc_eep; 3109 3110 leftlen = cplen; 3111 totlen = len = 0; 3112 3113 len = asc_prt_line(cp, leftlen, 3114 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", 3115 shost->host_no); 3116 ASC_PRT_NEXT(); 3117 3118 if (asc_get_eeprom_string((ushort *)&ep->adapter_info[0], serialstr) 3119 == ASC_TRUE) { 3120 len = 3121 asc_prt_line(cp, leftlen, " Serial Number: %s\n", 3122 serialstr); 3123 ASC_PRT_NEXT(); 3124 } else { 3125 if (ep->adapter_info[5] == 0xBB) { 3126 len = asc_prt_line(cp, leftlen, 3127 " Default Settings Used for EEPROM-less Adapter.\n"); 3128 ASC_PRT_NEXT(); 3129 } else { 3130 len = asc_prt_line(cp, leftlen, 3131 " Serial Number Signature Not Present.\n"); 3132 ASC_PRT_NEXT(); 3133 } 3134 } 3135 3136 len = asc_prt_line(cp, leftlen, 3137 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 3138 ASC_EEP_GET_CHIP_ID(ep), ep->max_total_qng, 3139 ep->max_tag_qng); 3140 ASC_PRT_NEXT(); 3141 3142 len = asc_prt_line(cp, leftlen, 3143 " cntl 0x%x, no_scam 0x%x\n", ep->cntl, ep->no_scam); 3144 ASC_PRT_NEXT(); 3145 3146 len = asc_prt_line(cp, leftlen, " Target ID: "); 3147 ASC_PRT_NEXT(); 3148 for (i = 0; i <= ASC_MAX_TID; i++) { 3149 len = asc_prt_line(cp, leftlen, " %d", i); 3150 ASC_PRT_NEXT(); 3151 } 3152 len = asc_prt_line(cp, leftlen, "\n"); 3153 ASC_PRT_NEXT(); 3154 3155 len = asc_prt_line(cp, leftlen, " Disconnects: "); 3156 ASC_PRT_NEXT(); 3157 for (i = 0; i <= ASC_MAX_TID; i++) { 3158 len = asc_prt_line(cp, leftlen, " %c", 3159 (ep-> 3160 disc_enable & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 3161 'N'); 3162 ASC_PRT_NEXT(); 3163 } 3164 len = asc_prt_line(cp, leftlen, "\n"); 3165 ASC_PRT_NEXT(); 3166 3167 len = asc_prt_line(cp, leftlen, " Command Queuing: "); 3168 ASC_PRT_NEXT(); 3169 for (i = 0; i <= ASC_MAX_TID; i++) { 3170 len = asc_prt_line(cp, leftlen, " %c", 3171 (ep-> 3172 use_cmd_qng & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 3173 'N'); 3174 ASC_PRT_NEXT(); 3175 } 3176 len = asc_prt_line(cp, leftlen, "\n"); 3177 ASC_PRT_NEXT(); 3178 3179 len = asc_prt_line(cp, leftlen, " Start Motor: "); 3180 ASC_PRT_NEXT(); 3181 for (i = 0; i <= ASC_MAX_TID; i++) { 3182 len = asc_prt_line(cp, leftlen, " %c", 3183 (ep-> 3184 start_motor & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 3185 'N'); 3186 ASC_PRT_NEXT(); 3187 } 3188 len = asc_prt_line(cp, leftlen, "\n"); 3189 ASC_PRT_NEXT(); 3190 3191 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:"); 3192 ASC_PRT_NEXT(); 3193 for (i = 0; i <= ASC_MAX_TID; i++) { 3194 len = asc_prt_line(cp, leftlen, " %c", 3195 (ep-> 3196 init_sdtr & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 3197 'N'); 3198 ASC_PRT_NEXT(); 3199 } 3200 len = asc_prt_line(cp, leftlen, "\n"); 3201 ASC_PRT_NEXT(); 3202 3203#ifdef CONFIG_ISA 3204 if (asc_dvc_varp->bus_type & ASC_IS_ISA) { 3205 len = asc_prt_line(cp, leftlen, 3206 " Host ISA DMA speed: %d MB/S\n", 3207 isa_dma_speed[ASC_EEP_GET_DMA_SPD(ep)]); 3208 ASC_PRT_NEXT(); 3209 } 3210#endif /* CONFIG_ISA */ 3211 3212 return totlen; 3213} 3214 3215/* 3216 * asc_prt_adv_board_eeprom() 3217 * 3218 * Print board EEPROM configuration. 3219 * 3220 * Note: no single line should be greater than ASC_PRTLINE_SIZE, 3221 * cf. asc_prt_line(). 3222 * 3223 * Return the number of characters copied into 'cp'. No more than 3224 * 'cplen' characters will be copied to 'cp'. 3225 */ 3226static int asc_prt_adv_board_eeprom(struct Scsi_Host *shost, char *cp, int cplen) 3227{ 3228 struct asc_board *boardp = shost_priv(shost); 3229 ADV_DVC_VAR *adv_dvc_varp; 3230 int leftlen; 3231 int totlen; 3232 int len; 3233 int i; 3234 char *termstr; 3235 uchar serialstr[13]; 3236 ADVEEP_3550_CONFIG *ep_3550 = NULL; 3237 ADVEEP_38C0800_CONFIG *ep_38C0800 = NULL; 3238 ADVEEP_38C1600_CONFIG *ep_38C1600 = NULL; 3239 ushort word; 3240 ushort *wordp; 3241 ushort sdtr_speed = 0; 3242 3243 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; 3244 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3245 ep_3550 = &boardp->eep_config.adv_3550_eep; 3246 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3247 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep; 3248 } else { 3249 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep; 3250 } 3251 3252 leftlen = cplen; 3253 totlen = len = 0; 3254 3255 len = asc_prt_line(cp, leftlen, 3256 "\nEEPROM Settings for AdvanSys SCSI Host %d:\n", 3257 shost->host_no); 3258 ASC_PRT_NEXT(); 3259 3260 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3261 wordp = &ep_3550->serial_number_word1; 3262 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3263 wordp = &ep_38C0800->serial_number_word1; 3264 } else { 3265 wordp = &ep_38C1600->serial_number_word1; 3266 } 3267 3268 if (asc_get_eeprom_string(wordp, serialstr) == ASC_TRUE) { 3269 len = 3270 asc_prt_line(cp, leftlen, " Serial Number: %s\n", 3271 serialstr); 3272 ASC_PRT_NEXT(); 3273 } else { 3274 len = asc_prt_line(cp, leftlen, 3275 " Serial Number Signature Not Present.\n"); 3276 ASC_PRT_NEXT(); 3277 } 3278 3279 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3280 len = asc_prt_line(cp, leftlen, 3281 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 3282 ep_3550->adapter_scsi_id, 3283 ep_3550->max_host_qng, ep_3550->max_dvc_qng); 3284 ASC_PRT_NEXT(); 3285 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3286 len = asc_prt_line(cp, leftlen, 3287 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 3288 ep_38C0800->adapter_scsi_id, 3289 ep_38C0800->max_host_qng, 3290 ep_38C0800->max_dvc_qng); 3291 ASC_PRT_NEXT(); 3292 } else { 3293 len = asc_prt_line(cp, leftlen, 3294 " Host SCSI ID: %u, Host Queue Size: %u, Device Queue Size: %u\n", 3295 ep_38C1600->adapter_scsi_id, 3296 ep_38C1600->max_host_qng, 3297 ep_38C1600->max_dvc_qng); 3298 ASC_PRT_NEXT(); 3299 } 3300 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3301 word = ep_3550->termination; 3302 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3303 word = ep_38C0800->termination_lvd; 3304 } else { 3305 word = ep_38C1600->termination_lvd; 3306 } 3307 switch (word) { 3308 case 1: 3309 termstr = "Low Off/High Off"; 3310 break; 3311 case 2: 3312 termstr = "Low Off/High On"; 3313 break; 3314 case 3: 3315 termstr = "Low On/High On"; 3316 break; 3317 default: 3318 case 0: 3319 termstr = "Automatic"; 3320 break; 3321 } 3322 3323 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3324 len = asc_prt_line(cp, leftlen, 3325 " termination: %u (%s), bios_ctrl: 0x%x\n", 3326 ep_3550->termination, termstr, 3327 ep_3550->bios_ctrl); 3328 ASC_PRT_NEXT(); 3329 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3330 len = asc_prt_line(cp, leftlen, 3331 " termination: %u (%s), bios_ctrl: 0x%x\n", 3332 ep_38C0800->termination_lvd, termstr, 3333 ep_38C0800->bios_ctrl); 3334 ASC_PRT_NEXT(); 3335 } else { 3336 len = asc_prt_line(cp, leftlen, 3337 " termination: %u (%s), bios_ctrl: 0x%x\n", 3338 ep_38C1600->termination_lvd, termstr, 3339 ep_38C1600->bios_ctrl); 3340 ASC_PRT_NEXT(); 3341 } 3342 3343 len = asc_prt_line(cp, leftlen, " Target ID: "); 3344 ASC_PRT_NEXT(); 3345 for (i = 0; i <= ADV_MAX_TID; i++) { 3346 len = asc_prt_line(cp, leftlen, " %X", i); 3347 ASC_PRT_NEXT(); 3348 } 3349 len = asc_prt_line(cp, leftlen, "\n"); 3350 ASC_PRT_NEXT(); 3351 3352 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3353 word = ep_3550->disc_enable; 3354 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3355 word = ep_38C0800->disc_enable; 3356 } else { 3357 word = ep_38C1600->disc_enable; 3358 } 3359 len = asc_prt_line(cp, leftlen, " Disconnects: "); 3360 ASC_PRT_NEXT(); 3361 for (i = 0; i <= ADV_MAX_TID; i++) { 3362 len = asc_prt_line(cp, leftlen, " %c", 3363 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3364 ASC_PRT_NEXT(); 3365 } 3366 len = asc_prt_line(cp, leftlen, "\n"); 3367 ASC_PRT_NEXT(); 3368 3369 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3370 word = ep_3550->tagqng_able; 3371 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3372 word = ep_38C0800->tagqng_able; 3373 } else { 3374 word = ep_38C1600->tagqng_able; 3375 } 3376 len = asc_prt_line(cp, leftlen, " Command Queuing: "); 3377 ASC_PRT_NEXT(); 3378 for (i = 0; i <= ADV_MAX_TID; i++) { 3379 len = asc_prt_line(cp, leftlen, " %c", 3380 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3381 ASC_PRT_NEXT(); 3382 } 3383 len = asc_prt_line(cp, leftlen, "\n"); 3384 ASC_PRT_NEXT(); 3385 3386 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3387 word = ep_3550->start_motor; 3388 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3389 word = ep_38C0800->start_motor; 3390 } else { 3391 word = ep_38C1600->start_motor; 3392 } 3393 len = asc_prt_line(cp, leftlen, " Start Motor: "); 3394 ASC_PRT_NEXT(); 3395 for (i = 0; i <= ADV_MAX_TID; i++) { 3396 len = asc_prt_line(cp, leftlen, " %c", 3397 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3398 ASC_PRT_NEXT(); 3399 } 3400 len = asc_prt_line(cp, leftlen, "\n"); 3401 ASC_PRT_NEXT(); 3402 3403 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3404 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:"); 3405 ASC_PRT_NEXT(); 3406 for (i = 0; i <= ADV_MAX_TID; i++) { 3407 len = asc_prt_line(cp, leftlen, " %c", 3408 (ep_3550-> 3409 sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 3410 'Y' : 'N'); 3411 ASC_PRT_NEXT(); 3412 } 3413 len = asc_prt_line(cp, leftlen, "\n"); 3414 ASC_PRT_NEXT(); 3415 } 3416 3417 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3418 len = asc_prt_line(cp, leftlen, " Ultra Transfer: "); 3419 ASC_PRT_NEXT(); 3420 for (i = 0; i <= ADV_MAX_TID; i++) { 3421 len = asc_prt_line(cp, leftlen, " %c", 3422 (ep_3550-> 3423 ultra_able & ADV_TID_TO_TIDMASK(i)) 3424 ? 'Y' : 'N'); 3425 ASC_PRT_NEXT(); 3426 } 3427 len = asc_prt_line(cp, leftlen, "\n"); 3428 ASC_PRT_NEXT(); 3429 } 3430 3431 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 3432 word = ep_3550->wdtr_able; 3433 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 3434 word = ep_38C0800->wdtr_able; 3435 } else { 3436 word = ep_38C1600->wdtr_able; 3437 } 3438 len = asc_prt_line(cp, leftlen, " Wide Transfer: "); 3439 ASC_PRT_NEXT(); 3440 for (i = 0; i <= ADV_MAX_TID; i++) { 3441 len = asc_prt_line(cp, leftlen, " %c", 3442 (word & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 'N'); 3443 ASC_PRT_NEXT(); 3444 } 3445 len = asc_prt_line(cp, leftlen, "\n"); 3446 ASC_PRT_NEXT(); 3447 3448 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800 || 3449 adv_dvc_varp->chip_type == ADV_CHIP_ASC38C1600) { 3450 len = asc_prt_line(cp, leftlen, 3451 " Synchronous Transfer Speed (Mhz):\n "); 3452 ASC_PRT_NEXT(); 3453 for (i = 0; i <= ADV_MAX_TID; i++) { 3454 char *speed_str; 3455 3456 if (i == 0) { 3457 sdtr_speed = adv_dvc_varp->sdtr_speed1; 3458 } else if (i == 4) { 3459 sdtr_speed = adv_dvc_varp->sdtr_speed2; 3460 } else if (i == 8) { 3461 sdtr_speed = adv_dvc_varp->sdtr_speed3; 3462 } else if (i == 12) { 3463 sdtr_speed = adv_dvc_varp->sdtr_speed4; 3464 } 3465 switch (sdtr_speed & ADV_MAX_TID) { 3466 case 0: 3467 speed_str = "Off"; 3468 break; 3469 case 1: 3470 speed_str = " 5"; 3471 break; 3472 case 2: 3473 speed_str = " 10"; 3474 break; 3475 case 3: 3476 speed_str = " 20"; 3477 break; 3478 case 4: 3479 speed_str = " 40"; 3480 break; 3481 case 5: 3482 speed_str = " 80"; 3483 break; 3484 default: 3485 speed_str = "Unk"; 3486 break; 3487 } 3488 len = asc_prt_line(cp, leftlen, "%X:%s ", i, speed_str); 3489 ASC_PRT_NEXT(); 3490 if (i == 7) { 3491 len = asc_prt_line(cp, leftlen, "\n "); 3492 ASC_PRT_NEXT(); 3493 } 3494 sdtr_speed >>= 4; 3495 } 3496 len = asc_prt_line(cp, leftlen, "\n"); 3497 ASC_PRT_NEXT(); 3498 } 3499 3500 return totlen; 3501} 3502 3503/* 3504 * asc_prt_driver_conf() 3505 * 3506 * Note: no single line should be greater than ASC_PRTLINE_SIZE, 3507 * cf. asc_prt_line(). 3508 * 3509 * Return the number of characters copied into 'cp'. No more than 3510 * 'cplen' characters will be copied to 'cp'. 3511 */ 3512static int asc_prt_driver_conf(struct Scsi_Host *shost, char *cp, int cplen) 3513{ 3514 struct asc_board *boardp = shost_priv(shost); 3515 int leftlen; 3516 int totlen; 3517 int len; 3518 int chip_scsi_id; 3519 3520 leftlen = cplen; 3521 totlen = len = 0; 3522 3523 len = asc_prt_line(cp, leftlen, 3524 "\nLinux Driver Configuration and Information for AdvanSys SCSI Host %d:\n", 3525 shost->host_no); 3526 ASC_PRT_NEXT(); 3527 3528 len = asc_prt_line(cp, leftlen, 3529 " host_busy %u, last_reset %u, max_id %u, max_lun %u, max_channel %u\n", 3530 shost->host_busy, shost->last_reset, shost->max_id, 3531 shost->max_lun, shost->max_channel); 3532 ASC_PRT_NEXT(); 3533 3534 len = asc_prt_line(cp, leftlen, 3535 " unique_id %d, can_queue %d, this_id %d, sg_tablesize %u, cmd_per_lun %u\n", 3536 shost->unique_id, shost->can_queue, shost->this_id, 3537 shost->sg_tablesize, shost->cmd_per_lun); 3538 ASC_PRT_NEXT(); 3539 3540 len = asc_prt_line(cp, leftlen, 3541 " unchecked_isa_dma %d, use_clustering %d\n", 3542 shost->unchecked_isa_dma, shost->use_clustering); 3543 ASC_PRT_NEXT(); 3544 3545 len = asc_prt_line(cp, leftlen, 3546 " flags 0x%x, last_reset 0x%x, jiffies 0x%x, asc_n_io_port 0x%x\n", 3547 boardp->flags, boardp->last_reset, jiffies, 3548 boardp->asc_n_io_port); 3549 ASC_PRT_NEXT(); 3550 3551 len = asc_prt_line(cp, leftlen, " io_port 0x%x\n", shost->io_port); 3552 ASC_PRT_NEXT(); 3553 3554 if (ASC_NARROW_BOARD(boardp)) { 3555 chip_scsi_id = boardp->dvc_cfg.asc_dvc_cfg.chip_scsi_id; 3556 } else { 3557 chip_scsi_id = boardp->dvc_var.adv_dvc_var.chip_scsi_id; 3558 } 3559 3560 return totlen; 3561} 3562 3563/* 3564 * asc_prt_asc_board_info() 3565 * 3566 * Print dynamic board configuration information. 3567 * 3568 * Note: no single line should be greater than ASC_PRTLINE_SIZE, 3569 * cf. asc_prt_line(). 3570 * 3571 * Return the number of characters copied into 'cp'. No more than 3572 * 'cplen' characters will be copied to 'cp'. 3573 */ 3574static int asc_prt_asc_board_info(struct Scsi_Host *shost, char *cp, int cplen) 3575{ 3576 struct asc_board *boardp = shost_priv(shost); 3577 int chip_scsi_id; 3578 int leftlen; 3579 int totlen; 3580 int len; 3581 ASC_DVC_VAR *v; 3582 ASC_DVC_CFG *c; 3583 int i; 3584 int renegotiate = 0; 3585 3586 v = &boardp->dvc_var.asc_dvc_var; 3587 c = &boardp->dvc_cfg.asc_dvc_cfg; 3588 chip_scsi_id = c->chip_scsi_id; 3589 3590 leftlen = cplen; 3591 totlen = len = 0; 3592 3593 len = asc_prt_line(cp, leftlen, 3594 "\nAsc Library Configuration and Statistics for AdvanSys SCSI Host %d:\n", 3595 shost->host_no); 3596 ASC_PRT_NEXT(); 3597 3598 len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, " 3599 "mcode_version 0x%x, err_code %u\n", 3600 c->chip_version, c->mcode_date, c->mcode_version, 3601 v->err_code); 3602 ASC_PRT_NEXT(); 3603 3604 /* Current number of commands waiting for the host. */ 3605 len = asc_prt_line(cp, leftlen, 3606 " Total Command Pending: %d\n", v->cur_total_qng); 3607 ASC_PRT_NEXT(); 3608 3609 len = asc_prt_line(cp, leftlen, " Command Queuing:"); 3610 ASC_PRT_NEXT(); 3611 for (i = 0; i <= ASC_MAX_TID; i++) { 3612 if ((chip_scsi_id == i) || 3613 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3614 continue; 3615 } 3616 len = asc_prt_line(cp, leftlen, " %X:%c", 3617 i, 3618 (v-> 3619 use_tagged_qng & ADV_TID_TO_TIDMASK(i)) ? 3620 'Y' : 'N'); 3621 ASC_PRT_NEXT(); 3622 } 3623 len = asc_prt_line(cp, leftlen, "\n"); 3624 ASC_PRT_NEXT(); 3625 3626 /* Current number of commands waiting for a device. */ 3627 len = asc_prt_line(cp, leftlen, " Command Queue Pending:"); 3628 ASC_PRT_NEXT(); 3629 for (i = 0; i <= ASC_MAX_TID; i++) { 3630 if ((chip_scsi_id == i) || 3631 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3632 continue; 3633 } 3634 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->cur_dvc_qng[i]); 3635 ASC_PRT_NEXT(); 3636 } 3637 len = asc_prt_line(cp, leftlen, "\n"); 3638 ASC_PRT_NEXT(); 3639 3640 /* Current limit on number of commands that can be sent to a device. */ 3641 len = asc_prt_line(cp, leftlen, " Command Queue Limit:"); 3642 ASC_PRT_NEXT(); 3643 for (i = 0; i <= ASC_MAX_TID; i++) { 3644 if ((chip_scsi_id == i) || 3645 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3646 continue; 3647 } 3648 len = asc_prt_line(cp, leftlen, " %X:%u", i, v->max_dvc_qng[i]); 3649 ASC_PRT_NEXT(); 3650 } 3651 len = asc_prt_line(cp, leftlen, "\n"); 3652 ASC_PRT_NEXT(); 3653 3654 /* Indicate whether the device has returned queue full status. */ 3655 len = asc_prt_line(cp, leftlen, " Command Queue Full:"); 3656 ASC_PRT_NEXT(); 3657 for (i = 0; i <= ASC_MAX_TID; i++) { 3658 if ((chip_scsi_id == i) || 3659 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3660 continue; 3661 } 3662 if (boardp->queue_full & ADV_TID_TO_TIDMASK(i)) { 3663 len = asc_prt_line(cp, leftlen, " %X:Y-%d", 3664 i, boardp->queue_full_cnt[i]); 3665 } else { 3666 len = asc_prt_line(cp, leftlen, " %X:N", i); 3667 } 3668 ASC_PRT_NEXT(); 3669 } 3670 len = asc_prt_line(cp, leftlen, "\n"); 3671 ASC_PRT_NEXT(); 3672 3673 len = asc_prt_line(cp, leftlen, " Synchronous Transfer:"); 3674 ASC_PRT_NEXT(); 3675 for (i = 0; i <= ASC_MAX_TID; i++) { 3676 if ((chip_scsi_id == i) || 3677 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3678 continue; 3679 } 3680 len = asc_prt_line(cp, leftlen, " %X:%c", 3681 i, 3682 (v-> 3683 sdtr_done & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 3684 'N'); 3685 ASC_PRT_NEXT(); 3686 } 3687 len = asc_prt_line(cp, leftlen, "\n"); 3688 ASC_PRT_NEXT(); 3689 3690 for (i = 0; i <= ASC_MAX_TID; i++) { 3691 uchar syn_period_ix; 3692 3693 if ((chip_scsi_id == i) || 3694 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) || 3695 ((v->init_sdtr & ADV_TID_TO_TIDMASK(i)) == 0)) { 3696 continue; 3697 } 3698 3699 len = asc_prt_line(cp, leftlen, " %X:", i); 3700 ASC_PRT_NEXT(); 3701 3702 if ((boardp->sdtr_data[i] & ASC_SYN_MAX_OFFSET) == 0) { 3703 len = asc_prt_line(cp, leftlen, " Asynchronous"); 3704 ASC_PRT_NEXT(); 3705 } else { 3706 syn_period_ix = 3707 (boardp->sdtr_data[i] >> 4) & (v->max_sdtr_index - 3708 1); 3709 3710 len = asc_prt_line(cp, leftlen, 3711 " Transfer Period Factor: %d (%d.%d Mhz),", 3712 v->sdtr_period_tbl[syn_period_ix], 3713 250 / 3714 v->sdtr_period_tbl[syn_period_ix], 3715 ASC_TENTHS(250, 3716 v-> 3717 sdtr_period_tbl 3718 [syn_period_ix])); 3719 ASC_PRT_NEXT(); 3720 3721 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d", 3722 boardp-> 3723 sdtr_data[i] & ASC_SYN_MAX_OFFSET); 3724 ASC_PRT_NEXT(); 3725 } 3726 3727 if ((v->sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { 3728 len = asc_prt_line(cp, leftlen, "*\n"); 3729 renegotiate = 1; 3730 } else { 3731 len = asc_prt_line(cp, leftlen, "\n"); 3732 } 3733 ASC_PRT_NEXT(); 3734 } 3735 3736 if (renegotiate) { 3737 len = asc_prt_line(cp, leftlen, 3738 " * = Re-negotiation pending before next command.\n"); 3739 ASC_PRT_NEXT(); 3740 } 3741 3742 return totlen; 3743} 3744 3745/* 3746 * asc_prt_adv_board_info() 3747 * 3748 * Print dynamic board configuration information. 3749 * 3750 * Note: no single line should be greater than ASC_PRTLINE_SIZE, 3751 * cf. asc_prt_line(). 3752 * 3753 * Return the number of characters copied into 'cp'. No more than 3754 * 'cplen' characters will be copied to 'cp'. 3755 */ 3756static int asc_prt_adv_board_info(struct Scsi_Host *shost, char *cp, int cplen) 3757{ 3758 struct asc_board *boardp = shost_priv(shost); 3759 int leftlen; 3760 int totlen; 3761 int len; 3762 int i; 3763 ADV_DVC_VAR *v; 3764 ADV_DVC_CFG *c; 3765 AdvPortAddr iop_base; 3766 ushort chip_scsi_id; 3767 ushort lramword; 3768 uchar lrambyte; 3769 ushort tagqng_able; 3770 ushort sdtr_able, wdtr_able; 3771 ushort wdtr_done, sdtr_done; 3772 ushort period = 0; 3773 int renegotiate = 0; 3774 3775 v = &boardp->dvc_var.adv_dvc_var; 3776 c = &boardp->dvc_cfg.adv_dvc_cfg; 3777 iop_base = v->iop_base; 3778 chip_scsi_id = v->chip_scsi_id; 3779 3780 leftlen = cplen; 3781 totlen = len = 0; 3782 3783 len = asc_prt_line(cp, leftlen, 3784 "\nAdv Library Configuration and Statistics for AdvanSys SCSI Host %d:\n", 3785 shost->host_no); 3786 ASC_PRT_NEXT(); 3787 3788 len = asc_prt_line(cp, leftlen, 3789 " iop_base 0x%lx, cable_detect: %X, err_code %u\n", 3790 v->iop_base, 3791 AdvReadWordRegister(iop_base, 3792 IOPW_SCSI_CFG1) & CABLE_DETECT, 3793 v->err_code); 3794 ASC_PRT_NEXT(); 3795 3796 len = asc_prt_line(cp, leftlen, " chip_version %u, mcode_date 0x%x, " 3797 "mcode_version 0x%x\n", c->chip_version, 3798 c->mcode_date, c->mcode_version); 3799 ASC_PRT_NEXT(); 3800 3801 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 3802 len = asc_prt_line(cp, leftlen, " Queuing Enabled:"); 3803 ASC_PRT_NEXT(); 3804 for (i = 0; i <= ADV_MAX_TID; i++) { 3805 if ((chip_scsi_id == i) || 3806 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3807 continue; 3808 } 3809 3810 len = asc_prt_line(cp, leftlen, " %X:%c", 3811 i, 3812 (tagqng_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 3813 'N'); 3814 ASC_PRT_NEXT(); 3815 } 3816 len = asc_prt_line(cp, leftlen, "\n"); 3817 ASC_PRT_NEXT(); 3818 3819 len = asc_prt_line(cp, leftlen, " Queue Limit:"); 3820 ASC_PRT_NEXT(); 3821 for (i = 0; i <= ADV_MAX_TID; i++) { 3822 if ((chip_scsi_id == i) || 3823 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3824 continue; 3825 } 3826 3827 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + i, 3828 lrambyte); 3829 3830 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte); 3831 ASC_PRT_NEXT(); 3832 } 3833 len = asc_prt_line(cp, leftlen, "\n"); 3834 ASC_PRT_NEXT(); 3835 3836 len = asc_prt_line(cp, leftlen, " Command Pending:"); 3837 ASC_PRT_NEXT(); 3838 for (i = 0; i <= ADV_MAX_TID; i++) { 3839 if ((chip_scsi_id == i) || 3840 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3841 continue; 3842 } 3843 3844 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_QUEUED_CMD + i, 3845 lrambyte); 3846 3847 len = asc_prt_line(cp, leftlen, " %X:%d", i, lrambyte); 3848 ASC_PRT_NEXT(); 3849 } 3850 len = asc_prt_line(cp, leftlen, "\n"); 3851 ASC_PRT_NEXT(); 3852 3853 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 3854 len = asc_prt_line(cp, leftlen, " Wide Enabled:"); 3855 ASC_PRT_NEXT(); 3856 for (i = 0; i <= ADV_MAX_TID; i++) { 3857 if ((chip_scsi_id == i) || 3858 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3859 continue; 3860 } 3861 3862 len = asc_prt_line(cp, leftlen, " %X:%c", 3863 i, 3864 (wdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 3865 'N'); 3866 ASC_PRT_NEXT(); 3867 } 3868 len = asc_prt_line(cp, leftlen, "\n"); 3869 ASC_PRT_NEXT(); 3870 3871 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, wdtr_done); 3872 len = asc_prt_line(cp, leftlen, " Transfer Bit Width:"); 3873 ASC_PRT_NEXT(); 3874 for (i = 0; i <= ADV_MAX_TID; i++) { 3875 if ((chip_scsi_id == i) || 3876 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3877 continue; 3878 } 3879 3880 AdvReadWordLram(iop_base, 3881 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i), 3882 lramword); 3883 3884 len = asc_prt_line(cp, leftlen, " %X:%d", 3885 i, (lramword & 0x8000) ? 16 : 8); 3886 ASC_PRT_NEXT(); 3887 3888 if ((wdtr_able & ADV_TID_TO_TIDMASK(i)) && 3889 (wdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { 3890 len = asc_prt_line(cp, leftlen, "*"); 3891 ASC_PRT_NEXT(); 3892 renegotiate = 1; 3893 } 3894 } 3895 len = asc_prt_line(cp, leftlen, "\n"); 3896 ASC_PRT_NEXT(); 3897 3898 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 3899 len = asc_prt_line(cp, leftlen, " Synchronous Enabled:"); 3900 ASC_PRT_NEXT(); 3901 for (i = 0; i <= ADV_MAX_TID; i++) { 3902 if ((chip_scsi_id == i) || 3903 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0)) { 3904 continue; 3905 } 3906 3907 len = asc_prt_line(cp, leftlen, " %X:%c", 3908 i, 3909 (sdtr_able & ADV_TID_TO_TIDMASK(i)) ? 'Y' : 3910 'N'); 3911 ASC_PRT_NEXT(); 3912 } 3913 len = asc_prt_line(cp, leftlen, "\n"); 3914 ASC_PRT_NEXT(); 3915 3916 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, sdtr_done); 3917 for (i = 0; i <= ADV_MAX_TID; i++) { 3918 3919 AdvReadWordLram(iop_base, 3920 ASC_MC_DEVICE_HSHK_CFG_TABLE + (2 * i), 3921 lramword); 3922 lramword &= ~0x8000; 3923 3924 if ((chip_scsi_id == i) || 3925 ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(i)) == 0) || 3926 ((sdtr_able & ADV_TID_TO_TIDMASK(i)) == 0)) { 3927 continue; 3928 } 3929 3930 len = asc_prt_line(cp, leftlen, " %X:", i); 3931 ASC_PRT_NEXT(); 3932 3933 if ((lramword & 0x1F) == 0) { /* Check for REQ/ACK Offset 0. */ 3934 len = asc_prt_line(cp, leftlen, " Asynchronous"); 3935 ASC_PRT_NEXT(); 3936 } else { 3937 len = 3938 asc_prt_line(cp, leftlen, 3939 " Transfer Period Factor: "); 3940 ASC_PRT_NEXT(); 3941 3942 if ((lramword & 0x1F00) == 0x1100) { /* 80 Mhz */ 3943 len = 3944 asc_prt_line(cp, leftlen, "9 (80.0 Mhz),"); 3945 ASC_PRT_NEXT(); 3946 } else if ((lramword & 0x1F00) == 0x1000) { /* 40 Mhz */ 3947 len = 3948 asc_prt_line(cp, leftlen, "10 (40.0 Mhz),"); 3949 ASC_PRT_NEXT(); 3950 } else { /* 20 Mhz or below. */ 3951 3952 period = (((lramword >> 8) * 25) + 50) / 4; 3953 3954 if (period == 0) { /* Should never happen. */ 3955 len = 3956 asc_prt_line(cp, leftlen, 3957 "%d (? Mhz), "); 3958 ASC_PRT_NEXT(); 3959 } else { 3960 len = asc_prt_line(cp, leftlen, 3961 "%d (%d.%d Mhz),", 3962 period, 250 / period, 3963 ASC_TENTHS(250, 3964 period)); 3965 ASC_PRT_NEXT(); 3966 } 3967 } 3968 3969 len = asc_prt_line(cp, leftlen, " REQ/ACK Offset: %d", 3970 lramword & 0x1F); 3971 ASC_PRT_NEXT(); 3972 } 3973 3974 if ((sdtr_done & ADV_TID_TO_TIDMASK(i)) == 0) { 3975 len = asc_prt_line(cp, leftlen, "*\n"); 3976 renegotiate = 1; 3977 } else { 3978 len = asc_prt_line(cp, leftlen, "\n"); 3979 } 3980 ASC_PRT_NEXT(); 3981 } 3982 3983 if (renegotiate) { 3984 len = asc_prt_line(cp, leftlen, 3985 " * = Re-negotiation pending before next command.\n"); 3986 ASC_PRT_NEXT(); 3987 } 3988 3989 return totlen; 3990} 3991 3992/* 3993 * asc_proc_copy() 3994 * 3995 * Copy proc information to a read buffer taking into account the current 3996 * read offset in the file and the remaining space in the read buffer. 3997 */ 3998static int 3999asc_proc_copy(off_t advoffset, off_t offset, char *curbuf, int leftlen, 4000 char *cp, int cplen) 4001{ 4002 int cnt = 0; 4003 4004 ASC_DBG(2, "offset %d, advoffset %d, cplen %d\n", 4005 (unsigned)offset, (unsigned)advoffset, cplen); 4006 if (offset <= advoffset) { 4007 /* Read offset below current offset, copy everything. */ 4008 cnt = min(cplen, leftlen); 4009 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n", 4010 (ulong)curbuf, (ulong)cp, cnt); 4011 memcpy(curbuf, cp, cnt); 4012 } else if (offset < advoffset + cplen) { 4013 /* Read offset within current range, partial copy. */ 4014 cnt = (advoffset + cplen) - offset; 4015 cp = (cp + cplen) - cnt; 4016 cnt = min(cnt, leftlen); 4017 ASC_DBG(2, "curbuf 0x%lx, cp 0x%lx, cnt %d\n", 4018 (ulong)curbuf, (ulong)cp, cnt); 4019 memcpy(curbuf, cp, cnt); 4020 } 4021 return cnt; 4022} 4023 4024#ifdef ADVANSYS_STATS 4025/* 4026 * asc_prt_board_stats() 4027 * 4028 * Note: no single line should be greater than ASC_PRTLINE_SIZE, 4029 * cf. asc_prt_line(). 4030 * 4031 * Return the number of characters copied into 'cp'. No more than 4032 * 'cplen' characters will be copied to 'cp'. 4033 */ 4034static int asc_prt_board_stats(struct Scsi_Host *shost, char *cp, int cplen) 4035{ 4036 struct asc_board *boardp = shost_priv(shost); 4037 struct asc_stats *s = &boardp->asc_stats; 4038 4039 int leftlen = cplen; 4040 int len, totlen = 0; 4041 4042 len = asc_prt_line(cp, leftlen, 4043 "\nLinux Driver Statistics for AdvanSys SCSI Host %d:\n", 4044 shost->host_no); 4045 ASC_PRT_NEXT(); 4046 4047 len = asc_prt_line(cp, leftlen, 4048 " queuecommand %lu, reset %lu, biosparam %lu, interrupt %lu\n", 4049 s->queuecommand, s->reset, s->biosparam, 4050 s->interrupt); 4051 ASC_PRT_NEXT(); 4052 4053 len = asc_prt_line(cp, leftlen, 4054 " callback %lu, done %lu, build_error %lu, build_noreq %lu, build_nosg %lu\n", 4055 s->callback, s->done, s->build_error, 4056 s->adv_build_noreq, s->adv_build_nosg); 4057 ASC_PRT_NEXT(); 4058 4059 len = asc_prt_line(cp, leftlen, 4060 " exe_noerror %lu, exe_busy %lu, exe_error %lu, exe_unknown %lu\n", 4061 s->exe_noerror, s->exe_busy, s->exe_error, 4062 s->exe_unknown); 4063 ASC_PRT_NEXT(); 4064 4065 /* 4066 * Display data transfer statistics. 4067 */ 4068 if (s->xfer_cnt > 0) { 4069 len = asc_prt_line(cp, leftlen, " xfer_cnt %lu, xfer_elem %lu, ", 4070 s->xfer_cnt, s->xfer_elem); 4071 ASC_PRT_NEXT(); 4072 4073 len = asc_prt_line(cp, leftlen, "xfer_bytes %lu.%01lu kb\n", 4074 s->xfer_sect / 2, ASC_TENTHS(s->xfer_sect, 2)); 4075 ASC_PRT_NEXT(); 4076 4077 /* Scatter gather transfer statistics */ 4078 len = asc_prt_line(cp, leftlen, " avg_num_elem %lu.%01lu, ", 4079 s->xfer_elem / s->xfer_cnt, 4080 ASC_TENTHS(s->xfer_elem, s->xfer_cnt)); 4081 ASC_PRT_NEXT(); 4082 4083 len = asc_prt_line(cp, leftlen, "avg_elem_size %lu.%01lu kb, ", 4084 (s->xfer_sect / 2) / s->xfer_elem, 4085 ASC_TENTHS((s->xfer_sect / 2), s->xfer_elem)); 4086 ASC_PRT_NEXT(); 4087 4088 len = asc_prt_line(cp, leftlen, "avg_xfer_size %lu.%01lu kb\n", 4089 (s->xfer_sect / 2) / s->xfer_cnt, 4090 ASC_TENTHS((s->xfer_sect / 2), s->xfer_cnt)); 4091 ASC_PRT_NEXT(); 4092 } 4093 4094 return totlen; 4095} 4096#endif /* ADVANSYS_STATS */ 4097 4098/* 4099 * advansys_proc_info() - /proc/scsi/advansys/{0,1,2,3,...} 4100 * 4101 * *buffer: I/O buffer 4102 * **start: if inout == FALSE pointer into buffer where user read should start 4103 * offset: current offset into a /proc/scsi/advansys/[0...] file 4104 * length: length of buffer 4105 * hostno: Scsi_Host host_no 4106 * inout: TRUE - user is writing; FALSE - user is reading 4107 * 4108 * Return the number of bytes read from or written to a 4109 * /proc/scsi/advansys/[0...] file. 4110 * 4111 * Note: This function uses the per board buffer 'prtbuf' which is 4112 * allocated when the board is initialized in advansys_detect(). The 4113 * buffer is ASC_PRTBUF_SIZE bytes. The function asc_proc_copy() is 4114 * used to write to the buffer. The way asc_proc_copy() is written 4115 * if 'prtbuf' is too small it will not be overwritten. Instead the 4116 * user just won't get all the available statistics. 4117 */ 4118static int 4119advansys_proc_info(struct Scsi_Host *shost, char *buffer, char **start, 4120 off_t offset, int length, int inout) 4121{ 4122 struct asc_board *boardp = shost_priv(shost); 4123 char *cp; 4124 int cplen; 4125 int cnt; 4126 int totcnt; 4127 int leftlen; 4128 char *curbuf; 4129 off_t advoffset; 4130 4131 ASC_DBG(1, "begin\n"); 4132 4133 /* 4134 * User write not supported. 4135 */ 4136 if (inout == TRUE) 4137 return -ENOSYS; 4138 4139 /* 4140 * User read of /proc/scsi/advansys/[0...] file. 4141 */ 4142 4143 /* Copy read data starting at the beginning of the buffer. */ 4144 *start = buffer; 4145 curbuf = buffer; 4146 advoffset = 0; 4147 totcnt = 0; 4148 leftlen = length; 4149 4150 /* 4151 * Get board configuration information. 4152 * 4153 * advansys_info() returns the board string from its own static buffer. 4154 */ 4155 cp = (char *)advansys_info(shost); 4156 strcat(cp, "\n"); 4157 cplen = strlen(cp); 4158 /* Copy board information. */ 4159 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); 4160 totcnt += cnt; 4161 leftlen -= cnt; 4162 if (leftlen == 0) { 4163 ASC_DBG(1, "totcnt %d\n", totcnt); 4164 return totcnt; 4165 } 4166 advoffset += cplen; 4167 curbuf += cnt; 4168 4169 /* 4170 * Display Wide Board BIOS Information. 4171 */ 4172 if (!ASC_NARROW_BOARD(boardp)) { 4173 cp = boardp->prtbuf; 4174 cplen = asc_prt_adv_bios(shost, cp, ASC_PRTBUF_SIZE); 4175 BUG_ON(cplen >= ASC_PRTBUF_SIZE); 4176 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, 4177 cplen); 4178 totcnt += cnt; 4179 leftlen -= cnt; 4180 if (leftlen == 0) { 4181 ASC_DBG(1, "totcnt %d\n", totcnt); 4182 return totcnt; 4183 } 4184 advoffset += cplen; 4185 curbuf += cnt; 4186 } 4187 4188 /* 4189 * Display driver information for each device attached to the board. 4190 */ 4191 cp = boardp->prtbuf; 4192 cplen = asc_prt_board_devices(shost, cp, ASC_PRTBUF_SIZE); 4193 BUG_ON(cplen >= ASC_PRTBUF_SIZE); 4194 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); 4195 totcnt += cnt; 4196 leftlen -= cnt; 4197 if (leftlen == 0) { 4198 ASC_DBG(1, "totcnt %d\n", totcnt); 4199 return totcnt; 4200 } 4201 advoffset += cplen; 4202 curbuf += cnt; 4203 4204 /* 4205 * Display EEPROM configuration for the board. 4206 */ 4207 cp = boardp->prtbuf; 4208 if (ASC_NARROW_BOARD(boardp)) { 4209 cplen = asc_prt_asc_board_eeprom(shost, cp, ASC_PRTBUF_SIZE); 4210 } else { 4211 cplen = asc_prt_adv_board_eeprom(shost, cp, ASC_PRTBUF_SIZE); 4212 } 4213 BUG_ON(cplen >= ASC_PRTBUF_SIZE); 4214 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); 4215 totcnt += cnt; 4216 leftlen -= cnt; 4217 if (leftlen == 0) { 4218 ASC_DBG(1, "totcnt %d\n", totcnt); 4219 return totcnt; 4220 } 4221 advoffset += cplen; 4222 curbuf += cnt; 4223 4224 /* 4225 * Display driver configuration and information for the board. 4226 */ 4227 cp = boardp->prtbuf; 4228 cplen = asc_prt_driver_conf(shost, cp, ASC_PRTBUF_SIZE); 4229 BUG_ON(cplen >= ASC_PRTBUF_SIZE); 4230 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); 4231 totcnt += cnt; 4232 leftlen -= cnt; 4233 if (leftlen == 0) { 4234 ASC_DBG(1, "totcnt %d\n", totcnt); 4235 return totcnt; 4236 } 4237 advoffset += cplen; 4238 curbuf += cnt; 4239 4240#ifdef ADVANSYS_STATS 4241 /* 4242 * Display driver statistics for the board. 4243 */ 4244 cp = boardp->prtbuf; 4245 cplen = asc_prt_board_stats(shost, cp, ASC_PRTBUF_SIZE); 4246 BUG_ON(cplen >= ASC_PRTBUF_SIZE); 4247 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); 4248 totcnt += cnt; 4249 leftlen -= cnt; 4250 if (leftlen == 0) { 4251 ASC_DBG(1, "totcnt %d\n", totcnt); 4252 return totcnt; 4253 } 4254 advoffset += cplen; 4255 curbuf += cnt; 4256#endif /* ADVANSYS_STATS */ 4257 4258 /* 4259 * Display Asc Library dynamic configuration information 4260 * for the board. 4261 */ 4262 cp = boardp->prtbuf; 4263 if (ASC_NARROW_BOARD(boardp)) { 4264 cplen = asc_prt_asc_board_info(shost, cp, ASC_PRTBUF_SIZE); 4265 } else { 4266 cplen = asc_prt_adv_board_info(shost, cp, ASC_PRTBUF_SIZE); 4267 } 4268 BUG_ON(cplen >= ASC_PRTBUF_SIZE); 4269 cnt = asc_proc_copy(advoffset, offset, curbuf, leftlen, cp, cplen); 4270 totcnt += cnt; 4271 leftlen -= cnt; 4272 if (leftlen == 0) { 4273 ASC_DBG(1, "totcnt %d\n", totcnt); 4274 return totcnt; 4275 } 4276 advoffset += cplen; 4277 curbuf += cnt; 4278 4279 ASC_DBG(1, "totcnt %d\n", totcnt); 4280 4281 return totcnt; 4282} 4283#endif /* CONFIG_PROC_FS */ 4284 4285static void asc_scsi_done(struct scsi_cmnd *scp) 4286{ 4287 scsi_dma_unmap(scp); 4288 ASC_STATS(scp->device->host, done); 4289 scp->scsi_done(scp); 4290} 4291 4292static void AscSetBank(PortAddr iop_base, uchar bank) 4293{ 4294 uchar val; 4295 4296 val = AscGetChipControl(iop_base) & 4297 (~ 4298 (CC_SINGLE_STEP | CC_TEST | CC_DIAG | CC_SCSI_RESET | 4299 CC_CHIP_RESET)); 4300 if (bank == 1) { 4301 val |= CC_BANK_ONE; 4302 } else if (bank == 2) { 4303 val |= CC_DIAG | CC_BANK_ONE; 4304 } else { 4305 val &= ~CC_BANK_ONE; 4306 } 4307 AscSetChipControl(iop_base, val); 4308} 4309 4310static void AscSetChipIH(PortAddr iop_base, ushort ins_code) 4311{ 4312 AscSetBank(iop_base, 1); 4313 AscWriteChipIH(iop_base, ins_code); 4314 AscSetBank(iop_base, 0); 4315} 4316 4317static int AscStartChip(PortAddr iop_base) 4318{ 4319 AscSetChipControl(iop_base, 0); 4320 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) { 4321 return (0); 4322 } 4323 return (1); 4324} 4325 4326static int AscStopChip(PortAddr iop_base) 4327{ 4328 uchar cc_val; 4329 4330 cc_val = 4331 AscGetChipControl(iop_base) & 4332 (~(CC_SINGLE_STEP | CC_TEST | CC_DIAG)); 4333 AscSetChipControl(iop_base, (uchar)(cc_val | CC_HALT)); 4334 AscSetChipIH(iop_base, INS_HALT); 4335 AscSetChipIH(iop_base, INS_RFLAG_WTM); 4336 if ((AscGetChipStatus(iop_base) & CSW_HALTED) == 0) { 4337 return (0); 4338 } 4339 return (1); 4340} 4341 4342static int AscIsChipHalted(PortAddr iop_base) 4343{ 4344 if ((AscGetChipStatus(iop_base) & CSW_HALTED) != 0) { 4345 if ((AscGetChipControl(iop_base) & CC_HALT) != 0) { 4346 return (1); 4347 } 4348 } 4349 return (0); 4350} 4351 4352static int AscResetChipAndScsiBus(ASC_DVC_VAR *asc_dvc) 4353{ 4354 PortAddr iop_base; 4355 int i = 10; 4356 4357 iop_base = asc_dvc->iop_base; 4358 while ((AscGetChipStatus(iop_base) & CSW_SCSI_RESET_ACTIVE) 4359 && (i-- > 0)) { 4360 mdelay(100); 4361 } 4362 AscStopChip(iop_base); 4363 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_SCSI_RESET | CC_HALT); 4364 udelay(60); 4365 AscSetChipIH(iop_base, INS_RFLAG_WTM); 4366 AscSetChipIH(iop_base, INS_HALT); 4367 AscSetChipControl(iop_base, CC_CHIP_RESET | CC_HALT); 4368 AscSetChipControl(iop_base, CC_HALT); 4369 mdelay(200); 4370 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT); 4371 AscSetChipStatus(iop_base, 0); 4372 return (AscIsChipHalted(iop_base)); 4373} 4374 4375static int AscFindSignature(PortAddr iop_base) 4376{ 4377 ushort sig_word; 4378 4379 ASC_DBG(1, "AscGetChipSignatureByte(0x%x) 0x%x\n", 4380 iop_base, AscGetChipSignatureByte(iop_base)); 4381 if (AscGetChipSignatureByte(iop_base) == (uchar)ASC_1000_ID1B) { 4382 ASC_DBG(1, "AscGetChipSignatureWord(0x%x) 0x%x\n", 4383 iop_base, AscGetChipSignatureWord(iop_base)); 4384 sig_word = AscGetChipSignatureWord(iop_base); 4385 if ((sig_word == (ushort)ASC_1000_ID0W) || 4386 (sig_word == (ushort)ASC_1000_ID0W_FIX)) { 4387 return (1); 4388 } 4389 } 4390 return (0); 4391} 4392 4393static void AscEnableInterrupt(PortAddr iop_base) 4394{ 4395 ushort cfg; 4396 4397 cfg = AscGetChipCfgLsw(iop_base); 4398 AscSetChipCfgLsw(iop_base, cfg | ASC_CFG0_HOST_INT_ON); 4399} 4400 4401static void AscDisableInterrupt(PortAddr iop_base) 4402{ 4403 ushort cfg; 4404 4405 cfg = AscGetChipCfgLsw(iop_base); 4406 AscSetChipCfgLsw(iop_base, cfg & (~ASC_CFG0_HOST_INT_ON)); 4407} 4408 4409static uchar AscReadLramByte(PortAddr iop_base, ushort addr) 4410{ 4411 unsigned char byte_data; 4412 unsigned short word_data; 4413 4414 if (isodd_word(addr)) { 4415 AscSetChipLramAddr(iop_base, addr - 1); 4416 word_data = AscGetChipLramData(iop_base); 4417 byte_data = (word_data >> 8) & 0xFF; 4418 } else { 4419 AscSetChipLramAddr(iop_base, addr); 4420 word_data = AscGetChipLramData(iop_base); 4421 byte_data = word_data & 0xFF; 4422 } 4423 return byte_data; 4424} 4425 4426static ushort AscReadLramWord(PortAddr iop_base, ushort addr) 4427{ 4428 ushort word_data; 4429 4430 AscSetChipLramAddr(iop_base, addr); 4431 word_data = AscGetChipLramData(iop_base); 4432 return (word_data); 4433} 4434 4435#if CC_VERY_LONG_SG_LIST 4436static ASC_DCNT AscReadLramDWord(PortAddr iop_base, ushort addr) 4437{ 4438 ushort val_low, val_high; 4439 ASC_DCNT dword_data; 4440 4441 AscSetChipLramAddr(iop_base, addr); 4442 val_low = AscGetChipLramData(iop_base); 4443 val_high = AscGetChipLramData(iop_base); 4444 dword_data = ((ASC_DCNT) val_high << 16) | (ASC_DCNT) val_low; 4445 return (dword_data); 4446} 4447#endif /* CC_VERY_LONG_SG_LIST */ 4448 4449static void 4450AscMemWordSetLram(PortAddr iop_base, ushort s_addr, ushort set_wval, int words) 4451{ 4452 int i; 4453 4454 AscSetChipLramAddr(iop_base, s_addr); 4455 for (i = 0; i < words; i++) { 4456 AscSetChipLramData(iop_base, set_wval); 4457 } 4458} 4459 4460static void AscWriteLramWord(PortAddr iop_base, ushort addr, ushort word_val) 4461{ 4462 AscSetChipLramAddr(iop_base, addr); 4463 AscSetChipLramData(iop_base, word_val); 4464} 4465 4466static void AscWriteLramByte(PortAddr iop_base, ushort addr, uchar byte_val) 4467{ 4468 ushort word_data; 4469 4470 if (isodd_word(addr)) { 4471 addr--; 4472 word_data = AscReadLramWord(iop_base, addr); 4473 word_data &= 0x00FF; 4474 word_data |= (((ushort)byte_val << 8) & 0xFF00); 4475 } else { 4476 word_data = AscReadLramWord(iop_base, addr); 4477 word_data &= 0xFF00; 4478 word_data |= ((ushort)byte_val & 0x00FF); 4479 } 4480 AscWriteLramWord(iop_base, addr, word_data); 4481} 4482 4483/* 4484 * Copy 2 bytes to LRAM. 4485 * 4486 * The source data is assumed to be in little-endian order in memory 4487 * and is maintained in little-endian order when written to LRAM. 4488 */ 4489static void 4490AscMemWordCopyPtrToLram(PortAddr iop_base, ushort s_addr, 4491 const uchar *s_buffer, int words) 4492{ 4493 int i; 4494 4495 AscSetChipLramAddr(iop_base, s_addr); 4496 for (i = 0; i < 2 * words; i += 2) { 4497 /* 4498 * On a little-endian system the second argument below 4499 * produces a little-endian ushort which is written to 4500 * LRAM in little-endian order. On a big-endian system 4501 * the second argument produces a big-endian ushort which 4502 * is "transparently" byte-swapped by outpw() and written 4503 * in little-endian order to LRAM. 4504 */ 4505 outpw(iop_base + IOP_RAM_DATA, 4506 ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); 4507 } 4508} 4509 4510/* 4511 * Copy 4 bytes to LRAM. 4512 * 4513 * The source data is assumed to be in little-endian order in memory 4514 * and is maintained in little-endian order when writen to LRAM. 4515 */ 4516static void 4517AscMemDWordCopyPtrToLram(PortAddr iop_base, 4518 ushort s_addr, uchar *s_buffer, int dwords) 4519{ 4520 int i; 4521 4522 AscSetChipLramAddr(iop_base, s_addr); 4523 for (i = 0; i < 4 * dwords; i += 4) { 4524 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 1] << 8) | s_buffer[i]); /* LSW */ 4525 outpw(iop_base + IOP_RAM_DATA, ((ushort)s_buffer[i + 3] << 8) | s_buffer[i + 2]); /* MSW */ 4526 } 4527} 4528 4529/* 4530 * Copy 2 bytes from LRAM. 4531 * 4532 * The source data is assumed to be in little-endian order in LRAM 4533 * and is maintained in little-endian order when written to memory. 4534 */ 4535static void 4536AscMemWordCopyPtrFromLram(PortAddr iop_base, 4537 ushort s_addr, uchar *d_buffer, int words) 4538{ 4539 int i; 4540 ushort word; 4541 4542 AscSetChipLramAddr(iop_base, s_addr); 4543 for (i = 0; i < 2 * words; i += 2) { 4544 word = inpw(iop_base + IOP_RAM_DATA); 4545 d_buffer[i] = word & 0xff; 4546 d_buffer[i + 1] = (word >> 8) & 0xff; 4547 } 4548} 4549 4550static ASC_DCNT AscMemSumLramWord(PortAddr iop_base, ushort s_addr, int words) 4551{ 4552 ASC_DCNT sum; 4553 int i; 4554 4555 sum = 0L; 4556 for (i = 0; i < words; i++, s_addr += 2) { 4557 sum += AscReadLramWord(iop_base, s_addr); 4558 } 4559 return (sum); 4560} 4561 4562static ushort AscInitLram(ASC_DVC_VAR *asc_dvc) 4563{ 4564 uchar i; 4565 ushort s_addr; 4566 PortAddr iop_base; 4567 ushort warn_code; 4568 4569 iop_base = asc_dvc->iop_base; 4570 warn_code = 0; 4571 AscMemWordSetLram(iop_base, ASC_QADR_BEG, 0, 4572 (ushort)(((int)(asc_dvc->max_total_qng + 2 + 1) * 4573 64) >> 1)); 4574 i = ASC_MIN_ACTIVE_QNO; 4575 s_addr = ASC_QADR_BEG + ASC_QBLK_SIZE; 4576 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), 4577 (uchar)(i + 1)); 4578 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), 4579 (uchar)(asc_dvc->max_total_qng)); 4580 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), 4581 (uchar)i); 4582 i++; 4583 s_addr += ASC_QBLK_SIZE; 4584 for (; i < asc_dvc->max_total_qng; i++, s_addr += ASC_QBLK_SIZE) { 4585 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), 4586 (uchar)(i + 1)); 4587 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), 4588 (uchar)(i - 1)); 4589 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), 4590 (uchar)i); 4591 } 4592 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_FWD), 4593 (uchar)ASC_QLINK_END); 4594 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_BWD), 4595 (uchar)(asc_dvc->max_total_qng - 1)); 4596 AscWriteLramByte(iop_base, (ushort)(s_addr + ASC_SCSIQ_B_QNO), 4597 (uchar)asc_dvc->max_total_qng); 4598 i++; 4599 s_addr += ASC_QBLK_SIZE; 4600 for (; i <= (uchar)(asc_dvc->max_total_qng + 3); 4601 i++, s_addr += ASC_QBLK_SIZE) { 4602 AscWriteLramByte(iop_base, 4603 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_FWD), i); 4604 AscWriteLramByte(iop_base, 4605 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_BWD), i); 4606 AscWriteLramByte(iop_base, 4607 (ushort)(s_addr + (ushort)ASC_SCSIQ_B_QNO), i); 4608 } 4609 return warn_code; 4610} 4611 4612static ASC_DCNT 4613AscLoadMicroCode(PortAddr iop_base, ushort s_addr, 4614 const uchar *mcode_buf, ushort mcode_size) 4615{ 4616 ASC_DCNT chksum; 4617 ushort mcode_word_size; 4618 ushort mcode_chksum; 4619 4620 /* Write the microcode buffer starting at LRAM address 0. */ 4621 mcode_word_size = (ushort)(mcode_size >> 1); 4622 AscMemWordSetLram(iop_base, s_addr, 0, mcode_word_size); 4623 AscMemWordCopyPtrToLram(iop_base, s_addr, mcode_buf, mcode_word_size); 4624 4625 chksum = AscMemSumLramWord(iop_base, s_addr, mcode_word_size); 4626 ASC_DBG(1, "chksum 0x%lx\n", (ulong)chksum); 4627 mcode_chksum = (ushort)AscMemSumLramWord(iop_base, 4628 (ushort)ASC_CODE_SEC_BEG, 4629 (ushort)((mcode_size - 4630 s_addr - (ushort) 4631 ASC_CODE_SEC_BEG) / 4632 2)); 4633 ASC_DBG(1, "mcode_chksum 0x%lx\n", (ulong)mcode_chksum); 4634 AscWriteLramWord(iop_base, ASCV_MCODE_CHKSUM_W, mcode_chksum); 4635 AscWriteLramWord(iop_base, ASCV_MCODE_SIZE_W, mcode_size); 4636 return chksum; 4637} 4638 4639static void AscInitQLinkVar(ASC_DVC_VAR *asc_dvc) 4640{ 4641 PortAddr iop_base; 4642 int i; 4643 ushort lram_addr; 4644 4645 iop_base = asc_dvc->iop_base; 4646 AscPutRiscVarFreeQHead(iop_base, 1); 4647 AscPutRiscVarDoneQTail(iop_base, asc_dvc->max_total_qng); 4648 AscPutVarFreeQHead(iop_base, 1); 4649 AscPutVarDoneQTail(iop_base, asc_dvc->max_total_qng); 4650 AscWriteLramByte(iop_base, ASCV_BUSY_QHEAD_B, 4651 (uchar)((int)asc_dvc->max_total_qng + 1)); 4652 AscWriteLramByte(iop_base, ASCV_DISC1_QHEAD_B, 4653 (uchar)((int)asc_dvc->max_total_qng + 2)); 4654 AscWriteLramByte(iop_base, (ushort)ASCV_TOTAL_READY_Q_B, 4655 asc_dvc->max_total_qng); 4656 AscWriteLramWord(iop_base, ASCV_ASCDVC_ERR_CODE_W, 0); 4657 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 4658 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 0); 4659 AscWriteLramByte(iop_base, ASCV_SCSIBUSY_B, 0); 4660 AscWriteLramByte(iop_base, ASCV_WTM_FLAG_B, 0); 4661 AscPutQDoneInProgress(iop_base, 0); 4662 lram_addr = ASC_QADR_BEG; 4663 for (i = 0; i < 32; i++, lram_addr += 2) { 4664 AscWriteLramWord(iop_base, lram_addr, 0); 4665 } 4666} 4667 4668static ushort AscInitMicroCodeVar(ASC_DVC_VAR *asc_dvc) 4669{ 4670 int i; 4671 ushort warn_code; 4672 PortAddr iop_base; 4673 ASC_PADDR phy_addr; 4674 ASC_DCNT phy_size; 4675 struct asc_board *board = asc_dvc_to_board(asc_dvc); 4676 4677 iop_base = asc_dvc->iop_base; 4678 warn_code = 0; 4679 for (i = 0; i <= ASC_MAX_TID; i++) { 4680 AscPutMCodeInitSDTRAtID(iop_base, i, 4681 asc_dvc->cfg->sdtr_period_offset[i]); 4682 } 4683 4684 AscInitQLinkVar(asc_dvc); 4685 AscWriteLramByte(iop_base, ASCV_DISC_ENABLE_B, 4686 asc_dvc->cfg->disc_enable); 4687 AscWriteLramByte(iop_base, ASCV_HOSTSCSI_ID_B, 4688 ASC_TID_TO_TARGET_ID(asc_dvc->cfg->chip_scsi_id)); 4689 4690 /* Ensure overrun buffer is aligned on an 8 byte boundary. */ 4691 BUG_ON((unsigned long)asc_dvc->overrun_buf & 7); 4692 asc_dvc->overrun_dma = dma_map_single(board->dev, asc_dvc->overrun_buf, 4693 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 4694 if (dma_mapping_error(board->dev, asc_dvc->overrun_dma)) { 4695 warn_code = -ENOMEM; 4696 goto err_dma_map; 4697 } 4698 phy_addr = cpu_to_le32(asc_dvc->overrun_dma); 4699 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_PADDR_D, 4700 (uchar *)&phy_addr, 1); 4701 phy_size = cpu_to_le32(ASC_OVERRUN_BSIZE); 4702 AscMemDWordCopyPtrToLram(iop_base, ASCV_OVERRUN_BSIZE_D, 4703 (uchar *)&phy_size, 1); 4704 4705 asc_dvc->cfg->mcode_date = 4706 AscReadLramWord(iop_base, (ushort)ASCV_MC_DATE_W); 4707 asc_dvc->cfg->mcode_version = 4708 AscReadLramWord(iop_base, (ushort)ASCV_MC_VER_W); 4709 4710 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR); 4711 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) { 4712 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR; 4713 warn_code = UW_ERR; 4714 goto err_mcode_start; 4715 } 4716 if (AscStartChip(iop_base) != 1) { 4717 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP; 4718 warn_code = UW_ERR; 4719 goto err_mcode_start; 4720 } 4721 4722 return warn_code; 4723 4724err_mcode_start: 4725 dma_unmap_single(board->dev, asc_dvc->overrun_dma, 4726 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 4727err_dma_map: 4728 asc_dvc->overrun_dma = 0; 4729 return warn_code; 4730} 4731 4732static ushort AscInitAsc1000Driver(ASC_DVC_VAR *asc_dvc) 4733{ 4734 const struct firmware *fw; 4735 const char fwname[] = "advansys/mcode.bin"; 4736 int err; 4737 unsigned long chksum; 4738 ushort warn_code; 4739 PortAddr iop_base; 4740 4741 iop_base = asc_dvc->iop_base; 4742 warn_code = 0; 4743 if ((asc_dvc->dvc_cntl & ASC_CNTL_RESET_SCSI) && 4744 !(asc_dvc->init_state & ASC_INIT_RESET_SCSI_DONE)) { 4745 AscResetChipAndScsiBus(asc_dvc); 4746 mdelay(asc_dvc->scsi_reset_wait * 1000); 4747 } 4748 asc_dvc->init_state |= ASC_INIT_STATE_BEG_LOAD_MC; 4749 if (asc_dvc->err_code != 0) 4750 return UW_ERR; 4751 if (!AscFindSignature(asc_dvc->iop_base)) { 4752 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 4753 return warn_code; 4754 } 4755 AscDisableInterrupt(iop_base); 4756 warn_code |= AscInitLram(asc_dvc); 4757 if (asc_dvc->err_code != 0) 4758 return UW_ERR; 4759 4760 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 4761 if (err) { 4762 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 4763 fwname, err); 4764 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; 4765 return err; 4766 } 4767 if (fw->size < 4) { 4768 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 4769 fw->size, fwname); 4770 release_firmware(fw); 4771 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; 4772 return -EINVAL; 4773 } 4774 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 4775 (fw->data[1] << 8) | fw->data[0]; 4776 ASC_DBG(1, "_asc_mcode_chksum 0x%lx\n", (ulong)chksum); 4777 if (AscLoadMicroCode(iop_base, 0, &fw->data[4], 4778 fw->size - 4) != chksum) { 4779 asc_dvc->err_code |= ASC_IERR_MCODE_CHKSUM; 4780 release_firmware(fw); 4781 return warn_code; 4782 } 4783 release_firmware(fw); 4784 warn_code |= AscInitMicroCodeVar(asc_dvc); 4785 if (!asc_dvc->overrun_dma) 4786 return warn_code; 4787 asc_dvc->init_state |= ASC_INIT_STATE_END_LOAD_MC; 4788 AscEnableInterrupt(iop_base); 4789 return warn_code; 4790} 4791 4792/* 4793 * Load the Microcode 4794 * 4795 * Write the microcode image to RISC memory starting at address 0. 4796 * 4797 * The microcode is stored compressed in the following format: 4798 * 4799 * 254 word (508 byte) table indexed by byte code followed 4800 * by the following byte codes: 4801 * 4802 * 1-Byte Code: 4803 * 00: Emit word 0 in table. 4804 * 01: Emit word 1 in table. 4805 * . 4806 * FD: Emit word 253 in table. 4807 * 4808 * Multi-Byte Code: 4809 * FE WW WW: (3 byte code) Word to emit is the next word WW WW. 4810 * FF BB WW WW: (4 byte code) Emit BB count times next word WW WW. 4811 * 4812 * Returns 0 or an error if the checksum doesn't match 4813 */ 4814static int AdvLoadMicrocode(AdvPortAddr iop_base, const unsigned char *buf, 4815 int size, int memsize, int chksum) 4816{ 4817 int i, j, end, len = 0; 4818 ADV_DCNT sum; 4819 4820 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0); 4821 4822 for (i = 253 * 2; i < size; i++) { 4823 if (buf[i] == 0xff) { 4824 unsigned short word = (buf[i + 3] << 8) | buf[i + 2]; 4825 for (j = 0; j < buf[i + 1]; j++) { 4826 AdvWriteWordAutoIncLram(iop_base, word); 4827 len += 2; 4828 } 4829 i += 3; 4830 } else if (buf[i] == 0xfe) { 4831 unsigned short word = (buf[i + 2] << 8) | buf[i + 1]; 4832 AdvWriteWordAutoIncLram(iop_base, word); 4833 i += 2; 4834 len += 2; 4835 } else { 4836 unsigned int off = buf[i] * 2; 4837 unsigned short word = (buf[off + 1] << 8) | buf[off]; 4838 AdvWriteWordAutoIncLram(iop_base, word); 4839 len += 2; 4840 } 4841 } 4842 4843 end = len; 4844 4845 while (len < memsize) { 4846 AdvWriteWordAutoIncLram(iop_base, 0); 4847 len += 2; 4848 } 4849 4850 /* Verify the microcode checksum. */ 4851 sum = 0; 4852 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, 0); 4853 4854 for (len = 0; len < end; len += 2) { 4855 sum += AdvReadWordAutoIncLram(iop_base); 4856 } 4857 4858 if (sum != chksum) 4859 return ASC_IERR_MCODE_CHKSUM; 4860 4861 return 0; 4862} 4863 4864static void AdvBuildCarrierFreelist(struct adv_dvc_var *asc_dvc) 4865{ 4866 ADV_CARR_T *carrp; 4867 ADV_SDCNT buf_size; 4868 ADV_PADDR carr_paddr; 4869 4870 carrp = (ADV_CARR_T *) ADV_16BALIGN(asc_dvc->carrier_buf); 4871 asc_dvc->carr_freelist = NULL; 4872 if (carrp == asc_dvc->carrier_buf) { 4873 buf_size = ADV_CARRIER_BUFSIZE; 4874 } else { 4875 buf_size = ADV_CARRIER_BUFSIZE - sizeof(ADV_CARR_T); 4876 } 4877 4878 do { 4879 /* Get physical address of the carrier 'carrp'. */ 4880 carr_paddr = cpu_to_le32(virt_to_bus(carrp)); 4881 4882 buf_size -= sizeof(ADV_CARR_T); 4883 4884 carrp->carr_pa = carr_paddr; 4885 carrp->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(carrp)); 4886 4887 /* 4888 * Insert the carrier at the beginning of the freelist. 4889 */ 4890 carrp->next_vpa = 4891 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist)); 4892 asc_dvc->carr_freelist = carrp; 4893 4894 carrp++; 4895 } while (buf_size > 0); 4896} 4897 4898/* 4899 * Send an idle command to the chip and wait for completion. 4900 * 4901 * Command completion is polled for once per microsecond. 4902 * 4903 * The function can be called from anywhere including an interrupt handler. 4904 * But the function is not re-entrant, so it uses the DvcEnter/LeaveCritical() 4905 * functions to prevent reentrancy. 4906 * 4907 * Return Values: 4908 * ADV_TRUE - command completed successfully 4909 * ADV_FALSE - command failed 4910 * ADV_ERROR - command timed out 4911 */ 4912static int 4913AdvSendIdleCmd(ADV_DVC_VAR *asc_dvc, 4914 ushort idle_cmd, ADV_DCNT idle_cmd_parameter) 4915{ 4916 int result; 4917 ADV_DCNT i, j; 4918 AdvPortAddr iop_base; 4919 4920 iop_base = asc_dvc->iop_base; 4921 4922 /* 4923 * Clear the idle command status which is set by the microcode 4924 * to a non-zero value to indicate when the command is completed. 4925 * The non-zero result is one of the IDLE_CMD_STATUS_* values 4926 */ 4927 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, (ushort)0); 4928 4929 /* 4930 * Write the idle command value after the idle command parameter 4931 * has been written to avoid a race condition. If the order is not 4932 * followed, the microcode may process the idle command before the 4933 * parameters have been written to LRAM. 4934 */ 4935 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IDLE_CMD_PARAMETER, 4936 cpu_to_le32(idle_cmd_parameter)); 4937 AdvWriteWordLram(iop_base, ASC_MC_IDLE_CMD, idle_cmd); 4938 4939 /* 4940 * Tickle the RISC to tell it to process the idle command. 4941 */ 4942 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_B); 4943 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { 4944 /* 4945 * Clear the tickle value. In the ASC-3550 the RISC flag 4946 * command 'clr_tickle_b' does not work unless the host 4947 * value is cleared. 4948 */ 4949 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_NOP); 4950 } 4951 4952 /* Wait for up to 100 millisecond for the idle command to timeout. */ 4953 for (i = 0; i < SCSI_WAIT_100_MSEC; i++) { 4954 /* Poll once each microsecond for command completion. */ 4955 for (j = 0; j < SCSI_US_PER_MSEC; j++) { 4956 AdvReadWordLram(iop_base, ASC_MC_IDLE_CMD_STATUS, 4957 result); 4958 if (result != 0) 4959 return result; 4960 udelay(1); 4961 } 4962 } 4963 4964 BUG(); /* The idle command should never timeout. */ 4965 return ADV_ERROR; 4966} 4967 4968/* 4969 * Reset SCSI Bus and purge all outstanding requests. 4970 * 4971 * Return Value: 4972 * ADV_TRUE(1) - All requests are purged and SCSI Bus is reset. 4973 * ADV_FALSE(0) - Microcode command failed. 4974 * ADV_ERROR(-1) - Microcode command timed-out. Microcode or IC 4975 * may be hung which requires driver recovery. 4976 */ 4977static int AdvResetSB(ADV_DVC_VAR *asc_dvc) 4978{ 4979 int status; 4980 4981 /* 4982 * Send the SCSI Bus Reset idle start idle command which asserts 4983 * the SCSI Bus Reset signal. 4984 */ 4985 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_START, 0L); 4986 if (status != ADV_TRUE) { 4987 return status; 4988 } 4989 4990 /* 4991 * Delay for the specified SCSI Bus Reset hold time. 4992 * 4993 * The hold time delay is done on the host because the RISC has no 4994 * microsecond accurate timer. 4995 */ 4996 udelay(ASC_SCSI_RESET_HOLD_TIME_US); 4997 4998 /* 4999 * Send the SCSI Bus Reset end idle command which de-asserts 5000 * the SCSI Bus Reset signal and purges any pending requests. 5001 */ 5002 status = AdvSendIdleCmd(asc_dvc, (ushort)IDLE_CMD_SCSI_RESET_END, 0L); 5003 if (status != ADV_TRUE) { 5004 return status; 5005 } 5006 5007 mdelay(asc_dvc->scsi_reset_wait * 1000); 5008 5009 return status; 5010} 5011 5012/* 5013 * Initialize the ASC-3550. 5014 * 5015 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 5016 * 5017 * For a non-fatal error return a warning code. If there are no warnings 5018 * then 0 is returned. 5019 * 5020 * Needed after initialization for error recovery. 5021 */ 5022static int AdvInitAsc3550Driver(ADV_DVC_VAR *asc_dvc) 5023{ 5024 const struct firmware *fw; 5025 const char fwname[] = "advansys/3550.bin"; 5026 AdvPortAddr iop_base; 5027 ushort warn_code; 5028 int begin_addr; 5029 int end_addr; 5030 ushort code_sum; 5031 int word; 5032 int i; 5033 int err; 5034 unsigned long chksum; 5035 ushort scsi_cfg1; 5036 uchar tid; 5037 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ 5038 ushort wdtr_able = 0, sdtr_able, tagqng_able; 5039 uchar max_cmd[ADV_MAX_TID + 1]; 5040 5041 /* If there is already an error, don't continue. */ 5042 if (asc_dvc->err_code != 0) 5043 return ADV_ERROR; 5044 5045 /* 5046 * The caller must set 'chip_type' to ADV_CHIP_ASC3550. 5047 */ 5048 if (asc_dvc->chip_type != ADV_CHIP_ASC3550) { 5049 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; 5050 return ADV_ERROR; 5051 } 5052 5053 warn_code = 0; 5054 iop_base = asc_dvc->iop_base; 5055 5056 /* 5057 * Save the RISC memory BIOS region before writing the microcode. 5058 * The BIOS may already be loaded and using its RISC LRAM region 5059 * so its region must be saved and restored. 5060 * 5061 * Note: This code makes the assumption, which is currently true, 5062 * that a chip reset does not clear RISC LRAM. 5063 */ 5064 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 5065 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 5066 bios_mem[i]); 5067 } 5068 5069 /* 5070 * Save current per TID negotiated values. 5071 */ 5072 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 0x55AA) { 5073 ushort bios_version, major, minor; 5074 5075 bios_version = 5076 bios_mem[(ASC_MC_BIOS_VERSION - ASC_MC_BIOSMEM) / 2]; 5077 major = (bios_version >> 12) & 0xF; 5078 minor = (bios_version >> 8) & 0xF; 5079 if (major < 3 || (major == 3 && minor == 1)) { 5080 /* BIOS 3.1 and earlier location of 'wdtr_able' variable. */ 5081 AdvReadWordLram(iop_base, 0x120, wdtr_able); 5082 } else { 5083 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5084 } 5085 } 5086 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5087 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 5088 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5089 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 5090 max_cmd[tid]); 5091 } 5092 5093 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 5094 if (err) { 5095 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 5096 fwname, err); 5097 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 5098 return err; 5099 } 5100 if (fw->size < 4) { 5101 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 5102 fw->size, fwname); 5103 release_firmware(fw); 5104 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 5105 return -EINVAL; 5106 } 5107 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 5108 (fw->data[1] << 8) | fw->data[0]; 5109 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4], 5110 fw->size - 4, ADV_3550_MEMSIZE, 5111 chksum); 5112 release_firmware(fw); 5113 if (asc_dvc->err_code) 5114 return ADV_ERROR; 5115 5116 /* 5117 * Restore the RISC memory BIOS region. 5118 */ 5119 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 5120 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 5121 bios_mem[i]); 5122 } 5123 5124 /* 5125 * Calculate and write the microcode code checksum to the microcode 5126 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 5127 */ 5128 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 5129 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); 5130 code_sum = 0; 5131 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); 5132 for (word = begin_addr; word < end_addr; word += 2) { 5133 code_sum += AdvReadWordAutoIncLram(iop_base); 5134 } 5135 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); 5136 5137 /* 5138 * Read and save microcode version and date. 5139 */ 5140 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, 5141 asc_dvc->cfg->mcode_date); 5142 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, 5143 asc_dvc->cfg->mcode_version); 5144 5145 /* 5146 * Set the chip type to indicate the ASC3550. 5147 */ 5148 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC3550); 5149 5150 /* 5151 * If the PCI Configuration Command Register "Parity Error Response 5152 * Control" Bit was clear (0), then set the microcode variable 5153 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 5154 * to ignore DMA parity errors. 5155 */ 5156 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { 5157 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5158 word |= CONTROL_FLAG_IGNORE_PERR; 5159 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5160 } 5161 5162 /* 5163 * For ASC-3550, setting the START_CTL_EMFU [3:2] bits sets a FIFO 5164 * threshold of 128 bytes. This register is only accessible to the host. 5165 */ 5166 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, 5167 START_CTL_EMFU | READ_CMD_MRM); 5168 5169 /* 5170 * Microcode operating variables for WDTR, SDTR, and command tag 5171 * queuing will be set in slave_configure() based on what a 5172 * device reports it is capable of in Inquiry byte 7. 5173 * 5174 * If SCSI Bus Resets have been disabled, then directly set 5175 * SDTR and WDTR from the EEPROM configuration. This will allow 5176 * the BIOS and warm boot to work without a SCSI bus hang on 5177 * the Inquiry caused by host and target mismatched DTR values. 5178 * Without the SCSI Bus Reset, before an Inquiry a device can't 5179 * be assumed to be in Asynchronous, Narrow mode. 5180 */ 5181 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 5182 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, 5183 asc_dvc->wdtr_able); 5184 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, 5185 asc_dvc->sdtr_able); 5186 } 5187 5188 /* 5189 * Set microcode operating variables for SDTR_SPEED1, SDTR_SPEED2, 5190 * SDTR_SPEED3, and SDTR_SPEED4 based on the ULTRA EEPROM per TID 5191 * bitmask. These values determine the maximum SDTR speed negotiated 5192 * with a device. 5193 * 5194 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 5195 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 5196 * without determining here whether the device supports SDTR. 5197 * 5198 * 4-bit speed SDTR speed name 5199 * =========== =============== 5200 * 0000b (0x0) SDTR disabled 5201 * 0001b (0x1) 5 Mhz 5202 * 0010b (0x2) 10 Mhz 5203 * 0011b (0x3) 20 Mhz (Ultra) 5204 * 0100b (0x4) 40 Mhz (LVD/Ultra2) 5205 * 0101b (0x5) 80 Mhz (LVD2/Ultra3) 5206 * 0110b (0x6) Undefined 5207 * . 5208 * 1111b (0xF) Undefined 5209 */ 5210 word = 0; 5211 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5212 if (ADV_TID_TO_TIDMASK(tid) & asc_dvc->ultra_able) { 5213 /* Set Ultra speed for TID 'tid'. */ 5214 word |= (0x3 << (4 * (tid % 4))); 5215 } else { 5216 /* Set Fast speed for TID 'tid'. */ 5217 word |= (0x2 << (4 * (tid % 4))); 5218 } 5219 if (tid == 3) { /* Check if done with sdtr_speed1. */ 5220 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, word); 5221 word = 0; 5222 } else if (tid == 7) { /* Check if done with sdtr_speed2. */ 5223 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, word); 5224 word = 0; 5225 } else if (tid == 11) { /* Check if done with sdtr_speed3. */ 5226 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, word); 5227 word = 0; 5228 } else if (tid == 15) { /* Check if done with sdtr_speed4. */ 5229 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, word); 5230 /* End of loop. */ 5231 } 5232 } 5233 5234 /* 5235 * Set microcode operating variable for the disconnect per TID bitmask. 5236 */ 5237 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, 5238 asc_dvc->cfg->disc_enable); 5239 5240 /* 5241 * Set SCSI_CFG0 Microcode Default Value. 5242 * 5243 * The microcode will set the SCSI_CFG0 register using this value 5244 * after it is started below. 5245 */ 5246 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, 5247 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | 5248 asc_dvc->chip_scsi_id); 5249 5250 /* 5251 * Determine SCSI_CFG1 Microcode Default Value. 5252 * 5253 * The microcode will set the SCSI_CFG1 register using this value 5254 * after it is started below. 5255 */ 5256 5257 /* Read current SCSI_CFG1 Register value. */ 5258 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 5259 5260 /* 5261 * If all three connectors are in use, return an error. 5262 */ 5263 if ((scsi_cfg1 & CABLE_ILLEGAL_A) == 0 || 5264 (scsi_cfg1 & CABLE_ILLEGAL_B) == 0) { 5265 asc_dvc->err_code |= ASC_IERR_ILLEGAL_CONNECTION; 5266 return ADV_ERROR; 5267 } 5268 5269 /* 5270 * If the internal narrow cable is reversed all of the SCSI_CTRL 5271 * register signals will be set. Check for and return an error if 5272 * this condition is found. 5273 */ 5274 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 5275 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; 5276 return ADV_ERROR; 5277 } 5278 5279 /* 5280 * If this is a differential board and a single-ended device 5281 * is attached to one of the connectors, return an error. 5282 */ 5283 if ((scsi_cfg1 & DIFF_MODE) && (scsi_cfg1 & DIFF_SENSE) == 0) { 5284 asc_dvc->err_code |= ASC_IERR_SINGLE_END_DEVICE; 5285 return ADV_ERROR; 5286 } 5287 5288 /* 5289 * If automatic termination control is enabled, then set the 5290 * termination value based on a table listed in a_condor.h. 5291 * 5292 * If manual termination was specified with an EEPROM setting 5293 * then 'termination' was set-up in AdvInitFrom3550EEPROM() and 5294 * is ready to be 'ored' into SCSI_CFG1. 5295 */ 5296 if (asc_dvc->cfg->termination == 0) { 5297 /* 5298 * The software always controls termination by setting TERM_CTL_SEL. 5299 * If TERM_CTL_SEL were set to 0, the hardware would set termination. 5300 */ 5301 asc_dvc->cfg->termination |= TERM_CTL_SEL; 5302 5303 switch (scsi_cfg1 & CABLE_DETECT) { 5304 /* TERM_CTL_H: on, TERM_CTL_L: on */ 5305 case 0x3: 5306 case 0x7: 5307 case 0xB: 5308 case 0xD: 5309 case 0xE: 5310 case 0xF: 5311 asc_dvc->cfg->termination |= (TERM_CTL_H | TERM_CTL_L); 5312 break; 5313 5314 /* TERM_CTL_H: on, TERM_CTL_L: off */ 5315 case 0x1: 5316 case 0x5: 5317 case 0x9: 5318 case 0xA: 5319 case 0xC: 5320 asc_dvc->cfg->termination |= TERM_CTL_H; 5321 break; 5322 5323 /* TERM_CTL_H: off, TERM_CTL_L: off */ 5324 case 0x2: 5325 case 0x6: 5326 break; 5327 } 5328 } 5329 5330 /* 5331 * Clear any set TERM_CTL_H and TERM_CTL_L bits. 5332 */ 5333 scsi_cfg1 &= ~TERM_CTL; 5334 5335 /* 5336 * Invert the TERM_CTL_H and TERM_CTL_L bits and then 5337 * set 'scsi_cfg1'. The TERM_POL bit does not need to be 5338 * referenced, because the hardware internally inverts 5339 * the Termination High and Low bits if TERM_POL is set. 5340 */ 5341 scsi_cfg1 |= (TERM_CTL_SEL | (~asc_dvc->cfg->termination & TERM_CTL)); 5342 5343 /* 5344 * Set SCSI_CFG1 Microcode Default Value 5345 * 5346 * Set filter value and possibly modified termination control 5347 * bits in the Microcode SCSI_CFG1 Register Value. 5348 * 5349 * The microcode will set the SCSI_CFG1 register using this value 5350 * after it is started below. 5351 */ 5352 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, 5353 FLTR_DISABLE | scsi_cfg1); 5354 5355 /* 5356 * Set MEM_CFG Microcode Default Value 5357 * 5358 * The microcode will set the MEM_CFG register using this value 5359 * after it is started below. 5360 * 5361 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 5362 * are defined. 5363 * 5364 * ASC-3550 has 8KB internal memory. 5365 */ 5366 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 5367 BIOS_EN | RAM_SZ_8KB); 5368 5369 /* 5370 * Set SEL_MASK Microcode Default Value 5371 * 5372 * The microcode will set the SEL_MASK register using this value 5373 * after it is started below. 5374 */ 5375 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, 5376 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); 5377 5378 AdvBuildCarrierFreelist(asc_dvc); 5379 5380 /* 5381 * Set-up the Host->RISC Initiator Command Queue (ICQ). 5382 */ 5383 5384 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) { 5385 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5386 return ADV_ERROR; 5387 } 5388 asc_dvc->carr_freelist = (ADV_CARR_T *) 5389 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa)); 5390 5391 /* 5392 * The first command issued will be placed in the stopper carrier. 5393 */ 5394 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); 5395 5396 /* 5397 * Set RISC ICQ physical address start value. 5398 */ 5399 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); 5400 5401 /* 5402 * Set-up the RISC->Host Initiator Response Queue (IRQ). 5403 */ 5404 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) { 5405 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5406 return ADV_ERROR; 5407 } 5408 asc_dvc->carr_freelist = (ADV_CARR_T *) 5409 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa)); 5410 5411 /* 5412 * The first command completed by the RISC will be placed in 5413 * the stopper. 5414 * 5415 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is 5416 * completed the RISC will set the ASC_RQ_STOPPER bit. 5417 */ 5418 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); 5419 5420 /* 5421 * Set RISC IRQ physical address start value. 5422 */ 5423 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); 5424 asc_dvc->carr_pending_cnt = 0; 5425 5426 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, 5427 (ADV_INTR_ENABLE_HOST_INTR | 5428 ADV_INTR_ENABLE_GLOBAL_INTR)); 5429 5430 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); 5431 AdvWriteWordRegister(iop_base, IOPW_PC, word); 5432 5433 /* finally, finally, gentlemen, start your engine */ 5434 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); 5435 5436 /* 5437 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 5438 * Resets should be performed. The RISC has to be running 5439 * to issue a SCSI Bus Reset. 5440 */ 5441 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 5442 /* 5443 * If the BIOS Signature is present in memory, restore the 5444 * BIOS Handshake Configuration Table and do not perform 5445 * a SCSI Bus Reset. 5446 */ 5447 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 5448 0x55AA) { 5449 /* 5450 * Restore per TID negotiated values. 5451 */ 5452 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5453 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5454 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 5455 tagqng_able); 5456 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5457 AdvWriteByteLram(iop_base, 5458 ASC_MC_NUMBER_OF_MAX_CMD + tid, 5459 max_cmd[tid]); 5460 } 5461 } else { 5462 if (AdvResetSB(asc_dvc) != ADV_TRUE) { 5463 warn_code = ASC_WARN_BUSRESET_ERROR; 5464 } 5465 } 5466 } 5467 5468 return warn_code; 5469} 5470 5471/* 5472 * Initialize the ASC-38C0800. 5473 * 5474 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 5475 * 5476 * For a non-fatal error return a warning code. If there are no warnings 5477 * then 0 is returned. 5478 * 5479 * Needed after initialization for error recovery. 5480 */ 5481static int AdvInitAsc38C0800Driver(ADV_DVC_VAR *asc_dvc) 5482{ 5483 const struct firmware *fw; 5484 const char fwname[] = "advansys/38C0800.bin"; 5485 AdvPortAddr iop_base; 5486 ushort warn_code; 5487 int begin_addr; 5488 int end_addr; 5489 ushort code_sum; 5490 int word; 5491 int i; 5492 int err; 5493 unsigned long chksum; 5494 ushort scsi_cfg1; 5495 uchar byte; 5496 uchar tid; 5497 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ 5498 ushort wdtr_able, sdtr_able, tagqng_able; 5499 uchar max_cmd[ADV_MAX_TID + 1]; 5500 5501 /* If there is already an error, don't continue. */ 5502 if (asc_dvc->err_code != 0) 5503 return ADV_ERROR; 5504 5505 /* 5506 * The caller must set 'chip_type' to ADV_CHIP_ASC38C0800. 5507 */ 5508 if (asc_dvc->chip_type != ADV_CHIP_ASC38C0800) { 5509 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; 5510 return ADV_ERROR; 5511 } 5512 5513 warn_code = 0; 5514 iop_base = asc_dvc->iop_base; 5515 5516 /* 5517 * Save the RISC memory BIOS region before writing the microcode. 5518 * The BIOS may already be loaded and using its RISC LRAM region 5519 * so its region must be saved and restored. 5520 * 5521 * Note: This code makes the assumption, which is currently true, 5522 * that a chip reset does not clear RISC LRAM. 5523 */ 5524 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 5525 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 5526 bios_mem[i]); 5527 } 5528 5529 /* 5530 * Save current per TID negotiated values. 5531 */ 5532 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5533 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5534 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 5535 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5536 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 5537 max_cmd[tid]); 5538 } 5539 5540 /* 5541 * RAM BIST (RAM Built-In Self Test) 5542 * 5543 * Address : I/O base + offset 0x38h register (byte). 5544 * Function: Bit 7-6(RW) : RAM mode 5545 * Normal Mode : 0x00 5546 * Pre-test Mode : 0x40 5547 * RAM Test Mode : 0x80 5548 * Bit 5 : unused 5549 * Bit 4(RO) : Done bit 5550 * Bit 3-0(RO) : Status 5551 * Host Error : 0x08 5552 * Int_RAM Error : 0x04 5553 * RISC Error : 0x02 5554 * SCSI Error : 0x01 5555 * No Error : 0x00 5556 * 5557 * Note: RAM BIST code should be put right here, before loading the 5558 * microcode and after saving the RISC memory BIOS region. 5559 */ 5560 5561 /* 5562 * LRAM Pre-test 5563 * 5564 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 5565 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 5566 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 5567 * to NORMAL_MODE, return an error too. 5568 */ 5569 for (i = 0; i < 2; i++) { 5570 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); 5571 mdelay(10); /* Wait for 10ms before reading back. */ 5572 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 5573 if ((byte & RAM_TEST_DONE) == 0 5574 || (byte & 0x0F) != PRE_TEST_VALUE) { 5575 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 5576 return ADV_ERROR; 5577 } 5578 5579 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 5580 mdelay(10); /* Wait for 10ms before reading back. */ 5581 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) 5582 != NORMAL_VALUE) { 5583 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 5584 return ADV_ERROR; 5585 } 5586 } 5587 5588 /* 5589 * LRAM Test - It takes about 1.5 ms to run through the test. 5590 * 5591 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 5592 * If Done bit not set or Status not 0, save register byte, set the 5593 * err_code, and return an error. 5594 */ 5595 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); 5596 mdelay(10); /* Wait for 10ms before checking status. */ 5597 5598 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 5599 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 5600 /* Get here if Done bit not set or Status not 0. */ 5601 asc_dvc->bist_err_code = byte; /* for BIOS display message */ 5602 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST; 5603 return ADV_ERROR; 5604 } 5605 5606 /* We need to reset back to normal mode after LRAM test passes. */ 5607 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 5608 5609 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 5610 if (err) { 5611 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 5612 fwname, err); 5613 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 5614 return err; 5615 } 5616 if (fw->size < 4) { 5617 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 5618 fw->size, fwname); 5619 release_firmware(fw); 5620 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 5621 return -EINVAL; 5622 } 5623 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 5624 (fw->data[1] << 8) | fw->data[0]; 5625 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4], 5626 fw->size - 4, ADV_38C0800_MEMSIZE, 5627 chksum); 5628 release_firmware(fw); 5629 if (asc_dvc->err_code) 5630 return ADV_ERROR; 5631 5632 /* 5633 * Restore the RISC memory BIOS region. 5634 */ 5635 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 5636 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 5637 bios_mem[i]); 5638 } 5639 5640 /* 5641 * Calculate and write the microcode code checksum to the microcode 5642 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 5643 */ 5644 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 5645 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); 5646 code_sum = 0; 5647 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); 5648 for (word = begin_addr; word < end_addr; word += 2) { 5649 code_sum += AdvReadWordAutoIncLram(iop_base); 5650 } 5651 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); 5652 5653 /* 5654 * Read microcode version and date. 5655 */ 5656 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, 5657 asc_dvc->cfg->mcode_date); 5658 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, 5659 asc_dvc->cfg->mcode_version); 5660 5661 /* 5662 * Set the chip type to indicate the ASC38C0800. 5663 */ 5664 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C0800); 5665 5666 /* 5667 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 5668 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 5669 * cable detection and then we are able to read C_DET[3:0]. 5670 * 5671 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 5672 * Microcode Default Value' section below. 5673 */ 5674 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 5675 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, 5676 scsi_cfg1 | DIS_TERM_DRV); 5677 5678 /* 5679 * If the PCI Configuration Command Register "Parity Error Response 5680 * Control" Bit was clear (0), then set the microcode variable 5681 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 5682 * to ignore DMA parity errors. 5683 */ 5684 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { 5685 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5686 word |= CONTROL_FLAG_IGNORE_PERR; 5687 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 5688 } 5689 5690 /* 5691 * For ASC-38C0800, set FIFO_THRESH_80B [6:4] bits and START_CTL_TH [3:2] 5692 * bits for the default FIFO threshold. 5693 * 5694 * Note: ASC-38C0800 FIFO threshold has been changed to 256 bytes. 5695 * 5696 * For DMA Errata #4 set the BC_THRESH_ENB bit. 5697 */ 5698 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, 5699 BC_THRESH_ENB | FIFO_THRESH_80B | START_CTL_TH | 5700 READ_CMD_MRM); 5701 5702 /* 5703 * Microcode operating variables for WDTR, SDTR, and command tag 5704 * queuing will be set in slave_configure() based on what a 5705 * device reports it is capable of in Inquiry byte 7. 5706 * 5707 * If SCSI Bus Resets have been disabled, then directly set 5708 * SDTR and WDTR from the EEPROM configuration. This will allow 5709 * the BIOS and warm boot to work without a SCSI bus hang on 5710 * the Inquiry caused by host and target mismatched DTR values. 5711 * Without the SCSI Bus Reset, before an Inquiry a device can't 5712 * be assumed to be in Asynchronous, Narrow mode. 5713 */ 5714 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 5715 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, 5716 asc_dvc->wdtr_able); 5717 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, 5718 asc_dvc->sdtr_able); 5719 } 5720 5721 /* 5722 * Set microcode operating variables for DISC and SDTR_SPEED1, 5723 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 5724 * configuration values. 5725 * 5726 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 5727 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 5728 * without determining here whether the device supports SDTR. 5729 */ 5730 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, 5731 asc_dvc->cfg->disc_enable); 5732 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1); 5733 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2); 5734 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3); 5735 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4); 5736 5737 /* 5738 * Set SCSI_CFG0 Microcode Default Value. 5739 * 5740 * The microcode will set the SCSI_CFG0 register using this value 5741 * after it is started below. 5742 */ 5743 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, 5744 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | 5745 asc_dvc->chip_scsi_id); 5746 5747 /* 5748 * Determine SCSI_CFG1 Microcode Default Value. 5749 * 5750 * The microcode will set the SCSI_CFG1 register using this value 5751 * after it is started below. 5752 */ 5753 5754 /* Read current SCSI_CFG1 Register value. */ 5755 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 5756 5757 /* 5758 * If the internal narrow cable is reversed all of the SCSI_CTRL 5759 * register signals will be set. Check for and return an error if 5760 * this condition is found. 5761 */ 5762 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 5763 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; 5764 return ADV_ERROR; 5765 } 5766 5767 /* 5768 * All kind of combinations of devices attached to one of four 5769 * connectors are acceptable except HVD device attached. For example, 5770 * LVD device can be attached to SE connector while SE device attached 5771 * to LVD connector. If LVD device attached to SE connector, it only 5772 * runs up to Ultra speed. 5773 * 5774 * If an HVD device is attached to one of LVD connectors, return an 5775 * error. However, there is no way to detect HVD device attached to 5776 * SE connectors. 5777 */ 5778 if (scsi_cfg1 & HVD) { 5779 asc_dvc->err_code = ASC_IERR_HVD_DEVICE; 5780 return ADV_ERROR; 5781 } 5782 5783 /* 5784 * If either SE or LVD automatic termination control is enabled, then 5785 * set the termination value based on a table listed in a_condor.h. 5786 * 5787 * If manual termination was specified with an EEPROM setting then 5788 * 'termination' was set-up in AdvInitFrom38C0800EEPROM() and is ready 5789 * to be 'ored' into SCSI_CFG1. 5790 */ 5791 if ((asc_dvc->cfg->termination & TERM_SE) == 0) { 5792 /* SE automatic termination control is enabled. */ 5793 switch (scsi_cfg1 & C_DET_SE) { 5794 /* TERM_SE_HI: on, TERM_SE_LO: on */ 5795 case 0x1: 5796 case 0x2: 5797 case 0x3: 5798 asc_dvc->cfg->termination |= TERM_SE; 5799 break; 5800 5801 /* TERM_SE_HI: on, TERM_SE_LO: off */ 5802 case 0x0: 5803 asc_dvc->cfg->termination |= TERM_SE_HI; 5804 break; 5805 } 5806 } 5807 5808 if ((asc_dvc->cfg->termination & TERM_LVD) == 0) { 5809 /* LVD automatic termination control is enabled. */ 5810 switch (scsi_cfg1 & C_DET_LVD) { 5811 /* TERM_LVD_HI: on, TERM_LVD_LO: on */ 5812 case 0x4: 5813 case 0x8: 5814 case 0xC: 5815 asc_dvc->cfg->termination |= TERM_LVD; 5816 break; 5817 5818 /* TERM_LVD_HI: off, TERM_LVD_LO: off */ 5819 case 0x0: 5820 break; 5821 } 5822 } 5823 5824 /* 5825 * Clear any set TERM_SE and TERM_LVD bits. 5826 */ 5827 scsi_cfg1 &= (~TERM_SE & ~TERM_LVD); 5828 5829 /* 5830 * Invert the TERM_SE and TERM_LVD bits and then set 'scsi_cfg1'. 5831 */ 5832 scsi_cfg1 |= (~asc_dvc->cfg->termination & 0xF0); 5833 5834 /* 5835 * Clear BIG_ENDIAN, DIS_TERM_DRV, Terminator Polarity and HVD/LVD/SE 5836 * bits and set possibly modified termination control bits in the 5837 * Microcode SCSI_CFG1 Register Value. 5838 */ 5839 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL & ~HVD_LVD_SE); 5840 5841 /* 5842 * Set SCSI_CFG1 Microcode Default Value 5843 * 5844 * Set possibly modified termination control and reset DIS_TERM_DRV 5845 * bits in the Microcode SCSI_CFG1 Register Value. 5846 * 5847 * The microcode will set the SCSI_CFG1 register using this value 5848 * after it is started below. 5849 */ 5850 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 5851 5852 /* 5853 * Set MEM_CFG Microcode Default Value 5854 * 5855 * The microcode will set the MEM_CFG register using this value 5856 * after it is started below. 5857 * 5858 * MEM_CFG may be accessed as a word or byte, but only bits 0-7 5859 * are defined. 5860 * 5861 * ASC-38C0800 has 16KB internal memory. 5862 */ 5863 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 5864 BIOS_EN | RAM_SZ_16KB); 5865 5866 /* 5867 * Set SEL_MASK Microcode Default Value 5868 * 5869 * The microcode will set the SEL_MASK register using this value 5870 * after it is started below. 5871 */ 5872 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, 5873 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); 5874 5875 AdvBuildCarrierFreelist(asc_dvc); 5876 5877 /* 5878 * Set-up the Host->RISC Initiator Command Queue (ICQ). 5879 */ 5880 5881 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) { 5882 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5883 return ADV_ERROR; 5884 } 5885 asc_dvc->carr_freelist = (ADV_CARR_T *) 5886 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa)); 5887 5888 /* 5889 * The first command issued will be placed in the stopper carrier. 5890 */ 5891 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); 5892 5893 /* 5894 * Set RISC ICQ physical address start value. 5895 * carr_pa is LE, must be native before write 5896 */ 5897 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); 5898 5899 /* 5900 * Set-up the RISC->Host Initiator Response Queue (IRQ). 5901 */ 5902 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) { 5903 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 5904 return ADV_ERROR; 5905 } 5906 asc_dvc->carr_freelist = (ADV_CARR_T *) 5907 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa)); 5908 5909 /* 5910 * The first command completed by the RISC will be placed in 5911 * the stopper. 5912 * 5913 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is 5914 * completed the RISC will set the ASC_RQ_STOPPER bit. 5915 */ 5916 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); 5917 5918 /* 5919 * Set RISC IRQ physical address start value. 5920 * 5921 * carr_pa is LE, must be native before write * 5922 */ 5923 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); 5924 asc_dvc->carr_pending_cnt = 0; 5925 5926 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, 5927 (ADV_INTR_ENABLE_HOST_INTR | 5928 ADV_INTR_ENABLE_GLOBAL_INTR)); 5929 5930 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); 5931 AdvWriteWordRegister(iop_base, IOPW_PC, word); 5932 5933 /* finally, finally, gentlemen, start your engine */ 5934 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); 5935 5936 /* 5937 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 5938 * Resets should be performed. The RISC has to be running 5939 * to issue a SCSI Bus Reset. 5940 */ 5941 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 5942 /* 5943 * If the BIOS Signature is present in memory, restore the 5944 * BIOS Handshake Configuration Table and do not perform 5945 * a SCSI Bus Reset. 5946 */ 5947 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 5948 0x55AA) { 5949 /* 5950 * Restore per TID negotiated values. 5951 */ 5952 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 5953 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 5954 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 5955 tagqng_able); 5956 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 5957 AdvWriteByteLram(iop_base, 5958 ASC_MC_NUMBER_OF_MAX_CMD + tid, 5959 max_cmd[tid]); 5960 } 5961 } else { 5962 if (AdvResetSB(asc_dvc) != ADV_TRUE) { 5963 warn_code = ASC_WARN_BUSRESET_ERROR; 5964 } 5965 } 5966 } 5967 5968 return warn_code; 5969} 5970 5971/* 5972 * Initialize the ASC-38C1600. 5973 * 5974 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 5975 * 5976 * For a non-fatal error return a warning code. If there are no warnings 5977 * then 0 is returned. 5978 * 5979 * Needed after initialization for error recovery. 5980 */ 5981static int AdvInitAsc38C1600Driver(ADV_DVC_VAR *asc_dvc) 5982{ 5983 const struct firmware *fw; 5984 const char fwname[] = "advansys/38C1600.bin"; 5985 AdvPortAddr iop_base; 5986 ushort warn_code; 5987 int begin_addr; 5988 int end_addr; 5989 ushort code_sum; 5990 long word; 5991 int i; 5992 int err; 5993 unsigned long chksum; 5994 ushort scsi_cfg1; 5995 uchar byte; 5996 uchar tid; 5997 ushort bios_mem[ASC_MC_BIOSLEN / 2]; /* BIOS RISC Memory 0x40-0x8F. */ 5998 ushort wdtr_able, sdtr_able, ppr_able, tagqng_able; 5999 uchar max_cmd[ASC_MAX_TID + 1]; 6000 6001 /* If there is already an error, don't continue. */ 6002 if (asc_dvc->err_code != 0) { 6003 return ADV_ERROR; 6004 } 6005 6006 /* 6007 * The caller must set 'chip_type' to ADV_CHIP_ASC38C1600. 6008 */ 6009 if (asc_dvc->chip_type != ADV_CHIP_ASC38C1600) { 6010 asc_dvc->err_code = ASC_IERR_BAD_CHIPTYPE; 6011 return ADV_ERROR; 6012 } 6013 6014 warn_code = 0; 6015 iop_base = asc_dvc->iop_base; 6016 6017 /* 6018 * Save the RISC memory BIOS region before writing the microcode. 6019 * The BIOS may already be loaded and using its RISC LRAM region 6020 * so its region must be saved and restored. 6021 * 6022 * Note: This code makes the assumption, which is currently true, 6023 * that a chip reset does not clear RISC LRAM. 6024 */ 6025 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 6026 AdvReadWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 6027 bios_mem[i]); 6028 } 6029 6030 /* 6031 * Save current per TID negotiated values. 6032 */ 6033 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 6034 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 6035 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 6036 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 6037 for (tid = 0; tid <= ASC_MAX_TID; tid++) { 6038 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 6039 max_cmd[tid]); 6040 } 6041 6042 /* 6043 * RAM BIST (Built-In Self Test) 6044 * 6045 * Address : I/O base + offset 0x38h register (byte). 6046 * Function: Bit 7-6(RW) : RAM mode 6047 * Normal Mode : 0x00 6048 * Pre-test Mode : 0x40 6049 * RAM Test Mode : 0x80 6050 * Bit 5 : unused 6051 * Bit 4(RO) : Done bit 6052 * Bit 3-0(RO) : Status 6053 * Host Error : 0x08 6054 * Int_RAM Error : 0x04 6055 * RISC Error : 0x02 6056 * SCSI Error : 0x01 6057 * No Error : 0x00 6058 * 6059 * Note: RAM BIST code should be put right here, before loading the 6060 * microcode and after saving the RISC memory BIOS region. 6061 */ 6062 6063 /* 6064 * LRAM Pre-test 6065 * 6066 * Write PRE_TEST_MODE (0x40) to register and wait for 10 milliseconds. 6067 * If Done bit not set or low nibble not PRE_TEST_VALUE (0x05), return 6068 * an error. Reset to NORMAL_MODE (0x00) and do again. If cannot reset 6069 * to NORMAL_MODE, return an error too. 6070 */ 6071 for (i = 0; i < 2; i++) { 6072 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, PRE_TEST_MODE); 6073 mdelay(10); /* Wait for 10ms before reading back. */ 6074 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 6075 if ((byte & RAM_TEST_DONE) == 0 6076 || (byte & 0x0F) != PRE_TEST_VALUE) { 6077 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 6078 return ADV_ERROR; 6079 } 6080 6081 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 6082 mdelay(10); /* Wait for 10ms before reading back. */ 6083 if (AdvReadByteRegister(iop_base, IOPB_RAM_BIST) 6084 != NORMAL_VALUE) { 6085 asc_dvc->err_code = ASC_IERR_BIST_PRE_TEST; 6086 return ADV_ERROR; 6087 } 6088 } 6089 6090 /* 6091 * LRAM Test - It takes about 1.5 ms to run through the test. 6092 * 6093 * Write RAM_TEST_MODE (0x80) to register and wait for 10 milliseconds. 6094 * If Done bit not set or Status not 0, save register byte, set the 6095 * err_code, and return an error. 6096 */ 6097 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, RAM_TEST_MODE); 6098 mdelay(10); /* Wait for 10ms before checking status. */ 6099 6100 byte = AdvReadByteRegister(iop_base, IOPB_RAM_BIST); 6101 if ((byte & RAM_TEST_DONE) == 0 || (byte & RAM_TEST_STATUS) != 0) { 6102 /* Get here if Done bit not set or Status not 0. */ 6103 asc_dvc->bist_err_code = byte; /* for BIOS display message */ 6104 asc_dvc->err_code = ASC_IERR_BIST_RAM_TEST; 6105 return ADV_ERROR; 6106 } 6107 6108 /* We need to reset back to normal mode after LRAM test passes. */ 6109 AdvWriteByteRegister(iop_base, IOPB_RAM_BIST, NORMAL_MODE); 6110 6111 err = request_firmware(&fw, fwname, asc_dvc->drv_ptr->dev); 6112 if (err) { 6113 printk(KERN_ERR "Failed to load image \"%s\" err %d\n", 6114 fwname, err); 6115 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 6116 return err; 6117 } 6118 if (fw->size < 4) { 6119 printk(KERN_ERR "Bogus length %zu in image \"%s\"\n", 6120 fw->size, fwname); 6121 release_firmware(fw); 6122 asc_dvc->err_code = ASC_IERR_MCODE_CHKSUM; 6123 return -EINVAL; 6124 } 6125 chksum = (fw->data[3] << 24) | (fw->data[2] << 16) | 6126 (fw->data[1] << 8) | fw->data[0]; 6127 asc_dvc->err_code = AdvLoadMicrocode(iop_base, &fw->data[4], 6128 fw->size - 4, ADV_38C1600_MEMSIZE, 6129 chksum); 6130 release_firmware(fw); 6131 if (asc_dvc->err_code) 6132 return ADV_ERROR; 6133 6134 /* 6135 * Restore the RISC memory BIOS region. 6136 */ 6137 for (i = 0; i < ASC_MC_BIOSLEN / 2; i++) { 6138 AdvWriteWordLram(iop_base, ASC_MC_BIOSMEM + (2 * i), 6139 bios_mem[i]); 6140 } 6141 6142 /* 6143 * Calculate and write the microcode code checksum to the microcode 6144 * code checksum location ASC_MC_CODE_CHK_SUM (0x2C). 6145 */ 6146 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, begin_addr); 6147 AdvReadWordLram(iop_base, ASC_MC_CODE_END_ADDR, end_addr); 6148 code_sum = 0; 6149 AdvWriteWordRegister(iop_base, IOPW_RAM_ADDR, begin_addr); 6150 for (word = begin_addr; word < end_addr; word += 2) { 6151 code_sum += AdvReadWordAutoIncLram(iop_base); 6152 } 6153 AdvWriteWordLram(iop_base, ASC_MC_CODE_CHK_SUM, code_sum); 6154 6155 /* 6156 * Read microcode version and date. 6157 */ 6158 AdvReadWordLram(iop_base, ASC_MC_VERSION_DATE, 6159 asc_dvc->cfg->mcode_date); 6160 AdvReadWordLram(iop_base, ASC_MC_VERSION_NUM, 6161 asc_dvc->cfg->mcode_version); 6162 6163 /* 6164 * Set the chip type to indicate the ASC38C1600. 6165 */ 6166 AdvWriteWordLram(iop_base, ASC_MC_CHIP_TYPE, ADV_CHIP_ASC38C1600); 6167 6168 /* 6169 * Write 1 to bit 14 'DIS_TERM_DRV' in the SCSI_CFG1 register. 6170 * When DIS_TERM_DRV set to 1, C_DET[3:0] will reflect current 6171 * cable detection and then we are able to read C_DET[3:0]. 6172 * 6173 * Note: We will reset DIS_TERM_DRV to 0 in the 'Set SCSI_CFG1 6174 * Microcode Default Value' section below. 6175 */ 6176 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 6177 AdvWriteWordRegister(iop_base, IOPW_SCSI_CFG1, 6178 scsi_cfg1 | DIS_TERM_DRV); 6179 6180 /* 6181 * If the PCI Configuration Command Register "Parity Error Response 6182 * Control" Bit was clear (0), then set the microcode variable 6183 * 'control_flag' CONTROL_FLAG_IGNORE_PERR flag to tell the microcode 6184 * to ignore DMA parity errors. 6185 */ 6186 if (asc_dvc->cfg->control_flag & CONTROL_FLAG_IGNORE_PERR) { 6187 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 6188 word |= CONTROL_FLAG_IGNORE_PERR; 6189 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 6190 } 6191 6192 /* 6193 * If the BIOS control flag AIPP (Asynchronous Information 6194 * Phase Protection) disable bit is not set, then set the firmware 6195 * 'control_flag' CONTROL_FLAG_ENABLE_AIPP bit to enable 6196 * AIPP checking and encoding. 6197 */ 6198 if ((asc_dvc->bios_ctrl & BIOS_CTRL_AIPP_DIS) == 0) { 6199 AdvReadWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 6200 word |= CONTROL_FLAG_ENABLE_AIPP; 6201 AdvWriteWordLram(iop_base, ASC_MC_CONTROL_FLAG, word); 6202 } 6203 6204 /* 6205 * For ASC-38C1600 use DMA_CFG0 default values: FIFO_THRESH_80B [6:4], 6206 * and START_CTL_TH [3:2]. 6207 */ 6208 AdvWriteByteRegister(iop_base, IOPB_DMA_CFG0, 6209 FIFO_THRESH_80B | START_CTL_TH | READ_CMD_MRM); 6210 6211 /* 6212 * Microcode operating variables for WDTR, SDTR, and command tag 6213 * queuing will be set in slave_configure() based on what a 6214 * device reports it is capable of in Inquiry byte 7. 6215 * 6216 * If SCSI Bus Resets have been disabled, then directly set 6217 * SDTR and WDTR from the EEPROM configuration. This will allow 6218 * the BIOS and warm boot to work without a SCSI bus hang on 6219 * the Inquiry caused by host and target mismatched DTR values. 6220 * Without the SCSI Bus Reset, before an Inquiry a device can't 6221 * be assumed to be in Asynchronous, Narrow mode. 6222 */ 6223 if ((asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) == 0) { 6224 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, 6225 asc_dvc->wdtr_able); 6226 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, 6227 asc_dvc->sdtr_able); 6228 } 6229 6230 /* 6231 * Set microcode operating variables for DISC and SDTR_SPEED1, 6232 * SDTR_SPEED2, SDTR_SPEED3, and SDTR_SPEED4 based on the EEPROM 6233 * configuration values. 6234 * 6235 * The SDTR per TID bitmask overrides the SDTR_SPEED1, SDTR_SPEED2, 6236 * SDTR_SPEED3, and SDTR_SPEED4 values so it is safe to set them 6237 * without determining here whether the device supports SDTR. 6238 */ 6239 AdvWriteWordLram(iop_base, ASC_MC_DISC_ENABLE, 6240 asc_dvc->cfg->disc_enable); 6241 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED1, asc_dvc->sdtr_speed1); 6242 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED2, asc_dvc->sdtr_speed2); 6243 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED3, asc_dvc->sdtr_speed3); 6244 AdvWriteWordLram(iop_base, ASC_MC_SDTR_SPEED4, asc_dvc->sdtr_speed4); 6245 6246 /* 6247 * Set SCSI_CFG0 Microcode Default Value. 6248 * 6249 * The microcode will set the SCSI_CFG0 register using this value 6250 * after it is started below. 6251 */ 6252 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG0, 6253 PARITY_EN | QUEUE_128 | SEL_TMO_LONG | OUR_ID_EN | 6254 asc_dvc->chip_scsi_id); 6255 6256 /* 6257 * Calculate SCSI_CFG1 Microcode Default Value. 6258 * 6259 * The microcode will set the SCSI_CFG1 register using this value 6260 * after it is started below. 6261 * 6262 * Each ASC-38C1600 function has only two cable detect bits. 6263 * The bus mode override bits are in IOPB_SOFT_OVER_WR. 6264 */ 6265 scsi_cfg1 = AdvReadWordRegister(iop_base, IOPW_SCSI_CFG1); 6266 6267 /* 6268 * If the cable is reversed all of the SCSI_CTRL register signals 6269 * will be set. Check for and return an error if this condition is 6270 * found. 6271 */ 6272 if ((AdvReadWordRegister(iop_base, IOPW_SCSI_CTRL) & 0x3F07) == 0x3F07) { 6273 asc_dvc->err_code |= ASC_IERR_REVERSED_CABLE; 6274 return ADV_ERROR; 6275 } 6276 6277 /* 6278 * Each ASC-38C1600 function has two connectors. Only an HVD device 6279 * can not be connected to either connector. An LVD device or SE device 6280 * may be connected to either connecor. If an SE device is connected, 6281 * then at most Ultra speed (20 Mhz) can be used on both connectors. 6282 * 6283 * If an HVD device is attached, return an error. 6284 */ 6285 if (scsi_cfg1 & HVD) { 6286 asc_dvc->err_code |= ASC_IERR_HVD_DEVICE; 6287 return ADV_ERROR; 6288 } 6289 6290 /* 6291 * Each function in the ASC-38C1600 uses only the SE cable detect and 6292 * termination because there are two connectors for each function. Each 6293 * function may use either LVD or SE mode. Corresponding the SE automatic 6294 * termination control EEPROM bits are used for each function. Each 6295 * function has its own EEPROM. If SE automatic control is enabled for 6296 * the function, then set the termination value based on a table listed 6297 * in a_condor.h. 6298 * 6299 * If manual termination is specified in the EEPROM for the function, 6300 * then 'termination' was set-up in AscInitFrom38C1600EEPROM() and is 6301 * ready to be 'ored' into SCSI_CFG1. 6302 */ 6303 if ((asc_dvc->cfg->termination & TERM_SE) == 0) { 6304 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc); 6305 /* SE automatic termination control is enabled. */ 6306 switch (scsi_cfg1 & C_DET_SE) { 6307 /* TERM_SE_HI: on, TERM_SE_LO: on */ 6308 case 0x1: 6309 case 0x2: 6310 case 0x3: 6311 asc_dvc->cfg->termination |= TERM_SE; 6312 break; 6313 6314 case 0x0: 6315 if (PCI_FUNC(pdev->devfn) == 0) { 6316 /* Function 0 - TERM_SE_HI: off, TERM_SE_LO: off */ 6317 } else { 6318 /* Function 1 - TERM_SE_HI: on, TERM_SE_LO: off */ 6319 asc_dvc->cfg->termination |= TERM_SE_HI; 6320 } 6321 break; 6322 } 6323 } 6324 6325 /* 6326 * Clear any set TERM_SE bits. 6327 */ 6328 scsi_cfg1 &= ~TERM_SE; 6329 6330 /* 6331 * Invert the TERM_SE bits and then set 'scsi_cfg1'. 6332 */ 6333 scsi_cfg1 |= (~asc_dvc->cfg->termination & TERM_SE); 6334 6335 /* 6336 * Clear Big Endian and Terminator Polarity bits and set possibly 6337 * modified termination control bits in the Microcode SCSI_CFG1 6338 * Register Value. 6339 * 6340 * Big Endian bit is not used even on big endian machines. 6341 */ 6342 scsi_cfg1 &= (~BIG_ENDIAN & ~DIS_TERM_DRV & ~TERM_POL); 6343 6344 /* 6345 * Set SCSI_CFG1 Microcode Default Value 6346 * 6347 * Set possibly modified termination control bits in the Microcode 6348 * SCSI_CFG1 Register Value. 6349 * 6350 * The microcode will set the SCSI_CFG1 register using this value 6351 * after it is started below. 6352 */ 6353 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SCSI_CFG1, scsi_cfg1); 6354 6355 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_MEM_CFG, 6356 BIOS_EN | RAM_SZ_16KB); 6357 6358 /* 6359 * Set SEL_MASK Microcode Default Value 6360 * 6361 * The microcode will set the SEL_MASK register using this value 6362 * after it is started below. 6363 */ 6364 AdvWriteWordLram(iop_base, ASC_MC_DEFAULT_SEL_MASK, 6365 ADV_TID_TO_TIDMASK(asc_dvc->chip_scsi_id)); 6366 6367 AdvBuildCarrierFreelist(asc_dvc); 6368 6369 /* 6370 * Set-up the Host->RISC Initiator Command Queue (ICQ). 6371 */ 6372 if ((asc_dvc->icq_sp = asc_dvc->carr_freelist) == NULL) { 6373 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 6374 return ADV_ERROR; 6375 } 6376 asc_dvc->carr_freelist = (ADV_CARR_T *) 6377 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->icq_sp->next_vpa)); 6378 6379 /* 6380 * The first command issued will be placed in the stopper carrier. 6381 */ 6382 asc_dvc->icq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); 6383 6384 /* 6385 * Set RISC ICQ physical address start value. Initialize the 6386 * COMMA register to the same value otherwise the RISC will 6387 * prematurely detect a command is available. 6388 */ 6389 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_ICQ, asc_dvc->icq_sp->carr_pa); 6390 AdvWriteDWordRegister(iop_base, IOPDW_COMMA, 6391 le32_to_cpu(asc_dvc->icq_sp->carr_pa)); 6392 6393 /* 6394 * Set-up the RISC->Host Initiator Response Queue (IRQ). 6395 */ 6396 if ((asc_dvc->irq_sp = asc_dvc->carr_freelist) == NULL) { 6397 asc_dvc->err_code |= ASC_IERR_NO_CARRIER; 6398 return ADV_ERROR; 6399 } 6400 asc_dvc->carr_freelist = (ADV_CARR_T *) 6401 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->next_vpa)); 6402 6403 /* 6404 * The first command completed by the RISC will be placed in 6405 * the stopper. 6406 * 6407 * Note: Set 'next_vpa' to ASC_CQ_STOPPER. When the request is 6408 * completed the RISC will set the ASC_RQ_STOPPER bit. 6409 */ 6410 asc_dvc->irq_sp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); 6411 6412 /* 6413 * Set RISC IRQ physical address start value. 6414 */ 6415 AdvWriteDWordLramNoSwap(iop_base, ASC_MC_IRQ, asc_dvc->irq_sp->carr_pa); 6416 asc_dvc->carr_pending_cnt = 0; 6417 6418 AdvWriteByteRegister(iop_base, IOPB_INTR_ENABLES, 6419 (ADV_INTR_ENABLE_HOST_INTR | 6420 ADV_INTR_ENABLE_GLOBAL_INTR)); 6421 AdvReadWordLram(iop_base, ASC_MC_CODE_BEGIN_ADDR, word); 6422 AdvWriteWordRegister(iop_base, IOPW_PC, word); 6423 6424 /* finally, finally, gentlemen, start your engine */ 6425 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_RUN); 6426 6427 /* 6428 * Reset the SCSI Bus if the EEPROM indicates that SCSI Bus 6429 * Resets should be performed. The RISC has to be running 6430 * to issue a SCSI Bus Reset. 6431 */ 6432 if (asc_dvc->bios_ctrl & BIOS_CTRL_RESET_SCSI_BUS) { 6433 /* 6434 * If the BIOS Signature is present in memory, restore the 6435 * per TID microcode operating variables. 6436 */ 6437 if (bios_mem[(ASC_MC_BIOS_SIGNATURE - ASC_MC_BIOSMEM) / 2] == 6438 0x55AA) { 6439 /* 6440 * Restore per TID negotiated values. 6441 */ 6442 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 6443 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 6444 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 6445 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 6446 tagqng_able); 6447 for (tid = 0; tid <= ASC_MAX_TID; tid++) { 6448 AdvWriteByteLram(iop_base, 6449 ASC_MC_NUMBER_OF_MAX_CMD + tid, 6450 max_cmd[tid]); 6451 } 6452 } else { 6453 if (AdvResetSB(asc_dvc) != ADV_TRUE) { 6454 warn_code = ASC_WARN_BUSRESET_ERROR; 6455 } 6456 } 6457 } 6458 6459 return warn_code; 6460} 6461 6462/* 6463 * Reset chip and SCSI Bus. 6464 * 6465 * Return Value: 6466 * ADV_TRUE(1) - Chip re-initialization and SCSI Bus Reset successful. 6467 * ADV_FALSE(0) - Chip re-initialization and SCSI Bus Reset failure. 6468 */ 6469static int AdvResetChipAndSB(ADV_DVC_VAR *asc_dvc) 6470{ 6471 int status; 6472 ushort wdtr_able, sdtr_able, tagqng_able; 6473 ushort ppr_able = 0; 6474 uchar tid, max_cmd[ADV_MAX_TID + 1]; 6475 AdvPortAddr iop_base; 6476 ushort bios_sig; 6477 6478 iop_base = asc_dvc->iop_base; 6479 6480 /* 6481 * Save current per TID negotiated values. 6482 */ 6483 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 6484 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 6485 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 6486 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 6487 } 6488 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 6489 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 6490 AdvReadByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 6491 max_cmd[tid]); 6492 } 6493 6494 /* 6495 * Force the AdvInitAsc3550/38C0800Driver() function to 6496 * perform a SCSI Bus Reset by clearing the BIOS signature word. 6497 * The initialization functions assumes a SCSI Bus Reset is not 6498 * needed if the BIOS signature word is present. 6499 */ 6500 AdvReadWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig); 6501 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, 0); 6502 6503 /* 6504 * Stop chip and reset it. 6505 */ 6506 AdvWriteWordRegister(iop_base, IOPW_RISC_CSR, ADV_RISC_CSR_STOP); 6507 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, ADV_CTRL_REG_CMD_RESET); 6508 mdelay(100); 6509 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, 6510 ADV_CTRL_REG_CMD_WR_IO_REG); 6511 6512 /* 6513 * Reset Adv Library error code, if any, and try 6514 * re-initializing the chip. 6515 */ 6516 asc_dvc->err_code = 0; 6517 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 6518 status = AdvInitAsc38C1600Driver(asc_dvc); 6519 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 6520 status = AdvInitAsc38C0800Driver(asc_dvc); 6521 } else { 6522 status = AdvInitAsc3550Driver(asc_dvc); 6523 } 6524 6525 /* Translate initialization return value to status value. */ 6526 if (status == 0) { 6527 status = ADV_TRUE; 6528 } else { 6529 status = ADV_FALSE; 6530 } 6531 6532 /* 6533 * Restore the BIOS signature word. 6534 */ 6535 AdvWriteWordLram(iop_base, ASC_MC_BIOS_SIGNATURE, bios_sig); 6536 6537 /* 6538 * Restore per TID negotiated values. 6539 */ 6540 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, wdtr_able); 6541 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, sdtr_able); 6542 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 6543 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, ppr_able); 6544 } 6545 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, tagqng_able); 6546 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 6547 AdvWriteByteLram(iop_base, ASC_MC_NUMBER_OF_MAX_CMD + tid, 6548 max_cmd[tid]); 6549 } 6550 6551 return status; 6552} 6553 6554/* 6555 * adv_async_callback() - Adv Library asynchronous event callback function. 6556 */ 6557static void adv_async_callback(ADV_DVC_VAR *adv_dvc_varp, uchar code) 6558{ 6559 switch (code) { 6560 case ADV_ASYNC_SCSI_BUS_RESET_DET: 6561 /* 6562 * The firmware detected a SCSI Bus reset. 6563 */ 6564 ASC_DBG(0, "ADV_ASYNC_SCSI_BUS_RESET_DET\n"); 6565 break; 6566 6567 case ADV_ASYNC_RDMA_FAILURE: 6568 /* 6569 * Handle RDMA failure by resetting the SCSI Bus and 6570 * possibly the chip if it is unresponsive. Log the error 6571 * with a unique code. 6572 */ 6573 ASC_DBG(0, "ADV_ASYNC_RDMA_FAILURE\n"); 6574 AdvResetChipAndSB(adv_dvc_varp); 6575 break; 6576 6577 case ADV_HOST_SCSI_BUS_RESET: 6578 /* 6579 * Host generated SCSI bus reset occurred. 6580 */ 6581 ASC_DBG(0, "ADV_HOST_SCSI_BUS_RESET\n"); 6582 break; 6583 6584 default: 6585 ASC_DBG(0, "unknown code 0x%x\n", code); 6586 break; 6587 } 6588} 6589 6590/* 6591 * adv_isr_callback() - Second Level Interrupt Handler called by AdvISR(). 6592 * 6593 * Callback function for the Wide SCSI Adv Library. 6594 */ 6595static void adv_isr_callback(ADV_DVC_VAR *adv_dvc_varp, ADV_SCSI_REQ_Q *scsiqp) 6596{ 6597 struct asc_board *boardp; 6598 adv_req_t *reqp; 6599 adv_sgblk_t *sgblkp; 6600 struct scsi_cmnd *scp; 6601 struct Scsi_Host *shost; 6602 ADV_DCNT resid_cnt; 6603 6604 ASC_DBG(1, "adv_dvc_varp 0x%lx, scsiqp 0x%lx\n", 6605 (ulong)adv_dvc_varp, (ulong)scsiqp); 6606 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp); 6607 6608 /* 6609 * Get the adv_req_t structure for the command that has been 6610 * completed. The adv_req_t structure actually contains the 6611 * completed ADV_SCSI_REQ_Q structure. 6612 */ 6613 reqp = (adv_req_t *)ADV_U32_TO_VADDR(scsiqp->srb_ptr); 6614 ASC_DBG(1, "reqp 0x%lx\n", (ulong)reqp); 6615 if (reqp == NULL) { 6616 ASC_PRINT("adv_isr_callback: reqp is NULL\n"); 6617 return; 6618 } 6619 6620 /* 6621 * Get the struct scsi_cmnd structure and Scsi_Host structure for the 6622 * command that has been completed. 6623 * 6624 * Note: The adv_req_t request structure and adv_sgblk_t structure, 6625 * if any, are dropped, because a board structure pointer can not be 6626 * determined. 6627 */ 6628 scp = reqp->cmndp; 6629 ASC_DBG(1, "scp 0x%p\n", scp); 6630 if (scp == NULL) { 6631 ASC_PRINT 6632 ("adv_isr_callback: scp is NULL; adv_req_t dropped.\n"); 6633 return; 6634 } 6635 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len); 6636 6637 shost = scp->device->host; 6638 ASC_STATS(shost, callback); 6639 ASC_DBG(1, "shost 0x%p\n", shost); 6640 6641 boardp = shost_priv(shost); 6642 BUG_ON(adv_dvc_varp != &boardp->dvc_var.adv_dvc_var); 6643 6644 /* 6645 * 'done_status' contains the command's ending status. 6646 */ 6647 switch (scsiqp->done_status) { 6648 case QD_NO_ERROR: 6649 ASC_DBG(2, "QD_NO_ERROR\n"); 6650 scp->result = 0; 6651 6652 /* 6653 * Check for an underrun condition. 6654 * 6655 * If there was no error and an underrun condition, then 6656 * then return the number of underrun bytes. 6657 */ 6658 resid_cnt = le32_to_cpu(scsiqp->data_cnt); 6659 if (scsi_bufflen(scp) != 0 && resid_cnt != 0 && 6660 resid_cnt <= scsi_bufflen(scp)) { 6661 ASC_DBG(1, "underrun condition %lu bytes\n", 6662 (ulong)resid_cnt); 6663 scsi_set_resid(scp, resid_cnt); 6664 } 6665 break; 6666 6667 case QD_WITH_ERROR: 6668 ASC_DBG(2, "QD_WITH_ERROR\n"); 6669 switch (scsiqp->host_status) { 6670 case QHSTA_NO_ERROR: 6671 if (scsiqp->scsi_status == SAM_STAT_CHECK_CONDITION) { 6672 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n"); 6673 ASC_DBG_PRT_SENSE(2, scp->sense_buffer, 6674 SCSI_SENSE_BUFFERSIZE); 6675 /* 6676 * Note: The 'status_byte()' macro used by 6677 * target drivers defined in scsi.h shifts the 6678 * status byte returned by host drivers right 6679 * by 1 bit. This is why target drivers also 6680 * use right shifted status byte definitions. 6681 * For instance target drivers use 6682 * CHECK_CONDITION, defined to 0x1, instead of 6683 * the SCSI defined check condition value of 6684 * 0x2. Host drivers are supposed to return 6685 * the status byte as it is defined by SCSI. 6686 */ 6687 scp->result = DRIVER_BYTE(DRIVER_SENSE) | 6688 STATUS_BYTE(scsiqp->scsi_status); 6689 } else { 6690 scp->result = STATUS_BYTE(scsiqp->scsi_status); 6691 } 6692 break; 6693 6694 default: 6695 /* Some other QHSTA error occurred. */ 6696 ASC_DBG(1, "host_status 0x%x\n", scsiqp->host_status); 6697 scp->result = HOST_BYTE(DID_BAD_TARGET); 6698 break; 6699 } 6700 break; 6701 6702 case QD_ABORTED_BY_HOST: 6703 ASC_DBG(1, "QD_ABORTED_BY_HOST\n"); 6704 scp->result = 6705 HOST_BYTE(DID_ABORT) | STATUS_BYTE(scsiqp->scsi_status); 6706 break; 6707 6708 default: 6709 ASC_DBG(1, "done_status 0x%x\n", scsiqp->done_status); 6710 scp->result = 6711 HOST_BYTE(DID_ERROR) | STATUS_BYTE(scsiqp->scsi_status); 6712 break; 6713 } 6714 6715 /* 6716 * If the 'init_tidmask' bit isn't already set for the target and the 6717 * current request finished normally, then set the bit for the target 6718 * to indicate that a device is present. 6719 */ 6720 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 && 6721 scsiqp->done_status == QD_NO_ERROR && 6722 scsiqp->host_status == QHSTA_NO_ERROR) { 6723 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id); 6724 } 6725 6726 asc_scsi_done(scp); 6727 6728 /* 6729 * Free all 'adv_sgblk_t' structures allocated for the request. 6730 */ 6731 while ((sgblkp = reqp->sgblkp) != NULL) { 6732 /* Remove 'sgblkp' from the request list. */ 6733 reqp->sgblkp = sgblkp->next_sgblkp; 6734 6735 /* Add 'sgblkp' to the board free list. */ 6736 sgblkp->next_sgblkp = boardp->adv_sgblkp; 6737 boardp->adv_sgblkp = sgblkp; 6738 } 6739 6740 /* 6741 * Free the adv_req_t structure used with the command by adding 6742 * it back to the board free list. 6743 */ 6744 reqp->next_reqp = boardp->adv_reqp; 6745 boardp->adv_reqp = reqp; 6746 6747 ASC_DBG(1, "done\n"); 6748} 6749 6750/* 6751 * Adv Library Interrupt Service Routine 6752 * 6753 * This function is called by a driver's interrupt service routine. 6754 * The function disables and re-enables interrupts. 6755 * 6756 * When a microcode idle command is completed, the ADV_DVC_VAR 6757 * 'idle_cmd_done' field is set to ADV_TRUE. 6758 * 6759 * Note: AdvISR() can be called when interrupts are disabled or even 6760 * when there is no hardware interrupt condition present. It will 6761 * always check for completed idle commands and microcode requests. 6762 * This is an important feature that shouldn't be changed because it 6763 * allows commands to be completed from polling mode loops. 6764 * 6765 * Return: 6766 * ADV_TRUE(1) - interrupt was pending 6767 * ADV_FALSE(0) - no interrupt was pending 6768 */ 6769static int AdvISR(ADV_DVC_VAR *asc_dvc) 6770{ 6771 AdvPortAddr iop_base; 6772 uchar int_stat; 6773 ushort target_bit; 6774 ADV_CARR_T *free_carrp; 6775 ADV_VADDR irq_next_vpa; 6776 ADV_SCSI_REQ_Q *scsiq; 6777 6778 iop_base = asc_dvc->iop_base; 6779 6780 /* Reading the register clears the interrupt. */ 6781 int_stat = AdvReadByteRegister(iop_base, IOPB_INTR_STATUS_REG); 6782 6783 if ((int_stat & (ADV_INTR_STATUS_INTRA | ADV_INTR_STATUS_INTRB | 6784 ADV_INTR_STATUS_INTRC)) == 0) { 6785 return ADV_FALSE; 6786 } 6787 6788 /* 6789 * Notify the driver of an asynchronous microcode condition by 6790 * calling the adv_async_callback function. The function 6791 * is passed the microcode ASC_MC_INTRB_CODE byte value. 6792 */ 6793 if (int_stat & ADV_INTR_STATUS_INTRB) { 6794 uchar intrb_code; 6795 6796 AdvReadByteLram(iop_base, ASC_MC_INTRB_CODE, intrb_code); 6797 6798 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 || 6799 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 6800 if (intrb_code == ADV_ASYNC_CARRIER_READY_FAILURE && 6801 asc_dvc->carr_pending_cnt != 0) { 6802 AdvWriteByteRegister(iop_base, IOPB_TICKLE, 6803 ADV_TICKLE_A); 6804 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { 6805 AdvWriteByteRegister(iop_base, 6806 IOPB_TICKLE, 6807 ADV_TICKLE_NOP); 6808 } 6809 } 6810 } 6811 6812 adv_async_callback(asc_dvc, intrb_code); 6813 } 6814 6815 /* 6816 * Check if the IRQ stopper carrier contains a completed request. 6817 */ 6818 while (((irq_next_vpa = 6819 le32_to_cpu(asc_dvc->irq_sp->next_vpa)) & ASC_RQ_DONE) != 0) { 6820 /* 6821 * Get a pointer to the newly completed ADV_SCSI_REQ_Q structure. 6822 * The RISC will have set 'areq_vpa' to a virtual address. 6823 * 6824 * The firmware will have copied the ASC_SCSI_REQ_Q.scsiq_ptr 6825 * field to the carrier ADV_CARR_T.areq_vpa field. The conversion 6826 * below complements the conversion of ASC_SCSI_REQ_Q.scsiq_ptr' 6827 * in AdvExeScsiQueue(). 6828 */ 6829 scsiq = (ADV_SCSI_REQ_Q *) 6830 ADV_U32_TO_VADDR(le32_to_cpu(asc_dvc->irq_sp->areq_vpa)); 6831 6832 /* 6833 * Request finished with good status and the queue was not 6834 * DMAed to host memory by the firmware. Set all status fields 6835 * to indicate good status. 6836 */ 6837 if ((irq_next_vpa & ASC_RQ_GOOD) != 0) { 6838 scsiq->done_status = QD_NO_ERROR; 6839 scsiq->host_status = scsiq->scsi_status = 0; 6840 scsiq->data_cnt = 0L; 6841 } 6842 6843 /* 6844 * Advance the stopper pointer to the next carrier 6845 * ignoring the lower four bits. Free the previous 6846 * stopper carrier. 6847 */ 6848 free_carrp = asc_dvc->irq_sp; 6849 asc_dvc->irq_sp = (ADV_CARR_T *) 6850 ADV_U32_TO_VADDR(ASC_GET_CARRP(irq_next_vpa)); 6851 6852 free_carrp->next_vpa = 6853 cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->carr_freelist)); 6854 asc_dvc->carr_freelist = free_carrp; 6855 asc_dvc->carr_pending_cnt--; 6856 6857 target_bit = ADV_TID_TO_TIDMASK(scsiq->target_id); 6858 6859 /* 6860 * Clear request microcode control flag. 6861 */ 6862 scsiq->cntl = 0; 6863 6864 /* 6865 * Notify the driver of the completed request by passing 6866 * the ADV_SCSI_REQ_Q pointer to its callback function. 6867 */ 6868 scsiq->a_flag |= ADV_SCSIQ_DONE; 6869 adv_isr_callback(asc_dvc, scsiq); 6870 /* 6871 * Note: After the driver callback function is called, 'scsiq' 6872 * can no longer be referenced. 6873 * 6874 * Fall through and continue processing other completed 6875 * requests... 6876 */ 6877 } 6878 return ADV_TRUE; 6879} 6880 6881static int AscSetLibErrorCode(ASC_DVC_VAR *asc_dvc, ushort err_code) 6882{ 6883 if (asc_dvc->err_code == 0) { 6884 asc_dvc->err_code = err_code; 6885 AscWriteLramWord(asc_dvc->iop_base, ASCV_ASCDVC_ERR_CODE_W, 6886 err_code); 6887 } 6888 return err_code; 6889} 6890 6891static void AscAckInterrupt(PortAddr iop_base) 6892{ 6893 uchar host_flag; 6894 uchar risc_flag; 6895 ushort loop; 6896 6897 loop = 0; 6898 do { 6899 risc_flag = AscReadLramByte(iop_base, ASCV_RISC_FLAG_B); 6900 if (loop++ > 0x7FFF) { 6901 break; 6902 } 6903 } while ((risc_flag & ASC_RISC_FLAG_GEN_INT) != 0); 6904 host_flag = 6905 AscReadLramByte(iop_base, 6906 ASCV_HOST_FLAG_B) & (~ASC_HOST_FLAG_ACK_INT); 6907 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, 6908 (uchar)(host_flag | ASC_HOST_FLAG_ACK_INT)); 6909 AscSetChipStatus(iop_base, CIW_INT_ACK); 6910 loop = 0; 6911 while (AscGetChipStatus(iop_base) & CSW_INT_PENDING) { 6912 AscSetChipStatus(iop_base, CIW_INT_ACK); 6913 if (loop++ > 3) { 6914 break; 6915 } 6916 } 6917 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag); 6918} 6919 6920static uchar AscGetSynPeriodIndex(ASC_DVC_VAR *asc_dvc, uchar syn_time) 6921{ 6922 const uchar *period_table; 6923 int max_index; 6924 int min_index; 6925 int i; 6926 6927 period_table = asc_dvc->sdtr_period_tbl; 6928 max_index = (int)asc_dvc->max_sdtr_index; 6929 min_index = (int)asc_dvc->min_sdtr_index; 6930 if ((syn_time <= period_table[max_index])) { 6931 for (i = min_index; i < (max_index - 1); i++) { 6932 if (syn_time <= period_table[i]) { 6933 return (uchar)i; 6934 } 6935 } 6936 return (uchar)max_index; 6937 } else { 6938 return (uchar)(max_index + 1); 6939 } 6940} 6941 6942static uchar 6943AscMsgOutSDTR(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar sdtr_offset) 6944{ 6945 EXT_MSG sdtr_buf; 6946 uchar sdtr_period_index; 6947 PortAddr iop_base; 6948 6949 iop_base = asc_dvc->iop_base; 6950 sdtr_buf.msg_type = EXTENDED_MESSAGE; 6951 sdtr_buf.msg_len = MS_SDTR_LEN; 6952 sdtr_buf.msg_req = EXTENDED_SDTR; 6953 sdtr_buf.xfer_period = sdtr_period; 6954 sdtr_offset &= ASC_SYN_MAX_OFFSET; 6955 sdtr_buf.req_ack_offset = sdtr_offset; 6956 sdtr_period_index = AscGetSynPeriodIndex(asc_dvc, sdtr_period); 6957 if (sdtr_period_index <= asc_dvc->max_sdtr_index) { 6958 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG, 6959 (uchar *)&sdtr_buf, 6960 sizeof(EXT_MSG) >> 1); 6961 return ((sdtr_period_index << 4) | sdtr_offset); 6962 } else { 6963 sdtr_buf.req_ack_offset = 0; 6964 AscMemWordCopyPtrToLram(iop_base, ASCV_MSGOUT_BEG, 6965 (uchar *)&sdtr_buf, 6966 sizeof(EXT_MSG) >> 1); 6967 return 0; 6968 } 6969} 6970 6971static uchar 6972AscCalSDTRData(ASC_DVC_VAR *asc_dvc, uchar sdtr_period, uchar syn_offset) 6973{ 6974 uchar byte; 6975 uchar sdtr_period_ix; 6976 6977 sdtr_period_ix = AscGetSynPeriodIndex(asc_dvc, sdtr_period); 6978 if (sdtr_period_ix > asc_dvc->max_sdtr_index) 6979 return 0xFF; 6980 byte = (sdtr_period_ix << 4) | (syn_offset & ASC_SYN_MAX_OFFSET); 6981 return byte; 6982} 6983 6984static int AscSetChipSynRegAtID(PortAddr iop_base, uchar id, uchar sdtr_data) 6985{ 6986 ASC_SCSI_BIT_ID_TYPE org_id; 6987 int i; 6988 int sta = TRUE; 6989 6990 AscSetBank(iop_base, 1); 6991 org_id = AscReadChipDvcID(iop_base); 6992 for (i = 0; i <= ASC_MAX_TID; i++) { 6993 if (org_id == (0x01 << i)) 6994 break; 6995 } 6996 org_id = (ASC_SCSI_BIT_ID_TYPE) i; 6997 AscWriteChipDvcID(iop_base, id); 6998 if (AscReadChipDvcID(iop_base) == (0x01 << id)) { 6999 AscSetBank(iop_base, 0); 7000 AscSetChipSyn(iop_base, sdtr_data); 7001 if (AscGetChipSyn(iop_base) != sdtr_data) { 7002 sta = FALSE; 7003 } 7004 } else { 7005 sta = FALSE; 7006 } 7007 AscSetBank(iop_base, 1); 7008 AscWriteChipDvcID(iop_base, org_id); 7009 AscSetBank(iop_base, 0); 7010 return (sta); 7011} 7012 7013static void AscSetChipSDTR(PortAddr iop_base, uchar sdtr_data, uchar tid_no) 7014{ 7015 AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data); 7016 AscPutMCodeSDTRDoneAtID(iop_base, tid_no, sdtr_data); 7017} 7018 7019static int AscIsrChipHalted(ASC_DVC_VAR *asc_dvc) 7020{ 7021 EXT_MSG ext_msg; 7022 EXT_MSG out_msg; 7023 ushort halt_q_addr; 7024 int sdtr_accept; 7025 ushort int_halt_code; 7026 ASC_SCSI_BIT_ID_TYPE scsi_busy; 7027 ASC_SCSI_BIT_ID_TYPE target_id; 7028 PortAddr iop_base; 7029 uchar tag_code; 7030 uchar q_status; 7031 uchar halt_qp; 7032 uchar sdtr_data; 7033 uchar target_ix; 7034 uchar q_cntl, tid_no; 7035 uchar cur_dvc_qng; 7036 uchar asyn_sdtr; 7037 uchar scsi_status; 7038 struct asc_board *boardp; 7039 7040 BUG_ON(!asc_dvc->drv_ptr); 7041 boardp = asc_dvc->drv_ptr; 7042 7043 iop_base = asc_dvc->iop_base; 7044 int_halt_code = AscReadLramWord(iop_base, ASCV_HALTCODE_W); 7045 7046 halt_qp = AscReadLramByte(iop_base, ASCV_CURCDB_B); 7047 halt_q_addr = ASC_QNO_TO_QADDR(halt_qp); 7048 target_ix = AscReadLramByte(iop_base, 7049 (ushort)(halt_q_addr + 7050 (ushort)ASC_SCSIQ_B_TARGET_IX)); 7051 q_cntl = AscReadLramByte(iop_base, 7052 (ushort)(halt_q_addr + (ushort)ASC_SCSIQ_B_CNTL)); 7053 tid_no = ASC_TIX_TO_TID(target_ix); 7054 target_id = (uchar)ASC_TID_TO_TARGET_ID(tid_no); 7055 if (asc_dvc->pci_fix_asyn_xfer & target_id) { 7056 asyn_sdtr = ASYN_SDTR_DATA_FIX_PCI_REV_AB; 7057 } else { 7058 asyn_sdtr = 0; 7059 } 7060 if (int_halt_code == ASC_HALT_DISABLE_ASYN_USE_SYN_FIX) { 7061 if (asc_dvc->pci_fix_asyn_xfer & target_id) { 7062 AscSetChipSDTR(iop_base, 0, tid_no); 7063 boardp->sdtr_data[tid_no] = 0; 7064 } 7065 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 7066 return (0); 7067 } else if (int_halt_code == ASC_HALT_ENABLE_ASYN_USE_SYN_FIX) { 7068 if (asc_dvc->pci_fix_asyn_xfer & target_id) { 7069 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); 7070 boardp->sdtr_data[tid_no] = asyn_sdtr; 7071 } 7072 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 7073 return (0); 7074 } else if (int_halt_code == ASC_HALT_EXTMSG_IN) { 7075 AscMemWordCopyPtrFromLram(iop_base, 7076 ASCV_MSGIN_BEG, 7077 (uchar *)&ext_msg, 7078 sizeof(EXT_MSG) >> 1); 7079 7080 if (ext_msg.msg_type == EXTENDED_MESSAGE && 7081 ext_msg.msg_req == EXTENDED_SDTR && 7082 ext_msg.msg_len == MS_SDTR_LEN) { 7083 sdtr_accept = TRUE; 7084 if ((ext_msg.req_ack_offset > ASC_SYN_MAX_OFFSET)) { 7085 7086 sdtr_accept = FALSE; 7087 ext_msg.req_ack_offset = ASC_SYN_MAX_OFFSET; 7088 } 7089 if ((ext_msg.xfer_period < 7090 asc_dvc->sdtr_period_tbl[asc_dvc->min_sdtr_index]) 7091 || (ext_msg.xfer_period > 7092 asc_dvc->sdtr_period_tbl[asc_dvc-> 7093 max_sdtr_index])) { 7094 sdtr_accept = FALSE; 7095 ext_msg.xfer_period = 7096 asc_dvc->sdtr_period_tbl[asc_dvc-> 7097 min_sdtr_index]; 7098 } 7099 if (sdtr_accept) { 7100 sdtr_data = 7101 AscCalSDTRData(asc_dvc, ext_msg.xfer_period, 7102 ext_msg.req_ack_offset); 7103 if ((sdtr_data == 0xFF)) { 7104 7105 q_cntl |= QC_MSG_OUT; 7106 asc_dvc->init_sdtr &= ~target_id; 7107 asc_dvc->sdtr_done &= ~target_id; 7108 AscSetChipSDTR(iop_base, asyn_sdtr, 7109 tid_no); 7110 boardp->sdtr_data[tid_no] = asyn_sdtr; 7111 } 7112 } 7113 if (ext_msg.req_ack_offset == 0) { 7114 7115 q_cntl &= ~QC_MSG_OUT; 7116 asc_dvc->init_sdtr &= ~target_id; 7117 asc_dvc->sdtr_done &= ~target_id; 7118 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); 7119 } else { 7120 if (sdtr_accept && (q_cntl & QC_MSG_OUT)) { 7121 q_cntl &= ~QC_MSG_OUT; 7122 asc_dvc->sdtr_done |= target_id; 7123 asc_dvc->init_sdtr |= target_id; 7124 asc_dvc->pci_fix_asyn_xfer &= 7125 ~target_id; 7126 sdtr_data = 7127 AscCalSDTRData(asc_dvc, 7128 ext_msg.xfer_period, 7129 ext_msg. 7130 req_ack_offset); 7131 AscSetChipSDTR(iop_base, sdtr_data, 7132 tid_no); 7133 boardp->sdtr_data[tid_no] = sdtr_data; 7134 } else { 7135 q_cntl |= QC_MSG_OUT; 7136 AscMsgOutSDTR(asc_dvc, 7137 ext_msg.xfer_period, 7138 ext_msg.req_ack_offset); 7139 asc_dvc->pci_fix_asyn_xfer &= 7140 ~target_id; 7141 sdtr_data = 7142 AscCalSDTRData(asc_dvc, 7143 ext_msg.xfer_period, 7144 ext_msg. 7145 req_ack_offset); 7146 AscSetChipSDTR(iop_base, sdtr_data, 7147 tid_no); 7148 boardp->sdtr_data[tid_no] = sdtr_data; 7149 asc_dvc->sdtr_done |= target_id; 7150 asc_dvc->init_sdtr |= target_id; 7151 } 7152 } 7153 7154 AscWriteLramByte(iop_base, 7155 (ushort)(halt_q_addr + 7156 (ushort)ASC_SCSIQ_B_CNTL), 7157 q_cntl); 7158 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 7159 return (0); 7160 } else if (ext_msg.msg_type == EXTENDED_MESSAGE && 7161 ext_msg.msg_req == EXTENDED_WDTR && 7162 ext_msg.msg_len == MS_WDTR_LEN) { 7163 7164 ext_msg.wdtr_width = 0; 7165 AscMemWordCopyPtrToLram(iop_base, 7166 ASCV_MSGOUT_BEG, 7167 (uchar *)&ext_msg, 7168 sizeof(EXT_MSG) >> 1); 7169 q_cntl |= QC_MSG_OUT; 7170 AscWriteLramByte(iop_base, 7171 (ushort)(halt_q_addr + 7172 (ushort)ASC_SCSIQ_B_CNTL), 7173 q_cntl); 7174 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 7175 return (0); 7176 } else { 7177 7178 ext_msg.msg_type = MESSAGE_REJECT; 7179 AscMemWordCopyPtrToLram(iop_base, 7180 ASCV_MSGOUT_BEG, 7181 (uchar *)&ext_msg, 7182 sizeof(EXT_MSG) >> 1); 7183 q_cntl |= QC_MSG_OUT; 7184 AscWriteLramByte(iop_base, 7185 (ushort)(halt_q_addr + 7186 (ushort)ASC_SCSIQ_B_CNTL), 7187 q_cntl); 7188 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 7189 return (0); 7190 } 7191 } else if (int_halt_code == ASC_HALT_CHK_CONDITION) { 7192 7193 q_cntl |= QC_REQ_SENSE; 7194 7195 if ((asc_dvc->init_sdtr & target_id) != 0) { 7196 7197 asc_dvc->sdtr_done &= ~target_id; 7198 7199 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); 7200 q_cntl |= QC_MSG_OUT; 7201 AscMsgOutSDTR(asc_dvc, 7202 asc_dvc-> 7203 sdtr_period_tbl[(sdtr_data >> 4) & 7204 (uchar)(asc_dvc-> 7205 max_sdtr_index - 7206 1)], 7207 (uchar)(sdtr_data & (uchar) 7208 ASC_SYN_MAX_OFFSET)); 7209 } 7210 7211 AscWriteLramByte(iop_base, 7212 (ushort)(halt_q_addr + 7213 (ushort)ASC_SCSIQ_B_CNTL), q_cntl); 7214 7215 tag_code = AscReadLramByte(iop_base, 7216 (ushort)(halt_q_addr + (ushort) 7217 ASC_SCSIQ_B_TAG_CODE)); 7218 tag_code &= 0xDC; 7219 if ((asc_dvc->pci_fix_asyn_xfer & target_id) 7220 && !(asc_dvc->pci_fix_asyn_xfer_always & target_id) 7221 ) { 7222 7223 tag_code |= (ASC_TAG_FLAG_DISABLE_DISCONNECT 7224 | ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX); 7225 7226 } 7227 AscWriteLramByte(iop_base, 7228 (ushort)(halt_q_addr + 7229 (ushort)ASC_SCSIQ_B_TAG_CODE), 7230 tag_code); 7231 7232 q_status = AscReadLramByte(iop_base, 7233 (ushort)(halt_q_addr + (ushort) 7234 ASC_SCSIQ_B_STATUS)); 7235 q_status |= (QS_READY | QS_BUSY); 7236 AscWriteLramByte(iop_base, 7237 (ushort)(halt_q_addr + 7238 (ushort)ASC_SCSIQ_B_STATUS), 7239 q_status); 7240 7241 scsi_busy = AscReadLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B); 7242 scsi_busy &= ~target_id; 7243 AscWriteLramByte(iop_base, (ushort)ASCV_SCSIBUSY_B, scsi_busy); 7244 7245 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 7246 return (0); 7247 } else if (int_halt_code == ASC_HALT_SDTR_REJECTED) { 7248 7249 AscMemWordCopyPtrFromLram(iop_base, 7250 ASCV_MSGOUT_BEG, 7251 (uchar *)&out_msg, 7252 sizeof(EXT_MSG) >> 1); 7253 7254 if ((out_msg.msg_type == EXTENDED_MESSAGE) && 7255 (out_msg.msg_len == MS_SDTR_LEN) && 7256 (out_msg.msg_req == EXTENDED_SDTR)) { 7257 7258 asc_dvc->init_sdtr &= ~target_id; 7259 asc_dvc->sdtr_done &= ~target_id; 7260 AscSetChipSDTR(iop_base, asyn_sdtr, tid_no); 7261 boardp->sdtr_data[tid_no] = asyn_sdtr; 7262 } 7263 q_cntl &= ~QC_MSG_OUT; 7264 AscWriteLramByte(iop_base, 7265 (ushort)(halt_q_addr + 7266 (ushort)ASC_SCSIQ_B_CNTL), q_cntl); 7267 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 7268 return (0); 7269 } else if (int_halt_code == ASC_HALT_SS_QUEUE_FULL) { 7270 7271 scsi_status = AscReadLramByte(iop_base, 7272 (ushort)((ushort)halt_q_addr + 7273 (ushort) 7274 ASC_SCSIQ_SCSI_STATUS)); 7275 cur_dvc_qng = 7276 AscReadLramByte(iop_base, 7277 (ushort)((ushort)ASC_QADR_BEG + 7278 (ushort)target_ix)); 7279 if ((cur_dvc_qng > 0) && (asc_dvc->cur_dvc_qng[tid_no] > 0)) { 7280 7281 scsi_busy = AscReadLramByte(iop_base, 7282 (ushort)ASCV_SCSIBUSY_B); 7283 scsi_busy |= target_id; 7284 AscWriteLramByte(iop_base, 7285 (ushort)ASCV_SCSIBUSY_B, scsi_busy); 7286 asc_dvc->queue_full_or_busy |= target_id; 7287 7288 if (scsi_status == SAM_STAT_TASK_SET_FULL) { 7289 if (cur_dvc_qng > ASC_MIN_TAGGED_CMD) { 7290 cur_dvc_qng -= 1; 7291 asc_dvc->max_dvc_qng[tid_no] = 7292 cur_dvc_qng; 7293 7294 AscWriteLramByte(iop_base, 7295 (ushort)((ushort) 7296 ASCV_MAX_DVC_QNG_BEG 7297 + (ushort) 7298 tid_no), 7299 cur_dvc_qng); 7300 7301 /* 7302 * Set the device queue depth to the 7303 * number of active requests when the 7304 * QUEUE FULL condition was encountered. 7305 */ 7306 boardp->queue_full |= target_id; 7307 boardp->queue_full_cnt[tid_no] = 7308 cur_dvc_qng; 7309 } 7310 } 7311 } 7312 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 7313 return (0); 7314 } 7315#if CC_VERY_LONG_SG_LIST 7316 else if (int_halt_code == ASC_HALT_HOST_COPY_SG_LIST_TO_RISC) { 7317 uchar q_no; 7318 ushort q_addr; 7319 uchar sg_wk_q_no; 7320 uchar first_sg_wk_q_no; 7321 ASC_SCSI_Q *scsiq; /* Ptr to driver request. */ 7322 ASC_SG_HEAD *sg_head; /* Ptr to driver SG request. */ 7323 ASC_SG_LIST_Q scsi_sg_q; /* Structure written to queue. */ 7324 ushort sg_list_dwords; 7325 ushort sg_entry_cnt; 7326 uchar next_qp; 7327 int i; 7328 7329 q_no = AscReadLramByte(iop_base, (ushort)ASCV_REQ_SG_LIST_QP); 7330 if (q_no == ASC_QLINK_END) 7331 return 0; 7332 7333 q_addr = ASC_QNO_TO_QADDR(q_no); 7334 7335 /* 7336 * Convert the request's SRB pointer to a host ASC_SCSI_REQ 7337 * structure pointer using a macro provided by the driver. 7338 * The ASC_SCSI_REQ pointer provides a pointer to the 7339 * host ASC_SG_HEAD structure. 7340 */ 7341 /* Read request's SRB pointer. */ 7342 scsiq = (ASC_SCSI_Q *) 7343 ASC_SRB2SCSIQ(ASC_U32_TO_VADDR(AscReadLramDWord(iop_base, 7344 (ushort) 7345 (q_addr + 7346 ASC_SCSIQ_D_SRBPTR)))); 7347 7348 /* 7349 * Get request's first and working SG queue. 7350 */ 7351 sg_wk_q_no = AscReadLramByte(iop_base, 7352 (ushort)(q_addr + 7353 ASC_SCSIQ_B_SG_WK_QP)); 7354 7355 first_sg_wk_q_no = AscReadLramByte(iop_base, 7356 (ushort)(q_addr + 7357 ASC_SCSIQ_B_FIRST_SG_WK_QP)); 7358 7359 /* 7360 * Reset request's working SG queue back to the 7361 * first SG queue. 7362 */ 7363 AscWriteLramByte(iop_base, 7364 (ushort)(q_addr + 7365 (ushort)ASC_SCSIQ_B_SG_WK_QP), 7366 first_sg_wk_q_no); 7367 7368 sg_head = scsiq->sg_head; 7369 7370 /* 7371 * Set sg_entry_cnt to the number of SG elements 7372 * that will be completed on this interrupt. 7373 * 7374 * Note: The allocated SG queues contain ASC_MAX_SG_LIST - 1 7375 * SG elements. The data_cnt and data_addr fields which 7376 * add 1 to the SG element capacity are not used when 7377 * restarting SG handling after a halt. 7378 */ 7379 if (scsiq->remain_sg_entry_cnt > (ASC_MAX_SG_LIST - 1)) { 7380 sg_entry_cnt = ASC_MAX_SG_LIST - 1; 7381 7382 /* 7383 * Keep track of remaining number of SG elements that 7384 * will need to be handled on the next interrupt. 7385 */ 7386 scsiq->remain_sg_entry_cnt -= (ASC_MAX_SG_LIST - 1); 7387 } else { 7388 sg_entry_cnt = scsiq->remain_sg_entry_cnt; 7389 scsiq->remain_sg_entry_cnt = 0; 7390 } 7391 7392 /* 7393 * Copy SG elements into the list of allocated SG queues. 7394 * 7395 * Last index completed is saved in scsiq->next_sg_index. 7396 */ 7397 next_qp = first_sg_wk_q_no; 7398 q_addr = ASC_QNO_TO_QADDR(next_qp); 7399 scsi_sg_q.sg_head_qp = q_no; 7400 scsi_sg_q.cntl = QCSG_SG_XFER_LIST; 7401 for (i = 0; i < sg_head->queue_cnt; i++) { 7402 scsi_sg_q.seq_no = i + 1; 7403 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 7404 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2); 7405 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 7406 /* 7407 * After very first SG queue RISC FW uses next 7408 * SG queue first element then checks sg_list_cnt 7409 * against zero and then decrements, so set 7410 * sg_list_cnt 1 less than number of SG elements 7411 * in each SG queue. 7412 */ 7413 scsi_sg_q.sg_list_cnt = ASC_SG_LIST_PER_Q - 1; 7414 scsi_sg_q.sg_cur_list_cnt = 7415 ASC_SG_LIST_PER_Q - 1; 7416 } else { 7417 /* 7418 * This is the last SG queue in the list of 7419 * allocated SG queues. If there are more 7420 * SG elements than will fit in the allocated 7421 * queues, then set the QCSG_SG_XFER_MORE flag. 7422 */ 7423 if (scsiq->remain_sg_entry_cnt != 0) { 7424 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE; 7425 } else { 7426 scsi_sg_q.cntl |= QCSG_SG_XFER_END; 7427 } 7428 /* equals sg_entry_cnt * 2 */ 7429 sg_list_dwords = sg_entry_cnt << 1; 7430 scsi_sg_q.sg_list_cnt = sg_entry_cnt - 1; 7431 scsi_sg_q.sg_cur_list_cnt = sg_entry_cnt - 1; 7432 sg_entry_cnt = 0; 7433 } 7434 7435 scsi_sg_q.q_no = next_qp; 7436 AscMemWordCopyPtrToLram(iop_base, 7437 q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 7438 (uchar *)&scsi_sg_q, 7439 sizeof(ASC_SG_LIST_Q) >> 1); 7440 7441 AscMemDWordCopyPtrToLram(iop_base, 7442 q_addr + ASC_SGQ_LIST_BEG, 7443 (uchar *)&sg_head-> 7444 sg_list[scsiq->next_sg_index], 7445 sg_list_dwords); 7446 7447 scsiq->next_sg_index += ASC_SG_LIST_PER_Q; 7448 7449 /* 7450 * If the just completed SG queue contained the 7451 * last SG element, then no more SG queues need 7452 * to be written. 7453 */ 7454 if (scsi_sg_q.cntl & QCSG_SG_XFER_END) { 7455 break; 7456 } 7457 7458 next_qp = AscReadLramByte(iop_base, 7459 (ushort)(q_addr + 7460 ASC_SCSIQ_B_FWD)); 7461 q_addr = ASC_QNO_TO_QADDR(next_qp); 7462 } 7463 7464 /* 7465 * Clear the halt condition so the RISC will be restarted 7466 * after the return. 7467 */ 7468 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0); 7469 return (0); 7470 } 7471#endif /* CC_VERY_LONG_SG_LIST */ 7472 return (0); 7473} 7474 7475/* 7476 * void 7477 * DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words) 7478 * 7479 * Calling/Exit State: 7480 * none 7481 * 7482 * Description: 7483 * Input an ASC_QDONE_INFO structure from the chip 7484 */ 7485static void 7486DvcGetQinfo(PortAddr iop_base, ushort s_addr, uchar *inbuf, int words) 7487{ 7488 int i; 7489 ushort word; 7490 7491 AscSetChipLramAddr(iop_base, s_addr); 7492 for (i = 0; i < 2 * words; i += 2) { 7493 if (i == 10) { 7494 continue; 7495 } 7496 word = inpw(iop_base + IOP_RAM_DATA); 7497 inbuf[i] = word & 0xff; 7498 inbuf[i + 1] = (word >> 8) & 0xff; 7499 } 7500 ASC_DBG_PRT_HEX(2, "DvcGetQinfo", inbuf, 2 * words); 7501} 7502 7503static uchar 7504_AscCopyLramScsiDoneQ(PortAddr iop_base, 7505 ushort q_addr, 7506 ASC_QDONE_INFO *scsiq, ASC_DCNT max_dma_count) 7507{ 7508 ushort _val; 7509 uchar sg_queue_cnt; 7510 7511 DvcGetQinfo(iop_base, 7512 q_addr + ASC_SCSIQ_DONE_INFO_BEG, 7513 (uchar *)scsiq, 7514 (sizeof(ASC_SCSIQ_2) + sizeof(ASC_SCSIQ_3)) / 2); 7515 7516 _val = AscReadLramWord(iop_base, 7517 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS)); 7518 scsiq->q_status = (uchar)_val; 7519 scsiq->q_no = (uchar)(_val >> 8); 7520 _val = AscReadLramWord(iop_base, 7521 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_CNTL)); 7522 scsiq->cntl = (uchar)_val; 7523 sg_queue_cnt = (uchar)(_val >> 8); 7524 _val = AscReadLramWord(iop_base, 7525 (ushort)(q_addr + 7526 (ushort)ASC_SCSIQ_B_SENSE_LEN)); 7527 scsiq->sense_len = (uchar)_val; 7528 scsiq->extra_bytes = (uchar)(_val >> 8); 7529 7530 /* 7531 * Read high word of remain bytes from alternate location. 7532 */ 7533 scsiq->remain_bytes = (((ADV_DCNT)AscReadLramWord(iop_base, 7534 (ushort)(q_addr + 7535 (ushort) 7536 ASC_SCSIQ_W_ALT_DC1))) 7537 << 16); 7538 /* 7539 * Read low word of remain bytes from original location. 7540 */ 7541 scsiq->remain_bytes += AscReadLramWord(iop_base, 7542 (ushort)(q_addr + (ushort) 7543 ASC_SCSIQ_DW_REMAIN_XFER_CNT)); 7544 7545 scsiq->remain_bytes &= max_dma_count; 7546 return sg_queue_cnt; 7547} 7548 7549/* 7550 * asc_isr_callback() - Second Level Interrupt Handler called by AscISR(). 7551 * 7552 * Interrupt callback function for the Narrow SCSI Asc Library. 7553 */ 7554static void asc_isr_callback(ASC_DVC_VAR *asc_dvc_varp, ASC_QDONE_INFO *qdonep) 7555{ 7556 struct asc_board *boardp; 7557 struct scsi_cmnd *scp; 7558 struct Scsi_Host *shost; 7559 7560 ASC_DBG(1, "asc_dvc_varp 0x%p, qdonep 0x%p\n", asc_dvc_varp, qdonep); 7561 ASC_DBG_PRT_ASC_QDONE_INFO(2, qdonep); 7562 7563 scp = advansys_srb_to_ptr(asc_dvc_varp, qdonep->d2.srb_ptr); 7564 if (!scp) 7565 return; 7566 7567 ASC_DBG_PRT_CDB(2, scp->cmnd, scp->cmd_len); 7568 7569 shost = scp->device->host; 7570 ASC_STATS(shost, callback); 7571 ASC_DBG(1, "shost 0x%p\n", shost); 7572 7573 boardp = shost_priv(shost); 7574 BUG_ON(asc_dvc_varp != &boardp->dvc_var.asc_dvc_var); 7575 7576 dma_unmap_single(boardp->dev, scp->SCp.dma_handle, 7577 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); 7578 /* 7579 * 'qdonep' contains the command's ending status. 7580 */ 7581 switch (qdonep->d3.done_stat) { 7582 case QD_NO_ERROR: 7583 ASC_DBG(2, "QD_NO_ERROR\n"); 7584 scp->result = 0; 7585 7586 /* 7587 * Check for an underrun condition. 7588 * 7589 * If there was no error and an underrun condition, then 7590 * return the number of underrun bytes. 7591 */ 7592 if (scsi_bufflen(scp) != 0 && qdonep->remain_bytes != 0 && 7593 qdonep->remain_bytes <= scsi_bufflen(scp)) { 7594 ASC_DBG(1, "underrun condition %u bytes\n", 7595 (unsigned)qdonep->remain_bytes); 7596 scsi_set_resid(scp, qdonep->remain_bytes); 7597 } 7598 break; 7599 7600 case QD_WITH_ERROR: 7601 ASC_DBG(2, "QD_WITH_ERROR\n"); 7602 switch (qdonep->d3.host_stat) { 7603 case QHSTA_NO_ERROR: 7604 if (qdonep->d3.scsi_stat == SAM_STAT_CHECK_CONDITION) { 7605 ASC_DBG(2, "SAM_STAT_CHECK_CONDITION\n"); 7606 ASC_DBG_PRT_SENSE(2, scp->sense_buffer, 7607 SCSI_SENSE_BUFFERSIZE); 7608 /* 7609 * Note: The 'status_byte()' macro used by 7610 * target drivers defined in scsi.h shifts the 7611 * status byte returned by host drivers right 7612 * by 1 bit. This is why target drivers also 7613 * use right shifted status byte definitions. 7614 * For instance target drivers use 7615 * CHECK_CONDITION, defined to 0x1, instead of 7616 * the SCSI defined check condition value of 7617 * 0x2. Host drivers are supposed to return 7618 * the status byte as it is defined by SCSI. 7619 */ 7620 scp->result = DRIVER_BYTE(DRIVER_SENSE) | 7621 STATUS_BYTE(qdonep->d3.scsi_stat); 7622 } else { 7623 scp->result = STATUS_BYTE(qdonep->d3.scsi_stat); 7624 } 7625 break; 7626 7627 default: 7628 /* QHSTA error occurred */ 7629 ASC_DBG(1, "host_stat 0x%x\n", qdonep->d3.host_stat); 7630 scp->result = HOST_BYTE(DID_BAD_TARGET); 7631 break; 7632 } 7633 break; 7634 7635 case QD_ABORTED_BY_HOST: 7636 ASC_DBG(1, "QD_ABORTED_BY_HOST\n"); 7637 scp->result = 7638 HOST_BYTE(DID_ABORT) | MSG_BYTE(qdonep->d3. 7639 scsi_msg) | 7640 STATUS_BYTE(qdonep->d3.scsi_stat); 7641 break; 7642 7643 default: 7644 ASC_DBG(1, "done_stat 0x%x\n", qdonep->d3.done_stat); 7645 scp->result = 7646 HOST_BYTE(DID_ERROR) | MSG_BYTE(qdonep->d3. 7647 scsi_msg) | 7648 STATUS_BYTE(qdonep->d3.scsi_stat); 7649 break; 7650 } 7651 7652 /* 7653 * If the 'init_tidmask' bit isn't already set for the target and the 7654 * current request finished normally, then set the bit for the target 7655 * to indicate that a device is present. 7656 */ 7657 if ((boardp->init_tidmask & ADV_TID_TO_TIDMASK(scp->device->id)) == 0 && 7658 qdonep->d3.done_stat == QD_NO_ERROR && 7659 qdonep->d3.host_stat == QHSTA_NO_ERROR) { 7660 boardp->init_tidmask |= ADV_TID_TO_TIDMASK(scp->device->id); 7661 } 7662 7663 asc_scsi_done(scp); 7664} 7665 7666static int AscIsrQDone(ASC_DVC_VAR *asc_dvc) 7667{ 7668 uchar next_qp; 7669 uchar n_q_used; 7670 uchar sg_list_qp; 7671 uchar sg_queue_cnt; 7672 uchar q_cnt; 7673 uchar done_q_tail; 7674 uchar tid_no; 7675 ASC_SCSI_BIT_ID_TYPE scsi_busy; 7676 ASC_SCSI_BIT_ID_TYPE target_id; 7677 PortAddr iop_base; 7678 ushort q_addr; 7679 ushort sg_q_addr; 7680 uchar cur_target_qng; 7681 ASC_QDONE_INFO scsiq_buf; 7682 ASC_QDONE_INFO *scsiq; 7683 int false_overrun; 7684 7685 iop_base = asc_dvc->iop_base; 7686 n_q_used = 1; 7687 scsiq = (ASC_QDONE_INFO *)&scsiq_buf; 7688 done_q_tail = (uchar)AscGetVarDoneQTail(iop_base); 7689 q_addr = ASC_QNO_TO_QADDR(done_q_tail); 7690 next_qp = AscReadLramByte(iop_base, 7691 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_FWD)); 7692 if (next_qp != ASC_QLINK_END) { 7693 AscPutVarDoneQTail(iop_base, next_qp); 7694 q_addr = ASC_QNO_TO_QADDR(next_qp); 7695 sg_queue_cnt = _AscCopyLramScsiDoneQ(iop_base, q_addr, scsiq, 7696 asc_dvc->max_dma_count); 7697 AscWriteLramByte(iop_base, 7698 (ushort)(q_addr + 7699 (ushort)ASC_SCSIQ_B_STATUS), 7700 (uchar)(scsiq-> 7701 q_status & (uchar)~(QS_READY | 7702 QS_ABORTED))); 7703 tid_no = ASC_TIX_TO_TID(scsiq->d2.target_ix); 7704 target_id = ASC_TIX_TO_TARGET_ID(scsiq->d2.target_ix); 7705 if ((scsiq->cntl & QC_SG_HEAD) != 0) { 7706 sg_q_addr = q_addr; 7707 sg_list_qp = next_qp; 7708 for (q_cnt = 0; q_cnt < sg_queue_cnt; q_cnt++) { 7709 sg_list_qp = AscReadLramByte(iop_base, 7710 (ushort)(sg_q_addr 7711 + (ushort) 7712 ASC_SCSIQ_B_FWD)); 7713 sg_q_addr = ASC_QNO_TO_QADDR(sg_list_qp); 7714 if (sg_list_qp == ASC_QLINK_END) { 7715 AscSetLibErrorCode(asc_dvc, 7716 ASCQ_ERR_SG_Q_LINKS); 7717 scsiq->d3.done_stat = QD_WITH_ERROR; 7718 scsiq->d3.host_stat = 7719 QHSTA_D_QDONE_SG_LIST_CORRUPTED; 7720 goto FATAL_ERR_QDONE; 7721 } 7722 AscWriteLramByte(iop_base, 7723 (ushort)(sg_q_addr + (ushort) 7724 ASC_SCSIQ_B_STATUS), 7725 QS_FREE); 7726 } 7727 n_q_used = sg_queue_cnt + 1; 7728 AscPutVarDoneQTail(iop_base, sg_list_qp); 7729 } 7730 if (asc_dvc->queue_full_or_busy & target_id) { 7731 cur_target_qng = AscReadLramByte(iop_base, 7732 (ushort)((ushort) 7733 ASC_QADR_BEG 7734 + (ushort) 7735 scsiq->d2. 7736 target_ix)); 7737 if (cur_target_qng < asc_dvc->max_dvc_qng[tid_no]) { 7738 scsi_busy = AscReadLramByte(iop_base, (ushort) 7739 ASCV_SCSIBUSY_B); 7740 scsi_busy &= ~target_id; 7741 AscWriteLramByte(iop_base, 7742 (ushort)ASCV_SCSIBUSY_B, 7743 scsi_busy); 7744 asc_dvc->queue_full_or_busy &= ~target_id; 7745 } 7746 } 7747 if (asc_dvc->cur_total_qng >= n_q_used) { 7748 asc_dvc->cur_total_qng -= n_q_used; 7749 if (asc_dvc->cur_dvc_qng[tid_no] != 0) { 7750 asc_dvc->cur_dvc_qng[tid_no]--; 7751 } 7752 } else { 7753 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CUR_QNG); 7754 scsiq->d3.done_stat = QD_WITH_ERROR; 7755 goto FATAL_ERR_QDONE; 7756 } 7757 if ((scsiq->d2.srb_ptr == 0UL) || 7758 ((scsiq->q_status & QS_ABORTED) != 0)) { 7759 return (0x11); 7760 } else if (scsiq->q_status == QS_DONE) { 7761 false_overrun = FALSE; 7762 if (scsiq->extra_bytes != 0) { 7763 scsiq->remain_bytes += 7764 (ADV_DCNT)scsiq->extra_bytes; 7765 } 7766 if (scsiq->d3.done_stat == QD_WITH_ERROR) { 7767 if (scsiq->d3.host_stat == 7768 QHSTA_M_DATA_OVER_RUN) { 7769 if ((scsiq-> 7770 cntl & (QC_DATA_IN | QC_DATA_OUT)) 7771 == 0) { 7772 scsiq->d3.done_stat = 7773 QD_NO_ERROR; 7774 scsiq->d3.host_stat = 7775 QHSTA_NO_ERROR; 7776 } else if (false_overrun) { 7777 scsiq->d3.done_stat = 7778 QD_NO_ERROR; 7779 scsiq->d3.host_stat = 7780 QHSTA_NO_ERROR; 7781 } 7782 } else if (scsiq->d3.host_stat == 7783 QHSTA_M_HUNG_REQ_SCSI_BUS_RESET) { 7784 AscStopChip(iop_base); 7785 AscSetChipControl(iop_base, 7786 (uchar)(CC_SCSI_RESET 7787 | CC_HALT)); 7788 udelay(60); 7789 AscSetChipControl(iop_base, CC_HALT); 7790 AscSetChipStatus(iop_base, 7791 CIW_CLR_SCSI_RESET_INT); 7792 AscSetChipStatus(iop_base, 0); 7793 AscSetChipControl(iop_base, 0); 7794 } 7795 } 7796 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) { 7797 asc_isr_callback(asc_dvc, scsiq); 7798 } else { 7799 if ((AscReadLramByte(iop_base, 7800 (ushort)(q_addr + (ushort) 7801 ASC_SCSIQ_CDB_BEG)) 7802 == START_STOP)) { 7803 asc_dvc->unit_not_ready &= ~target_id; 7804 if (scsiq->d3.done_stat != QD_NO_ERROR) { 7805 asc_dvc->start_motor &= 7806 ~target_id; 7807 } 7808 } 7809 } 7810 return (1); 7811 } else { 7812 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_Q_STATUS); 7813 FATAL_ERR_QDONE: 7814 if ((scsiq->cntl & QC_NO_CALLBACK) == 0) { 7815 asc_isr_callback(asc_dvc, scsiq); 7816 } 7817 return (0x80); 7818 } 7819 } 7820 return (0); 7821} 7822 7823static int AscISR(ASC_DVC_VAR *asc_dvc) 7824{ 7825 ASC_CS_TYPE chipstat; 7826 PortAddr iop_base; 7827 ushort saved_ram_addr; 7828 uchar ctrl_reg; 7829 uchar saved_ctrl_reg; 7830 int int_pending; 7831 int status; 7832 uchar host_flag; 7833 7834 iop_base = asc_dvc->iop_base; 7835 int_pending = FALSE; 7836 7837 if (AscIsIntPending(iop_base) == 0) 7838 return int_pending; 7839 7840 if ((asc_dvc->init_state & ASC_INIT_STATE_END_LOAD_MC) == 0) { 7841 return ERR; 7842 } 7843 if (asc_dvc->in_critical_cnt != 0) { 7844 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_ON_CRITICAL); 7845 return ERR; 7846 } 7847 if (asc_dvc->is_in_int) { 7848 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_ISR_RE_ENTRY); 7849 return ERR; 7850 } 7851 asc_dvc->is_in_int = TRUE; 7852 ctrl_reg = AscGetChipControl(iop_base); 7853 saved_ctrl_reg = ctrl_reg & (~(CC_SCSI_RESET | CC_CHIP_RESET | 7854 CC_SINGLE_STEP | CC_DIAG | CC_TEST)); 7855 chipstat = AscGetChipStatus(iop_base); 7856 if (chipstat & CSW_SCSI_RESET_LATCH) { 7857 if (!(asc_dvc->bus_type & (ASC_IS_VL | ASC_IS_EISA))) { 7858 int i = 10; 7859 int_pending = TRUE; 7860 asc_dvc->sdtr_done = 0; 7861 saved_ctrl_reg &= (uchar)(~CC_HALT); 7862 while ((AscGetChipStatus(iop_base) & 7863 CSW_SCSI_RESET_ACTIVE) && (i-- > 0)) { 7864 mdelay(100); 7865 } 7866 AscSetChipControl(iop_base, (CC_CHIP_RESET | CC_HALT)); 7867 AscSetChipControl(iop_base, CC_HALT); 7868 AscSetChipStatus(iop_base, CIW_CLR_SCSI_RESET_INT); 7869 AscSetChipStatus(iop_base, 0); 7870 chipstat = AscGetChipStatus(iop_base); 7871 } 7872 } 7873 saved_ram_addr = AscGetChipLramAddr(iop_base); 7874 host_flag = AscReadLramByte(iop_base, 7875 ASCV_HOST_FLAG_B) & 7876 (uchar)(~ASC_HOST_FLAG_IN_ISR); 7877 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, 7878 (uchar)(host_flag | (uchar)ASC_HOST_FLAG_IN_ISR)); 7879 if ((chipstat & CSW_INT_PENDING) || (int_pending)) { 7880 AscAckInterrupt(iop_base); 7881 int_pending = TRUE; 7882 if ((chipstat & CSW_HALTED) && (ctrl_reg & CC_SINGLE_STEP)) { 7883 if (AscIsrChipHalted(asc_dvc) == ERR) { 7884 goto ISR_REPORT_QDONE_FATAL_ERROR; 7885 } else { 7886 saved_ctrl_reg &= (uchar)(~CC_HALT); 7887 } 7888 } else { 7889 ISR_REPORT_QDONE_FATAL_ERROR: 7890 if ((asc_dvc->dvc_cntl & ASC_CNTL_INT_MULTI_Q) != 0) { 7891 while (((status = 7892 AscIsrQDone(asc_dvc)) & 0x01) != 0) { 7893 } 7894 } else { 7895 do { 7896 if ((status = 7897 AscIsrQDone(asc_dvc)) == 1) { 7898 break; 7899 } 7900 } while (status == 0x11); 7901 } 7902 if ((status & 0x80) != 0) 7903 int_pending = ERR; 7904 } 7905 } 7906 AscWriteLramByte(iop_base, ASCV_HOST_FLAG_B, host_flag); 7907 AscSetChipLramAddr(iop_base, saved_ram_addr); 7908 AscSetChipControl(iop_base, saved_ctrl_reg); 7909 asc_dvc->is_in_int = FALSE; 7910 return int_pending; 7911} 7912 7913/* 7914 * advansys_reset() 7915 * 7916 * Reset the bus associated with the command 'scp'. 7917 * 7918 * This function runs its own thread. Interrupts must be blocked but 7919 * sleeping is allowed and no locking other than for host structures is 7920 * required. Returns SUCCESS or FAILED. 7921 */ 7922static int advansys_reset(struct scsi_cmnd *scp) 7923{ 7924 struct Scsi_Host *shost = scp->device->host; 7925 struct asc_board *boardp = shost_priv(shost); 7926 unsigned long flags; 7927 int status; 7928 int ret = SUCCESS; 7929 7930 ASC_DBG(1, "0x%p\n", scp); 7931 7932 ASC_STATS(shost, reset); 7933 7934 scmd_printk(KERN_INFO, scp, "SCSI bus reset started...\n"); 7935 7936 if (ASC_NARROW_BOARD(boardp)) { 7937 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var; 7938 7939 /* Reset the chip and SCSI bus. */ 7940 ASC_DBG(1, "before AscInitAsc1000Driver()\n"); 7941 status = AscInitAsc1000Driver(asc_dvc); 7942 7943 /* Refer to ASC_IERR_* definitions for meaning of 'err_code'. */ 7944 if (asc_dvc->err_code || !asc_dvc->overrun_dma) { 7945 scmd_printk(KERN_INFO, scp, "SCSI bus reset error: " 7946 "0x%x, status: 0x%x\n", asc_dvc->err_code, 7947 status); 7948 ret = FAILED; 7949 } else if (status) { 7950 scmd_printk(KERN_INFO, scp, "SCSI bus reset warning: " 7951 "0x%x\n", status); 7952 } else { 7953 scmd_printk(KERN_INFO, scp, "SCSI bus reset " 7954 "successful\n"); 7955 } 7956 7957 ASC_DBG(1, "after AscInitAsc1000Driver()\n"); 7958 spin_lock_irqsave(shost->host_lock, flags); 7959 } else { 7960 /* 7961 * If the suggest reset bus flags are set, then reset the bus. 7962 * Otherwise only reset the device. 7963 */ 7964 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var; 7965 7966 /* 7967 * Reset the target's SCSI bus. 7968 */ 7969 ASC_DBG(1, "before AdvResetChipAndSB()\n"); 7970 switch (AdvResetChipAndSB(adv_dvc)) { 7971 case ASC_TRUE: 7972 scmd_printk(KERN_INFO, scp, "SCSI bus reset " 7973 "successful\n"); 7974 break; 7975 case ASC_FALSE: 7976 default: 7977 scmd_printk(KERN_INFO, scp, "SCSI bus reset error\n"); 7978 ret = FAILED; 7979 break; 7980 } 7981 spin_lock_irqsave(shost->host_lock, flags); 7982 AdvISR(adv_dvc); 7983 } 7984 7985 /* Save the time of the most recently completed reset. */ 7986 boardp->last_reset = jiffies; 7987 spin_unlock_irqrestore(shost->host_lock, flags); 7988 7989 ASC_DBG(1, "ret %d\n", ret); 7990 7991 return ret; 7992} 7993 7994/* 7995 * advansys_biosparam() 7996 * 7997 * Translate disk drive geometry if the "BIOS greater than 1 GB" 7998 * support is enabled for a drive. 7999 * 8000 * ip (information pointer) is an int array with the following definition: 8001 * ip[0]: heads 8002 * ip[1]: sectors 8003 * ip[2]: cylinders 8004 */ 8005static int 8006advansys_biosparam(struct scsi_device *sdev, struct block_device *bdev, 8007 sector_t capacity, int ip[]) 8008{ 8009 struct asc_board *boardp = shost_priv(sdev->host); 8010 8011 ASC_DBG(1, "begin\n"); 8012 ASC_STATS(sdev->host, biosparam); 8013 if (ASC_NARROW_BOARD(boardp)) { 8014 if ((boardp->dvc_var.asc_dvc_var.dvc_cntl & 8015 ASC_CNTL_BIOS_GT_1GB) && capacity > 0x200000) { 8016 ip[0] = 255; 8017 ip[1] = 63; 8018 } else { 8019 ip[0] = 64; 8020 ip[1] = 32; 8021 } 8022 } else { 8023 if ((boardp->dvc_var.adv_dvc_var.bios_ctrl & 8024 BIOS_CTRL_EXTENDED_XLAT) && capacity > 0x200000) { 8025 ip[0] = 255; 8026 ip[1] = 63; 8027 } else { 8028 ip[0] = 64; 8029 ip[1] = 32; 8030 } 8031 } 8032 ip[2] = (unsigned long)capacity / (ip[0] * ip[1]); 8033 ASC_DBG(1, "end\n"); 8034 return 0; 8035} 8036 8037/* 8038 * First-level interrupt handler. 8039 * 8040 * 'dev_id' is a pointer to the interrupting adapter's Scsi_Host. 8041 */ 8042static irqreturn_t advansys_interrupt(int irq, void *dev_id) 8043{ 8044 struct Scsi_Host *shost = dev_id; 8045 struct asc_board *boardp = shost_priv(shost); 8046 irqreturn_t result = IRQ_NONE; 8047 8048 ASC_DBG(2, "boardp 0x%p\n", boardp); 8049 spin_lock(shost->host_lock); 8050 if (ASC_NARROW_BOARD(boardp)) { 8051 if (AscIsIntPending(shost->io_port)) { 8052 result = IRQ_HANDLED; 8053 ASC_STATS(shost, interrupt); 8054 ASC_DBG(1, "before AscISR()\n"); 8055 AscISR(&boardp->dvc_var.asc_dvc_var); 8056 } 8057 } else { 8058 ASC_DBG(1, "before AdvISR()\n"); 8059 if (AdvISR(&boardp->dvc_var.adv_dvc_var)) { 8060 result = IRQ_HANDLED; 8061 ASC_STATS(shost, interrupt); 8062 } 8063 } 8064 spin_unlock(shost->host_lock); 8065 8066 ASC_DBG(1, "end\n"); 8067 return result; 8068} 8069 8070static int AscHostReqRiscHalt(PortAddr iop_base) 8071{ 8072 int count = 0; 8073 int sta = 0; 8074 uchar saved_stop_code; 8075 8076 if (AscIsChipHalted(iop_base)) 8077 return (1); 8078 saved_stop_code = AscReadLramByte(iop_base, ASCV_STOP_CODE_B); 8079 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 8080 ASC_STOP_HOST_REQ_RISC_HALT | ASC_STOP_REQ_RISC_STOP); 8081 do { 8082 if (AscIsChipHalted(iop_base)) { 8083 sta = 1; 8084 break; 8085 } 8086 mdelay(100); 8087 } while (count++ < 20); 8088 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, saved_stop_code); 8089 return (sta); 8090} 8091 8092static int 8093AscSetRunChipSynRegAtID(PortAddr iop_base, uchar tid_no, uchar sdtr_data) 8094{ 8095 int sta = FALSE; 8096 8097 if (AscHostReqRiscHalt(iop_base)) { 8098 sta = AscSetChipSynRegAtID(iop_base, tid_no, sdtr_data); 8099 AscStartChip(iop_base); 8100 } 8101 return sta; 8102} 8103 8104static void AscAsyncFix(ASC_DVC_VAR *asc_dvc, struct scsi_device *sdev) 8105{ 8106 char type = sdev->type; 8107 ASC_SCSI_BIT_ID_TYPE tid_bits = 1 << sdev->id; 8108 8109 if (!(asc_dvc->bug_fix_cntl & ASC_BUG_FIX_ASYN_USE_SYN)) 8110 return; 8111 if (asc_dvc->init_sdtr & tid_bits) 8112 return; 8113 8114 if ((type == TYPE_ROM) && (strncmp(sdev->vendor, "HP ", 3) == 0)) 8115 asc_dvc->pci_fix_asyn_xfer_always |= tid_bits; 8116 8117 asc_dvc->pci_fix_asyn_xfer |= tid_bits; 8118 if ((type == TYPE_PROCESSOR) || (type == TYPE_SCANNER) || 8119 (type == TYPE_ROM) || (type == TYPE_TAPE)) 8120 asc_dvc->pci_fix_asyn_xfer &= ~tid_bits; 8121 8122 if (asc_dvc->pci_fix_asyn_xfer & tid_bits) 8123 AscSetRunChipSynRegAtID(asc_dvc->iop_base, sdev->id, 8124 ASYN_SDTR_DATA_FIX_PCI_REV_AB); 8125} 8126 8127static void 8128advansys_narrow_slave_configure(struct scsi_device *sdev, ASC_DVC_VAR *asc_dvc) 8129{ 8130 ASC_SCSI_BIT_ID_TYPE tid_bit = 1 << sdev->id; 8131 ASC_SCSI_BIT_ID_TYPE orig_use_tagged_qng = asc_dvc->use_tagged_qng; 8132 8133 if (sdev->lun == 0) { 8134 ASC_SCSI_BIT_ID_TYPE orig_init_sdtr = asc_dvc->init_sdtr; 8135 if ((asc_dvc->cfg->sdtr_enable & tid_bit) && sdev->sdtr) { 8136 asc_dvc->init_sdtr |= tid_bit; 8137 } else { 8138 asc_dvc->init_sdtr &= ~tid_bit; 8139 } 8140 8141 if (orig_init_sdtr != asc_dvc->init_sdtr) 8142 AscAsyncFix(asc_dvc, sdev); 8143 } 8144 8145 if (sdev->tagged_supported) { 8146 if (asc_dvc->cfg->cmd_qng_enabled & tid_bit) { 8147 if (sdev->lun == 0) { 8148 asc_dvc->cfg->can_tagged_qng |= tid_bit; 8149 asc_dvc->use_tagged_qng |= tid_bit; 8150 } 8151 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, 8152 asc_dvc->max_dvc_qng[sdev->id]); 8153 } 8154 } else { 8155 if (sdev->lun == 0) { 8156 asc_dvc->cfg->can_tagged_qng &= ~tid_bit; 8157 asc_dvc->use_tagged_qng &= ~tid_bit; 8158 } 8159 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun); 8160 } 8161 8162 if ((sdev->lun == 0) && 8163 (orig_use_tagged_qng != asc_dvc->use_tagged_qng)) { 8164 AscWriteLramByte(asc_dvc->iop_base, ASCV_DISC_ENABLE_B, 8165 asc_dvc->cfg->disc_enable); 8166 AscWriteLramByte(asc_dvc->iop_base, ASCV_USE_TAGGED_QNG_B, 8167 asc_dvc->use_tagged_qng); 8168 AscWriteLramByte(asc_dvc->iop_base, ASCV_CAN_TAGGED_QNG_B, 8169 asc_dvc->cfg->can_tagged_qng); 8170 8171 asc_dvc->max_dvc_qng[sdev->id] = 8172 asc_dvc->cfg->max_tag_qng[sdev->id]; 8173 AscWriteLramByte(asc_dvc->iop_base, 8174 (ushort)(ASCV_MAX_DVC_QNG_BEG + sdev->id), 8175 asc_dvc->max_dvc_qng[sdev->id]); 8176 } 8177} 8178 8179/* 8180 * Wide Transfers 8181 * 8182 * If the EEPROM enabled WDTR for the device and the device supports wide 8183 * bus (16 bit) transfers, then turn on the device's 'wdtr_able' bit and 8184 * write the new value to the microcode. 8185 */ 8186static void 8187advansys_wide_enable_wdtr(AdvPortAddr iop_base, unsigned short tidmask) 8188{ 8189 unsigned short cfg_word; 8190 AdvReadWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word); 8191 if ((cfg_word & tidmask) != 0) 8192 return; 8193 8194 cfg_word |= tidmask; 8195 AdvWriteWordLram(iop_base, ASC_MC_WDTR_ABLE, cfg_word); 8196 8197 /* 8198 * Clear the microcode SDTR and WDTR negotiation done indicators for 8199 * the target to cause it to negotiate with the new setting set above. 8200 * WDTR when accepted causes the target to enter asynchronous mode, so 8201 * SDTR must be negotiated. 8202 */ 8203 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 8204 cfg_word &= ~tidmask; 8205 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 8206 AdvReadWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word); 8207 cfg_word &= ~tidmask; 8208 AdvWriteWordLram(iop_base, ASC_MC_WDTR_DONE, cfg_word); 8209} 8210 8211/* 8212 * Synchronous Transfers 8213 * 8214 * If the EEPROM enabled SDTR for the device and the device 8215 * supports synchronous transfers, then turn on the device's 8216 * 'sdtr_able' bit. Write the new value to the microcode. 8217 */ 8218static void 8219advansys_wide_enable_sdtr(AdvPortAddr iop_base, unsigned short tidmask) 8220{ 8221 unsigned short cfg_word; 8222 AdvReadWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word); 8223 if ((cfg_word & tidmask) != 0) 8224 return; 8225 8226 cfg_word |= tidmask; 8227 AdvWriteWordLram(iop_base, ASC_MC_SDTR_ABLE, cfg_word); 8228 8229 /* 8230 * Clear the microcode "SDTR negotiation" done indicator for the 8231 * target to cause it to negotiate with the new setting set above. 8232 */ 8233 AdvReadWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 8234 cfg_word &= ~tidmask; 8235 AdvWriteWordLram(iop_base, ASC_MC_SDTR_DONE, cfg_word); 8236} 8237 8238/* 8239 * PPR (Parallel Protocol Request) Capable 8240 * 8241 * If the device supports DT mode, then it must be PPR capable. 8242 * The PPR message will be used in place of the SDTR and WDTR 8243 * messages to negotiate synchronous speed and offset, transfer 8244 * width, and protocol options. 8245 */ 8246static void advansys_wide_enable_ppr(ADV_DVC_VAR *adv_dvc, 8247 AdvPortAddr iop_base, unsigned short tidmask) 8248{ 8249 AdvReadWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able); 8250 adv_dvc->ppr_able |= tidmask; 8251 AdvWriteWordLram(iop_base, ASC_MC_PPR_ABLE, adv_dvc->ppr_able); 8252} 8253 8254static void 8255advansys_wide_slave_configure(struct scsi_device *sdev, ADV_DVC_VAR *adv_dvc) 8256{ 8257 AdvPortAddr iop_base = adv_dvc->iop_base; 8258 unsigned short tidmask = 1 << sdev->id; 8259 8260 if (sdev->lun == 0) { 8261 /* 8262 * Handle WDTR, SDTR, and Tag Queuing. If the feature 8263 * is enabled in the EEPROM and the device supports the 8264 * feature, then enable it in the microcode. 8265 */ 8266 8267 if ((adv_dvc->wdtr_able & tidmask) && sdev->wdtr) 8268 advansys_wide_enable_wdtr(iop_base, tidmask); 8269 if ((adv_dvc->sdtr_able & tidmask) && sdev->sdtr) 8270 advansys_wide_enable_sdtr(iop_base, tidmask); 8271 if (adv_dvc->chip_type == ADV_CHIP_ASC38C1600 && sdev->ppr) 8272 advansys_wide_enable_ppr(adv_dvc, iop_base, tidmask); 8273 8274 /* 8275 * Tag Queuing is disabled for the BIOS which runs in polled 8276 * mode and would see no benefit from Tag Queuing. Also by 8277 * disabling Tag Queuing in the BIOS devices with Tag Queuing 8278 * bugs will at least work with the BIOS. 8279 */ 8280 if ((adv_dvc->tagqng_able & tidmask) && 8281 sdev->tagged_supported) { 8282 unsigned short cfg_word; 8283 AdvReadWordLram(iop_base, ASC_MC_TAGQNG_ABLE, cfg_word); 8284 cfg_word |= tidmask; 8285 AdvWriteWordLram(iop_base, ASC_MC_TAGQNG_ABLE, 8286 cfg_word); 8287 AdvWriteByteLram(iop_base, 8288 ASC_MC_NUMBER_OF_MAX_CMD + sdev->id, 8289 adv_dvc->max_dvc_qng); 8290 } 8291 } 8292 8293 if ((adv_dvc->tagqng_able & tidmask) && sdev->tagged_supported) { 8294 scsi_adjust_queue_depth(sdev, MSG_ORDERED_TAG, 8295 adv_dvc->max_dvc_qng); 8296 } else { 8297 scsi_adjust_queue_depth(sdev, 0, sdev->host->cmd_per_lun); 8298 } 8299} 8300 8301/* 8302 * Set the number of commands to queue per device for the 8303 * specified host adapter. 8304 */ 8305static int advansys_slave_configure(struct scsi_device *sdev) 8306{ 8307 struct asc_board *boardp = shost_priv(sdev->host); 8308 8309 if (ASC_NARROW_BOARD(boardp)) 8310 advansys_narrow_slave_configure(sdev, 8311 &boardp->dvc_var.asc_dvc_var); 8312 else 8313 advansys_wide_slave_configure(sdev, 8314 &boardp->dvc_var.adv_dvc_var); 8315 8316 return 0; 8317} 8318 8319static __le32 advansys_get_sense_buffer_dma(struct scsi_cmnd *scp) 8320{ 8321 struct asc_board *board = shost_priv(scp->device->host); 8322 scp->SCp.dma_handle = dma_map_single(board->dev, scp->sense_buffer, 8323 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); 8324 dma_cache_sync(board->dev, scp->sense_buffer, 8325 SCSI_SENSE_BUFFERSIZE, DMA_FROM_DEVICE); 8326 return cpu_to_le32(scp->SCp.dma_handle); 8327} 8328 8329static int asc_build_req(struct asc_board *boardp, struct scsi_cmnd *scp, 8330 struct asc_scsi_q *asc_scsi_q) 8331{ 8332 struct asc_dvc_var *asc_dvc = &boardp->dvc_var.asc_dvc_var; 8333 int use_sg; 8334 8335 memset(asc_scsi_q, 0, sizeof(*asc_scsi_q)); 8336 8337 /* 8338 * Point the ASC_SCSI_Q to the 'struct scsi_cmnd'. 8339 */ 8340 asc_scsi_q->q2.srb_ptr = advansys_ptr_to_srb(asc_dvc, scp); 8341 if (asc_scsi_q->q2.srb_ptr == BAD_SRB) { 8342 scp->result = HOST_BYTE(DID_SOFT_ERROR); 8343 return ASC_ERROR; 8344 } 8345 8346 /* 8347 * Build the ASC_SCSI_Q request. 8348 */ 8349 asc_scsi_q->cdbptr = &scp->cmnd[0]; 8350 asc_scsi_q->q2.cdb_len = scp->cmd_len; 8351 asc_scsi_q->q1.target_id = ASC_TID_TO_TARGET_ID(scp->device->id); 8352 asc_scsi_q->q1.target_lun = scp->device->lun; 8353 asc_scsi_q->q2.target_ix = 8354 ASC_TIDLUN_TO_IX(scp->device->id, scp->device->lun); 8355 asc_scsi_q->q1.sense_addr = advansys_get_sense_buffer_dma(scp); 8356 asc_scsi_q->q1.sense_len = SCSI_SENSE_BUFFERSIZE; 8357 8358 /* 8359 * If there are any outstanding requests for the current target, 8360 * then every 255th request send an ORDERED request. This heuristic 8361 * tries to retain the benefit of request sorting while preventing 8362 * request starvation. 255 is the max number of tags or pending commands 8363 * a device may have outstanding. 8364 * 8365 * The request count is incremented below for every successfully 8366 * started request. 8367 * 8368 */ 8369 if ((asc_dvc->cur_dvc_qng[scp->device->id] > 0) && 8370 (boardp->reqcnt[scp->device->id] % 255) == 0) { 8371 asc_scsi_q->q2.tag_code = MSG_ORDERED_TAG; 8372 } else { 8373 asc_scsi_q->q2.tag_code = MSG_SIMPLE_TAG; 8374 } 8375 8376 /* Build ASC_SCSI_Q */ 8377 use_sg = scsi_dma_map(scp); 8378 if (use_sg != 0) { 8379 int sgcnt; 8380 struct scatterlist *slp; 8381 struct asc_sg_head *asc_sg_head; 8382 8383 if (use_sg > scp->device->host->sg_tablesize) { 8384 scmd_printk(KERN_ERR, scp, "use_sg %d > " 8385 "sg_tablesize %d\n", use_sg, 8386 scp->device->host->sg_tablesize); 8387 scsi_dma_unmap(scp); 8388 scp->result = HOST_BYTE(DID_ERROR); 8389 return ASC_ERROR; 8390 } 8391 8392 asc_sg_head = kzalloc(sizeof(asc_scsi_q->sg_head) + 8393 use_sg * sizeof(struct asc_sg_list), GFP_ATOMIC); 8394 if (!asc_sg_head) { 8395 scsi_dma_unmap(scp); 8396 scp->result = HOST_BYTE(DID_SOFT_ERROR); 8397 return ASC_ERROR; 8398 } 8399 8400 asc_scsi_q->q1.cntl |= QC_SG_HEAD; 8401 asc_scsi_q->sg_head = asc_sg_head; 8402 asc_scsi_q->q1.data_cnt = 0; 8403 asc_scsi_q->q1.data_addr = 0; 8404 /* This is a byte value, otherwise it would need to be swapped. */ 8405 asc_sg_head->entry_cnt = asc_scsi_q->q1.sg_queue_cnt = use_sg; 8406 ASC_STATS_ADD(scp->device->host, xfer_elem, 8407 asc_sg_head->entry_cnt); 8408 8409 /* 8410 * Convert scatter-gather list into ASC_SG_HEAD list. 8411 */ 8412 scsi_for_each_sg(scp, slp, use_sg, sgcnt) { 8413 asc_sg_head->sg_list[sgcnt].addr = 8414 cpu_to_le32(sg_dma_address(slp)); 8415 asc_sg_head->sg_list[sgcnt].bytes = 8416 cpu_to_le32(sg_dma_len(slp)); 8417 ASC_STATS_ADD(scp->device->host, xfer_sect, 8418 DIV_ROUND_UP(sg_dma_len(slp), 512)); 8419 } 8420 } 8421 8422 ASC_STATS(scp->device->host, xfer_cnt); 8423 8424 ASC_DBG_PRT_ASC_SCSI_Q(2, asc_scsi_q); 8425 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len); 8426 8427 return ASC_NOERROR; 8428} 8429 8430/* 8431 * Build scatter-gather list for Adv Library (Wide Board). 8432 * 8433 * Additional ADV_SG_BLOCK structures will need to be allocated 8434 * if the total number of scatter-gather elements exceeds 8435 * NO_OF_SG_PER_BLOCK (15). The ADV_SG_BLOCK structures are 8436 * assumed to be physically contiguous. 8437 * 8438 * Return: 8439 * ADV_SUCCESS(1) - SG List successfully created 8440 * ADV_ERROR(-1) - SG List creation failed 8441 */ 8442static int 8443adv_get_sglist(struct asc_board *boardp, adv_req_t *reqp, struct scsi_cmnd *scp, 8444 int use_sg) 8445{ 8446 adv_sgblk_t *sgblkp; 8447 ADV_SCSI_REQ_Q *scsiqp; 8448 struct scatterlist *slp; 8449 int sg_elem_cnt; 8450 ADV_SG_BLOCK *sg_block, *prev_sg_block; 8451 ADV_PADDR sg_block_paddr; 8452 int i; 8453 8454 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q); 8455 slp = scsi_sglist(scp); 8456 sg_elem_cnt = use_sg; 8457 prev_sg_block = NULL; 8458 reqp->sgblkp = NULL; 8459 8460 for (;;) { 8461 /* 8462 * Allocate a 'adv_sgblk_t' structure from the board free 8463 * list. One 'adv_sgblk_t' structure holds NO_OF_SG_PER_BLOCK 8464 * (15) scatter-gather elements. 8465 */ 8466 if ((sgblkp = boardp->adv_sgblkp) == NULL) { 8467 ASC_DBG(1, "no free adv_sgblk_t\n"); 8468 ASC_STATS(scp->device->host, adv_build_nosg); 8469 8470 /* 8471 * Allocation failed. Free 'adv_sgblk_t' structures 8472 * already allocated for the request. 8473 */ 8474 while ((sgblkp = reqp->sgblkp) != NULL) { 8475 /* Remove 'sgblkp' from the request list. */ 8476 reqp->sgblkp = sgblkp->next_sgblkp; 8477 8478 /* Add 'sgblkp' to the board free list. */ 8479 sgblkp->next_sgblkp = boardp->adv_sgblkp; 8480 boardp->adv_sgblkp = sgblkp; 8481 } 8482 return ASC_BUSY; 8483 } 8484 8485 /* Complete 'adv_sgblk_t' board allocation. */ 8486 boardp->adv_sgblkp = sgblkp->next_sgblkp; 8487 sgblkp->next_sgblkp = NULL; 8488 8489 /* 8490 * Get 8 byte aligned virtual and physical addresses 8491 * for the allocated ADV_SG_BLOCK structure. 8492 */ 8493 sg_block = (ADV_SG_BLOCK *)ADV_8BALIGN(&sgblkp->sg_block); 8494 sg_block_paddr = virt_to_bus(sg_block); 8495 8496 /* 8497 * Check if this is the first 'adv_sgblk_t' for the 8498 * request. 8499 */ 8500 if (reqp->sgblkp == NULL) { 8501 /* Request's first scatter-gather block. */ 8502 reqp->sgblkp = sgblkp; 8503 8504 /* 8505 * Set ADV_SCSI_REQ_T ADV_SG_BLOCK virtual and physical 8506 * address pointers. 8507 */ 8508 scsiqp->sg_list_ptr = sg_block; 8509 scsiqp->sg_real_addr = cpu_to_le32(sg_block_paddr); 8510 } else { 8511 /* Request's second or later scatter-gather block. */ 8512 sgblkp->next_sgblkp = reqp->sgblkp; 8513 reqp->sgblkp = sgblkp; 8514 8515 /* 8516 * Point the previous ADV_SG_BLOCK structure to 8517 * the newly allocated ADV_SG_BLOCK structure. 8518 */ 8519 prev_sg_block->sg_ptr = cpu_to_le32(sg_block_paddr); 8520 } 8521 8522 for (i = 0; i < NO_OF_SG_PER_BLOCK; i++) { 8523 sg_block->sg_list[i].sg_addr = 8524 cpu_to_le32(sg_dma_address(slp)); 8525 sg_block->sg_list[i].sg_count = 8526 cpu_to_le32(sg_dma_len(slp)); 8527 ASC_STATS_ADD(scp->device->host, xfer_sect, 8528 DIV_ROUND_UP(sg_dma_len(slp), 512)); 8529 8530 if (--sg_elem_cnt == 0) { /* Last ADV_SG_BLOCK and scatter-gather entry. */ 8531 sg_block->sg_cnt = i + 1; 8532 sg_block->sg_ptr = 0L; /* Last ADV_SG_BLOCK in list. */ 8533 return ADV_SUCCESS; 8534 } 8535 slp++; 8536 } 8537 sg_block->sg_cnt = NO_OF_SG_PER_BLOCK; 8538 prev_sg_block = sg_block; 8539 } 8540} 8541 8542/* 8543 * Build a request structure for the Adv Library (Wide Board). 8544 * 8545 * If an adv_req_t can not be allocated to issue the request, 8546 * then return ASC_BUSY. If an error occurs, then return ASC_ERROR. 8547 * 8548 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the 8549 * microcode for DMA addresses or math operations are byte swapped 8550 * to little-endian order. 8551 */ 8552static int 8553adv_build_req(struct asc_board *boardp, struct scsi_cmnd *scp, 8554 ADV_SCSI_REQ_Q **adv_scsiqpp) 8555{ 8556 adv_req_t *reqp; 8557 ADV_SCSI_REQ_Q *scsiqp; 8558 int i; 8559 int ret; 8560 int use_sg; 8561 8562 /* 8563 * Allocate an adv_req_t structure from the board to execute 8564 * the command. 8565 */ 8566 if (boardp->adv_reqp == NULL) { 8567 ASC_DBG(1, "no free adv_req_t\n"); 8568 ASC_STATS(scp->device->host, adv_build_noreq); 8569 return ASC_BUSY; 8570 } else { 8571 reqp = boardp->adv_reqp; 8572 boardp->adv_reqp = reqp->next_reqp; 8573 reqp->next_reqp = NULL; 8574 } 8575 8576 /* 8577 * Get 32-byte aligned ADV_SCSI_REQ_Q and ADV_SG_BLOCK pointers. 8578 */ 8579 scsiqp = (ADV_SCSI_REQ_Q *)ADV_32BALIGN(&reqp->scsi_req_q); 8580 8581 /* 8582 * Initialize the structure. 8583 */ 8584 scsiqp->cntl = scsiqp->scsi_cntl = scsiqp->done_status = 0; 8585 8586 /* 8587 * Set the ADV_SCSI_REQ_Q 'srb_ptr' to point to the adv_req_t structure. 8588 */ 8589 scsiqp->srb_ptr = ADV_VADDR_TO_U32(reqp); 8590 8591 /* 8592 * Set the adv_req_t 'cmndp' to point to the struct scsi_cmnd structure. 8593 */ 8594 reqp->cmndp = scp; 8595 8596 /* 8597 * Build the ADV_SCSI_REQ_Q request. 8598 */ 8599 8600 /* Set CDB length and copy it to the request structure. */ 8601 scsiqp->cdb_len = scp->cmd_len; 8602 /* Copy first 12 CDB bytes to cdb[]. */ 8603 for (i = 0; i < scp->cmd_len && i < 12; i++) { 8604 scsiqp->cdb[i] = scp->cmnd[i]; 8605 } 8606 /* Copy last 4 CDB bytes, if present, to cdb16[]. */ 8607 for (; i < scp->cmd_len; i++) { 8608 scsiqp->cdb16[i - 12] = scp->cmnd[i]; 8609 } 8610 8611 scsiqp->target_id = scp->device->id; 8612 scsiqp->target_lun = scp->device->lun; 8613 8614 scsiqp->sense_addr = cpu_to_le32(virt_to_bus(&scp->sense_buffer[0])); 8615 scsiqp->sense_len = SCSI_SENSE_BUFFERSIZE; 8616 8617 /* Build ADV_SCSI_REQ_Q */ 8618 8619 use_sg = scsi_dma_map(scp); 8620 if (use_sg == 0) { 8621 /* Zero-length transfer */ 8622 reqp->sgblkp = NULL; 8623 scsiqp->data_cnt = 0; 8624 scsiqp->vdata_addr = NULL; 8625 8626 scsiqp->data_addr = 0; 8627 scsiqp->sg_list_ptr = NULL; 8628 scsiqp->sg_real_addr = 0; 8629 } else { 8630 if (use_sg > ADV_MAX_SG_LIST) { 8631 scmd_printk(KERN_ERR, scp, "use_sg %d > " 8632 "ADV_MAX_SG_LIST %d\n", use_sg, 8633 scp->device->host->sg_tablesize); 8634 scsi_dma_unmap(scp); 8635 scp->result = HOST_BYTE(DID_ERROR); 8636 8637 /* 8638 * Free the 'adv_req_t' structure by adding it back 8639 * to the board free list. 8640 */ 8641 reqp->next_reqp = boardp->adv_reqp; 8642 boardp->adv_reqp = reqp; 8643 8644 return ASC_ERROR; 8645 } 8646 8647 scsiqp->data_cnt = cpu_to_le32(scsi_bufflen(scp)); 8648 8649 ret = adv_get_sglist(boardp, reqp, scp, use_sg); 8650 if (ret != ADV_SUCCESS) { 8651 /* 8652 * Free the adv_req_t structure by adding it back to 8653 * the board free list. 8654 */ 8655 reqp->next_reqp = boardp->adv_reqp; 8656 boardp->adv_reqp = reqp; 8657 8658 return ret; 8659 } 8660 8661 ASC_STATS_ADD(scp->device->host, xfer_elem, use_sg); 8662 } 8663 8664 ASC_STATS(scp->device->host, xfer_cnt); 8665 8666 ASC_DBG_PRT_ADV_SCSI_REQ_Q(2, scsiqp); 8667 ASC_DBG_PRT_CDB(1, scp->cmnd, scp->cmd_len); 8668 8669 *adv_scsiqpp = scsiqp; 8670 8671 return ASC_NOERROR; 8672} 8673 8674static int AscSgListToQueue(int sg_list) 8675{ 8676 int n_sg_list_qs; 8677 8678 n_sg_list_qs = ((sg_list - 1) / ASC_SG_LIST_PER_Q); 8679 if (((sg_list - 1) % ASC_SG_LIST_PER_Q) != 0) 8680 n_sg_list_qs++; 8681 return n_sg_list_qs + 1; 8682} 8683 8684static uint 8685AscGetNumOfFreeQueue(ASC_DVC_VAR *asc_dvc, uchar target_ix, uchar n_qs) 8686{ 8687 uint cur_used_qs; 8688 uint cur_free_qs; 8689 ASC_SCSI_BIT_ID_TYPE target_id; 8690 uchar tid_no; 8691 8692 target_id = ASC_TIX_TO_TARGET_ID(target_ix); 8693 tid_no = ASC_TIX_TO_TID(target_ix); 8694 if ((asc_dvc->unit_not_ready & target_id) || 8695 (asc_dvc->queue_full_or_busy & target_id)) { 8696 return 0; 8697 } 8698 if (n_qs == 1) { 8699 cur_used_qs = (uint) asc_dvc->cur_total_qng + 8700 (uint) asc_dvc->last_q_shortage + (uint) ASC_MIN_FREE_Q; 8701 } else { 8702 cur_used_qs = (uint) asc_dvc->cur_total_qng + 8703 (uint) ASC_MIN_FREE_Q; 8704 } 8705 if ((uint) (cur_used_qs + n_qs) <= (uint) asc_dvc->max_total_qng) { 8706 cur_free_qs = (uint) asc_dvc->max_total_qng - cur_used_qs; 8707 if (asc_dvc->cur_dvc_qng[tid_no] >= 8708 asc_dvc->max_dvc_qng[tid_no]) { 8709 return 0; 8710 } 8711 return cur_free_qs; 8712 } 8713 if (n_qs > 1) { 8714 if ((n_qs > asc_dvc->last_q_shortage) 8715 && (n_qs <= (asc_dvc->max_total_qng - ASC_MIN_FREE_Q))) { 8716 asc_dvc->last_q_shortage = n_qs; 8717 } 8718 } 8719 return 0; 8720} 8721 8722static uchar AscAllocFreeQueue(PortAddr iop_base, uchar free_q_head) 8723{ 8724 ushort q_addr; 8725 uchar next_qp; 8726 uchar q_status; 8727 8728 q_addr = ASC_QNO_TO_QADDR(free_q_head); 8729 q_status = (uchar)AscReadLramByte(iop_base, 8730 (ushort)(q_addr + 8731 ASC_SCSIQ_B_STATUS)); 8732 next_qp = AscReadLramByte(iop_base, (ushort)(q_addr + ASC_SCSIQ_B_FWD)); 8733 if (((q_status & QS_READY) == 0) && (next_qp != ASC_QLINK_END)) 8734 return next_qp; 8735 return ASC_QLINK_END; 8736} 8737 8738static uchar 8739AscAllocMultipleFreeQueue(PortAddr iop_base, uchar free_q_head, uchar n_free_q) 8740{ 8741 uchar i; 8742 8743 for (i = 0; i < n_free_q; i++) { 8744 free_q_head = AscAllocFreeQueue(iop_base, free_q_head); 8745 if (free_q_head == ASC_QLINK_END) 8746 break; 8747 } 8748 return free_q_head; 8749} 8750 8751/* 8752 * void 8753 * DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) 8754 * 8755 * Calling/Exit State: 8756 * none 8757 * 8758 * Description: 8759 * Output an ASC_SCSI_Q structure to the chip 8760 */ 8761static void 8762DvcPutScsiQ(PortAddr iop_base, ushort s_addr, uchar *outbuf, int words) 8763{ 8764 int i; 8765 8766 ASC_DBG_PRT_HEX(2, "DvcPutScsiQ", outbuf, 2 * words); 8767 AscSetChipLramAddr(iop_base, s_addr); 8768 for (i = 0; i < 2 * words; i += 2) { 8769 if (i == 4 || i == 20) { 8770 continue; 8771 } 8772 outpw(iop_base + IOP_RAM_DATA, 8773 ((ushort)outbuf[i + 1] << 8) | outbuf[i]); 8774 } 8775} 8776 8777static int AscPutReadyQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no) 8778{ 8779 ushort q_addr; 8780 uchar tid_no; 8781 uchar sdtr_data; 8782 uchar syn_period_ix; 8783 uchar syn_offset; 8784 PortAddr iop_base; 8785 8786 iop_base = asc_dvc->iop_base; 8787 if (((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) && 8788 ((asc_dvc->sdtr_done & scsiq->q1.target_id) == 0)) { 8789 tid_no = ASC_TIX_TO_TID(scsiq->q2.target_ix); 8790 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); 8791 syn_period_ix = 8792 (sdtr_data >> 4) & (asc_dvc->max_sdtr_index - 1); 8793 syn_offset = sdtr_data & ASC_SYN_MAX_OFFSET; 8794 AscMsgOutSDTR(asc_dvc, 8795 asc_dvc->sdtr_period_tbl[syn_period_ix], 8796 syn_offset); 8797 scsiq->q1.cntl |= QC_MSG_OUT; 8798 } 8799 q_addr = ASC_QNO_TO_QADDR(q_no); 8800 if ((scsiq->q1.target_id & asc_dvc->use_tagged_qng) == 0) { 8801 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG; 8802 } 8803 scsiq->q1.status = QS_FREE; 8804 AscMemWordCopyPtrToLram(iop_base, 8805 q_addr + ASC_SCSIQ_CDB_BEG, 8806 (uchar *)scsiq->cdbptr, scsiq->q2.cdb_len >> 1); 8807 8808 DvcPutScsiQ(iop_base, 8809 q_addr + ASC_SCSIQ_CPY_BEG, 8810 (uchar *)&scsiq->q1.cntl, 8811 ((sizeof(ASC_SCSIQ_1) + sizeof(ASC_SCSIQ_2)) / 2) - 1); 8812 AscWriteLramWord(iop_base, 8813 (ushort)(q_addr + (ushort)ASC_SCSIQ_B_STATUS), 8814 (ushort)(((ushort)scsiq->q1. 8815 q_no << 8) | (ushort)QS_READY)); 8816 return 1; 8817} 8818 8819static int 8820AscPutReadySgListQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar q_no) 8821{ 8822 int sta; 8823 int i; 8824 ASC_SG_HEAD *sg_head; 8825 ASC_SG_LIST_Q scsi_sg_q; 8826 ASC_DCNT saved_data_addr; 8827 ASC_DCNT saved_data_cnt; 8828 PortAddr iop_base; 8829 ushort sg_list_dwords; 8830 ushort sg_index; 8831 ushort sg_entry_cnt; 8832 ushort q_addr; 8833 uchar next_qp; 8834 8835 iop_base = asc_dvc->iop_base; 8836 sg_head = scsiq->sg_head; 8837 saved_data_addr = scsiq->q1.data_addr; 8838 saved_data_cnt = scsiq->q1.data_cnt; 8839 scsiq->q1.data_addr = (ASC_PADDR) sg_head->sg_list[0].addr; 8840 scsiq->q1.data_cnt = (ASC_DCNT) sg_head->sg_list[0].bytes; 8841#if CC_VERY_LONG_SG_LIST 8842 /* 8843 * If sg_head->entry_cnt is greater than ASC_MAX_SG_LIST 8844 * then not all SG elements will fit in the allocated queues. 8845 * The rest of the SG elements will be copied when the RISC 8846 * completes the SG elements that fit and halts. 8847 */ 8848 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) { 8849 /* 8850 * Set sg_entry_cnt to be the number of SG elements that 8851 * will fit in the allocated SG queues. It is minus 1, because 8852 * the first SG element is handled above. ASC_MAX_SG_LIST is 8853 * already inflated by 1 to account for this. For example it 8854 * may be 50 which is 1 + 7 queues * 7 SG elements. 8855 */ 8856 sg_entry_cnt = ASC_MAX_SG_LIST - 1; 8857 8858 /* 8859 * Keep track of remaining number of SG elements that will 8860 * need to be handled from a_isr.c. 8861 */ 8862 scsiq->remain_sg_entry_cnt = 8863 sg_head->entry_cnt - ASC_MAX_SG_LIST; 8864 } else { 8865#endif /* CC_VERY_LONG_SG_LIST */ 8866 /* 8867 * Set sg_entry_cnt to be the number of SG elements that 8868 * will fit in the allocated SG queues. It is minus 1, because 8869 * the first SG element is handled above. 8870 */ 8871 sg_entry_cnt = sg_head->entry_cnt - 1; 8872#if CC_VERY_LONG_SG_LIST 8873 } 8874#endif /* CC_VERY_LONG_SG_LIST */ 8875 if (sg_entry_cnt != 0) { 8876 scsiq->q1.cntl |= QC_SG_HEAD; 8877 q_addr = ASC_QNO_TO_QADDR(q_no); 8878 sg_index = 1; 8879 scsiq->q1.sg_queue_cnt = sg_head->queue_cnt; 8880 scsi_sg_q.sg_head_qp = q_no; 8881 scsi_sg_q.cntl = QCSG_SG_XFER_LIST; 8882 for (i = 0; i < sg_head->queue_cnt; i++) { 8883 scsi_sg_q.seq_no = i + 1; 8884 if (sg_entry_cnt > ASC_SG_LIST_PER_Q) { 8885 sg_list_dwords = (uchar)(ASC_SG_LIST_PER_Q * 2); 8886 sg_entry_cnt -= ASC_SG_LIST_PER_Q; 8887 if (i == 0) { 8888 scsi_sg_q.sg_list_cnt = 8889 ASC_SG_LIST_PER_Q; 8890 scsi_sg_q.sg_cur_list_cnt = 8891 ASC_SG_LIST_PER_Q; 8892 } else { 8893 scsi_sg_q.sg_list_cnt = 8894 ASC_SG_LIST_PER_Q - 1; 8895 scsi_sg_q.sg_cur_list_cnt = 8896 ASC_SG_LIST_PER_Q - 1; 8897 } 8898 } else { 8899#if CC_VERY_LONG_SG_LIST 8900 /* 8901 * This is the last SG queue in the list of 8902 * allocated SG queues. If there are more 8903 * SG elements than will fit in the allocated 8904 * queues, then set the QCSG_SG_XFER_MORE flag. 8905 */ 8906 if (sg_head->entry_cnt > ASC_MAX_SG_LIST) { 8907 scsi_sg_q.cntl |= QCSG_SG_XFER_MORE; 8908 } else { 8909#endif /* CC_VERY_LONG_SG_LIST */ 8910 scsi_sg_q.cntl |= QCSG_SG_XFER_END; 8911#if CC_VERY_LONG_SG_LIST 8912 } 8913#endif /* CC_VERY_LONG_SG_LIST */ 8914 sg_list_dwords = sg_entry_cnt << 1; 8915 if (i == 0) { 8916 scsi_sg_q.sg_list_cnt = sg_entry_cnt; 8917 scsi_sg_q.sg_cur_list_cnt = 8918 sg_entry_cnt; 8919 } else { 8920 scsi_sg_q.sg_list_cnt = 8921 sg_entry_cnt - 1; 8922 scsi_sg_q.sg_cur_list_cnt = 8923 sg_entry_cnt - 1; 8924 } 8925 sg_entry_cnt = 0; 8926 } 8927 next_qp = AscReadLramByte(iop_base, 8928 (ushort)(q_addr + 8929 ASC_SCSIQ_B_FWD)); 8930 scsi_sg_q.q_no = next_qp; 8931 q_addr = ASC_QNO_TO_QADDR(next_qp); 8932 AscMemWordCopyPtrToLram(iop_base, 8933 q_addr + ASC_SCSIQ_SGHD_CPY_BEG, 8934 (uchar *)&scsi_sg_q, 8935 sizeof(ASC_SG_LIST_Q) >> 1); 8936 AscMemDWordCopyPtrToLram(iop_base, 8937 q_addr + ASC_SGQ_LIST_BEG, 8938 (uchar *)&sg_head-> 8939 sg_list[sg_index], 8940 sg_list_dwords); 8941 sg_index += ASC_SG_LIST_PER_Q; 8942 scsiq->next_sg_index = sg_index; 8943 } 8944 } else { 8945 scsiq->q1.cntl &= ~QC_SG_HEAD; 8946 } 8947 sta = AscPutReadyQueue(asc_dvc, scsiq, q_no); 8948 scsiq->q1.data_addr = saved_data_addr; 8949 scsiq->q1.data_cnt = saved_data_cnt; 8950 return (sta); 8951} 8952 8953static int 8954AscSendScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq, uchar n_q_required) 8955{ 8956 PortAddr iop_base; 8957 uchar free_q_head; 8958 uchar next_qp; 8959 uchar tid_no; 8960 uchar target_ix; 8961 int sta; 8962 8963 iop_base = asc_dvc->iop_base; 8964 target_ix = scsiq->q2.target_ix; 8965 tid_no = ASC_TIX_TO_TID(target_ix); 8966 sta = 0; 8967 free_q_head = (uchar)AscGetVarFreeQHead(iop_base); 8968 if (n_q_required > 1) { 8969 next_qp = AscAllocMultipleFreeQueue(iop_base, free_q_head, 8970 (uchar)n_q_required); 8971 if (next_qp != ASC_QLINK_END) { 8972 asc_dvc->last_q_shortage = 0; 8973 scsiq->sg_head->queue_cnt = n_q_required - 1; 8974 scsiq->q1.q_no = free_q_head; 8975 sta = AscPutReadySgListQueue(asc_dvc, scsiq, 8976 free_q_head); 8977 } 8978 } else if (n_q_required == 1) { 8979 next_qp = AscAllocFreeQueue(iop_base, free_q_head); 8980 if (next_qp != ASC_QLINK_END) { 8981 scsiq->q1.q_no = free_q_head; 8982 sta = AscPutReadyQueue(asc_dvc, scsiq, free_q_head); 8983 } 8984 } 8985 if (sta == 1) { 8986 AscPutVarFreeQHead(iop_base, next_qp); 8987 asc_dvc->cur_total_qng += n_q_required; 8988 asc_dvc->cur_dvc_qng[tid_no]++; 8989 } 8990 return sta; 8991} 8992 8993#define ASC_SYN_OFFSET_ONE_DISABLE_LIST 16 8994static uchar _syn_offset_one_disable_cmd[ASC_SYN_OFFSET_ONE_DISABLE_LIST] = { 8995 INQUIRY, 8996 REQUEST_SENSE, 8997 READ_CAPACITY, 8998 READ_TOC, 8999 MODE_SELECT, 9000 MODE_SENSE, 9001 MODE_SELECT_10, 9002 MODE_SENSE_10, 9003 0xFF, 9004 0xFF, 9005 0xFF, 9006 0xFF, 9007 0xFF, 9008 0xFF, 9009 0xFF, 9010 0xFF 9011}; 9012 9013static int AscExeScsiQueue(ASC_DVC_VAR *asc_dvc, ASC_SCSI_Q *scsiq) 9014{ 9015 PortAddr iop_base; 9016 int sta; 9017 int n_q_required; 9018 int disable_syn_offset_one_fix; 9019 int i; 9020 ASC_PADDR addr; 9021 ushort sg_entry_cnt = 0; 9022 ushort sg_entry_cnt_minus_one = 0; 9023 uchar target_ix; 9024 uchar tid_no; 9025 uchar sdtr_data; 9026 uchar extra_bytes; 9027 uchar scsi_cmd; 9028 uchar disable_cmd; 9029 ASC_SG_HEAD *sg_head; 9030 ASC_DCNT data_cnt; 9031 9032 iop_base = asc_dvc->iop_base; 9033 sg_head = scsiq->sg_head; 9034 if (asc_dvc->err_code != 0) 9035 return (ERR); 9036 scsiq->q1.q_no = 0; 9037 if ((scsiq->q2.tag_code & ASC_TAG_FLAG_EXTRA_BYTES) == 0) { 9038 scsiq->q1.extra_bytes = 0; 9039 } 9040 sta = 0; 9041 target_ix = scsiq->q2.target_ix; 9042 tid_no = ASC_TIX_TO_TID(target_ix); 9043 n_q_required = 1; 9044 if (scsiq->cdbptr[0] == REQUEST_SENSE) { 9045 if ((asc_dvc->init_sdtr & scsiq->q1.target_id) != 0) { 9046 asc_dvc->sdtr_done &= ~scsiq->q1.target_id; 9047 sdtr_data = AscGetMCodeInitSDTRAtID(iop_base, tid_no); 9048 AscMsgOutSDTR(asc_dvc, 9049 asc_dvc-> 9050 sdtr_period_tbl[(sdtr_data >> 4) & 9051 (uchar)(asc_dvc-> 9052 max_sdtr_index - 9053 1)], 9054 (uchar)(sdtr_data & (uchar) 9055 ASC_SYN_MAX_OFFSET)); 9056 scsiq->q1.cntl |= (QC_MSG_OUT | QC_URGENT); 9057 } 9058 } 9059 if (asc_dvc->in_critical_cnt != 0) { 9060 AscSetLibErrorCode(asc_dvc, ASCQ_ERR_CRITICAL_RE_ENTRY); 9061 return (ERR); 9062 } 9063 asc_dvc->in_critical_cnt++; 9064 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { 9065 if ((sg_entry_cnt = sg_head->entry_cnt) == 0) { 9066 asc_dvc->in_critical_cnt--; 9067 return (ERR); 9068 } 9069#if !CC_VERY_LONG_SG_LIST 9070 if (sg_entry_cnt > ASC_MAX_SG_LIST) { 9071 asc_dvc->in_critical_cnt--; 9072 return (ERR); 9073 } 9074#endif /* !CC_VERY_LONG_SG_LIST */ 9075 if (sg_entry_cnt == 1) { 9076 scsiq->q1.data_addr = 9077 (ADV_PADDR)sg_head->sg_list[0].addr; 9078 scsiq->q1.data_cnt = 9079 (ADV_DCNT)sg_head->sg_list[0].bytes; 9080 scsiq->q1.cntl &= ~(QC_SG_HEAD | QC_SG_SWAP_QUEUE); 9081 } 9082 sg_entry_cnt_minus_one = sg_entry_cnt - 1; 9083 } 9084 scsi_cmd = scsiq->cdbptr[0]; 9085 disable_syn_offset_one_fix = FALSE; 9086 if ((asc_dvc->pci_fix_asyn_xfer & scsiq->q1.target_id) && 9087 !(asc_dvc->pci_fix_asyn_xfer_always & scsiq->q1.target_id)) { 9088 if (scsiq->q1.cntl & QC_SG_HEAD) { 9089 data_cnt = 0; 9090 for (i = 0; i < sg_entry_cnt; i++) { 9091 data_cnt += 9092 (ADV_DCNT)le32_to_cpu(sg_head->sg_list[i]. 9093 bytes); 9094 } 9095 } else { 9096 data_cnt = le32_to_cpu(scsiq->q1.data_cnt); 9097 } 9098 if (data_cnt != 0UL) { 9099 if (data_cnt < 512UL) { 9100 disable_syn_offset_one_fix = TRUE; 9101 } else { 9102 for (i = 0; i < ASC_SYN_OFFSET_ONE_DISABLE_LIST; 9103 i++) { 9104 disable_cmd = 9105 _syn_offset_one_disable_cmd[i]; 9106 if (disable_cmd == 0xFF) { 9107 break; 9108 } 9109 if (scsi_cmd == disable_cmd) { 9110 disable_syn_offset_one_fix = 9111 TRUE; 9112 break; 9113 } 9114 } 9115 } 9116 } 9117 } 9118 if (disable_syn_offset_one_fix) { 9119 scsiq->q2.tag_code &= ~MSG_SIMPLE_TAG; 9120 scsiq->q2.tag_code |= (ASC_TAG_FLAG_DISABLE_ASYN_USE_SYN_FIX | 9121 ASC_TAG_FLAG_DISABLE_DISCONNECT); 9122 } else { 9123 scsiq->q2.tag_code &= 0x27; 9124 } 9125 if ((scsiq->q1.cntl & QC_SG_HEAD) != 0) { 9126 if (asc_dvc->bug_fix_cntl) { 9127 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 9128 if ((scsi_cmd == READ_6) || 9129 (scsi_cmd == READ_10)) { 9130 addr = 9131 (ADV_PADDR)le32_to_cpu(sg_head-> 9132 sg_list 9133 [sg_entry_cnt_minus_one]. 9134 addr) + 9135 (ADV_DCNT)le32_to_cpu(sg_head-> 9136 sg_list 9137 [sg_entry_cnt_minus_one]. 9138 bytes); 9139 extra_bytes = 9140 (uchar)((ushort)addr & 0x0003); 9141 if ((extra_bytes != 0) 9142 && 9143 ((scsiq->q2. 9144 tag_code & 9145 ASC_TAG_FLAG_EXTRA_BYTES) 9146 == 0)) { 9147 scsiq->q2.tag_code |= 9148 ASC_TAG_FLAG_EXTRA_BYTES; 9149 scsiq->q1.extra_bytes = 9150 extra_bytes; 9151 data_cnt = 9152 le32_to_cpu(sg_head-> 9153 sg_list 9154 [sg_entry_cnt_minus_one]. 9155 bytes); 9156 data_cnt -= 9157 (ASC_DCNT) extra_bytes; 9158 sg_head-> 9159 sg_list 9160 [sg_entry_cnt_minus_one]. 9161 bytes = 9162 cpu_to_le32(data_cnt); 9163 } 9164 } 9165 } 9166 } 9167 sg_head->entry_to_copy = sg_head->entry_cnt; 9168#if CC_VERY_LONG_SG_LIST 9169 /* 9170 * Set the sg_entry_cnt to the maximum possible. The rest of 9171 * the SG elements will be copied when the RISC completes the 9172 * SG elements that fit and halts. 9173 */ 9174 if (sg_entry_cnt > ASC_MAX_SG_LIST) { 9175 sg_entry_cnt = ASC_MAX_SG_LIST; 9176 } 9177#endif /* CC_VERY_LONG_SG_LIST */ 9178 n_q_required = AscSgListToQueue(sg_entry_cnt); 9179 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, n_q_required) >= 9180 (uint) n_q_required) 9181 || ((scsiq->q1.cntl & QC_URGENT) != 0)) { 9182 if ((sta = 9183 AscSendScsiQueue(asc_dvc, scsiq, 9184 n_q_required)) == 1) { 9185 asc_dvc->in_critical_cnt--; 9186 return (sta); 9187 } 9188 } 9189 } else { 9190 if (asc_dvc->bug_fix_cntl) { 9191 if (asc_dvc->bug_fix_cntl & ASC_BUG_FIX_IF_NOT_DWB) { 9192 if ((scsi_cmd == READ_6) || 9193 (scsi_cmd == READ_10)) { 9194 addr = 9195 le32_to_cpu(scsiq->q1.data_addr) + 9196 le32_to_cpu(scsiq->q1.data_cnt); 9197 extra_bytes = 9198 (uchar)((ushort)addr & 0x0003); 9199 if ((extra_bytes != 0) 9200 && 9201 ((scsiq->q2. 9202 tag_code & 9203 ASC_TAG_FLAG_EXTRA_BYTES) 9204 == 0)) { 9205 data_cnt = 9206 le32_to_cpu(scsiq->q1. 9207 data_cnt); 9208 if (((ushort)data_cnt & 0x01FF) 9209 == 0) { 9210 scsiq->q2.tag_code |= 9211 ASC_TAG_FLAG_EXTRA_BYTES; 9212 data_cnt -= (ASC_DCNT) 9213 extra_bytes; 9214 scsiq->q1.data_cnt = 9215 cpu_to_le32 9216 (data_cnt); 9217 scsiq->q1.extra_bytes = 9218 extra_bytes; 9219 } 9220 } 9221 } 9222 } 9223 } 9224 n_q_required = 1; 9225 if ((AscGetNumOfFreeQueue(asc_dvc, target_ix, 1) >= 1) || 9226 ((scsiq->q1.cntl & QC_URGENT) != 0)) { 9227 if ((sta = AscSendScsiQueue(asc_dvc, scsiq, 9228 n_q_required)) == 1) { 9229 asc_dvc->in_critical_cnt--; 9230 return (sta); 9231 } 9232 } 9233 } 9234 asc_dvc->in_critical_cnt--; 9235 return (sta); 9236} 9237 9238/* 9239 * AdvExeScsiQueue() - Send a request to the RISC microcode program. 9240 * 9241 * Allocate a carrier structure, point the carrier to the ADV_SCSI_REQ_Q, 9242 * add the carrier to the ICQ (Initiator Command Queue), and tickle the 9243 * RISC to notify it a new command is ready to be executed. 9244 * 9245 * If 'done_status' is not set to QD_DO_RETRY, then 'error_retry' will be 9246 * set to SCSI_MAX_RETRY. 9247 * 9248 * Multi-byte fields in the ASC_SCSI_REQ_Q that are used by the microcode 9249 * for DMA addresses or math operations are byte swapped to little-endian 9250 * order. 9251 * 9252 * Return: 9253 * ADV_SUCCESS(1) - The request was successfully queued. 9254 * ADV_BUSY(0) - Resource unavailable; Retry again after pending 9255 * request completes. 9256 * ADV_ERROR(-1) - Invalid ADV_SCSI_REQ_Q request structure 9257 * host IC error. 9258 */ 9259static int AdvExeScsiQueue(ADV_DVC_VAR *asc_dvc, ADV_SCSI_REQ_Q *scsiq) 9260{ 9261 AdvPortAddr iop_base; 9262 ADV_PADDR req_paddr; 9263 ADV_CARR_T *new_carrp; 9264 9265 /* 9266 * The ADV_SCSI_REQ_Q 'target_id' field should never exceed ADV_MAX_TID. 9267 */ 9268 if (scsiq->target_id > ADV_MAX_TID) { 9269 scsiq->host_status = QHSTA_M_INVALID_DEVICE; 9270 scsiq->done_status = QD_WITH_ERROR; 9271 return ADV_ERROR; 9272 } 9273 9274 iop_base = asc_dvc->iop_base; 9275 9276 /* 9277 * Allocate a carrier ensuring at least one carrier always 9278 * remains on the freelist and initialize fields. 9279 */ 9280 if ((new_carrp = asc_dvc->carr_freelist) == NULL) { 9281 return ADV_BUSY; 9282 } 9283 asc_dvc->carr_freelist = (ADV_CARR_T *) 9284 ADV_U32_TO_VADDR(le32_to_cpu(new_carrp->next_vpa)); 9285 asc_dvc->carr_pending_cnt++; 9286 9287 /* 9288 * Set the carrier to be a stopper by setting 'next_vpa' 9289 * to the stopper value. The current stopper will be changed 9290 * below to point to the new stopper. 9291 */ 9292 new_carrp->next_vpa = cpu_to_le32(ASC_CQ_STOPPER); 9293 9294 /* 9295 * Clear the ADV_SCSI_REQ_Q done flag. 9296 */ 9297 scsiq->a_flag &= ~ADV_SCSIQ_DONE; 9298 9299 req_paddr = virt_to_bus(scsiq); 9300 BUG_ON(req_paddr & 31); 9301 /* Wait for assertion before making little-endian */ 9302 req_paddr = cpu_to_le32(req_paddr); 9303 9304 /* Save virtual and physical address of ADV_SCSI_REQ_Q and carrier. */ 9305 scsiq->scsiq_ptr = cpu_to_le32(ADV_VADDR_TO_U32(scsiq)); 9306 scsiq->scsiq_rptr = req_paddr; 9307 9308 scsiq->carr_va = cpu_to_le32(ADV_VADDR_TO_U32(asc_dvc->icq_sp)); 9309 /* 9310 * Every ADV_CARR_T.carr_pa is byte swapped to little-endian 9311 * order during initialization. 9312 */ 9313 scsiq->carr_pa = asc_dvc->icq_sp->carr_pa; 9314 9315 /* 9316 * Use the current stopper to send the ADV_SCSI_REQ_Q command to 9317 * the microcode. The newly allocated stopper will become the new 9318 * stopper. 9319 */ 9320 asc_dvc->icq_sp->areq_vpa = req_paddr; 9321 9322 /* 9323 * Set the 'next_vpa' pointer for the old stopper to be the 9324 * physical address of the new stopper. The RISC can only 9325 * follow physical addresses. 9326 */ 9327 asc_dvc->icq_sp->next_vpa = new_carrp->carr_pa; 9328 9329 /* 9330 * Set the host adapter stopper pointer to point to the new carrier. 9331 */ 9332 asc_dvc->icq_sp = new_carrp; 9333 9334 if (asc_dvc->chip_type == ADV_CHIP_ASC3550 || 9335 asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 9336 /* 9337 * Tickle the RISC to tell it to read its Command Queue Head pointer. 9338 */ 9339 AdvWriteByteRegister(iop_base, IOPB_TICKLE, ADV_TICKLE_A); 9340 if (asc_dvc->chip_type == ADV_CHIP_ASC3550) { 9341 /* 9342 * Clear the tickle value. In the ASC-3550 the RISC flag 9343 * command 'clr_tickle_a' does not work unless the host 9344 * value is cleared. 9345 */ 9346 AdvWriteByteRegister(iop_base, IOPB_TICKLE, 9347 ADV_TICKLE_NOP); 9348 } 9349 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 9350 /* 9351 * Notify the RISC a carrier is ready by writing the physical 9352 * address of the new carrier stopper to the COMMA register. 9353 */ 9354 AdvWriteDWordRegister(iop_base, IOPDW_COMMA, 9355 le32_to_cpu(new_carrp->carr_pa)); 9356 } 9357 9358 return ADV_SUCCESS; 9359} 9360 9361/* 9362 * Execute a single 'Scsi_Cmnd'. 9363 */ 9364static int asc_execute_scsi_cmnd(struct scsi_cmnd *scp) 9365{ 9366 int ret, err_code; 9367 struct asc_board *boardp = shost_priv(scp->device->host); 9368 9369 ASC_DBG(1, "scp 0x%p\n", scp); 9370 9371 if (ASC_NARROW_BOARD(boardp)) { 9372 ASC_DVC_VAR *asc_dvc = &boardp->dvc_var.asc_dvc_var; 9373 struct asc_scsi_q asc_scsi_q; 9374 9375 /* asc_build_req() can not return ASC_BUSY. */ 9376 ret = asc_build_req(boardp, scp, &asc_scsi_q); 9377 if (ret == ASC_ERROR) { 9378 ASC_STATS(scp->device->host, build_error); 9379 return ASC_ERROR; 9380 } 9381 9382 ret = AscExeScsiQueue(asc_dvc, &asc_scsi_q); 9383 kfree(asc_scsi_q.sg_head); 9384 err_code = asc_dvc->err_code; 9385 } else { 9386 ADV_DVC_VAR *adv_dvc = &boardp->dvc_var.adv_dvc_var; 9387 ADV_SCSI_REQ_Q *adv_scsiqp; 9388 9389 switch (adv_build_req(boardp, scp, &adv_scsiqp)) { 9390 case ASC_NOERROR: 9391 ASC_DBG(3, "adv_build_req ASC_NOERROR\n"); 9392 break; 9393 case ASC_BUSY: 9394 ASC_DBG(1, "adv_build_req ASC_BUSY\n"); 9395 /* 9396 * The asc_stats fields 'adv_build_noreq' and 9397 * 'adv_build_nosg' count wide board busy conditions. 9398 * They are updated in adv_build_req and 9399 * adv_get_sglist, respectively. 9400 */ 9401 return ASC_BUSY; 9402 case ASC_ERROR: 9403 default: 9404 ASC_DBG(1, "adv_build_req ASC_ERROR\n"); 9405 ASC_STATS(scp->device->host, build_error); 9406 return ASC_ERROR; 9407 } 9408 9409 ret = AdvExeScsiQueue(adv_dvc, adv_scsiqp); 9410 err_code = adv_dvc->err_code; 9411 } 9412 9413 switch (ret) { 9414 case ASC_NOERROR: 9415 ASC_STATS(scp->device->host, exe_noerror); 9416 /* 9417 * Increment monotonically increasing per device 9418 * successful request counter. Wrapping doesn't matter. 9419 */ 9420 boardp->reqcnt[scp->device->id]++; 9421 ASC_DBG(1, "ExeScsiQueue() ASC_NOERROR\n"); 9422 break; 9423 case ASC_BUSY: 9424 ASC_STATS(scp->device->host, exe_busy); 9425 break; 9426 case ASC_ERROR: 9427 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() ASC_ERROR, " 9428 "err_code 0x%x\n", err_code); 9429 ASC_STATS(scp->device->host, exe_error); 9430 scp->result = HOST_BYTE(DID_ERROR); 9431 break; 9432 default: 9433 scmd_printk(KERN_ERR, scp, "ExeScsiQueue() unknown, " 9434 "err_code 0x%x\n", err_code); 9435 ASC_STATS(scp->device->host, exe_unknown); 9436 scp->result = HOST_BYTE(DID_ERROR); 9437 break; 9438 } 9439 9440 ASC_DBG(1, "end\n"); 9441 return ret; 9442} 9443 9444/* 9445 * advansys_queuecommand() - interrupt-driven I/O entrypoint. 9446 * 9447 * This function always returns 0. Command return status is saved 9448 * in the 'scp' result field. 9449 */ 9450static int 9451advansys_queuecommand(struct scsi_cmnd *scp, void (*done)(struct scsi_cmnd *)) 9452{ 9453 struct Scsi_Host *shost = scp->device->host; 9454 int asc_res, result = 0; 9455 9456 ASC_STATS(shost, queuecommand); 9457 scp->scsi_done = done; 9458 9459 asc_res = asc_execute_scsi_cmnd(scp); 9460 9461 switch (asc_res) { 9462 case ASC_NOERROR: 9463 break; 9464 case ASC_BUSY: 9465 result = SCSI_MLQUEUE_HOST_BUSY; 9466 break; 9467 case ASC_ERROR: 9468 default: 9469 asc_scsi_done(scp); 9470 break; 9471 } 9472 9473 return result; 9474} 9475 9476static ushort __devinit AscGetEisaChipCfg(PortAddr iop_base) 9477{ 9478 PortAddr eisa_cfg_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) | 9479 (PortAddr) (ASC_EISA_CFG_IOP_MASK); 9480 return inpw(eisa_cfg_iop); 9481} 9482 9483/* 9484 * Return the BIOS address of the adapter at the specified 9485 * I/O port and with the specified bus type. 9486 */ 9487static unsigned short __devinit 9488AscGetChipBiosAddress(PortAddr iop_base, unsigned short bus_type) 9489{ 9490 unsigned short cfg_lsw; 9491 unsigned short bios_addr; 9492 9493 /* 9494 * The PCI BIOS is re-located by the motherboard BIOS. Because 9495 * of this the driver can not determine where a PCI BIOS is 9496 * loaded and executes. 9497 */ 9498 if (bus_type & ASC_IS_PCI) 9499 return 0; 9500 9501 if ((bus_type & ASC_IS_EISA) != 0) { 9502 cfg_lsw = AscGetEisaChipCfg(iop_base); 9503 cfg_lsw &= 0x000F; 9504 bios_addr = ASC_BIOS_MIN_ADDR + cfg_lsw * ASC_BIOS_BANK_SIZE; 9505 return bios_addr; 9506 } 9507 9508 cfg_lsw = AscGetChipCfgLsw(iop_base); 9509 9510 /* 9511 * ISA PnP uses the top bit as the 32K BIOS flag 9512 */ 9513 if (bus_type == ASC_IS_ISAPNP) 9514 cfg_lsw &= 0x7FFF; 9515 bios_addr = ASC_BIOS_MIN_ADDR + (cfg_lsw >> 12) * ASC_BIOS_BANK_SIZE; 9516 return bios_addr; 9517} 9518 9519static uchar __devinit AscSetChipScsiID(PortAddr iop_base, uchar new_host_id) 9520{ 9521 ushort cfg_lsw; 9522 9523 if (AscGetChipScsiID(iop_base) == new_host_id) { 9524 return (new_host_id); 9525 } 9526 cfg_lsw = AscGetChipCfgLsw(iop_base); 9527 cfg_lsw &= 0xF8FF; 9528 cfg_lsw |= (ushort)((new_host_id & ASC_MAX_TID) << 8); 9529 AscSetChipCfgLsw(iop_base, cfg_lsw); 9530 return (AscGetChipScsiID(iop_base)); 9531} 9532 9533static unsigned char __devinit AscGetChipScsiCtrl(PortAddr iop_base) 9534{ 9535 unsigned char sc; 9536 9537 AscSetBank(iop_base, 1); 9538 sc = inp(iop_base + IOP_REG_SC); 9539 AscSetBank(iop_base, 0); 9540 return sc; 9541} 9542 9543static unsigned char __devinit 9544AscGetChipVersion(PortAddr iop_base, unsigned short bus_type) 9545{ 9546 if (bus_type & ASC_IS_EISA) { 9547 PortAddr eisa_iop; 9548 unsigned char revision; 9549 eisa_iop = (PortAddr) ASC_GET_EISA_SLOT(iop_base) | 9550 (PortAddr) ASC_EISA_REV_IOP_MASK; 9551 revision = inp(eisa_iop); 9552 return ASC_CHIP_MIN_VER_EISA - 1 + revision; 9553 } 9554 return AscGetChipVerNo(iop_base); 9555} 9556 9557#ifdef CONFIG_ISA 9558static void __devinit AscEnableIsaDma(uchar dma_channel) 9559{ 9560 if (dma_channel < 4) { 9561 outp(0x000B, (ushort)(0xC0 | dma_channel)); 9562 outp(0x000A, dma_channel); 9563 } else if (dma_channel < 8) { 9564 outp(0x00D6, (ushort)(0xC0 | (dma_channel - 4))); 9565 outp(0x00D4, (ushort)(dma_channel - 4)); 9566 } 9567} 9568#endif /* CONFIG_ISA */ 9569 9570static int AscStopQueueExe(PortAddr iop_base) 9571{ 9572 int count = 0; 9573 9574 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) == 0) { 9575 AscWriteLramByte(iop_base, ASCV_STOP_CODE_B, 9576 ASC_STOP_REQ_RISC_STOP); 9577 do { 9578 if (AscReadLramByte(iop_base, ASCV_STOP_CODE_B) & 9579 ASC_STOP_ACK_RISC_STOP) { 9580 return (1); 9581 } 9582 mdelay(100); 9583 } while (count++ < 20); 9584 } 9585 return (0); 9586} 9587 9588static ASC_DCNT __devinit AscGetMaxDmaCount(ushort bus_type) 9589{ 9590 if (bus_type & ASC_IS_ISA) 9591 return ASC_MAX_ISA_DMA_COUNT; 9592 else if (bus_type & (ASC_IS_EISA | ASC_IS_VL)) 9593 return ASC_MAX_VL_DMA_COUNT; 9594 return ASC_MAX_PCI_DMA_COUNT; 9595} 9596 9597#ifdef CONFIG_ISA 9598static ushort __devinit AscGetIsaDmaChannel(PortAddr iop_base) 9599{ 9600 ushort channel; 9601 9602 channel = AscGetChipCfgLsw(iop_base) & 0x0003; 9603 if (channel == 0x03) 9604 return (0); 9605 else if (channel == 0x00) 9606 return (7); 9607 return (channel + 4); 9608} 9609 9610static ushort __devinit AscSetIsaDmaChannel(PortAddr iop_base, ushort dma_channel) 9611{ 9612 ushort cfg_lsw; 9613 uchar value; 9614 9615 if ((dma_channel >= 5) && (dma_channel <= 7)) { 9616 if (dma_channel == 7) 9617 value = 0x00; 9618 else 9619 value = dma_channel - 4; 9620 cfg_lsw = AscGetChipCfgLsw(iop_base) & 0xFFFC; 9621 cfg_lsw |= value; 9622 AscSetChipCfgLsw(iop_base, cfg_lsw); 9623 return (AscGetIsaDmaChannel(iop_base)); 9624 } 9625 return 0; 9626} 9627 9628static uchar __devinit AscGetIsaDmaSpeed(PortAddr iop_base) 9629{ 9630 uchar speed_value; 9631 9632 AscSetBank(iop_base, 1); 9633 speed_value = AscReadChipDmaSpeed(iop_base); 9634 speed_value &= 0x07; 9635 AscSetBank(iop_base, 0); 9636 return speed_value; 9637} 9638 9639static uchar __devinit AscSetIsaDmaSpeed(PortAddr iop_base, uchar speed_value) 9640{ 9641 speed_value &= 0x07; 9642 AscSetBank(iop_base, 1); 9643 AscWriteChipDmaSpeed(iop_base, speed_value); 9644 AscSetBank(iop_base, 0); 9645 return AscGetIsaDmaSpeed(iop_base); 9646} 9647#endif /* CONFIG_ISA */ 9648 9649static ushort __devinit AscInitAscDvcVar(ASC_DVC_VAR *asc_dvc) 9650{ 9651 int i; 9652 PortAddr iop_base; 9653 ushort warn_code; 9654 uchar chip_version; 9655 9656 iop_base = asc_dvc->iop_base; 9657 warn_code = 0; 9658 asc_dvc->err_code = 0; 9659 if ((asc_dvc->bus_type & 9660 (ASC_IS_ISA | ASC_IS_PCI | ASC_IS_EISA | ASC_IS_VL)) == 0) { 9661 asc_dvc->err_code |= ASC_IERR_NO_BUS_TYPE; 9662 } 9663 AscSetChipControl(iop_base, CC_HALT); 9664 AscSetChipStatus(iop_base, 0); 9665 asc_dvc->bug_fix_cntl = 0; 9666 asc_dvc->pci_fix_asyn_xfer = 0; 9667 asc_dvc->pci_fix_asyn_xfer_always = 0; 9668 /* asc_dvc->init_state initialized in AscInitGetConfig(). */ 9669 asc_dvc->sdtr_done = 0; 9670 asc_dvc->cur_total_qng = 0; 9671 asc_dvc->is_in_int = 0; 9672 asc_dvc->in_critical_cnt = 0; 9673 asc_dvc->last_q_shortage = 0; 9674 asc_dvc->use_tagged_qng = 0; 9675 asc_dvc->no_scam = 0; 9676 asc_dvc->unit_not_ready = 0; 9677 asc_dvc->queue_full_or_busy = 0; 9678 asc_dvc->redo_scam = 0; 9679 asc_dvc->res2 = 0; 9680 asc_dvc->min_sdtr_index = 0; 9681 asc_dvc->cfg->can_tagged_qng = 0; 9682 asc_dvc->cfg->cmd_qng_enabled = 0; 9683 asc_dvc->dvc_cntl = ASC_DEF_DVC_CNTL; 9684 asc_dvc->init_sdtr = 0; 9685 asc_dvc->max_total_qng = ASC_DEF_MAX_TOTAL_QNG; 9686 asc_dvc->scsi_reset_wait = 3; 9687 asc_dvc->start_motor = ASC_SCSI_WIDTH_BIT_SET; 9688 asc_dvc->max_dma_count = AscGetMaxDmaCount(asc_dvc->bus_type); 9689 asc_dvc->cfg->sdtr_enable = ASC_SCSI_WIDTH_BIT_SET; 9690 asc_dvc->cfg->disc_enable = ASC_SCSI_WIDTH_BIT_SET; 9691 asc_dvc->cfg->chip_scsi_id = ASC_DEF_CHIP_SCSI_ID; 9692 chip_version = AscGetChipVersion(iop_base, asc_dvc->bus_type); 9693 asc_dvc->cfg->chip_version = chip_version; 9694 asc_dvc->sdtr_period_tbl = asc_syn_xfer_period; 9695 asc_dvc->max_sdtr_index = 7; 9696 if ((asc_dvc->bus_type & ASC_IS_PCI) && 9697 (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3150)) { 9698 asc_dvc->bus_type = ASC_IS_PCI_ULTRA; 9699 asc_dvc->sdtr_period_tbl = asc_syn_ultra_xfer_period; 9700 asc_dvc->max_sdtr_index = 15; 9701 if (chip_version == ASC_CHIP_VER_PCI_ULTRA_3150) { 9702 AscSetExtraControl(iop_base, 9703 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 9704 } else if (chip_version >= ASC_CHIP_VER_PCI_ULTRA_3050) { 9705 AscSetExtraControl(iop_base, 9706 (SEC_ACTIVE_NEGATE | 9707 SEC_ENABLE_FILTER)); 9708 } 9709 } 9710 if (asc_dvc->bus_type == ASC_IS_PCI) { 9711 AscSetExtraControl(iop_base, 9712 (SEC_ACTIVE_NEGATE | SEC_SLEW_RATE)); 9713 } 9714 9715 asc_dvc->cfg->isa_dma_speed = ASC_DEF_ISA_DMA_SPEED; 9716#ifdef CONFIG_ISA 9717 if ((asc_dvc->bus_type & ASC_IS_ISA) != 0) { 9718 if (chip_version >= ASC_CHIP_MIN_VER_ISA_PNP) { 9719 AscSetChipIFC(iop_base, IFC_INIT_DEFAULT); 9720 asc_dvc->bus_type = ASC_IS_ISAPNP; 9721 } 9722 asc_dvc->cfg->isa_dma_channel = 9723 (uchar)AscGetIsaDmaChannel(iop_base); 9724 } 9725#endif /* CONFIG_ISA */ 9726 for (i = 0; i <= ASC_MAX_TID; i++) { 9727 asc_dvc->cur_dvc_qng[i] = 0; 9728 asc_dvc->max_dvc_qng[i] = ASC_MAX_SCSI1_QNG; 9729 asc_dvc->scsiq_busy_head[i] = (ASC_SCSI_Q *)0L; 9730 asc_dvc->scsiq_busy_tail[i] = (ASC_SCSI_Q *)0L; 9731 asc_dvc->cfg->max_tag_qng[i] = ASC_MAX_INRAM_TAG_QNG; 9732 } 9733 return warn_code; 9734} 9735 9736static int __devinit AscWriteEEPCmdReg(PortAddr iop_base, uchar cmd_reg) 9737{ 9738 int retry; 9739 9740 for (retry = 0; retry < ASC_EEP_MAX_RETRY; retry++) { 9741 unsigned char read_back; 9742 AscSetChipEEPCmd(iop_base, cmd_reg); 9743 mdelay(1); 9744 read_back = AscGetChipEEPCmd(iop_base); 9745 if (read_back == cmd_reg) 9746 return 1; 9747 } 9748 return 0; 9749} 9750 9751static void __devinit AscWaitEEPRead(void) 9752{ 9753 mdelay(1); 9754} 9755 9756static ushort __devinit AscReadEEPWord(PortAddr iop_base, uchar addr) 9757{ 9758 ushort read_wval; 9759 uchar cmd_reg; 9760 9761 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE); 9762 AscWaitEEPRead(); 9763 cmd_reg = addr | ASC_EEP_CMD_READ; 9764 AscWriteEEPCmdReg(iop_base, cmd_reg); 9765 AscWaitEEPRead(); 9766 read_wval = AscGetChipEEPData(iop_base); 9767 AscWaitEEPRead(); 9768 return read_wval; 9769} 9770 9771static ushort __devinit 9772AscGetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type) 9773{ 9774 ushort wval; 9775 ushort sum; 9776 ushort *wbuf; 9777 int cfg_beg; 9778 int cfg_end; 9779 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2; 9780 int s_addr; 9781 9782 wbuf = (ushort *)cfg_buf; 9783 sum = 0; 9784 /* Read two config words; Byte-swapping done by AscReadEEPWord(). */ 9785 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 9786 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr); 9787 sum += *wbuf; 9788 } 9789 if (bus_type & ASC_IS_VL) { 9790 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 9791 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 9792 } else { 9793 cfg_beg = ASC_EEP_DVC_CFG_BEG; 9794 cfg_end = ASC_EEP_MAX_DVC_ADDR; 9795 } 9796 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 9797 wval = AscReadEEPWord(iop_base, (uchar)s_addr); 9798 if (s_addr <= uchar_end_in_config) { 9799 /* 9800 * Swap all char fields - must unswap bytes already swapped 9801 * by AscReadEEPWord(). 9802 */ 9803 *wbuf = le16_to_cpu(wval); 9804 } else { 9805 /* Don't swap word field at the end - cntl field. */ 9806 *wbuf = wval; 9807 } 9808 sum += wval; /* Checksum treats all EEPROM data as words. */ 9809 } 9810 /* 9811 * Read the checksum word which will be compared against 'sum' 9812 * by the caller. Word field already swapped. 9813 */ 9814 *wbuf = AscReadEEPWord(iop_base, (uchar)s_addr); 9815 return sum; 9816} 9817 9818static int __devinit AscTestExternalLram(ASC_DVC_VAR *asc_dvc) 9819{ 9820 PortAddr iop_base; 9821 ushort q_addr; 9822 ushort saved_word; 9823 int sta; 9824 9825 iop_base = asc_dvc->iop_base; 9826 sta = 0; 9827 q_addr = ASC_QNO_TO_QADDR(241); 9828 saved_word = AscReadLramWord(iop_base, q_addr); 9829 AscSetChipLramAddr(iop_base, q_addr); 9830 AscSetChipLramData(iop_base, 0x55AA); 9831 mdelay(10); 9832 AscSetChipLramAddr(iop_base, q_addr); 9833 if (AscGetChipLramData(iop_base) == 0x55AA) { 9834 sta = 1; 9835 AscWriteLramWord(iop_base, q_addr, saved_word); 9836 } 9837 return (sta); 9838} 9839 9840static void __devinit AscWaitEEPWrite(void) 9841{ 9842 mdelay(20); 9843} 9844 9845static int __devinit AscWriteEEPDataReg(PortAddr iop_base, ushort data_reg) 9846{ 9847 ushort read_back; 9848 int retry; 9849 9850 retry = 0; 9851 while (TRUE) { 9852 AscSetChipEEPData(iop_base, data_reg); 9853 mdelay(1); 9854 read_back = AscGetChipEEPData(iop_base); 9855 if (read_back == data_reg) { 9856 return (1); 9857 } 9858 if (retry++ > ASC_EEP_MAX_RETRY) { 9859 return (0); 9860 } 9861 } 9862} 9863 9864static ushort __devinit 9865AscWriteEEPWord(PortAddr iop_base, uchar addr, ushort word_val) 9866{ 9867 ushort read_wval; 9868 9869 read_wval = AscReadEEPWord(iop_base, addr); 9870 if (read_wval != word_val) { 9871 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_ABLE); 9872 AscWaitEEPRead(); 9873 AscWriteEEPDataReg(iop_base, word_val); 9874 AscWaitEEPRead(); 9875 AscWriteEEPCmdReg(iop_base, 9876 (uchar)((uchar)ASC_EEP_CMD_WRITE | addr)); 9877 AscWaitEEPWrite(); 9878 AscWriteEEPCmdReg(iop_base, ASC_EEP_CMD_WRITE_DISABLE); 9879 AscWaitEEPRead(); 9880 return (AscReadEEPWord(iop_base, addr)); 9881 } 9882 return (read_wval); 9883} 9884 9885static int __devinit 9886AscSetEEPConfigOnce(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type) 9887{ 9888 int n_error; 9889 ushort *wbuf; 9890 ushort word; 9891 ushort sum; 9892 int s_addr; 9893 int cfg_beg; 9894 int cfg_end; 9895 int uchar_end_in_config = ASC_EEP_MAX_DVC_ADDR - 2; 9896 9897 wbuf = (ushort *)cfg_buf; 9898 n_error = 0; 9899 sum = 0; 9900 /* Write two config words; AscWriteEEPWord() will swap bytes. */ 9901 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 9902 sum += *wbuf; 9903 if (*wbuf != AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) { 9904 n_error++; 9905 } 9906 } 9907 if (bus_type & ASC_IS_VL) { 9908 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 9909 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 9910 } else { 9911 cfg_beg = ASC_EEP_DVC_CFG_BEG; 9912 cfg_end = ASC_EEP_MAX_DVC_ADDR; 9913 } 9914 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 9915 if (s_addr <= uchar_end_in_config) { 9916 /* 9917 * This is a char field. Swap char fields before they are 9918 * swapped again by AscWriteEEPWord(). 9919 */ 9920 word = cpu_to_le16(*wbuf); 9921 if (word != 9922 AscWriteEEPWord(iop_base, (uchar)s_addr, word)) { 9923 n_error++; 9924 } 9925 } else { 9926 /* Don't swap word field at the end - cntl field. */ 9927 if (*wbuf != 9928 AscWriteEEPWord(iop_base, (uchar)s_addr, *wbuf)) { 9929 n_error++; 9930 } 9931 } 9932 sum += *wbuf; /* Checksum calculated from word values. */ 9933 } 9934 /* Write checksum word. It will be swapped by AscWriteEEPWord(). */ 9935 *wbuf = sum; 9936 if (sum != AscWriteEEPWord(iop_base, (uchar)s_addr, sum)) { 9937 n_error++; 9938 } 9939 9940 /* Read EEPROM back again. */ 9941 wbuf = (ushort *)cfg_buf; 9942 /* 9943 * Read two config words; Byte-swapping done by AscReadEEPWord(). 9944 */ 9945 for (s_addr = 0; s_addr < 2; s_addr++, wbuf++) { 9946 if (*wbuf != AscReadEEPWord(iop_base, (uchar)s_addr)) { 9947 n_error++; 9948 } 9949 } 9950 if (bus_type & ASC_IS_VL) { 9951 cfg_beg = ASC_EEP_DVC_CFG_BEG_VL; 9952 cfg_end = ASC_EEP_MAX_DVC_ADDR_VL; 9953 } else { 9954 cfg_beg = ASC_EEP_DVC_CFG_BEG; 9955 cfg_end = ASC_EEP_MAX_DVC_ADDR; 9956 } 9957 for (s_addr = cfg_beg; s_addr <= (cfg_end - 1); s_addr++, wbuf++) { 9958 if (s_addr <= uchar_end_in_config) { 9959 /* 9960 * Swap all char fields. Must unswap bytes already swapped 9961 * by AscReadEEPWord(). 9962 */ 9963 word = 9964 le16_to_cpu(AscReadEEPWord 9965 (iop_base, (uchar)s_addr)); 9966 } else { 9967 /* Don't swap word field at the end - cntl field. */ 9968 word = AscReadEEPWord(iop_base, (uchar)s_addr); 9969 } 9970 if (*wbuf != word) { 9971 n_error++; 9972 } 9973 } 9974 /* Read checksum; Byte swapping not needed. */ 9975 if (AscReadEEPWord(iop_base, (uchar)s_addr) != sum) { 9976 n_error++; 9977 } 9978 return n_error; 9979} 9980 9981static int __devinit 9982AscSetEEPConfig(PortAddr iop_base, ASCEEP_CONFIG *cfg_buf, ushort bus_type) 9983{ 9984 int retry; 9985 int n_error; 9986 9987 retry = 0; 9988 while (TRUE) { 9989 if ((n_error = AscSetEEPConfigOnce(iop_base, cfg_buf, 9990 bus_type)) == 0) { 9991 break; 9992 } 9993 if (++retry > ASC_EEP_MAX_RETRY) { 9994 break; 9995 } 9996 } 9997 return n_error; 9998} 9999 10000static ushort __devinit AscInitFromEEP(ASC_DVC_VAR *asc_dvc) 10001{ 10002 ASCEEP_CONFIG eep_config_buf; 10003 ASCEEP_CONFIG *eep_config; 10004 PortAddr iop_base; 10005 ushort chksum; 10006 ushort warn_code; 10007 ushort cfg_msw, cfg_lsw; 10008 int i; 10009 int write_eep = 0; 10010 10011 iop_base = asc_dvc->iop_base; 10012 warn_code = 0; 10013 AscWriteLramWord(iop_base, ASCV_HALTCODE_W, 0x00FE); 10014 AscStopQueueExe(iop_base); 10015 if ((AscStopChip(iop_base) == FALSE) || 10016 (AscGetChipScsiCtrl(iop_base) != 0)) { 10017 asc_dvc->init_state |= ASC_INIT_RESET_SCSI_DONE; 10018 AscResetChipAndScsiBus(asc_dvc); 10019 mdelay(asc_dvc->scsi_reset_wait * 1000); 10020 } 10021 if (AscIsChipHalted(iop_base) == FALSE) { 10022 asc_dvc->err_code |= ASC_IERR_START_STOP_CHIP; 10023 return (warn_code); 10024 } 10025 AscSetPCAddr(iop_base, ASC_MCODE_START_ADDR); 10026 if (AscGetPCAddr(iop_base) != ASC_MCODE_START_ADDR) { 10027 asc_dvc->err_code |= ASC_IERR_SET_PC_ADDR; 10028 return (warn_code); 10029 } 10030 eep_config = (ASCEEP_CONFIG *)&eep_config_buf; 10031 cfg_msw = AscGetChipCfgMsw(iop_base); 10032 cfg_lsw = AscGetChipCfgLsw(iop_base); 10033 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 10034 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 10035 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 10036 AscSetChipCfgMsw(iop_base, cfg_msw); 10037 } 10038 chksum = AscGetEEPConfig(iop_base, eep_config, asc_dvc->bus_type); 10039 ASC_DBG(1, "chksum 0x%x\n", chksum); 10040 if (chksum == 0) { 10041 chksum = 0xaa55; 10042 } 10043 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) { 10044 warn_code |= ASC_WARN_AUTO_CONFIG; 10045 if (asc_dvc->cfg->chip_version == 3) { 10046 if (eep_config->cfg_lsw != cfg_lsw) { 10047 warn_code |= ASC_WARN_EEPROM_RECOVER; 10048 eep_config->cfg_lsw = 10049 AscGetChipCfgLsw(iop_base); 10050 } 10051 if (eep_config->cfg_msw != cfg_msw) { 10052 warn_code |= ASC_WARN_EEPROM_RECOVER; 10053 eep_config->cfg_msw = 10054 AscGetChipCfgMsw(iop_base); 10055 } 10056 } 10057 } 10058 eep_config->cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 10059 eep_config->cfg_lsw |= ASC_CFG0_HOST_INT_ON; 10060 ASC_DBG(1, "eep_config->chksum 0x%x\n", eep_config->chksum); 10061 if (chksum != eep_config->chksum) { 10062 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) == 10063 ASC_CHIP_VER_PCI_ULTRA_3050) { 10064 ASC_DBG(1, "chksum error ignored; EEPROM-less board\n"); 10065 eep_config->init_sdtr = 0xFF; 10066 eep_config->disc_enable = 0xFF; 10067 eep_config->start_motor = 0xFF; 10068 eep_config->use_cmd_qng = 0; 10069 eep_config->max_total_qng = 0xF0; 10070 eep_config->max_tag_qng = 0x20; 10071 eep_config->cntl = 0xBFFF; 10072 ASC_EEP_SET_CHIP_ID(eep_config, 7); 10073 eep_config->no_scam = 0; 10074 eep_config->adapter_info[0] = 0; 10075 eep_config->adapter_info[1] = 0; 10076 eep_config->adapter_info[2] = 0; 10077 eep_config->adapter_info[3] = 0; 10078 eep_config->adapter_info[4] = 0; 10079 /* Indicate EEPROM-less board. */ 10080 eep_config->adapter_info[5] = 0xBB; 10081 } else { 10082 ASC_PRINT 10083 ("AscInitFromEEP: EEPROM checksum error; Will try to re-write EEPROM.\n"); 10084 write_eep = 1; 10085 warn_code |= ASC_WARN_EEPROM_CHKSUM; 10086 } 10087 } 10088 asc_dvc->cfg->sdtr_enable = eep_config->init_sdtr; 10089 asc_dvc->cfg->disc_enable = eep_config->disc_enable; 10090 asc_dvc->cfg->cmd_qng_enabled = eep_config->use_cmd_qng; 10091 asc_dvc->cfg->isa_dma_speed = ASC_EEP_GET_DMA_SPD(eep_config); 10092 asc_dvc->start_motor = eep_config->start_motor; 10093 asc_dvc->dvc_cntl = eep_config->cntl; 10094 asc_dvc->no_scam = eep_config->no_scam; 10095 asc_dvc->cfg->adapter_info[0] = eep_config->adapter_info[0]; 10096 asc_dvc->cfg->adapter_info[1] = eep_config->adapter_info[1]; 10097 asc_dvc->cfg->adapter_info[2] = eep_config->adapter_info[2]; 10098 asc_dvc->cfg->adapter_info[3] = eep_config->adapter_info[3]; 10099 asc_dvc->cfg->adapter_info[4] = eep_config->adapter_info[4]; 10100 asc_dvc->cfg->adapter_info[5] = eep_config->adapter_info[5]; 10101 if (!AscTestExternalLram(asc_dvc)) { 10102 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == 10103 ASC_IS_PCI_ULTRA)) { 10104 eep_config->max_total_qng = 10105 ASC_MAX_PCI_ULTRA_INRAM_TOTAL_QNG; 10106 eep_config->max_tag_qng = 10107 ASC_MAX_PCI_ULTRA_INRAM_TAG_QNG; 10108 } else { 10109 eep_config->cfg_msw |= 0x0800; 10110 cfg_msw |= 0x0800; 10111 AscSetChipCfgMsw(iop_base, cfg_msw); 10112 eep_config->max_total_qng = ASC_MAX_PCI_INRAM_TOTAL_QNG; 10113 eep_config->max_tag_qng = ASC_MAX_INRAM_TAG_QNG; 10114 } 10115 } else { 10116 } 10117 if (eep_config->max_total_qng < ASC_MIN_TOTAL_QNG) { 10118 eep_config->max_total_qng = ASC_MIN_TOTAL_QNG; 10119 } 10120 if (eep_config->max_total_qng > ASC_MAX_TOTAL_QNG) { 10121 eep_config->max_total_qng = ASC_MAX_TOTAL_QNG; 10122 } 10123 if (eep_config->max_tag_qng > eep_config->max_total_qng) { 10124 eep_config->max_tag_qng = eep_config->max_total_qng; 10125 } 10126 if (eep_config->max_tag_qng < ASC_MIN_TAG_Q_PER_DVC) { 10127 eep_config->max_tag_qng = ASC_MIN_TAG_Q_PER_DVC; 10128 } 10129 asc_dvc->max_total_qng = eep_config->max_total_qng; 10130 if ((eep_config->use_cmd_qng & eep_config->disc_enable) != 10131 eep_config->use_cmd_qng) { 10132 eep_config->disc_enable = eep_config->use_cmd_qng; 10133 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 10134 } 10135 ASC_EEP_SET_CHIP_ID(eep_config, 10136 ASC_EEP_GET_CHIP_ID(eep_config) & ASC_MAX_TID); 10137 asc_dvc->cfg->chip_scsi_id = ASC_EEP_GET_CHIP_ID(eep_config); 10138 if (((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) && 10139 !(asc_dvc->dvc_cntl & ASC_CNTL_SDTR_ENABLE_ULTRA)) { 10140 asc_dvc->min_sdtr_index = ASC_SDTR_ULTRA_PCI_10MB_INDEX; 10141 } 10142 10143 for (i = 0; i <= ASC_MAX_TID; i++) { 10144 asc_dvc->dos_int13_table[i] = eep_config->dos_int13_table[i]; 10145 asc_dvc->cfg->max_tag_qng[i] = eep_config->max_tag_qng; 10146 asc_dvc->cfg->sdtr_period_offset[i] = 10147 (uchar)(ASC_DEF_SDTR_OFFSET | 10148 (asc_dvc->min_sdtr_index << 4)); 10149 } 10150 eep_config->cfg_msw = AscGetChipCfgMsw(iop_base); 10151 if (write_eep) { 10152 if ((i = AscSetEEPConfig(iop_base, eep_config, 10153 asc_dvc->bus_type)) != 0) { 10154 ASC_PRINT1 10155 ("AscInitFromEEP: Failed to re-write EEPROM with %d errors.\n", 10156 i); 10157 } else { 10158 ASC_PRINT 10159 ("AscInitFromEEP: Successfully re-wrote EEPROM.\n"); 10160 } 10161 } 10162 return (warn_code); 10163} 10164 10165static int __devinit AscInitGetConfig(struct Scsi_Host *shost) 10166{ 10167 struct asc_board *board = shost_priv(shost); 10168 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var; 10169 unsigned short warn_code = 0; 10170 10171 asc_dvc->init_state = ASC_INIT_STATE_BEG_GET_CFG; 10172 if (asc_dvc->err_code != 0) 10173 return asc_dvc->err_code; 10174 10175 if (AscFindSignature(asc_dvc->iop_base)) { 10176 warn_code |= AscInitAscDvcVar(asc_dvc); 10177 warn_code |= AscInitFromEEP(asc_dvc); 10178 asc_dvc->init_state |= ASC_INIT_STATE_END_GET_CFG; 10179 if (asc_dvc->scsi_reset_wait > ASC_MAX_SCSI_RESET_WAIT) 10180 asc_dvc->scsi_reset_wait = ASC_MAX_SCSI_RESET_WAIT; 10181 } else { 10182 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 10183 } 10184 10185 switch (warn_code) { 10186 case 0: /* No error */ 10187 break; 10188 case ASC_WARN_IO_PORT_ROTATE: 10189 shost_printk(KERN_WARNING, shost, "I/O port address " 10190 "modified\n"); 10191 break; 10192 case ASC_WARN_AUTO_CONFIG: 10193 shost_printk(KERN_WARNING, shost, "I/O port increment switch " 10194 "enabled\n"); 10195 break; 10196 case ASC_WARN_EEPROM_CHKSUM: 10197 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n"); 10198 break; 10199 case ASC_WARN_IRQ_MODIFIED: 10200 shost_printk(KERN_WARNING, shost, "IRQ modified\n"); 10201 break; 10202 case ASC_WARN_CMD_QNG_CONFLICT: 10203 shost_printk(KERN_WARNING, shost, "tag queuing enabled w/o " 10204 "disconnects\n"); 10205 break; 10206 default: 10207 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n", 10208 warn_code); 10209 break; 10210 } 10211 10212 if (asc_dvc->err_code != 0) 10213 shost_printk(KERN_ERR, shost, "error 0x%x at init_state " 10214 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state); 10215 10216 return asc_dvc->err_code; 10217} 10218 10219static int __devinit AscInitSetConfig(struct pci_dev *pdev, struct Scsi_Host *shost) 10220{ 10221 struct asc_board *board = shost_priv(shost); 10222 ASC_DVC_VAR *asc_dvc = &board->dvc_var.asc_dvc_var; 10223 PortAddr iop_base = asc_dvc->iop_base; 10224 unsigned short cfg_msw; 10225 unsigned short warn_code = 0; 10226 10227 asc_dvc->init_state |= ASC_INIT_STATE_BEG_SET_CFG; 10228 if (asc_dvc->err_code != 0) 10229 return asc_dvc->err_code; 10230 if (!AscFindSignature(asc_dvc->iop_base)) { 10231 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 10232 return asc_dvc->err_code; 10233 } 10234 10235 cfg_msw = AscGetChipCfgMsw(iop_base); 10236 if ((cfg_msw & ASC_CFG_MSW_CLR_MASK) != 0) { 10237 cfg_msw &= ~ASC_CFG_MSW_CLR_MASK; 10238 warn_code |= ASC_WARN_CFG_MSW_RECOVER; 10239 AscSetChipCfgMsw(iop_base, cfg_msw); 10240 } 10241 if ((asc_dvc->cfg->cmd_qng_enabled & asc_dvc->cfg->disc_enable) != 10242 asc_dvc->cfg->cmd_qng_enabled) { 10243 asc_dvc->cfg->disc_enable = asc_dvc->cfg->cmd_qng_enabled; 10244 warn_code |= ASC_WARN_CMD_QNG_CONFLICT; 10245 } 10246 if (AscGetChipStatus(iop_base) & CSW_AUTO_CONFIG) { 10247 warn_code |= ASC_WARN_AUTO_CONFIG; 10248 } 10249#ifdef CONFIG_PCI 10250 if (asc_dvc->bus_type & ASC_IS_PCI) { 10251 cfg_msw &= 0xFFC0; 10252 AscSetChipCfgMsw(iop_base, cfg_msw); 10253 if ((asc_dvc->bus_type & ASC_IS_PCI_ULTRA) == ASC_IS_PCI_ULTRA) { 10254 } else { 10255 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) || 10256 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) { 10257 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_IF_NOT_DWB; 10258 asc_dvc->bug_fix_cntl |= 10259 ASC_BUG_FIX_ASYN_USE_SYN; 10260 } 10261 } 10262 } else 10263#endif /* CONFIG_PCI */ 10264 if (asc_dvc->bus_type == ASC_IS_ISAPNP) { 10265 if (AscGetChipVersion(iop_base, asc_dvc->bus_type) 10266 == ASC_CHIP_VER_ASYN_BUG) { 10267 asc_dvc->bug_fix_cntl |= ASC_BUG_FIX_ASYN_USE_SYN; 10268 } 10269 } 10270 if (AscSetChipScsiID(iop_base, asc_dvc->cfg->chip_scsi_id) != 10271 asc_dvc->cfg->chip_scsi_id) { 10272 asc_dvc->err_code |= ASC_IERR_SET_SCSI_ID; 10273 } 10274#ifdef CONFIG_ISA 10275 if (asc_dvc->bus_type & ASC_IS_ISA) { 10276 AscSetIsaDmaChannel(iop_base, asc_dvc->cfg->isa_dma_channel); 10277 AscSetIsaDmaSpeed(iop_base, asc_dvc->cfg->isa_dma_speed); 10278 } 10279#endif /* CONFIG_ISA */ 10280 10281 asc_dvc->init_state |= ASC_INIT_STATE_END_SET_CFG; 10282 10283 switch (warn_code) { 10284 case 0: /* No error. */ 10285 break; 10286 case ASC_WARN_IO_PORT_ROTATE: 10287 shost_printk(KERN_WARNING, shost, "I/O port address " 10288 "modified\n"); 10289 break; 10290 case ASC_WARN_AUTO_CONFIG: 10291 shost_printk(KERN_WARNING, shost, "I/O port increment switch " 10292 "enabled\n"); 10293 break; 10294 case ASC_WARN_EEPROM_CHKSUM: 10295 shost_printk(KERN_WARNING, shost, "EEPROM checksum error\n"); 10296 break; 10297 case ASC_WARN_IRQ_MODIFIED: 10298 shost_printk(KERN_WARNING, shost, "IRQ modified\n"); 10299 break; 10300 case ASC_WARN_CMD_QNG_CONFLICT: 10301 shost_printk(KERN_WARNING, shost, "tag queuing w/o " 10302 "disconnects\n"); 10303 break; 10304 default: 10305 shost_printk(KERN_WARNING, shost, "unknown warning: 0x%x\n", 10306 warn_code); 10307 break; 10308 } 10309 10310 if (asc_dvc->err_code != 0) 10311 shost_printk(KERN_ERR, shost, "error 0x%x at init_state " 10312 "0x%x\n", asc_dvc->err_code, asc_dvc->init_state); 10313 10314 return asc_dvc->err_code; 10315} 10316 10317/* 10318 * EEPROM Configuration. 10319 * 10320 * All drivers should use this structure to set the default EEPROM 10321 * configuration. The BIOS now uses this structure when it is built. 10322 * Additional structure information can be found in a_condor.h where 10323 * the structure is defined. 10324 * 10325 * The *_Field_IsChar structs are needed to correct for endianness. 10326 * These values are read from the board 16 bits at a time directly 10327 * into the structs. Because some fields are char, the values will be 10328 * in the wrong order. The *_Field_IsChar tells when to flip the 10329 * bytes. Data read and written to PCI memory is automatically swapped 10330 * on big-endian platforms so char fields read as words are actually being 10331 * unswapped on big-endian platforms. 10332 */ 10333static ADVEEP_3550_CONFIG Default_3550_EEPROM_Config __devinitdata = { 10334 ADV_EEPROM_BIOS_ENABLE, /* cfg_lsw */ 10335 0x0000, /* cfg_msw */ 10336 0xFFFF, /* disc_enable */ 10337 0xFFFF, /* wdtr_able */ 10338 0xFFFF, /* sdtr_able */ 10339 0xFFFF, /* start_motor */ 10340 0xFFFF, /* tagqng_able */ 10341 0xFFFF, /* bios_scan */ 10342 0, /* scam_tolerant */ 10343 7, /* adapter_scsi_id */ 10344 0, /* bios_boot_delay */ 10345 3, /* scsi_reset_delay */ 10346 0, /* bios_id_lun */ 10347 0, /* termination */ 10348 0, /* reserved1 */ 10349 0xFFE7, /* bios_ctrl */ 10350 0xFFFF, /* ultra_able */ 10351 0, /* reserved2 */ 10352 ASC_DEF_MAX_HOST_QNG, /* max_host_qng */ 10353 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 10354 0, /* dvc_cntl */ 10355 0, /* bug_fix */ 10356 0, /* serial_number_word1 */ 10357 0, /* serial_number_word2 */ 10358 0, /* serial_number_word3 */ 10359 0, /* check_sum */ 10360 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 10361 , /* oem_name[16] */ 10362 0, /* dvc_err_code */ 10363 0, /* adv_err_code */ 10364 0, /* adv_err_addr */ 10365 0, /* saved_dvc_err_code */ 10366 0, /* saved_adv_err_code */ 10367 0, /* saved_adv_err_addr */ 10368 0 /* num_of_err */ 10369}; 10370 10371static ADVEEP_3550_CONFIG ADVEEP_3550_Config_Field_IsChar __devinitdata = { 10372 0, /* cfg_lsw */ 10373 0, /* cfg_msw */ 10374 0, /* -disc_enable */ 10375 0, /* wdtr_able */ 10376 0, /* sdtr_able */ 10377 0, /* start_motor */ 10378 0, /* tagqng_able */ 10379 0, /* bios_scan */ 10380 0, /* scam_tolerant */ 10381 1, /* adapter_scsi_id */ 10382 1, /* bios_boot_delay */ 10383 1, /* scsi_reset_delay */ 10384 1, /* bios_id_lun */ 10385 1, /* termination */ 10386 1, /* reserved1 */ 10387 0, /* bios_ctrl */ 10388 0, /* ultra_able */ 10389 0, /* reserved2 */ 10390 1, /* max_host_qng */ 10391 1, /* max_dvc_qng */ 10392 0, /* dvc_cntl */ 10393 0, /* bug_fix */ 10394 0, /* serial_number_word1 */ 10395 0, /* serial_number_word2 */ 10396 0, /* serial_number_word3 */ 10397 0, /* check_sum */ 10398 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} 10399 , /* oem_name[16] */ 10400 0, /* dvc_err_code */ 10401 0, /* adv_err_code */ 10402 0, /* adv_err_addr */ 10403 0, /* saved_dvc_err_code */ 10404 0, /* saved_adv_err_code */ 10405 0, /* saved_adv_err_addr */ 10406 0 /* num_of_err */ 10407}; 10408 10409static ADVEEP_38C0800_CONFIG Default_38C0800_EEPROM_Config __devinitdata = { 10410 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 10411 0x0000, /* 01 cfg_msw */ 10412 0xFFFF, /* 02 disc_enable */ 10413 0xFFFF, /* 03 wdtr_able */ 10414 0x4444, /* 04 sdtr_speed1 */ 10415 0xFFFF, /* 05 start_motor */ 10416 0xFFFF, /* 06 tagqng_able */ 10417 0xFFFF, /* 07 bios_scan */ 10418 0, /* 08 scam_tolerant */ 10419 7, /* 09 adapter_scsi_id */ 10420 0, /* bios_boot_delay */ 10421 3, /* 10 scsi_reset_delay */ 10422 0, /* bios_id_lun */ 10423 0, /* 11 termination_se */ 10424 0, /* termination_lvd */ 10425 0xFFE7, /* 12 bios_ctrl */ 10426 0x4444, /* 13 sdtr_speed2 */ 10427 0x4444, /* 14 sdtr_speed3 */ 10428 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 10429 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 10430 0, /* 16 dvc_cntl */ 10431 0x4444, /* 17 sdtr_speed4 */ 10432 0, /* 18 serial_number_word1 */ 10433 0, /* 19 serial_number_word2 */ 10434 0, /* 20 serial_number_word3 */ 10435 0, /* 21 check_sum */ 10436 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 10437 , /* 22-29 oem_name[16] */ 10438 0, /* 30 dvc_err_code */ 10439 0, /* 31 adv_err_code */ 10440 0, /* 32 adv_err_addr */ 10441 0, /* 33 saved_dvc_err_code */ 10442 0, /* 34 saved_adv_err_code */ 10443 0, /* 35 saved_adv_err_addr */ 10444 0, /* 36 reserved */ 10445 0, /* 37 reserved */ 10446 0, /* 38 reserved */ 10447 0, /* 39 reserved */ 10448 0, /* 40 reserved */ 10449 0, /* 41 reserved */ 10450 0, /* 42 reserved */ 10451 0, /* 43 reserved */ 10452 0, /* 44 reserved */ 10453 0, /* 45 reserved */ 10454 0, /* 46 reserved */ 10455 0, /* 47 reserved */ 10456 0, /* 48 reserved */ 10457 0, /* 49 reserved */ 10458 0, /* 50 reserved */ 10459 0, /* 51 reserved */ 10460 0, /* 52 reserved */ 10461 0, /* 53 reserved */ 10462 0, /* 54 reserved */ 10463 0, /* 55 reserved */ 10464 0, /* 56 cisptr_lsw */ 10465 0, /* 57 cisprt_msw */ 10466 PCI_VENDOR_ID_ASP, /* 58 subsysvid */ 10467 PCI_DEVICE_ID_38C0800_REV1, /* 59 subsysid */ 10468 0, /* 60 reserved */ 10469 0, /* 61 reserved */ 10470 0, /* 62 reserved */ 10471 0 /* 63 reserved */ 10472}; 10473 10474static ADVEEP_38C0800_CONFIG ADVEEP_38C0800_Config_Field_IsChar __devinitdata = { 10475 0, /* 00 cfg_lsw */ 10476 0, /* 01 cfg_msw */ 10477 0, /* 02 disc_enable */ 10478 0, /* 03 wdtr_able */ 10479 0, /* 04 sdtr_speed1 */ 10480 0, /* 05 start_motor */ 10481 0, /* 06 tagqng_able */ 10482 0, /* 07 bios_scan */ 10483 0, /* 08 scam_tolerant */ 10484 1, /* 09 adapter_scsi_id */ 10485 1, /* bios_boot_delay */ 10486 1, /* 10 scsi_reset_delay */ 10487 1, /* bios_id_lun */ 10488 1, /* 11 termination_se */ 10489 1, /* termination_lvd */ 10490 0, /* 12 bios_ctrl */ 10491 0, /* 13 sdtr_speed2 */ 10492 0, /* 14 sdtr_speed3 */ 10493 1, /* 15 max_host_qng */ 10494 1, /* max_dvc_qng */ 10495 0, /* 16 dvc_cntl */ 10496 0, /* 17 sdtr_speed4 */ 10497 0, /* 18 serial_number_word1 */ 10498 0, /* 19 serial_number_word2 */ 10499 0, /* 20 serial_number_word3 */ 10500 0, /* 21 check_sum */ 10501 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} 10502 , /* 22-29 oem_name[16] */ 10503 0, /* 30 dvc_err_code */ 10504 0, /* 31 adv_err_code */ 10505 0, /* 32 adv_err_addr */ 10506 0, /* 33 saved_dvc_err_code */ 10507 0, /* 34 saved_adv_err_code */ 10508 0, /* 35 saved_adv_err_addr */ 10509 0, /* 36 reserved */ 10510 0, /* 37 reserved */ 10511 0, /* 38 reserved */ 10512 0, /* 39 reserved */ 10513 0, /* 40 reserved */ 10514 0, /* 41 reserved */ 10515 0, /* 42 reserved */ 10516 0, /* 43 reserved */ 10517 0, /* 44 reserved */ 10518 0, /* 45 reserved */ 10519 0, /* 46 reserved */ 10520 0, /* 47 reserved */ 10521 0, /* 48 reserved */ 10522 0, /* 49 reserved */ 10523 0, /* 50 reserved */ 10524 0, /* 51 reserved */ 10525 0, /* 52 reserved */ 10526 0, /* 53 reserved */ 10527 0, /* 54 reserved */ 10528 0, /* 55 reserved */ 10529 0, /* 56 cisptr_lsw */ 10530 0, /* 57 cisprt_msw */ 10531 0, /* 58 subsysvid */ 10532 0, /* 59 subsysid */ 10533 0, /* 60 reserved */ 10534 0, /* 61 reserved */ 10535 0, /* 62 reserved */ 10536 0 /* 63 reserved */ 10537}; 10538 10539static ADVEEP_38C1600_CONFIG Default_38C1600_EEPROM_Config __devinitdata = { 10540 ADV_EEPROM_BIOS_ENABLE, /* 00 cfg_lsw */ 10541 0x0000, /* 01 cfg_msw */ 10542 0xFFFF, /* 02 disc_enable */ 10543 0xFFFF, /* 03 wdtr_able */ 10544 0x5555, /* 04 sdtr_speed1 */ 10545 0xFFFF, /* 05 start_motor */ 10546 0xFFFF, /* 06 tagqng_able */ 10547 0xFFFF, /* 07 bios_scan */ 10548 0, /* 08 scam_tolerant */ 10549 7, /* 09 adapter_scsi_id */ 10550 0, /* bios_boot_delay */ 10551 3, /* 10 scsi_reset_delay */ 10552 0, /* bios_id_lun */ 10553 0, /* 11 termination_se */ 10554 0, /* termination_lvd */ 10555 0xFFE7, /* 12 bios_ctrl */ 10556 0x5555, /* 13 sdtr_speed2 */ 10557 0x5555, /* 14 sdtr_speed3 */ 10558 ASC_DEF_MAX_HOST_QNG, /* 15 max_host_qng */ 10559 ASC_DEF_MAX_DVC_QNG, /* max_dvc_qng */ 10560 0, /* 16 dvc_cntl */ 10561 0x5555, /* 17 sdtr_speed4 */ 10562 0, /* 18 serial_number_word1 */ 10563 0, /* 19 serial_number_word2 */ 10564 0, /* 20 serial_number_word3 */ 10565 0, /* 21 check_sum */ 10566 {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0} 10567 , /* 22-29 oem_name[16] */ 10568 0, /* 30 dvc_err_code */ 10569 0, /* 31 adv_err_code */ 10570 0, /* 32 adv_err_addr */ 10571 0, /* 33 saved_dvc_err_code */ 10572 0, /* 34 saved_adv_err_code */ 10573 0, /* 35 saved_adv_err_addr */ 10574 0, /* 36 reserved */ 10575 0, /* 37 reserved */ 10576 0, /* 38 reserved */ 10577 0, /* 39 reserved */ 10578 0, /* 40 reserved */ 10579 0, /* 41 reserved */ 10580 0, /* 42 reserved */ 10581 0, /* 43 reserved */ 10582 0, /* 44 reserved */ 10583 0, /* 45 reserved */ 10584 0, /* 46 reserved */ 10585 0, /* 47 reserved */ 10586 0, /* 48 reserved */ 10587 0, /* 49 reserved */ 10588 0, /* 50 reserved */ 10589 0, /* 51 reserved */ 10590 0, /* 52 reserved */ 10591 0, /* 53 reserved */ 10592 0, /* 54 reserved */ 10593 0, /* 55 reserved */ 10594 0, /* 56 cisptr_lsw */ 10595 0, /* 57 cisprt_msw */ 10596 PCI_VENDOR_ID_ASP, /* 58 subsysvid */ 10597 PCI_DEVICE_ID_38C1600_REV1, /* 59 subsysid */ 10598 0, /* 60 reserved */ 10599 0, /* 61 reserved */ 10600 0, /* 62 reserved */ 10601 0 /* 63 reserved */ 10602}; 10603 10604static ADVEEP_38C1600_CONFIG ADVEEP_38C1600_Config_Field_IsChar __devinitdata = { 10605 0, /* 00 cfg_lsw */ 10606 0, /* 01 cfg_msw */ 10607 0, /* 02 disc_enable */ 10608 0, /* 03 wdtr_able */ 10609 0, /* 04 sdtr_speed1 */ 10610 0, /* 05 start_motor */ 10611 0, /* 06 tagqng_able */ 10612 0, /* 07 bios_scan */ 10613 0, /* 08 scam_tolerant */ 10614 1, /* 09 adapter_scsi_id */ 10615 1, /* bios_boot_delay */ 10616 1, /* 10 scsi_reset_delay */ 10617 1, /* bios_id_lun */ 10618 1, /* 11 termination_se */ 10619 1, /* termination_lvd */ 10620 0, /* 12 bios_ctrl */ 10621 0, /* 13 sdtr_speed2 */ 10622 0, /* 14 sdtr_speed3 */ 10623 1, /* 15 max_host_qng */ 10624 1, /* max_dvc_qng */ 10625 0, /* 16 dvc_cntl */ 10626 0, /* 17 sdtr_speed4 */ 10627 0, /* 18 serial_number_word1 */ 10628 0, /* 19 serial_number_word2 */ 10629 0, /* 20 serial_number_word3 */ 10630 0, /* 21 check_sum */ 10631 {1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1} 10632 , /* 22-29 oem_name[16] */ 10633 0, /* 30 dvc_err_code */ 10634 0, /* 31 adv_err_code */ 10635 0, /* 32 adv_err_addr */ 10636 0, /* 33 saved_dvc_err_code */ 10637 0, /* 34 saved_adv_err_code */ 10638 0, /* 35 saved_adv_err_addr */ 10639 0, /* 36 reserved */ 10640 0, /* 37 reserved */ 10641 0, /* 38 reserved */ 10642 0, /* 39 reserved */ 10643 0, /* 40 reserved */ 10644 0, /* 41 reserved */ 10645 0, /* 42 reserved */ 10646 0, /* 43 reserved */ 10647 0, /* 44 reserved */ 10648 0, /* 45 reserved */ 10649 0, /* 46 reserved */ 10650 0, /* 47 reserved */ 10651 0, /* 48 reserved */ 10652 0, /* 49 reserved */ 10653 0, /* 50 reserved */ 10654 0, /* 51 reserved */ 10655 0, /* 52 reserved */ 10656 0, /* 53 reserved */ 10657 0, /* 54 reserved */ 10658 0, /* 55 reserved */ 10659 0, /* 56 cisptr_lsw */ 10660 0, /* 57 cisprt_msw */ 10661 0, /* 58 subsysvid */ 10662 0, /* 59 subsysid */ 10663 0, /* 60 reserved */ 10664 0, /* 61 reserved */ 10665 0, /* 62 reserved */ 10666 0 /* 63 reserved */ 10667}; 10668 10669#ifdef CONFIG_PCI 10670/* 10671 * Wait for EEPROM command to complete 10672 */ 10673static void __devinit AdvWaitEEPCmd(AdvPortAddr iop_base) 10674{ 10675 int eep_delay_ms; 10676 10677 for (eep_delay_ms = 0; eep_delay_ms < ADV_EEP_DELAY_MS; eep_delay_ms++) { 10678 if (AdvReadWordRegister(iop_base, IOPW_EE_CMD) & 10679 ASC_EEP_CMD_DONE) { 10680 break; 10681 } 10682 mdelay(1); 10683 } 10684 if ((AdvReadWordRegister(iop_base, IOPW_EE_CMD) & ASC_EEP_CMD_DONE) == 10685 0) 10686 BUG(); 10687} 10688 10689/* 10690 * Read the EEPROM from specified location 10691 */ 10692static ushort __devinit AdvReadEEPWord(AdvPortAddr iop_base, int eep_word_addr) 10693{ 10694 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 10695 ASC_EEP_CMD_READ | eep_word_addr); 10696 AdvWaitEEPCmd(iop_base); 10697 return AdvReadWordRegister(iop_base, IOPW_EE_DATA); 10698} 10699 10700/* 10701 * Write the EEPROM from 'cfg_buf'. 10702 */ 10703static void __devinit 10704AdvSet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf) 10705{ 10706 ushort *wbuf; 10707 ushort addr, chksum; 10708 ushort *charfields; 10709 10710 wbuf = (ushort *)cfg_buf; 10711 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar; 10712 chksum = 0; 10713 10714 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 10715 AdvWaitEEPCmd(iop_base); 10716 10717 /* 10718 * Write EEPROM from word 0 to word 20. 10719 */ 10720 for (addr = ADV_EEP_DVC_CFG_BEGIN; 10721 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { 10722 ushort word; 10723 10724 if (*charfields++) { 10725 word = cpu_to_le16(*wbuf); 10726 } else { 10727 word = *wbuf; 10728 } 10729 chksum += *wbuf; /* Checksum is calculated from word values. */ 10730 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 10731 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 10732 ASC_EEP_CMD_WRITE | addr); 10733 AdvWaitEEPCmd(iop_base); 10734 mdelay(ADV_EEP_DELAY_MS); 10735 } 10736 10737 /* 10738 * Write EEPROM checksum at word 21. 10739 */ 10740 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); 10741 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 10742 AdvWaitEEPCmd(iop_base); 10743 wbuf++; 10744 charfields++; 10745 10746 /* 10747 * Write EEPROM OEM name at words 22 to 29. 10748 */ 10749 for (addr = ADV_EEP_DVC_CTL_BEGIN; 10750 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 10751 ushort word; 10752 10753 if (*charfields++) { 10754 word = cpu_to_le16(*wbuf); 10755 } else { 10756 word = *wbuf; 10757 } 10758 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 10759 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 10760 ASC_EEP_CMD_WRITE | addr); 10761 AdvWaitEEPCmd(iop_base); 10762 } 10763 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); 10764 AdvWaitEEPCmd(iop_base); 10765} 10766 10767/* 10768 * Write the EEPROM from 'cfg_buf'. 10769 */ 10770static void __devinit 10771AdvSet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf) 10772{ 10773 ushort *wbuf; 10774 ushort *charfields; 10775 ushort addr, chksum; 10776 10777 wbuf = (ushort *)cfg_buf; 10778 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar; 10779 chksum = 0; 10780 10781 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 10782 AdvWaitEEPCmd(iop_base); 10783 10784 /* 10785 * Write EEPROM from word 0 to word 20. 10786 */ 10787 for (addr = ADV_EEP_DVC_CFG_BEGIN; 10788 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { 10789 ushort word; 10790 10791 if (*charfields++) { 10792 word = cpu_to_le16(*wbuf); 10793 } else { 10794 word = *wbuf; 10795 } 10796 chksum += *wbuf; /* Checksum is calculated from word values. */ 10797 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 10798 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 10799 ASC_EEP_CMD_WRITE | addr); 10800 AdvWaitEEPCmd(iop_base); 10801 mdelay(ADV_EEP_DELAY_MS); 10802 } 10803 10804 /* 10805 * Write EEPROM checksum at word 21. 10806 */ 10807 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); 10808 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 10809 AdvWaitEEPCmd(iop_base); 10810 wbuf++; 10811 charfields++; 10812 10813 /* 10814 * Write EEPROM OEM name at words 22 to 29. 10815 */ 10816 for (addr = ADV_EEP_DVC_CTL_BEGIN; 10817 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 10818 ushort word; 10819 10820 if (*charfields++) { 10821 word = cpu_to_le16(*wbuf); 10822 } else { 10823 word = *wbuf; 10824 } 10825 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 10826 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 10827 ASC_EEP_CMD_WRITE | addr); 10828 AdvWaitEEPCmd(iop_base); 10829 } 10830 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); 10831 AdvWaitEEPCmd(iop_base); 10832} 10833 10834/* 10835 * Write the EEPROM from 'cfg_buf'. 10836 */ 10837static void __devinit 10838AdvSet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf) 10839{ 10840 ushort *wbuf; 10841 ushort *charfields; 10842 ushort addr, chksum; 10843 10844 wbuf = (ushort *)cfg_buf; 10845 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar; 10846 chksum = 0; 10847 10848 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_ABLE); 10849 AdvWaitEEPCmd(iop_base); 10850 10851 /* 10852 * Write EEPROM from word 0 to word 20. 10853 */ 10854 for (addr = ADV_EEP_DVC_CFG_BEGIN; 10855 addr < ADV_EEP_DVC_CFG_END; addr++, wbuf++) { 10856 ushort word; 10857 10858 if (*charfields++) { 10859 word = cpu_to_le16(*wbuf); 10860 } else { 10861 word = *wbuf; 10862 } 10863 chksum += *wbuf; /* Checksum is calculated from word values. */ 10864 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 10865 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 10866 ASC_EEP_CMD_WRITE | addr); 10867 AdvWaitEEPCmd(iop_base); 10868 mdelay(ADV_EEP_DELAY_MS); 10869 } 10870 10871 /* 10872 * Write EEPROM checksum at word 21. 10873 */ 10874 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, chksum); 10875 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE | addr); 10876 AdvWaitEEPCmd(iop_base); 10877 wbuf++; 10878 charfields++; 10879 10880 /* 10881 * Write EEPROM OEM name at words 22 to 29. 10882 */ 10883 for (addr = ADV_EEP_DVC_CTL_BEGIN; 10884 addr < ADV_EEP_MAX_WORD_ADDR; addr++, wbuf++) { 10885 ushort word; 10886 10887 if (*charfields++) { 10888 word = cpu_to_le16(*wbuf); 10889 } else { 10890 word = *wbuf; 10891 } 10892 AdvWriteWordRegister(iop_base, IOPW_EE_DATA, word); 10893 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, 10894 ASC_EEP_CMD_WRITE | addr); 10895 AdvWaitEEPCmd(iop_base); 10896 } 10897 AdvWriteWordRegister(iop_base, IOPW_EE_CMD, ASC_EEP_CMD_WRITE_DISABLE); 10898 AdvWaitEEPCmd(iop_base); 10899} 10900 10901/* 10902 * Read EEPROM configuration into the specified buffer. 10903 * 10904 * Return a checksum based on the EEPROM configuration read. 10905 */ 10906static ushort __devinit 10907AdvGet3550EEPConfig(AdvPortAddr iop_base, ADVEEP_3550_CONFIG *cfg_buf) 10908{ 10909 ushort wval, chksum; 10910 ushort *wbuf; 10911 int eep_addr; 10912 ushort *charfields; 10913 10914 charfields = (ushort *)&ADVEEP_3550_Config_Field_IsChar; 10915 wbuf = (ushort *)cfg_buf; 10916 chksum = 0; 10917 10918 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; 10919 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { 10920 wval = AdvReadEEPWord(iop_base, eep_addr); 10921 chksum += wval; /* Checksum is calculated from word values. */ 10922 if (*charfields++) { 10923 *wbuf = le16_to_cpu(wval); 10924 } else { 10925 *wbuf = wval; 10926 } 10927 } 10928 /* Read checksum word. */ 10929 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 10930 wbuf++; 10931 charfields++; 10932 10933 /* Read rest of EEPROM not covered by the checksum. */ 10934 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; 10935 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { 10936 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 10937 if (*charfields++) { 10938 *wbuf = le16_to_cpu(*wbuf); 10939 } 10940 } 10941 return chksum; 10942} 10943 10944/* 10945 * Read EEPROM configuration into the specified buffer. 10946 * 10947 * Return a checksum based on the EEPROM configuration read. 10948 */ 10949static ushort __devinit 10950AdvGet38C0800EEPConfig(AdvPortAddr iop_base, ADVEEP_38C0800_CONFIG *cfg_buf) 10951{ 10952 ushort wval, chksum; 10953 ushort *wbuf; 10954 int eep_addr; 10955 ushort *charfields; 10956 10957 charfields = (ushort *)&ADVEEP_38C0800_Config_Field_IsChar; 10958 wbuf = (ushort *)cfg_buf; 10959 chksum = 0; 10960 10961 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; 10962 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { 10963 wval = AdvReadEEPWord(iop_base, eep_addr); 10964 chksum += wval; /* Checksum is calculated from word values. */ 10965 if (*charfields++) { 10966 *wbuf = le16_to_cpu(wval); 10967 } else { 10968 *wbuf = wval; 10969 } 10970 } 10971 /* Read checksum word. */ 10972 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 10973 wbuf++; 10974 charfields++; 10975 10976 /* Read rest of EEPROM not covered by the checksum. */ 10977 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; 10978 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { 10979 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 10980 if (*charfields++) { 10981 *wbuf = le16_to_cpu(*wbuf); 10982 } 10983 } 10984 return chksum; 10985} 10986 10987/* 10988 * Read EEPROM configuration into the specified buffer. 10989 * 10990 * Return a checksum based on the EEPROM configuration read. 10991 */ 10992static ushort __devinit 10993AdvGet38C1600EEPConfig(AdvPortAddr iop_base, ADVEEP_38C1600_CONFIG *cfg_buf) 10994{ 10995 ushort wval, chksum; 10996 ushort *wbuf; 10997 int eep_addr; 10998 ushort *charfields; 10999 11000 charfields = (ushort *)&ADVEEP_38C1600_Config_Field_IsChar; 11001 wbuf = (ushort *)cfg_buf; 11002 chksum = 0; 11003 11004 for (eep_addr = ADV_EEP_DVC_CFG_BEGIN; 11005 eep_addr < ADV_EEP_DVC_CFG_END; eep_addr++, wbuf++) { 11006 wval = AdvReadEEPWord(iop_base, eep_addr); 11007 chksum += wval; /* Checksum is calculated from word values. */ 11008 if (*charfields++) { 11009 *wbuf = le16_to_cpu(wval); 11010 } else { 11011 *wbuf = wval; 11012 } 11013 } 11014 /* Read checksum word. */ 11015 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 11016 wbuf++; 11017 charfields++; 11018 11019 /* Read rest of EEPROM not covered by the checksum. */ 11020 for (eep_addr = ADV_EEP_DVC_CTL_BEGIN; 11021 eep_addr < ADV_EEP_MAX_WORD_ADDR; eep_addr++, wbuf++) { 11022 *wbuf = AdvReadEEPWord(iop_base, eep_addr); 11023 if (*charfields++) { 11024 *wbuf = le16_to_cpu(*wbuf); 11025 } 11026 } 11027 return chksum; 11028} 11029 11030/* 11031 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 11032 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 11033 * all of this is done. 11034 * 11035 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 11036 * 11037 * For a non-fatal error return a warning code. If there are no warnings 11038 * then 0 is returned. 11039 * 11040 * Note: Chip is stopped on entry. 11041 */ 11042static int __devinit AdvInitFrom3550EEP(ADV_DVC_VAR *asc_dvc) 11043{ 11044 AdvPortAddr iop_base; 11045 ushort warn_code; 11046 ADVEEP_3550_CONFIG eep_config; 11047 11048 iop_base = asc_dvc->iop_base; 11049 11050 warn_code = 0; 11051 11052 /* 11053 * Read the board's EEPROM configuration. 11054 * 11055 * Set default values if a bad checksum is found. 11056 */ 11057 if (AdvGet3550EEPConfig(iop_base, &eep_config) != eep_config.check_sum) { 11058 warn_code |= ASC_WARN_EEPROM_CHKSUM; 11059 11060 /* 11061 * Set EEPROM default values. 11062 */ 11063 memcpy(&eep_config, &Default_3550_EEPROM_Config, 11064 sizeof(ADVEEP_3550_CONFIG)); 11065 11066 /* 11067 * Assume the 6 byte board serial number that was read from 11068 * EEPROM is correct even if the EEPROM checksum failed. 11069 */ 11070 eep_config.serial_number_word3 = 11071 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); 11072 11073 eep_config.serial_number_word2 = 11074 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); 11075 11076 eep_config.serial_number_word1 = 11077 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); 11078 11079 AdvSet3550EEPConfig(iop_base, &eep_config); 11080 } 11081 /* 11082 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the 11083 * EEPROM configuration that was read. 11084 * 11085 * This is the mapping of EEPROM fields to Adv Library fields. 11086 */ 11087 asc_dvc->wdtr_able = eep_config.wdtr_able; 11088 asc_dvc->sdtr_able = eep_config.sdtr_able; 11089 asc_dvc->ultra_able = eep_config.ultra_able; 11090 asc_dvc->tagqng_able = eep_config.tagqng_able; 11091 asc_dvc->cfg->disc_enable = eep_config.disc_enable; 11092 asc_dvc->max_host_qng = eep_config.max_host_qng; 11093 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 11094 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID); 11095 asc_dvc->start_motor = eep_config.start_motor; 11096 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; 11097 asc_dvc->bios_ctrl = eep_config.bios_ctrl; 11098 asc_dvc->no_scam = eep_config.scam_tolerant; 11099 asc_dvc->cfg->serial1 = eep_config.serial_number_word1; 11100 asc_dvc->cfg->serial2 = eep_config.serial_number_word2; 11101 asc_dvc->cfg->serial3 = eep_config.serial_number_word3; 11102 11103 /* 11104 * Set the host maximum queuing (max. 253, min. 16) and the per device 11105 * maximum queuing (max. 63, min. 4). 11106 */ 11107 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 11108 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 11109 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 11110 /* If the value is zero, assume it is uninitialized. */ 11111 if (eep_config.max_host_qng == 0) { 11112 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 11113 } else { 11114 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 11115 } 11116 } 11117 11118 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 11119 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 11120 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 11121 /* If the value is zero, assume it is uninitialized. */ 11122 if (eep_config.max_dvc_qng == 0) { 11123 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 11124 } else { 11125 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 11126 } 11127 } 11128 11129 /* 11130 * If 'max_dvc_qng' is greater than 'max_host_qng', then 11131 * set 'max_dvc_qng' to 'max_host_qng'. 11132 */ 11133 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 11134 eep_config.max_dvc_qng = eep_config.max_host_qng; 11135 } 11136 11137 /* 11138 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 11139 * values based on possibly adjusted EEPROM values. 11140 */ 11141 asc_dvc->max_host_qng = eep_config.max_host_qng; 11142 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 11143 11144 /* 11145 * If the EEPROM 'termination' field is set to automatic (0), then set 11146 * the ADV_DVC_CFG 'termination' field to automatic also. 11147 * 11148 * If the termination is specified with a non-zero 'termination' 11149 * value check that a legal value is set and set the ADV_DVC_CFG 11150 * 'termination' field appropriately. 11151 */ 11152 if (eep_config.termination == 0) { 11153 asc_dvc->cfg->termination = 0; /* auto termination */ 11154 } else { 11155 /* Enable manual control with low off / high off. */ 11156 if (eep_config.termination == 1) { 11157 asc_dvc->cfg->termination = TERM_CTL_SEL; 11158 11159 /* Enable manual control with low off / high on. */ 11160 } else if (eep_config.termination == 2) { 11161 asc_dvc->cfg->termination = TERM_CTL_SEL | TERM_CTL_H; 11162 11163 /* Enable manual control with low on / high on. */ 11164 } else if (eep_config.termination == 3) { 11165 asc_dvc->cfg->termination = 11166 TERM_CTL_SEL | TERM_CTL_H | TERM_CTL_L; 11167 } else { 11168 /* 11169 * The EEPROM 'termination' field contains a bad value. Use 11170 * automatic termination instead. 11171 */ 11172 asc_dvc->cfg->termination = 0; 11173 warn_code |= ASC_WARN_EEPROM_TERMINATION; 11174 } 11175 } 11176 11177 return warn_code; 11178} 11179 11180/* 11181 * Read the board's EEPROM configuration. Set fields in ADV_DVC_VAR and 11182 * ADV_DVC_CFG based on the EEPROM settings. The chip is stopped while 11183 * all of this is done. 11184 * 11185 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 11186 * 11187 * For a non-fatal error return a warning code. If there are no warnings 11188 * then 0 is returned. 11189 * 11190 * Note: Chip is stopped on entry. 11191 */ 11192static int __devinit AdvInitFrom38C0800EEP(ADV_DVC_VAR *asc_dvc) 11193{ 11194 AdvPortAddr iop_base; 11195 ushort warn_code; 11196 ADVEEP_38C0800_CONFIG eep_config; 11197 uchar tid, termination; 11198 ushort sdtr_speed = 0; 11199 11200 iop_base = asc_dvc->iop_base; 11201 11202 warn_code = 0; 11203 11204 /* 11205 * Read the board's EEPROM configuration. 11206 * 11207 * Set default values if a bad checksum is found. 11208 */ 11209 if (AdvGet38C0800EEPConfig(iop_base, &eep_config) != 11210 eep_config.check_sum) { 11211 warn_code |= ASC_WARN_EEPROM_CHKSUM; 11212 11213 /* 11214 * Set EEPROM default values. 11215 */ 11216 memcpy(&eep_config, &Default_38C0800_EEPROM_Config, 11217 sizeof(ADVEEP_38C0800_CONFIG)); 11218 11219 /* 11220 * Assume the 6 byte board serial number that was read from 11221 * EEPROM is correct even if the EEPROM checksum failed. 11222 */ 11223 eep_config.serial_number_word3 = 11224 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); 11225 11226 eep_config.serial_number_word2 = 11227 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); 11228 11229 eep_config.serial_number_word1 = 11230 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); 11231 11232 AdvSet38C0800EEPConfig(iop_base, &eep_config); 11233 } 11234 /* 11235 * Set ADV_DVC_VAR and ADV_DVC_CFG variables from the 11236 * EEPROM configuration that was read. 11237 * 11238 * This is the mapping of EEPROM fields to Adv Library fields. 11239 */ 11240 asc_dvc->wdtr_able = eep_config.wdtr_able; 11241 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1; 11242 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2; 11243 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3; 11244 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4; 11245 asc_dvc->tagqng_able = eep_config.tagqng_able; 11246 asc_dvc->cfg->disc_enable = eep_config.disc_enable; 11247 asc_dvc->max_host_qng = eep_config.max_host_qng; 11248 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 11249 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ADV_MAX_TID); 11250 asc_dvc->start_motor = eep_config.start_motor; 11251 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; 11252 asc_dvc->bios_ctrl = eep_config.bios_ctrl; 11253 asc_dvc->no_scam = eep_config.scam_tolerant; 11254 asc_dvc->cfg->serial1 = eep_config.serial_number_word1; 11255 asc_dvc->cfg->serial2 = eep_config.serial_number_word2; 11256 asc_dvc->cfg->serial3 = eep_config.serial_number_word3; 11257 11258 /* 11259 * For every Target ID if any of its 'sdtr_speed[1234]' bits 11260 * are set, then set an 'sdtr_able' bit for it. 11261 */ 11262 asc_dvc->sdtr_able = 0; 11263 for (tid = 0; tid <= ADV_MAX_TID; tid++) { 11264 if (tid == 0) { 11265 sdtr_speed = asc_dvc->sdtr_speed1; 11266 } else if (tid == 4) { 11267 sdtr_speed = asc_dvc->sdtr_speed2; 11268 } else if (tid == 8) { 11269 sdtr_speed = asc_dvc->sdtr_speed3; 11270 } else if (tid == 12) { 11271 sdtr_speed = asc_dvc->sdtr_speed4; 11272 } 11273 if (sdtr_speed & ADV_MAX_TID) { 11274 asc_dvc->sdtr_able |= (1 << tid); 11275 } 11276 sdtr_speed >>= 4; 11277 } 11278 11279 /* 11280 * Set the host maximum queuing (max. 253, min. 16) and the per device 11281 * maximum queuing (max. 63, min. 4). 11282 */ 11283 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 11284 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 11285 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 11286 /* If the value is zero, assume it is uninitialized. */ 11287 if (eep_config.max_host_qng == 0) { 11288 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 11289 } else { 11290 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 11291 } 11292 } 11293 11294 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 11295 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 11296 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 11297 /* If the value is zero, assume it is uninitialized. */ 11298 if (eep_config.max_dvc_qng == 0) { 11299 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 11300 } else { 11301 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 11302 } 11303 } 11304 11305 /* 11306 * If 'max_dvc_qng' is greater than 'max_host_qng', then 11307 * set 'max_dvc_qng' to 'max_host_qng'. 11308 */ 11309 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 11310 eep_config.max_dvc_qng = eep_config.max_host_qng; 11311 } 11312 11313 /* 11314 * Set ADV_DVC_VAR 'max_host_qng' and ADV_DVC_VAR 'max_dvc_qng' 11315 * values based on possibly adjusted EEPROM values. 11316 */ 11317 asc_dvc->max_host_qng = eep_config.max_host_qng; 11318 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 11319 11320 /* 11321 * If the EEPROM 'termination' field is set to automatic (0), then set 11322 * the ADV_DVC_CFG 'termination' field to automatic also. 11323 * 11324 * If the termination is specified with a non-zero 'termination' 11325 * value check that a legal value is set and set the ADV_DVC_CFG 11326 * 'termination' field appropriately. 11327 */ 11328 if (eep_config.termination_se == 0) { 11329 termination = 0; /* auto termination for SE */ 11330 } else { 11331 /* Enable manual control with low off / high off. */ 11332 if (eep_config.termination_se == 1) { 11333 termination = 0; 11334 11335 /* Enable manual control with low off / high on. */ 11336 } else if (eep_config.termination_se == 2) { 11337 termination = TERM_SE_HI; 11338 11339 /* Enable manual control with low on / high on. */ 11340 } else if (eep_config.termination_se == 3) { 11341 termination = TERM_SE; 11342 } else { 11343 /* 11344 * The EEPROM 'termination_se' field contains a bad value. 11345 * Use automatic termination instead. 11346 */ 11347 termination = 0; 11348 warn_code |= ASC_WARN_EEPROM_TERMINATION; 11349 } 11350 } 11351 11352 if (eep_config.termination_lvd == 0) { 11353 asc_dvc->cfg->termination = termination; /* auto termination for LVD */ 11354 } else { 11355 /* Enable manual control with low off / high off. */ 11356 if (eep_config.termination_lvd == 1) { 11357 asc_dvc->cfg->termination = termination; 11358 11359 /* Enable manual control with low off / high on. */ 11360 } else if (eep_config.termination_lvd == 2) { 11361 asc_dvc->cfg->termination = termination | TERM_LVD_HI; 11362 11363 /* Enable manual control with low on / high on. */ 11364 } else if (eep_config.termination_lvd == 3) { 11365 asc_dvc->cfg->termination = termination | TERM_LVD; 11366 } else { 11367 /* 11368 * The EEPROM 'termination_lvd' field contains a bad value. 11369 * Use automatic termination instead. 11370 */ 11371 asc_dvc->cfg->termination = termination; 11372 warn_code |= ASC_WARN_EEPROM_TERMINATION; 11373 } 11374 } 11375 11376 return warn_code; 11377} 11378 11379/* 11380 * Read the board's EEPROM configuration. Set fields in ASC_DVC_VAR and 11381 * ASC_DVC_CFG based on the EEPROM settings. The chip is stopped while 11382 * all of this is done. 11383 * 11384 * On failure set the ASC_DVC_VAR field 'err_code' and return ADV_ERROR. 11385 * 11386 * For a non-fatal error return a warning code. If there are no warnings 11387 * then 0 is returned. 11388 * 11389 * Note: Chip is stopped on entry. 11390 */ 11391static int __devinit AdvInitFrom38C1600EEP(ADV_DVC_VAR *asc_dvc) 11392{ 11393 AdvPortAddr iop_base; 11394 ushort warn_code; 11395 ADVEEP_38C1600_CONFIG eep_config; 11396 uchar tid, termination; 11397 ushort sdtr_speed = 0; 11398 11399 iop_base = asc_dvc->iop_base; 11400 11401 warn_code = 0; 11402 11403 /* 11404 * Read the board's EEPROM configuration. 11405 * 11406 * Set default values if a bad checksum is found. 11407 */ 11408 if (AdvGet38C1600EEPConfig(iop_base, &eep_config) != 11409 eep_config.check_sum) { 11410 struct pci_dev *pdev = adv_dvc_to_pdev(asc_dvc); 11411 warn_code |= ASC_WARN_EEPROM_CHKSUM; 11412 11413 /* 11414 * Set EEPROM default values. 11415 */ 11416 memcpy(&eep_config, &Default_38C1600_EEPROM_Config, 11417 sizeof(ADVEEP_38C1600_CONFIG)); 11418 11419 if (PCI_FUNC(pdev->devfn) != 0) { 11420 u8 ints; 11421 /* 11422 * Disable Bit 14 (BIOS_ENABLE) to fix SPARC Ultra 60 11423 * and old Mac system booting problem. The Expansion 11424 * ROM must be disabled in Function 1 for these systems 11425 */ 11426 eep_config.cfg_lsw &= ~ADV_EEPROM_BIOS_ENABLE; 11427 /* 11428 * Clear the INTAB (bit 11) if the GPIO 0 input 11429 * indicates the Function 1 interrupt line is wired 11430 * to INTB. 11431 * 11432 * Set/Clear Bit 11 (INTAB) from the GPIO bit 0 input: 11433 * 1 - Function 1 interrupt line wired to INT A. 11434 * 0 - Function 1 interrupt line wired to INT B. 11435 * 11436 * Note: Function 0 is always wired to INTA. 11437 * Put all 5 GPIO bits in input mode and then read 11438 * their input values. 11439 */ 11440 AdvWriteByteRegister(iop_base, IOPB_GPIO_CNTL, 0); 11441 ints = AdvReadByteRegister(iop_base, IOPB_GPIO_DATA); 11442 if ((ints & 0x01) == 0) 11443 eep_config.cfg_lsw &= ~ADV_EEPROM_INTAB; 11444 } 11445 11446 /* 11447 * Assume the 6 byte board serial number that was read from 11448 * EEPROM is correct even if the EEPROM checksum failed. 11449 */ 11450 eep_config.serial_number_word3 = 11451 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 1); 11452 eep_config.serial_number_word2 = 11453 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 2); 11454 eep_config.serial_number_word1 = 11455 AdvReadEEPWord(iop_base, ADV_EEP_DVC_CFG_END - 3); 11456 11457 AdvSet38C1600EEPConfig(iop_base, &eep_config); 11458 } 11459 11460 /* 11461 * Set ASC_DVC_VAR and ASC_DVC_CFG variables from the 11462 * EEPROM configuration that was read. 11463 * 11464 * This is the mapping of EEPROM fields to Adv Library fields. 11465 */ 11466 asc_dvc->wdtr_able = eep_config.wdtr_able; 11467 asc_dvc->sdtr_speed1 = eep_config.sdtr_speed1; 11468 asc_dvc->sdtr_speed2 = eep_config.sdtr_speed2; 11469 asc_dvc->sdtr_speed3 = eep_config.sdtr_speed3; 11470 asc_dvc->sdtr_speed4 = eep_config.sdtr_speed4; 11471 asc_dvc->ppr_able = 0; 11472 asc_dvc->tagqng_able = eep_config.tagqng_able; 11473 asc_dvc->cfg->disc_enable = eep_config.disc_enable; 11474 asc_dvc->max_host_qng = eep_config.max_host_qng; 11475 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 11476 asc_dvc->chip_scsi_id = (eep_config.adapter_scsi_id & ASC_MAX_TID); 11477 asc_dvc->start_motor = eep_config.start_motor; 11478 asc_dvc->scsi_reset_wait = eep_config.scsi_reset_delay; 11479 asc_dvc->bios_ctrl = eep_config.bios_ctrl; 11480 asc_dvc->no_scam = eep_config.scam_tolerant; 11481 11482 /* 11483 * For every Target ID if any of its 'sdtr_speed[1234]' bits 11484 * are set, then set an 'sdtr_able' bit for it. 11485 */ 11486 asc_dvc->sdtr_able = 0; 11487 for (tid = 0; tid <= ASC_MAX_TID; tid++) { 11488 if (tid == 0) { 11489 sdtr_speed = asc_dvc->sdtr_speed1; 11490 } else if (tid == 4) { 11491 sdtr_speed = asc_dvc->sdtr_speed2; 11492 } else if (tid == 8) { 11493 sdtr_speed = asc_dvc->sdtr_speed3; 11494 } else if (tid == 12) { 11495 sdtr_speed = asc_dvc->sdtr_speed4; 11496 } 11497 if (sdtr_speed & ASC_MAX_TID) { 11498 asc_dvc->sdtr_able |= (1 << tid); 11499 } 11500 sdtr_speed >>= 4; 11501 } 11502 11503 /* 11504 * Set the host maximum queuing (max. 253, min. 16) and the per device 11505 * maximum queuing (max. 63, min. 4). 11506 */ 11507 if (eep_config.max_host_qng > ASC_DEF_MAX_HOST_QNG) { 11508 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 11509 } else if (eep_config.max_host_qng < ASC_DEF_MIN_HOST_QNG) { 11510 /* If the value is zero, assume it is uninitialized. */ 11511 if (eep_config.max_host_qng == 0) { 11512 eep_config.max_host_qng = ASC_DEF_MAX_HOST_QNG; 11513 } else { 11514 eep_config.max_host_qng = ASC_DEF_MIN_HOST_QNG; 11515 } 11516 } 11517 11518 if (eep_config.max_dvc_qng > ASC_DEF_MAX_DVC_QNG) { 11519 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 11520 } else if (eep_config.max_dvc_qng < ASC_DEF_MIN_DVC_QNG) { 11521 /* If the value is zero, assume it is uninitialized. */ 11522 if (eep_config.max_dvc_qng == 0) { 11523 eep_config.max_dvc_qng = ASC_DEF_MAX_DVC_QNG; 11524 } else { 11525 eep_config.max_dvc_qng = ASC_DEF_MIN_DVC_QNG; 11526 } 11527 } 11528 11529 /* 11530 * If 'max_dvc_qng' is greater than 'max_host_qng', then 11531 * set 'max_dvc_qng' to 'max_host_qng'. 11532 */ 11533 if (eep_config.max_dvc_qng > eep_config.max_host_qng) { 11534 eep_config.max_dvc_qng = eep_config.max_host_qng; 11535 } 11536 11537 /* 11538 * Set ASC_DVC_VAR 'max_host_qng' and ASC_DVC_VAR 'max_dvc_qng' 11539 * values based on possibly adjusted EEPROM values. 11540 */ 11541 asc_dvc->max_host_qng = eep_config.max_host_qng; 11542 asc_dvc->max_dvc_qng = eep_config.max_dvc_qng; 11543 11544 /* 11545 * If the EEPROM 'termination' field is set to automatic (0), then set 11546 * the ASC_DVC_CFG 'termination' field to automatic also. 11547 * 11548 * If the termination is specified with a non-zero 'termination' 11549 * value check that a legal value is set and set the ASC_DVC_CFG 11550 * 'termination' field appropriately. 11551 */ 11552 if (eep_config.termination_se == 0) { 11553 termination = 0; /* auto termination for SE */ 11554 } else { 11555 /* Enable manual control with low off / high off. */ 11556 if (eep_config.termination_se == 1) { 11557 termination = 0; 11558 11559 /* Enable manual control with low off / high on. */ 11560 } else if (eep_config.termination_se == 2) { 11561 termination = TERM_SE_HI; 11562 11563 /* Enable manual control with low on / high on. */ 11564 } else if (eep_config.termination_se == 3) { 11565 termination = TERM_SE; 11566 } else { 11567 /* 11568 * The EEPROM 'termination_se' field contains a bad value. 11569 * Use automatic termination instead. 11570 */ 11571 termination = 0; 11572 warn_code |= ASC_WARN_EEPROM_TERMINATION; 11573 } 11574 } 11575 11576 if (eep_config.termination_lvd == 0) { 11577 asc_dvc->cfg->termination = termination; /* auto termination for LVD */ 11578 } else { 11579 /* Enable manual control with low off / high off. */ 11580 if (eep_config.termination_lvd == 1) { 11581 asc_dvc->cfg->termination = termination; 11582 11583 /* Enable manual control with low off / high on. */ 11584 } else if (eep_config.termination_lvd == 2) { 11585 asc_dvc->cfg->termination = termination | TERM_LVD_HI; 11586 11587 /* Enable manual control with low on / high on. */ 11588 } else if (eep_config.termination_lvd == 3) { 11589 asc_dvc->cfg->termination = termination | TERM_LVD; 11590 } else { 11591 /* 11592 * The EEPROM 'termination_lvd' field contains a bad value. 11593 * Use automatic termination instead. 11594 */ 11595 asc_dvc->cfg->termination = termination; 11596 warn_code |= ASC_WARN_EEPROM_TERMINATION; 11597 } 11598 } 11599 11600 return warn_code; 11601} 11602 11603/* 11604 * Initialize the ADV_DVC_VAR structure. 11605 * 11606 * On failure set the ADV_DVC_VAR field 'err_code' and return ADV_ERROR. 11607 * 11608 * For a non-fatal error return a warning code. If there are no warnings 11609 * then 0 is returned. 11610 */ 11611static int __devinit 11612AdvInitGetConfig(struct pci_dev *pdev, struct Scsi_Host *shost) 11613{ 11614 struct asc_board *board = shost_priv(shost); 11615 ADV_DVC_VAR *asc_dvc = &board->dvc_var.adv_dvc_var; 11616 unsigned short warn_code = 0; 11617 AdvPortAddr iop_base = asc_dvc->iop_base; 11618 u16 cmd; 11619 int status; 11620 11621 asc_dvc->err_code = 0; 11622 11623 /* 11624 * Save the state of the PCI Configuration Command Register 11625 * "Parity Error Response Control" Bit. If the bit is clear (0), 11626 * in AdvInitAsc3550/38C0800Driver() tell the microcode to ignore 11627 * DMA parity errors. 11628 */ 11629 asc_dvc->cfg->control_flag = 0; 11630 pci_read_config_word(pdev, PCI_COMMAND, &cmd); 11631 if ((cmd & PCI_COMMAND_PARITY) == 0) 11632 asc_dvc->cfg->control_flag |= CONTROL_FLAG_IGNORE_PERR; 11633 11634 asc_dvc->cfg->chip_version = 11635 AdvGetChipVersion(iop_base, asc_dvc->bus_type); 11636 11637 ASC_DBG(1, "iopb_chip_id_1: 0x%x 0x%x\n", 11638 (ushort)AdvReadByteRegister(iop_base, IOPB_CHIP_ID_1), 11639 (ushort)ADV_CHIP_ID_BYTE); 11640 11641 ASC_DBG(1, "iopw_chip_id_0: 0x%x 0x%x\n", 11642 (ushort)AdvReadWordRegister(iop_base, IOPW_CHIP_ID_0), 11643 (ushort)ADV_CHIP_ID_WORD); 11644 11645 /* 11646 * Reset the chip to start and allow register writes. 11647 */ 11648 if (AdvFindSignature(iop_base) == 0) { 11649 asc_dvc->err_code = ASC_IERR_BAD_SIGNATURE; 11650 return ADV_ERROR; 11651 } else { 11652 /* 11653 * The caller must set 'chip_type' to a valid setting. 11654 */ 11655 if (asc_dvc->chip_type != ADV_CHIP_ASC3550 && 11656 asc_dvc->chip_type != ADV_CHIP_ASC38C0800 && 11657 asc_dvc->chip_type != ADV_CHIP_ASC38C1600) { 11658 asc_dvc->err_code |= ASC_IERR_BAD_CHIPTYPE; 11659 return ADV_ERROR; 11660 } 11661 11662 /* 11663 * Reset Chip. 11664 */ 11665 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, 11666 ADV_CTRL_REG_CMD_RESET); 11667 mdelay(100); 11668 AdvWriteWordRegister(iop_base, IOPW_CTRL_REG, 11669 ADV_CTRL_REG_CMD_WR_IO_REG); 11670 11671 if (asc_dvc->chip_type == ADV_CHIP_ASC38C1600) { 11672 status = AdvInitFrom38C1600EEP(asc_dvc); 11673 } else if (asc_dvc->chip_type == ADV_CHIP_ASC38C0800) { 11674 status = AdvInitFrom38C0800EEP(asc_dvc); 11675 } else { 11676 status = AdvInitFrom3550EEP(asc_dvc); 11677 } 11678 warn_code |= status; 11679 } 11680 11681 if (warn_code != 0) 11682 shost_printk(KERN_WARNING, shost, "warning: 0x%x\n", warn_code); 11683 11684 if (asc_dvc->err_code) 11685 shost_printk(KERN_ERR, shost, "error code 0x%x\n", 11686 asc_dvc->err_code); 11687 11688 return asc_dvc->err_code; 11689} 11690#endif 11691 11692static struct scsi_host_template advansys_template = { 11693 .proc_name = DRV_NAME, 11694#ifdef CONFIG_PROC_FS 11695 .proc_info = advansys_proc_info, 11696#endif 11697 .name = DRV_NAME, 11698 .info = advansys_info, 11699 .queuecommand = advansys_queuecommand, 11700 .eh_bus_reset_handler = advansys_reset, 11701 .bios_param = advansys_biosparam, 11702 .slave_configure = advansys_slave_configure, 11703 /* 11704 * Because the driver may control an ISA adapter 'unchecked_isa_dma' 11705 * must be set. The flag will be cleared in advansys_board_found 11706 * for non-ISA adapters. 11707 */ 11708 .unchecked_isa_dma = 1, 11709 /* 11710 * All adapters controlled by this driver are capable of large 11711 * scatter-gather lists. According to the mid-level SCSI documentation 11712 * this obviates any performance gain provided by setting 11713 * 'use_clustering'. But empirically while CPU utilization is increased 11714 * by enabling clustering, I/O throughput increases as well. 11715 */ 11716 .use_clustering = ENABLE_CLUSTERING, 11717}; 11718 11719static int __devinit advansys_wide_init_chip(struct Scsi_Host *shost) 11720{ 11721 struct asc_board *board = shost_priv(shost); 11722 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var; 11723 int req_cnt = 0; 11724 adv_req_t *reqp = NULL; 11725 int sg_cnt = 0; 11726 adv_sgblk_t *sgp; 11727 int warn_code, err_code; 11728 11729 /* 11730 * Allocate buffer carrier structures. The total size 11731 * is about 4 KB, so allocate all at once. 11732 */ 11733 adv_dvc->carrier_buf = kmalloc(ADV_CARRIER_BUFSIZE, GFP_KERNEL); 11734 ASC_DBG(1, "carrier_buf 0x%p\n", adv_dvc->carrier_buf); 11735 11736 if (!adv_dvc->carrier_buf) 11737 goto kmalloc_failed; 11738 11739 /* 11740 * Allocate up to 'max_host_qng' request structures for the Wide 11741 * board. The total size is about 16 KB, so allocate all at once. 11742 * If the allocation fails decrement and try again. 11743 */ 11744 for (req_cnt = adv_dvc->max_host_qng; req_cnt > 0; req_cnt--) { 11745 reqp = kmalloc(sizeof(adv_req_t) * req_cnt, GFP_KERNEL); 11746 11747 ASC_DBG(1, "reqp 0x%p, req_cnt %d, bytes %lu\n", reqp, req_cnt, 11748 (ulong)sizeof(adv_req_t) * req_cnt); 11749 11750 if (reqp) 11751 break; 11752 } 11753 11754 if (!reqp) 11755 goto kmalloc_failed; 11756 11757 adv_dvc->orig_reqp = reqp; 11758 11759 /* 11760 * Allocate up to ADV_TOT_SG_BLOCK request structures for 11761 * the Wide board. Each structure is about 136 bytes. 11762 */ 11763 board->adv_sgblkp = NULL; 11764 for (sg_cnt = 0; sg_cnt < ADV_TOT_SG_BLOCK; sg_cnt++) { 11765 sgp = kmalloc(sizeof(adv_sgblk_t), GFP_KERNEL); 11766 11767 if (!sgp) 11768 break; 11769 11770 sgp->next_sgblkp = board->adv_sgblkp; 11771 board->adv_sgblkp = sgp; 11772 11773 } 11774 11775 ASC_DBG(1, "sg_cnt %d * %lu = %lu bytes\n", sg_cnt, sizeof(adv_sgblk_t), 11776 sizeof(adv_sgblk_t) * sg_cnt); 11777 11778 if (!board->adv_sgblkp) 11779 goto kmalloc_failed; 11780 11781 /* 11782 * Point 'adv_reqp' to the request structures and 11783 * link them together. 11784 */ 11785 req_cnt--; 11786 reqp[req_cnt].next_reqp = NULL; 11787 for (; req_cnt > 0; req_cnt--) { 11788 reqp[req_cnt - 1].next_reqp = &reqp[req_cnt]; 11789 } 11790 board->adv_reqp = &reqp[0]; 11791 11792 if (adv_dvc->chip_type == ADV_CHIP_ASC3550) { 11793 ASC_DBG(2, "AdvInitAsc3550Driver()\n"); 11794 warn_code = AdvInitAsc3550Driver(adv_dvc); 11795 } else if (adv_dvc->chip_type == ADV_CHIP_ASC38C0800) { 11796 ASC_DBG(2, "AdvInitAsc38C0800Driver()\n"); 11797 warn_code = AdvInitAsc38C0800Driver(adv_dvc); 11798 } else { 11799 ASC_DBG(2, "AdvInitAsc38C1600Driver()\n"); 11800 warn_code = AdvInitAsc38C1600Driver(adv_dvc); 11801 } 11802 err_code = adv_dvc->err_code; 11803 11804 if (warn_code || err_code) { 11805 shost_printk(KERN_WARNING, shost, "error: warn 0x%x, error " 11806 "0x%x\n", warn_code, err_code); 11807 } 11808 11809 goto exit; 11810 11811 kmalloc_failed: 11812 shost_printk(KERN_ERR, shost, "error: kmalloc() failed\n"); 11813 err_code = ADV_ERROR; 11814 exit: 11815 return err_code; 11816} 11817 11818static void advansys_wide_free_mem(struct asc_board *board) 11819{ 11820 struct adv_dvc_var *adv_dvc = &board->dvc_var.adv_dvc_var; 11821 kfree(adv_dvc->carrier_buf); 11822 adv_dvc->carrier_buf = NULL; 11823 kfree(adv_dvc->orig_reqp); 11824 adv_dvc->orig_reqp = board->adv_reqp = NULL; 11825 while (board->adv_sgblkp) { 11826 adv_sgblk_t *sgp = board->adv_sgblkp; 11827 board->adv_sgblkp = sgp->next_sgblkp; 11828 kfree(sgp); 11829 } 11830} 11831 11832static int __devinit advansys_board_found(struct Scsi_Host *shost, 11833 unsigned int iop, int bus_type) 11834{ 11835 struct pci_dev *pdev; 11836 struct asc_board *boardp = shost_priv(shost); 11837 ASC_DVC_VAR *asc_dvc_varp = NULL; 11838 ADV_DVC_VAR *adv_dvc_varp = NULL; 11839 int share_irq, warn_code, ret; 11840 11841 pdev = (bus_type == ASC_IS_PCI) ? to_pci_dev(boardp->dev) : NULL; 11842 11843 if (ASC_NARROW_BOARD(boardp)) { 11844 ASC_DBG(1, "narrow board\n"); 11845 asc_dvc_varp = &boardp->dvc_var.asc_dvc_var; 11846 asc_dvc_varp->bus_type = bus_type; 11847 asc_dvc_varp->drv_ptr = boardp; 11848 asc_dvc_varp->cfg = &boardp->dvc_cfg.asc_dvc_cfg; 11849 asc_dvc_varp->iop_base = iop; 11850 } else { 11851#ifdef CONFIG_PCI 11852 adv_dvc_varp = &boardp->dvc_var.adv_dvc_var; 11853 adv_dvc_varp->drv_ptr = boardp; 11854 adv_dvc_varp->cfg = &boardp->dvc_cfg.adv_dvc_cfg; 11855 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW) { 11856 ASC_DBG(1, "wide board ASC-3550\n"); 11857 adv_dvc_varp->chip_type = ADV_CHIP_ASC3550; 11858 } else if (pdev->device == PCI_DEVICE_ID_38C0800_REV1) { 11859 ASC_DBG(1, "wide board ASC-38C0800\n"); 11860 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C0800; 11861 } else { 11862 ASC_DBG(1, "wide board ASC-38C1600\n"); 11863 adv_dvc_varp->chip_type = ADV_CHIP_ASC38C1600; 11864 } 11865 11866 boardp->asc_n_io_port = pci_resource_len(pdev, 1); 11867 boardp->ioremap_addr = pci_ioremap_bar(pdev, 1); 11868 if (!boardp->ioremap_addr) { 11869 shost_printk(KERN_ERR, shost, "ioremap(%lx, %d) " 11870 "returned NULL\n", 11871 (long)pci_resource_start(pdev, 1), 11872 boardp->asc_n_io_port); 11873 ret = -ENODEV; 11874 goto err_shost; 11875 } 11876 adv_dvc_varp->iop_base = (AdvPortAddr)boardp->ioremap_addr; 11877 ASC_DBG(1, "iop_base: 0x%p\n", adv_dvc_varp->iop_base); 11878 11879 /* 11880 * Even though it isn't used to access wide boards, other 11881 * than for the debug line below, save I/O Port address so 11882 * that it can be reported. 11883 */ 11884 boardp->ioport = iop; 11885 11886 ASC_DBG(1, "iopb_chip_id_1 0x%x, iopw_chip_id_0 0x%x\n", 11887 (ushort)inp(iop + 1), (ushort)inpw(iop)); 11888#endif /* CONFIG_PCI */ 11889 } 11890 11891#ifdef CONFIG_PROC_FS 11892 /* 11893 * Allocate buffer for printing information from 11894 * /proc/scsi/advansys/[0...]. 11895 */ 11896 boardp->prtbuf = kmalloc(ASC_PRTBUF_SIZE, GFP_KERNEL); 11897 if (!boardp->prtbuf) { 11898 shost_printk(KERN_ERR, shost, "kmalloc(%d) returned NULL\n", 11899 ASC_PRTBUF_SIZE); 11900 ret = -ENOMEM; 11901 goto err_unmap; 11902 } 11903#endif /* CONFIG_PROC_FS */ 11904 11905 if (ASC_NARROW_BOARD(boardp)) { 11906 /* 11907 * Set the board bus type and PCI IRQ before 11908 * calling AscInitGetConfig(). 11909 */ 11910 switch (asc_dvc_varp->bus_type) { 11911#ifdef CONFIG_ISA 11912 case ASC_IS_ISA: 11913 shost->unchecked_isa_dma = TRUE; 11914 share_irq = 0; 11915 break; 11916 case ASC_IS_VL: 11917 shost->unchecked_isa_dma = FALSE; 11918 share_irq = 0; 11919 break; 11920 case ASC_IS_EISA: 11921 shost->unchecked_isa_dma = FALSE; 11922 share_irq = IRQF_SHARED; 11923 break; 11924#endif /* CONFIG_ISA */ 11925#ifdef CONFIG_PCI 11926 case ASC_IS_PCI: 11927 shost->unchecked_isa_dma = FALSE; 11928 share_irq = IRQF_SHARED; 11929 break; 11930#endif /* CONFIG_PCI */ 11931 default: 11932 shost_printk(KERN_ERR, shost, "unknown adapter type: " 11933 "%d\n", asc_dvc_varp->bus_type); 11934 shost->unchecked_isa_dma = TRUE; 11935 share_irq = 0; 11936 break; 11937 } 11938 11939 /* 11940 * NOTE: AscInitGetConfig() may change the board's 11941 * bus_type value. The bus_type value should no 11942 * longer be used. If the bus_type field must be 11943 * referenced only use the bit-wise AND operator "&". 11944 */ 11945 ASC_DBG(2, "AscInitGetConfig()\n"); 11946 ret = AscInitGetConfig(shost) ? -ENODEV : 0; 11947 } else { 11948#ifdef CONFIG_PCI 11949 /* 11950 * For Wide boards set PCI information before calling 11951 * AdvInitGetConfig(). 11952 */ 11953 shost->unchecked_isa_dma = FALSE; 11954 share_irq = IRQF_SHARED; 11955 ASC_DBG(2, "AdvInitGetConfig()\n"); 11956 11957 ret = AdvInitGetConfig(pdev, shost) ? -ENODEV : 0; 11958#endif /* CONFIG_PCI */ 11959 } 11960 11961 if (ret) 11962 goto err_free_proc; 11963 11964 /* 11965 * Save the EEPROM configuration so that it can be displayed 11966 * from /proc/scsi/advansys/[0...]. 11967 */ 11968 if (ASC_NARROW_BOARD(boardp)) { 11969 11970 ASCEEP_CONFIG *ep; 11971 11972 /* 11973 * Set the adapter's target id bit in the 'init_tidmask' field. 11974 */ 11975 boardp->init_tidmask |= 11976 ADV_TID_TO_TIDMASK(asc_dvc_varp->cfg->chip_scsi_id); 11977 11978 /* 11979 * Save EEPROM settings for the board. 11980 */ 11981 ep = &boardp->eep_config.asc_eep; 11982 11983 ep->init_sdtr = asc_dvc_varp->cfg->sdtr_enable; 11984 ep->disc_enable = asc_dvc_varp->cfg->disc_enable; 11985 ep->use_cmd_qng = asc_dvc_varp->cfg->cmd_qng_enabled; 11986 ASC_EEP_SET_DMA_SPD(ep, asc_dvc_varp->cfg->isa_dma_speed); 11987 ep->start_motor = asc_dvc_varp->start_motor; 11988 ep->cntl = asc_dvc_varp->dvc_cntl; 11989 ep->no_scam = asc_dvc_varp->no_scam; 11990 ep->max_total_qng = asc_dvc_varp->max_total_qng; 11991 ASC_EEP_SET_CHIP_ID(ep, asc_dvc_varp->cfg->chip_scsi_id); 11992 /* 'max_tag_qng' is set to the same value for every device. */ 11993 ep->max_tag_qng = asc_dvc_varp->cfg->max_tag_qng[0]; 11994 ep->adapter_info[0] = asc_dvc_varp->cfg->adapter_info[0]; 11995 ep->adapter_info[1] = asc_dvc_varp->cfg->adapter_info[1]; 11996 ep->adapter_info[2] = asc_dvc_varp->cfg->adapter_info[2]; 11997 ep->adapter_info[3] = asc_dvc_varp->cfg->adapter_info[3]; 11998 ep->adapter_info[4] = asc_dvc_varp->cfg->adapter_info[4]; 11999 ep->adapter_info[5] = asc_dvc_varp->cfg->adapter_info[5]; 12000 12001 /* 12002 * Modify board configuration. 12003 */ 12004 ASC_DBG(2, "AscInitSetConfig()\n"); 12005 ret = AscInitSetConfig(pdev, shost) ? -ENODEV : 0; 12006 if (ret) 12007 goto err_free_proc; 12008 } else { 12009 ADVEEP_3550_CONFIG *ep_3550; 12010 ADVEEP_38C0800_CONFIG *ep_38C0800; 12011 ADVEEP_38C1600_CONFIG *ep_38C1600; 12012 12013 /* 12014 * Save Wide EEP Configuration Information. 12015 */ 12016 if (adv_dvc_varp->chip_type == ADV_CHIP_ASC3550) { 12017 ep_3550 = &boardp->eep_config.adv_3550_eep; 12018 12019 ep_3550->adapter_scsi_id = adv_dvc_varp->chip_scsi_id; 12020 ep_3550->max_host_qng = adv_dvc_varp->max_host_qng; 12021 ep_3550->max_dvc_qng = adv_dvc_varp->max_dvc_qng; 12022 ep_3550->termination = adv_dvc_varp->cfg->termination; 12023 ep_3550->disc_enable = adv_dvc_varp->cfg->disc_enable; 12024 ep_3550->bios_ctrl = adv_dvc_varp->bios_ctrl; 12025 ep_3550->wdtr_able = adv_dvc_varp->wdtr_able; 12026 ep_3550->sdtr_able = adv_dvc_varp->sdtr_able; 12027 ep_3550->ultra_able = adv_dvc_varp->ultra_able; 12028 ep_3550->tagqng_able = adv_dvc_varp->tagqng_able; 12029 ep_3550->start_motor = adv_dvc_varp->start_motor; 12030 ep_3550->scsi_reset_delay = 12031 adv_dvc_varp->scsi_reset_wait; 12032 ep_3550->serial_number_word1 = 12033 adv_dvc_varp->cfg->serial1; 12034 ep_3550->serial_number_word2 = 12035 adv_dvc_varp->cfg->serial2; 12036 ep_3550->serial_number_word3 = 12037 adv_dvc_varp->cfg->serial3; 12038 } else if (adv_dvc_varp->chip_type == ADV_CHIP_ASC38C0800) { 12039 ep_38C0800 = &boardp->eep_config.adv_38C0800_eep; 12040 12041 ep_38C0800->adapter_scsi_id = 12042 adv_dvc_varp->chip_scsi_id; 12043 ep_38C0800->max_host_qng = adv_dvc_varp->max_host_qng; 12044 ep_38C0800->max_dvc_qng = adv_dvc_varp->max_dvc_qng; 12045 ep_38C0800->termination_lvd = 12046 adv_dvc_varp->cfg->termination; 12047 ep_38C0800->disc_enable = 12048 adv_dvc_varp->cfg->disc_enable; 12049 ep_38C0800->bios_ctrl = adv_dvc_varp->bios_ctrl; 12050 ep_38C0800->wdtr_able = adv_dvc_varp->wdtr_able; 12051 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able; 12052 ep_38C0800->sdtr_speed1 = adv_dvc_varp->sdtr_speed1; 12053 ep_38C0800->sdtr_speed2 = adv_dvc_varp->sdtr_speed2; 12054 ep_38C0800->sdtr_speed3 = adv_dvc_varp->sdtr_speed3; 12055 ep_38C0800->sdtr_speed4 = adv_dvc_varp->sdtr_speed4; 12056 ep_38C0800->tagqng_able = adv_dvc_varp->tagqng_able; 12057 ep_38C0800->start_motor = adv_dvc_varp->start_motor; 12058 ep_38C0800->scsi_reset_delay = 12059 adv_dvc_varp->scsi_reset_wait; 12060 ep_38C0800->serial_number_word1 = 12061 adv_dvc_varp->cfg->serial1; 12062 ep_38C0800->serial_number_word2 = 12063 adv_dvc_varp->cfg->serial2; 12064 ep_38C0800->serial_number_word3 = 12065 adv_dvc_varp->cfg->serial3; 12066 } else { 12067 ep_38C1600 = &boardp->eep_config.adv_38C1600_eep; 12068 12069 ep_38C1600->adapter_scsi_id = 12070 adv_dvc_varp->chip_scsi_id; 12071 ep_38C1600->max_host_qng = adv_dvc_varp->max_host_qng; 12072 ep_38C1600->max_dvc_qng = adv_dvc_varp->max_dvc_qng; 12073 ep_38C1600->termination_lvd = 12074 adv_dvc_varp->cfg->termination; 12075 ep_38C1600->disc_enable = 12076 adv_dvc_varp->cfg->disc_enable; 12077 ep_38C1600->bios_ctrl = adv_dvc_varp->bios_ctrl; 12078 ep_38C1600->wdtr_able = adv_dvc_varp->wdtr_able; 12079 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able; 12080 ep_38C1600->sdtr_speed1 = adv_dvc_varp->sdtr_speed1; 12081 ep_38C1600->sdtr_speed2 = adv_dvc_varp->sdtr_speed2; 12082 ep_38C1600->sdtr_speed3 = adv_dvc_varp->sdtr_speed3; 12083 ep_38C1600->sdtr_speed4 = adv_dvc_varp->sdtr_speed4; 12084 ep_38C1600->tagqng_able = adv_dvc_varp->tagqng_able; 12085 ep_38C1600->start_motor = adv_dvc_varp->start_motor; 12086 ep_38C1600->scsi_reset_delay = 12087 adv_dvc_varp->scsi_reset_wait; 12088 ep_38C1600->serial_number_word1 = 12089 adv_dvc_varp->cfg->serial1; 12090 ep_38C1600->serial_number_word2 = 12091 adv_dvc_varp->cfg->serial2; 12092 ep_38C1600->serial_number_word3 = 12093 adv_dvc_varp->cfg->serial3; 12094 } 12095 12096 /* 12097 * Set the adapter's target id bit in the 'init_tidmask' field. 12098 */ 12099 boardp->init_tidmask |= 12100 ADV_TID_TO_TIDMASK(adv_dvc_varp->chip_scsi_id); 12101 } 12102 12103 /* 12104 * Channels are numbered beginning with 0. For AdvanSys one host 12105 * structure supports one channel. Multi-channel boards have a 12106 * separate host structure for each channel. 12107 */ 12108 shost->max_channel = 0; 12109 if (ASC_NARROW_BOARD(boardp)) { 12110 shost->max_id = ASC_MAX_TID + 1; 12111 shost->max_lun = ASC_MAX_LUN + 1; 12112 shost->max_cmd_len = ASC_MAX_CDB_LEN; 12113 12114 shost->io_port = asc_dvc_varp->iop_base; 12115 boardp->asc_n_io_port = ASC_IOADR_GAP; 12116 shost->this_id = asc_dvc_varp->cfg->chip_scsi_id; 12117 12118 /* Set maximum number of queues the adapter can handle. */ 12119 shost->can_queue = asc_dvc_varp->max_total_qng; 12120 } else { 12121 shost->max_id = ADV_MAX_TID + 1; 12122 shost->max_lun = ADV_MAX_LUN + 1; 12123 shost->max_cmd_len = ADV_MAX_CDB_LEN; 12124 12125 /* 12126 * Save the I/O Port address and length even though 12127 * I/O ports are not used to access Wide boards. 12128 * Instead the Wide boards are accessed with 12129 * PCI Memory Mapped I/O. 12130 */ 12131 shost->io_port = iop; 12132 12133 shost->this_id = adv_dvc_varp->chip_scsi_id; 12134 12135 /* Set maximum number of queues the adapter can handle. */ 12136 shost->can_queue = adv_dvc_varp->max_host_qng; 12137 } 12138 12139 /* 12140 * Following v1.3.89, 'cmd_per_lun' is no longer needed 12141 * and should be set to zero. 12142 * 12143 * But because of a bug introduced in v1.3.89 if the driver is 12144 * compiled as a module and 'cmd_per_lun' is zero, the Mid-Level 12145 * SCSI function 'allocate_device' will panic. To allow the driver 12146 * to work as a module in these kernels set 'cmd_per_lun' to 1. 12147 * 12148 * Note: This is wrong. cmd_per_lun should be set to the depth 12149 * you want on untagged devices always. 12150 #ifdef MODULE 12151 */ 12152 shost->cmd_per_lun = 1; 12153/* #else 12154 shost->cmd_per_lun = 0; 12155#endif */ 12156 12157 /* 12158 * Set the maximum number of scatter-gather elements the 12159 * adapter can handle. 12160 */ 12161 if (ASC_NARROW_BOARD(boardp)) { 12162 /* 12163 * Allow two commands with 'sg_tablesize' scatter-gather 12164 * elements to be executed simultaneously. This value is 12165 * the theoretical hardware limit. It may be decreased 12166 * below. 12167 */ 12168 shost->sg_tablesize = 12169 (((asc_dvc_varp->max_total_qng - 2) / 2) * 12170 ASC_SG_LIST_PER_Q) + 1; 12171 } else { 12172 shost->sg_tablesize = ADV_MAX_SG_LIST; 12173 } 12174 12175 /* 12176 * The value of 'sg_tablesize' can not exceed the SCSI 12177 * mid-level driver definition of SG_ALL. SG_ALL also 12178 * must not be exceeded, because it is used to define the 12179 * size of the scatter-gather table in 'struct asc_sg_head'. 12180 */ 12181 if (shost->sg_tablesize > SG_ALL) { 12182 shost->sg_tablesize = SG_ALL; 12183 } 12184 12185 ASC_DBG(1, "sg_tablesize: %d\n", shost->sg_tablesize); 12186 12187 /* BIOS start address. */ 12188 if (ASC_NARROW_BOARD(boardp)) { 12189 shost->base = AscGetChipBiosAddress(asc_dvc_varp->iop_base, 12190 asc_dvc_varp->bus_type); 12191 } else { 12192 /* 12193 * Fill-in BIOS board variables. The Wide BIOS saves 12194 * information in LRAM that is used by the driver. 12195 */ 12196 AdvReadWordLram(adv_dvc_varp->iop_base, 12197 BIOS_SIGNATURE, boardp->bios_signature); 12198 AdvReadWordLram(adv_dvc_varp->iop_base, 12199 BIOS_VERSION, boardp->bios_version); 12200 AdvReadWordLram(adv_dvc_varp->iop_base, 12201 BIOS_CODESEG, boardp->bios_codeseg); 12202 AdvReadWordLram(adv_dvc_varp->iop_base, 12203 BIOS_CODELEN, boardp->bios_codelen); 12204 12205 ASC_DBG(1, "bios_signature 0x%x, bios_version 0x%x\n", 12206 boardp->bios_signature, boardp->bios_version); 12207 12208 ASC_DBG(1, "bios_codeseg 0x%x, bios_codelen 0x%x\n", 12209 boardp->bios_codeseg, boardp->bios_codelen); 12210 12211 /* 12212 * If the BIOS saved a valid signature, then fill in 12213 * the BIOS code segment base address. 12214 */ 12215 if (boardp->bios_signature == 0x55AA) { 12216 /* 12217 * Convert x86 realmode code segment to a linear 12218 * address by shifting left 4. 12219 */ 12220 shost->base = ((ulong)boardp->bios_codeseg << 4); 12221 } else { 12222 shost->base = 0; 12223 } 12224 } 12225 12226 /* 12227 * Register Board Resources - I/O Port, DMA, IRQ 12228 */ 12229 12230 /* Register DMA Channel for Narrow boards. */ 12231 shost->dma_channel = NO_ISA_DMA; /* Default to no ISA DMA. */ 12232#ifdef CONFIG_ISA 12233 if (ASC_NARROW_BOARD(boardp)) { 12234 /* Register DMA channel for ISA bus. */ 12235 if (asc_dvc_varp->bus_type & ASC_IS_ISA) { 12236 shost->dma_channel = asc_dvc_varp->cfg->isa_dma_channel; 12237 ret = request_dma(shost->dma_channel, DRV_NAME); 12238 if (ret) { 12239 shost_printk(KERN_ERR, shost, "request_dma() " 12240 "%d failed %d\n", 12241 shost->dma_channel, ret); 12242 goto err_free_proc; 12243 } 12244 AscEnableIsaDma(shost->dma_channel); 12245 } 12246 } 12247#endif /* CONFIG_ISA */ 12248 12249 /* Register IRQ Number. */ 12250 ASC_DBG(2, "request_irq(%d, %p)\n", boardp->irq, shost); 12251 12252 ret = request_irq(boardp->irq, advansys_interrupt, share_irq, 12253 DRV_NAME, shost); 12254 12255 if (ret) { 12256 if (ret == -EBUSY) { 12257 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x " 12258 "already in use\n", boardp->irq); 12259 } else if (ret == -EINVAL) { 12260 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x " 12261 "not valid\n", boardp->irq); 12262 } else { 12263 shost_printk(KERN_ERR, shost, "request_irq(): IRQ 0x%x " 12264 "failed with %d\n", boardp->irq, ret); 12265 } 12266 goto err_free_dma; 12267 } 12268 12269 /* 12270 * Initialize board RISC chip and enable interrupts. 12271 */ 12272 if (ASC_NARROW_BOARD(boardp)) { 12273 ASC_DBG(2, "AscInitAsc1000Driver()\n"); 12274 12275 asc_dvc_varp->overrun_buf = kzalloc(ASC_OVERRUN_BSIZE, GFP_KERNEL); 12276 if (!asc_dvc_varp->overrun_buf) { 12277 ret = -ENOMEM; 12278 goto err_free_irq; 12279 } 12280 warn_code = AscInitAsc1000Driver(asc_dvc_varp); 12281 12282 if (warn_code || asc_dvc_varp->err_code) { 12283 shost_printk(KERN_ERR, shost, "error: init_state 0x%x, " 12284 "warn 0x%x, error 0x%x\n", 12285 asc_dvc_varp->init_state, warn_code, 12286 asc_dvc_varp->err_code); 12287 if (!asc_dvc_varp->overrun_dma) { 12288 ret = -ENODEV; 12289 goto err_free_mem; 12290 } 12291 } 12292 } else { 12293 if (advansys_wide_init_chip(shost)) { 12294 ret = -ENODEV; 12295 goto err_free_mem; 12296 } 12297 } 12298 12299 ASC_DBG_PRT_SCSI_HOST(2, shost); 12300 12301 ret = scsi_add_host(shost, boardp->dev); 12302 if (ret) 12303 goto err_free_mem; 12304 12305 scsi_scan_host(shost); 12306 return 0; 12307 12308 err_free_mem: 12309 if (ASC_NARROW_BOARD(boardp)) { 12310 if (asc_dvc_varp->overrun_dma) 12311 dma_unmap_single(boardp->dev, asc_dvc_varp->overrun_dma, 12312 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 12313 kfree(asc_dvc_varp->overrun_buf); 12314 } else 12315 advansys_wide_free_mem(boardp); 12316 err_free_irq: 12317 free_irq(boardp->irq, shost); 12318 err_free_dma: 12319#ifdef CONFIG_ISA 12320 if (shost->dma_channel != NO_ISA_DMA) 12321 free_dma(shost->dma_channel); 12322#endif 12323 err_free_proc: 12324 kfree(boardp->prtbuf); 12325 err_unmap: 12326 if (boardp->ioremap_addr) 12327 iounmap(boardp->ioremap_addr); 12328 err_shost: 12329 return ret; 12330} 12331 12332/* 12333 * advansys_release() 12334 * 12335 * Release resources allocated for a single AdvanSys adapter. 12336 */ 12337static int advansys_release(struct Scsi_Host *shost) 12338{ 12339 struct asc_board *board = shost_priv(shost); 12340 ASC_DBG(1, "begin\n"); 12341 scsi_remove_host(shost); 12342 free_irq(board->irq, shost); 12343#ifdef CONFIG_ISA 12344 if (shost->dma_channel != NO_ISA_DMA) { 12345 ASC_DBG(1, "free_dma()\n"); 12346 free_dma(shost->dma_channel); 12347 } 12348#endif 12349 if (ASC_NARROW_BOARD(board)) { 12350 dma_unmap_single(board->dev, 12351 board->dvc_var.asc_dvc_var.overrun_dma, 12352 ASC_OVERRUN_BSIZE, DMA_FROM_DEVICE); 12353 kfree(board->dvc_var.asc_dvc_var.overrun_buf); 12354 } else { 12355 iounmap(board->ioremap_addr); 12356 advansys_wide_free_mem(board); 12357 } 12358 kfree(board->prtbuf); 12359 scsi_host_put(shost); 12360 ASC_DBG(1, "end\n"); 12361 return 0; 12362} 12363 12364#define ASC_IOADR_TABLE_MAX_IX 11 12365 12366static PortAddr _asc_def_iop_base[ASC_IOADR_TABLE_MAX_IX] = { 12367 0x100, 0x0110, 0x120, 0x0130, 0x140, 0x0150, 0x0190, 12368 0x0210, 0x0230, 0x0250, 0x0330 12369}; 12370 12371/* 12372 * The ISA IRQ number is found in bits 2 and 3 of the CfgLsw. It decodes as: 12373 * 00: 10 12374 * 01: 11 12375 * 10: 12 12376 * 11: 15 12377 */ 12378static unsigned int __devinit advansys_isa_irq_no(PortAddr iop_base) 12379{ 12380 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base); 12381 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x03) + 10; 12382 if (chip_irq == 13) 12383 chip_irq = 15; 12384 return chip_irq; 12385} 12386 12387static int __devinit advansys_isa_probe(struct device *dev, unsigned int id) 12388{ 12389 int err = -ENODEV; 12390 PortAddr iop_base = _asc_def_iop_base[id]; 12391 struct Scsi_Host *shost; 12392 struct asc_board *board; 12393 12394 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) { 12395 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base); 12396 return -ENODEV; 12397 } 12398 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base); 12399 if (!AscFindSignature(iop_base)) 12400 goto release_region; 12401 if (!(AscGetChipVersion(iop_base, ASC_IS_ISA) & ASC_CHIP_VER_ISA_BIT)) 12402 goto release_region; 12403 12404 err = -ENOMEM; 12405 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 12406 if (!shost) 12407 goto release_region; 12408 12409 board = shost_priv(shost); 12410 board->irq = advansys_isa_irq_no(iop_base); 12411 board->dev = dev; 12412 12413 err = advansys_board_found(shost, iop_base, ASC_IS_ISA); 12414 if (err) 12415 goto free_host; 12416 12417 dev_set_drvdata(dev, shost); 12418 return 0; 12419 12420 free_host: 12421 scsi_host_put(shost); 12422 release_region: 12423 release_region(iop_base, ASC_IOADR_GAP); 12424 return err; 12425} 12426 12427static int __devexit advansys_isa_remove(struct device *dev, unsigned int id) 12428{ 12429 int ioport = _asc_def_iop_base[id]; 12430 advansys_release(dev_get_drvdata(dev)); 12431 release_region(ioport, ASC_IOADR_GAP); 12432 return 0; 12433} 12434 12435static struct isa_driver advansys_isa_driver = { 12436 .probe = advansys_isa_probe, 12437 .remove = __devexit_p(advansys_isa_remove), 12438 .driver = { 12439 .owner = THIS_MODULE, 12440 .name = DRV_NAME, 12441 }, 12442}; 12443 12444/* 12445 * The VLB IRQ number is found in bits 2 to 4 of the CfgLsw. It decodes as: 12446 * 000: invalid 12447 * 001: 10 12448 * 010: 11 12449 * 011: 12 12450 * 100: invalid 12451 * 101: 14 12452 * 110: 15 12453 * 111: invalid 12454 */ 12455static unsigned int __devinit advansys_vlb_irq_no(PortAddr iop_base) 12456{ 12457 unsigned short cfg_lsw = AscGetChipCfgLsw(iop_base); 12458 unsigned int chip_irq = ((cfg_lsw >> 2) & 0x07) + 9; 12459 if ((chip_irq < 10) || (chip_irq == 13) || (chip_irq > 15)) 12460 return 0; 12461 return chip_irq; 12462} 12463 12464static int __devinit advansys_vlb_probe(struct device *dev, unsigned int id) 12465{ 12466 int err = -ENODEV; 12467 PortAddr iop_base = _asc_def_iop_base[id]; 12468 struct Scsi_Host *shost; 12469 struct asc_board *board; 12470 12471 if (!request_region(iop_base, ASC_IOADR_GAP, DRV_NAME)) { 12472 ASC_DBG(1, "I/O port 0x%x busy\n", iop_base); 12473 return -ENODEV; 12474 } 12475 ASC_DBG(1, "probing I/O port 0x%x\n", iop_base); 12476 if (!AscFindSignature(iop_base)) 12477 goto release_region; 12478 /* 12479 * I don't think this condition can actually happen, but the old 12480 * driver did it, and the chances of finding a VLB setup in 2007 12481 * to do testing with is slight to none. 12482 */ 12483 if (AscGetChipVersion(iop_base, ASC_IS_VL) > ASC_CHIP_MAX_VER_VL) 12484 goto release_region; 12485 12486 err = -ENOMEM; 12487 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 12488 if (!shost) 12489 goto release_region; 12490 12491 board = shost_priv(shost); 12492 board->irq = advansys_vlb_irq_no(iop_base); 12493 board->dev = dev; 12494 12495 err = advansys_board_found(shost, iop_base, ASC_IS_VL); 12496 if (err) 12497 goto free_host; 12498 12499 dev_set_drvdata(dev, shost); 12500 return 0; 12501 12502 free_host: 12503 scsi_host_put(shost); 12504 release_region: 12505 release_region(iop_base, ASC_IOADR_GAP); 12506 return -ENODEV; 12507} 12508 12509static struct isa_driver advansys_vlb_driver = { 12510 .probe = advansys_vlb_probe, 12511 .remove = __devexit_p(advansys_isa_remove), 12512 .driver = { 12513 .owner = THIS_MODULE, 12514 .name = "advansys_vlb", 12515 }, 12516}; 12517 12518static struct eisa_device_id advansys_eisa_table[] __devinitdata = { 12519 { "ABP7401" }, 12520 { "ABP7501" }, 12521 { "" } 12522}; 12523 12524MODULE_DEVICE_TABLE(eisa, advansys_eisa_table); 12525 12526/* 12527 * EISA is a little more tricky than PCI; each EISA device may have two 12528 * channels, and this driver is written to make each channel its own Scsi_Host 12529 */ 12530struct eisa_scsi_data { 12531 struct Scsi_Host *host[2]; 12532}; 12533 12534/* 12535 * The EISA IRQ number is found in bits 8 to 10 of the CfgLsw. It decodes as: 12536 * 000: 10 12537 * 001: 11 12538 * 010: 12 12539 * 011: invalid 12540 * 100: 14 12541 * 101: 15 12542 * 110: invalid 12543 * 111: invalid 12544 */ 12545static unsigned int __devinit advansys_eisa_irq_no(struct eisa_device *edev) 12546{ 12547 unsigned short cfg_lsw = inw(edev->base_addr + 0xc86); 12548 unsigned int chip_irq = ((cfg_lsw >> 8) & 0x07) + 10; 12549 if ((chip_irq == 13) || (chip_irq > 15)) 12550 return 0; 12551 return chip_irq; 12552} 12553 12554static int __devinit advansys_eisa_probe(struct device *dev) 12555{ 12556 int i, ioport, irq = 0; 12557 int err; 12558 struct eisa_device *edev = to_eisa_device(dev); 12559 struct eisa_scsi_data *data; 12560 12561 err = -ENOMEM; 12562 data = kzalloc(sizeof(*data), GFP_KERNEL); 12563 if (!data) 12564 goto fail; 12565 ioport = edev->base_addr + 0xc30; 12566 12567 err = -ENODEV; 12568 for (i = 0; i < 2; i++, ioport += 0x20) { 12569 struct asc_board *board; 12570 struct Scsi_Host *shost; 12571 if (!request_region(ioport, ASC_IOADR_GAP, DRV_NAME)) { 12572 printk(KERN_WARNING "Region %x-%x busy\n", ioport, 12573 ioport + ASC_IOADR_GAP - 1); 12574 continue; 12575 } 12576 if (!AscFindSignature(ioport)) { 12577 release_region(ioport, ASC_IOADR_GAP); 12578 continue; 12579 } 12580 12581 /* 12582 * I don't know why we need to do this for EISA chips, but 12583 * not for any others. It looks to be equivalent to 12584 * AscGetChipCfgMsw, but I may have overlooked something, 12585 * so I'm not converting it until I get an EISA board to 12586 * test with. 12587 */ 12588 inw(ioport + 4); 12589 12590 if (!irq) 12591 irq = advansys_eisa_irq_no(edev); 12592 12593 err = -ENOMEM; 12594 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 12595 if (!shost) 12596 goto release_region; 12597 12598 board = shost_priv(shost); 12599 board->irq = irq; 12600 board->dev = dev; 12601 12602 err = advansys_board_found(shost, ioport, ASC_IS_EISA); 12603 if (!err) { 12604 data->host[i] = shost; 12605 continue; 12606 } 12607 12608 scsi_host_put(shost); 12609 release_region: 12610 release_region(ioport, ASC_IOADR_GAP); 12611 break; 12612 } 12613 12614 if (err) 12615 goto free_data; 12616 dev_set_drvdata(dev, data); 12617 return 0; 12618 12619 free_data: 12620 kfree(data->host[0]); 12621 kfree(data->host[1]); 12622 kfree(data); 12623 fail: 12624 return err; 12625} 12626 12627static __devexit int advansys_eisa_remove(struct device *dev) 12628{ 12629 int i; 12630 struct eisa_scsi_data *data = dev_get_drvdata(dev); 12631 12632 for (i = 0; i < 2; i++) { 12633 int ioport; 12634 struct Scsi_Host *shost = data->host[i]; 12635 if (!shost) 12636 continue; 12637 ioport = shost->io_port; 12638 advansys_release(shost); 12639 release_region(ioport, ASC_IOADR_GAP); 12640 } 12641 12642 kfree(data); 12643 return 0; 12644} 12645 12646static struct eisa_driver advansys_eisa_driver = { 12647 .id_table = advansys_eisa_table, 12648 .driver = { 12649 .name = DRV_NAME, 12650 .probe = advansys_eisa_probe, 12651 .remove = __devexit_p(advansys_eisa_remove), 12652 } 12653}; 12654 12655/* PCI Devices supported by this driver */ 12656static struct pci_device_id advansys_pci_tbl[] __devinitdata = { 12657 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_1200A, 12658 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 12659 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940, 12660 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 12661 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940U, 12662 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 12663 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_ASP_ABP940UW, 12664 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 12665 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C0800_REV1, 12666 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 12667 {PCI_VENDOR_ID_ASP, PCI_DEVICE_ID_38C1600_REV1, 12668 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0}, 12669 {} 12670}; 12671 12672MODULE_DEVICE_TABLE(pci, advansys_pci_tbl); 12673 12674static void __devinit advansys_set_latency(struct pci_dev *pdev) 12675{ 12676 if ((pdev->device == PCI_DEVICE_ID_ASP_1200A) || 12677 (pdev->device == PCI_DEVICE_ID_ASP_ABP940)) { 12678 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0); 12679 } else { 12680 u8 latency; 12681 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &latency); 12682 if (latency < 0x20) 12683 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x20); 12684 } 12685} 12686 12687static int __devinit 12688advansys_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 12689{ 12690 int err, ioport; 12691 struct Scsi_Host *shost; 12692 struct asc_board *board; 12693 12694 err = pci_enable_device(pdev); 12695 if (err) 12696 goto fail; 12697 err = pci_request_regions(pdev, DRV_NAME); 12698 if (err) 12699 goto disable_device; 12700 pci_set_master(pdev); 12701 advansys_set_latency(pdev); 12702 12703 err = -ENODEV; 12704 if (pci_resource_len(pdev, 0) == 0) 12705 goto release_region; 12706 12707 ioport = pci_resource_start(pdev, 0); 12708 12709 err = -ENOMEM; 12710 shost = scsi_host_alloc(&advansys_template, sizeof(*board)); 12711 if (!shost) 12712 goto release_region; 12713 12714 board = shost_priv(shost); 12715 board->irq = pdev->irq; 12716 board->dev = &pdev->dev; 12717 12718 if (pdev->device == PCI_DEVICE_ID_ASP_ABP940UW || 12719 pdev->device == PCI_DEVICE_ID_38C0800_REV1 || 12720 pdev->device == PCI_DEVICE_ID_38C1600_REV1) { 12721 board->flags |= ASC_IS_WIDE_BOARD; 12722 } 12723 12724 err = advansys_board_found(shost, ioport, ASC_IS_PCI); 12725 if (err) 12726 goto free_host; 12727 12728 pci_set_drvdata(pdev, shost); 12729 return 0; 12730 12731 free_host: 12732 scsi_host_put(shost); 12733 release_region: 12734 pci_release_regions(pdev); 12735 disable_device: 12736 pci_disable_device(pdev); 12737 fail: 12738 return err; 12739} 12740 12741static void __devexit advansys_pci_remove(struct pci_dev *pdev) 12742{ 12743 advansys_release(pci_get_drvdata(pdev)); 12744 pci_release_regions(pdev); 12745 pci_disable_device(pdev); 12746} 12747 12748static struct pci_driver advansys_pci_driver = { 12749 .name = DRV_NAME, 12750 .id_table = advansys_pci_tbl, 12751 .probe = advansys_pci_probe, 12752 .remove = __devexit_p(advansys_pci_remove), 12753}; 12754 12755static int __init advansys_init(void) 12756{ 12757 int error; 12758 12759 error = isa_register_driver(&advansys_isa_driver, 12760 ASC_IOADR_TABLE_MAX_IX); 12761 if (error) 12762 goto fail; 12763 12764 error = isa_register_driver(&advansys_vlb_driver, 12765 ASC_IOADR_TABLE_MAX_IX); 12766 if (error) 12767 goto unregister_isa; 12768 12769 error = eisa_driver_register(&advansys_eisa_driver); 12770 if (error) 12771 goto unregister_vlb; 12772 12773 error = pci_register_driver(&advansys_pci_driver); 12774 if (error) 12775 goto unregister_eisa; 12776 12777 return 0; 12778 12779 unregister_eisa: 12780 eisa_driver_unregister(&advansys_eisa_driver); 12781 unregister_vlb: 12782 isa_unregister_driver(&advansys_vlb_driver); 12783 unregister_isa: 12784 isa_unregister_driver(&advansys_isa_driver); 12785 fail: 12786 return error; 12787} 12788 12789static void __exit advansys_exit(void) 12790{ 12791 pci_unregister_driver(&advansys_pci_driver); 12792 eisa_driver_unregister(&advansys_eisa_driver); 12793 isa_unregister_driver(&advansys_vlb_driver); 12794 isa_unregister_driver(&advansys_isa_driver); 12795} 12796 12797module_init(advansys_init); 12798module_exit(advansys_exit); 12799 12800MODULE_LICENSE("GPL"); 12801MODULE_FIRMWARE("advansys/mcode.bin"); 12802MODULE_FIRMWARE("advansys/3550.bin"); 12803MODULE_FIRMWARE("advansys/38C0800.bin"); 12804MODULE_FIRMWARE("advansys/38C1600.bin"); 12805