1/****************************************************************************** 2 * 3 * GPL LICENSE SUMMARY 4 * 5 * Copyright(c) 2008 - 2010 Intel Corporation. All rights reserved. 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of version 2 of the GNU General Public License as 9 * published by the Free Software Foundation. 10 * 11 * This program is distributed in the hope that it will be useful, but 12 * WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * General Public License for more details. 15 * 16 * You should have received a copy of the GNU General Public License 17 * along with this program; if not, write to the Free Software 18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110, 19 * USA 20 * 21 * The full GNU General Public License is included in this distribution 22 * in the file called LICENSE.GPL. 23 * 24 * Contact Information: 25 * Intel Linux Wireless <ilw@linux.intel.com> 26 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 27 * 28 *****************************************************************************/ 29#include <linux/etherdevice.h> 30#include <linux/kernel.h> 31#include <linux/module.h> 32#include <linux/init.h> 33#include <linux/sched.h> 34 35#include "iwl-dev.h" 36#include "iwl-core.h" 37#include "iwl-io.h" 38#include "iwl-helpers.h" 39#include "iwl-agn-hw.h" 40#include "iwl-agn.h" 41#include "iwl-sta.h" 42 43static inline u32 iwlagn_get_scd_ssn(struct iwl5000_tx_resp *tx_resp) 44{ 45 return le32_to_cpup((__le32 *)&tx_resp->status + 46 tx_resp->frame_count) & MAX_SN; 47} 48 49static int iwlagn_tx_status_reply_tx(struct iwl_priv *priv, 50 struct iwl_ht_agg *agg, 51 struct iwl5000_tx_resp *tx_resp, 52 int txq_id, u16 start_idx) 53{ 54 u16 status; 55 struct agg_tx_status *frame_status = &tx_resp->status; 56 struct ieee80211_tx_info *info = NULL; 57 struct ieee80211_hdr *hdr = NULL; 58 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); 59 int i, sh, idx; 60 u16 seq; 61 62 if (agg->wait_for_ba) 63 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n"); 64 65 agg->frame_count = tx_resp->frame_count; 66 agg->start_idx = start_idx; 67 agg->rate_n_flags = rate_n_flags; 68 agg->bitmap = 0; 69 70 /* # frames attempted by Tx command */ 71 if (agg->frame_count == 1) { 72 /* Only one frame was attempted; no block-ack will arrive */ 73 status = le16_to_cpu(frame_status[0].status); 74 idx = start_idx; 75 76 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n", 77 agg->frame_count, agg->start_idx, idx); 78 79 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb); 80 info->status.rates[0].count = tx_resp->failure_frame + 1; 81 info->flags &= ~IEEE80211_TX_CTL_AMPDU; 82 info->flags |= iwl_tx_status_to_mac80211(status); 83 iwlagn_hwrate_to_tx_control(priv, rate_n_flags, info); 84 85 86 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n", 87 status & 0xff, tx_resp->failure_frame); 88 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags); 89 90 agg->wait_for_ba = 0; 91 } else { 92 /* Two or more frames were attempted; expect block-ack */ 93 u64 bitmap = 0; 94 95 /* 96 * Start is the lowest frame sent. It may not be the first 97 * frame in the batch; we figure this out dynamically during 98 * the following loop. 99 */ 100 int start = agg->start_idx; 101 102 /* Construct bit-map of pending frames within Tx window */ 103 for (i = 0; i < agg->frame_count; i++) { 104 u16 sc; 105 status = le16_to_cpu(frame_status[i].status); 106 seq = le16_to_cpu(frame_status[i].sequence); 107 idx = SEQ_TO_INDEX(seq); 108 txq_id = SEQ_TO_QUEUE(seq); 109 110 if (status & (AGG_TX_STATE_FEW_BYTES_MSK | 111 AGG_TX_STATE_ABORT_MSK)) 112 continue; 113 114 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n", 115 agg->frame_count, txq_id, idx); 116 117 hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx); 118 if (!hdr) { 119 IWL_ERR(priv, 120 "BUG_ON idx doesn't point to valid skb" 121 " idx=%d, txq_id=%d\n", idx, txq_id); 122 return -1; 123 } 124 125 sc = le16_to_cpu(hdr->seq_ctrl); 126 if (idx != (SEQ_TO_SN(sc) & 0xff)) { 127 IWL_ERR(priv, 128 "BUG_ON idx doesn't match seq control" 129 " idx=%d, seq_idx=%d, seq=%d\n", 130 idx, SEQ_TO_SN(sc), 131 hdr->seq_ctrl); 132 return -1; 133 } 134 135 IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n", 136 i, idx, SEQ_TO_SN(sc)); 137 138 /* 139 * sh -> how many frames ahead of the starting frame is 140 * the current one? 141 * 142 * Note that all frames sent in the batch must be in a 143 * 64-frame window, so this number should be in [0,63]. 144 * If outside of this window, then we've found a new 145 * "first" frame in the batch and need to change start. 146 */ 147 sh = idx - start; 148 149 /* 150 * If >= 64, out of window. start must be at the front 151 * of the circular buffer, idx must be near the end of 152 * the buffer, and idx is the new "first" frame. Shift 153 * the indices around. 154 */ 155 if (sh >= 64) { 156 /* Shift bitmap by start - idx, wrapped */ 157 sh = 0x100 - idx + start; 158 bitmap = bitmap << sh; 159 /* Now idx is the new start so sh = 0 */ 160 sh = 0; 161 start = idx; 162 /* 163 * If <= -64 then wraps the 256-pkt circular buffer 164 * (e.g., start = 255 and idx = 0, sh should be 1) 165 */ 166 } else if (sh <= -64) { 167 sh = 0x100 - start + idx; 168 /* 169 * If < 0 but > -64, out of window. idx is before start 170 * but not wrapped. Shift the indices around. 171 */ 172 } else if (sh < 0) { 173 /* Shift by how far start is ahead of idx */ 174 sh = start - idx; 175 bitmap = bitmap << sh; 176 /* Now idx is the new start so sh = 0 */ 177 start = idx; 178 sh = 0; 179 } 180 /* Sequence number start + sh was sent in this batch */ 181 bitmap |= 1ULL << sh; 182 IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n", 183 start, (unsigned long long)bitmap); 184 } 185 186 /* 187 * Store the bitmap and possibly the new start, if we wrapped 188 * the buffer above 189 */ 190 agg->bitmap = bitmap; 191 agg->start_idx = start; 192 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n", 193 agg->frame_count, agg->start_idx, 194 (unsigned long long)agg->bitmap); 195 196 if (bitmap) 197 agg->wait_for_ba = 1; 198 } 199 return 0; 200} 201 202void iwl_check_abort_status(struct iwl_priv *priv, 203 u8 frame_count, u32 status) 204{ 205 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) { 206 IWL_ERR(priv, "Tx flush command to flush out all frames\n"); 207 if (!test_bit(STATUS_EXIT_PENDING, &priv->status)) 208 queue_work(priv->workqueue, &priv->tx_flush); 209 } 210} 211 212static void iwlagn_rx_reply_tx(struct iwl_priv *priv, 213 struct iwl_rx_mem_buffer *rxb) 214{ 215 struct iwl_rx_packet *pkt = rxb_addr(rxb); 216 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 217 int txq_id = SEQ_TO_QUEUE(sequence); 218 int index = SEQ_TO_INDEX(sequence); 219 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 220 struct ieee80211_tx_info *info; 221 struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 222 u32 status = le16_to_cpu(tx_resp->status.status); 223 int tid; 224 int sta_id; 225 int freed; 226 unsigned long flags; 227 228 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { 229 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d " 230 "is out of range [0-%d] %d %d\n", txq_id, 231 index, txq->q.n_bd, txq->q.write_ptr, 232 txq->q.read_ptr); 233 return; 234 } 235 236 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb); 237 memset(&info->status, 0, sizeof(info->status)); 238 239 tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS; 240 sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS; 241 242 spin_lock_irqsave(&priv->sta_lock, flags); 243 if (txq->sched_retry) { 244 const u32 scd_ssn = iwlagn_get_scd_ssn(tx_resp); 245 struct iwl_ht_agg *agg; 246 247 agg = &priv->stations[sta_id].tid[tid].agg; 248 249 iwlagn_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index); 250 251 /* check if BAR is needed */ 252 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status)) 253 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 254 255 if (txq->q.read_ptr != (scd_ssn & 0xff)) { 256 index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); 257 IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim " 258 "scd_ssn=%d idx=%d txq=%d swq=%d\n", 259 scd_ssn , index, txq_id, txq->swq_id); 260 261 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index); 262 iwl_free_tfds_in_queue(priv, sta_id, tid, freed); 263 264 if (priv->mac80211_registered && 265 (iwl_queue_space(&txq->q) > txq->q.low_mark) && 266 (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) { 267 if (agg->state == IWL_AGG_OFF) 268 iwl_wake_queue(priv, txq_id); 269 else 270 iwl_wake_queue(priv, txq->swq_id); 271 } 272 } 273 } else { 274 BUG_ON(txq_id != txq->swq_id); 275 276 info->status.rates[0].count = tx_resp->failure_frame + 1; 277 info->flags |= iwl_tx_status_to_mac80211(status); 278 iwlagn_hwrate_to_tx_control(priv, 279 le32_to_cpu(tx_resp->rate_n_flags), 280 info); 281 282 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags " 283 "0x%x retries %d\n", 284 txq_id, 285 iwl_get_tx_fail_reason(status), status, 286 le32_to_cpu(tx_resp->rate_n_flags), 287 tx_resp->failure_frame); 288 289 freed = iwlagn_tx_queue_reclaim(priv, txq_id, index); 290 iwl_free_tfds_in_queue(priv, sta_id, tid, freed); 291 292 if (priv->mac80211_registered && 293 (iwl_queue_space(&txq->q) > txq->q.low_mark)) 294 iwl_wake_queue(priv, txq_id); 295 } 296 297 iwlagn_txq_check_empty(priv, sta_id, tid, txq_id); 298 299 iwl_check_abort_status(priv, tx_resp->frame_count, status); 300 spin_unlock_irqrestore(&priv->sta_lock, flags); 301} 302 303void iwlagn_rx_handler_setup(struct iwl_priv *priv) 304{ 305 /* init calibration handlers */ 306 priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] = 307 iwlagn_rx_calib_result; 308 priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] = 309 iwlagn_rx_calib_complete; 310 priv->rx_handlers[REPLY_TX] = iwlagn_rx_reply_tx; 311} 312 313void iwlagn_setup_deferred_work(struct iwl_priv *priv) 314{ 315 /* in agn, the tx power calibration is done in uCode */ 316 priv->disable_tx_power_cal = 1; 317} 318 319int iwlagn_hw_valid_rtc_data_addr(u32 addr) 320{ 321 return (addr >= IWLAGN_RTC_DATA_LOWER_BOUND) && 322 (addr < IWLAGN_RTC_DATA_UPPER_BOUND); 323} 324 325int iwlagn_send_tx_power(struct iwl_priv *priv) 326{ 327 struct iwl5000_tx_power_dbm_cmd tx_power_cmd; 328 u8 tx_ant_cfg_cmd; 329 330 /* half dBm need to multiply */ 331 tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt); 332 333 if (priv->tx_power_lmt_in_half_dbm && 334 priv->tx_power_lmt_in_half_dbm < tx_power_cmd.global_lmt) { 335 /* 336 * For the newer devices which using enhanced/extend tx power 337 * table in EEPROM, the format is in half dBm. driver need to 338 * convert to dBm format before report to mac80211. 339 * By doing so, there is a possibility of 1/2 dBm resolution 340 * lost. driver will perform "round-up" operation before 341 * reporting, but it will cause 1/2 dBm tx power over the 342 * regulatory limit. Perform the checking here, if the 343 * "tx_power_user_lmt" is higher than EEPROM value (in 344 * half-dBm format), lower the tx power based on EEPROM 345 */ 346 tx_power_cmd.global_lmt = priv->tx_power_lmt_in_half_dbm; 347 } 348 tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED; 349 tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO; 350 351 if (IWL_UCODE_API(priv->ucode_ver) == 1) 352 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1; 353 else 354 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD; 355 356 return iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd, 357 sizeof(tx_power_cmd), &tx_power_cmd, 358 NULL); 359} 360 361void iwlagn_temperature(struct iwl_priv *priv) 362{ 363 /* store temperature from statistics (in Celsius) */ 364 priv->temperature = 365 le32_to_cpu(priv->_agn.statistics.general.common.temperature); 366 iwl_tt_handler(priv); 367} 368 369u16 iwlagn_eeprom_calib_version(struct iwl_priv *priv) 370{ 371 struct iwl_eeprom_calib_hdr { 372 u8 version; 373 u8 pa_type; 374 u16 voltage; 375 } *hdr; 376 377 hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv, 378 EEPROM_CALIB_ALL); 379 return hdr->version; 380 381} 382 383/* 384 * EEPROM 385 */ 386static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address) 387{ 388 u16 offset = 0; 389 390 if ((address & INDIRECT_ADDRESS) == 0) 391 return address; 392 393 switch (address & INDIRECT_TYPE_MSK) { 394 case INDIRECT_HOST: 395 offset = iwl_eeprom_query16(priv, EEPROM_LINK_HOST); 396 break; 397 case INDIRECT_GENERAL: 398 offset = iwl_eeprom_query16(priv, EEPROM_LINK_GENERAL); 399 break; 400 case INDIRECT_REGULATORY: 401 offset = iwl_eeprom_query16(priv, EEPROM_LINK_REGULATORY); 402 break; 403 case INDIRECT_CALIBRATION: 404 offset = iwl_eeprom_query16(priv, EEPROM_LINK_CALIBRATION); 405 break; 406 case INDIRECT_PROCESS_ADJST: 407 offset = iwl_eeprom_query16(priv, EEPROM_LINK_PROCESS_ADJST); 408 break; 409 case INDIRECT_OTHERS: 410 offset = iwl_eeprom_query16(priv, EEPROM_LINK_OTHERS); 411 break; 412 default: 413 IWL_ERR(priv, "illegal indirect type: 0x%X\n", 414 address & INDIRECT_TYPE_MSK); 415 break; 416 } 417 418 /* translate the offset from words to byte */ 419 return (address & ADDRESS_MSK) + (offset << 1); 420} 421 422const u8 *iwlagn_eeprom_query_addr(const struct iwl_priv *priv, 423 size_t offset) 424{ 425 u32 address = eeprom_indirect_address(priv, offset); 426 BUG_ON(address >= priv->cfg->eeprom_size); 427 return &priv->eeprom[address]; 428} 429 430struct iwl_mod_params iwlagn_mod_params = { 431 .amsdu_size_8K = 1, 432 .restart_fw = 1, 433 /* the rest are 0 by default */ 434}; 435 436void iwlagn_rx_queue_reset(struct iwl_priv *priv, struct iwl_rx_queue *rxq) 437{ 438 unsigned long flags; 439 int i; 440 spin_lock_irqsave(&rxq->lock, flags); 441 INIT_LIST_HEAD(&rxq->rx_free); 442 INIT_LIST_HEAD(&rxq->rx_used); 443 /* Fill the rx_used queue with _all_ of the Rx buffers */ 444 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { 445 /* In the reset function, these buffers may have been allocated 446 * to an SKB, so we need to unmap and free potential storage */ 447 if (rxq->pool[i].page != NULL) { 448 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma, 449 PAGE_SIZE << priv->hw_params.rx_page_order, 450 PCI_DMA_FROMDEVICE); 451 __iwl_free_pages(priv, rxq->pool[i].page); 452 rxq->pool[i].page = NULL; 453 } 454 list_add_tail(&rxq->pool[i].list, &rxq->rx_used); 455 } 456 457 for (i = 0; i < RX_QUEUE_SIZE; i++) 458 rxq->queue[i] = NULL; 459 460 /* Set us so that we have processed and used all buffers, but have 461 * not restocked the Rx queue with fresh buffers */ 462 rxq->read = rxq->write = 0; 463 rxq->write_actual = 0; 464 rxq->free_count = 0; 465 spin_unlock_irqrestore(&rxq->lock, flags); 466} 467 468int iwlagn_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) 469{ 470 u32 rb_size; 471 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 472 u32 rb_timeout = 0; 473 474 if (!priv->cfg->use_isr_legacy) 475 rb_timeout = RX_RB_TIMEOUT; 476 477 if (priv->cfg->mod_params->amsdu_size_8K) 478 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 479 else 480 rb_size = FH_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 481 482 /* Stop Rx DMA */ 483 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 484 485 /* Reset driver's Rx queue write index */ 486 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 487 488 /* Tell device where to find RBD circular buffer in DRAM */ 489 iwl_write_direct32(priv, FH_RSCSR_CHNL0_RBDCB_BASE_REG, 490 (u32)(rxq->bd_dma >> 8)); 491 492 /* Tell device where in DRAM to update its Rx status */ 493 iwl_write_direct32(priv, FH_RSCSR_CHNL0_STTS_WPTR_REG, 494 rxq->rb_stts_dma >> 4); 495 496 /* Enable Rx DMA 497 * FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY is set because of HW bug in 498 * the credit mechanism in 5000 HW RX FIFO 499 * Direct rx interrupts to hosts 500 * Rx buffer size 4 or 8k 501 * RB timeout 0x10 502 * 256 RBDs 503 */ 504 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 505 FH_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 506 FH_RCSR_CHNL0_RX_IGNORE_RXF_EMPTY | 507 FH_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 508 FH_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | 509 rb_size| 510 (rb_timeout << FH_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS)| 511 (rfdnlog << FH_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 512 513 /* Set interrupt coalescing timer to default (2048 usecs) */ 514 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_TIMEOUT_DEF); 515 516 return 0; 517} 518 519int iwlagn_hw_nic_init(struct iwl_priv *priv) 520{ 521 unsigned long flags; 522 struct iwl_rx_queue *rxq = &priv->rxq; 523 int ret; 524 525 /* nic_init */ 526 spin_lock_irqsave(&priv->lock, flags); 527 priv->cfg->ops->lib->apm_ops.init(priv); 528 529 /* Set interrupt coalescing calibration timer to default (512 usecs) */ 530 iwl_write8(priv, CSR_INT_COALESCING, IWL_HOST_INT_CALIB_TIMEOUT_DEF); 531 532 spin_unlock_irqrestore(&priv->lock, flags); 533 534 ret = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN); 535 536 priv->cfg->ops->lib->apm_ops.config(priv); 537 538 /* Allocate the RX queue, or reset if it is already allocated */ 539 if (!rxq->bd) { 540 ret = iwl_rx_queue_alloc(priv); 541 if (ret) { 542 IWL_ERR(priv, "Unable to initialize Rx queue\n"); 543 return -ENOMEM; 544 } 545 } else 546 iwlagn_rx_queue_reset(priv, rxq); 547 548 iwlagn_rx_replenish(priv); 549 550 iwlagn_rx_init(priv, rxq); 551 552 spin_lock_irqsave(&priv->lock, flags); 553 554 rxq->need_update = 1; 555 iwl_rx_queue_update_write_ptr(priv, rxq); 556 557 spin_unlock_irqrestore(&priv->lock, flags); 558 559 /* Allocate or reset and init all Tx and Command queues */ 560 if (!priv->txq) { 561 ret = iwlagn_txq_ctx_alloc(priv); 562 if (ret) 563 return ret; 564 } else 565 iwlagn_txq_ctx_reset(priv); 566 567 set_bit(STATUS_INIT, &priv->status); 568 569 return 0; 570} 571 572/** 573 * iwlagn_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 574 */ 575static inline __le32 iwlagn_dma_addr2rbd_ptr(struct iwl_priv *priv, 576 dma_addr_t dma_addr) 577{ 578 return cpu_to_le32((u32)(dma_addr >> 8)); 579} 580 581/** 582 * iwlagn_rx_queue_restock - refill RX queue from pre-allocated pool 583 * 584 * If there are slots in the RX queue that need to be restocked, 585 * and we have free pre-allocated buffers, fill the ranks as much 586 * as we can, pulling from rx_free. 587 * 588 * This moves the 'write' index forward to catch up with 'processed', and 589 * also updates the memory address in the firmware to reference the new 590 * target buffer. 591 */ 592void iwlagn_rx_queue_restock(struct iwl_priv *priv) 593{ 594 struct iwl_rx_queue *rxq = &priv->rxq; 595 struct list_head *element; 596 struct iwl_rx_mem_buffer *rxb; 597 unsigned long flags; 598 599 spin_lock_irqsave(&rxq->lock, flags); 600 while ((iwl_rx_queue_space(rxq) > 0) && (rxq->free_count)) { 601 /* The overwritten rxb must be a used one */ 602 rxb = rxq->queue[rxq->write]; 603 BUG_ON(rxb && rxb->page); 604 605 /* Get next free Rx buffer, remove from free list */ 606 element = rxq->rx_free.next; 607 rxb = list_entry(element, struct iwl_rx_mem_buffer, list); 608 list_del(element); 609 610 /* Point to Rx buffer via next RBD in circular buffer */ 611 rxq->bd[rxq->write] = iwlagn_dma_addr2rbd_ptr(priv, 612 rxb->page_dma); 613 rxq->queue[rxq->write] = rxb; 614 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 615 rxq->free_count--; 616 } 617 spin_unlock_irqrestore(&rxq->lock, flags); 618 /* If the pre-allocated buffer pool is dropping low, schedule to 619 * refill it */ 620 if (rxq->free_count <= RX_LOW_WATERMARK) 621 queue_work(priv->workqueue, &priv->rx_replenish); 622 623 624 /* If we've added more space for the firmware to place data, tell it. 625 * Increment device's write pointer in multiples of 8. */ 626 if (rxq->write_actual != (rxq->write & ~0x7)) { 627 spin_lock_irqsave(&rxq->lock, flags); 628 rxq->need_update = 1; 629 spin_unlock_irqrestore(&rxq->lock, flags); 630 iwl_rx_queue_update_write_ptr(priv, rxq); 631 } 632} 633 634/** 635 * iwlagn_rx_replenish - Move all used packet from rx_used to rx_free 636 * 637 * When moving to rx_free an SKB is allocated for the slot. 638 * 639 * Also restock the Rx queue via iwl_rx_queue_restock. 640 * This is called as a scheduled work item (except for during initialization) 641 */ 642void iwlagn_rx_allocate(struct iwl_priv *priv, gfp_t priority) 643{ 644 struct iwl_rx_queue *rxq = &priv->rxq; 645 struct list_head *element; 646 struct iwl_rx_mem_buffer *rxb; 647 struct page *page; 648 unsigned long flags; 649 gfp_t gfp_mask = priority; 650 651 while (1) { 652 spin_lock_irqsave(&rxq->lock, flags); 653 if (list_empty(&rxq->rx_used)) { 654 spin_unlock_irqrestore(&rxq->lock, flags); 655 return; 656 } 657 spin_unlock_irqrestore(&rxq->lock, flags); 658 659 if (rxq->free_count > RX_LOW_WATERMARK) 660 gfp_mask |= __GFP_NOWARN; 661 662 if (priv->hw_params.rx_page_order > 0) 663 gfp_mask |= __GFP_COMP; 664 665 /* Alloc a new receive buffer */ 666 page = alloc_pages(gfp_mask, priv->hw_params.rx_page_order); 667 if (!page) { 668 if (net_ratelimit()) 669 IWL_DEBUG_INFO(priv, "alloc_pages failed, " 670 "order: %d\n", 671 priv->hw_params.rx_page_order); 672 673 if ((rxq->free_count <= RX_LOW_WATERMARK) && 674 net_ratelimit()) 675 IWL_CRIT(priv, "Failed to alloc_pages with %s. Only %u free buffers remaining.\n", 676 priority == GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL", 677 rxq->free_count); 678 /* We don't reschedule replenish work here -- we will 679 * call the restock method and if it still needs 680 * more buffers it will schedule replenish */ 681 return; 682 } 683 684 spin_lock_irqsave(&rxq->lock, flags); 685 686 if (list_empty(&rxq->rx_used)) { 687 spin_unlock_irqrestore(&rxq->lock, flags); 688 __free_pages(page, priv->hw_params.rx_page_order); 689 return; 690 } 691 element = rxq->rx_used.next; 692 rxb = list_entry(element, struct iwl_rx_mem_buffer, list); 693 list_del(element); 694 695 spin_unlock_irqrestore(&rxq->lock, flags); 696 697 BUG_ON(rxb->page); 698 rxb->page = page; 699 /* Get physical address of the RB */ 700 rxb->page_dma = pci_map_page(priv->pci_dev, page, 0, 701 PAGE_SIZE << priv->hw_params.rx_page_order, 702 PCI_DMA_FROMDEVICE); 703 /* dma address must be no more than 36 bits */ 704 BUG_ON(rxb->page_dma & ~DMA_BIT_MASK(36)); 705 /* and also 256 byte aligned! */ 706 BUG_ON(rxb->page_dma & DMA_BIT_MASK(8)); 707 708 spin_lock_irqsave(&rxq->lock, flags); 709 710 list_add_tail(&rxb->list, &rxq->rx_free); 711 rxq->free_count++; 712 priv->alloc_rxb_page++; 713 714 spin_unlock_irqrestore(&rxq->lock, flags); 715 } 716} 717 718void iwlagn_rx_replenish(struct iwl_priv *priv) 719{ 720 unsigned long flags; 721 722 iwlagn_rx_allocate(priv, GFP_KERNEL); 723 724 spin_lock_irqsave(&priv->lock, flags); 725 iwlagn_rx_queue_restock(priv); 726 spin_unlock_irqrestore(&priv->lock, flags); 727} 728 729void iwlagn_rx_replenish_now(struct iwl_priv *priv) 730{ 731 iwlagn_rx_allocate(priv, GFP_ATOMIC); 732 733 iwlagn_rx_queue_restock(priv); 734} 735 736/* Assumes that the skb field of the buffers in 'pool' is kept accurate. 737 * If an SKB has been detached, the POOL needs to have its SKB set to NULL 738 * This free routine walks the list of POOL entries and if SKB is set to 739 * non NULL it is unmapped and freed 740 */ 741void iwlagn_rx_queue_free(struct iwl_priv *priv, struct iwl_rx_queue *rxq) 742{ 743 int i; 744 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { 745 if (rxq->pool[i].page != NULL) { 746 pci_unmap_page(priv->pci_dev, rxq->pool[i].page_dma, 747 PAGE_SIZE << priv->hw_params.rx_page_order, 748 PCI_DMA_FROMDEVICE); 749 __iwl_free_pages(priv, rxq->pool[i].page); 750 rxq->pool[i].page = NULL; 751 } 752 } 753 754 dma_free_coherent(&priv->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd, 755 rxq->bd_dma); 756 dma_free_coherent(&priv->pci_dev->dev, sizeof(struct iwl_rb_status), 757 rxq->rb_stts, rxq->rb_stts_dma); 758 rxq->bd = NULL; 759 rxq->rb_stts = NULL; 760} 761 762int iwlagn_rxq_stop(struct iwl_priv *priv) 763{ 764 765 /* stop Rx DMA */ 766 iwl_write_direct32(priv, FH_MEM_RCSR_CHNL0_CONFIG_REG, 0); 767 iwl_poll_direct_bit(priv, FH_MEM_RSSR_RX_STATUS_REG, 768 FH_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); 769 770 return 0; 771} 772 773int iwlagn_hwrate_to_mac80211_idx(u32 rate_n_flags, enum ieee80211_band band) 774{ 775 int idx = 0; 776 int band_offset = 0; 777 778 /* HT rate format: mac80211 wants an MCS number, which is just LSB */ 779 if (rate_n_flags & RATE_MCS_HT_MSK) { 780 idx = (rate_n_flags & 0xff); 781 return idx; 782 /* Legacy rate format, search for match in table */ 783 } else { 784 if (band == IEEE80211_BAND_5GHZ) 785 band_offset = IWL_FIRST_OFDM_RATE; 786 for (idx = band_offset; idx < IWL_RATE_COUNT_LEGACY; idx++) 787 if (iwl_rates[idx].plcp == (rate_n_flags & 0xFF)) 788 return idx - band_offset; 789 } 790 791 return -1; 792} 793 794/* Calc max signal level (dBm) among 3 possible receivers */ 795static inline int iwlagn_calc_rssi(struct iwl_priv *priv, 796 struct iwl_rx_phy_res *rx_resp) 797{ 798 return priv->cfg->ops->utils->calc_rssi(priv, rx_resp); 799} 800 801static u32 iwlagn_translate_rx_status(struct iwl_priv *priv, u32 decrypt_in) 802{ 803 u32 decrypt_out = 0; 804 805 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) == 806 RX_RES_STATUS_STATION_FOUND) 807 decrypt_out |= (RX_RES_STATUS_STATION_FOUND | 808 RX_RES_STATUS_NO_STATION_INFO_MISMATCH); 809 810 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK); 811 812 /* packet was not encrypted */ 813 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == 814 RX_RES_STATUS_SEC_TYPE_NONE) 815 return decrypt_out; 816 817 /* packet was encrypted with unknown alg */ 818 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == 819 RX_RES_STATUS_SEC_TYPE_ERR) 820 return decrypt_out; 821 822 /* decryption was not done in HW */ 823 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) != 824 RX_MPDU_RES_STATUS_DEC_DONE_MSK) 825 return decrypt_out; 826 827 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) { 828 829 case RX_RES_STATUS_SEC_TYPE_CCMP: 830 /* alg is CCM: check MIC only */ 831 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK)) 832 /* Bad MIC */ 833 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; 834 else 835 decrypt_out |= RX_RES_STATUS_DECRYPT_OK; 836 837 break; 838 839 case RX_RES_STATUS_SEC_TYPE_TKIP: 840 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) { 841 /* Bad TTAK */ 842 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK; 843 break; 844 } 845 /* fall through if TTAK OK */ 846 default: 847 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK)) 848 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; 849 else 850 decrypt_out |= RX_RES_STATUS_DECRYPT_OK; 851 break; 852 } 853 854 IWL_DEBUG_RX(priv, "decrypt_in:0x%x decrypt_out = 0x%x\n", 855 decrypt_in, decrypt_out); 856 857 return decrypt_out; 858} 859 860static void iwlagn_pass_packet_to_mac80211(struct iwl_priv *priv, 861 struct ieee80211_hdr *hdr, 862 u16 len, 863 u32 ampdu_status, 864 struct iwl_rx_mem_buffer *rxb, 865 struct ieee80211_rx_status *stats) 866{ 867 struct sk_buff *skb; 868 __le16 fc = hdr->frame_control; 869 870 /* We only process data packets if the interface is open */ 871 if (unlikely(!priv->is_open)) { 872 IWL_DEBUG_DROP_LIMIT(priv, 873 "Dropping packet while interface is not open.\n"); 874 return; 875 } 876 877 /* In case of HW accelerated crypto and bad decryption, drop */ 878 if (!priv->cfg->mod_params->sw_crypto && 879 iwl_set_decrypted_flag(priv, hdr, ampdu_status, stats)) 880 return; 881 882 skb = dev_alloc_skb(128); 883 if (!skb) { 884 IWL_ERR(priv, "dev_alloc_skb failed\n"); 885 return; 886 } 887 888 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), len); 889 890 iwl_update_stats(priv, false, fc, len); 891 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats)); 892 893 ieee80211_rx(priv->hw, skb); 894 priv->alloc_rxb_page--; 895 rxb->page = NULL; 896} 897 898/* Called for REPLY_RX (legacy ABG frames), or 899 * REPLY_RX_MPDU_CMD (HT high-throughput N frames). */ 900void iwlagn_rx_reply_rx(struct iwl_priv *priv, 901 struct iwl_rx_mem_buffer *rxb) 902{ 903 struct ieee80211_hdr *header; 904 struct ieee80211_rx_status rx_status; 905 struct iwl_rx_packet *pkt = rxb_addr(rxb); 906 struct iwl_rx_phy_res *phy_res; 907 __le32 rx_pkt_status; 908 struct iwl_rx_mpdu_res_start *amsdu; 909 u32 len; 910 u32 ampdu_status; 911 u32 rate_n_flags; 912 913 /** 914 * REPLY_RX and REPLY_RX_MPDU_CMD are handled differently. 915 * REPLY_RX: physical layer info is in this buffer 916 * REPLY_RX_MPDU_CMD: physical layer info was sent in separate 917 * command and cached in priv->last_phy_res 918 * 919 * Here we set up local variables depending on which command is 920 * received. 921 */ 922 if (pkt->hdr.cmd == REPLY_RX) { 923 phy_res = (struct iwl_rx_phy_res *)pkt->u.raw; 924 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) 925 + phy_res->cfg_phy_cnt); 926 927 len = le16_to_cpu(phy_res->byte_count); 928 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*phy_res) + 929 phy_res->cfg_phy_cnt + len); 930 ampdu_status = le32_to_cpu(rx_pkt_status); 931 } else { 932 if (!priv->_agn.last_phy_res_valid) { 933 IWL_ERR(priv, "MPDU frame without cached PHY data\n"); 934 return; 935 } 936 phy_res = &priv->_agn.last_phy_res; 937 amsdu = (struct iwl_rx_mpdu_res_start *)pkt->u.raw; 938 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu)); 939 len = le16_to_cpu(amsdu->byte_count); 940 rx_pkt_status = *(__le32 *)(pkt->u.raw + sizeof(*amsdu) + len); 941 ampdu_status = iwlagn_translate_rx_status(priv, 942 le32_to_cpu(rx_pkt_status)); 943 } 944 945 if ((unlikely(phy_res->cfg_phy_cnt > 20))) { 946 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n", 947 phy_res->cfg_phy_cnt); 948 return; 949 } 950 951 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) || 952 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) { 953 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", 954 le32_to_cpu(rx_pkt_status)); 955 return; 956 } 957 958 /* This will be used in several places later */ 959 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags); 960 961 /* rx_status carries information about the packet to mac80211 */ 962 rx_status.mactime = le64_to_cpu(phy_res->timestamp); 963 rx_status.freq = 964 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel)); 965 rx_status.band = (phy_res->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? 966 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; 967 rx_status.rate_idx = 968 iwlagn_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band); 969 rx_status.flag = 0; 970 971 /* TSF isn't reliable. In order to allow smooth user experience, 972 * this W/A doesn't propagate it to the mac80211 */ 973 /*rx_status.flag |= RX_FLAG_TSFT;*/ 974 975 priv->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp); 976 977 /* Find max signal strength (dBm) among 3 antenna/receiver chains */ 978 rx_status.signal = iwlagn_calc_rssi(priv, phy_res); 979 980 iwl_dbg_log_rx_data_frame(priv, len, header); 981 IWL_DEBUG_STATS_LIMIT(priv, "Rssi %d, TSF %llu\n", 982 rx_status.signal, (unsigned long long)rx_status.mactime); 983 984 /* 985 * "antenna number" 986 * 987 * It seems that the antenna field in the phy flags value 988 * is actually a bit field. This is undefined by radiotap, 989 * it wants an actual antenna number but I always get "7" 990 * for most legacy frames I receive indicating that the 991 * same frame was received on all three RX chains. 992 * 993 * I think this field should be removed in favor of a 994 * new 802.11n radiotap field "RX chains" that is defined 995 * as a bitmask. 996 */ 997 rx_status.antenna = 998 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) 999 >> RX_RES_PHY_FLAGS_ANTENNA_POS; 1000 1001 /* set the preamble flag if appropriate */ 1002 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) 1003 rx_status.flag |= RX_FLAG_SHORTPRE; 1004 1005 /* Set up the HT phy flags */ 1006 if (rate_n_flags & RATE_MCS_HT_MSK) 1007 rx_status.flag |= RX_FLAG_HT; 1008 if (rate_n_flags & RATE_MCS_HT40_MSK) 1009 rx_status.flag |= RX_FLAG_40MHZ; 1010 if (rate_n_flags & RATE_MCS_SGI_MSK) 1011 rx_status.flag |= RX_FLAG_SHORT_GI; 1012 1013 iwlagn_pass_packet_to_mac80211(priv, header, len, ampdu_status, 1014 rxb, &rx_status); 1015} 1016 1017/* Cache phy data (Rx signal strength, etc) for HT frame (REPLY_RX_PHY_CMD). 1018 * This will be used later in iwl_rx_reply_rx() for REPLY_RX_MPDU_CMD. */ 1019void iwlagn_rx_reply_rx_phy(struct iwl_priv *priv, 1020 struct iwl_rx_mem_buffer *rxb) 1021{ 1022 struct iwl_rx_packet *pkt = rxb_addr(rxb); 1023 priv->_agn.last_phy_res_valid = true; 1024 memcpy(&priv->_agn.last_phy_res, pkt->u.raw, 1025 sizeof(struct iwl_rx_phy_res)); 1026} 1027 1028static int iwl_get_single_channel_for_scan(struct iwl_priv *priv, 1029 struct ieee80211_vif *vif, 1030 enum ieee80211_band band, 1031 struct iwl_scan_channel *scan_ch) 1032{ 1033 const struct ieee80211_supported_band *sband; 1034 u16 passive_dwell = 0; 1035 u16 active_dwell = 0; 1036 int added = 0; 1037 u16 channel = 0; 1038 1039 sband = iwl_get_hw_mode(priv, band); 1040 if (!sband) { 1041 IWL_ERR(priv, "invalid band\n"); 1042 return added; 1043 } 1044 1045 active_dwell = iwl_get_active_dwell_time(priv, band, 0); 1046 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif); 1047 1048 if (passive_dwell <= active_dwell) 1049 passive_dwell = active_dwell + 1; 1050 1051 channel = iwl_get_single_channel_number(priv, band); 1052 if (channel) { 1053 scan_ch->channel = cpu_to_le16(channel); 1054 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE; 1055 scan_ch->active_dwell = cpu_to_le16(active_dwell); 1056 scan_ch->passive_dwell = cpu_to_le16(passive_dwell); 1057 /* Set txpower levels to defaults */ 1058 scan_ch->dsp_atten = 110; 1059 if (band == IEEE80211_BAND_5GHZ) 1060 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3; 1061 else 1062 scan_ch->tx_gain = ((1 << 5) | (5 << 3)); 1063 added++; 1064 } else 1065 IWL_ERR(priv, "no valid channel found\n"); 1066 return added; 1067} 1068 1069static int iwl_get_channels_for_scan(struct iwl_priv *priv, 1070 struct ieee80211_vif *vif, 1071 enum ieee80211_band band, 1072 u8 is_active, u8 n_probes, 1073 struct iwl_scan_channel *scan_ch) 1074{ 1075 struct ieee80211_channel *chan; 1076 const struct ieee80211_supported_band *sband; 1077 const struct iwl_channel_info *ch_info; 1078 u16 passive_dwell = 0; 1079 u16 active_dwell = 0; 1080 int added, i; 1081 u16 channel; 1082 1083 sband = iwl_get_hw_mode(priv, band); 1084 if (!sband) 1085 return 0; 1086 1087 active_dwell = iwl_get_active_dwell_time(priv, band, n_probes); 1088 passive_dwell = iwl_get_passive_dwell_time(priv, band, vif); 1089 1090 if (passive_dwell <= active_dwell) 1091 passive_dwell = active_dwell + 1; 1092 1093 for (i = 0, added = 0; i < priv->scan_request->n_channels; i++) { 1094 chan = priv->scan_request->channels[i]; 1095 1096 if (chan->band != band) 1097 continue; 1098 1099 channel = ieee80211_frequency_to_channel(chan->center_freq); 1100 scan_ch->channel = cpu_to_le16(channel); 1101 1102 ch_info = iwl_get_channel_info(priv, band, channel); 1103 if (!is_channel_valid(ch_info)) { 1104 IWL_DEBUG_SCAN(priv, "Channel %d is INVALID for this band.\n", 1105 channel); 1106 continue; 1107 } 1108 1109 if (!is_active || is_channel_passive(ch_info) || 1110 (chan->flags & IEEE80211_CHAN_PASSIVE_SCAN)) 1111 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE; 1112 else 1113 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE; 1114 1115 if (n_probes) 1116 scan_ch->type |= IWL_SCAN_PROBE_MASK(n_probes); 1117 1118 scan_ch->active_dwell = cpu_to_le16(active_dwell); 1119 scan_ch->passive_dwell = cpu_to_le16(passive_dwell); 1120 1121 /* Set txpower levels to defaults */ 1122 scan_ch->dsp_atten = 110; 1123 1124 /* NOTE: if we were doing 6Mb OFDM for scans we'd use 1125 * power level: 1126 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3; 1127 */ 1128 if (band == IEEE80211_BAND_5GHZ) 1129 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3; 1130 else 1131 scan_ch->tx_gain = ((1 << 5) | (5 << 3)); 1132 1133 IWL_DEBUG_SCAN(priv, "Scanning ch=%d prob=0x%X [%s %d]\n", 1134 channel, le32_to_cpu(scan_ch->type), 1135 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ? 1136 "ACTIVE" : "PASSIVE", 1137 (scan_ch->type & SCAN_CHANNEL_TYPE_ACTIVE) ? 1138 active_dwell : passive_dwell); 1139 1140 scan_ch++; 1141 added++; 1142 } 1143 1144 IWL_DEBUG_SCAN(priv, "total channels to scan %d\n", added); 1145 return added; 1146} 1147 1148void iwlagn_request_scan(struct iwl_priv *priv, struct ieee80211_vif *vif) 1149{ 1150 struct iwl_host_cmd cmd = { 1151 .id = REPLY_SCAN_CMD, 1152 .len = sizeof(struct iwl_scan_cmd), 1153 .flags = CMD_SIZE_HUGE, 1154 }; 1155 struct iwl_scan_cmd *scan; 1156 struct ieee80211_conf *conf = NULL; 1157 u32 rate_flags = 0; 1158 u16 cmd_len; 1159 u16 rx_chain = 0; 1160 enum ieee80211_band band; 1161 u8 n_probes = 0; 1162 u8 rx_ant = priv->hw_params.valid_rx_ant; 1163 u8 rate; 1164 bool is_active = false; 1165 int chan_mod; 1166 u8 active_chains; 1167 u8 scan_tx_antennas = priv->hw_params.valid_tx_ant; 1168 1169 conf = ieee80211_get_hw_conf(priv->hw); 1170 1171 cancel_delayed_work(&priv->scan_check); 1172 1173 if (!iwl_is_ready(priv)) { 1174 IWL_WARN(priv, "request scan called when driver not ready.\n"); 1175 goto done; 1176 } 1177 1178 /* Make sure the scan wasn't canceled before this queued work 1179 * was given the chance to run... */ 1180 if (!test_bit(STATUS_SCANNING, &priv->status)) 1181 goto done; 1182 1183 /* This should never be called or scheduled if there is currently 1184 * a scan active in the hardware. */ 1185 if (test_bit(STATUS_SCAN_HW, &priv->status)) { 1186 IWL_DEBUG_INFO(priv, "Multiple concurrent scan requests in parallel. " 1187 "Ignoring second request.\n"); 1188 goto done; 1189 } 1190 1191 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) { 1192 IWL_DEBUG_SCAN(priv, "Aborting scan due to device shutdown\n"); 1193 goto done; 1194 } 1195 1196 if (test_bit(STATUS_SCAN_ABORTING, &priv->status)) { 1197 IWL_DEBUG_HC(priv, "Scan request while abort pending. Queuing.\n"); 1198 goto done; 1199 } 1200 1201 if (iwl_is_rfkill(priv)) { 1202 IWL_DEBUG_HC(priv, "Aborting scan due to RF Kill activation\n"); 1203 goto done; 1204 } 1205 1206 if (!test_bit(STATUS_READY, &priv->status)) { 1207 IWL_DEBUG_HC(priv, "Scan request while uninitialized. Queuing.\n"); 1208 goto done; 1209 } 1210 1211 if (!priv->scan_cmd) { 1212 priv->scan_cmd = kmalloc(sizeof(struct iwl_scan_cmd) + 1213 IWL_MAX_SCAN_SIZE, GFP_KERNEL); 1214 if (!priv->scan_cmd) { 1215 IWL_DEBUG_SCAN(priv, 1216 "fail to allocate memory for scan\n"); 1217 goto done; 1218 } 1219 } 1220 scan = priv->scan_cmd; 1221 memset(scan, 0, sizeof(struct iwl_scan_cmd) + IWL_MAX_SCAN_SIZE); 1222 1223 scan->quiet_plcp_th = IWL_PLCP_QUIET_THRESH; 1224 scan->quiet_time = IWL_ACTIVE_QUIET_TIME; 1225 1226 if (iwl_is_associated(priv)) { 1227 u16 interval = 0; 1228 u32 extra; 1229 u32 suspend_time = 100; 1230 u32 scan_suspend_time = 100; 1231 unsigned long flags; 1232 1233 IWL_DEBUG_INFO(priv, "Scanning while associated...\n"); 1234 spin_lock_irqsave(&priv->lock, flags); 1235 if (priv->is_internal_short_scan) 1236 interval = 0; 1237 else 1238 interval = vif->bss_conf.beacon_int; 1239 spin_unlock_irqrestore(&priv->lock, flags); 1240 1241 scan->suspend_time = 0; 1242 scan->max_out_time = cpu_to_le32(200 * 1024); 1243 if (!interval) 1244 interval = suspend_time; 1245 1246 extra = (suspend_time / interval) << 22; 1247 scan_suspend_time = (extra | 1248 ((suspend_time % interval) * 1024)); 1249 scan->suspend_time = cpu_to_le32(scan_suspend_time); 1250 IWL_DEBUG_SCAN(priv, "suspend_time 0x%X beacon interval %d\n", 1251 scan_suspend_time, interval); 1252 } 1253 1254 if (priv->is_internal_short_scan) { 1255 IWL_DEBUG_SCAN(priv, "Start internal passive scan.\n"); 1256 } else if (priv->scan_request->n_ssids) { 1257 int i, p = 0; 1258 IWL_DEBUG_SCAN(priv, "Kicking off active scan\n"); 1259 for (i = 0; i < priv->scan_request->n_ssids; i++) { 1260 /* always does wildcard anyway */ 1261 if (!priv->scan_request->ssids[i].ssid_len) 1262 continue; 1263 scan->direct_scan[p].id = WLAN_EID_SSID; 1264 scan->direct_scan[p].len = 1265 priv->scan_request->ssids[i].ssid_len; 1266 memcpy(scan->direct_scan[p].ssid, 1267 priv->scan_request->ssids[i].ssid, 1268 priv->scan_request->ssids[i].ssid_len); 1269 n_probes++; 1270 p++; 1271 } 1272 is_active = true; 1273 } else 1274 IWL_DEBUG_SCAN(priv, "Start passive scan.\n"); 1275 1276 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; 1277 scan->tx_cmd.sta_id = priv->hw_params.bcast_sta_id; 1278 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 1279 1280 switch (priv->scan_band) { 1281 case IEEE80211_BAND_2GHZ: 1282 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; 1283 chan_mod = le32_to_cpu(priv->active_rxon.flags & RXON_FLG_CHANNEL_MODE_MSK) 1284 >> RXON_FLG_CHANNEL_MODE_POS; 1285 if (chan_mod == CHANNEL_MODE_PURE_40) { 1286 rate = IWL_RATE_6M_PLCP; 1287 } else { 1288 rate = IWL_RATE_1M_PLCP; 1289 rate_flags = RATE_MCS_CCK_MSK; 1290 } 1291 scan->good_CRC_th = IWL_GOOD_CRC_TH_DISABLED; 1292 break; 1293 case IEEE80211_BAND_5GHZ: 1294 rate = IWL_RATE_6M_PLCP; 1295 scan->good_CRC_th = is_active ? IWL_GOOD_CRC_TH_DEFAULT : 1296 IWL_GOOD_CRC_TH_NEVER; 1297 break; 1298 default: 1299 IWL_WARN(priv, "Invalid scan band count\n"); 1300 goto done; 1301 } 1302 1303 band = priv->scan_band; 1304 1305 if (priv->cfg->scan_rx_antennas[band]) 1306 rx_ant = priv->cfg->scan_rx_antennas[band]; 1307 1308 if (priv->cfg->scan_tx_antennas[band]) 1309 scan_tx_antennas = priv->cfg->scan_tx_antennas[band]; 1310 1311 priv->scan_tx_ant[band] = iwl_toggle_tx_ant(priv, priv->scan_tx_ant[band], 1312 scan_tx_antennas); 1313 rate_flags |= iwl_ant_idx_to_flags(priv->scan_tx_ant[band]); 1314 scan->tx_cmd.rate_n_flags = iwl_hw_set_rate_n_flags(rate, rate_flags); 1315 1316 /* In power save mode use one chain, otherwise use all chains */ 1317 if (test_bit(STATUS_POWER_PMI, &priv->status)) { 1318 /* rx_ant has been set to all valid chains previously */ 1319 active_chains = rx_ant & 1320 ((u8)(priv->chain_noise_data.active_chains)); 1321 if (!active_chains) 1322 active_chains = rx_ant; 1323 1324 IWL_DEBUG_SCAN(priv, "chain_noise_data.active_chains: %u\n", 1325 priv->chain_noise_data.active_chains); 1326 1327 rx_ant = first_antenna(active_chains); 1328 } 1329 /* MIMO is not used here, but value is required */ 1330 rx_chain |= priv->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS; 1331 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS; 1332 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS; 1333 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS; 1334 scan->rx_chain = cpu_to_le16(rx_chain); 1335 if (!priv->is_internal_short_scan) { 1336 cmd_len = iwl_fill_probe_req(priv, 1337 (struct ieee80211_mgmt *)scan->data, 1338 vif->addr, 1339 priv->scan_request->ie, 1340 priv->scan_request->ie_len, 1341 IWL_MAX_SCAN_SIZE - sizeof(*scan)); 1342 } else { 1343 /* use bcast addr, will not be transmitted but must be valid */ 1344 cmd_len = iwl_fill_probe_req(priv, 1345 (struct ieee80211_mgmt *)scan->data, 1346 iwl_bcast_addr, NULL, 0, 1347 IWL_MAX_SCAN_SIZE - sizeof(*scan)); 1348 1349 } 1350 scan->tx_cmd.len = cpu_to_le16(cmd_len); 1351 1352 scan->filter_flags |= (RXON_FILTER_ACCEPT_GRP_MSK | 1353 RXON_FILTER_BCON_AWARE_MSK); 1354 1355 if (priv->is_internal_short_scan) { 1356 scan->channel_count = 1357 iwl_get_single_channel_for_scan(priv, vif, band, 1358 (void *)&scan->data[le16_to_cpu( 1359 scan->tx_cmd.len)]); 1360 } else { 1361 scan->channel_count = 1362 iwl_get_channels_for_scan(priv, vif, band, 1363 is_active, n_probes, 1364 (void *)&scan->data[le16_to_cpu( 1365 scan->tx_cmd.len)]); 1366 } 1367 if (scan->channel_count == 0) { 1368 IWL_DEBUG_SCAN(priv, "channel count %d\n", scan->channel_count); 1369 goto done; 1370 } 1371 1372 cmd.len += le16_to_cpu(scan->tx_cmd.len) + 1373 scan->channel_count * sizeof(struct iwl_scan_channel); 1374 cmd.data = scan; 1375 scan->len = cpu_to_le16(cmd.len); 1376 1377 set_bit(STATUS_SCAN_HW, &priv->status); 1378 if (iwl_send_cmd_sync(priv, &cmd)) 1379 goto done; 1380 1381 queue_delayed_work(priv->workqueue, &priv->scan_check, 1382 IWL_SCAN_CHECK_WATCHDOG); 1383 1384 return; 1385 1386 done: 1387 /* Cannot perform scan. Make sure we clear scanning 1388 * bits from status so next scan request can be performed. 1389 * If we don't clear scanning status bit here all next scan 1390 * will fail 1391 */ 1392 clear_bit(STATUS_SCAN_HW, &priv->status); 1393 clear_bit(STATUS_SCANNING, &priv->status); 1394 /* inform mac80211 scan aborted */ 1395 queue_work(priv->workqueue, &priv->abort_scan); 1396} 1397 1398int iwlagn_manage_ibss_station(struct iwl_priv *priv, 1399 struct ieee80211_vif *vif, bool add) 1400{ 1401 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; 1402 1403 if (add) 1404 return iwl_add_bssid_station(priv, vif->bss_conf.bssid, true, 1405 &vif_priv->ibss_bssid_sta_id); 1406 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id, 1407 vif->bss_conf.bssid); 1408} 1409 1410void iwl_free_tfds_in_queue(struct iwl_priv *priv, 1411 int sta_id, int tid, int freed) 1412{ 1413 lockdep_assert_held(&priv->sta_lock); 1414 1415 if (priv->stations[sta_id].tid[tid].tfds_in_queue >= freed) 1416 priv->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1417 else { 1418 IWL_DEBUG_TX(priv, "free more than tfds_in_queue (%u:%d)\n", 1419 priv->stations[sta_id].tid[tid].tfds_in_queue, 1420 freed); 1421 priv->stations[sta_id].tid[tid].tfds_in_queue = 0; 1422 } 1423} 1424 1425#define IWL_FLUSH_WAIT_MS 2000 1426 1427int iwlagn_wait_tx_queue_empty(struct iwl_priv *priv) 1428{ 1429 struct iwl_tx_queue *txq; 1430 struct iwl_queue *q; 1431 int cnt; 1432 unsigned long now = jiffies; 1433 int ret = 0; 1434 1435 /* waiting for all the tx frames complete might take a while */ 1436 for (cnt = 0; cnt < priv->hw_params.max_txq_num; cnt++) { 1437 if (cnt == IWL_CMD_QUEUE_NUM) 1438 continue; 1439 txq = &priv->txq[cnt]; 1440 q = &txq->q; 1441 while (q->read_ptr != q->write_ptr && !time_after(jiffies, 1442 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) 1443 msleep(1); 1444 1445 if (q->read_ptr != q->write_ptr) { 1446 IWL_ERR(priv, "fail to flush all tx fifo queues\n"); 1447 ret = -ETIMEDOUT; 1448 break; 1449 } 1450 } 1451 return ret; 1452} 1453 1454#define IWL_TX_QUEUE_MSK 0xfffff 1455 1456/** 1457 * iwlagn_txfifo_flush: send REPLY_TXFIFO_FLUSH command to uCode 1458 * 1459 * pre-requirements: 1460 * 1. acquire mutex before calling 1461 * 2. make sure rf is on and not in exit state 1462 */ 1463int iwlagn_txfifo_flush(struct iwl_priv *priv, u16 flush_control) 1464{ 1465 struct iwl_txfifo_flush_cmd flush_cmd; 1466 struct iwl_host_cmd cmd = { 1467 .id = REPLY_TXFIFO_FLUSH, 1468 .len = sizeof(struct iwl_txfifo_flush_cmd), 1469 .flags = CMD_SYNC, 1470 .data = &flush_cmd, 1471 }; 1472 1473 might_sleep(); 1474 1475 memset(&flush_cmd, 0, sizeof(flush_cmd)); 1476 flush_cmd.fifo_control = IWL_TX_FIFO_VO_MSK | IWL_TX_FIFO_VI_MSK | 1477 IWL_TX_FIFO_BE_MSK | IWL_TX_FIFO_BK_MSK; 1478 if (priv->cfg->sku & IWL_SKU_N) 1479 flush_cmd.fifo_control |= IWL_AGG_TX_QUEUE_MSK; 1480 1481 IWL_DEBUG_INFO(priv, "fifo queue control: 0X%x\n", 1482 flush_cmd.fifo_control); 1483 flush_cmd.flush_control = cpu_to_le16(flush_control); 1484 1485 return iwl_send_cmd(priv, &cmd); 1486} 1487 1488void iwlagn_dev_txfifo_flush(struct iwl_priv *priv, u16 flush_control) 1489{ 1490 mutex_lock(&priv->mutex); 1491 ieee80211_stop_queues(priv->hw); 1492 if (priv->cfg->ops->lib->txfifo_flush(priv, IWL_DROP_ALL)) { 1493 IWL_ERR(priv, "flush request fail\n"); 1494 goto done; 1495 } 1496 IWL_DEBUG_INFO(priv, "wait transmit/flush all frames\n"); 1497 iwlagn_wait_tx_queue_empty(priv); 1498done: 1499 ieee80211_wake_queues(priv->hw); 1500 mutex_unlock(&priv->mutex); 1501} 1502