1/****************************************************************************** 2 * 3 * Copyright(c) 2003 - 2010 Intel Corporation. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of version 2 of the GNU General Public License as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 * You should have received a copy of the GNU General Public License along with 15 * this program; if not, write to the Free Software Foundation, Inc., 16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA 17 * 18 * The full GNU General Public License is included in this distribution in the 19 * file called LICENSE. 20 * 21 * Contact Information: 22 * Intel Linux Wireless <ilw@linux.intel.com> 23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 24 * 25 *****************************************************************************/ 26 27#include <linux/kernel.h> 28#include <linux/module.h> 29#include <linux/init.h> 30#include <linux/slab.h> 31#include <linux/pci.h> 32#include <linux/dma-mapping.h> 33#include <linux/delay.h> 34#include <linux/sched.h> 35#include <linux/skbuff.h> 36#include <linux/netdevice.h> 37#include <linux/wireless.h> 38#include <linux/firmware.h> 39#include <linux/etherdevice.h> 40#include <asm/unaligned.h> 41#include <net/mac80211.h> 42 43#include "iwl-fh.h" 44#include "iwl-3945-fh.h" 45#include "iwl-commands.h" 46#include "iwl-sta.h" 47#include "iwl-3945.h" 48#include "iwl-eeprom.h" 49#include "iwl-core.h" 50#include "iwl-helpers.h" 51#include "iwl-led.h" 52#include "iwl-3945-led.h" 53#include "iwl-3945-debugfs.h" 54 55#define IWL_DECLARE_RATE_INFO(r, ip, in, rp, rn, pp, np) \ 56 [IWL_RATE_##r##M_INDEX] = { IWL_RATE_##r##M_PLCP, \ 57 IWL_RATE_##r##M_IEEE, \ 58 IWL_RATE_##ip##M_INDEX, \ 59 IWL_RATE_##in##M_INDEX, \ 60 IWL_RATE_##rp##M_INDEX, \ 61 IWL_RATE_##rn##M_INDEX, \ 62 IWL_RATE_##pp##M_INDEX, \ 63 IWL_RATE_##np##M_INDEX, \ 64 IWL_RATE_##r##M_INDEX_TABLE, \ 65 IWL_RATE_##ip##M_INDEX_TABLE } 66 67/* 68 * Parameter order: 69 * rate, prev rate, next rate, prev tgg rate, next tgg rate 70 * 71 * If there isn't a valid next or previous rate then INV is used which 72 * maps to IWL_RATE_INVALID 73 * 74 */ 75const struct iwl3945_rate_info iwl3945_rates[IWL_RATE_COUNT_3945] = { 76 IWL_DECLARE_RATE_INFO(1, INV, 2, INV, 2, INV, 2), /* 1mbps */ 77 IWL_DECLARE_RATE_INFO(2, 1, 5, 1, 5, 1, 5), /* 2mbps */ 78 IWL_DECLARE_RATE_INFO(5, 2, 6, 2, 11, 2, 11), /*5.5mbps */ 79 IWL_DECLARE_RATE_INFO(11, 9, 12, 5, 12, 5, 18), /* 11mbps */ 80 IWL_DECLARE_RATE_INFO(6, 5, 9, 5, 11, 5, 11), /* 6mbps */ 81 IWL_DECLARE_RATE_INFO(9, 6, 11, 5, 11, 5, 11), /* 9mbps */ 82 IWL_DECLARE_RATE_INFO(12, 11, 18, 11, 18, 11, 18), /* 12mbps */ 83 IWL_DECLARE_RATE_INFO(18, 12, 24, 12, 24, 11, 24), /* 18mbps */ 84 IWL_DECLARE_RATE_INFO(24, 18, 36, 18, 36, 18, 36), /* 24mbps */ 85 IWL_DECLARE_RATE_INFO(36, 24, 48, 24, 48, 24, 48), /* 36mbps */ 86 IWL_DECLARE_RATE_INFO(48, 36, 54, 36, 54, 36, 54), /* 48mbps */ 87 IWL_DECLARE_RATE_INFO(54, 48, INV, 48, INV, 48, INV),/* 54mbps */ 88}; 89 90/* 1 = enable the iwl3945_disable_events() function */ 91#define IWL_EVT_DISABLE (0) 92#define IWL_EVT_DISABLE_SIZE (1532/32) 93 94/** 95 * iwl3945_disable_events - Disable selected events in uCode event log 96 * 97 * Disable an event by writing "1"s into "disable" 98 * bitmap in SRAM. Bit position corresponds to Event # (id/type). 99 * Default values of 0 enable uCode events to be logged. 100 * Use for only special debugging. This function is just a placeholder as-is, 101 * you'll need to provide the special bits! ... 102 * ... and set IWL_EVT_DISABLE to 1. */ 103void iwl3945_disable_events(struct iwl_priv *priv) 104{ 105 int i; 106 u32 base; /* SRAM address of event log header */ 107 u32 disable_ptr; /* SRAM address of event-disable bitmap array */ 108 u32 array_size; /* # of u32 entries in array */ 109 u32 evt_disable[IWL_EVT_DISABLE_SIZE] = { 110 0x00000000, /* 31 - 0 Event id numbers */ 111 0x00000000, /* 63 - 32 */ 112 0x00000000, /* 95 - 64 */ 113 0x00000000, /* 127 - 96 */ 114 0x00000000, /* 159 - 128 */ 115 0x00000000, /* 191 - 160 */ 116 0x00000000, /* 223 - 192 */ 117 0x00000000, /* 255 - 224 */ 118 0x00000000, /* 287 - 256 */ 119 0x00000000, /* 319 - 288 */ 120 0x00000000, /* 351 - 320 */ 121 0x00000000, /* 383 - 352 */ 122 0x00000000, /* 415 - 384 */ 123 0x00000000, /* 447 - 416 */ 124 0x00000000, /* 479 - 448 */ 125 0x00000000, /* 511 - 480 */ 126 0x00000000, /* 543 - 512 */ 127 0x00000000, /* 575 - 544 */ 128 0x00000000, /* 607 - 576 */ 129 0x00000000, /* 639 - 608 */ 130 0x00000000, /* 671 - 640 */ 131 0x00000000, /* 703 - 672 */ 132 0x00000000, /* 735 - 704 */ 133 0x00000000, /* 767 - 736 */ 134 0x00000000, /* 799 - 768 */ 135 0x00000000, /* 831 - 800 */ 136 0x00000000, /* 863 - 832 */ 137 0x00000000, /* 895 - 864 */ 138 0x00000000, /* 927 - 896 */ 139 0x00000000, /* 959 - 928 */ 140 0x00000000, /* 991 - 960 */ 141 0x00000000, /* 1023 - 992 */ 142 0x00000000, /* 1055 - 1024 */ 143 0x00000000, /* 1087 - 1056 */ 144 0x00000000, /* 1119 - 1088 */ 145 0x00000000, /* 1151 - 1120 */ 146 0x00000000, /* 1183 - 1152 */ 147 0x00000000, /* 1215 - 1184 */ 148 0x00000000, /* 1247 - 1216 */ 149 0x00000000, /* 1279 - 1248 */ 150 0x00000000, /* 1311 - 1280 */ 151 0x00000000, /* 1343 - 1312 */ 152 0x00000000, /* 1375 - 1344 */ 153 0x00000000, /* 1407 - 1376 */ 154 0x00000000, /* 1439 - 1408 */ 155 0x00000000, /* 1471 - 1440 */ 156 0x00000000, /* 1503 - 1472 */ 157 }; 158 159 base = le32_to_cpu(priv->card_alive.log_event_table_ptr); 160 if (!iwl3945_hw_valid_rtc_data_addr(base)) { 161 IWL_ERR(priv, "Invalid event log pointer 0x%08X\n", base); 162 return; 163 } 164 165 disable_ptr = iwl_read_targ_mem(priv, base + (4 * sizeof(u32))); 166 array_size = iwl_read_targ_mem(priv, base + (5 * sizeof(u32))); 167 168 if (IWL_EVT_DISABLE && (array_size == IWL_EVT_DISABLE_SIZE)) { 169 IWL_DEBUG_INFO(priv, "Disabling selected uCode log events at 0x%x\n", 170 disable_ptr); 171 for (i = 0; i < IWL_EVT_DISABLE_SIZE; i++) 172 iwl_write_targ_mem(priv, 173 disable_ptr + (i * sizeof(u32)), 174 evt_disable[i]); 175 176 } else { 177 IWL_DEBUG_INFO(priv, "Selected uCode log events may be disabled\n"); 178 IWL_DEBUG_INFO(priv, " by writing \"1\"s into disable bitmap\n"); 179 IWL_DEBUG_INFO(priv, " in SRAM at 0x%x, size %d u32s\n", 180 disable_ptr, array_size); 181 } 182 183} 184 185static int iwl3945_hwrate_to_plcp_idx(u8 plcp) 186{ 187 int idx; 188 189 for (idx = 0; idx < IWL_RATE_COUNT_3945; idx++) 190 if (iwl3945_rates[idx].plcp == plcp) 191 return idx; 192 return -1; 193} 194 195#ifdef CONFIG_IWLWIFI_DEBUG 196#define TX_STATUS_ENTRY(x) case TX_3945_STATUS_FAIL_ ## x: return #x 197 198static const char *iwl3945_get_tx_fail_reason(u32 status) 199{ 200 switch (status & TX_STATUS_MSK) { 201 case TX_3945_STATUS_SUCCESS: 202 return "SUCCESS"; 203 TX_STATUS_ENTRY(SHORT_LIMIT); 204 TX_STATUS_ENTRY(LONG_LIMIT); 205 TX_STATUS_ENTRY(FIFO_UNDERRUN); 206 TX_STATUS_ENTRY(MGMNT_ABORT); 207 TX_STATUS_ENTRY(NEXT_FRAG); 208 TX_STATUS_ENTRY(LIFE_EXPIRE); 209 TX_STATUS_ENTRY(DEST_PS); 210 TX_STATUS_ENTRY(ABORTED); 211 TX_STATUS_ENTRY(BT_RETRY); 212 TX_STATUS_ENTRY(STA_INVALID); 213 TX_STATUS_ENTRY(FRAG_DROPPED); 214 TX_STATUS_ENTRY(TID_DISABLE); 215 TX_STATUS_ENTRY(FRAME_FLUSHED); 216 TX_STATUS_ENTRY(INSUFFICIENT_CF_POLL); 217 TX_STATUS_ENTRY(TX_LOCKED); 218 TX_STATUS_ENTRY(NO_BEACON_ON_RADAR); 219 } 220 221 return "UNKNOWN"; 222} 223#else 224static inline const char *iwl3945_get_tx_fail_reason(u32 status) 225{ 226 return ""; 227} 228#endif 229 230/* 231 * get ieee prev rate from rate scale table. 232 * for A and B mode we need to overright prev 233 * value 234 */ 235int iwl3945_rs_next_rate(struct iwl_priv *priv, int rate) 236{ 237 int next_rate = iwl3945_get_prev_ieee_rate(rate); 238 239 switch (priv->band) { 240 case IEEE80211_BAND_5GHZ: 241 if (rate == IWL_RATE_12M_INDEX) 242 next_rate = IWL_RATE_9M_INDEX; 243 else if (rate == IWL_RATE_6M_INDEX) 244 next_rate = IWL_RATE_6M_INDEX; 245 break; 246 case IEEE80211_BAND_2GHZ: 247 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) && 248 iwl_is_associated(priv)) { 249 if (rate == IWL_RATE_11M_INDEX) 250 next_rate = IWL_RATE_5M_INDEX; 251 } 252 break; 253 254 default: 255 break; 256 } 257 258 return next_rate; 259} 260 261 262/** 263 * iwl3945_tx_queue_reclaim - Reclaim Tx queue entries already Tx'd 264 * 265 * When FW advances 'R' index, all entries between old and new 'R' index 266 * need to be reclaimed. As result, some free space forms. If there is 267 * enough free space (> low mark), wake the stack that feeds us. 268 */ 269static void iwl3945_tx_queue_reclaim(struct iwl_priv *priv, 270 int txq_id, int index) 271{ 272 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 273 struct iwl_queue *q = &txq->q; 274 struct iwl_tx_info *tx_info; 275 276 BUG_ON(txq_id == IWL_CMD_QUEUE_NUM); 277 278 for (index = iwl_queue_inc_wrap(index, q->n_bd); q->read_ptr != index; 279 q->read_ptr = iwl_queue_inc_wrap(q->read_ptr, q->n_bd)) { 280 281 tx_info = &txq->txb[txq->q.read_ptr]; 282 ieee80211_tx_status_irqsafe(priv->hw, tx_info->skb); 283 tx_info->skb = NULL; 284 priv->cfg->ops->lib->txq_free_tfd(priv, txq); 285 } 286 287 if (iwl_queue_space(q) > q->low_mark && (txq_id >= 0) && 288 (txq_id != IWL_CMD_QUEUE_NUM) && 289 priv->mac80211_registered) 290 iwl_wake_queue(priv, txq_id); 291} 292 293/** 294 * iwl3945_rx_reply_tx - Handle Tx response 295 */ 296static void iwl3945_rx_reply_tx(struct iwl_priv *priv, 297 struct iwl_rx_mem_buffer *rxb) 298{ 299 struct iwl_rx_packet *pkt = rxb_addr(rxb); 300 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 301 int txq_id = SEQ_TO_QUEUE(sequence); 302 int index = SEQ_TO_INDEX(sequence); 303 struct iwl_tx_queue *txq = &priv->txq[txq_id]; 304 struct ieee80211_tx_info *info; 305 struct iwl3945_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 306 u32 status = le32_to_cpu(tx_resp->status); 307 int rate_idx; 308 int fail; 309 310 if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) { 311 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d " 312 "is out of range [0-%d] %d %d\n", txq_id, 313 index, txq->q.n_bd, txq->q.write_ptr, 314 txq->q.read_ptr); 315 return; 316 } 317 318 info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb); 319 ieee80211_tx_info_clear_status(info); 320 321 /* Fill the MRR chain with some info about on-chip retransmissions */ 322 rate_idx = iwl3945_hwrate_to_plcp_idx(tx_resp->rate); 323 if (info->band == IEEE80211_BAND_5GHZ) 324 rate_idx -= IWL_FIRST_OFDM_RATE; 325 326 fail = tx_resp->failure_frame; 327 328 info->status.rates[0].idx = rate_idx; 329 info->status.rates[0].count = fail + 1; /* add final attempt */ 330 331 /* tx_status->rts_retry_count = tx_resp->failure_rts; */ 332 info->flags |= ((status & TX_STATUS_MSK) == TX_STATUS_SUCCESS) ? 333 IEEE80211_TX_STAT_ACK : 0; 334 335 IWL_DEBUG_TX(priv, "Tx queue %d Status %s (0x%08x) plcp rate %d retries %d\n", 336 txq_id, iwl3945_get_tx_fail_reason(status), status, 337 tx_resp->rate, tx_resp->failure_frame); 338 339 IWL_DEBUG_TX_REPLY(priv, "Tx queue reclaim %d\n", index); 340 iwl3945_tx_queue_reclaim(priv, txq_id, index); 341 342 if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK)) 343 IWL_ERR(priv, "TODO: Implement Tx ABORT REQUIRED!!!\n"); 344} 345 346 347 348/***************************************************************************** 349 * 350 * Intel PRO/Wireless 3945ABG/BG Network Connection 351 * 352 * RX handler implementations 353 * 354 *****************************************************************************/ 355#ifdef CONFIG_IWLWIFI_DEBUGFS 356static void iwl3945_accumulative_statistics(struct iwl_priv *priv, 357 __le32 *stats) 358{ 359 int i; 360 __le32 *prev_stats; 361 u32 *accum_stats; 362 u32 *delta, *max_delta; 363 364 prev_stats = (__le32 *)&priv->_3945.statistics; 365 accum_stats = (u32 *)&priv->_3945.accum_statistics; 366 delta = (u32 *)&priv->_3945.delta_statistics; 367 max_delta = (u32 *)&priv->_3945.max_delta; 368 369 for (i = sizeof(__le32); i < sizeof(struct iwl3945_notif_statistics); 370 i += sizeof(__le32), stats++, prev_stats++, delta++, 371 max_delta++, accum_stats++) { 372 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) { 373 *delta = (le32_to_cpu(*stats) - 374 le32_to_cpu(*prev_stats)); 375 *accum_stats += *delta; 376 if (*delta > *max_delta) 377 *max_delta = *delta; 378 } 379 } 380 381 /* reset accumulative statistics for "no-counter" type statistics */ 382 priv->_3945.accum_statistics.general.temperature = 383 priv->_3945.statistics.general.temperature; 384 priv->_3945.accum_statistics.general.ttl_timestamp = 385 priv->_3945.statistics.general.ttl_timestamp; 386} 387#endif 388 389/** 390 * iwl3945_good_plcp_health - checks for plcp error. 391 * 392 * When the plcp error is exceeding the thresholds, reset the radio 393 * to improve the throughput. 394 */ 395static bool iwl3945_good_plcp_health(struct iwl_priv *priv, 396 struct iwl_rx_packet *pkt) 397{ 398 bool rc = true; 399 struct iwl3945_notif_statistics current_stat; 400 int combined_plcp_delta; 401 unsigned int plcp_msec; 402 unsigned long plcp_received_jiffies; 403 404 if (priv->cfg->plcp_delta_threshold == 405 IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE) { 406 IWL_DEBUG_RADIO(priv, "plcp_err check disabled\n"); 407 return rc; 408 } 409 memcpy(¤t_stat, pkt->u.raw, sizeof(struct 410 iwl3945_notif_statistics)); 411 /* 412 * check for plcp_err and trigger radio reset if it exceeds 413 * the plcp error threshold plcp_delta. 414 */ 415 plcp_received_jiffies = jiffies; 416 plcp_msec = jiffies_to_msecs((long) plcp_received_jiffies - 417 (long) priv->plcp_jiffies); 418 priv->plcp_jiffies = plcp_received_jiffies; 419 /* 420 * check to make sure plcp_msec is not 0 to prevent division 421 * by zero. 422 */ 423 if (plcp_msec) { 424 combined_plcp_delta = 425 (le32_to_cpu(current_stat.rx.ofdm.plcp_err) - 426 le32_to_cpu(priv->_3945.statistics.rx.ofdm.plcp_err)); 427 428 if ((combined_plcp_delta > 0) && 429 ((combined_plcp_delta * 100) / plcp_msec) > 430 priv->cfg->plcp_delta_threshold) { 431 /* 432 * if plcp_err exceed the threshold, the following 433 * data is printed in csv format: 434 * Text: plcp_err exceeded %d, 435 * Received ofdm.plcp_err, 436 * Current ofdm.plcp_err, 437 * combined_plcp_delta, 438 * plcp_msec 439 */ 440 IWL_DEBUG_RADIO(priv, "plcp_err exceeded %u, " 441 "%u, %d, %u mSecs\n", 442 priv->cfg->plcp_delta_threshold, 443 le32_to_cpu(current_stat.rx.ofdm.plcp_err), 444 combined_plcp_delta, plcp_msec); 445 /* 446 * Reset the RF radio due to the high plcp 447 * error rate 448 */ 449 rc = false; 450 } 451 } 452 return rc; 453} 454 455void iwl3945_hw_rx_statistics(struct iwl_priv *priv, 456 struct iwl_rx_mem_buffer *rxb) 457{ 458 struct iwl_rx_packet *pkt = rxb_addr(rxb); 459 460 IWL_DEBUG_RX(priv, "Statistics notification received (%d vs %d).\n", 461 (int)sizeof(struct iwl3945_notif_statistics), 462 le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK); 463#ifdef CONFIG_IWLWIFI_DEBUGFS 464 iwl3945_accumulative_statistics(priv, (__le32 *)&pkt->u.raw); 465#endif 466 iwl_recover_from_statistics(priv, pkt); 467 468 memcpy(&priv->_3945.statistics, pkt->u.raw, sizeof(priv->_3945.statistics)); 469} 470 471void iwl3945_reply_statistics(struct iwl_priv *priv, 472 struct iwl_rx_mem_buffer *rxb) 473{ 474 struct iwl_rx_packet *pkt = rxb_addr(rxb); 475 __le32 *flag = (__le32 *)&pkt->u.raw; 476 477 if (le32_to_cpu(*flag) & UCODE_STATISTICS_CLEAR_MSK) { 478#ifdef CONFIG_IWLWIFI_DEBUGFS 479 memset(&priv->_3945.accum_statistics, 0, 480 sizeof(struct iwl3945_notif_statistics)); 481 memset(&priv->_3945.delta_statistics, 0, 482 sizeof(struct iwl3945_notif_statistics)); 483 memset(&priv->_3945.max_delta, 0, 484 sizeof(struct iwl3945_notif_statistics)); 485#endif 486 IWL_DEBUG_RX(priv, "Statistics have been cleared\n"); 487 } 488 iwl3945_hw_rx_statistics(priv, rxb); 489} 490 491 492/****************************************************************************** 493 * 494 * Misc. internal state and helper functions 495 * 496 ******************************************************************************/ 497 498/* This is necessary only for a number of statistics, see the caller. */ 499static int iwl3945_is_network_packet(struct iwl_priv *priv, 500 struct ieee80211_hdr *header) 501{ 502 /* Filter incoming packets to determine if they are targeted toward 503 * this network, discarding packets coming from ourselves */ 504 switch (priv->iw_mode) { 505 case NL80211_IFTYPE_ADHOC: /* Header: Dest. | Source | BSSID */ 506 /* packets to our IBSS update information */ 507 return !compare_ether_addr(header->addr3, priv->bssid); 508 case NL80211_IFTYPE_STATION: /* Header: Dest. | AP{BSSID} | Source */ 509 /* packets to our IBSS update information */ 510 return !compare_ether_addr(header->addr2, priv->bssid); 511 default: 512 return 1; 513 } 514} 515 516static void iwl3945_pass_packet_to_mac80211(struct iwl_priv *priv, 517 struct iwl_rx_mem_buffer *rxb, 518 struct ieee80211_rx_status *stats) 519{ 520 struct iwl_rx_packet *pkt = rxb_addr(rxb); 521 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)IWL_RX_DATA(pkt); 522 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt); 523 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt); 524 u16 len = le16_to_cpu(rx_hdr->len); 525 struct sk_buff *skb; 526 __le16 fc = hdr->frame_control; 527 528 /* We received data from the HW, so stop the watchdog */ 529 if (unlikely(len + IWL39_RX_FRAME_SIZE > 530 PAGE_SIZE << priv->hw_params.rx_page_order)) { 531 IWL_DEBUG_DROP(priv, "Corruption detected!\n"); 532 return; 533 } 534 535 /* We only process data packets if the interface is open */ 536 if (unlikely(!priv->is_open)) { 537 IWL_DEBUG_DROP_LIMIT(priv, 538 "Dropping packet while interface is not open.\n"); 539 return; 540 } 541 542 skb = dev_alloc_skb(128); 543 if (!skb) { 544 IWL_ERR(priv, "dev_alloc_skb failed\n"); 545 return; 546 } 547 548 if (!iwl3945_mod_params.sw_crypto) 549 iwl_set_decrypted_flag(priv, 550 (struct ieee80211_hdr *)rxb_addr(rxb), 551 le32_to_cpu(rx_end->status), stats); 552 553 skb_add_rx_frag(skb, 0, rxb->page, 554 (void *)rx_hdr->payload - (void *)pkt, len); 555 556 iwl_update_stats(priv, false, fc, len); 557 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats)); 558 559 ieee80211_rx(priv->hw, skb); 560 priv->alloc_rxb_page--; 561 rxb->page = NULL; 562} 563 564#define IWL_DELAY_NEXT_SCAN_AFTER_ASSOC (HZ*6) 565 566static void iwl3945_rx_reply_rx(struct iwl_priv *priv, 567 struct iwl_rx_mem_buffer *rxb) 568{ 569 struct ieee80211_hdr *header; 570 struct ieee80211_rx_status rx_status; 571 struct iwl_rx_packet *pkt = rxb_addr(rxb); 572 struct iwl3945_rx_frame_stats *rx_stats = IWL_RX_STATS(pkt); 573 struct iwl3945_rx_frame_hdr *rx_hdr = IWL_RX_HDR(pkt); 574 struct iwl3945_rx_frame_end *rx_end = IWL_RX_END(pkt); 575 u16 rx_stats_sig_avg __maybe_unused = le16_to_cpu(rx_stats->sig_avg); 576 u16 rx_stats_noise_diff __maybe_unused = le16_to_cpu(rx_stats->noise_diff); 577 u8 network_packet; 578 579 rx_status.flag = 0; 580 rx_status.mactime = le64_to_cpu(rx_end->timestamp); 581 rx_status.freq = 582 ieee80211_channel_to_frequency(le16_to_cpu(rx_hdr->channel)); 583 rx_status.band = (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? 584 IEEE80211_BAND_2GHZ : IEEE80211_BAND_5GHZ; 585 586 rx_status.rate_idx = iwl3945_hwrate_to_plcp_idx(rx_hdr->rate); 587 if (rx_status.band == IEEE80211_BAND_5GHZ) 588 rx_status.rate_idx -= IWL_FIRST_OFDM_RATE; 589 590 rx_status.antenna = (le16_to_cpu(rx_hdr->phy_flags) & 591 RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 4; 592 593 /* set the preamble flag if appropriate */ 594 if (rx_hdr->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) 595 rx_status.flag |= RX_FLAG_SHORTPRE; 596 597 if ((unlikely(rx_stats->phy_count > 20))) { 598 IWL_DEBUG_DROP(priv, "dsp size out of range [0,20]: %d/n", 599 rx_stats->phy_count); 600 return; 601 } 602 603 if (!(rx_end->status & RX_RES_STATUS_NO_CRC32_ERROR) 604 || !(rx_end->status & RX_RES_STATUS_NO_RXE_OVERFLOW)) { 605 IWL_DEBUG_RX(priv, "Bad CRC or FIFO: 0x%08X.\n", rx_end->status); 606 return; 607 } 608 609 610 611 /* Convert 3945's rssi indicator to dBm */ 612 rx_status.signal = rx_stats->rssi - IWL39_RSSI_OFFSET; 613 614 IWL_DEBUG_STATS(priv, "Rssi %d sig_avg %d noise_diff %d\n", 615 rx_status.signal, rx_stats_sig_avg, 616 rx_stats_noise_diff); 617 618 header = (struct ieee80211_hdr *)IWL_RX_DATA(pkt); 619 620 network_packet = iwl3945_is_network_packet(priv, header); 621 622 IWL_DEBUG_STATS_LIMIT(priv, "[%c] %d RSSI:%d Signal:%u, Rate:%u\n", 623 network_packet ? '*' : ' ', 624 le16_to_cpu(rx_hdr->channel), 625 rx_status.signal, rx_status.signal, 626 rx_status.rate_idx); 627 628 iwl_dbg_log_rx_data_frame(priv, le16_to_cpu(rx_hdr->len), header); 629 630 if (network_packet) { 631 priv->_3945.last_beacon_time = 632 le32_to_cpu(rx_end->beacon_timestamp); 633 priv->_3945.last_tsf = le64_to_cpu(rx_end->timestamp); 634 priv->_3945.last_rx_rssi = rx_status.signal; 635 } 636 637 iwl3945_pass_packet_to_mac80211(priv, rxb, &rx_status); 638} 639 640int iwl3945_hw_txq_attach_buf_to_tfd(struct iwl_priv *priv, 641 struct iwl_tx_queue *txq, 642 dma_addr_t addr, u16 len, u8 reset, u8 pad) 643{ 644 int count; 645 struct iwl_queue *q; 646 struct iwl3945_tfd *tfd, *tfd_tmp; 647 648 q = &txq->q; 649 tfd_tmp = (struct iwl3945_tfd *)txq->tfds; 650 tfd = &tfd_tmp[q->write_ptr]; 651 652 if (reset) 653 memset(tfd, 0, sizeof(*tfd)); 654 655 count = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags)); 656 657 if ((count >= NUM_TFD_CHUNKS) || (count < 0)) { 658 IWL_ERR(priv, "Error can not send more than %d chunks\n", 659 NUM_TFD_CHUNKS); 660 return -EINVAL; 661 } 662 663 tfd->tbs[count].addr = cpu_to_le32(addr); 664 tfd->tbs[count].len = cpu_to_le32(len); 665 666 count++; 667 668 tfd->control_flags = cpu_to_le32(TFD_CTL_COUNT_SET(count) | 669 TFD_CTL_PAD_SET(pad)); 670 671 return 0; 672} 673 674/** 675 * iwl3945_hw_txq_free_tfd - Free one TFD, those at index [txq->q.read_ptr] 676 * 677 * Does NOT advance any indexes 678 */ 679void iwl3945_hw_txq_free_tfd(struct iwl_priv *priv, struct iwl_tx_queue *txq) 680{ 681 struct iwl3945_tfd *tfd_tmp = (struct iwl3945_tfd *)txq->tfds; 682 int index = txq->q.read_ptr; 683 struct iwl3945_tfd *tfd = &tfd_tmp[index]; 684 struct pci_dev *dev = priv->pci_dev; 685 int i; 686 int counter; 687 688 /* sanity check */ 689 counter = TFD_CTL_COUNT_GET(le32_to_cpu(tfd->control_flags)); 690 if (counter > NUM_TFD_CHUNKS) { 691 IWL_ERR(priv, "Too many chunks: %i\n", counter); 692 /* @todo issue fatal error, it is quite serious situation */ 693 return; 694 } 695 696 /* Unmap tx_cmd */ 697 if (counter) 698 pci_unmap_single(dev, 699 dma_unmap_addr(&txq->meta[index], mapping), 700 dma_unmap_len(&txq->meta[index], len), 701 PCI_DMA_TODEVICE); 702 703 /* unmap chunks if any */ 704 705 for (i = 1; i < counter; i++) 706 pci_unmap_single(dev, le32_to_cpu(tfd->tbs[i].addr), 707 le32_to_cpu(tfd->tbs[i].len), PCI_DMA_TODEVICE); 708 709 /* free SKB */ 710 if (txq->txb) { 711 struct sk_buff *skb; 712 713 skb = txq->txb[txq->q.read_ptr].skb; 714 715 /* can be called from irqs-disabled context */ 716 if (skb) { 717 dev_kfree_skb_any(skb); 718 txq->txb[txq->q.read_ptr].skb = NULL; 719 } 720 } 721} 722 723/** 724 * iwl3945_hw_build_tx_cmd_rate - Add rate portion to TX_CMD: 725 * 726*/ 727void iwl3945_hw_build_tx_cmd_rate(struct iwl_priv *priv, 728 struct iwl_device_cmd *cmd, 729 struct ieee80211_tx_info *info, 730 struct ieee80211_hdr *hdr, 731 int sta_id, int tx_id) 732{ 733 u16 hw_value = ieee80211_get_tx_rate(priv->hw, info)->hw_value; 734 u16 rate_index = min(hw_value & 0xffff, IWL_RATE_COUNT_3945); 735 u16 rate_mask; 736 int rate; 737 u8 rts_retry_limit; 738 u8 data_retry_limit; 739 __le32 tx_flags; 740 __le16 fc = hdr->frame_control; 741 struct iwl3945_tx_cmd *tx_cmd = (struct iwl3945_tx_cmd *)cmd->cmd.payload; 742 743 rate = iwl3945_rates[rate_index].plcp; 744 tx_flags = tx_cmd->tx_flags; 745 746 /* We need to figure out how to get the sta->supp_rates while 747 * in this running context */ 748 rate_mask = IWL_RATES_MASK; 749 750 751 /* Set retry limit on DATA packets and Probe Responses*/ 752 if (ieee80211_is_probe_resp(fc)) 753 data_retry_limit = 3; 754 else 755 data_retry_limit = IWL_DEFAULT_TX_RETRY; 756 tx_cmd->data_retry_limit = data_retry_limit; 757 758 if (tx_id >= IWL_CMD_QUEUE_NUM) 759 rts_retry_limit = 3; 760 else 761 rts_retry_limit = 7; 762 763 if (data_retry_limit < rts_retry_limit) 764 rts_retry_limit = data_retry_limit; 765 tx_cmd->rts_retry_limit = rts_retry_limit; 766 767 tx_cmd->rate = rate; 768 tx_cmd->tx_flags = tx_flags; 769 770 /* OFDM */ 771 tx_cmd->supp_rates[0] = 772 ((rate_mask & IWL_OFDM_RATES_MASK) >> IWL_FIRST_OFDM_RATE) & 0xFF; 773 774 /* CCK */ 775 tx_cmd->supp_rates[1] = (rate_mask & 0xF); 776 777 IWL_DEBUG_RATE(priv, "Tx sta id: %d, rate: %d (plcp), flags: 0x%4X " 778 "cck/ofdm mask: 0x%x/0x%x\n", sta_id, 779 tx_cmd->rate, le32_to_cpu(tx_cmd->tx_flags), 780 tx_cmd->supp_rates[1], tx_cmd->supp_rates[0]); 781} 782 783static u8 iwl3945_sync_sta(struct iwl_priv *priv, int sta_id, u16 tx_rate) 784{ 785 unsigned long flags_spin; 786 struct iwl_station_entry *station; 787 788 if (sta_id == IWL_INVALID_STATION) 789 return IWL_INVALID_STATION; 790 791 spin_lock_irqsave(&priv->sta_lock, flags_spin); 792 station = &priv->stations[sta_id]; 793 794 station->sta.sta.modify_mask = STA_MODIFY_TX_RATE_MSK; 795 station->sta.rate_n_flags = cpu_to_le16(tx_rate); 796 station->sta.mode = STA_CONTROL_MODIFY_MSK; 797 iwl_send_add_sta(priv, &station->sta, CMD_ASYNC); 798 spin_unlock_irqrestore(&priv->sta_lock, flags_spin); 799 800 IWL_DEBUG_RATE(priv, "SCALE sync station %d to rate %d\n", 801 sta_id, tx_rate); 802 return sta_id; 803} 804 805static int iwl3945_set_pwr_src(struct iwl_priv *priv, enum iwl_pwr_src src) 806{ 807 if (src == IWL_PWR_SRC_VAUX) { 808 if (pci_pme_capable(priv->pci_dev, PCI_D3cold)) { 809 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 810 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 811 ~APMG_PS_CTRL_MSK_PWR_SRC); 812 813 iwl_poll_bit(priv, CSR_GPIO_IN, 814 CSR_GPIO_IN_VAL_VAUX_PWR_SRC, 815 CSR_GPIO_IN_BIT_AUX_POWER, 5000); 816 } 817 } else { 818 iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG, 819 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 820 ~APMG_PS_CTRL_MSK_PWR_SRC); 821 822 iwl_poll_bit(priv, CSR_GPIO_IN, CSR_GPIO_IN_VAL_VMAIN_PWR_SRC, 823 CSR_GPIO_IN_BIT_AUX_POWER, 5000); /* uS */ 824 } 825 826 return 0; 827} 828 829static int iwl3945_rx_init(struct iwl_priv *priv, struct iwl_rx_queue *rxq) 830{ 831 iwl_write_direct32(priv, FH39_RCSR_RBD_BASE(0), rxq->bd_dma); 832 iwl_write_direct32(priv, FH39_RCSR_RPTR_ADDR(0), rxq->rb_stts_dma); 833 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), 0); 834 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 835 FH39_RCSR_RX_CONFIG_REG_VAL_DMA_CHNL_EN_ENABLE | 836 FH39_RCSR_RX_CONFIG_REG_VAL_RDRBD_EN_ENABLE | 837 FH39_RCSR_RX_CONFIG_REG_BIT_WR_STTS_EN | 838 FH39_RCSR_RX_CONFIG_REG_VAL_MAX_FRAG_SIZE_128 | 839 (RX_QUEUE_SIZE_LOG << FH39_RCSR_RX_CONFIG_REG_POS_RBDC_SIZE) | 840 FH39_RCSR_RX_CONFIG_REG_VAL_IRQ_DEST_INT_HOST | 841 (1 << FH39_RCSR_RX_CONFIG_REG_POS_IRQ_RBTH) | 842 FH39_RCSR_RX_CONFIG_REG_VAL_MSG_MODE_FH); 843 844 /* fake read to flush all prev I/O */ 845 iwl_read_direct32(priv, FH39_RSSR_CTRL); 846 847 return 0; 848} 849 850static int iwl3945_tx_reset(struct iwl_priv *priv) 851{ 852 853 /* bypass mode */ 854 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0x2); 855 856 /* RA 0 is active */ 857 iwl_write_prph(priv, ALM_SCD_ARASTAT_REG, 0x01); 858 859 /* all 6 fifo are active */ 860 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0x3f); 861 862 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_1_REG, 0x010000); 863 iwl_write_prph(priv, ALM_SCD_SBYP_MODE_2_REG, 0x030002); 864 iwl_write_prph(priv, ALM_SCD_TXF4MF_REG, 0x000004); 865 iwl_write_prph(priv, ALM_SCD_TXF5MF_REG, 0x000005); 866 867 iwl_write_direct32(priv, FH39_TSSR_CBB_BASE, 868 priv->_3945.shared_phys); 869 870 iwl_write_direct32(priv, FH39_TSSR_MSG_CONFIG, 871 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TXPD_ON | 872 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_TXPD_ON | 873 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_MAX_FRAG_SIZE_128B | 874 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_SNOOP_RD_TFD_ON | 875 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RD_CBB_ON | 876 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_ORDER_RSP_WAIT_TH | 877 FH39_TSSR_TX_MSG_CONFIG_REG_VAL_RSP_WAIT_TH); 878 879 880 return 0; 881} 882 883/** 884 * iwl3945_txq_ctx_reset - Reset TX queue context 885 * 886 * Destroys all DMA structures and initialize them again 887 */ 888static int iwl3945_txq_ctx_reset(struct iwl_priv *priv) 889{ 890 int rc; 891 int txq_id, slots_num; 892 893 iwl3945_hw_txq_ctx_free(priv); 894 895 /* allocate tx queue structure */ 896 rc = iwl_alloc_txq_mem(priv); 897 if (rc) 898 return rc; 899 900 /* Tx CMD queue */ 901 rc = iwl3945_tx_reset(priv); 902 if (rc) 903 goto error; 904 905 /* Tx queue(s) */ 906 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { 907 slots_num = (txq_id == IWL_CMD_QUEUE_NUM) ? 908 TFD_CMD_SLOTS : TFD_TX_CMD_SLOTS; 909 rc = iwl_tx_queue_init(priv, &priv->txq[txq_id], slots_num, 910 txq_id); 911 if (rc) { 912 IWL_ERR(priv, "Tx %d queue init failed\n", txq_id); 913 goto error; 914 } 915 } 916 917 return rc; 918 919 error: 920 iwl3945_hw_txq_ctx_free(priv); 921 return rc; 922} 923 924 925/* 926 * Start up 3945's basic functionality after it has been reset 927 * (e.g. after platform boot, or shutdown via iwl_apm_stop()) 928 * NOTE: This does not load uCode nor start the embedded processor 929 */ 930static int iwl3945_apm_init(struct iwl_priv *priv) 931{ 932 int ret = iwl_apm_init(priv); 933 934 /* Clear APMG (NIC's internal power management) interrupts */ 935 iwl_write_prph(priv, APMG_RTC_INT_MSK_REG, 0x0); 936 iwl_write_prph(priv, APMG_RTC_INT_STT_REG, 0xFFFFFFFF); 937 938 /* Reset radio chip */ 939 iwl_set_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ); 940 udelay(5); 941 iwl_clear_bits_prph(priv, APMG_PS_CTRL_REG, APMG_PS_CTRL_VAL_RESET_REQ); 942 943 return ret; 944} 945 946static void iwl3945_nic_config(struct iwl_priv *priv) 947{ 948 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; 949 unsigned long flags; 950 u8 rev_id = 0; 951 952 spin_lock_irqsave(&priv->lock, flags); 953 954 /* Determine HW type */ 955 pci_read_config_byte(priv->pci_dev, PCI_REVISION_ID, &rev_id); 956 957 IWL_DEBUG_INFO(priv, "HW Revision ID = 0x%X\n", rev_id); 958 959 if (rev_id & PCI_CFG_REV_ID_BIT_RTP) 960 IWL_DEBUG_INFO(priv, "RTP type\n"); 961 else if (rev_id & PCI_CFG_REV_ID_BIT_BASIC_SKU) { 962 IWL_DEBUG_INFO(priv, "3945 RADIO-MB type\n"); 963 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 964 CSR39_HW_IF_CONFIG_REG_BIT_3945_MB); 965 } else { 966 IWL_DEBUG_INFO(priv, "3945 RADIO-MM type\n"); 967 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 968 CSR39_HW_IF_CONFIG_REG_BIT_3945_MM); 969 } 970 971 if (EEPROM_SKU_CAP_OP_MODE_MRC == eeprom->sku_cap) { 972 IWL_DEBUG_INFO(priv, "SKU OP mode is mrc\n"); 973 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 974 CSR39_HW_IF_CONFIG_REG_BIT_SKU_MRC); 975 } else 976 IWL_DEBUG_INFO(priv, "SKU OP mode is basic\n"); 977 978 if ((eeprom->board_revision & 0xF0) == 0xD0) { 979 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n", 980 eeprom->board_revision); 981 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 982 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); 983 } else { 984 IWL_DEBUG_INFO(priv, "3945ABG revision is 0x%X\n", 985 eeprom->board_revision); 986 iwl_clear_bit(priv, CSR_HW_IF_CONFIG_REG, 987 CSR39_HW_IF_CONFIG_REG_BIT_BOARD_TYPE); 988 } 989 990 if (eeprom->almgor_m_version <= 1) { 991 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 992 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_A); 993 IWL_DEBUG_INFO(priv, "Card M type A version is 0x%X\n", 994 eeprom->almgor_m_version); 995 } else { 996 IWL_DEBUG_INFO(priv, "Card M type B version is 0x%X\n", 997 eeprom->almgor_m_version); 998 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG, 999 CSR39_HW_IF_CONFIG_REG_BITS_SILICON_TYPE_B); 1000 } 1001 spin_unlock_irqrestore(&priv->lock, flags); 1002 1003 if (eeprom->sku_cap & EEPROM_SKU_CAP_SW_RF_KILL_ENABLE) 1004 IWL_DEBUG_RF_KILL(priv, "SW RF KILL supported in EEPROM.\n"); 1005 1006 if (eeprom->sku_cap & EEPROM_SKU_CAP_HW_RF_KILL_ENABLE) 1007 IWL_DEBUG_RF_KILL(priv, "HW RF KILL supported in EEPROM.\n"); 1008} 1009 1010int iwl3945_hw_nic_init(struct iwl_priv *priv) 1011{ 1012 int rc; 1013 unsigned long flags; 1014 struct iwl_rx_queue *rxq = &priv->rxq; 1015 1016 spin_lock_irqsave(&priv->lock, flags); 1017 priv->cfg->ops->lib->apm_ops.init(priv); 1018 spin_unlock_irqrestore(&priv->lock, flags); 1019 1020 rc = priv->cfg->ops->lib->apm_ops.set_pwr_src(priv, IWL_PWR_SRC_VMAIN); 1021 if (rc) 1022 return rc; 1023 1024 priv->cfg->ops->lib->apm_ops.config(priv); 1025 1026 /* Allocate the RX queue, or reset if it is already allocated */ 1027 if (!rxq->bd) { 1028 rc = iwl_rx_queue_alloc(priv); 1029 if (rc) { 1030 IWL_ERR(priv, "Unable to initialize Rx queue\n"); 1031 return -ENOMEM; 1032 } 1033 } else 1034 iwl3945_rx_queue_reset(priv, rxq); 1035 1036 iwl3945_rx_replenish(priv); 1037 1038 iwl3945_rx_init(priv, rxq); 1039 1040 1041 /* Look at using this instead: 1042 rxq->need_update = 1; 1043 iwl_rx_queue_update_write_ptr(priv, rxq); 1044 */ 1045 1046 iwl_write_direct32(priv, FH39_RCSR_WPTR(0), rxq->write & ~7); 1047 1048 rc = iwl3945_txq_ctx_reset(priv); 1049 if (rc) 1050 return rc; 1051 1052 set_bit(STATUS_INIT, &priv->status); 1053 1054 return 0; 1055} 1056 1057/** 1058 * iwl3945_hw_txq_ctx_free - Free TXQ Context 1059 * 1060 * Destroy all TX DMA queues and structures 1061 */ 1062void iwl3945_hw_txq_ctx_free(struct iwl_priv *priv) 1063{ 1064 int txq_id; 1065 1066 /* Tx queues */ 1067 if (priv->txq) 1068 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; 1069 txq_id++) 1070 if (txq_id == IWL_CMD_QUEUE_NUM) 1071 iwl_cmd_queue_free(priv); 1072 else 1073 iwl_tx_queue_free(priv, txq_id); 1074 1075 /* free tx queue structure */ 1076 iwl_free_txq_mem(priv); 1077} 1078 1079void iwl3945_hw_txq_ctx_stop(struct iwl_priv *priv) 1080{ 1081 int txq_id; 1082 1083 /* stop SCD */ 1084 iwl_write_prph(priv, ALM_SCD_MODE_REG, 0); 1085 iwl_write_prph(priv, ALM_SCD_TXFACT_REG, 0); 1086 1087 /* reset TFD queues */ 1088 for (txq_id = 0; txq_id < priv->hw_params.max_txq_num; txq_id++) { 1089 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 0x0); 1090 iwl_poll_direct_bit(priv, FH39_TSSR_TX_STATUS, 1091 FH39_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(txq_id), 1092 1000); 1093 } 1094 1095 iwl3945_hw_txq_ctx_free(priv); 1096} 1097 1098/** 1099 * iwl3945_hw_reg_adjust_power_by_temp 1100 * return index delta into power gain settings table 1101*/ 1102static int iwl3945_hw_reg_adjust_power_by_temp(int new_reading, int old_reading) 1103{ 1104 return (new_reading - old_reading) * (-11) / 100; 1105} 1106 1107/** 1108 * iwl3945_hw_reg_temp_out_of_range - Keep temperature in sane range 1109 */ 1110static inline int iwl3945_hw_reg_temp_out_of_range(int temperature) 1111{ 1112 return ((temperature < -260) || (temperature > 25)) ? 1 : 0; 1113} 1114 1115int iwl3945_hw_get_temperature(struct iwl_priv *priv) 1116{ 1117 return iwl_read32(priv, CSR_UCODE_DRV_GP2); 1118} 1119 1120/** 1121 * iwl3945_hw_reg_txpower_get_temperature 1122 * get the current temperature by reading from NIC 1123*/ 1124static int iwl3945_hw_reg_txpower_get_temperature(struct iwl_priv *priv) 1125{ 1126 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; 1127 int temperature; 1128 1129 temperature = iwl3945_hw_get_temperature(priv); 1130 1131 /* driver's okay range is -260 to +25. 1132 * human readable okay range is 0 to +285 */ 1133 IWL_DEBUG_INFO(priv, "Temperature: %d\n", temperature + IWL_TEMP_CONVERT); 1134 1135 /* handle insane temp reading */ 1136 if (iwl3945_hw_reg_temp_out_of_range(temperature)) { 1137 IWL_ERR(priv, "Error bad temperature value %d\n", temperature); 1138 1139 /* if really really hot(?), 1140 * substitute the 3rd band/group's temp measured at factory */ 1141 if (priv->last_temperature > 100) 1142 temperature = eeprom->groups[2].temperature; 1143 else /* else use most recent "sane" value from driver */ 1144 temperature = priv->last_temperature; 1145 } 1146 1147 return temperature; /* raw, not "human readable" */ 1148} 1149 1150/* Adjust Txpower only if temperature variance is greater than threshold. 1151 * 1152 * Both are lower than older versions' 9 degrees */ 1153#define IWL_TEMPERATURE_LIMIT_TIMER 6 1154 1155/** 1156 * is_temp_calib_needed - determines if new calibration is needed 1157 * 1158 * records new temperature in tx_mgr->temperature. 1159 * replaces tx_mgr->last_temperature *only* if calib needed 1160 * (assumes caller will actually do the calibration!). */ 1161static int is_temp_calib_needed(struct iwl_priv *priv) 1162{ 1163 int temp_diff; 1164 1165 priv->temperature = iwl3945_hw_reg_txpower_get_temperature(priv); 1166 temp_diff = priv->temperature - priv->last_temperature; 1167 1168 /* get absolute value */ 1169 if (temp_diff < 0) { 1170 IWL_DEBUG_POWER(priv, "Getting cooler, delta %d,\n", temp_diff); 1171 temp_diff = -temp_diff; 1172 } else if (temp_diff == 0) 1173 IWL_DEBUG_POWER(priv, "Same temp,\n"); 1174 else 1175 IWL_DEBUG_POWER(priv, "Getting warmer, delta %d,\n", temp_diff); 1176 1177 /* if we don't need calibration, *don't* update last_temperature */ 1178 if (temp_diff < IWL_TEMPERATURE_LIMIT_TIMER) { 1179 IWL_DEBUG_POWER(priv, "Timed thermal calib not needed\n"); 1180 return 0; 1181 } 1182 1183 IWL_DEBUG_POWER(priv, "Timed thermal calib needed\n"); 1184 1185 /* assume that caller will actually do calib ... 1186 * update the "last temperature" value */ 1187 priv->last_temperature = priv->temperature; 1188 return 1; 1189} 1190 1191#define IWL_MAX_GAIN_ENTRIES 78 1192#define IWL_CCK_FROM_OFDM_POWER_DIFF -5 1193#define IWL_CCK_FROM_OFDM_INDEX_DIFF (10) 1194 1195/* radio and DSP power table, each step is 1/2 dB. 1196 * 1st number is for RF analog gain, 2nd number is for DSP pre-DAC gain. */ 1197static struct iwl3945_tx_power power_gain_table[2][IWL_MAX_GAIN_ENTRIES] = { 1198 { 1199 {251, 127}, /* 2.4 GHz, highest power */ 1200 {251, 127}, 1201 {251, 127}, 1202 {251, 127}, 1203 {251, 125}, 1204 {251, 110}, 1205 {251, 105}, 1206 {251, 98}, 1207 {187, 125}, 1208 {187, 115}, 1209 {187, 108}, 1210 {187, 99}, 1211 {243, 119}, 1212 {243, 111}, 1213 {243, 105}, 1214 {243, 97}, 1215 {243, 92}, 1216 {211, 106}, 1217 {211, 100}, 1218 {179, 120}, 1219 {179, 113}, 1220 {179, 107}, 1221 {147, 125}, 1222 {147, 119}, 1223 {147, 112}, 1224 {147, 106}, 1225 {147, 101}, 1226 {147, 97}, 1227 {147, 91}, 1228 {115, 107}, 1229 {235, 121}, 1230 {235, 115}, 1231 {235, 109}, 1232 {203, 127}, 1233 {203, 121}, 1234 {203, 115}, 1235 {203, 108}, 1236 {203, 102}, 1237 {203, 96}, 1238 {203, 92}, 1239 {171, 110}, 1240 {171, 104}, 1241 {171, 98}, 1242 {139, 116}, 1243 {227, 125}, 1244 {227, 119}, 1245 {227, 113}, 1246 {227, 107}, 1247 {227, 101}, 1248 {227, 96}, 1249 {195, 113}, 1250 {195, 106}, 1251 {195, 102}, 1252 {195, 95}, 1253 {163, 113}, 1254 {163, 106}, 1255 {163, 102}, 1256 {163, 95}, 1257 {131, 113}, 1258 {131, 106}, 1259 {131, 102}, 1260 {131, 95}, 1261 {99, 113}, 1262 {99, 106}, 1263 {99, 102}, 1264 {99, 95}, 1265 {67, 113}, 1266 {67, 106}, 1267 {67, 102}, 1268 {67, 95}, 1269 {35, 113}, 1270 {35, 106}, 1271 {35, 102}, 1272 {35, 95}, 1273 {3, 113}, 1274 {3, 106}, 1275 {3, 102}, 1276 {3, 95} }, /* 2.4 GHz, lowest power */ 1277 { 1278 {251, 127}, /* 5.x GHz, highest power */ 1279 {251, 120}, 1280 {251, 114}, 1281 {219, 119}, 1282 {219, 101}, 1283 {187, 113}, 1284 {187, 102}, 1285 {155, 114}, 1286 {155, 103}, 1287 {123, 117}, 1288 {123, 107}, 1289 {123, 99}, 1290 {123, 92}, 1291 {91, 108}, 1292 {59, 125}, 1293 {59, 118}, 1294 {59, 109}, 1295 {59, 102}, 1296 {59, 96}, 1297 {59, 90}, 1298 {27, 104}, 1299 {27, 98}, 1300 {27, 92}, 1301 {115, 118}, 1302 {115, 111}, 1303 {115, 104}, 1304 {83, 126}, 1305 {83, 121}, 1306 {83, 113}, 1307 {83, 105}, 1308 {83, 99}, 1309 {51, 118}, 1310 {51, 111}, 1311 {51, 104}, 1312 {51, 98}, 1313 {19, 116}, 1314 {19, 109}, 1315 {19, 102}, 1316 {19, 98}, 1317 {19, 93}, 1318 {171, 113}, 1319 {171, 107}, 1320 {171, 99}, 1321 {139, 120}, 1322 {139, 113}, 1323 {139, 107}, 1324 {139, 99}, 1325 {107, 120}, 1326 {107, 113}, 1327 {107, 107}, 1328 {107, 99}, 1329 {75, 120}, 1330 {75, 113}, 1331 {75, 107}, 1332 {75, 99}, 1333 {43, 120}, 1334 {43, 113}, 1335 {43, 107}, 1336 {43, 99}, 1337 {11, 120}, 1338 {11, 113}, 1339 {11, 107}, 1340 {11, 99}, 1341 {131, 107}, 1342 {131, 99}, 1343 {99, 120}, 1344 {99, 113}, 1345 {99, 107}, 1346 {99, 99}, 1347 {67, 120}, 1348 {67, 113}, 1349 {67, 107}, 1350 {67, 99}, 1351 {35, 120}, 1352 {35, 113}, 1353 {35, 107}, 1354 {35, 99}, 1355 {3, 120} } /* 5.x GHz, lowest power */ 1356}; 1357 1358static inline u8 iwl3945_hw_reg_fix_power_index(int index) 1359{ 1360 if (index < 0) 1361 return 0; 1362 if (index >= IWL_MAX_GAIN_ENTRIES) 1363 return IWL_MAX_GAIN_ENTRIES - 1; 1364 return (u8) index; 1365} 1366 1367/* Kick off thermal recalibration check every 60 seconds */ 1368#define REG_RECALIB_PERIOD (60) 1369 1370/** 1371 * iwl3945_hw_reg_set_scan_power - Set Tx power for scan probe requests 1372 * 1373 * Set (in our channel info database) the direct scan Tx power for 1 Mbit (CCK) 1374 * or 6 Mbit (OFDM) rates. 1375 */ 1376static void iwl3945_hw_reg_set_scan_power(struct iwl_priv *priv, u32 scan_tbl_index, 1377 s32 rate_index, const s8 *clip_pwrs, 1378 struct iwl_channel_info *ch_info, 1379 int band_index) 1380{ 1381 struct iwl3945_scan_power_info *scan_power_info; 1382 s8 power; 1383 u8 power_index; 1384 1385 scan_power_info = &ch_info->scan_pwr_info[scan_tbl_index]; 1386 1387 /* use this channel group's 6Mbit clipping/saturation pwr, 1388 * but cap at regulatory scan power restriction (set during init 1389 * based on eeprom channel data) for this channel. */ 1390 power = min(ch_info->scan_power, clip_pwrs[IWL_RATE_6M_INDEX_TABLE]); 1391 1392 power = min(power, priv->tx_power_user_lmt); 1393 scan_power_info->requested_power = power; 1394 1395 /* find difference between new scan *power* and current "normal" 1396 * Tx *power* for 6Mb. Use this difference (x2) to adjust the 1397 * current "normal" temperature-compensated Tx power *index* for 1398 * this rate (1Mb or 6Mb) to yield new temp-compensated scan power 1399 * *index*. */ 1400 power_index = ch_info->power_info[rate_index].power_table_index 1401 - (power - ch_info->power_info 1402 [IWL_RATE_6M_INDEX_TABLE].requested_power) * 2; 1403 1404 /* store reference index that we use when adjusting *all* scan 1405 * powers. So we can accommodate user (all channel) or spectrum 1406 * management (single channel) power changes "between" temperature 1407 * feedback compensation procedures. 1408 * don't force fit this reference index into gain table; it may be a 1409 * negative number. This will help avoid errors when we're at 1410 * the lower bounds (highest gains, for warmest temperatures) 1411 * of the table. */ 1412 1413 /* don't exceed table bounds for "real" setting */ 1414 power_index = iwl3945_hw_reg_fix_power_index(power_index); 1415 1416 scan_power_info->power_table_index = power_index; 1417 scan_power_info->tpc.tx_gain = 1418 power_gain_table[band_index][power_index].tx_gain; 1419 scan_power_info->tpc.dsp_atten = 1420 power_gain_table[band_index][power_index].dsp_atten; 1421} 1422 1423/** 1424 * iwl3945_send_tx_power - fill in Tx Power command with gain settings 1425 * 1426 * Configures power settings for all rates for the current channel, 1427 * using values from channel info struct, and send to NIC 1428 */ 1429static int iwl3945_send_tx_power(struct iwl_priv *priv) 1430{ 1431 int rate_idx, i; 1432 const struct iwl_channel_info *ch_info = NULL; 1433 struct iwl3945_txpowertable_cmd txpower = { 1434 .channel = priv->active_rxon.channel, 1435 }; 1436 1437 txpower.band = (priv->band == IEEE80211_BAND_5GHZ) ? 0 : 1; 1438 ch_info = iwl_get_channel_info(priv, 1439 priv->band, 1440 le16_to_cpu(priv->active_rxon.channel)); 1441 if (!ch_info) { 1442 IWL_ERR(priv, 1443 "Failed to get channel info for channel %d [%d]\n", 1444 le16_to_cpu(priv->active_rxon.channel), priv->band); 1445 return -EINVAL; 1446 } 1447 1448 if (!is_channel_valid(ch_info)) { 1449 IWL_DEBUG_POWER(priv, "Not calling TX_PWR_TABLE_CMD on " 1450 "non-Tx channel.\n"); 1451 return 0; 1452 } 1453 1454 /* fill cmd with power settings for all rates for current channel */ 1455 /* Fill OFDM rate */ 1456 for (rate_idx = IWL_FIRST_OFDM_RATE, i = 0; 1457 rate_idx <= IWL39_LAST_OFDM_RATE; rate_idx++, i++) { 1458 1459 txpower.power[i].tpc = ch_info->power_info[i].tpc; 1460 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp; 1461 1462 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n", 1463 le16_to_cpu(txpower.channel), 1464 txpower.band, 1465 txpower.power[i].tpc.tx_gain, 1466 txpower.power[i].tpc.dsp_atten, 1467 txpower.power[i].rate); 1468 } 1469 /* Fill CCK rates */ 1470 for (rate_idx = IWL_FIRST_CCK_RATE; 1471 rate_idx <= IWL_LAST_CCK_RATE; rate_idx++, i++) { 1472 txpower.power[i].tpc = ch_info->power_info[i].tpc; 1473 txpower.power[i].rate = iwl3945_rates[rate_idx].plcp; 1474 1475 IWL_DEBUG_POWER(priv, "ch %d:%d rf %d dsp %3d rate code 0x%02x\n", 1476 le16_to_cpu(txpower.channel), 1477 txpower.band, 1478 txpower.power[i].tpc.tx_gain, 1479 txpower.power[i].tpc.dsp_atten, 1480 txpower.power[i].rate); 1481 } 1482 1483 return iwl_send_cmd_pdu(priv, REPLY_TX_PWR_TABLE_CMD, 1484 sizeof(struct iwl3945_txpowertable_cmd), 1485 &txpower); 1486 1487} 1488 1489/** 1490 * iwl3945_hw_reg_set_new_power - Configures power tables at new levels 1491 * @ch_info: Channel to update. Uses power_info.requested_power. 1492 * 1493 * Replace requested_power and base_power_index ch_info fields for 1494 * one channel. 1495 * 1496 * Called if user or spectrum management changes power preferences. 1497 * Takes into account h/w and modulation limitations (clip power). 1498 * 1499 * This does *not* send anything to NIC, just sets up ch_info for one channel. 1500 * 1501 * NOTE: reg_compensate_for_temperature_dif() *must* be run after this to 1502 * properly fill out the scan powers, and actual h/w gain settings, 1503 * and send changes to NIC 1504 */ 1505static int iwl3945_hw_reg_set_new_power(struct iwl_priv *priv, 1506 struct iwl_channel_info *ch_info) 1507{ 1508 struct iwl3945_channel_power_info *power_info; 1509 int power_changed = 0; 1510 int i; 1511 const s8 *clip_pwrs; 1512 int power; 1513 1514 /* Get this chnlgrp's rate-to-max/clip-powers table */ 1515 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers; 1516 1517 /* Get this channel's rate-to-current-power settings table */ 1518 power_info = ch_info->power_info; 1519 1520 /* update OFDM Txpower settings */ 1521 for (i = IWL_RATE_6M_INDEX_TABLE; i <= IWL_RATE_54M_INDEX_TABLE; 1522 i++, ++power_info) { 1523 int delta_idx; 1524 1525 /* limit new power to be no more than h/w capability */ 1526 power = min(ch_info->curr_txpow, clip_pwrs[i]); 1527 if (power == power_info->requested_power) 1528 continue; 1529 1530 /* find difference between old and new requested powers, 1531 * update base (non-temp-compensated) power index */ 1532 delta_idx = (power - power_info->requested_power) * 2; 1533 power_info->base_power_index -= delta_idx; 1534 1535 /* save new requested power value */ 1536 power_info->requested_power = power; 1537 1538 power_changed = 1; 1539 } 1540 1541 /* update CCK Txpower settings, based on OFDM 12M setting ... 1542 * ... all CCK power settings for a given channel are the *same*. */ 1543 if (power_changed) { 1544 power = 1545 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE]. 1546 requested_power + IWL_CCK_FROM_OFDM_POWER_DIFF; 1547 1548 /* do all CCK rates' iwl3945_channel_power_info structures */ 1549 for (i = IWL_RATE_1M_INDEX_TABLE; i <= IWL_RATE_11M_INDEX_TABLE; i++) { 1550 power_info->requested_power = power; 1551 power_info->base_power_index = 1552 ch_info->power_info[IWL_RATE_12M_INDEX_TABLE]. 1553 base_power_index + IWL_CCK_FROM_OFDM_INDEX_DIFF; 1554 ++power_info; 1555 } 1556 } 1557 1558 return 0; 1559} 1560 1561/** 1562 * iwl3945_hw_reg_get_ch_txpower_limit - returns new power limit for channel 1563 * 1564 * NOTE: Returned power limit may be less (but not more) than requested, 1565 * based strictly on regulatory (eeprom and spectrum mgt) limitations 1566 * (no consideration for h/w clipping limitations). 1567 */ 1568static int iwl3945_hw_reg_get_ch_txpower_limit(struct iwl_channel_info *ch_info) 1569{ 1570 s8 max_power; 1571 1572 max_power = ch_info->eeprom.max_power_avg; 1573 1574 return min(max_power, ch_info->max_power_avg); 1575} 1576 1577/** 1578 * iwl3945_hw_reg_comp_txpower_temp - Compensate for temperature 1579 * 1580 * Compensate txpower settings of *all* channels for temperature. 1581 * This only accounts for the difference between current temperature 1582 * and the factory calibration temperatures, and bases the new settings 1583 * on the channel's base_power_index. 1584 * 1585 * If RxOn is "associated", this sends the new Txpower to NIC! 1586 */ 1587static int iwl3945_hw_reg_comp_txpower_temp(struct iwl_priv *priv) 1588{ 1589 struct iwl_channel_info *ch_info = NULL; 1590 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; 1591 int delta_index; 1592 const s8 *clip_pwrs; /* array of h/w max power levels for each rate */ 1593 u8 a_band; 1594 u8 rate_index; 1595 u8 scan_tbl_index; 1596 u8 i; 1597 int ref_temp; 1598 int temperature = priv->temperature; 1599 1600 if (priv->disable_tx_power_cal || 1601 test_bit(STATUS_SCANNING, &priv->status)) { 1602 /* do not perform tx power calibration */ 1603 return 0; 1604 } 1605 /* set up new Tx power info for each and every channel, 2.4 and 5.x */ 1606 for (i = 0; i < priv->channel_count; i++) { 1607 ch_info = &priv->channel_info[i]; 1608 a_band = is_channel_a_band(ch_info); 1609 1610 /* Get this chnlgrp's factory calibration temperature */ 1611 ref_temp = (s16)eeprom->groups[ch_info->group_index]. 1612 temperature; 1613 1614 /* get power index adjustment based on current and factory 1615 * temps */ 1616 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature, 1617 ref_temp); 1618 1619 /* set tx power value for all rates, OFDM and CCK */ 1620 for (rate_index = 0; rate_index < IWL_RATE_COUNT; 1621 rate_index++) { 1622 int power_idx = 1623 ch_info->power_info[rate_index].base_power_index; 1624 1625 /* temperature compensate */ 1626 power_idx += delta_index; 1627 1628 /* stay within table range */ 1629 power_idx = iwl3945_hw_reg_fix_power_index(power_idx); 1630 ch_info->power_info[rate_index]. 1631 power_table_index = (u8) power_idx; 1632 ch_info->power_info[rate_index].tpc = 1633 power_gain_table[a_band][power_idx]; 1634 } 1635 1636 /* Get this chnlgrp's rate-to-max/clip-powers table */ 1637 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers; 1638 1639 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */ 1640 for (scan_tbl_index = 0; 1641 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) { 1642 s32 actual_index = (scan_tbl_index == 0) ? 1643 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE; 1644 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index, 1645 actual_index, clip_pwrs, 1646 ch_info, a_band); 1647 } 1648 } 1649 1650 /* send Txpower command for current channel to ucode */ 1651 return priv->cfg->ops->lib->send_tx_power(priv); 1652} 1653 1654int iwl3945_hw_reg_set_txpower(struct iwl_priv *priv, s8 power) 1655{ 1656 struct iwl_channel_info *ch_info; 1657 s8 max_power; 1658 u8 a_band; 1659 u8 i; 1660 1661 if (priv->tx_power_user_lmt == power) { 1662 IWL_DEBUG_POWER(priv, "Requested Tx power same as current " 1663 "limit: %ddBm.\n", power); 1664 return 0; 1665 } 1666 1667 IWL_DEBUG_POWER(priv, "Setting upper limit clamp to %ddBm.\n", power); 1668 priv->tx_power_user_lmt = power; 1669 1670 /* set up new Tx powers for each and every channel, 2.4 and 5.x */ 1671 1672 for (i = 0; i < priv->channel_count; i++) { 1673 ch_info = &priv->channel_info[i]; 1674 a_band = is_channel_a_band(ch_info); 1675 1676 /* find minimum power of all user and regulatory constraints 1677 * (does not consider h/w clipping limitations) */ 1678 max_power = iwl3945_hw_reg_get_ch_txpower_limit(ch_info); 1679 max_power = min(power, max_power); 1680 if (max_power != ch_info->curr_txpow) { 1681 ch_info->curr_txpow = max_power; 1682 1683 /* this considers the h/w clipping limitations */ 1684 iwl3945_hw_reg_set_new_power(priv, ch_info); 1685 } 1686 } 1687 1688 /* update txpower settings for all channels, 1689 * send to NIC if associated. */ 1690 is_temp_calib_needed(priv); 1691 iwl3945_hw_reg_comp_txpower_temp(priv); 1692 1693 return 0; 1694} 1695 1696static int iwl3945_send_rxon_assoc(struct iwl_priv *priv) 1697{ 1698 int rc = 0; 1699 struct iwl_rx_packet *pkt; 1700 struct iwl3945_rxon_assoc_cmd rxon_assoc; 1701 struct iwl_host_cmd cmd = { 1702 .id = REPLY_RXON_ASSOC, 1703 .len = sizeof(rxon_assoc), 1704 .flags = CMD_WANT_SKB, 1705 .data = &rxon_assoc, 1706 }; 1707 const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon; 1708 const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon; 1709 1710 if ((rxon1->flags == rxon2->flags) && 1711 (rxon1->filter_flags == rxon2->filter_flags) && 1712 (rxon1->cck_basic_rates == rxon2->cck_basic_rates) && 1713 (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) { 1714 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC. Not resending.\n"); 1715 return 0; 1716 } 1717 1718 rxon_assoc.flags = priv->staging_rxon.flags; 1719 rxon_assoc.filter_flags = priv->staging_rxon.filter_flags; 1720 rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates; 1721 rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates; 1722 rxon_assoc.reserved = 0; 1723 1724 rc = iwl_send_cmd_sync(priv, &cmd); 1725 if (rc) 1726 return rc; 1727 1728 pkt = (struct iwl_rx_packet *)cmd.reply_page; 1729 if (pkt->hdr.flags & IWL_CMD_FAILED_MSK) { 1730 IWL_ERR(priv, "Bad return from REPLY_RXON_ASSOC command\n"); 1731 rc = -EIO; 1732 } 1733 1734 iwl_free_pages(priv, cmd.reply_page); 1735 1736 return rc; 1737} 1738 1739/** 1740 * iwl3945_commit_rxon - commit staging_rxon to hardware 1741 * 1742 * The RXON command in staging_rxon is committed to the hardware and 1743 * the active_rxon structure is updated with the new data. This 1744 * function correctly transitions out of the RXON_ASSOC_MSK state if 1745 * a HW tune is required based on the RXON structure changes. 1746 */ 1747static int iwl3945_commit_rxon(struct iwl_priv *priv) 1748{ 1749 /* cast away the const for active_rxon in this function */ 1750 struct iwl3945_rxon_cmd *active_rxon = (void *)&priv->active_rxon; 1751 struct iwl3945_rxon_cmd *staging_rxon = (void *)&priv->staging_rxon; 1752 int rc = 0; 1753 bool new_assoc = 1754 !!(priv->staging_rxon.filter_flags & RXON_FILTER_ASSOC_MSK); 1755 1756 if (!iwl_is_alive(priv)) 1757 return -1; 1758 1759 /* always get timestamp with Rx frame */ 1760 staging_rxon->flags |= RXON_FLG_TSF2HOST_MSK; 1761 1762 /* select antenna */ 1763 staging_rxon->flags &= 1764 ~(RXON_FLG_DIS_DIV_MSK | RXON_FLG_ANT_SEL_MSK); 1765 staging_rxon->flags |= iwl3945_get_antenna_flags(priv); 1766 1767 rc = iwl_check_rxon_cmd(priv); 1768 if (rc) { 1769 IWL_ERR(priv, "Invalid RXON configuration. Not committing.\n"); 1770 return -EINVAL; 1771 } 1772 1773 /* If we don't need to send a full RXON, we can use 1774 * iwl3945_rxon_assoc_cmd which is used to reconfigure filter 1775 * and other flags for the current radio configuration. */ 1776 if (!iwl_full_rxon_required(priv)) { 1777 rc = iwl_send_rxon_assoc(priv); 1778 if (rc) { 1779 IWL_ERR(priv, "Error setting RXON_ASSOC " 1780 "configuration (%d).\n", rc); 1781 return rc; 1782 } 1783 1784 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon)); 1785 1786 return 0; 1787 } 1788 1789 /* If we are currently associated and the new config requires 1790 * an RXON_ASSOC and the new config wants the associated mask enabled, 1791 * we must clear the associated from the active configuration 1792 * before we apply the new config */ 1793 if (iwl_is_associated(priv) && new_assoc) { 1794 IWL_DEBUG_INFO(priv, "Toggling associated bit on current RXON\n"); 1795 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; 1796 1797 /* 1798 * reserved4 and 5 could have been filled by the iwlcore code. 1799 * Let's clear them before pushing to the 3945. 1800 */ 1801 active_rxon->reserved4 = 0; 1802 active_rxon->reserved5 = 0; 1803 rc = iwl_send_cmd_pdu(priv, REPLY_RXON, 1804 sizeof(struct iwl3945_rxon_cmd), 1805 &priv->active_rxon); 1806 1807 /* If the mask clearing failed then we set 1808 * active_rxon back to what it was previously */ 1809 if (rc) { 1810 active_rxon->filter_flags |= RXON_FILTER_ASSOC_MSK; 1811 IWL_ERR(priv, "Error clearing ASSOC_MSK on current " 1812 "configuration (%d).\n", rc); 1813 return rc; 1814 } 1815 iwl_clear_ucode_stations(priv); 1816 iwl_restore_stations(priv); 1817 } 1818 1819 IWL_DEBUG_INFO(priv, "Sending RXON\n" 1820 "* with%s RXON_FILTER_ASSOC_MSK\n" 1821 "* channel = %d\n" 1822 "* bssid = %pM\n", 1823 (new_assoc ? "" : "out"), 1824 le16_to_cpu(staging_rxon->channel), 1825 staging_rxon->bssid_addr); 1826 1827 /* 1828 * reserved4 and 5 could have been filled by the iwlcore code. 1829 * Let's clear them before pushing to the 3945. 1830 */ 1831 staging_rxon->reserved4 = 0; 1832 staging_rxon->reserved5 = 0; 1833 1834 iwl_set_rxon_hwcrypto(priv, !iwl3945_mod_params.sw_crypto); 1835 1836 /* Apply the new configuration */ 1837 rc = iwl_send_cmd_pdu(priv, REPLY_RXON, 1838 sizeof(struct iwl3945_rxon_cmd), 1839 staging_rxon); 1840 if (rc) { 1841 IWL_ERR(priv, "Error setting new configuration (%d).\n", rc); 1842 return rc; 1843 } 1844 1845 memcpy(active_rxon, staging_rxon, sizeof(*active_rxon)); 1846 1847 if (!new_assoc) { 1848 iwl_clear_ucode_stations(priv); 1849 iwl_restore_stations(priv); 1850 } 1851 1852 /* If we issue a new RXON command which required a tune then we must 1853 * send a new TXPOWER command or we won't be able to Tx any frames */ 1854 rc = priv->cfg->ops->lib->send_tx_power(priv); 1855 if (rc) { 1856 IWL_ERR(priv, "Error setting Tx power (%d).\n", rc); 1857 return rc; 1858 } 1859 1860 /* Init the hardware's rate fallback order based on the band */ 1861 rc = iwl3945_init_hw_rate_table(priv); 1862 if (rc) { 1863 IWL_ERR(priv, "Error setting HW rate table: %02X\n", rc); 1864 return -EIO; 1865 } 1866 1867 return 0; 1868} 1869 1870/** 1871 * iwl3945_reg_txpower_periodic - called when time to check our temperature. 1872 * 1873 * -- reset periodic timer 1874 * -- see if temp has changed enough to warrant re-calibration ... if so: 1875 * -- correct coeffs for temp (can reset temp timer) 1876 * -- save this temp as "last", 1877 * -- send new set of gain settings to NIC 1878 * NOTE: This should continue working, even when we're not associated, 1879 * so we can keep our internal table of scan powers current. */ 1880void iwl3945_reg_txpower_periodic(struct iwl_priv *priv) 1881{ 1882 /* This will kick in the "brute force" 1883 * iwl3945_hw_reg_comp_txpower_temp() below */ 1884 if (!is_temp_calib_needed(priv)) 1885 goto reschedule; 1886 1887 /* Set up a new set of temp-adjusted TxPowers, send to NIC. 1888 * This is based *only* on current temperature, 1889 * ignoring any previous power measurements */ 1890 iwl3945_hw_reg_comp_txpower_temp(priv); 1891 1892 reschedule: 1893 queue_delayed_work(priv->workqueue, 1894 &priv->_3945.thermal_periodic, REG_RECALIB_PERIOD * HZ); 1895} 1896 1897static void iwl3945_bg_reg_txpower_periodic(struct work_struct *work) 1898{ 1899 struct iwl_priv *priv = container_of(work, struct iwl_priv, 1900 _3945.thermal_periodic.work); 1901 1902 if (test_bit(STATUS_EXIT_PENDING, &priv->status)) 1903 return; 1904 1905 mutex_lock(&priv->mutex); 1906 iwl3945_reg_txpower_periodic(priv); 1907 mutex_unlock(&priv->mutex); 1908} 1909 1910/** 1911 * iwl3945_hw_reg_get_ch_grp_index - find the channel-group index (0-4) 1912 * for the channel. 1913 * 1914 * This function is used when initializing channel-info structs. 1915 * 1916 * NOTE: These channel groups do *NOT* match the bands above! 1917 * These channel groups are based on factory-tested channels; 1918 * on A-band, EEPROM's "group frequency" entries represent the top 1919 * channel in each group 1-4. Group 5 All B/G channels are in group 0. 1920 */ 1921static u16 iwl3945_hw_reg_get_ch_grp_index(struct iwl_priv *priv, 1922 const struct iwl_channel_info *ch_info) 1923{ 1924 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; 1925 struct iwl3945_eeprom_txpower_group *ch_grp = &eeprom->groups[0]; 1926 u8 group; 1927 u16 group_index = 0; /* based on factory calib frequencies */ 1928 u8 grp_channel; 1929 1930 /* Find the group index for the channel ... don't use index 1(?) */ 1931 if (is_channel_a_band(ch_info)) { 1932 for (group = 1; group < 5; group++) { 1933 grp_channel = ch_grp[group].group_channel; 1934 if (ch_info->channel <= grp_channel) { 1935 group_index = group; 1936 break; 1937 } 1938 } 1939 /* group 4 has a few channels *above* its factory cal freq */ 1940 if (group == 5) 1941 group_index = 4; 1942 } else 1943 group_index = 0; /* 2.4 GHz, group 0 */ 1944 1945 IWL_DEBUG_POWER(priv, "Chnl %d mapped to grp %d\n", ch_info->channel, 1946 group_index); 1947 return group_index; 1948} 1949 1950/** 1951 * iwl3945_hw_reg_get_matched_power_index - Interpolate to get nominal index 1952 * 1953 * Interpolate to get nominal (i.e. at factory calibration temperature) index 1954 * into radio/DSP gain settings table for requested power. 1955 */ 1956static int iwl3945_hw_reg_get_matched_power_index(struct iwl_priv *priv, 1957 s8 requested_power, 1958 s32 setting_index, s32 *new_index) 1959{ 1960 const struct iwl3945_eeprom_txpower_group *chnl_grp = NULL; 1961 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; 1962 s32 index0, index1; 1963 s32 power = 2 * requested_power; 1964 s32 i; 1965 const struct iwl3945_eeprom_txpower_sample *samples; 1966 s32 gains0, gains1; 1967 s32 res; 1968 s32 denominator; 1969 1970 chnl_grp = &eeprom->groups[setting_index]; 1971 samples = chnl_grp->samples; 1972 for (i = 0; i < 5; i++) { 1973 if (power == samples[i].power) { 1974 *new_index = samples[i].gain_index; 1975 return 0; 1976 } 1977 } 1978 1979 if (power > samples[1].power) { 1980 index0 = 0; 1981 index1 = 1; 1982 } else if (power > samples[2].power) { 1983 index0 = 1; 1984 index1 = 2; 1985 } else if (power > samples[3].power) { 1986 index0 = 2; 1987 index1 = 3; 1988 } else { 1989 index0 = 3; 1990 index1 = 4; 1991 } 1992 1993 denominator = (s32) samples[index1].power - (s32) samples[index0].power; 1994 if (denominator == 0) 1995 return -EINVAL; 1996 gains0 = (s32) samples[index0].gain_index * (1 << 19); 1997 gains1 = (s32) samples[index1].gain_index * (1 << 19); 1998 res = gains0 + (gains1 - gains0) * 1999 ((s32) power - (s32) samples[index0].power) / denominator + 2000 (1 << 18); 2001 *new_index = res >> 19; 2002 return 0; 2003} 2004 2005static void iwl3945_hw_reg_init_channel_groups(struct iwl_priv *priv) 2006{ 2007 u32 i; 2008 s32 rate_index; 2009 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; 2010 const struct iwl3945_eeprom_txpower_group *group; 2011 2012 IWL_DEBUG_POWER(priv, "Initializing factory calib info from EEPROM\n"); 2013 2014 for (i = 0; i < IWL_NUM_TX_CALIB_GROUPS; i++) { 2015 s8 *clip_pwrs; /* table of power levels for each rate */ 2016 s8 satur_pwr; /* saturation power for each chnl group */ 2017 group = &eeprom->groups[i]; 2018 2019 /* sanity check on factory saturation power value */ 2020 if (group->saturation_power < 40) { 2021 IWL_WARN(priv, "Error: saturation power is %d, " 2022 "less than minimum expected 40\n", 2023 group->saturation_power); 2024 return; 2025 } 2026 2027 /* 2028 * Derive requested power levels for each rate, based on 2029 * hardware capabilities (saturation power for band). 2030 * Basic value is 3dB down from saturation, with further 2031 * power reductions for highest 3 data rates. These 2032 * backoffs provide headroom for high rate modulation 2033 * power peaks, without too much distortion (clipping). 2034 */ 2035 /* we'll fill in this array with h/w max power levels */ 2036 clip_pwrs = (s8 *) priv->_3945.clip_groups[i].clip_powers; 2037 2038 /* divide factory saturation power by 2 to find -3dB level */ 2039 satur_pwr = (s8) (group->saturation_power >> 1); 2040 2041 /* fill in channel group's nominal powers for each rate */ 2042 for (rate_index = 0; 2043 rate_index < IWL_RATE_COUNT_3945; rate_index++, clip_pwrs++) { 2044 switch (rate_index) { 2045 case IWL_RATE_36M_INDEX_TABLE: 2046 if (i == 0) /* B/G */ 2047 *clip_pwrs = satur_pwr; 2048 else /* A */ 2049 *clip_pwrs = satur_pwr - 5; 2050 break; 2051 case IWL_RATE_48M_INDEX_TABLE: 2052 if (i == 0) 2053 *clip_pwrs = satur_pwr - 7; 2054 else 2055 *clip_pwrs = satur_pwr - 10; 2056 break; 2057 case IWL_RATE_54M_INDEX_TABLE: 2058 if (i == 0) 2059 *clip_pwrs = satur_pwr - 9; 2060 else 2061 *clip_pwrs = satur_pwr - 12; 2062 break; 2063 default: 2064 *clip_pwrs = satur_pwr; 2065 break; 2066 } 2067 } 2068 } 2069} 2070 2071/** 2072 * iwl3945_txpower_set_from_eeprom - Set channel power info based on EEPROM 2073 * 2074 * Second pass (during init) to set up priv->channel_info 2075 * 2076 * Set up Tx-power settings in our channel info database for each VALID 2077 * (for this geo/SKU) channel, at all Tx data rates, based on eeprom values 2078 * and current temperature. 2079 * 2080 * Since this is based on current temperature (at init time), these values may 2081 * not be valid for very long, but it gives us a starting/default point, 2082 * and allows us to active (i.e. using Tx) scan. 2083 * 2084 * This does *not* write values to NIC, just sets up our internal table. 2085 */ 2086int iwl3945_txpower_set_from_eeprom(struct iwl_priv *priv) 2087{ 2088 struct iwl_channel_info *ch_info = NULL; 2089 struct iwl3945_channel_power_info *pwr_info; 2090 struct iwl3945_eeprom *eeprom = (struct iwl3945_eeprom *)priv->eeprom; 2091 int delta_index; 2092 u8 rate_index; 2093 u8 scan_tbl_index; 2094 const s8 *clip_pwrs; /* array of power levels for each rate */ 2095 u8 gain, dsp_atten; 2096 s8 power; 2097 u8 pwr_index, base_pwr_index, a_band; 2098 u8 i; 2099 int temperature; 2100 2101 /* save temperature reference, 2102 * so we can determine next time to calibrate */ 2103 temperature = iwl3945_hw_reg_txpower_get_temperature(priv); 2104 priv->last_temperature = temperature; 2105 2106 iwl3945_hw_reg_init_channel_groups(priv); 2107 2108 /* initialize Tx power info for each and every channel, 2.4 and 5.x */ 2109 for (i = 0, ch_info = priv->channel_info; i < priv->channel_count; 2110 i++, ch_info++) { 2111 a_band = is_channel_a_band(ch_info); 2112 if (!is_channel_valid(ch_info)) 2113 continue; 2114 2115 /* find this channel's channel group (*not* "band") index */ 2116 ch_info->group_index = 2117 iwl3945_hw_reg_get_ch_grp_index(priv, ch_info); 2118 2119 /* Get this chnlgrp's rate->max/clip-powers table */ 2120 clip_pwrs = priv->_3945.clip_groups[ch_info->group_index].clip_powers; 2121 2122 /* calculate power index *adjustment* value according to 2123 * diff between current temperature and factory temperature */ 2124 delta_index = iwl3945_hw_reg_adjust_power_by_temp(temperature, 2125 eeprom->groups[ch_info->group_index]. 2126 temperature); 2127 2128 IWL_DEBUG_POWER(priv, "Delta index for channel %d: %d [%d]\n", 2129 ch_info->channel, delta_index, temperature + 2130 IWL_TEMP_CONVERT); 2131 2132 /* set tx power value for all OFDM rates */ 2133 for (rate_index = 0; rate_index < IWL_OFDM_RATES; 2134 rate_index++) { 2135 s32 uninitialized_var(power_idx); 2136 int rc; 2137 2138 /* use channel group's clip-power table, 2139 * but don't exceed channel's max power */ 2140 s8 pwr = min(ch_info->max_power_avg, 2141 clip_pwrs[rate_index]); 2142 2143 pwr_info = &ch_info->power_info[rate_index]; 2144 2145 /* get base (i.e. at factory-measured temperature) 2146 * power table index for this rate's power */ 2147 rc = iwl3945_hw_reg_get_matched_power_index(priv, pwr, 2148 ch_info->group_index, 2149 &power_idx); 2150 if (rc) { 2151 IWL_ERR(priv, "Invalid power index\n"); 2152 return rc; 2153 } 2154 pwr_info->base_power_index = (u8) power_idx; 2155 2156 /* temperature compensate */ 2157 power_idx += delta_index; 2158 2159 /* stay within range of gain table */ 2160 power_idx = iwl3945_hw_reg_fix_power_index(power_idx); 2161 2162 /* fill 1 OFDM rate's iwl3945_channel_power_info struct */ 2163 pwr_info->requested_power = pwr; 2164 pwr_info->power_table_index = (u8) power_idx; 2165 pwr_info->tpc.tx_gain = 2166 power_gain_table[a_band][power_idx].tx_gain; 2167 pwr_info->tpc.dsp_atten = 2168 power_gain_table[a_band][power_idx].dsp_atten; 2169 } 2170 2171 /* set tx power for CCK rates, based on OFDM 12 Mbit settings*/ 2172 pwr_info = &ch_info->power_info[IWL_RATE_12M_INDEX_TABLE]; 2173 power = pwr_info->requested_power + 2174 IWL_CCK_FROM_OFDM_POWER_DIFF; 2175 pwr_index = pwr_info->power_table_index + 2176 IWL_CCK_FROM_OFDM_INDEX_DIFF; 2177 base_pwr_index = pwr_info->base_power_index + 2178 IWL_CCK_FROM_OFDM_INDEX_DIFF; 2179 2180 /* stay within table range */ 2181 pwr_index = iwl3945_hw_reg_fix_power_index(pwr_index); 2182 gain = power_gain_table[a_band][pwr_index].tx_gain; 2183 dsp_atten = power_gain_table[a_band][pwr_index].dsp_atten; 2184 2185 /* fill each CCK rate's iwl3945_channel_power_info structure 2186 * NOTE: All CCK-rate Txpwrs are the same for a given chnl! 2187 * NOTE: CCK rates start at end of OFDM rates! */ 2188 for (rate_index = 0; 2189 rate_index < IWL_CCK_RATES; rate_index++) { 2190 pwr_info = &ch_info->power_info[rate_index+IWL_OFDM_RATES]; 2191 pwr_info->requested_power = power; 2192 pwr_info->power_table_index = pwr_index; 2193 pwr_info->base_power_index = base_pwr_index; 2194 pwr_info->tpc.tx_gain = gain; 2195 pwr_info->tpc.dsp_atten = dsp_atten; 2196 } 2197 2198 /* set scan tx power, 1Mbit for CCK, 6Mbit for OFDM */ 2199 for (scan_tbl_index = 0; 2200 scan_tbl_index < IWL_NUM_SCAN_RATES; scan_tbl_index++) { 2201 s32 actual_index = (scan_tbl_index == 0) ? 2202 IWL_RATE_1M_INDEX_TABLE : IWL_RATE_6M_INDEX_TABLE; 2203 iwl3945_hw_reg_set_scan_power(priv, scan_tbl_index, 2204 actual_index, clip_pwrs, ch_info, a_band); 2205 } 2206 } 2207 2208 return 0; 2209} 2210 2211int iwl3945_hw_rxq_stop(struct iwl_priv *priv) 2212{ 2213 int rc; 2214 2215 iwl_write_direct32(priv, FH39_RCSR_CONFIG(0), 0); 2216 rc = iwl_poll_direct_bit(priv, FH39_RSSR_STATUS, 2217 FH39_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 1000); 2218 if (rc < 0) 2219 IWL_ERR(priv, "Can't stop Rx DMA.\n"); 2220 2221 return 0; 2222} 2223 2224int iwl3945_hw_tx_queue_init(struct iwl_priv *priv, struct iwl_tx_queue *txq) 2225{ 2226 int txq_id = txq->q.id; 2227 2228 struct iwl3945_shared *shared_data = priv->_3945.shared_virt; 2229 2230 shared_data->tx_base_ptr[txq_id] = cpu_to_le32((u32)txq->q.dma_addr); 2231 2232 iwl_write_direct32(priv, FH39_CBCC_CTRL(txq_id), 0); 2233 iwl_write_direct32(priv, FH39_CBCC_BASE(txq_id), 0); 2234 2235 iwl_write_direct32(priv, FH39_TCSR_CONFIG(txq_id), 2236 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_RTC_NOINT | 2237 FH39_TCSR_TX_CONFIG_REG_VAL_MSG_MODE_TXF | 2238 FH39_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_IFTFD | 2239 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE_VAL | 2240 FH39_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE); 2241 2242 /* fake read to flush all prev. writes */ 2243 iwl_read32(priv, FH39_TSSR_CBB_BASE); 2244 2245 return 0; 2246} 2247 2248/* 2249 * HCMD utils 2250 */ 2251static u16 iwl3945_get_hcmd_size(u8 cmd_id, u16 len) 2252{ 2253 switch (cmd_id) { 2254 case REPLY_RXON: 2255 return sizeof(struct iwl3945_rxon_cmd); 2256 case POWER_TABLE_CMD: 2257 return sizeof(struct iwl3945_powertable_cmd); 2258 default: 2259 return len; 2260 } 2261} 2262 2263 2264static u16 iwl3945_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data) 2265{ 2266 struct iwl3945_addsta_cmd *addsta = (struct iwl3945_addsta_cmd *)data; 2267 addsta->mode = cmd->mode; 2268 memcpy(&addsta->sta, &cmd->sta, sizeof(struct sta_id_modify)); 2269 memcpy(&addsta->key, &cmd->key, sizeof(struct iwl4965_keyinfo)); 2270 addsta->station_flags = cmd->station_flags; 2271 addsta->station_flags_msk = cmd->station_flags_msk; 2272 addsta->tid_disable_tx = cpu_to_le16(0); 2273 addsta->rate_n_flags = cmd->rate_n_flags; 2274 addsta->add_immediate_ba_tid = cmd->add_immediate_ba_tid; 2275 addsta->remove_immediate_ba_tid = cmd->remove_immediate_ba_tid; 2276 addsta->add_immediate_ba_ssn = cmd->add_immediate_ba_ssn; 2277 2278 return (u16)sizeof(struct iwl3945_addsta_cmd); 2279} 2280 2281static int iwl3945_manage_ibss_station(struct iwl_priv *priv, 2282 struct ieee80211_vif *vif, bool add) 2283{ 2284 struct iwl_vif_priv *vif_priv = (void *)vif->drv_priv; 2285 int ret; 2286 2287 if (add) { 2288 ret = iwl_add_bssid_station(priv, vif->bss_conf.bssid, false, 2289 &vif_priv->ibss_bssid_sta_id); 2290 if (ret) 2291 return ret; 2292 2293 iwl3945_sync_sta(priv, vif_priv->ibss_bssid_sta_id, 2294 (priv->band == IEEE80211_BAND_5GHZ) ? 2295 IWL_RATE_6M_PLCP : IWL_RATE_1M_PLCP); 2296 iwl3945_rate_scale_init(priv->hw, vif_priv->ibss_bssid_sta_id); 2297 2298 return 0; 2299 } 2300 2301 return iwl_remove_station(priv, vif_priv->ibss_bssid_sta_id, 2302 vif->bss_conf.bssid); 2303} 2304 2305/** 2306 * iwl3945_init_hw_rate_table - Initialize the hardware rate fallback table 2307 */ 2308int iwl3945_init_hw_rate_table(struct iwl_priv *priv) 2309{ 2310 int rc, i, index, prev_index; 2311 struct iwl3945_rate_scaling_cmd rate_cmd = { 2312 .reserved = {0, 0, 0}, 2313 }; 2314 struct iwl3945_rate_scaling_info *table = rate_cmd.table; 2315 2316 for (i = 0; i < ARRAY_SIZE(iwl3945_rates); i++) { 2317 index = iwl3945_rates[i].table_rs_index; 2318 2319 table[index].rate_n_flags = 2320 iwl3945_hw_set_rate_n_flags(iwl3945_rates[i].plcp, 0); 2321 table[index].try_cnt = priv->retry_rate; 2322 prev_index = iwl3945_get_prev_ieee_rate(i); 2323 table[index].next_rate_index = 2324 iwl3945_rates[prev_index].table_rs_index; 2325 } 2326 2327 switch (priv->band) { 2328 case IEEE80211_BAND_5GHZ: 2329 IWL_DEBUG_RATE(priv, "Select A mode rate scale\n"); 2330 /* If one of the following CCK rates is used, 2331 * have it fall back to the 6M OFDM rate */ 2332 for (i = IWL_RATE_1M_INDEX_TABLE; 2333 i <= IWL_RATE_11M_INDEX_TABLE; i++) 2334 table[i].next_rate_index = 2335 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index; 2336 2337 /* Don't fall back to CCK rates */ 2338 table[IWL_RATE_12M_INDEX_TABLE].next_rate_index = 2339 IWL_RATE_9M_INDEX_TABLE; 2340 2341 /* Don't drop out of OFDM rates */ 2342 table[IWL_RATE_6M_INDEX_TABLE].next_rate_index = 2343 iwl3945_rates[IWL_FIRST_OFDM_RATE].table_rs_index; 2344 break; 2345 2346 case IEEE80211_BAND_2GHZ: 2347 IWL_DEBUG_RATE(priv, "Select B/G mode rate scale\n"); 2348 /* If an OFDM rate is used, have it fall back to the 2349 * 1M CCK rates */ 2350 2351 if (!(priv->_3945.sta_supp_rates & IWL_OFDM_RATES_MASK) && 2352 iwl_is_associated(priv)) { 2353 2354 index = IWL_FIRST_CCK_RATE; 2355 for (i = IWL_RATE_6M_INDEX_TABLE; 2356 i <= IWL_RATE_54M_INDEX_TABLE; i++) 2357 table[i].next_rate_index = 2358 iwl3945_rates[index].table_rs_index; 2359 2360 index = IWL_RATE_11M_INDEX_TABLE; 2361 /* CCK shouldn't fall back to OFDM... */ 2362 table[index].next_rate_index = IWL_RATE_5M_INDEX_TABLE; 2363 } 2364 break; 2365 2366 default: 2367 WARN_ON(1); 2368 break; 2369 } 2370 2371 /* Update the rate scaling for control frame Tx */ 2372 rate_cmd.table_id = 0; 2373 rc = iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd), 2374 &rate_cmd); 2375 if (rc) 2376 return rc; 2377 2378 /* Update the rate scaling for data frame Tx */ 2379 rate_cmd.table_id = 1; 2380 return iwl_send_cmd_pdu(priv, REPLY_RATE_SCALE, sizeof(rate_cmd), 2381 &rate_cmd); 2382} 2383 2384/* Called when initializing driver */ 2385int iwl3945_hw_set_hw_params(struct iwl_priv *priv) 2386{ 2387 memset((void *)&priv->hw_params, 0, 2388 sizeof(struct iwl_hw_params)); 2389 2390 priv->_3945.shared_virt = 2391 dma_alloc_coherent(&priv->pci_dev->dev, 2392 sizeof(struct iwl3945_shared), 2393 &priv->_3945.shared_phys, GFP_KERNEL); 2394 if (!priv->_3945.shared_virt) { 2395 IWL_ERR(priv, "failed to allocate pci memory\n"); 2396 return -ENOMEM; 2397 } 2398 2399 /* Assign number of Usable TX queues */ 2400 priv->hw_params.max_txq_num = priv->cfg->num_of_queues; 2401 2402 priv->hw_params.tfd_size = sizeof(struct iwl3945_tfd); 2403 priv->hw_params.rx_page_order = get_order(IWL_RX_BUF_SIZE_3K); 2404 priv->hw_params.max_rxq_size = RX_QUEUE_SIZE; 2405 priv->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; 2406 priv->hw_params.max_stations = IWL3945_STATION_COUNT; 2407 priv->hw_params.bcast_sta_id = IWL3945_BROADCAST_ID; 2408 2409 priv->hw_params.rx_wrt_ptr_reg = FH39_RSCSR_CHNL0_WPTR; 2410 priv->hw_params.max_beacon_itrvl = IWL39_MAX_UCODE_BEACON_INTERVAL; 2411 priv->hw_params.beacon_time_tsf_bits = IWL3945_EXT_BEACON_TIME_POS; 2412 2413 return 0; 2414} 2415 2416unsigned int iwl3945_hw_get_beacon_cmd(struct iwl_priv *priv, 2417 struct iwl3945_frame *frame, u8 rate) 2418{ 2419 struct iwl3945_tx_beacon_cmd *tx_beacon_cmd; 2420 unsigned int frame_size; 2421 2422 tx_beacon_cmd = (struct iwl3945_tx_beacon_cmd *)&frame->u; 2423 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); 2424 2425 tx_beacon_cmd->tx.sta_id = priv->hw_params.bcast_sta_id; 2426 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 2427 2428 frame_size = iwl3945_fill_beacon_frame(priv, 2429 tx_beacon_cmd->frame, 2430 sizeof(frame->u) - sizeof(*tx_beacon_cmd)); 2431 2432 BUG_ON(frame_size > MAX_MPDU_SIZE); 2433 tx_beacon_cmd->tx.len = cpu_to_le16((u16)frame_size); 2434 2435 tx_beacon_cmd->tx.rate = rate; 2436 tx_beacon_cmd->tx.tx_flags = (TX_CMD_FLG_SEQ_CTL_MSK | 2437 TX_CMD_FLG_TSF_MSK); 2438 2439 /* supp_rates[0] == OFDM start at IWL_FIRST_OFDM_RATE*/ 2440 tx_beacon_cmd->tx.supp_rates[0] = 2441 (IWL_OFDM_BASIC_RATES_MASK >> IWL_FIRST_OFDM_RATE) & 0xFF; 2442 2443 tx_beacon_cmd->tx.supp_rates[1] = 2444 (IWL_CCK_BASIC_RATES_MASK & 0xF); 2445 2446 return sizeof(struct iwl3945_tx_beacon_cmd) + frame_size; 2447} 2448 2449void iwl3945_hw_rx_handler_setup(struct iwl_priv *priv) 2450{ 2451 priv->rx_handlers[REPLY_TX] = iwl3945_rx_reply_tx; 2452 priv->rx_handlers[REPLY_3945_RX] = iwl3945_rx_reply_rx; 2453} 2454 2455void iwl3945_hw_setup_deferred_work(struct iwl_priv *priv) 2456{ 2457 INIT_DELAYED_WORK(&priv->_3945.thermal_periodic, 2458 iwl3945_bg_reg_txpower_periodic); 2459} 2460 2461void iwl3945_hw_cancel_deferred_work(struct iwl_priv *priv) 2462{ 2463 cancel_delayed_work(&priv->_3945.thermal_periodic); 2464} 2465 2466/* check contents of special bootstrap uCode SRAM */ 2467static int iwl3945_verify_bsm(struct iwl_priv *priv) 2468 { 2469 __le32 *image = priv->ucode_boot.v_addr; 2470 u32 len = priv->ucode_boot.len; 2471 u32 reg; 2472 u32 val; 2473 2474 IWL_DEBUG_INFO(priv, "Begin verify bsm\n"); 2475 2476 /* verify BSM SRAM contents */ 2477 val = iwl_read_prph(priv, BSM_WR_DWCOUNT_REG); 2478 for (reg = BSM_SRAM_LOWER_BOUND; 2479 reg < BSM_SRAM_LOWER_BOUND + len; 2480 reg += sizeof(u32), image++) { 2481 val = iwl_read_prph(priv, reg); 2482 if (val != le32_to_cpu(*image)) { 2483 IWL_ERR(priv, "BSM uCode verification failed at " 2484 "addr 0x%08X+%u (of %u), is 0x%x, s/b 0x%x\n", 2485 BSM_SRAM_LOWER_BOUND, 2486 reg - BSM_SRAM_LOWER_BOUND, len, 2487 val, le32_to_cpu(*image)); 2488 return -EIO; 2489 } 2490 } 2491 2492 IWL_DEBUG_INFO(priv, "BSM bootstrap uCode image OK\n"); 2493 2494 return 0; 2495} 2496 2497 2498/****************************************************************************** 2499 * 2500 * EEPROM related functions 2501 * 2502 ******************************************************************************/ 2503 2504/* 2505 * Clear the OWNER_MSK, to establish driver (instead of uCode running on 2506 * embedded controller) as EEPROM reader; each read is a series of pulses 2507 * to/from the EEPROM chip, not a single event, so even reads could conflict 2508 * if they weren't arbitrated by some ownership mechanism. Here, the driver 2509 * simply claims ownership, which should be safe when this function is called 2510 * (i.e. before loading uCode!). 2511 */ 2512static int iwl3945_eeprom_acquire_semaphore(struct iwl_priv *priv) 2513{ 2514 _iwl_clear_bit(priv, CSR_EEPROM_GP, CSR_EEPROM_GP_IF_OWNER_MSK); 2515 return 0; 2516} 2517 2518 2519static void iwl3945_eeprom_release_semaphore(struct iwl_priv *priv) 2520{ 2521 return; 2522} 2523 2524 /** 2525 * iwl3945_load_bsm - Load bootstrap instructions 2526 * 2527 * BSM operation: 2528 * 2529 * The Bootstrap State Machine (BSM) stores a short bootstrap uCode program 2530 * in special SRAM that does not power down during RFKILL. When powering back 2531 * up after power-saving sleeps (or during initial uCode load), the BSM loads 2532 * the bootstrap program into the on-board processor, and starts it. 2533 * 2534 * The bootstrap program loads (via DMA) instructions and data for a new 2535 * program from host DRAM locations indicated by the host driver in the 2536 * BSM_DRAM_* registers. Once the new program is loaded, it starts 2537 * automatically. 2538 * 2539 * When initializing the NIC, the host driver points the BSM to the 2540 * "initialize" uCode image. This uCode sets up some internal data, then 2541 * notifies host via "initialize alive" that it is complete. 2542 * 2543 * The host then replaces the BSM_DRAM_* pointer values to point to the 2544 * normal runtime uCode instructions and a backup uCode data cache buffer 2545 * (filled initially with starting data values for the on-board processor), 2546 * then triggers the "initialize" uCode to load and launch the runtime uCode, 2547 * which begins normal operation. 2548 * 2549 * When doing a power-save shutdown, runtime uCode saves data SRAM into 2550 * the backup data cache in DRAM before SRAM is powered down. 2551 * 2552 * When powering back up, the BSM loads the bootstrap program. This reloads 2553 * the runtime uCode instructions and the backup data cache into SRAM, 2554 * and re-launches the runtime uCode from where it left off. 2555 */ 2556static int iwl3945_load_bsm(struct iwl_priv *priv) 2557{ 2558 __le32 *image = priv->ucode_boot.v_addr; 2559 u32 len = priv->ucode_boot.len; 2560 dma_addr_t pinst; 2561 dma_addr_t pdata; 2562 u32 inst_len; 2563 u32 data_len; 2564 int rc; 2565 int i; 2566 u32 done; 2567 u32 reg_offset; 2568 2569 IWL_DEBUG_INFO(priv, "Begin load bsm\n"); 2570 2571 /* make sure bootstrap program is no larger than BSM's SRAM size */ 2572 if (len > IWL39_MAX_BSM_SIZE) 2573 return -EINVAL; 2574 2575 /* Tell bootstrap uCode where to find the "Initialize" uCode 2576 * in host DRAM ... host DRAM physical address bits 31:0 for 3945. 2577 * NOTE: iwl3945_initialize_alive_start() will replace these values, 2578 * after the "initialize" uCode has run, to point to 2579 * runtime/protocol instructions and backup data cache. */ 2580 pinst = priv->ucode_init.p_addr; 2581 pdata = priv->ucode_init_data.p_addr; 2582 inst_len = priv->ucode_init.len; 2583 data_len = priv->ucode_init_data.len; 2584 2585 iwl_write_prph(priv, BSM_DRAM_INST_PTR_REG, pinst); 2586 iwl_write_prph(priv, BSM_DRAM_DATA_PTR_REG, pdata); 2587 iwl_write_prph(priv, BSM_DRAM_INST_BYTECOUNT_REG, inst_len); 2588 iwl_write_prph(priv, BSM_DRAM_DATA_BYTECOUNT_REG, data_len); 2589 2590 /* Fill BSM memory with bootstrap instructions */ 2591 for (reg_offset = BSM_SRAM_LOWER_BOUND; 2592 reg_offset < BSM_SRAM_LOWER_BOUND + len; 2593 reg_offset += sizeof(u32), image++) 2594 _iwl_write_prph(priv, reg_offset, 2595 le32_to_cpu(*image)); 2596 2597 rc = iwl3945_verify_bsm(priv); 2598 if (rc) 2599 return rc; 2600 2601 /* Tell BSM to copy from BSM SRAM into instruction SRAM, when asked */ 2602 iwl_write_prph(priv, BSM_WR_MEM_SRC_REG, 0x0); 2603 iwl_write_prph(priv, BSM_WR_MEM_DST_REG, 2604 IWL39_RTC_INST_LOWER_BOUND); 2605 iwl_write_prph(priv, BSM_WR_DWCOUNT_REG, len / sizeof(u32)); 2606 2607 /* Load bootstrap code into instruction SRAM now, 2608 * to prepare to load "initialize" uCode */ 2609 iwl_write_prph(priv, BSM_WR_CTRL_REG, 2610 BSM_WR_CTRL_REG_BIT_START); 2611 2612 /* Wait for load of bootstrap uCode to finish */ 2613 for (i = 0; i < 100; i++) { 2614 done = iwl_read_prph(priv, BSM_WR_CTRL_REG); 2615 if (!(done & BSM_WR_CTRL_REG_BIT_START)) 2616 break; 2617 udelay(10); 2618 } 2619 if (i < 100) 2620 IWL_DEBUG_INFO(priv, "BSM write complete, poll %d iterations\n", i); 2621 else { 2622 IWL_ERR(priv, "BSM write did not complete!\n"); 2623 return -EIO; 2624 } 2625 2626 /* Enable future boot loads whenever power management unit triggers it 2627 * (e.g. when powering back up after power-save shutdown) */ 2628 iwl_write_prph(priv, BSM_WR_CTRL_REG, 2629 BSM_WR_CTRL_REG_BIT_START_EN); 2630 2631 return 0; 2632} 2633 2634static struct iwl_hcmd_ops iwl3945_hcmd = { 2635 .rxon_assoc = iwl3945_send_rxon_assoc, 2636 .commit_rxon = iwl3945_commit_rxon, 2637 .send_bt_config = iwl_send_bt_config, 2638}; 2639 2640static struct iwl_lib_ops iwl3945_lib = { 2641 .txq_attach_buf_to_tfd = iwl3945_hw_txq_attach_buf_to_tfd, 2642 .txq_free_tfd = iwl3945_hw_txq_free_tfd, 2643 .txq_init = iwl3945_hw_tx_queue_init, 2644 .load_ucode = iwl3945_load_bsm, 2645 .dump_nic_event_log = iwl3945_dump_nic_event_log, 2646 .dump_nic_error_log = iwl3945_dump_nic_error_log, 2647 .apm_ops = { 2648 .init = iwl3945_apm_init, 2649 .stop = iwl_apm_stop, 2650 .config = iwl3945_nic_config, 2651 .set_pwr_src = iwl3945_set_pwr_src, 2652 }, 2653 .eeprom_ops = { 2654 .regulatory_bands = { 2655 EEPROM_REGULATORY_BAND_1_CHANNELS, 2656 EEPROM_REGULATORY_BAND_2_CHANNELS, 2657 EEPROM_REGULATORY_BAND_3_CHANNELS, 2658 EEPROM_REGULATORY_BAND_4_CHANNELS, 2659 EEPROM_REGULATORY_BAND_5_CHANNELS, 2660 EEPROM_REGULATORY_BAND_NO_HT40, 2661 EEPROM_REGULATORY_BAND_NO_HT40, 2662 }, 2663 .verify_signature = iwlcore_eeprom_verify_signature, 2664 .acquire_semaphore = iwl3945_eeprom_acquire_semaphore, 2665 .release_semaphore = iwl3945_eeprom_release_semaphore, 2666 .query_addr = iwlcore_eeprom_query_addr, 2667 }, 2668 .send_tx_power = iwl3945_send_tx_power, 2669 .is_valid_rtc_data_addr = iwl3945_hw_valid_rtc_data_addr, 2670 .post_associate = iwl3945_post_associate, 2671 .isr = iwl_isr_legacy, 2672 .config_ap = iwl3945_config_ap, 2673 .manage_ibss_station = iwl3945_manage_ibss_station, 2674 .recover_from_tx_stall = iwl_bg_monitor_recover, 2675 .check_plcp_health = iwl3945_good_plcp_health, 2676 2677 .debugfs_ops = { 2678 .rx_stats_read = iwl3945_ucode_rx_stats_read, 2679 .tx_stats_read = iwl3945_ucode_tx_stats_read, 2680 .general_stats_read = iwl3945_ucode_general_stats_read, 2681 }, 2682}; 2683 2684static struct iwl_hcmd_utils_ops iwl3945_hcmd_utils = { 2685 .get_hcmd_size = iwl3945_get_hcmd_size, 2686 .build_addsta_hcmd = iwl3945_build_addsta_hcmd, 2687 .tx_cmd_protection = iwlcore_tx_cmd_protection, 2688 .request_scan = iwl3945_request_scan, 2689}; 2690 2691static const struct iwl_ops iwl3945_ops = { 2692 .lib = &iwl3945_lib, 2693 .hcmd = &iwl3945_hcmd, 2694 .utils = &iwl3945_hcmd_utils, 2695 .led = &iwl3945_led_ops, 2696}; 2697 2698static struct iwl_cfg iwl3945_bg_cfg = { 2699 .name = "3945BG", 2700 .fw_name_pre = IWL3945_FW_PRE, 2701 .ucode_api_max = IWL3945_UCODE_API_MAX, 2702 .ucode_api_min = IWL3945_UCODE_API_MIN, 2703 .sku = IWL_SKU_G, 2704 .eeprom_size = IWL3945_EEPROM_IMG_SIZE, 2705 .eeprom_ver = EEPROM_3945_EEPROM_VERSION, 2706 .ops = &iwl3945_ops, 2707 .num_of_queues = IWL39_NUM_QUEUES, 2708 .mod_params = &iwl3945_mod_params, 2709 .pll_cfg_val = CSR39_ANA_PLL_CFG_VAL, 2710 .set_l0s = false, 2711 .use_bsm = true, 2712 .use_isr_legacy = true, 2713 .ht_greenfield_support = false, 2714 .led_compensation = 64, 2715 .broken_powersave = true, 2716 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF, 2717 .monitor_recover_period = IWL_DEF_MONITORING_PERIOD, 2718 .max_event_log_size = 512, 2719 .tx_power_by_driver = true, 2720}; 2721 2722static struct iwl_cfg iwl3945_abg_cfg = { 2723 .name = "3945ABG", 2724 .fw_name_pre = IWL3945_FW_PRE, 2725 .ucode_api_max = IWL3945_UCODE_API_MAX, 2726 .ucode_api_min = IWL3945_UCODE_API_MIN, 2727 .sku = IWL_SKU_A|IWL_SKU_G, 2728 .eeprom_size = IWL3945_EEPROM_IMG_SIZE, 2729 .eeprom_ver = EEPROM_3945_EEPROM_VERSION, 2730 .ops = &iwl3945_ops, 2731 .num_of_queues = IWL39_NUM_QUEUES, 2732 .mod_params = &iwl3945_mod_params, 2733 .use_isr_legacy = true, 2734 .ht_greenfield_support = false, 2735 .led_compensation = 64, 2736 .broken_powersave = true, 2737 .plcp_delta_threshold = IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF, 2738 .monitor_recover_period = IWL_DEF_MONITORING_PERIOD, 2739 .max_event_log_size = 512, 2740 .tx_power_by_driver = true, 2741}; 2742 2743DEFINE_PCI_DEVICE_TABLE(iwl3945_hw_card_ids) = { 2744 {IWL_PCI_DEVICE(0x4222, 0x1005, iwl3945_bg_cfg)}, 2745 {IWL_PCI_DEVICE(0x4222, 0x1034, iwl3945_bg_cfg)}, 2746 {IWL_PCI_DEVICE(0x4222, 0x1044, iwl3945_bg_cfg)}, 2747 {IWL_PCI_DEVICE(0x4227, 0x1014, iwl3945_bg_cfg)}, 2748 {IWL_PCI_DEVICE(0x4222, PCI_ANY_ID, iwl3945_abg_cfg)}, 2749 {IWL_PCI_DEVICE(0x4227, PCI_ANY_ID, iwl3945_abg_cfg)}, 2750 {0} 2751}; 2752 2753MODULE_DEVICE_TABLE(pci, iwl3945_hw_card_ids); 2754