1/* 2 * Copyright (c) 2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef WMI_H 18#define WMI_H 19 20 21struct wmi_event_txrate { 22 __be32 txrate; 23 struct { 24 u8 rssi_thresh; 25 u8 per; 26 } rc_stats; 27} __packed; 28 29struct wmi_cmd_hdr { 30 __be16 command_id; 31 __be16 seq_no; 32} __packed; 33 34struct wmi_swba { 35 u8 beacon_pending; 36} __packed; 37 38enum wmi_cmd_id { 39 WMI_ECHO_CMDID = 0x0001, 40 WMI_ACCESS_MEMORY_CMDID, 41 42 /* Commands to Target */ 43 WMI_DISABLE_INTR_CMDID, 44 WMI_ENABLE_INTR_CMDID, 45 WMI_RX_LINK_CMDID, 46 WMI_ATH_INIT_CMDID, 47 WMI_ABORT_TXQ_CMDID, 48 WMI_STOP_TX_DMA_CMDID, 49 WMI_STOP_DMA_RECV_CMDID, 50 WMI_ABORT_TX_DMA_CMDID, 51 WMI_DRAIN_TXQ_CMDID, 52 WMI_DRAIN_TXQ_ALL_CMDID, 53 WMI_START_RECV_CMDID, 54 WMI_STOP_RECV_CMDID, 55 WMI_FLUSH_RECV_CMDID, 56 WMI_SET_MODE_CMDID, 57 WMI_RESET_CMDID, 58 WMI_NODE_CREATE_CMDID, 59 WMI_NODE_REMOVE_CMDID, 60 WMI_VAP_REMOVE_CMDID, 61 WMI_VAP_CREATE_CMDID, 62 WMI_BEACON_UPDATE_CMDID, 63 WMI_REG_READ_CMDID, 64 WMI_REG_WRITE_CMDID, 65 WMI_RC_STATE_CHANGE_CMDID, 66 WMI_RC_RATE_UPDATE_CMDID, 67 WMI_DEBUG_INFO_CMDID, 68 WMI_HOST_ATTACH, 69 WMI_TARGET_IC_UPDATE_CMDID, 70 WMI_TGT_STATS_CMDID, 71 WMI_TX_AGGR_ENABLE_CMDID, 72 WMI_TGT_DETACH_CMDID, 73 WMI_TGT_TXQ_ENABLE_CMDID, 74}; 75 76enum wmi_event_id { 77 WMI_TGT_RDY_EVENTID = 0x1001, 78 WMI_SWBA_EVENTID, 79 WMI_FATAL_EVENTID, 80 WMI_TXTO_EVENTID, 81 WMI_BMISS_EVENTID, 82 WMI_WLAN_TXCOMP_EVENTID, 83 WMI_DELBA_EVENTID, 84 WMI_TXRATE_EVENTID, 85}; 86 87#define MAX_CMD_NUMBER 62 88 89struct register_write { 90 __be32 reg; 91 __be32 val; 92}; 93 94struct wmi { 95 struct ath9k_htc_priv *drv_priv; 96 struct htc_target *htc; 97 enum htc_endpoint_id ctrl_epid; 98 struct mutex op_mutex; 99 struct completion cmd_wait; 100 enum wmi_cmd_id last_cmd_id; 101 u16 tx_seq_id; 102 u8 *cmd_rsp_buf; 103 u32 cmd_rsp_len; 104 bool stopped; 105 106 struct sk_buff *wmi_skb; 107 spinlock_t wmi_lock; 108 109 atomic_t mwrite_cnt; 110 struct register_write multi_write[MAX_CMD_NUMBER]; 111 u32 multi_write_idx; 112 struct mutex multi_write_mutex; 113}; 114 115struct wmi *ath9k_init_wmi(struct ath9k_htc_priv *priv); 116void ath9k_deinit_wmi(struct ath9k_htc_priv *priv); 117int ath9k_wmi_connect(struct htc_target *htc, struct wmi *wmi, 118 enum htc_endpoint_id *wmi_ctrl_epid); 119int ath9k_wmi_cmd(struct wmi *wmi, enum wmi_cmd_id cmd_id, 120 u8 *cmd_buf, u32 cmd_len, 121 u8 *rsp_buf, u32 rsp_len, 122 u32 timeout); 123void ath9k_wmi_tasklet(unsigned long data); 124 125#define WMI_CMD(_wmi_cmd) \ 126 do { \ 127 ret = ath9k_wmi_cmd(priv->wmi, _wmi_cmd, NULL, 0, \ 128 (u8 *) &cmd_rsp, \ 129 sizeof(cmd_rsp), HZ*2); \ 130 } while (0) 131 132#define WMI_CMD_BUF(_wmi_cmd, _buf) \ 133 do { \ 134 ret = ath9k_wmi_cmd(priv->wmi, _wmi_cmd, \ 135 (u8 *) _buf, sizeof(*_buf), \ 136 &cmd_rsp, sizeof(cmd_rsp), HZ*2); \ 137 } while (0) 138 139#endif /* WMI_H */ 140