1/* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef REG_H 18#define REG_H 19 20#include "../reg.h" 21 22#define AR_CR 0x0008 23#define AR_CR_RXE (AR_SREV_9300_20_OR_LATER(ah) ? 0x0000000c : 0x00000004) 24#define AR_CR_RXD 0x00000020 25#define AR_CR_SWI 0x00000040 26 27#define AR_RXDP 0x000C 28 29#define AR_CFG 0x0014 30#define AR_CFG_SWTD 0x00000001 31#define AR_CFG_SWTB 0x00000002 32#define AR_CFG_SWRD 0x00000004 33#define AR_CFG_SWRB 0x00000008 34#define AR_CFG_SWRG 0x00000010 35#define AR_CFG_AP_ADHOC_INDICATION 0x00000020 36#define AR_CFG_PHOK 0x00000100 37#define AR_CFG_CLK_GATE_DIS 0x00000400 38#define AR_CFG_EEBS 0x00000200 39#define AR_CFG_PCI_MASTER_REQ_Q_THRESH 0x00060000 40#define AR_CFG_PCI_MASTER_REQ_Q_THRESH_S 17 41 42#define AR_RXBP_THRESH 0x0018 43#define AR_RXBP_THRESH_HP 0x0000000f 44#define AR_RXBP_THRESH_HP_S 0 45#define AR_RXBP_THRESH_LP 0x00003f00 46#define AR_RXBP_THRESH_LP_S 8 47 48#define AR_MIRT 0x0020 49#define AR_MIRT_VAL 0x0000ffff 50#define AR_MIRT_VAL_S 16 51 52#define AR_IER 0x0024 53#define AR_IER_ENABLE 0x00000001 54#define AR_IER_DISABLE 0x00000000 55 56#define AR_TIMT 0x0028 57#define AR_TIMT_LAST 0x0000ffff 58#define AR_TIMT_LAST_S 0 59#define AR_TIMT_FIRST 0xffff0000 60#define AR_TIMT_FIRST_S 16 61 62#define AR_RIMT 0x002C 63#define AR_RIMT_LAST 0x0000ffff 64#define AR_RIMT_LAST_S 0 65#define AR_RIMT_FIRST 0xffff0000 66#define AR_RIMT_FIRST_S 16 67 68#define AR_DMASIZE_4B 0x00000000 69#define AR_DMASIZE_8B 0x00000001 70#define AR_DMASIZE_16B 0x00000002 71#define AR_DMASIZE_32B 0x00000003 72#define AR_DMASIZE_64B 0x00000004 73#define AR_DMASIZE_128B 0x00000005 74#define AR_DMASIZE_256B 0x00000006 75#define AR_DMASIZE_512B 0x00000007 76 77#define AR_TXCFG 0x0030 78#define AR_TXCFG_DMASZ_MASK 0x00000007 79#define AR_TXCFG_DMASZ_4B 0 80#define AR_TXCFG_DMASZ_8B 1 81#define AR_TXCFG_DMASZ_16B 2 82#define AR_TXCFG_DMASZ_32B 3 83#define AR_TXCFG_DMASZ_64B 4 84#define AR_TXCFG_DMASZ_128B 5 85#define AR_TXCFG_DMASZ_256B 6 86#define AR_TXCFG_DMASZ_512B 7 87#define AR_FTRIG 0x000003F0 88#define AR_FTRIG_S 4 89#define AR_FTRIG_IMMED 0x00000000 90#define AR_FTRIG_64B 0x00000010 91#define AR_FTRIG_128B 0x00000020 92#define AR_FTRIG_192B 0x00000030 93#define AR_FTRIG_256B 0x00000040 94#define AR_FTRIG_512B 0x00000080 95#define AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY 0x00000800 96 97#define AR_RXCFG 0x0034 98#define AR_RXCFG_CHIRP 0x00000008 99#define AR_RXCFG_ZLFDMA 0x00000010 100#define AR_RXCFG_DMASZ_MASK 0x00000007 101#define AR_RXCFG_DMASZ_4B 0 102#define AR_RXCFG_DMASZ_8B 1 103#define AR_RXCFG_DMASZ_16B 2 104#define AR_RXCFG_DMASZ_32B 3 105#define AR_RXCFG_DMASZ_64B 4 106#define AR_RXCFG_DMASZ_128B 5 107#define AR_RXCFG_DMASZ_256B 6 108#define AR_RXCFG_DMASZ_512B 7 109 110#define AR_MIBC 0x0040 111#define AR_MIBC_COW 0x00000001 112#define AR_MIBC_FMC 0x00000002 113#define AR_MIBC_CMC 0x00000004 114#define AR_MIBC_MCS 0x00000008 115 116#define AR_TOPS 0x0044 117#define AR_TOPS_MASK 0x0000FFFF 118 119#define AR_RXNPTO 0x0048 120#define AR_RXNPTO_MASK 0x000003FF 121 122#define AR_TXNPTO 0x004C 123#define AR_TXNPTO_MASK 0x000003FF 124#define AR_TXNPTO_QCU_MASK 0x000FFC00 125 126#define AR_RPGTO 0x0050 127#define AR_RPGTO_MASK 0x000003FF 128 129#define AR_RPCNT 0x0054 130#define AR_RPCNT_MASK 0x0000001F 131 132#define AR_MACMISC 0x0058 133#define AR_MACMISC_PCI_EXT_FORCE 0x00000010 134#define AR_MACMISC_DMA_OBS 0x000001E0 135#define AR_MACMISC_DMA_OBS_S 5 136#define AR_MACMISC_DMA_OBS_LINE_0 0 137#define AR_MACMISC_DMA_OBS_LINE_1 1 138#define AR_MACMISC_DMA_OBS_LINE_2 2 139#define AR_MACMISC_DMA_OBS_LINE_3 3 140#define AR_MACMISC_DMA_OBS_LINE_4 4 141#define AR_MACMISC_DMA_OBS_LINE_5 5 142#define AR_MACMISC_DMA_OBS_LINE_6 6 143#define AR_MACMISC_DMA_OBS_LINE_7 7 144#define AR_MACMISC_DMA_OBS_LINE_8 8 145#define AR_MACMISC_MISC_OBS 0x00000E00 146#define AR_MACMISC_MISC_OBS_S 9 147#define AR_MACMISC_MISC_OBS_BUS_LSB 0x00007000 148#define AR_MACMISC_MISC_OBS_BUS_LSB_S 12 149#define AR_MACMISC_MISC_OBS_BUS_MSB 0x00038000 150#define AR_MACMISC_MISC_OBS_BUS_MSB_S 15 151#define AR_MACMISC_MISC_OBS_BUS_1 1 152 153#define AR_DATABUF_SIZE 0x0060 154#define AR_DATABUF_SIZE_MASK 0x00000FFF 155 156#define AR_GTXTO 0x0064 157#define AR_GTXTO_TIMEOUT_COUNTER 0x0000FFFF 158#define AR_GTXTO_TIMEOUT_LIMIT 0xFFFF0000 159#define AR_GTXTO_TIMEOUT_LIMIT_S 16 160 161#define AR_GTTM 0x0068 162#define AR_GTTM_USEC 0x00000001 163#define AR_GTTM_IGNORE_IDLE 0x00000002 164#define AR_GTTM_RESET_IDLE 0x00000004 165#define AR_GTTM_CST_USEC 0x00000008 166 167#define AR_CST 0x006C 168#define AR_CST_TIMEOUT_COUNTER 0x0000FFFF 169#define AR_CST_TIMEOUT_LIMIT 0xFFFF0000 170#define AR_CST_TIMEOUT_LIMIT_S 16 171 172#define AR_HP_RXDP 0x0074 173#define AR_LP_RXDP 0x0078 174 175#define AR_ISR 0x0080 176#define AR_ISR_RXOK 0x00000001 177#define AR_ISR_RXDESC 0x00000002 178#define AR_ISR_HP_RXOK 0x00000001 179#define AR_ISR_LP_RXOK 0x00000002 180#define AR_ISR_RXERR 0x00000004 181#define AR_ISR_RXNOPKT 0x00000008 182#define AR_ISR_RXEOL 0x00000010 183#define AR_ISR_RXORN 0x00000020 184#define AR_ISR_TXOK 0x00000040 185#define AR_ISR_TXDESC 0x00000080 186#define AR_ISR_TXERR 0x00000100 187#define AR_ISR_TXNOPKT 0x00000200 188#define AR_ISR_TXEOL 0x00000400 189#define AR_ISR_TXURN 0x00000800 190#define AR_ISR_MIB 0x00001000 191#define AR_ISR_SWI 0x00002000 192#define AR_ISR_RXPHY 0x00004000 193#define AR_ISR_RXKCM 0x00008000 194#define AR_ISR_SWBA 0x00010000 195#define AR_ISR_BRSSI 0x00020000 196#define AR_ISR_BMISS 0x00040000 197#define AR_ISR_BNR 0x00100000 198#define AR_ISR_RXCHIRP 0x00200000 199#define AR_ISR_BCNMISC 0x00800000 200#define AR_ISR_TIM 0x00800000 201#define AR_ISR_QCBROVF 0x02000000 202#define AR_ISR_QCBRURN 0x04000000 203#define AR_ISR_QTRIG 0x08000000 204#define AR_ISR_GENTMR 0x10000000 205 206#define AR_ISR_TXMINTR 0x00080000 207#define AR_ISR_RXMINTR 0x01000000 208#define AR_ISR_TXINTM 0x40000000 209#define AR_ISR_RXINTM 0x80000000 210 211#define AR_ISR_S0 0x0084 212#define AR_ISR_S0_QCU_TXOK 0x000003FF 213#define AR_ISR_S0_QCU_TXOK_S 0 214#define AR_ISR_S0_QCU_TXDESC 0x03FF0000 215#define AR_ISR_S0_QCU_TXDESC_S 16 216 217#define AR_ISR_S1 0x0088 218#define AR_ISR_S1_QCU_TXERR 0x000003FF 219#define AR_ISR_S1_QCU_TXERR_S 0 220#define AR_ISR_S1_QCU_TXEOL 0x03FF0000 221#define AR_ISR_S1_QCU_TXEOL_S 16 222 223#define AR_ISR_S2 0x008c 224#define AR_ISR_S2_QCU_TXURN 0x000003FF 225#define AR_ISR_S2_BB_WATCHDOG 0x00010000 226#define AR_ISR_S2_CST 0x00400000 227#define AR_ISR_S2_GTT 0x00800000 228#define AR_ISR_S2_TIM 0x01000000 229#define AR_ISR_S2_CABEND 0x02000000 230#define AR_ISR_S2_DTIMSYNC 0x04000000 231#define AR_ISR_S2_BCNTO 0x08000000 232#define AR_ISR_S2_CABTO 0x10000000 233#define AR_ISR_S2_DTIM 0x20000000 234#define AR_ISR_S2_TSFOOR 0x40000000 235#define AR_ISR_S2_TBTT_TIME 0x80000000 236 237#define AR_ISR_S3 0x0090 238#define AR_ISR_S3_QCU_QCBROVF 0x000003FF 239#define AR_ISR_S3_QCU_QCBRURN 0x03FF0000 240 241#define AR_ISR_S4 0x0094 242#define AR_ISR_S4_QCU_QTRIG 0x000003FF 243#define AR_ISR_S4_RESV0 0xFFFFFC00 244 245#define AR_ISR_S5 0x0098 246#define AR_ISR_S5_TIMER_TRIG 0x000000FF 247#define AR_ISR_S5_TIMER_THRESH 0x0007FE00 248#define AR_ISR_S5_TIM_TIMER 0x00000010 249#define AR_ISR_S5_DTIM_TIMER 0x00000020 250#define AR_IMR_S5 0x00b8 251#define AR_IMR_S5_TIM_TIMER 0x00000010 252#define AR_IMR_S5_DTIM_TIMER 0x00000020 253#define AR_ISR_S5_GENTIMER_TRIG 0x0000FF80 254#define AR_ISR_S5_GENTIMER_TRIG_S 0 255#define AR_ISR_S5_GENTIMER_THRESH 0xFF800000 256#define AR_ISR_S5_GENTIMER_THRESH_S 16 257#define AR_IMR_S5_GENTIMER_TRIG 0x0000FF80 258#define AR_IMR_S5_GENTIMER_TRIG_S 0 259#define AR_IMR_S5_GENTIMER_THRESH 0xFF800000 260#define AR_IMR_S5_GENTIMER_THRESH_S 16 261 262#define AR_IMR 0x00a0 263#define AR_IMR_RXOK 0x00000001 264#define AR_IMR_RXDESC 0x00000002 265#define AR_IMR_RXOK_HP 0x00000001 266#define AR_IMR_RXOK_LP 0x00000002 267#define AR_IMR_RXERR 0x00000004 268#define AR_IMR_RXNOPKT 0x00000008 269#define AR_IMR_RXEOL 0x00000010 270#define AR_IMR_RXORN 0x00000020 271#define AR_IMR_TXOK 0x00000040 272#define AR_IMR_TXDESC 0x00000080 273#define AR_IMR_TXERR 0x00000100 274#define AR_IMR_TXNOPKT 0x00000200 275#define AR_IMR_TXEOL 0x00000400 276#define AR_IMR_TXURN 0x00000800 277#define AR_IMR_MIB 0x00001000 278#define AR_IMR_SWI 0x00002000 279#define AR_IMR_RXPHY 0x00004000 280#define AR_IMR_RXKCM 0x00008000 281#define AR_IMR_SWBA 0x00010000 282#define AR_IMR_BRSSI 0x00020000 283#define AR_IMR_BMISS 0x00040000 284#define AR_IMR_BNR 0x00100000 285#define AR_IMR_RXCHIRP 0x00200000 286#define AR_IMR_BCNMISC 0x00800000 287#define AR_IMR_TIM 0x00800000 288#define AR_IMR_QCBROVF 0x02000000 289#define AR_IMR_QCBRURN 0x04000000 290#define AR_IMR_QTRIG 0x08000000 291#define AR_IMR_GENTMR 0x10000000 292 293#define AR_IMR_TXMINTR 0x00080000 294#define AR_IMR_RXMINTR 0x01000000 295#define AR_IMR_TXINTM 0x40000000 296#define AR_IMR_RXINTM 0x80000000 297 298#define AR_IMR_S0 0x00a4 299#define AR_IMR_S0_QCU_TXOK 0x000003FF 300#define AR_IMR_S0_QCU_TXOK_S 0 301#define AR_IMR_S0_QCU_TXDESC 0x03FF0000 302#define AR_IMR_S0_QCU_TXDESC_S 16 303 304#define AR_IMR_S1 0x00a8 305#define AR_IMR_S1_QCU_TXERR 0x000003FF 306#define AR_IMR_S1_QCU_TXERR_S 0 307#define AR_IMR_S1_QCU_TXEOL 0x03FF0000 308#define AR_IMR_S1_QCU_TXEOL_S 16 309 310#define AR_IMR_S2 0x00ac 311#define AR_IMR_S2_QCU_TXURN 0x000003FF 312#define AR_IMR_S2_QCU_TXURN_S 0 313#define AR_IMR_S2_CST 0x00400000 314#define AR_IMR_S2_GTT 0x00800000 315#define AR_IMR_S2_TIM 0x01000000 316#define AR_IMR_S2_CABEND 0x02000000 317#define AR_IMR_S2_DTIMSYNC 0x04000000 318#define AR_IMR_S2_BCNTO 0x08000000 319#define AR_IMR_S2_CABTO 0x10000000 320#define AR_IMR_S2_DTIM 0x20000000 321#define AR_IMR_S2_TSFOOR 0x40000000 322 323#define AR_IMR_S3 0x00b0 324#define AR_IMR_S3_QCU_QCBROVF 0x000003FF 325#define AR_IMR_S3_QCU_QCBRURN 0x03FF0000 326#define AR_IMR_S3_QCU_QCBRURN_S 16 327 328#define AR_IMR_S4 0x00b4 329#define AR_IMR_S4_QCU_QTRIG 0x000003FF 330#define AR_IMR_S4_RESV0 0xFFFFFC00 331 332#define AR_IMR_S5 0x00b8 333#define AR_IMR_S5_TIMER_TRIG 0x000000FF 334#define AR_IMR_S5_TIMER_THRESH 0x0000FF00 335 336 337#define AR_ISR_RAC 0x00c0 338#define AR_ISR_S0_S 0x00c4 339#define AR_ISR_S0_QCU_TXOK 0x000003FF 340#define AR_ISR_S0_QCU_TXOK_S 0 341#define AR_ISR_S0_QCU_TXDESC 0x03FF0000 342#define AR_ISR_S0_QCU_TXDESC_S 16 343 344#define AR_ISR_S1_S 0x00c8 345#define AR_ISR_S1_QCU_TXERR 0x000003FF 346#define AR_ISR_S1_QCU_TXERR_S 0 347#define AR_ISR_S1_QCU_TXEOL 0x03FF0000 348#define AR_ISR_S1_QCU_TXEOL_S 16 349 350#define AR_ISR_S2_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d0 : 0x00cc) 351#define AR_ISR_S3_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d4 : 0x00d0) 352#define AR_ISR_S4_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00d8 : 0x00d4) 353#define AR_ISR_S5_S (AR_SREV_9300_20_OR_LATER(ah) ? 0x00dc : 0x00d8) 354#define AR_DMADBG_0 0x00e0 355#define AR_DMADBG_1 0x00e4 356#define AR_DMADBG_2 0x00e8 357#define AR_DMADBG_3 0x00ec 358#define AR_DMADBG_4 0x00f0 359#define AR_DMADBG_5 0x00f4 360#define AR_DMADBG_6 0x00f8 361#define AR_DMADBG_7 0x00fc 362 363#define AR_NUM_QCU 10 364#define AR_QCU_0 0x0001 365#define AR_QCU_1 0x0002 366#define AR_QCU_2 0x0004 367#define AR_QCU_3 0x0008 368#define AR_QCU_4 0x0010 369#define AR_QCU_5 0x0020 370#define AR_QCU_6 0x0040 371#define AR_QCU_7 0x0080 372#define AR_QCU_8 0x0100 373#define AR_QCU_9 0x0200 374 375#define AR_Q0_TXDP 0x0800 376#define AR_Q1_TXDP 0x0804 377#define AR_Q2_TXDP 0x0808 378#define AR_Q3_TXDP 0x080c 379#define AR_Q4_TXDP 0x0810 380#define AR_Q5_TXDP 0x0814 381#define AR_Q6_TXDP 0x0818 382#define AR_Q7_TXDP 0x081c 383#define AR_Q8_TXDP 0x0820 384#define AR_Q9_TXDP 0x0824 385#define AR_QTXDP(_i) (AR_Q0_TXDP + ((_i)<<2)) 386 387#define AR_Q_STATUS_RING_START 0x830 388#define AR_Q_STATUS_RING_END 0x834 389 390#define AR_Q_TXE 0x0840 391#define AR_Q_TXE_M 0x000003FF 392 393#define AR_Q_TXD 0x0880 394#define AR_Q_TXD_M 0x000003FF 395 396#define AR_Q0_CBRCFG 0x08c0 397#define AR_Q1_CBRCFG 0x08c4 398#define AR_Q2_CBRCFG 0x08c8 399#define AR_Q3_CBRCFG 0x08cc 400#define AR_Q4_CBRCFG 0x08d0 401#define AR_Q5_CBRCFG 0x08d4 402#define AR_Q6_CBRCFG 0x08d8 403#define AR_Q7_CBRCFG 0x08dc 404#define AR_Q8_CBRCFG 0x08e0 405#define AR_Q9_CBRCFG 0x08e4 406#define AR_QCBRCFG(_i) (AR_Q0_CBRCFG + ((_i)<<2)) 407#define AR_Q_CBRCFG_INTERVAL 0x00FFFFFF 408#define AR_Q_CBRCFG_INTERVAL_S 0 409#define AR_Q_CBRCFG_OVF_THRESH 0xFF000000 410#define AR_Q_CBRCFG_OVF_THRESH_S 24 411 412#define AR_Q0_RDYTIMECFG 0x0900 413#define AR_Q1_RDYTIMECFG 0x0904 414#define AR_Q2_RDYTIMECFG 0x0908 415#define AR_Q3_RDYTIMECFG 0x090c 416#define AR_Q4_RDYTIMECFG 0x0910 417#define AR_Q5_RDYTIMECFG 0x0914 418#define AR_Q6_RDYTIMECFG 0x0918 419#define AR_Q7_RDYTIMECFG 0x091c 420#define AR_Q8_RDYTIMECFG 0x0920 421#define AR_Q9_RDYTIMECFG 0x0924 422#define AR_QRDYTIMECFG(_i) (AR_Q0_RDYTIMECFG + ((_i)<<2)) 423#define AR_Q_RDYTIMECFG_DURATION 0x00FFFFFF 424#define AR_Q_RDYTIMECFG_DURATION_S 0 425#define AR_Q_RDYTIMECFG_EN 0x01000000 426 427#define AR_Q_ONESHOTARM_SC 0x0940 428#define AR_Q_ONESHOTARM_SC_M 0x000003FF 429#define AR_Q_ONESHOTARM_SC_RESV0 0xFFFFFC00 430 431#define AR_Q_ONESHOTARM_CC 0x0980 432#define AR_Q_ONESHOTARM_CC_M 0x000003FF 433#define AR_Q_ONESHOTARM_CC_RESV0 0xFFFFFC00 434 435#define AR_Q0_MISC 0x09c0 436#define AR_Q1_MISC 0x09c4 437#define AR_Q2_MISC 0x09c8 438#define AR_Q3_MISC 0x09cc 439#define AR_Q4_MISC 0x09d0 440#define AR_Q5_MISC 0x09d4 441#define AR_Q6_MISC 0x09d8 442#define AR_Q7_MISC 0x09dc 443#define AR_Q8_MISC 0x09e0 444#define AR_Q9_MISC 0x09e4 445#define AR_QMISC(_i) (AR_Q0_MISC + ((_i)<<2)) 446#define AR_Q_MISC_FSP 0x0000000F 447#define AR_Q_MISC_FSP_ASAP 0 448#define AR_Q_MISC_FSP_CBR 1 449#define AR_Q_MISC_FSP_DBA_GATED 2 450#define AR_Q_MISC_FSP_TIM_GATED 3 451#define AR_Q_MISC_FSP_BEACON_SENT_GATED 4 452#define AR_Q_MISC_FSP_BEACON_RCVD_GATED 5 453#define AR_Q_MISC_ONE_SHOT_EN 0x00000010 454#define AR_Q_MISC_CBR_INCR_DIS1 0x00000020 455#define AR_Q_MISC_CBR_INCR_DIS0 0x00000040 456#define AR_Q_MISC_BEACON_USE 0x00000080 457#define AR_Q_MISC_CBR_EXP_CNTR_LIMIT_EN 0x00000100 458#define AR_Q_MISC_RDYTIME_EXP_POLICY 0x00000200 459#define AR_Q_MISC_RESET_CBR_EXP_CTR 0x00000400 460#define AR_Q_MISC_DCU_EARLY_TERM_REQ 0x00000800 461#define AR_Q_MISC_RESV0 0xFFFFF000 462 463#define AR_Q0_STS 0x0a00 464#define AR_Q1_STS 0x0a04 465#define AR_Q2_STS 0x0a08 466#define AR_Q3_STS 0x0a0c 467#define AR_Q4_STS 0x0a10 468#define AR_Q5_STS 0x0a14 469#define AR_Q6_STS 0x0a18 470#define AR_Q7_STS 0x0a1c 471#define AR_Q8_STS 0x0a20 472#define AR_Q9_STS 0x0a24 473#define AR_QSTS(_i) (AR_Q0_STS + ((_i)<<2)) 474#define AR_Q_STS_PEND_FR_CNT 0x00000003 475#define AR_Q_STS_RESV0 0x000000FC 476#define AR_Q_STS_CBR_EXP_CNT 0x0000FF00 477#define AR_Q_STS_RESV1 0xFFFF0000 478 479#define AR_Q_RDYTIMESHDN 0x0a40 480#define AR_Q_RDYTIMESHDN_M 0x000003FF 481 482/* MAC Descriptor CRC check */ 483#define AR_Q_DESC_CRCCHK 0xa44 484/* Enable CRC check on the descriptor fetched from host */ 485#define AR_Q_DESC_CRCCHK_EN 1 486 487#define AR_NUM_DCU 10 488#define AR_DCU_0 0x0001 489#define AR_DCU_1 0x0002 490#define AR_DCU_2 0x0004 491#define AR_DCU_3 0x0008 492#define AR_DCU_4 0x0010 493#define AR_DCU_5 0x0020 494#define AR_DCU_6 0x0040 495#define AR_DCU_7 0x0080 496#define AR_DCU_8 0x0100 497#define AR_DCU_9 0x0200 498 499#define AR_D0_QCUMASK 0x1000 500#define AR_D1_QCUMASK 0x1004 501#define AR_D2_QCUMASK 0x1008 502#define AR_D3_QCUMASK 0x100c 503#define AR_D4_QCUMASK 0x1010 504#define AR_D5_QCUMASK 0x1014 505#define AR_D6_QCUMASK 0x1018 506#define AR_D7_QCUMASK 0x101c 507#define AR_D8_QCUMASK 0x1020 508#define AR_D9_QCUMASK 0x1024 509#define AR_DQCUMASK(_i) (AR_D0_QCUMASK + ((_i)<<2)) 510#define AR_D_QCUMASK 0x000003FF 511#define AR_D_QCUMASK_RESV0 0xFFFFFC00 512 513#define AR_D_TXBLK_CMD 0x1038 514#define AR_D_TXBLK_DATA(i) (AR_D_TXBLK_CMD+(i)) 515 516#define AR_D0_LCL_IFS 0x1040 517#define AR_D1_LCL_IFS 0x1044 518#define AR_D2_LCL_IFS 0x1048 519#define AR_D3_LCL_IFS 0x104c 520#define AR_D4_LCL_IFS 0x1050 521#define AR_D5_LCL_IFS 0x1054 522#define AR_D6_LCL_IFS 0x1058 523#define AR_D7_LCL_IFS 0x105c 524#define AR_D8_LCL_IFS 0x1060 525#define AR_D9_LCL_IFS 0x1064 526#define AR_DLCL_IFS(_i) (AR_D0_LCL_IFS + ((_i)<<2)) 527#define AR_D_LCL_IFS_CWMIN 0x000003FF 528#define AR_D_LCL_IFS_CWMIN_S 0 529#define AR_D_LCL_IFS_CWMAX 0x000FFC00 530#define AR_D_LCL_IFS_CWMAX_S 10 531#define AR_D_LCL_IFS_AIFS 0x0FF00000 532#define AR_D_LCL_IFS_AIFS_S 20 533 534#define AR_D_LCL_IFS_RESV0 0xF0000000 535 536#define AR_D0_RETRY_LIMIT 0x1080 537#define AR_D1_RETRY_LIMIT 0x1084 538#define AR_D2_RETRY_LIMIT 0x1088 539#define AR_D3_RETRY_LIMIT 0x108c 540#define AR_D4_RETRY_LIMIT 0x1090 541#define AR_D5_RETRY_LIMIT 0x1094 542#define AR_D6_RETRY_LIMIT 0x1098 543#define AR_D7_RETRY_LIMIT 0x109c 544#define AR_D8_RETRY_LIMIT 0x10a0 545#define AR_D9_RETRY_LIMIT 0x10a4 546#define AR_DRETRY_LIMIT(_i) (AR_D0_RETRY_LIMIT + ((_i)<<2)) 547#define AR_D_RETRY_LIMIT_FR_SH 0x0000000F 548#define AR_D_RETRY_LIMIT_FR_SH_S 0 549#define AR_D_RETRY_LIMIT_STA_SH 0x00003F00 550#define AR_D_RETRY_LIMIT_STA_SH_S 8 551#define AR_D_RETRY_LIMIT_STA_LG 0x000FC000 552#define AR_D_RETRY_LIMIT_STA_LG_S 14 553#define AR_D_RETRY_LIMIT_RESV0 0xFFF00000 554 555#define AR_D0_CHNTIME 0x10c0 556#define AR_D1_CHNTIME 0x10c4 557#define AR_D2_CHNTIME 0x10c8 558#define AR_D3_CHNTIME 0x10cc 559#define AR_D4_CHNTIME 0x10d0 560#define AR_D5_CHNTIME 0x10d4 561#define AR_D6_CHNTIME 0x10d8 562#define AR_D7_CHNTIME 0x10dc 563#define AR_D8_CHNTIME 0x10e0 564#define AR_D9_CHNTIME 0x10e4 565#define AR_DCHNTIME(_i) (AR_D0_CHNTIME + ((_i)<<2)) 566#define AR_D_CHNTIME_DUR 0x000FFFFF 567#define AR_D_CHNTIME_DUR_S 0 568#define AR_D_CHNTIME_EN 0x00100000 569#define AR_D_CHNTIME_RESV0 0xFFE00000 570 571#define AR_D0_MISC 0x1100 572#define AR_D1_MISC 0x1104 573#define AR_D2_MISC 0x1108 574#define AR_D3_MISC 0x110c 575#define AR_D4_MISC 0x1110 576#define AR_D5_MISC 0x1114 577#define AR_D6_MISC 0x1118 578#define AR_D7_MISC 0x111c 579#define AR_D8_MISC 0x1120 580#define AR_D9_MISC 0x1124 581#define AR_DMISC(_i) (AR_D0_MISC + ((_i)<<2)) 582#define AR_D_MISC_BKOFF_THRESH 0x0000003F 583#define AR_D_MISC_RETRY_CNT_RESET_EN 0x00000040 584#define AR_D_MISC_CW_RESET_EN 0x00000080 585#define AR_D_MISC_FRAG_WAIT_EN 0x00000100 586#define AR_D_MISC_FRAG_BKOFF_EN 0x00000200 587#define AR_D_MISC_CW_BKOFF_EN 0x00001000 588#define AR_D_MISC_VIR_COL_HANDLING 0x0000C000 589#define AR_D_MISC_VIR_COL_HANDLING_S 14 590#define AR_D_MISC_VIR_COL_HANDLING_DEFAULT 0 591#define AR_D_MISC_VIR_COL_HANDLING_IGNORE 1 592#define AR_D_MISC_BEACON_USE 0x00010000 593#define AR_D_MISC_ARB_LOCKOUT_CNTRL 0x00060000 594#define AR_D_MISC_ARB_LOCKOUT_CNTRL_S 17 595#define AR_D_MISC_ARB_LOCKOUT_CNTRL_NONE 0 596#define AR_D_MISC_ARB_LOCKOUT_CNTRL_INTRA_FR 1 597#define AR_D_MISC_ARB_LOCKOUT_CNTRL_GLOBAL 2 598#define AR_D_MISC_ARB_LOCKOUT_IGNORE 0x00080000 599#define AR_D_MISC_SEQ_NUM_INCR_DIS 0x00100000 600#define AR_D_MISC_POST_FR_BKOFF_DIS 0x00200000 601#define AR_D_MISC_VIT_COL_CW_BKOFF_EN 0x00400000 602#define AR_D_MISC_BLOWN_IFS_RETRY_EN 0x00800000 603#define AR_D_MISC_RESV0 0xFF000000 604 605#define AR_D_SEQNUM 0x1140 606 607#define AR_D_GBL_IFS_SIFS 0x1030 608#define AR_D_GBL_IFS_SIFS_M 0x0000FFFF 609#define AR_D_GBL_IFS_SIFS_ASYNC_FIFO_DUR 0x000003AB 610#define AR_D_GBL_IFS_SIFS_RESV0 0xFFFFFFFF 611 612#define AR_D_TXBLK_BASE 0x1038 613#define AR_D_TXBLK_WRITE_BITMASK 0x0000FFFF 614#define AR_D_TXBLK_WRITE_BITMASK_S 0 615#define AR_D_TXBLK_WRITE_SLICE 0x000F0000 616#define AR_D_TXBLK_WRITE_SLICE_S 16 617#define AR_D_TXBLK_WRITE_DCU 0x00F00000 618#define AR_D_TXBLK_WRITE_DCU_S 20 619#define AR_D_TXBLK_WRITE_COMMAND 0x0F000000 620#define AR_D_TXBLK_WRITE_COMMAND_S 24 621 622#define AR_D_GBL_IFS_SLOT 0x1070 623#define AR_D_GBL_IFS_SLOT_M 0x0000FFFF 624#define AR_D_GBL_IFS_SLOT_RESV0 0xFFFF0000 625#define AR_D_GBL_IFS_SLOT_ASYNC_FIFO_DUR 0x00000420 626 627#define AR_D_GBL_IFS_EIFS 0x10b0 628#define AR_D_GBL_IFS_EIFS_M 0x0000FFFF 629#define AR_D_GBL_IFS_EIFS_RESV0 0xFFFF0000 630#define AR_D_GBL_IFS_EIFS_ASYNC_FIFO_DUR 0x0000A5EB 631 632#define AR_D_GBL_IFS_MISC 0x10f0 633#define AR_D_GBL_IFS_MISC_LFSR_SLICE_SEL 0x00000007 634#define AR_D_GBL_IFS_MISC_TURBO_MODE 0x00000008 635#define AR_D_GBL_IFS_MISC_USEC_DURATION 0x000FFC00 636#define AR_D_GBL_IFS_MISC_DCU_ARBITER_DLY 0x00300000 637#define AR_D_GBL_IFS_MISC_RANDOM_LFSR_SLICE_DIS 0x01000000 638#define AR_D_GBL_IFS_MISC_SLOT_XMIT_WIND_LEN 0x06000000 639#define AR_D_GBL_IFS_MISC_FORCE_XMIT_SLOT_BOUND 0x08000000 640#define AR_D_GBL_IFS_MISC_IGNORE_BACKOFF 0x10000000 641 642#define AR_D_FPCTL 0x1230 643#define AR_D_FPCTL_DCU 0x0000000F 644#define AR_D_FPCTL_DCU_S 0 645#define AR_D_FPCTL_PREFETCH_EN 0x00000010 646#define AR_D_FPCTL_BURST_PREFETCH 0x00007FE0 647#define AR_D_FPCTL_BURST_PREFETCH_S 5 648 649#define AR_D_TXPSE 0x1270 650#define AR_D_TXPSE_CTRL 0x000003FF 651#define AR_D_TXPSE_RESV0 0x0000FC00 652#define AR_D_TXPSE_STATUS 0x00010000 653#define AR_D_TXPSE_RESV1 0xFFFE0000 654 655#define AR_D_TXSLOTMASK 0x12f0 656#define AR_D_TXSLOTMASK_NUM 0x0000000F 657 658#define AR_CFG_LED 0x1f04 659#define AR_CFG_SCLK_RATE_IND 0x00000003 660#define AR_CFG_SCLK_RATE_IND_S 0 661#define AR_CFG_SCLK_32MHZ 0x00000000 662#define AR_CFG_SCLK_4MHZ 0x00000001 663#define AR_CFG_SCLK_1MHZ 0x00000002 664#define AR_CFG_SCLK_32KHZ 0x00000003 665#define AR_CFG_LED_BLINK_SLOW 0x00000008 666#define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 667#define AR_CFG_LED_MODE_SEL 0x00000380 668#define AR_CFG_LED_MODE_SEL_S 7 669#define AR_CFG_LED_POWER 0x00000280 670#define AR_CFG_LED_POWER_S 7 671#define AR_CFG_LED_NETWORK 0x00000300 672#define AR_CFG_LED_NETWORK_S 7 673#define AR_CFG_LED_MODE_PROP 0x0 674#define AR_CFG_LED_MODE_RPROP 0x1 675#define AR_CFG_LED_MODE_SPLIT 0x2 676#define AR_CFG_LED_MODE_RAND 0x3 677#define AR_CFG_LED_MODE_POWER_OFF 0x4 678#define AR_CFG_LED_MODE_POWER_ON 0x5 679#define AR_CFG_LED_MODE_NETWORK_OFF 0x4 680#define AR_CFG_LED_MODE_NETWORK_ON 0x6 681#define AR_CFG_LED_ASSOC_CTL 0x00000c00 682#define AR_CFG_LED_ASSOC_CTL_S 10 683#define AR_CFG_LED_ASSOC_NONE 0x0 684#define AR_CFG_LED_ASSOC_ACTIVE 0x1 685#define AR_CFG_LED_ASSOC_PENDING 0x2 686 687#define AR_CFG_LED_BLINK_SLOW 0x00000008 688#define AR_CFG_LED_BLINK_SLOW_S 3 689 690#define AR_CFG_LED_BLINK_THRESH_SEL 0x00000070 691#define AR_CFG_LED_BLINK_THRESH_SEL_S 4 692 693#define AR_MAC_SLEEP 0x1f00 694#define AR_MAC_SLEEP_MAC_AWAKE 0x00000000 695#define AR_MAC_SLEEP_MAC_ASLEEP 0x00000001 696 697#define AR_RC 0x4000 698#define AR_RC_AHB 0x00000001 699#define AR_RC_APB 0x00000002 700#define AR_RC_HOSTIF 0x00000100 701 702#define AR_WA 0x4004 703#define AR_WA_BIT6 (1 << 6) 704#define AR_WA_BIT7 (1 << 7) 705#define AR_WA_BIT23 (1 << 23) 706#define AR_WA_D3_L1_DISABLE (1 << 14) 707#define AR_WA_D3_TO_L1_DISABLE_REAL (1 << 16) 708#define AR_WA_ASPM_TIMER_BASED_DISABLE (1 << 17) 709#define AR_WA_RESET_EN (1 << 18) /* Sw Control to enable PCI-Reset to POR (bit 15) */ 710#define AR_WA_ANALOG_SHIFT (1 << 20) 711#define AR_WA_POR_SHORT (1 << 21) /* PCI-E Phy reset control */ 712#define AR_WA_BIT22 (1 << 22) 713#define AR9285_WA_DEFAULT 0x004a050b 714#define AR9280_WA_DEFAULT 0x0040073b 715#define AR_WA_DEFAULT 0x0000073f 716 717 718#define AR_PM_STATE 0x4008 719#define AR_PM_STATE_PME_D3COLD_VAUX 0x00100000 720 721#define AR_HOST_TIMEOUT 0x4018 722#define AR_HOST_TIMEOUT_APB_CNTR 0x0000FFFF 723#define AR_HOST_TIMEOUT_APB_CNTR_S 0 724#define AR_HOST_TIMEOUT_LCL_CNTR 0xFFFF0000 725#define AR_HOST_TIMEOUT_LCL_CNTR_S 16 726 727#define AR_EEPROM 0x401c 728#define AR_EEPROM_ABSENT 0x00000100 729#define AR_EEPROM_CORRUPT 0x00000200 730#define AR_EEPROM_PROT_MASK 0x03FFFC00 731#define AR_EEPROM_PROT_MASK_S 10 732 733#define EEPROM_PROTECT_RP_0_31 0x0001 734#define EEPROM_PROTECT_WP_0_31 0x0002 735#define EEPROM_PROTECT_RP_32_63 0x0004 736#define EEPROM_PROTECT_WP_32_63 0x0008 737#define EEPROM_PROTECT_RP_64_127 0x0010 738#define EEPROM_PROTECT_WP_64_127 0x0020 739#define EEPROM_PROTECT_RP_128_191 0x0040 740#define EEPROM_PROTECT_WP_128_191 0x0080 741#define EEPROM_PROTECT_RP_192_255 0x0100 742#define EEPROM_PROTECT_WP_192_255 0x0200 743#define EEPROM_PROTECT_RP_256_511 0x0400 744#define EEPROM_PROTECT_WP_256_511 0x0800 745#define EEPROM_PROTECT_RP_512_1023 0x1000 746#define EEPROM_PROTECT_WP_512_1023 0x2000 747#define EEPROM_PROTECT_RP_1024_2047 0x4000 748#define EEPROM_PROTECT_WP_1024_2047 0x8000 749 750#define AR_SREV \ 751 ((AR_SREV_9100(ah)) ? 0x0600 : 0x4020) 752 753#define AR_SREV_ID \ 754 ((AR_SREV_9100(ah)) ? 0x00000FFF : 0x000000FF) 755#define AR_SREV_VERSION 0x000000F0 756#define AR_SREV_VERSION_S 4 757#define AR_SREV_REVISION 0x00000007 758 759#define AR_SREV_ID2 0xFFFFFFFF 760#define AR_SREV_VERSION2 0xFFFC0000 761#define AR_SREV_VERSION2_S 18 762#define AR_SREV_TYPE2 0x0003F000 763#define AR_SREV_TYPE2_S 12 764#define AR_SREV_TYPE2_CHAIN 0x00001000 765#define AR_SREV_TYPE2_HOST_MODE 0x00002000 766#define AR_SREV_REVISION2 0x00000F00 767#define AR_SREV_REVISION2_S 8 768 769#define AR_SREV_VERSION_5416_PCI 0xD 770#define AR_SREV_VERSION_5416_PCIE 0xC 771#define AR_SREV_REVISION_5416_10 0 772#define AR_SREV_REVISION_5416_20 1 773#define AR_SREV_REVISION_5416_22 2 774#define AR_SREV_VERSION_9100 0x14 775#define AR_SREV_VERSION_9160 0x40 776#define AR_SREV_REVISION_9160_10 0 777#define AR_SREV_REVISION_9160_11 1 778#define AR_SREV_VERSION_9280 0x80 779#define AR_SREV_REVISION_9280_10 0 780#define AR_SREV_REVISION_9280_20 1 781#define AR_SREV_REVISION_9280_21 2 782#define AR_SREV_VERSION_9285 0xC0 783#define AR_SREV_REVISION_9285_10 0 784#define AR_SREV_REVISION_9285_11 1 785#define AR_SREV_REVISION_9285_12 2 786#define AR_SREV_VERSION_9287 0x180 787#define AR_SREV_REVISION_9287_10 0 788#define AR_SREV_REVISION_9287_11 1 789#define AR_SREV_REVISION_9287_12 2 790#define AR_SREV_REVISION_9287_13 3 791#define AR_SREV_VERSION_9271 0x140 792#define AR_SREV_REVISION_9271_10 0 793#define AR_SREV_REVISION_9271_11 1 794#define AR_SREV_VERSION_9300 0x1c0 795#define AR_SREV_REVISION_9300_20 2 /* 2.0 and 2.1 */ 796 797#define AR_SREV_5416(_ah) \ 798 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCI) || \ 799 ((_ah)->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)) 800#define AR_SREV_5416_20_OR_LATER(_ah) \ 801 (((AR_SREV_5416(_ah)) && \ 802 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_20)) || \ 803 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) 804#define AR_SREV_5416_22_OR_LATER(_ah) \ 805 (((AR_SREV_5416(_ah)) && \ 806 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_5416_22)) || \ 807 ((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) 808 809#define AR_SREV_9100(ah) \ 810 ((ah->hw_version.macVersion) == AR_SREV_VERSION_9100) 811#define AR_SREV_9100_OR_LATER(_ah) \ 812 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9100)) 813 814#define AR_SREV_9160(_ah) \ 815 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9160)) 816#define AR_SREV_9160_10_OR_LATER(_ah) \ 817 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9160)) 818#define AR_SREV_9160_11(_ah) \ 819 (AR_SREV_9160(_ah) && \ 820 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9160_11)) 821#define AR_SREV_9280(_ah) \ 822 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280)) 823#define AR_SREV_9280_10_OR_LATER(_ah) \ 824 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9280)) 825#define AR_SREV_9280_20(_ah) \ 826 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \ 827 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20)) 828#define AR_SREV_9280_20_OR_LATER(_ah) \ 829 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9280) || \ 830 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9280) && \ 831 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9280_20))) 832 833#define AR_SREV_9285(_ah) \ 834 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9285)) 835#define AR_SREV_9285_10_OR_LATER(_ah) \ 836 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9285)) 837#define AR_SREV_9285_11(_ah) \ 838 (AR_SREV_9285(ah) && \ 839 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_11)) 840#define AR_SREV_9285_11_OR_LATER(_ah) \ 841 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \ 842 (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \ 843 AR_SREV_REVISION_9285_11))) 844#define AR_SREV_9285_12(_ah) \ 845 (AR_SREV_9285(ah) && \ 846 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9285_12)) 847#define AR_SREV_9285_12_OR_LATER(_ah) \ 848 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9285) || \ 849 (AR_SREV_9285(ah) && ((_ah)->hw_version.macRev >= \ 850 AR_SREV_REVISION_9285_12))) 851 852#define AR_SREV_9287(_ah) \ 853 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287)) 854#define AR_SREV_9287_10_OR_LATER(_ah) \ 855 (((_ah)->hw_version.macVersion >= AR_SREV_VERSION_9287)) 856#define AR_SREV_9287_10(_ah) \ 857 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 858 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_10)) 859#define AR_SREV_9287_11(_ah) \ 860 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 861 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_11)) 862#define AR_SREV_9287_11_OR_LATER(_ah) \ 863 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \ 864 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 865 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_11))) 866#define AR_SREV_9287_12(_ah) \ 867 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 868 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9287_12)) 869#define AR_SREV_9287_12_OR_LATER(_ah) \ 870 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \ 871 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 872 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_12))) 873#define AR_SREV_9287_13_OR_LATER(_ah) \ 874 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9287) || \ 875 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9287) && \ 876 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9287_13))) 877 878#define AR_SREV_9271(_ah) \ 879 (((_ah))->hw_version.macVersion == AR_SREV_VERSION_9271) 880#define AR_SREV_9271_10(_ah) \ 881 (AR_SREV_9271(_ah) && \ 882 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_10)) 883#define AR_SREV_9271_11(_ah) \ 884 (AR_SREV_9271(_ah) && \ 885 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9271_11)) 886 887#define AR_SREV_9300(_ah) \ 888 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300)) 889#define AR_SREV_9300_20(_ah) \ 890 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \ 891 ((_ah)->hw_version.macRev == AR_SREV_REVISION_9300_20)) 892#define AR_SREV_9300_20_OR_LATER(_ah) \ 893 (((_ah)->hw_version.macVersion > AR_SREV_VERSION_9300) || \ 894 (((_ah)->hw_version.macVersion == AR_SREV_VERSION_9300) && \ 895 ((_ah)->hw_version.macRev >= AR_SREV_REVISION_9300_20))) 896 897#define AR_SREV_9285E_20(_ah) \ 898 (AR_SREV_9285_12_OR_LATER(_ah) && \ 899 ((REG_READ(_ah, AR_AN_SYNTH9) & 0x7) == 0x1)) 900 901#define AR_DEVID_7010(_ah) \ 902 (((_ah)->hw_version.devid == 0x7010) || \ 903 ((_ah)->hw_version.devid == 0x7015) || \ 904 ((_ah)->hw_version.devid == 0x9018) || \ 905 ((_ah)->hw_version.devid == 0xA704) || \ 906 ((_ah)->hw_version.devid == 0x1200)) 907 908#define AR9287_HTC_DEVID(_ah) \ 909 (((_ah)->hw_version.devid == 0x7015) || \ 910 ((_ah)->hw_version.devid == 0x1200)) 911 912#define AR_RADIO_SREV_MAJOR 0xf0 913#define AR_RAD5133_SREV_MAJOR 0xc0 914#define AR_RAD2133_SREV_MAJOR 0xd0 915#define AR_RAD5122_SREV_MAJOR 0xe0 916#define AR_RAD2122_SREV_MAJOR 0xf0 917 918#define AR_AHB_MODE 0x4024 919#define AR_AHB_EXACT_WR_EN 0x00000000 920#define AR_AHB_BUF_WR_EN 0x00000001 921#define AR_AHB_EXACT_RD_EN 0x00000000 922#define AR_AHB_CACHELINE_RD_EN 0x00000002 923#define AR_AHB_PREFETCH_RD_EN 0x00000004 924#define AR_AHB_PAGE_SIZE_1K 0x00000000 925#define AR_AHB_PAGE_SIZE_2K 0x00000008 926#define AR_AHB_PAGE_SIZE_4K 0x00000010 927#define AR_AHB_CUSTOM_BURST_EN 0x000000C0 928#define AR_AHB_CUSTOM_BURST_EN_S 6 929#define AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL 3 930 931#define AR_INTR_RTC_IRQ 0x00000001 932#define AR_INTR_MAC_IRQ 0x00000002 933#define AR_INTR_EEP_PROT_ACCESS 0x00000004 934#define AR_INTR_MAC_AWAKE 0x00020000 935#define AR_INTR_MAC_ASLEEP 0x00040000 936#define AR_INTR_SPURIOUS 0xFFFFFFFF 937 938 939#define AR_INTR_SYNC_CAUSE_CLR 0x4028 940 941#define AR_INTR_SYNC_CAUSE 0x4028 942 943#define AR_INTR_SYNC_ENABLE 0x402c 944#define AR_INTR_SYNC_ENABLE_GPIO 0xFFFC0000 945#define AR_INTR_SYNC_ENABLE_GPIO_S 18 946 947enum { 948 AR_INTR_SYNC_RTC_IRQ = 0x00000001, 949 AR_INTR_SYNC_MAC_IRQ = 0x00000002, 950 AR_INTR_SYNC_EEPROM_ILLEGAL_ACCESS = 0x00000004, 951 AR_INTR_SYNC_APB_TIMEOUT = 0x00000008, 952 AR_INTR_SYNC_PCI_MODE_CONFLICT = 0x00000010, 953 AR_INTR_SYNC_HOST1_FATAL = 0x00000020, 954 AR_INTR_SYNC_HOST1_PERR = 0x00000040, 955 AR_INTR_SYNC_TRCV_FIFO_PERR = 0x00000080, 956 AR_INTR_SYNC_RADM_CPL_EP = 0x00000100, 957 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT = 0x00000200, 958 AR_INTR_SYNC_RADM_CPL_TLP_ABORT = 0x00000400, 959 AR_INTR_SYNC_RADM_CPL_ECRC_ERR = 0x00000800, 960 AR_INTR_SYNC_RADM_CPL_TIMEOUT = 0x00001000, 961 AR_INTR_SYNC_LOCAL_TIMEOUT = 0x00002000, 962 AR_INTR_SYNC_PM_ACCESS = 0x00004000, 963 AR_INTR_SYNC_MAC_AWAKE = 0x00008000, 964 AR_INTR_SYNC_MAC_ASLEEP = 0x00010000, 965 AR_INTR_SYNC_MAC_SLEEP_ACCESS = 0x00020000, 966 AR_INTR_SYNC_ALL = 0x0003FFFF, 967 968 969 AR_INTR_SYNC_DEFAULT = (AR_INTR_SYNC_HOST1_FATAL | 970 AR_INTR_SYNC_HOST1_PERR | 971 AR_INTR_SYNC_RADM_CPL_EP | 972 AR_INTR_SYNC_RADM_CPL_DLLP_ABORT | 973 AR_INTR_SYNC_RADM_CPL_TLP_ABORT | 974 AR_INTR_SYNC_RADM_CPL_ECRC_ERR | 975 AR_INTR_SYNC_RADM_CPL_TIMEOUT | 976 AR_INTR_SYNC_LOCAL_TIMEOUT | 977 AR_INTR_SYNC_MAC_SLEEP_ACCESS), 978 979 AR_INTR_SYNC_SPURIOUS = 0xFFFFFFFF, 980 981}; 982 983#define AR_INTR_ASYNC_MASK 0x4030 984#define AR_INTR_ASYNC_MASK_GPIO 0xFFFC0000 985#define AR_INTR_ASYNC_MASK_GPIO_S 18 986 987#define AR_INTR_SYNC_MASK 0x4034 988#define AR_INTR_SYNC_MASK_GPIO 0xFFFC0000 989#define AR_INTR_SYNC_MASK_GPIO_S 18 990 991#define AR_INTR_ASYNC_CAUSE_CLR 0x4038 992#define AR_INTR_ASYNC_CAUSE 0x4038 993 994#define AR_INTR_ASYNC_ENABLE 0x403c 995#define AR_INTR_ASYNC_ENABLE_GPIO 0xFFFC0000 996#define AR_INTR_ASYNC_ENABLE_GPIO_S 18 997 998#define AR_PCIE_SERDES 0x4040 999#define AR_PCIE_SERDES2 0x4044 1000#define AR_PCIE_PM_CTRL 0x4014 1001#define AR_PCIE_PM_CTRL_ENA 0x00080000 1002 1003#define AR_NUM_GPIO 14 1004#define AR928X_NUM_GPIO 10 1005#define AR9285_NUM_GPIO 12 1006#define AR9287_NUM_GPIO 11 1007#define AR9271_NUM_GPIO 16 1008#define AR9300_NUM_GPIO 17 1009#define AR7010_NUM_GPIO 16 1010 1011#define AR_GPIO_IN_OUT 0x4048 1012#define AR_GPIO_IN_VAL 0x0FFFC000 1013#define AR_GPIO_IN_VAL_S 14 1014#define AR928X_GPIO_IN_VAL 0x000FFC00 1015#define AR928X_GPIO_IN_VAL_S 10 1016#define AR9285_GPIO_IN_VAL 0x00FFF000 1017#define AR9285_GPIO_IN_VAL_S 12 1018#define AR9287_GPIO_IN_VAL 0x003FF800 1019#define AR9287_GPIO_IN_VAL_S 11 1020#define AR9271_GPIO_IN_VAL 0xFFFF0000 1021#define AR9271_GPIO_IN_VAL_S 16 1022#define AR7010_GPIO_IN_VAL 0x0000FFFF 1023#define AR7010_GPIO_IN_VAL_S 0 1024 1025#define AR_GPIO_IN 0x404c 1026#define AR9300_GPIO_IN_VAL 0x0001FFFF 1027#define AR9300_GPIO_IN_VAL_S 0 1028 1029#define AR_GPIO_OE_OUT (AR_SREV_9300_20_OR_LATER(ah) ? 0x4050 : 0x404c) 1030#define AR_GPIO_OE_OUT_DRV 0x3 1031#define AR_GPIO_OE_OUT_DRV_NO 0x0 1032#define AR_GPIO_OE_OUT_DRV_LOW 0x1 1033#define AR_GPIO_OE_OUT_DRV_HI 0x2 1034#define AR_GPIO_OE_OUT_DRV_ALL 0x3 1035 1036#define AR7010_GPIO_OE 0x52000 1037#define AR7010_GPIO_OE_MASK 0x1 1038#define AR7010_GPIO_OE_AS_OUTPUT 0x0 1039#define AR7010_GPIO_OE_AS_INPUT 0x1 1040#define AR7010_GPIO_IN 0x52004 1041#define AR7010_GPIO_OUT 0x52008 1042#define AR7010_GPIO_SET 0x5200C 1043#define AR7010_GPIO_CLEAR 0x52010 1044#define AR7010_GPIO_INT 0x52014 1045#define AR7010_GPIO_INT_TYPE 0x52018 1046#define AR7010_GPIO_INT_POLARITY 0x5201C 1047#define AR7010_GPIO_PENDING 0x52020 1048#define AR7010_GPIO_INT_MASK 0x52024 1049#define AR7010_GPIO_FUNCTION 0x52028 1050 1051#define AR_GPIO_INTR_POL (AR_SREV_9300_20_OR_LATER(ah) ? 0x4058 : 0x4050) 1052#define AR_GPIO_INTR_POL_VAL 0x0001FFFF 1053#define AR_GPIO_INTR_POL_VAL_S 0 1054 1055#define AR_GPIO_INPUT_EN_VAL (AR_SREV_9300_20_OR_LATER(ah) ? 0x405c : 0x4054) 1056#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF 0x00000004 1057#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_S 2 1058#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF 0x00000008 1059#define AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_S 3 1060#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_DEF 0x00000010 1061#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_S 4 1062#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF 0x00000080 1063#define AR_GPIO_INPUT_EN_VAL_RFSILENT_DEF_S 7 1064#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB 0x00000400 1065#define AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB_S 10 1066#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB 0x00001000 1067#define AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB_S 12 1068#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB 0x00008000 1069#define AR_GPIO_INPUT_EN_VAL_RFSILENT_BB_S 15 1070#define AR_GPIO_RTC_RESET_OVERRIDE_ENABLE 0x00010000 1071#define AR_GPIO_JTAG_DISABLE 0x00020000 1072 1073#define AR_GPIO_INPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4060 : 0x4058) 1074#define AR_GPIO_INPUT_MUX1_BT_ACTIVE 0x000f0000 1075#define AR_GPIO_INPUT_MUX1_BT_ACTIVE_S 16 1076#define AR_GPIO_INPUT_MUX1_BT_PRIORITY 0x00000f00 1077#define AR_GPIO_INPUT_MUX1_BT_PRIORITY_S 8 1078 1079#define AR_GPIO_INPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4064 : 0x405c) 1080#define AR_GPIO_INPUT_MUX2_CLK25 0x0000000f 1081#define AR_GPIO_INPUT_MUX2_CLK25_S 0 1082#define AR_GPIO_INPUT_MUX2_RFSILENT 0x000000f0 1083#define AR_GPIO_INPUT_MUX2_RFSILENT_S 4 1084#define AR_GPIO_INPUT_MUX2_RTC_RESET 0x00000f00 1085#define AR_GPIO_INPUT_MUX2_RTC_RESET_S 8 1086 1087#define AR_GPIO_OUTPUT_MUX1 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4068 : 0x4060) 1088#define AR_GPIO_OUTPUT_MUX2 (AR_SREV_9300_20_OR_LATER(ah) ? 0x406c : 0x4064) 1089#define AR_GPIO_OUTPUT_MUX3 (AR_SREV_9300_20_OR_LATER(ah) ? 0x4070 : 0x4068) 1090 1091#define AR_INPUT_STATE (AR_SREV_9300_20_OR_LATER(ah) ? 0x4074 : 0x406c) 1092 1093#define AR_EEPROM_STATUS_DATA (AR_SREV_9300_20_OR_LATER(ah) ? 0x4084 : 0x407c) 1094#define AR_EEPROM_STATUS_DATA_VAL 0x0000ffff 1095#define AR_EEPROM_STATUS_DATA_VAL_S 0 1096#define AR_EEPROM_STATUS_DATA_BUSY 0x00010000 1097#define AR_EEPROM_STATUS_DATA_BUSY_ACCESS 0x00020000 1098#define AR_EEPROM_STATUS_DATA_PROT_ACCESS 0x00040000 1099#define AR_EEPROM_STATUS_DATA_ABSENT_ACCESS 0x00080000 1100 1101#define AR_OBS (AR_SREV_9300_20_OR_LATER(ah) ? 0x4088 : 0x4080) 1102 1103#define AR_GPIO_PDPU (AR_SREV_9300_20_OR_LATER(ah) ? 0x4090 : 0x4088) 1104 1105#define AR_PCIE_MSI (AR_SREV_9300_20_OR_LATER(ah) ? 0x40a4 : 0x4094) 1106#define AR_PCIE_MSI_ENABLE 0x00000001 1107 1108#define AR_INTR_PRIO_SYNC_ENABLE 0x40c4 1109#define AR_INTR_PRIO_ASYNC_MASK 0x40c8 1110#define AR_INTR_PRIO_SYNC_MASK 0x40cc 1111#define AR_INTR_PRIO_ASYNC_ENABLE 0x40d4 1112 1113#define AR_RTC_9300_PLL_DIV 0x000003ff 1114#define AR_RTC_9300_PLL_DIV_S 0 1115#define AR_RTC_9300_PLL_REFDIV 0x00003C00 1116#define AR_RTC_9300_PLL_REFDIV_S 10 1117#define AR_RTC_9300_PLL_CLKSEL 0x0000C000 1118#define AR_RTC_9300_PLL_CLKSEL_S 14 1119 1120#define AR_RTC_9160_PLL_DIV 0x000003ff 1121#define AR_RTC_9160_PLL_DIV_S 0 1122#define AR_RTC_9160_PLL_REFDIV 0x00003C00 1123#define AR_RTC_9160_PLL_REFDIV_S 10 1124#define AR_RTC_9160_PLL_CLKSEL 0x0000C000 1125#define AR_RTC_9160_PLL_CLKSEL_S 14 1126 1127#define AR_RTC_BASE 0x00020000 1128#define AR_RTC_RC \ 1129 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0000) : 0x7000) 1130#define AR_RTC_RC_M 0x00000003 1131#define AR_RTC_RC_MAC_WARM 0x00000001 1132#define AR_RTC_RC_MAC_COLD 0x00000002 1133#define AR_RTC_RC_COLD_RESET 0x00000004 1134#define AR_RTC_RC_WARM_RESET 0x00000008 1135 1136/* Crystal Control */ 1137#define AR_RTC_XTAL_CONTROL 0x7004 1138 1139/* Reg Control 0 */ 1140#define AR_RTC_REG_CONTROL0 0x7008 1141 1142/* Reg Control 1 */ 1143#define AR_RTC_REG_CONTROL1 0x700c 1144#define AR_RTC_REG_CONTROL1_SWREG_PROGRAM 0x00000001 1145 1146#define AR_RTC_PLL_CONTROL \ 1147 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0014) : 0x7014) 1148 1149#define AR_RTC_PLL_DIV 0x0000001f 1150#define AR_RTC_PLL_DIV_S 0 1151#define AR_RTC_PLL_DIV2 0x00000020 1152#define AR_RTC_PLL_REFDIV_5 0x000000c0 1153#define AR_RTC_PLL_CLKSEL 0x00000300 1154#define AR_RTC_PLL_CLKSEL_S 8 1155 1156#define AR_RTC_RESET \ 1157 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0040) : 0x7040) 1158#define AR_RTC_RESET_EN (0x00000001) 1159 1160#define AR_RTC_STATUS \ 1161 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0044) : 0x7044) 1162 1163#define AR_RTC_STATUS_M \ 1164 ((AR_SREV_9100(ah)) ? 0x0000003f : 0x0000000f) 1165 1166#define AR_RTC_PM_STATUS_M 0x0000000f 1167 1168#define AR_RTC_STATUS_SHUTDOWN 0x00000001 1169#define AR_RTC_STATUS_ON 0x00000002 1170#define AR_RTC_STATUS_SLEEP 0x00000004 1171#define AR_RTC_STATUS_WAKEUP 0x00000008 1172 1173#define AR_RTC_SLEEP_CLK \ 1174 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0048) : 0x7048) 1175#define AR_RTC_FORCE_DERIVED_CLK 0x2 1176#define AR_RTC_FORCE_SWREG_PRD 0x00000004 1177 1178#define AR_RTC_FORCE_WAKE \ 1179 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x004c) : 0x704c) 1180#define AR_RTC_FORCE_WAKE_EN 0x00000001 1181#define AR_RTC_FORCE_WAKE_ON_INT 0x00000002 1182 1183 1184#define AR_RTC_INTR_CAUSE \ 1185 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0050) : 0x7050) 1186 1187#define AR_RTC_INTR_ENABLE \ 1188 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0054) : 0x7054) 1189 1190#define AR_RTC_INTR_MASK \ 1191 ((AR_SREV_9100(ah)) ? (AR_RTC_BASE + 0x0058) : 0x7058) 1192 1193/* RTC_DERIVED_* - only for AR9100 */ 1194 1195#define AR_RTC_DERIVED_CLK (AR_RTC_BASE + 0x0038) 1196#define AR_RTC_DERIVED_CLK_PERIOD 0x0000fffe 1197#define AR_RTC_DERIVED_CLK_PERIOD_S 1 1198 1199#define AR_SEQ_MASK 0x8060 1200 1201#define AR_AN_RF2G1_CH0 0x7810 1202#define AR_AN_RF2G1_CH0_OB 0x03800000 1203#define AR_AN_RF2G1_CH0_OB_S 23 1204#define AR_AN_RF2G1_CH0_DB 0x1C000000 1205#define AR_AN_RF2G1_CH0_DB_S 26 1206 1207#define AR_AN_RF5G1_CH0 0x7818 1208#define AR_AN_RF5G1_CH0_OB5 0x00070000 1209#define AR_AN_RF5G1_CH0_OB5_S 16 1210#define AR_AN_RF5G1_CH0_DB5 0x00380000 1211#define AR_AN_RF5G1_CH0_DB5_S 19 1212 1213#define AR_AN_RF2G1_CH1 0x7834 1214#define AR_AN_RF2G1_CH1_OB 0x03800000 1215#define AR_AN_RF2G1_CH1_OB_S 23 1216#define AR_AN_RF2G1_CH1_DB 0x1C000000 1217#define AR_AN_RF2G1_CH1_DB_S 26 1218 1219#define AR_AN_RF5G1_CH1 0x783C 1220#define AR_AN_RF5G1_CH1_OB5 0x00070000 1221#define AR_AN_RF5G1_CH1_OB5_S 16 1222#define AR_AN_RF5G1_CH1_DB5 0x00380000 1223#define AR_AN_RF5G1_CH1_DB5_S 19 1224 1225#define AR_AN_TOP1 0x7890 1226#define AR_AN_TOP1_DACIPMODE 0x00040000 1227#define AR_AN_TOP1_DACIPMODE_S 18 1228 1229#define AR_AN_TOP2 0x7894 1230#define AR_AN_TOP2_XPABIAS_LVL 0xC0000000 1231#define AR_AN_TOP2_XPABIAS_LVL_S 30 1232#define AR_AN_TOP2_LOCALBIAS 0x00200000 1233#define AR_AN_TOP2_LOCALBIAS_S 21 1234#define AR_AN_TOP2_PWDCLKIND 0x00400000 1235#define AR_AN_TOP2_PWDCLKIND_S 22 1236 1237#define AR_AN_SYNTH9 0x7868 1238#define AR_AN_SYNTH9_REFDIVA 0xf8000000 1239#define AR_AN_SYNTH9_REFDIVA_S 27 1240 1241#define AR9285_AN_RF2G1 0x7820 1242#define AR9285_AN_RF2G1_ENPACAL 0x00000800 1243#define AR9285_AN_RF2G1_ENPACAL_S 11 1244#define AR9285_AN_RF2G1_PDPADRV1 0x02000000 1245#define AR9285_AN_RF2G1_PDPADRV1_S 25 1246#define AR9285_AN_RF2G1_PDPADRV2 0x01000000 1247#define AR9285_AN_RF2G1_PDPADRV2_S 24 1248#define AR9285_AN_RF2G1_PDPAOUT 0x00800000 1249#define AR9285_AN_RF2G1_PDPAOUT_S 23 1250 1251 1252#define AR9285_AN_RF2G2 0x7824 1253#define AR9285_AN_RF2G2_OFFCAL 0x00001000 1254#define AR9285_AN_RF2G2_OFFCAL_S 12 1255 1256#define AR9285_AN_RF2G3 0x7828 1257#define AR9285_AN_RF2G3_PDVCCOMP 0x02000000 1258#define AR9285_AN_RF2G3_PDVCCOMP_S 25 1259#define AR9285_AN_RF2G3_OB_0 0x00E00000 1260#define AR9285_AN_RF2G3_OB_0_S 21 1261#define AR9285_AN_RF2G3_OB_1 0x001C0000 1262#define AR9285_AN_RF2G3_OB_1_S 18 1263#define AR9285_AN_RF2G3_OB_2 0x00038000 1264#define AR9285_AN_RF2G3_OB_2_S 15 1265#define AR9285_AN_RF2G3_OB_3 0x00007000 1266#define AR9285_AN_RF2G3_OB_3_S 12 1267#define AR9285_AN_RF2G3_OB_4 0x00000E00 1268#define AR9285_AN_RF2G3_OB_4_S 9 1269 1270#define AR9285_AN_RF2G3_DB1_0 0x000001C0 1271#define AR9285_AN_RF2G3_DB1_0_S 6 1272#define AR9285_AN_RF2G3_DB1_1 0x00000038 1273#define AR9285_AN_RF2G3_DB1_1_S 3 1274#define AR9285_AN_RF2G3_DB1_2 0x00000007 1275#define AR9285_AN_RF2G3_DB1_2_S 0 1276#define AR9285_AN_RF2G4 0x782C 1277#define AR9285_AN_RF2G4_DB1_3 0xE0000000 1278#define AR9285_AN_RF2G4_DB1_3_S 29 1279#define AR9285_AN_RF2G4_DB1_4 0x1C000000 1280#define AR9285_AN_RF2G4_DB1_4_S 26 1281 1282#define AR9285_AN_RF2G4_DB2_0 0x03800000 1283#define AR9285_AN_RF2G4_DB2_0_S 23 1284#define AR9285_AN_RF2G4_DB2_1 0x00700000 1285#define AR9285_AN_RF2G4_DB2_1_S 20 1286#define AR9285_AN_RF2G4_DB2_2 0x000E0000 1287#define AR9285_AN_RF2G4_DB2_2_S 17 1288#define AR9285_AN_RF2G4_DB2_3 0x0001C000 1289#define AR9285_AN_RF2G4_DB2_3_S 14 1290#define AR9285_AN_RF2G4_DB2_4 0x00003800 1291#define AR9285_AN_RF2G4_DB2_4_S 11 1292 1293#define AR9285_RF2G5 0x7830 1294#define AR9285_RF2G5_IC50TX 0xfffff8ff 1295#define AR9285_RF2G5_IC50TX_SET 0x00000400 1296#define AR9285_RF2G5_IC50TX_XE_SET 0x00000500 1297#define AR9285_RF2G5_IC50TX_CLEAR 0x00000700 1298#define AR9285_RF2G5_IC50TX_CLEAR_S 8 1299 1300/* AR9271 : 0x7828, 0x782c different setting from AR9285 */ 1301#define AR9271_AN_RF2G3_OB_cck 0x001C0000 1302#define AR9271_AN_RF2G3_OB_cck_S 18 1303#define AR9271_AN_RF2G3_OB_psk 0x00038000 1304#define AR9271_AN_RF2G3_OB_psk_S 15 1305#define AR9271_AN_RF2G3_OB_qam 0x00007000 1306#define AR9271_AN_RF2G3_OB_qam_S 12 1307 1308#define AR9271_AN_RF2G3_DB_1 0x00E00000 1309#define AR9271_AN_RF2G3_DB_1_S 21 1310 1311#define AR9271_AN_RF2G3_CCOMP 0xFFF 1312#define AR9271_AN_RF2G3_CCOMP_S 0 1313 1314#define AR9271_AN_RF2G4_DB_2 0xE0000000 1315#define AR9271_AN_RF2G4_DB_2_S 29 1316 1317#define AR9285_AN_RF2G6 0x7834 1318#define AR9285_AN_RF2G6_CCOMP 0x00007800 1319#define AR9285_AN_RF2G6_CCOMP_S 11 1320#define AR9285_AN_RF2G6_OFFS 0x03f00000 1321#define AR9285_AN_RF2G6_OFFS_S 20 1322 1323#define AR9271_AN_RF2G6_OFFS 0x07f00000 1324#define AR9271_AN_RF2G6_OFFS_S 20 1325 1326#define AR9285_AN_RF2G7 0x7838 1327#define AR9285_AN_RF2G7_PWDDB 0x00000002 1328#define AR9285_AN_RF2G7_PWDDB_S 1 1329#define AR9285_AN_RF2G7_PADRVGN2TAB0 0xE0000000 1330#define AR9285_AN_RF2G7_PADRVGN2TAB0_S 29 1331 1332#define AR9285_AN_RF2G8 0x783C 1333#define AR9285_AN_RF2G8_PADRVGN2TAB0 0x0001C000 1334#define AR9285_AN_RF2G8_PADRVGN2TAB0_S 14 1335 1336 1337#define AR9285_AN_RF2G9 0x7840 1338#define AR9285_AN_RXTXBB1 0x7854 1339#define AR9285_AN_RXTXBB1_PDRXTXBB1 0x00000020 1340#define AR9285_AN_RXTXBB1_PDRXTXBB1_S 5 1341#define AR9285_AN_RXTXBB1_PDV2I 0x00000080 1342#define AR9285_AN_RXTXBB1_PDV2I_S 7 1343#define AR9285_AN_RXTXBB1_PDDACIF 0x00000100 1344#define AR9285_AN_RXTXBB1_PDDACIF_S 8 1345#define AR9285_AN_RXTXBB1_SPARE9 0x00000001 1346#define AR9285_AN_RXTXBB1_SPARE9_S 0 1347 1348#define AR9285_AN_TOP2 0x7868 1349 1350#define AR9285_AN_TOP3 0x786c 1351#define AR9285_AN_TOP3_XPABIAS_LVL 0x0000000C 1352#define AR9285_AN_TOP3_XPABIAS_LVL_S 2 1353#define AR9285_AN_TOP3_PWDDAC 0x00800000 1354#define AR9285_AN_TOP3_PWDDAC_S 23 1355 1356#define AR9285_AN_TOP4 0x7870 1357#define AR9285_AN_TOP4_DEFAULT 0x10142c00 1358 1359#define AR9287_AN_RF2G3_CH0 0x7808 1360#define AR9287_AN_RF2G3_CH1 0x785c 1361#define AR9287_AN_RF2G3_DB1 0xE0000000 1362#define AR9287_AN_RF2G3_DB1_S 29 1363#define AR9287_AN_RF2G3_DB2 0x1C000000 1364#define AR9287_AN_RF2G3_DB2_S 26 1365#define AR9287_AN_RF2G3_OB_CCK 0x03800000 1366#define AR9287_AN_RF2G3_OB_CCK_S 23 1367#define AR9287_AN_RF2G3_OB_PSK 0x00700000 1368#define AR9287_AN_RF2G3_OB_PSK_S 20 1369#define AR9287_AN_RF2G3_OB_QAM 0x000E0000 1370#define AR9287_AN_RF2G3_OB_QAM_S 17 1371#define AR9287_AN_RF2G3_OB_PAL_OFF 0x0001C000 1372#define AR9287_AN_RF2G3_OB_PAL_OFF_S 14 1373 1374#define AR9287_AN_TXPC0 0x7898 1375#define AR9287_AN_TXPC0_TXPCMODE 0x0000C000 1376#define AR9287_AN_TXPC0_TXPCMODE_S 14 1377#define AR9287_AN_TXPC0_TXPCMODE_NORMAL 0 1378#define AR9287_AN_TXPC0_TXPCMODE_TEST 1 1379#define AR9287_AN_TXPC0_TXPCMODE_TEMPSENSE 2 1380#define AR9287_AN_TXPC0_TXPCMODE_ATBTEST 3 1381 1382#define AR9287_AN_TOP2 0x78b4 1383#define AR9287_AN_TOP2_XPABIAS_LVL 0xC0000000 1384#define AR9287_AN_TOP2_XPABIAS_LVL_S 30 1385 1386/* AR9271 specific stuff */ 1387#define AR9271_RESET_POWER_DOWN_CONTROL 0x50044 1388#define AR9271_RADIO_RF_RST 0x20 1389#define AR9271_GATE_MAC_CTL 0x4000 1390 1391#define AR_STA_ID0 0x8000 1392#define AR_STA_ID1 0x8004 1393#define AR_STA_ID1_SADH_MASK 0x0000FFFF 1394#define AR_STA_ID1_STA_AP 0x00010000 1395#define AR_STA_ID1_ADHOC 0x00020000 1396#define AR_STA_ID1_PWR_SAV 0x00040000 1397#define AR_STA_ID1_KSRCHDIS 0x00080000 1398#define AR_STA_ID1_PCF 0x00100000 1399#define AR_STA_ID1_USE_DEFANT 0x00200000 1400#define AR_STA_ID1_DEFANT_UPDATE 0x00400000 1401#define AR_STA_ID1_RTS_USE_DEF 0x00800000 1402#define AR_STA_ID1_ACKCTS_6MB 0x01000000 1403#define AR_STA_ID1_BASE_RATE_11B 0x02000000 1404#define AR_STA_ID1_SECTOR_SELF_GEN 0x04000000 1405#define AR_STA_ID1_CRPT_MIC_ENABLE 0x08000000 1406#define AR_STA_ID1_KSRCH_MODE 0x10000000 1407#define AR_STA_ID1_PRESERVE_SEQNUM 0x20000000 1408#define AR_STA_ID1_CBCIV_ENDIAN 0x40000000 1409#define AR_STA_ID1_MCAST_KSRCH 0x80000000 1410 1411#define AR_BSS_ID0 0x8008 1412#define AR_BSS_ID1 0x800C 1413#define AR_BSS_ID1_U16 0x0000FFFF 1414#define AR_BSS_ID1_AID 0x07FF0000 1415#define AR_BSS_ID1_AID_S 16 1416 1417#define AR_BCN_RSSI_AVE 0x8010 1418#define AR_BCN_RSSI_AVE_MASK 0x00000FFF 1419 1420#define AR_TIME_OUT 0x8014 1421#define AR_TIME_OUT_ACK 0x00003FFF 1422#define AR_TIME_OUT_ACK_S 0 1423#define AR_TIME_OUT_CTS 0x3FFF0000 1424#define AR_TIME_OUT_CTS_S 16 1425#define AR_TIME_OUT_ACK_CTS_ASYNC_FIFO_DUR 0x16001D56 1426 1427#define AR_RSSI_THR 0x8018 1428#define AR_RSSI_THR_MASK 0x000000FF 1429#define AR_RSSI_THR_BM_THR 0x0000FF00 1430#define AR_RSSI_THR_BM_THR_S 8 1431#define AR_RSSI_BCN_WEIGHT 0x1F000000 1432#define AR_RSSI_BCN_WEIGHT_S 24 1433#define AR_RSSI_BCN_RSSI_RST 0x20000000 1434 1435#define AR_USEC 0x801c 1436#define AR_USEC_USEC 0x0000007F 1437#define AR_USEC_TX_LAT 0x007FC000 1438#define AR_USEC_TX_LAT_S 14 1439#define AR_USEC_RX_LAT 0x1F800000 1440#define AR_USEC_RX_LAT_S 23 1441#define AR_USEC_ASYNC_FIFO_DUR 0x12e00074 1442 1443#define AR_RESET_TSF 0x8020 1444#define AR_RESET_TSF_ONCE 0x01000000 1445 1446#define AR_MAX_CFP_DUR 0x8038 1447#define AR_CFP_VAL 0x0000FFFF 1448 1449#define AR_RX_FILTER 0x803C 1450 1451#define AR_MCAST_FIL0 0x8040 1452#define AR_MCAST_FIL1 0x8044 1453 1454/* 1455 * AR_DIAG_SW - Register which can be used for diagnostics and testing purposes. 1456 * 1457 * The force RX abort (AR_DIAG_RX_ABORT, bit 25) can be used in conjunction with 1458 * RX block (AR_DIAG_RX_DIS, bit 5) to help fast channel change to shut down 1459 * receive. The force RX abort bit will kill any frame which is currently being 1460 * transferred between the MAC and baseband. The RX block bit (AR_DIAG_RX_DIS) 1461 * will prevent any new frames from getting started. 1462 */ 1463#define AR_DIAG_SW 0x8048 1464#define AR_DIAG_CACHE_ACK 0x00000001 1465#define AR_DIAG_ACK_DIS 0x00000002 1466#define AR_DIAG_CTS_DIS 0x00000004 1467#define AR_DIAG_ENCRYPT_DIS 0x00000008 1468#define AR_DIAG_DECRYPT_DIS 0x00000010 1469#define AR_DIAG_RX_DIS 0x00000020 /* RX block */ 1470#define AR_DIAG_LOOP_BACK 0x00000040 1471#define AR_DIAG_CORR_FCS 0x00000080 1472#define AR_DIAG_CHAN_INFO 0x00000100 1473#define AR_DIAG_SCRAM_SEED 0x0001FE00 1474#define AR_DIAG_SCRAM_SEED_S 8 1475#define AR_DIAG_FRAME_NV0 0x00020000 1476#define AR_DIAG_OBS_PT_SEL1 0x000C0000 1477#define AR_DIAG_OBS_PT_SEL1_S 18 1478#define AR_DIAG_FORCE_RX_CLEAR 0x00100000 /* force rx_clear high */ 1479#define AR_DIAG_IGNORE_VIRT_CS 0x00200000 1480#define AR_DIAG_FORCE_CH_IDLE_HIGH 0x00400000 1481#define AR_DIAG_EIFS_CTRL_ENA 0x00800000 1482#define AR_DIAG_DUAL_CHAIN_INFO 0x01000000 1483#define AR_DIAG_RX_ABORT 0x02000000 /* Force RX abort */ 1484#define AR_DIAG_SATURATE_CYCLE_CNT 0x04000000 1485#define AR_DIAG_OBS_PT_SEL2 0x08000000 1486#define AR_DIAG_RX_CLEAR_CTL_LOW 0x10000000 1487#define AR_DIAG_RX_CLEAR_EXT_LOW 0x20000000 1488 1489#define AR_TSF_L32 0x804c 1490#define AR_TSF_U32 0x8050 1491 1492#define AR_TST_ADDAC 0x8054 1493#define AR_DEF_ANTENNA 0x8058 1494 1495#define AR_AES_MUTE_MASK0 0x805c 1496#define AR_AES_MUTE_MASK0_FC 0x0000FFFF 1497#define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 1498#define AR_AES_MUTE_MASK0_QOS_S 16 1499 1500#define AR_AES_MUTE_MASK1 0x8060 1501#define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF 1502#define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 1503#define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1504 1505#define AR_GATED_CLKS 0x8064 1506#define AR_GATED_CLKS_TX 0x00000002 1507#define AR_GATED_CLKS_RX 0x00000004 1508#define AR_GATED_CLKS_REG 0x00000008 1509 1510#define AR_OBS_BUS_CTRL 0x8068 1511#define AR_OBS_BUS_SEL_1 0x00040000 1512#define AR_OBS_BUS_SEL_2 0x00080000 1513#define AR_OBS_BUS_SEL_3 0x000C0000 1514#define AR_OBS_BUS_SEL_4 0x08040000 1515#define AR_OBS_BUS_SEL_5 0x08080000 1516 1517#define AR_OBS_BUS_1 0x806c 1518#define AR_OBS_BUS_1_PCU 0x00000001 1519#define AR_OBS_BUS_1_RX_END 0x00000002 1520#define AR_OBS_BUS_1_RX_WEP 0x00000004 1521#define AR_OBS_BUS_1_RX_BEACON 0x00000008 1522#define AR_OBS_BUS_1_RX_FILTER 0x00000010 1523#define AR_OBS_BUS_1_TX_HCF 0x00000020 1524#define AR_OBS_BUS_1_QUIET_TIME 0x00000040 1525#define AR_OBS_BUS_1_CHAN_IDLE 0x00000080 1526#define AR_OBS_BUS_1_TX_HOLD 0x00000100 1527#define AR_OBS_BUS_1_TX_FRAME 0x00000200 1528#define AR_OBS_BUS_1_RX_FRAME 0x00000400 1529#define AR_OBS_BUS_1_RX_CLEAR 0x00000800 1530#define AR_OBS_BUS_1_WEP_STATE 0x0003F000 1531#define AR_OBS_BUS_1_WEP_STATE_S 12 1532#define AR_OBS_BUS_1_RX_STATE 0x01F00000 1533#define AR_OBS_BUS_1_RX_STATE_S 20 1534#define AR_OBS_BUS_1_TX_STATE 0x7E000000 1535#define AR_OBS_BUS_1_TX_STATE_S 25 1536 1537#define AR_LAST_TSTP 0x8080 1538#define AR_NAV 0x8084 1539#define AR_RTS_OK 0x8088 1540#define AR_RTS_FAIL 0x808c 1541#define AR_ACK_FAIL 0x8090 1542#define AR_FCS_FAIL 0x8094 1543#define AR_BEACON_CNT 0x8098 1544 1545#define AR_SLEEP1 0x80d4 1546#define AR_SLEEP1_ASSUME_DTIM 0x00080000 1547#define AR_SLEEP1_CAB_TIMEOUT 0xFFE00000 1548#define AR_SLEEP1_CAB_TIMEOUT_S 21 1549 1550#define AR_SLEEP2 0x80d8 1551#define AR_SLEEP2_BEACON_TIMEOUT 0xFFE00000 1552#define AR_SLEEP2_BEACON_TIMEOUT_S 21 1553 1554#define AR_TPC 0x80e8 1555#define AR_TPC_ACK 0x0000003f 1556#define AR_TPC_ACK_S 0x00 1557#define AR_TPC_CTS 0x00003f00 1558#define AR_TPC_CTS_S 0x08 1559#define AR_TPC_CHIRP 0x003f0000 1560#define AR_TPC_CHIRP_S 0x16 1561 1562#define AR_TFCNT 0x80ec 1563#define AR_RFCNT 0x80f0 1564#define AR_RCCNT 0x80f4 1565#define AR_CCCNT 0x80f8 1566 1567#define AR_QUIET1 0x80fc 1568#define AR_QUIET1_NEXT_QUIET_S 0 1569#define AR_QUIET1_NEXT_QUIET_M 0x0000ffff 1570#define AR_QUIET1_QUIET_ENABLE 0x00010000 1571#define AR_QUIET1_QUIET_ACK_CTS_ENABLE 0x00020000 1572#define AR_QUIET1_QUIET_ACK_CTS_ENABLE_S 17 1573#define AR_QUIET2 0x8100 1574#define AR_QUIET2_QUIET_PERIOD_S 0 1575#define AR_QUIET2_QUIET_PERIOD_M 0x0000ffff 1576#define AR_QUIET2_QUIET_DUR_S 16 1577#define AR_QUIET2_QUIET_DUR 0xffff0000 1578 1579#define AR_TSF_PARM 0x8104 1580#define AR_TSF_INCREMENT_M 0x000000ff 1581#define AR_TSF_INCREMENT_S 0x00 1582 1583#define AR_QOS_NO_ACK 0x8108 1584#define AR_QOS_NO_ACK_TWO_BIT 0x0000000f 1585#define AR_QOS_NO_ACK_TWO_BIT_S 0 1586#define AR_QOS_NO_ACK_BIT_OFF 0x00000070 1587#define AR_QOS_NO_ACK_BIT_OFF_S 4 1588#define AR_QOS_NO_ACK_BYTE_OFF 0x00000180 1589#define AR_QOS_NO_ACK_BYTE_OFF_S 7 1590 1591#define AR_PHY_ERR 0x810c 1592 1593#define AR_PHY_ERR_DCHIRP 0x00000008 1594#define AR_PHY_ERR_RADAR 0x00000020 1595#define AR_PHY_ERR_OFDM_TIMING 0x00020000 1596#define AR_PHY_ERR_CCK_TIMING 0x02000000 1597 1598#define AR_RXFIFO_CFG 0x8114 1599 1600 1601#define AR_MIC_QOS_CONTROL 0x8118 1602#define AR_MIC_QOS_SELECT 0x811c 1603 1604#define AR_PCU_MISC 0x8120 1605#define AR_PCU_FORCE_BSSID_MATCH 0x00000001 1606#define AR_PCU_MIC_NEW_LOC_ENA 0x00000004 1607#define AR_PCU_TX_ADD_TSF 0x00000008 1608#define AR_PCU_CCK_SIFS_MODE 0x00000010 1609#define AR_PCU_RX_ANT_UPDT 0x00000800 1610#define AR_PCU_TXOP_TBTT_LIMIT_ENA 0x00001000 1611#define AR_PCU_MISS_BCN_IN_SLEEP 0x00004000 1612#define AR_PCU_BUG_12306_FIX_ENA 0x00020000 1613#define AR_PCU_FORCE_QUIET_COLL 0x00040000 1614#define AR_PCU_TBTT_PROTECT 0x00200000 1615#define AR_PCU_CLEAR_VMF 0x01000000 1616#define AR_PCU_CLEAR_BA_VALID 0x04000000 1617 1618#define AR_PCU_BT_ANT_PREVENT_RX 0x00100000 1619#define AR_PCU_BT_ANT_PREVENT_RX_S 20 1620 1621#define AR_FILT_OFDM 0x8124 1622#define AR_FILT_OFDM_COUNT 0x00FFFFFF 1623 1624#define AR_FILT_CCK 0x8128 1625#define AR_FILT_CCK_COUNT 0x00FFFFFF 1626 1627#define AR_PHY_ERR_1 0x812c 1628#define AR_PHY_ERR_1_COUNT 0x00FFFFFF 1629#define AR_PHY_ERR_MASK_1 0x8130 1630 1631#define AR_PHY_ERR_2 0x8134 1632#define AR_PHY_ERR_2_COUNT 0x00FFFFFF 1633#define AR_PHY_ERR_MASK_2 0x8138 1634 1635#define AR_PHY_COUNTMAX (3 << 22) 1636#define AR_MIBCNT_INTRMASK (3 << 22) 1637 1638#define AR_TSFOOR_THRESHOLD 0x813c 1639#define AR_TSFOOR_THRESHOLD_VAL 0x0000FFFF 1640 1641#define AR_PHY_ERR_EIFS_MASK 0x8144 1642 1643#define AR_PHY_ERR_3 0x8168 1644#define AR_PHY_ERR_3_COUNT 0x00FFFFFF 1645#define AR_PHY_ERR_MASK_3 0x816c 1646 1647#define AR_BT_COEX_MODE 0x8170 1648#define AR_BT_TIME_EXTEND 0x000000ff 1649#define AR_BT_TIME_EXTEND_S 0 1650#define AR_BT_TXSTATE_EXTEND 0x00000100 1651#define AR_BT_TXSTATE_EXTEND_S 8 1652#define AR_BT_TX_FRAME_EXTEND 0x00000200 1653#define AR_BT_TX_FRAME_EXTEND_S 9 1654#define AR_BT_MODE 0x00000c00 1655#define AR_BT_MODE_S 10 1656#define AR_BT_QUIET 0x00001000 1657#define AR_BT_QUIET_S 12 1658#define AR_BT_QCU_THRESH 0x0001e000 1659#define AR_BT_QCU_THRESH_S 13 1660#define AR_BT_RX_CLEAR_POLARITY 0x00020000 1661#define AR_BT_RX_CLEAR_POLARITY_S 17 1662#define AR_BT_PRIORITY_TIME 0x00fc0000 1663#define AR_BT_PRIORITY_TIME_S 18 1664#define AR_BT_FIRST_SLOT_TIME 0xff000000 1665#define AR_BT_FIRST_SLOT_TIME_S 24 1666 1667#define AR_BT_COEX_WEIGHT 0x8174 1668#define AR_BT_COEX_WGHT 0xff55 1669#define AR_STOMP_ALL_WLAN_WGHT 0xfcfc 1670#define AR_STOMP_LOW_WLAN_WGHT 0xa8a8 1671#define AR_STOMP_NONE_WLAN_WGHT 0x0000 1672#define AR_BTCOEX_BT_WGHT 0x0000ffff 1673#define AR_BTCOEX_BT_WGHT_S 0 1674#define AR_BTCOEX_WL_WGHT 0xffff0000 1675#define AR_BTCOEX_WL_WGHT_S 16 1676 1677#define AR_BT_COEX_MODE2 0x817c 1678#define AR_BT_BCN_MISS_THRESH 0x000000ff 1679#define AR_BT_BCN_MISS_THRESH_S 0 1680#define AR_BT_BCN_MISS_CNT 0x0000ff00 1681#define AR_BT_BCN_MISS_CNT_S 8 1682#define AR_BT_HOLD_RX_CLEAR 0x00010000 1683#define AR_BT_HOLD_RX_CLEAR_S 16 1684#define AR_BT_DISABLE_BT_ANT 0x00100000 1685#define AR_BT_DISABLE_BT_ANT_S 20 1686 1687#define AR_TXSIFS 0x81d0 1688#define AR_TXSIFS_TIME 0x000000FF 1689#define AR_TXSIFS_TX_LATENCY 0x00000F00 1690#define AR_TXSIFS_TX_LATENCY_S 8 1691#define AR_TXSIFS_ACK_SHIFT 0x00007000 1692#define AR_TXSIFS_ACK_SHIFT_S 12 1693 1694#define AR_TXOP_X 0x81ec 1695#define AR_TXOP_X_VAL 0x000000FF 1696 1697 1698#define AR_TXOP_0_3 0x81f0 1699#define AR_TXOP_4_7 0x81f4 1700#define AR_TXOP_8_11 0x81f8 1701#define AR_TXOP_12_15 0x81fc 1702 1703#define AR_NEXT_NDP2_TIMER 0x8180 1704#define AR_FIRST_NDP_TIMER 7 1705#define AR_NDP2_PERIOD 0x81a0 1706#define AR_NDP2_TIMER_MODE 0x81c0 1707 1708#define AR_GEN_TIMERS(_i) (0x8200 + ((_i) << 2)) 1709#define AR_NEXT_TBTT_TIMER AR_GEN_TIMERS(0) 1710#define AR_NEXT_DMA_BEACON_ALERT AR_GEN_TIMERS(1) 1711#define AR_NEXT_SWBA AR_GEN_TIMERS(2) 1712#define AR_NEXT_CFP AR_GEN_TIMERS(2) 1713#define AR_NEXT_HCF AR_GEN_TIMERS(3) 1714#define AR_NEXT_TIM AR_GEN_TIMERS(4) 1715#define AR_NEXT_DTIM AR_GEN_TIMERS(5) 1716#define AR_NEXT_QUIET_TIMER AR_GEN_TIMERS(6) 1717#define AR_NEXT_NDP_TIMER AR_GEN_TIMERS(7) 1718 1719#define AR_BEACON_PERIOD AR_GEN_TIMERS(8) 1720#define AR_DMA_BEACON_PERIOD AR_GEN_TIMERS(9) 1721#define AR_SWBA_PERIOD AR_GEN_TIMERS(10) 1722#define AR_HCF_PERIOD AR_GEN_TIMERS(11) 1723#define AR_TIM_PERIOD AR_GEN_TIMERS(12) 1724#define AR_DTIM_PERIOD AR_GEN_TIMERS(13) 1725#define AR_QUIET_PERIOD AR_GEN_TIMERS(14) 1726#define AR_NDP_PERIOD AR_GEN_TIMERS(15) 1727 1728#define AR_TIMER_MODE 0x8240 1729#define AR_TBTT_TIMER_EN 0x00000001 1730#define AR_DBA_TIMER_EN 0x00000002 1731#define AR_SWBA_TIMER_EN 0x00000004 1732#define AR_HCF_TIMER_EN 0x00000008 1733#define AR_TIM_TIMER_EN 0x00000010 1734#define AR_DTIM_TIMER_EN 0x00000020 1735#define AR_QUIET_TIMER_EN 0x00000040 1736#define AR_NDP_TIMER_EN 0x00000080 1737#define AR_TIMER_OVERFLOW_INDEX 0x00000700 1738#define AR_TIMER_OVERFLOW_INDEX_S 8 1739#define AR_TIMER_THRESH 0xFFFFF000 1740#define AR_TIMER_THRESH_S 12 1741 1742#define AR_SLP32_MODE 0x8244 1743#define AR_SLP32_HALF_CLK_LATENCY 0x000FFFFF 1744#define AR_SLP32_ENA 0x00100000 1745#define AR_SLP32_TSF_WRITE_STATUS 0x00200000 1746 1747#define AR_SLP32_WAKE 0x8248 1748#define AR_SLP32_WAKE_XTL_TIME 0x0000FFFF 1749 1750#define AR_SLP32_INC 0x824c 1751#define AR_SLP32_TST_INC 0x000FFFFF 1752 1753#define AR_SLP_CNT 0x8250 1754#define AR_SLP_CYCLE_CNT 0x8254 1755 1756#define AR_SLP_MIB_CTRL 0x8258 1757#define AR_SLP_MIB_CLEAR 0x00000001 1758#define AR_SLP_MIB_PENDING 0x00000002 1759 1760#define AR_MAC_PCU_LOGIC_ANALYZER 0x8264 1761#define AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768 0x20000000 1762 1763 1764#define AR_2040_MODE 0x8318 1765#define AR_2040_JOINED_RX_CLEAR 0x00000001 1766 1767 1768#define AR_EXTRCCNT 0x8328 1769 1770#define AR_SELFGEN_MASK 0x832c 1771 1772#define AR_PCU_TXBUF_CTRL 0x8340 1773#define AR_PCU_TXBUF_CTRL_SIZE_MASK 0x7FF 1774#define AR_PCU_TXBUF_CTRL_USABLE_SIZE 0x700 1775#define AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE 0x380 1776 1777#define AR_PCU_MISC_MODE2 0x8344 1778#define AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE 0x00000002 1779#define AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT 0x00000004 1780 1781#define AR_PCU_MISC_MODE2_RESERVED 0x00000038 1782#define AR_PCU_MISC_MODE2_ADHOC_MCAST_KEYID_ENABLE 0x00000040 1783#define AR_PCU_MISC_MODE2_CFP_IGNORE 0x00000080 1784#define AR_PCU_MISC_MODE2_MGMT_QOS 0x0000FF00 1785#define AR_PCU_MISC_MODE2_MGMT_QOS_S 8 1786#define AR_PCU_MISC_MODE2_ENABLE_LOAD_NAV_BEACON_DURATION 0x00010000 1787#define AR_PCU_MISC_MODE2_ENABLE_AGGWEP 0x00020000 1788#define AR_PCU_MISC_MODE2_HWWAR1 0x00100000 1789#define AR_PCU_MISC_MODE2_HWWAR2 0x02000000 1790#define AR_PCU_MISC_MODE2_RESERVED2 0xFFFE0000 1791 1792#define AR_MAC_PCU_ASYNC_FIFO_REG3 0x8358 1793#define AR_MAC_PCU_ASYNC_FIFO_REG3_DATAPATH_SEL 0x00000400 1794#define AR_MAC_PCU_ASYNC_FIFO_REG3_SOFT_RESET 0x80000000 1795 1796 1797#define AR_AES_MUTE_MASK0 0x805c 1798#define AR_AES_MUTE_MASK0_FC 0x0000FFFF 1799#define AR_AES_MUTE_MASK0_QOS 0xFFFF0000 1800#define AR_AES_MUTE_MASK0_QOS_S 16 1801 1802#define AR_AES_MUTE_MASK1 0x8060 1803#define AR_AES_MUTE_MASK1_SEQ 0x0000FFFF 1804#define AR_AES_MUTE_MASK1_SEQ_S 0 1805#define AR_AES_MUTE_MASK1_FC_MGMT 0xFFFF0000 1806#define AR_AES_MUTE_MASK1_FC_MGMT_S 16 1807 1808#define AR_RATE_DURATION_0 0x8700 1809#define AR_RATE_DURATION_31 0x87CC 1810#define AR_RATE_DURATION_32 0x8780 1811#define AR_RATE_DURATION(_n) (AR_RATE_DURATION_0 + ((_n)<<2)) 1812 1813 1814#define AR_KEYTABLE_0 0x8800 1815#define AR_KEYTABLE(_n) (AR_KEYTABLE_0 + ((_n)*32)) 1816#define AR_KEY_CACHE_SIZE 128 1817#define AR_RSVD_KEYTABLE_ENTRIES 4 1818#define AR_KEY_TYPE 0x00000007 1819#define AR_KEYTABLE_TYPE_40 0x00000000 1820#define AR_KEYTABLE_TYPE_104 0x00000001 1821#define AR_KEYTABLE_TYPE_128 0x00000003 1822#define AR_KEYTABLE_TYPE_TKIP 0x00000004 1823#define AR_KEYTABLE_TYPE_AES 0x00000005 1824#define AR_KEYTABLE_TYPE_CCM 0x00000006 1825#define AR_KEYTABLE_TYPE_CLR 0x00000007 1826#define AR_KEYTABLE_ANT 0x00000008 1827#define AR_KEYTABLE_VALID 0x00008000 1828#define AR_KEYTABLE_KEY0(_n) (AR_KEYTABLE(_n) + 0) 1829#define AR_KEYTABLE_KEY1(_n) (AR_KEYTABLE(_n) + 4) 1830#define AR_KEYTABLE_KEY2(_n) (AR_KEYTABLE(_n) + 8) 1831#define AR_KEYTABLE_KEY3(_n) (AR_KEYTABLE(_n) + 12) 1832#define AR_KEYTABLE_KEY4(_n) (AR_KEYTABLE(_n) + 16) 1833#define AR_KEYTABLE_TYPE(_n) (AR_KEYTABLE(_n) + 20) 1834#define AR_KEYTABLE_MAC0(_n) (AR_KEYTABLE(_n) + 24) 1835#define AR_KEYTABLE_MAC1(_n) (AR_KEYTABLE(_n) + 28) 1836 1837#define AR9271_CORE_CLOCK 117 /* clock to 117Mhz */ 1838#define AR9271_TARGET_BAUD_RATE 19200 /* 115200 */ 1839 1840#define AR_AGG_WEP_ENABLE_FIX 0x00000008 /* This allows the use of AR_AGG_WEP_ENABLE */ 1841#define AR_ADHOC_MCAST_KEYID_ENABLE 0x00000040 /* This bit enables the Multicast search 1842 * based on both MAC Address and Key ID. 1843 * If bit is 0, then Multicast search is 1844 * based on MAC address only. 1845 * For Merlin and above only. 1846 */ 1847#define AR_AGG_WEP_ENABLE 0x00020000 /* This field enables AGG_WEP feature, 1848 * when it is enable, AGG_WEP would takes 1849 * charge of the encryption interface of 1850 * pcu_txsm. 1851 */ 1852 1853#define AR9300_SM_BASE 0xa200 1854#define AR9002_PHY_AGC_CONTROL 0x9860 1855#define AR9003_PHY_AGC_CONTROL AR9300_SM_BASE + 0xc4 1856#define AR_PHY_AGC_CONTROL (AR_SREV_9300_20_OR_LATER(ah) ? AR9003_PHY_AGC_CONTROL : AR9002_PHY_AGC_CONTROL) 1857#define AR_PHY_AGC_CONTROL_CAL 0x00000001 /* do internal calibration */ 1858#define AR_PHY_AGC_CONTROL_NF 0x00000002 /* do noise-floor calibration */ 1859#define AR_PHY_AGC_CONTROL_OFFSET_CAL 0x00000800 /* allow offset calibration */ 1860#define AR_PHY_AGC_CONTROL_ENABLE_NF 0x00008000 /* enable noise floor calibration to happen */ 1861#define AR_PHY_AGC_CONTROL_FLTR_CAL 0x00010000 /* allow tx filter calibration */ 1862#define AR_PHY_AGC_CONTROL_NO_UPDATE_NF 0x00020000 /* don't update noise floor automatically */ 1863#define AR_PHY_AGC_CONTROL_EXT_NF_PWR_MEAS 0x00040000 /* extend noise floor power measurement */ 1864#define AR_PHY_AGC_CONTROL_CLC_SUCCESS 0x00080000 /* carrier leak calibration done */ 1865#define AR_PHY_AGC_CONTROL_YCOK_MAX 0x000003c0 1866#define AR_PHY_AGC_CONTROL_YCOK_MAX_S 6 1867 1868#endif 1869