1/* 2 * Copyright (c) 2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "htc.h" 18 19MODULE_AUTHOR("Atheros Communications"); 20MODULE_LICENSE("Dual BSD/GPL"); 21MODULE_DESCRIPTION("Atheros driver 802.11n HTC based wireless devices"); 22 23static unsigned int ath9k_debug = ATH_DBG_DEFAULT; 24module_param_named(debug, ath9k_debug, uint, 0); 25MODULE_PARM_DESC(debug, "Debugging mask"); 26 27int htc_modparam_nohwcrypt; 28module_param_named(nohwcrypt, htc_modparam_nohwcrypt, int, 0444); 29MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption"); 30 31#define CHAN2G(_freq, _idx) { \ 32 .center_freq = (_freq), \ 33 .hw_value = (_idx), \ 34 .max_power = 20, \ 35} 36 37#define CHAN5G(_freq, _idx) { \ 38 .band = IEEE80211_BAND_5GHZ, \ 39 .center_freq = (_freq), \ 40 .hw_value = (_idx), \ 41 .max_power = 20, \ 42} 43 44static struct ieee80211_channel ath9k_2ghz_channels[] = { 45 CHAN2G(2412, 0), /* Channel 1 */ 46 CHAN2G(2417, 1), /* Channel 2 */ 47 CHAN2G(2422, 2), /* Channel 3 */ 48 CHAN2G(2427, 3), /* Channel 4 */ 49 CHAN2G(2432, 4), /* Channel 5 */ 50 CHAN2G(2437, 5), /* Channel 6 */ 51 CHAN2G(2442, 6), /* Channel 7 */ 52 CHAN2G(2447, 7), /* Channel 8 */ 53 CHAN2G(2452, 8), /* Channel 9 */ 54 CHAN2G(2457, 9), /* Channel 10 */ 55 CHAN2G(2462, 10), /* Channel 11 */ 56 CHAN2G(2467, 11), /* Channel 12 */ 57 CHAN2G(2472, 12), /* Channel 13 */ 58 CHAN2G(2484, 13), /* Channel 14 */ 59}; 60 61static struct ieee80211_channel ath9k_5ghz_channels[] = { 62 /* _We_ call this UNII 1 */ 63 CHAN5G(5180, 14), /* Channel 36 */ 64 CHAN5G(5200, 15), /* Channel 40 */ 65 CHAN5G(5220, 16), /* Channel 44 */ 66 CHAN5G(5240, 17), /* Channel 48 */ 67 /* _We_ call this UNII 2 */ 68 CHAN5G(5260, 18), /* Channel 52 */ 69 CHAN5G(5280, 19), /* Channel 56 */ 70 CHAN5G(5300, 20), /* Channel 60 */ 71 CHAN5G(5320, 21), /* Channel 64 */ 72 /* _We_ call this "Middle band" */ 73 CHAN5G(5500, 22), /* Channel 100 */ 74 CHAN5G(5520, 23), /* Channel 104 */ 75 CHAN5G(5540, 24), /* Channel 108 */ 76 CHAN5G(5560, 25), /* Channel 112 */ 77 CHAN5G(5580, 26), /* Channel 116 */ 78 CHAN5G(5600, 27), /* Channel 120 */ 79 CHAN5G(5620, 28), /* Channel 124 */ 80 CHAN5G(5640, 29), /* Channel 128 */ 81 CHAN5G(5660, 30), /* Channel 132 */ 82 CHAN5G(5680, 31), /* Channel 136 */ 83 CHAN5G(5700, 32), /* Channel 140 */ 84 /* _We_ call this UNII 3 */ 85 CHAN5G(5745, 33), /* Channel 149 */ 86 CHAN5G(5765, 34), /* Channel 153 */ 87 CHAN5G(5785, 35), /* Channel 157 */ 88 CHAN5G(5805, 36), /* Channel 161 */ 89 CHAN5G(5825, 37), /* Channel 165 */ 90}; 91 92/* Atheros hardware rate code addition for short premble */ 93#define SHPCHECK(__hw_rate, __flags) \ 94 ((__flags & IEEE80211_RATE_SHORT_PREAMBLE) ? (__hw_rate | 0x04) : 0) 95 96#define RATE(_bitrate, _hw_rate, _flags) { \ 97 .bitrate = (_bitrate), \ 98 .flags = (_flags), \ 99 .hw_value = (_hw_rate), \ 100 .hw_value_short = (SHPCHECK(_hw_rate, _flags)) \ 101} 102 103static struct ieee80211_rate ath9k_legacy_rates[] = { 104 RATE(10, 0x1b, 0), 105 RATE(20, 0x1a, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp : 0x1e */ 106 RATE(55, 0x19, IEEE80211_RATE_SHORT_PREAMBLE), /* shortp: 0x1d */ 107 RATE(110, 0x18, IEEE80211_RATE_SHORT_PREAMBLE), /* short: 0x1c */ 108 RATE(60, 0x0b, 0), 109 RATE(90, 0x0f, 0), 110 RATE(120, 0x0a, 0), 111 RATE(180, 0x0e, 0), 112 RATE(240, 0x09, 0), 113 RATE(360, 0x0d, 0), 114 RATE(480, 0x08, 0), 115 RATE(540, 0x0c, 0), 116}; 117 118static int ath9k_htc_wait_for_target(struct ath9k_htc_priv *priv) 119{ 120 int time_left; 121 122 if (atomic_read(&priv->htc->tgt_ready) > 0) { 123 atomic_dec(&priv->htc->tgt_ready); 124 return 0; 125 } 126 127 /* Firmware can take up to 50ms to get ready, to be safe use 1 second */ 128 time_left = wait_for_completion_timeout(&priv->htc->target_wait, HZ); 129 if (!time_left) { 130 dev_err(priv->dev, "ath9k_htc: Target is unresponsive\n"); 131 return -ETIMEDOUT; 132 } 133 134 atomic_dec(&priv->htc->tgt_ready); 135 136 return 0; 137} 138 139static void ath9k_deinit_priv(struct ath9k_htc_priv *priv) 140{ 141 ath9k_htc_exit_debug(priv->ah); 142 ath9k_hw_deinit(priv->ah); 143 tasklet_kill(&priv->wmi_tasklet); 144 tasklet_kill(&priv->rx_tasklet); 145 tasklet_kill(&priv->tx_tasklet); 146 kfree(priv->ah); 147 priv->ah = NULL; 148} 149 150static void ath9k_deinit_device(struct ath9k_htc_priv *priv) 151{ 152 struct ieee80211_hw *hw = priv->hw; 153 154 wiphy_rfkill_stop_polling(hw->wiphy); 155 ath9k_deinit_leds(priv); 156 ieee80211_unregister_hw(hw); 157 ath9k_rx_cleanup(priv); 158 ath9k_tx_cleanup(priv); 159 ath9k_deinit_priv(priv); 160} 161 162static inline int ath9k_htc_connect_svc(struct ath9k_htc_priv *priv, 163 u16 service_id, 164 void (*tx) (void *, 165 struct sk_buff *, 166 enum htc_endpoint_id, 167 bool txok), 168 enum htc_endpoint_id *ep_id) 169{ 170 struct htc_service_connreq req; 171 172 memset(&req, 0, sizeof(struct htc_service_connreq)); 173 174 req.service_id = service_id; 175 req.ep_callbacks.priv = priv; 176 req.ep_callbacks.rx = ath9k_htc_rxep; 177 req.ep_callbacks.tx = tx; 178 179 return htc_connect_service(priv->htc, &req, ep_id); 180} 181 182static int ath9k_init_htc_services(struct ath9k_htc_priv *priv, u16 devid) 183{ 184 int ret; 185 186 /* WMI CMD*/ 187 ret = ath9k_wmi_connect(priv->htc, priv->wmi, &priv->wmi_cmd_ep); 188 if (ret) 189 goto err; 190 191 /* Beacon */ 192 ret = ath9k_htc_connect_svc(priv, WMI_BEACON_SVC, ath9k_htc_beaconep, 193 &priv->beacon_ep); 194 if (ret) 195 goto err; 196 197 /* CAB */ 198 ret = ath9k_htc_connect_svc(priv, WMI_CAB_SVC, ath9k_htc_txep, 199 &priv->cab_ep); 200 if (ret) 201 goto err; 202 203 204 /* UAPSD */ 205 ret = ath9k_htc_connect_svc(priv, WMI_UAPSD_SVC, ath9k_htc_txep, 206 &priv->uapsd_ep); 207 if (ret) 208 goto err; 209 210 /* MGMT */ 211 ret = ath9k_htc_connect_svc(priv, WMI_MGMT_SVC, ath9k_htc_txep, 212 &priv->mgmt_ep); 213 if (ret) 214 goto err; 215 216 /* DATA BE */ 217 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BE_SVC, ath9k_htc_txep, 218 &priv->data_be_ep); 219 if (ret) 220 goto err; 221 222 /* DATA BK */ 223 ret = ath9k_htc_connect_svc(priv, WMI_DATA_BK_SVC, ath9k_htc_txep, 224 &priv->data_bk_ep); 225 if (ret) 226 goto err; 227 228 /* DATA VI */ 229 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VI_SVC, ath9k_htc_txep, 230 &priv->data_vi_ep); 231 if (ret) 232 goto err; 233 234 /* DATA VO */ 235 ret = ath9k_htc_connect_svc(priv, WMI_DATA_VO_SVC, ath9k_htc_txep, 236 &priv->data_vo_ep); 237 if (ret) 238 goto err; 239 240 /* 241 * Setup required credits before initializing HTC. 242 * This is a bit hacky, but, since queuing is done in 243 * the HIF layer, shouldn't matter much. 244 */ 245 246 switch(devid) { 247 case 0x7010: 248 case 0x7015: 249 case 0x9018: 250 case 0xA704: 251 case 0x1200: 252 priv->htc->credits = 45; 253 break; 254 default: 255 priv->htc->credits = 33; 256 } 257 258 ret = htc_init(priv->htc); 259 if (ret) 260 goto err; 261 262 dev_info(priv->dev, "ath9k_htc: HTC initialized with %d credits\n", 263 priv->htc->credits); 264 265 return 0; 266 267err: 268 dev_err(priv->dev, "ath9k_htc: Unable to initialize HTC services\n"); 269 return ret; 270} 271 272static int ath9k_reg_notifier(struct wiphy *wiphy, 273 struct regulatory_request *request) 274{ 275 struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy); 276 struct ath9k_htc_priv *priv = hw->priv; 277 278 return ath_reg_notifier_apply(wiphy, request, 279 ath9k_hw_regulatory(priv->ah)); 280} 281 282static unsigned int ath9k_regread(void *hw_priv, u32 reg_offset) 283{ 284 struct ath_hw *ah = (struct ath_hw *) hw_priv; 285 struct ath_common *common = ath9k_hw_common(ah); 286 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 287 __be32 val, reg = cpu_to_be32(reg_offset); 288 int r; 289 290 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_READ_CMDID, 291 (u8 *) ®, sizeof(reg), 292 (u8 *) &val, sizeof(val), 293 100); 294 if (unlikely(r)) { 295 ath_print(common, ATH_DBG_WMI, 296 "REGISTER READ FAILED: (0x%04x, %d)\n", 297 reg_offset, r); 298 return -EIO; 299 } 300 301 return be32_to_cpu(val); 302} 303 304static void ath9k_regwrite_single(void *hw_priv, u32 val, u32 reg_offset) 305{ 306 struct ath_hw *ah = (struct ath_hw *) hw_priv; 307 struct ath_common *common = ath9k_hw_common(ah); 308 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 309 __be32 buf[2] = { 310 cpu_to_be32(reg_offset), 311 cpu_to_be32(val), 312 }; 313 int r; 314 315 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, 316 (u8 *) &buf, sizeof(buf), 317 (u8 *) &val, sizeof(val), 318 100); 319 if (unlikely(r)) { 320 ath_print(common, ATH_DBG_WMI, 321 "REGISTER WRITE FAILED:(0x%04x, %d)\n", 322 reg_offset, r); 323 } 324} 325 326static void ath9k_regwrite_buffer(void *hw_priv, u32 val, u32 reg_offset) 327{ 328 struct ath_hw *ah = (struct ath_hw *) hw_priv; 329 struct ath_common *common = ath9k_hw_common(ah); 330 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 331 u32 rsp_status; 332 int r; 333 334 mutex_lock(&priv->wmi->multi_write_mutex); 335 336 /* Store the register/value */ 337 priv->wmi->multi_write[priv->wmi->multi_write_idx].reg = 338 cpu_to_be32(reg_offset); 339 priv->wmi->multi_write[priv->wmi->multi_write_idx].val = 340 cpu_to_be32(val); 341 342 priv->wmi->multi_write_idx++; 343 344 /* If the buffer is full, send it out. */ 345 if (priv->wmi->multi_write_idx == MAX_CMD_NUMBER) { 346 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, 347 (u8 *) &priv->wmi->multi_write, 348 sizeof(struct register_write) * priv->wmi->multi_write_idx, 349 (u8 *) &rsp_status, sizeof(rsp_status), 350 100); 351 if (unlikely(r)) { 352 ath_print(common, ATH_DBG_WMI, 353 "REGISTER WRITE FAILED, multi len: %d\n", 354 priv->wmi->multi_write_idx); 355 } 356 priv->wmi->multi_write_idx = 0; 357 } 358 359 mutex_unlock(&priv->wmi->multi_write_mutex); 360} 361 362static void ath9k_regwrite(void *hw_priv, u32 val, u32 reg_offset) 363{ 364 struct ath_hw *ah = (struct ath_hw *) hw_priv; 365 struct ath_common *common = ath9k_hw_common(ah); 366 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 367 368 if (atomic_read(&priv->wmi->mwrite_cnt)) 369 ath9k_regwrite_buffer(hw_priv, val, reg_offset); 370 else 371 ath9k_regwrite_single(hw_priv, val, reg_offset); 372} 373 374static void ath9k_enable_regwrite_buffer(void *hw_priv) 375{ 376 struct ath_hw *ah = (struct ath_hw *) hw_priv; 377 struct ath_common *common = ath9k_hw_common(ah); 378 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 379 380 atomic_inc(&priv->wmi->mwrite_cnt); 381} 382 383static void ath9k_disable_regwrite_buffer(void *hw_priv) 384{ 385 struct ath_hw *ah = (struct ath_hw *) hw_priv; 386 struct ath_common *common = ath9k_hw_common(ah); 387 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 388 389 atomic_dec(&priv->wmi->mwrite_cnt); 390} 391 392static void ath9k_regwrite_flush(void *hw_priv) 393{ 394 struct ath_hw *ah = (struct ath_hw *) hw_priv; 395 struct ath_common *common = ath9k_hw_common(ah); 396 struct ath9k_htc_priv *priv = (struct ath9k_htc_priv *) common->priv; 397 u32 rsp_status; 398 int r; 399 400 mutex_lock(&priv->wmi->multi_write_mutex); 401 402 if (priv->wmi->multi_write_idx) { 403 r = ath9k_wmi_cmd(priv->wmi, WMI_REG_WRITE_CMDID, 404 (u8 *) &priv->wmi->multi_write, 405 sizeof(struct register_write) * priv->wmi->multi_write_idx, 406 (u8 *) &rsp_status, sizeof(rsp_status), 407 100); 408 if (unlikely(r)) { 409 ath_print(common, ATH_DBG_WMI, 410 "REGISTER WRITE FAILED, multi len: %d\n", 411 priv->wmi->multi_write_idx); 412 } 413 priv->wmi->multi_write_idx = 0; 414 } 415 416 mutex_unlock(&priv->wmi->multi_write_mutex); 417} 418 419static const struct ath_ops ath9k_common_ops = { 420 .read = ath9k_regread, 421 .write = ath9k_regwrite, 422 .enable_write_buffer = ath9k_enable_regwrite_buffer, 423 .disable_write_buffer = ath9k_disable_regwrite_buffer, 424 .write_flush = ath9k_regwrite_flush, 425}; 426 427static void ath_usb_read_cachesize(struct ath_common *common, int *csz) 428{ 429 *csz = L1_CACHE_BYTES >> 2; 430} 431 432static bool ath_usb_eeprom_read(struct ath_common *common, u32 off, u16 *data) 433{ 434 struct ath_hw *ah = (struct ath_hw *) common->ah; 435 436 (void)REG_READ(ah, AR5416_EEPROM_OFFSET + (off << AR5416_EEPROM_S)); 437 438 if (!ath9k_hw_wait(ah, 439 AR_EEPROM_STATUS_DATA, 440 AR_EEPROM_STATUS_DATA_BUSY | 441 AR_EEPROM_STATUS_DATA_PROT_ACCESS, 0, 442 AH_WAIT_TIMEOUT)) 443 return false; 444 445 *data = MS(REG_READ(ah, AR_EEPROM_STATUS_DATA), 446 AR_EEPROM_STATUS_DATA_VAL); 447 448 return true; 449} 450 451static const struct ath_bus_ops ath9k_usb_bus_ops = { 452 .ath_bus_type = ATH_USB, 453 .read_cachesize = ath_usb_read_cachesize, 454 .eeprom_read = ath_usb_eeprom_read, 455}; 456 457static void setup_ht_cap(struct ath9k_htc_priv *priv, 458 struct ieee80211_sta_ht_cap *ht_info) 459{ 460 struct ath_common *common = ath9k_hw_common(priv->ah); 461 u8 tx_streams, rx_streams; 462 int i; 463 464 ht_info->ht_supported = true; 465 ht_info->cap = IEEE80211_HT_CAP_SUP_WIDTH_20_40 | 466 IEEE80211_HT_CAP_SM_PS | 467 IEEE80211_HT_CAP_SGI_40 | 468 IEEE80211_HT_CAP_DSSSCCK40; 469 470 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_SGI_20) 471 ht_info->cap |= IEEE80211_HT_CAP_SGI_20; 472 473 ht_info->cap |= (1 << IEEE80211_HT_CAP_RX_STBC_SHIFT); 474 475 ht_info->ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; 476 ht_info->ampdu_density = IEEE80211_HT_MPDU_DENSITY_8; 477 478 memset(&ht_info->mcs, 0, sizeof(ht_info->mcs)); 479 480 /* ath9k_htc supports only 1 or 2 stream devices */ 481 tx_streams = ath9k_cmn_count_streams(common->tx_chainmask, 2); 482 rx_streams = ath9k_cmn_count_streams(common->rx_chainmask, 2); 483 484 ath_print(common, ATH_DBG_CONFIG, 485 "TX streams %d, RX streams: %d\n", 486 tx_streams, rx_streams); 487 488 if (tx_streams != rx_streams) { 489 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_RX_DIFF; 490 ht_info->mcs.tx_params |= ((tx_streams - 1) << 491 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT); 492 } 493 494 for (i = 0; i < rx_streams; i++) 495 ht_info->mcs.rx_mask[i] = 0xff; 496 497 ht_info->mcs.tx_params |= IEEE80211_HT_MCS_TX_DEFINED; 498} 499 500static int ath9k_init_queues(struct ath9k_htc_priv *priv) 501{ 502 struct ath_common *common = ath9k_hw_common(priv->ah); 503 int i; 504 505 for (i = 0; i < ARRAY_SIZE(priv->hwq_map); i++) 506 priv->hwq_map[i] = -1; 507 508 priv->beaconq = ath9k_hw_beaconq_setup(priv->ah); 509 if (priv->beaconq == -1) { 510 ath_print(common, ATH_DBG_FATAL, 511 "Unable to setup BEACON xmit queue\n"); 512 goto err; 513 } 514 515 priv->cabq = ath9k_htc_cabq_setup(priv); 516 if (priv->cabq == -1) { 517 ath_print(common, ATH_DBG_FATAL, 518 "Unable to setup CAB xmit queue\n"); 519 goto err; 520 } 521 522 if (!ath9k_htc_txq_setup(priv, WME_AC_BE)) { 523 ath_print(common, ATH_DBG_FATAL, 524 "Unable to setup xmit queue for BE traffic\n"); 525 goto err; 526 } 527 528 if (!ath9k_htc_txq_setup(priv, WME_AC_BK)) { 529 ath_print(common, ATH_DBG_FATAL, 530 "Unable to setup xmit queue for BK traffic\n"); 531 goto err; 532 } 533 if (!ath9k_htc_txq_setup(priv, WME_AC_VI)) { 534 ath_print(common, ATH_DBG_FATAL, 535 "Unable to setup xmit queue for VI traffic\n"); 536 goto err; 537 } 538 if (!ath9k_htc_txq_setup(priv, WME_AC_VO)) { 539 ath_print(common, ATH_DBG_FATAL, 540 "Unable to setup xmit queue for VO traffic\n"); 541 goto err; 542 } 543 544 return 0; 545 546err: 547 return -EINVAL; 548} 549 550static void ath9k_init_crypto(struct ath9k_htc_priv *priv) 551{ 552 struct ath_common *common = ath9k_hw_common(priv->ah); 553 int i = 0; 554 555 /* Get the hardware key cache size. */ 556 common->keymax = priv->ah->caps.keycache_size; 557 if (common->keymax > ATH_KEYMAX) { 558 ath_print(common, ATH_DBG_ANY, 559 "Warning, using only %u entries in %u key cache\n", 560 ATH_KEYMAX, common->keymax); 561 common->keymax = ATH_KEYMAX; 562 } 563 564 /* 565 * Reset the key cache since some parts do not 566 * reset the contents on initial power up. 567 */ 568 for (i = 0; i < common->keymax; i++) 569 ath9k_hw_keyreset(priv->ah, (u16) i); 570} 571 572static void ath9k_init_channels_rates(struct ath9k_htc_priv *priv) 573{ 574 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) { 575 priv->sbands[IEEE80211_BAND_2GHZ].channels = 576 ath9k_2ghz_channels; 577 priv->sbands[IEEE80211_BAND_2GHZ].band = IEEE80211_BAND_2GHZ; 578 priv->sbands[IEEE80211_BAND_2GHZ].n_channels = 579 ARRAY_SIZE(ath9k_2ghz_channels); 580 priv->sbands[IEEE80211_BAND_2GHZ].bitrates = ath9k_legacy_rates; 581 priv->sbands[IEEE80211_BAND_2GHZ].n_bitrates = 582 ARRAY_SIZE(ath9k_legacy_rates); 583 } 584 585 if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes)) { 586 priv->sbands[IEEE80211_BAND_5GHZ].channels = ath9k_5ghz_channels; 587 priv->sbands[IEEE80211_BAND_5GHZ].band = IEEE80211_BAND_5GHZ; 588 priv->sbands[IEEE80211_BAND_5GHZ].n_channels = 589 ARRAY_SIZE(ath9k_5ghz_channels); 590 priv->sbands[IEEE80211_BAND_5GHZ].bitrates = 591 ath9k_legacy_rates + 4; 592 priv->sbands[IEEE80211_BAND_5GHZ].n_bitrates = 593 ARRAY_SIZE(ath9k_legacy_rates) - 4; 594 } 595} 596 597static void ath9k_init_misc(struct ath9k_htc_priv *priv) 598{ 599 struct ath_common *common = ath9k_hw_common(priv->ah); 600 601 common->tx_chainmask = priv->ah->caps.tx_chainmask; 602 common->rx_chainmask = priv->ah->caps.rx_chainmask; 603 604 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_BSSIDMASK) 605 memcpy(common->bssidmask, ath_bcast_mac, ETH_ALEN); 606 607 priv->ah->opmode = NL80211_IFTYPE_STATION; 608} 609 610static int ath9k_init_priv(struct ath9k_htc_priv *priv, u16 devid) 611{ 612 struct ath_hw *ah = NULL; 613 struct ath_common *common; 614 int ret = 0, csz = 0; 615 616 priv->op_flags |= OP_INVALID; 617 618 ah = kzalloc(sizeof(struct ath_hw), GFP_KERNEL); 619 if (!ah) 620 return -ENOMEM; 621 622 ah->hw_version.devid = devid; 623 ah->hw_version.subsysid = 0; 624 priv->ah = ah; 625 626 common = ath9k_hw_common(ah); 627 common->ops = &ath9k_common_ops; 628 common->bus_ops = &ath9k_usb_bus_ops; 629 common->ah = ah; 630 common->hw = priv->hw; 631 common->priv = priv; 632 common->debug_mask = ath9k_debug; 633 634 spin_lock_init(&priv->wmi->wmi_lock); 635 spin_lock_init(&priv->beacon_lock); 636 spin_lock_init(&priv->tx_lock); 637 mutex_init(&priv->mutex); 638 mutex_init(&priv->htc_pm_lock); 639 tasklet_init(&priv->wmi_tasklet, ath9k_wmi_tasklet, 640 (unsigned long)priv); 641 tasklet_init(&priv->rx_tasklet, ath9k_rx_tasklet, 642 (unsigned long)priv); 643 tasklet_init(&priv->tx_tasklet, ath9k_tx_tasklet, (unsigned long)priv); 644 INIT_DELAYED_WORK(&priv->ath9k_ani_work, ath9k_ani_work); 645 INIT_WORK(&priv->ps_work, ath9k_ps_work); 646 647 /* 648 * Cache line size is used to size and align various 649 * structures used to communicate with the hardware. 650 */ 651 ath_read_cachesize(common, &csz); 652 common->cachelsz = csz << 2; /* convert to bytes */ 653 654 ret = ath9k_hw_init(ah); 655 if (ret) { 656 ath_print(common, ATH_DBG_FATAL, 657 "Unable to initialize hardware; " 658 "initialization status: %d\n", ret); 659 goto err_hw; 660 } 661 662 ret = ath9k_htc_init_debug(ah); 663 if (ret) { 664 ath_print(common, ATH_DBG_FATAL, 665 "Unable to create debugfs files\n"); 666 goto err_debug; 667 } 668 669 ret = ath9k_init_queues(priv); 670 if (ret) 671 goto err_queues; 672 673 ath9k_init_crypto(priv); 674 ath9k_init_channels_rates(priv); 675 ath9k_init_misc(priv); 676 677 return 0; 678 679err_queues: 680 ath9k_htc_exit_debug(ah); 681err_debug: 682 ath9k_hw_deinit(ah); 683err_hw: 684 685 kfree(ah); 686 priv->ah = NULL; 687 688 return ret; 689} 690 691static void ath9k_set_hw_capab(struct ath9k_htc_priv *priv, 692 struct ieee80211_hw *hw) 693{ 694 struct ath_common *common = ath9k_hw_common(priv->ah); 695 696 hw->flags = IEEE80211_HW_SIGNAL_DBM | 697 IEEE80211_HW_AMPDU_AGGREGATION | 698 IEEE80211_HW_SPECTRUM_MGMT | 699 IEEE80211_HW_HAS_RATE_CONTROL | 700 IEEE80211_HW_RX_INCLUDES_FCS | 701 IEEE80211_HW_SUPPORTS_PS | 702 IEEE80211_HW_PS_NULLFUNC_STACK; 703 704 hw->wiphy->interface_modes = 705 BIT(NL80211_IFTYPE_STATION) | 706 BIT(NL80211_IFTYPE_ADHOC); 707 708 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 709 710 hw->queues = 4; 711 hw->channel_change_time = 5000; 712 hw->max_listen_interval = 10; 713 hw->vif_data_size = sizeof(struct ath9k_htc_vif); 714 hw->sta_data_size = sizeof(struct ath9k_htc_sta); 715 716 /* tx_frame_hdr is larger than tx_mgmt_hdr anyway */ 717 hw->extra_tx_headroom = sizeof(struct tx_frame_hdr) + 718 sizeof(struct htc_frame_hdr) + 4; 719 720 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) 721 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = 722 &priv->sbands[IEEE80211_BAND_2GHZ]; 723 if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes)) 724 hw->wiphy->bands[IEEE80211_BAND_5GHZ] = 725 &priv->sbands[IEEE80211_BAND_5GHZ]; 726 727 if (priv->ah->caps.hw_caps & ATH9K_HW_CAP_HT) { 728 if (test_bit(ATH9K_MODE_11G, priv->ah->caps.wireless_modes)) 729 setup_ht_cap(priv, 730 &priv->sbands[IEEE80211_BAND_2GHZ].ht_cap); 731 if (test_bit(ATH9K_MODE_11A, priv->ah->caps.wireless_modes)) 732 setup_ht_cap(priv, 733 &priv->sbands[IEEE80211_BAND_5GHZ].ht_cap); 734 } 735 736 SET_IEEE80211_PERM_ADDR(hw, common->macaddr); 737} 738 739static int ath9k_init_device(struct ath9k_htc_priv *priv, u16 devid) 740{ 741 struct ieee80211_hw *hw = priv->hw; 742 struct ath_common *common; 743 struct ath_hw *ah; 744 int error = 0; 745 struct ath_regulatory *reg; 746 747 /* Bring up device */ 748 error = ath9k_init_priv(priv, devid); 749 if (error != 0) 750 goto err_init; 751 752 ah = priv->ah; 753 common = ath9k_hw_common(ah); 754 ath9k_set_hw_capab(priv, hw); 755 756 /* Initialize regulatory */ 757 error = ath_regd_init(&common->regulatory, priv->hw->wiphy, 758 ath9k_reg_notifier); 759 if (error) 760 goto err_regd; 761 762 reg = &common->regulatory; 763 764 /* Setup TX */ 765 error = ath9k_tx_init(priv); 766 if (error != 0) 767 goto err_tx; 768 769 /* Setup RX */ 770 error = ath9k_rx_init(priv); 771 if (error != 0) 772 goto err_rx; 773 774 /* Register with mac80211 */ 775 error = ieee80211_register_hw(hw); 776 if (error) 777 goto err_register; 778 779 /* Handle world regulatory */ 780 if (!ath_is_world_regd(reg)) { 781 error = regulatory_hint(hw->wiphy, reg->alpha2); 782 if (error) 783 goto err_world; 784 } 785 786 ath9k_init_leds(priv); 787 ath9k_start_rfkill_poll(priv); 788 789 return 0; 790 791err_world: 792 ieee80211_unregister_hw(hw); 793err_register: 794 ath9k_rx_cleanup(priv); 795err_rx: 796 ath9k_tx_cleanup(priv); 797err_tx: 798 /* Nothing */ 799err_regd: 800 ath9k_deinit_priv(priv); 801err_init: 802 return error; 803} 804 805int ath9k_htc_probe_device(struct htc_target *htc_handle, struct device *dev, 806 u16 devid) 807{ 808 struct ieee80211_hw *hw; 809 struct ath9k_htc_priv *priv; 810 int ret; 811 812 hw = ieee80211_alloc_hw(sizeof(struct ath9k_htc_priv), &ath9k_htc_ops); 813 if (!hw) 814 return -ENOMEM; 815 816 priv = hw->priv; 817 priv->hw = hw; 818 priv->htc = htc_handle; 819 priv->dev = dev; 820 htc_handle->drv_priv = priv; 821 SET_IEEE80211_DEV(hw, priv->dev); 822 823 ret = ath9k_htc_wait_for_target(priv); 824 if (ret) 825 goto err_free; 826 827 priv->wmi = ath9k_init_wmi(priv); 828 if (!priv->wmi) { 829 ret = -EINVAL; 830 goto err_free; 831 } 832 833 ret = ath9k_init_htc_services(priv, devid); 834 if (ret) 835 goto err_init; 836 837 /* The device may have been unplugged earlier. */ 838 priv->op_flags &= ~OP_UNPLUGGED; 839 840 ret = ath9k_init_device(priv, devid); 841 if (ret) 842 goto err_init; 843 844 return 0; 845 846err_init: 847 ath9k_deinit_wmi(priv); 848err_free: 849 ieee80211_free_hw(hw); 850 return ret; 851} 852 853void ath9k_htc_disconnect_device(struct htc_target *htc_handle, bool hotunplug) 854{ 855 if (htc_handle->drv_priv) { 856 857 /* Check if the device has been yanked out. */ 858 if (hotunplug) 859 htc_handle->drv_priv->op_flags |= OP_UNPLUGGED; 860 861 ath9k_deinit_device(htc_handle->drv_priv); 862 ath9k_deinit_wmi(htc_handle->drv_priv); 863 ieee80211_free_hw(htc_handle->drv_priv->hw); 864 } 865} 866 867#ifdef CONFIG_PM 868int ath9k_htc_resume(struct htc_target *htc_handle) 869{ 870 int ret; 871 872 ret = ath9k_htc_wait_for_target(htc_handle->drv_priv); 873 if (ret) 874 return ret; 875 876 ret = ath9k_init_htc_services(htc_handle->drv_priv, 877 htc_handle->drv_priv->ah->hw_version.devid); 878 return ret; 879} 880#endif 881 882static int __init ath9k_htc_init(void) 883{ 884 int error; 885 886 error = ath9k_htc_debug_create_root(); 887 if (error < 0) { 888 printk(KERN_ERR 889 "ath9k_htc: Unable to create debugfs root: %d\n", 890 error); 891 goto err_dbg; 892 } 893 894 error = ath9k_hif_usb_init(); 895 if (error < 0) { 896 printk(KERN_ERR 897 "ath9k_htc: No USB devices found," 898 " driver not installed.\n"); 899 error = -ENODEV; 900 goto err_usb; 901 } 902 903 return 0; 904 905err_usb: 906 ath9k_htc_debug_remove_root(); 907err_dbg: 908 return error; 909} 910module_init(ath9k_htc_init); 911 912static void __exit ath9k_htc_exit(void) 913{ 914 ath9k_hif_usb_exit(); 915 ath9k_htc_debug_remove_root(); 916 printk(KERN_INFO "ath9k_htc: Driver unloaded\n"); 917} 918module_exit(ath9k_htc_exit); 919