1/* 2 * Copyright (c) 2008-2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#ifndef EEPROM_H 18#define EEPROM_H 19 20#include "../ath.h" 21#include <net/cfg80211.h> 22#include "ar9003_eeprom.h" 23 24#define AH_USE_EEPROM 0x1 25 26#ifdef __BIG_ENDIAN 27#define AR5416_EEPROM_MAGIC 0x5aa5 28#else 29#define AR5416_EEPROM_MAGIC 0xa55a 30#endif 31 32#define CTRY_DEBUG 0x1ff 33#define CTRY_DEFAULT 0 34 35#define AR_EEPROM_EEPCAP_COMPRESS_DIS 0x0001 36#define AR_EEPROM_EEPCAP_AES_DIS 0x0002 37#define AR_EEPROM_EEPCAP_FASTFRAME_DIS 0x0004 38#define AR_EEPROM_EEPCAP_BURST_DIS 0x0008 39#define AR_EEPROM_EEPCAP_MAXQCU 0x01F0 40#define AR_EEPROM_EEPCAP_MAXQCU_S 4 41#define AR_EEPROM_EEPCAP_HEAVY_CLIP_EN 0x0200 42#define AR_EEPROM_EEPCAP_KC_ENTRIES 0xF000 43#define AR_EEPROM_EEPCAP_KC_ENTRIES_S 12 44 45#define AR_EEPROM_EEREGCAP_EN_FCC_MIDBAND 0x0040 46#define AR_EEPROM_EEREGCAP_EN_KK_U1_EVEN 0x0080 47#define AR_EEPROM_EEREGCAP_EN_KK_U2 0x0100 48#define AR_EEPROM_EEREGCAP_EN_KK_MIDBAND 0x0200 49#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD 0x0400 50#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A 0x0800 51 52#define AR_EEPROM_EEREGCAP_EN_KK_U1_ODD_PRE4_0 0x4000 53#define AR_EEPROM_EEREGCAP_EN_KK_NEW_11A_PRE4_0 0x8000 54 55#define AR5416_EEPROM_MAGIC_OFFSET 0x0 56#define AR5416_EEPROM_S 2 57#define AR5416_EEPROM_OFFSET 0x2000 58#define AR5416_EEPROM_MAX 0xae0 59 60#define AR5416_EEPROM_START_ADDR \ 61 (AR_SREV_9100(ah)) ? 0x1fff1000 : 0x503f1200 62 63#define SD_NO_CTL 0xE0 64#define NO_CTL 0xff 65#define CTL_MODE_M 0xf 66#define CTL_11A 0 67#define CTL_11B 1 68#define CTL_11G 2 69#define CTL_2GHT20 5 70#define CTL_5GHT20 6 71#define CTL_2GHT40 7 72#define CTL_5GHT40 8 73 74#define EXT_ADDITIVE (0x8000) 75#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE) 76#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE) 77#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE) 78 79#define SUB_NUM_CTL_MODES_AT_5G_40 2 80#define SUB_NUM_CTL_MODES_AT_2G_40 3 81 82#define INCREASE_MAXPOW_BY_TWO_CHAIN 6 /* 10*log10(2)*2 */ 83#define INCREASE_MAXPOW_BY_THREE_CHAIN 10 /* 10*log10(3)*2 */ 84 85/* 86 * For AR9285 and later chipsets, the following bits are not being programmed 87 * in EEPROM and so need to be enabled always. 88 * 89 * Bit 0: en_fcc_mid 90 * Bit 1: en_jap_mid 91 * Bit 2: en_fcc_dfs_ht40 92 * Bit 3: en_jap_ht40 93 * Bit 4: en_jap_dfs_ht40 94 */ 95#define AR9285_RDEXT_DEFAULT 0x1F 96 97#define ATH9K_POW_SM(_r, _s) (((_r) & 0x3f) << (_s)) 98#define FREQ2FBIN(x, y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) 99#define ath9k_hw_use_flash(_ah) (!(_ah->ah_flags & AH_USE_EEPROM)) 100 101#define AR5416_VER_MASK (eep->baseEepHeader.version & AR5416_EEP_VER_MINOR_MASK) 102#define OLC_FOR_AR9280_20_LATER (AR_SREV_9280_20_OR_LATER(ah) && \ 103 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 104#define OLC_FOR_AR9287_10_LATER (AR_SREV_9287_10_OR_LATER(ah) && \ 105 ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL)) 106 107#define AR_EEPROM_RFSILENT_GPIO_SEL 0x001c 108#define AR_EEPROM_RFSILENT_GPIO_SEL_S 2 109#define AR_EEPROM_RFSILENT_POLARITY 0x0002 110#define AR_EEPROM_RFSILENT_POLARITY_S 1 111 112#define EEP_RFSILENT_ENABLED 0x0001 113#define EEP_RFSILENT_ENABLED_S 0 114#define EEP_RFSILENT_POLARITY 0x0002 115#define EEP_RFSILENT_POLARITY_S 1 116#define EEP_RFSILENT_GPIO_SEL 0x001c 117#define EEP_RFSILENT_GPIO_SEL_S 2 118 119#define AR5416_OPFLAGS_11A 0x01 120#define AR5416_OPFLAGS_11G 0x02 121#define AR5416_OPFLAGS_N_5G_HT40 0x04 122#define AR5416_OPFLAGS_N_2G_HT40 0x08 123#define AR5416_OPFLAGS_N_5G_HT20 0x10 124#define AR5416_OPFLAGS_N_2G_HT20 0x20 125 126#define AR5416_EEP_NO_BACK_VER 0x1 127#define AR5416_EEP_VER 0xE 128#define AR5416_EEP_VER_MINOR_MASK 0x0FFF 129#define AR5416_EEP_MINOR_VER_2 0x2 130#define AR5416_EEP_MINOR_VER_3 0x3 131#define AR5416_EEP_MINOR_VER_7 0x7 132#define AR5416_EEP_MINOR_VER_9 0x9 133#define AR5416_EEP_MINOR_VER_16 0x10 134#define AR5416_EEP_MINOR_VER_17 0x11 135#define AR5416_EEP_MINOR_VER_19 0x13 136#define AR5416_EEP_MINOR_VER_20 0x14 137#define AR5416_EEP_MINOR_VER_21 0x15 138#define AR5416_EEP_MINOR_VER_22 0x16 139 140#define AR5416_NUM_5G_CAL_PIERS 8 141#define AR5416_NUM_2G_CAL_PIERS 4 142#define AR5416_NUM_5G_20_TARGET_POWERS 8 143#define AR5416_NUM_5G_40_TARGET_POWERS 8 144#define AR5416_NUM_2G_CCK_TARGET_POWERS 3 145#define AR5416_NUM_2G_20_TARGET_POWERS 4 146#define AR5416_NUM_2G_40_TARGET_POWERS 4 147#define AR5416_NUM_CTLS 24 148#define AR5416_NUM_BAND_EDGES 8 149#define AR5416_NUM_PD_GAINS 4 150#define AR5416_PD_GAINS_IN_MASK 4 151#define AR5416_PD_GAIN_ICEPTS 5 152#define AR5416_EEPROM_MODAL_SPURS 5 153#define AR5416_MAX_RATE_POWER 63 154#define AR5416_NUM_PDADC_VALUES 128 155#define AR5416_BCHAN_UNUSED 0xFF 156#define AR5416_MAX_PWR_RANGE_IN_HALF_DB 64 157#define AR5416_MAX_CHAINS 3 158#define AR9300_MAX_CHAINS 3 159#define AR5416_PWR_TABLE_OFFSET_DB -5 160 161/* Rx gain type values */ 162#define AR5416_EEP_RXGAIN_23DB_BACKOFF 0 163#define AR5416_EEP_RXGAIN_13DB_BACKOFF 1 164#define AR5416_EEP_RXGAIN_ORIG 2 165 166/* Tx gain type values */ 167#define AR5416_EEP_TXGAIN_ORIGINAL 0 168#define AR5416_EEP_TXGAIN_HIGH_POWER 1 169 170#define AR5416_EEP4K_START_LOC 64 171#define AR5416_EEP4K_NUM_2G_CAL_PIERS 3 172#define AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS 3 173#define AR5416_EEP4K_NUM_2G_20_TARGET_POWERS 3 174#define AR5416_EEP4K_NUM_2G_40_TARGET_POWERS 3 175#define AR5416_EEP4K_NUM_CTLS 12 176#define AR5416_EEP4K_NUM_BAND_EDGES 4 177#define AR5416_EEP4K_NUM_PD_GAINS 2 178#define AR5416_EEP4K_PD_GAINS_IN_MASK 4 179#define AR5416_EEP4K_PD_GAIN_ICEPTS 5 180#define AR5416_EEP4K_MAX_CHAINS 1 181 182#define AR9280_TX_GAIN_TABLE_SIZE 22 183 184#define AR9287_EEP_VER 0xE 185#define AR9287_EEP_VER_MINOR_MASK 0xFFF 186#define AR9287_EEP_MINOR_VER_1 0x1 187#define AR9287_EEP_MINOR_VER_2 0x2 188#define AR9287_EEP_MINOR_VER_3 0x3 189#define AR9287_EEP_MINOR_VER AR9287_EEP_MINOR_VER_3 190#define AR9287_EEP_MINOR_VER_b AR9287_EEP_MINOR_VER 191#define AR9287_EEP_NO_BACK_VER AR9287_EEP_MINOR_VER_1 192 193#define AR9287_EEP_START_LOC 128 194#define AR9287_HTC_EEP_START_LOC 256 195#define AR9287_NUM_2G_CAL_PIERS 3 196#define AR9287_NUM_2G_CCK_TARGET_POWERS 3 197#define AR9287_NUM_2G_20_TARGET_POWERS 3 198#define AR9287_NUM_2G_40_TARGET_POWERS 3 199#define AR9287_NUM_CTLS 12 200#define AR9287_NUM_BAND_EDGES 4 201#define AR9287_NUM_PD_GAINS 4 202#define AR9287_PD_GAINS_IN_MASK 4 203#define AR9287_PD_GAIN_ICEPTS 1 204#define AR9287_EEPROM_MODAL_SPURS 5 205#define AR9287_MAX_RATE_POWER 63 206#define AR9287_NUM_PDADC_VALUES 128 207#define AR9287_NUM_RATES 16 208#define AR9287_BCHAN_UNUSED 0xFF 209#define AR9287_MAX_PWR_RANGE_IN_HALF_DB 64 210#define AR9287_OPFLAGS_11A 0x01 211#define AR9287_OPFLAGS_11G 0x02 212#define AR9287_OPFLAGS_2G_HT40 0x08 213#define AR9287_OPFLAGS_2G_HT20 0x20 214#define AR9287_OPFLAGS_5G_HT40 0x04 215#define AR9287_OPFLAGS_5G_HT20 0x10 216#define AR9287_EEPMISC_BIG_ENDIAN 0x01 217#define AR9287_EEPMISC_WOW 0x02 218#define AR9287_MAX_CHAINS 2 219#define AR9287_ANT_16S 32 220#define AR9287_custdatasize 20 221 222#define AR9287_NUM_ANT_CHAIN_FIELDS 6 223#define AR9287_NUM_ANT_COMMON_FIELDS 4 224#define AR9287_SIZE_ANT_CHAIN_FIELD 2 225#define AR9287_SIZE_ANT_COMMON_FIELD 4 226#define AR9287_ANT_CHAIN_MASK 0x3 227#define AR9287_ANT_COMMON_MASK 0xf 228#define AR9287_CHAIN_0_IDX 0 229#define AR9287_CHAIN_1_IDX 1 230#define AR9287_DATA_SZ 32 231 232#define AR9287_PWR_TABLE_OFFSET_DB -5 233 234#define AR9287_CHECKSUM_LOCATION (AR9287_EEP_START_LOC + 1) 235 236#define CTL_EDGE_TPOWER(_ctl) ((_ctl) & 0x3f) 237#define CTL_EDGE_FLAGS(_ctl) (((_ctl) >> 6) & 0x03) 238 239enum eeprom_param { 240 EEP_NFTHRESH_5, 241 EEP_NFTHRESH_2, 242 EEP_MAC_MSW, 243 EEP_MAC_MID, 244 EEP_MAC_LSW, 245 EEP_REG_0, 246 EEP_REG_1, 247 EEP_OP_CAP, 248 EEP_OP_MODE, 249 EEP_RF_SILENT, 250 EEP_OB_5, 251 EEP_DB_5, 252 EEP_OB_2, 253 EEP_DB_2, 254 EEP_MINOR_REV, 255 EEP_TX_MASK, 256 EEP_RX_MASK, 257 EEP_FSTCLK_5G, 258 EEP_RXGAIN_TYPE, 259 EEP_OL_PWRCTRL, 260 EEP_TXGAIN_TYPE, 261 EEP_RC_CHAIN_MASK, 262 EEP_DAC_HPWR_5G, 263 EEP_FRAC_N_5G, 264 EEP_DEV_TYPE, 265 EEP_TEMPSENSE_SLOPE, 266 EEP_TEMPSENSE_SLOPE_PAL_ON, 267 EEP_PWR_TABLE_OFFSET, 268 EEP_DRIVE_STRENGTH, 269 EEP_INTERNAL_REGULATOR, 270 EEP_SWREG, 271 EEP_PAPRD, 272}; 273 274enum ar5416_rates { 275 rate6mb, rate9mb, rate12mb, rate18mb, 276 rate24mb, rate36mb, rate48mb, rate54mb, 277 rate1l, rate2l, rate2s, rate5_5l, 278 rate5_5s, rate11l, rate11s, rateXr, 279 rateHt20_0, rateHt20_1, rateHt20_2, rateHt20_3, 280 rateHt20_4, rateHt20_5, rateHt20_6, rateHt20_7, 281 rateHt40_0, rateHt40_1, rateHt40_2, rateHt40_3, 282 rateHt40_4, rateHt40_5, rateHt40_6, rateHt40_7, 283 rateDupCck, rateDupOfdm, rateExtCck, rateExtOfdm, 284 Ar5416RateSize 285}; 286 287enum ath9k_hal_freq_band { 288 ATH9K_HAL_FREQ_BAND_5GHZ = 0, 289 ATH9K_HAL_FREQ_BAND_2GHZ = 1 290}; 291 292struct base_eep_header { 293 u16 length; 294 u16 checksum; 295 u16 version; 296 u8 opCapFlags; 297 u8 eepMisc; 298 u16 regDmn[2]; 299 u8 macAddr[6]; 300 u8 rxMask; 301 u8 txMask; 302 u16 rfSilent; 303 u16 blueToothOptions; 304 u16 deviceCap; 305 u32 binBuildNumber; 306 u8 deviceType; 307 u8 pwdclkind; 308 u8 fastClk5g; 309 u8 divChain; 310 u8 rxGainType; 311 u8 dacHiPwrMode_5G; 312 u8 openLoopPwrCntl; 313 u8 dacLpMode; 314 u8 txGainType; 315 u8 rcChainMask; 316 u8 desiredScaleCCK; 317 u8 pwr_table_offset; 318 u8 frac_n_5g; 319 u8 futureBase_3[21]; 320} __packed; 321 322struct base_eep_header_4k { 323 u16 length; 324 u16 checksum; 325 u16 version; 326 u8 opCapFlags; 327 u8 eepMisc; 328 u16 regDmn[2]; 329 u8 macAddr[6]; 330 u8 rxMask; 331 u8 txMask; 332 u16 rfSilent; 333 u16 blueToothOptions; 334 u16 deviceCap; 335 u32 binBuildNumber; 336 u8 deviceType; 337 u8 txGainType; 338} __packed; 339 340 341struct spur_chan { 342 u16 spurChan; 343 u8 spurRangeLow; 344 u8 spurRangeHigh; 345} __packed; 346 347struct modal_eep_header { 348 u32 antCtrlChain[AR5416_MAX_CHAINS]; 349 u32 antCtrlCommon; 350 u8 antennaGainCh[AR5416_MAX_CHAINS]; 351 u8 switchSettling; 352 u8 txRxAttenCh[AR5416_MAX_CHAINS]; 353 u8 rxTxMarginCh[AR5416_MAX_CHAINS]; 354 u8 adcDesiredSize; 355 u8 pgaDesiredSize; 356 u8 xlnaGainCh[AR5416_MAX_CHAINS]; 357 u8 txEndToXpaOff; 358 u8 txEndToRxOn; 359 u8 txFrameToXpaOn; 360 u8 thresh62; 361 u8 noiseFloorThreshCh[AR5416_MAX_CHAINS]; 362 u8 xpdGain; 363 u8 xpd; 364 u8 iqCalICh[AR5416_MAX_CHAINS]; 365 u8 iqCalQCh[AR5416_MAX_CHAINS]; 366 u8 pdGainOverlap; 367 u8 ob; 368 u8 db; 369 u8 xpaBiasLvl; 370 u8 pwrDecreaseFor2Chain; 371 u8 pwrDecreaseFor3Chain; 372 u8 txFrameToDataStart; 373 u8 txFrameToPaOn; 374 u8 ht40PowerIncForPdadc; 375 u8 bswAtten[AR5416_MAX_CHAINS]; 376 u8 bswMargin[AR5416_MAX_CHAINS]; 377 u8 swSettleHt40; 378 u8 xatten2Db[AR5416_MAX_CHAINS]; 379 u8 xatten2Margin[AR5416_MAX_CHAINS]; 380 u8 ob_ch1; 381 u8 db_ch1; 382 u8 useAnt1:1, 383 force_xpaon:1, 384 local_bias:1, 385 femBandSelectUsed:1, xlnabufin:1, xlnaisel:2, xlnabufmode:1; 386 u8 miscBits; 387 u16 xpaBiasLvlFreq[3]; 388 u8 futureModal[6]; 389 390 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; 391} __packed; 392 393struct calDataPerFreqOpLoop { 394 u8 pwrPdg[2][5]; 395 u8 vpdPdg[2][5]; 396 u8 pcdac[2][5]; 397 u8 empty[2][5]; 398} __packed; 399 400struct modal_eep_4k_header { 401 u32 antCtrlChain[AR5416_EEP4K_MAX_CHAINS]; 402 u32 antCtrlCommon; 403 u8 antennaGainCh[AR5416_EEP4K_MAX_CHAINS]; 404 u8 switchSettling; 405 u8 txRxAttenCh[AR5416_EEP4K_MAX_CHAINS]; 406 u8 rxTxMarginCh[AR5416_EEP4K_MAX_CHAINS]; 407 u8 adcDesiredSize; 408 u8 pgaDesiredSize; 409 u8 xlnaGainCh[AR5416_EEP4K_MAX_CHAINS]; 410 u8 txEndToXpaOff; 411 u8 txEndToRxOn; 412 u8 txFrameToXpaOn; 413 u8 thresh62; 414 u8 noiseFloorThreshCh[AR5416_EEP4K_MAX_CHAINS]; 415 u8 xpdGain; 416 u8 xpd; 417 u8 iqCalICh[AR5416_EEP4K_MAX_CHAINS]; 418 u8 iqCalQCh[AR5416_EEP4K_MAX_CHAINS]; 419 u8 pdGainOverlap; 420#ifdef __BIG_ENDIAN_BITFIELD 421 u8 ob_1:4, ob_0:4; 422 u8 db1_1:4, db1_0:4; 423#else 424 u8 ob_0:4, ob_1:4; 425 u8 db1_0:4, db1_1:4; 426#endif 427 u8 xpaBiasLvl; 428 u8 txFrameToDataStart; 429 u8 txFrameToPaOn; 430 u8 ht40PowerIncForPdadc; 431 u8 bswAtten[AR5416_EEP4K_MAX_CHAINS]; 432 u8 bswMargin[AR5416_EEP4K_MAX_CHAINS]; 433 u8 swSettleHt40; 434 u8 xatten2Db[AR5416_EEP4K_MAX_CHAINS]; 435 u8 xatten2Margin[AR5416_EEP4K_MAX_CHAINS]; 436#ifdef __BIG_ENDIAN_BITFIELD 437 u8 db2_1:4, db2_0:4; 438#else 439 u8 db2_0:4, db2_1:4; 440#endif 441 u8 version; 442#ifdef __BIG_ENDIAN_BITFIELD 443 u8 ob_3:4, ob_2:4; 444 u8 antdiv_ctl1:4, ob_4:4; 445 u8 db1_3:4, db1_2:4; 446 u8 antdiv_ctl2:4, db1_4:4; 447 u8 db2_2:4, db2_3:4; 448 u8 reserved:4, db2_4:4; 449#else 450 u8 ob_2:4, ob_3:4; 451 u8 ob_4:4, antdiv_ctl1:4; 452 u8 db1_2:4, db1_3:4; 453 u8 db1_4:4, antdiv_ctl2:4; 454 u8 db2_2:4, db2_3:4; 455 u8 db2_4:4, reserved:4; 456#endif 457 u8 futureModal[4]; 458 struct spur_chan spurChans[AR5416_EEPROM_MODAL_SPURS]; 459} __packed; 460 461struct base_eep_ar9287_header { 462 u16 length; 463 u16 checksum; 464 u16 version; 465 u8 opCapFlags; 466 u8 eepMisc; 467 u16 regDmn[2]; 468 u8 macAddr[6]; 469 u8 rxMask; 470 u8 txMask; 471 u16 rfSilent; 472 u16 blueToothOptions; 473 u16 deviceCap; 474 u32 binBuildNumber; 475 u8 deviceType; 476 u8 openLoopPwrCntl; 477 int8_t pwrTableOffset; 478 int8_t tempSensSlope; 479 int8_t tempSensSlopePalOn; 480 u8 futureBase[29]; 481} __packed; 482 483struct modal_eep_ar9287_header { 484 u32 antCtrlChain[AR9287_MAX_CHAINS]; 485 u32 antCtrlCommon; 486 int8_t antennaGainCh[AR9287_MAX_CHAINS]; 487 u8 switchSettling; 488 u8 txRxAttenCh[AR9287_MAX_CHAINS]; 489 u8 rxTxMarginCh[AR9287_MAX_CHAINS]; 490 int8_t adcDesiredSize; 491 u8 txEndToXpaOff; 492 u8 txEndToRxOn; 493 u8 txFrameToXpaOn; 494 u8 thresh62; 495 int8_t noiseFloorThreshCh[AR9287_MAX_CHAINS]; 496 u8 xpdGain; 497 u8 xpd; 498 int8_t iqCalICh[AR9287_MAX_CHAINS]; 499 int8_t iqCalQCh[AR9287_MAX_CHAINS]; 500 u8 pdGainOverlap; 501 u8 xpaBiasLvl; 502 u8 txFrameToDataStart; 503 u8 txFrameToPaOn; 504 u8 ht40PowerIncForPdadc; 505 u8 bswAtten[AR9287_MAX_CHAINS]; 506 u8 bswMargin[AR9287_MAX_CHAINS]; 507 u8 swSettleHt40; 508 u8 version; 509 u8 db1; 510 u8 db2; 511 u8 ob_cck; 512 u8 ob_psk; 513 u8 ob_qam; 514 u8 ob_pal_off; 515 u8 futureModal[30]; 516 struct spur_chan spurChans[AR9287_EEPROM_MODAL_SPURS]; 517} __packed; 518 519struct cal_data_per_freq { 520 u8 pwrPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 521 u8 vpdPdg[AR5416_NUM_PD_GAINS][AR5416_PD_GAIN_ICEPTS]; 522} __packed; 523 524struct cal_data_per_freq_4k { 525 u8 pwrPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; 526 u8 vpdPdg[AR5416_EEP4K_NUM_PD_GAINS][AR5416_EEP4K_PD_GAIN_ICEPTS]; 527} __packed; 528 529struct cal_target_power_leg { 530 u8 bChannel; 531 u8 tPow2x[4]; 532} __packed; 533 534struct cal_target_power_ht { 535 u8 bChannel; 536 u8 tPow2x[8]; 537} __packed; 538 539struct cal_ctl_edges { 540 u8 bChannel; 541 u8 ctl; 542} __packed; 543 544struct cal_data_op_loop_ar9287 { 545 u8 pwrPdg[2][5]; 546 u8 vpdPdg[2][5]; 547 u8 pcdac[2][5]; 548 u8 empty[2][5]; 549} __packed; 550 551struct cal_data_per_freq_ar9287 { 552 u8 pwrPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 553 u8 vpdPdg[AR9287_NUM_PD_GAINS][AR9287_PD_GAIN_ICEPTS]; 554} __packed; 555 556union cal_data_per_freq_ar9287_u { 557 struct cal_data_op_loop_ar9287 calDataOpen; 558 struct cal_data_per_freq_ar9287 calDataClose; 559} __packed; 560 561struct cal_ctl_data_ar9287 { 562 struct cal_ctl_edges 563 ctlEdges[AR9287_MAX_CHAINS][AR9287_NUM_BAND_EDGES]; 564} __packed; 565 566struct cal_ctl_data { 567 struct cal_ctl_edges 568 ctlEdges[AR5416_MAX_CHAINS][AR5416_NUM_BAND_EDGES]; 569} __packed; 570 571struct cal_ctl_data_4k { 572 struct cal_ctl_edges 573 ctlEdges[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_BAND_EDGES]; 574} __packed; 575 576struct ar5416_eeprom_def { 577 struct base_eep_header baseEepHeader; 578 u8 custData[64]; 579 struct modal_eep_header modalHeader[2]; 580 u8 calFreqPier5G[AR5416_NUM_5G_CAL_PIERS]; 581 u8 calFreqPier2G[AR5416_NUM_2G_CAL_PIERS]; 582 struct cal_data_per_freq 583 calPierData5G[AR5416_MAX_CHAINS][AR5416_NUM_5G_CAL_PIERS]; 584 struct cal_data_per_freq 585 calPierData2G[AR5416_MAX_CHAINS][AR5416_NUM_2G_CAL_PIERS]; 586 struct cal_target_power_leg 587 calTargetPower5G[AR5416_NUM_5G_20_TARGET_POWERS]; 588 struct cal_target_power_ht 589 calTargetPower5GHT20[AR5416_NUM_5G_20_TARGET_POWERS]; 590 struct cal_target_power_ht 591 calTargetPower5GHT40[AR5416_NUM_5G_40_TARGET_POWERS]; 592 struct cal_target_power_leg 593 calTargetPowerCck[AR5416_NUM_2G_CCK_TARGET_POWERS]; 594 struct cal_target_power_leg 595 calTargetPower2G[AR5416_NUM_2G_20_TARGET_POWERS]; 596 struct cal_target_power_ht 597 calTargetPower2GHT20[AR5416_NUM_2G_20_TARGET_POWERS]; 598 struct cal_target_power_ht 599 calTargetPower2GHT40[AR5416_NUM_2G_40_TARGET_POWERS]; 600 u8 ctlIndex[AR5416_NUM_CTLS]; 601 struct cal_ctl_data ctlData[AR5416_NUM_CTLS]; 602 u8 padding; 603} __packed; 604 605struct ar5416_eeprom_4k { 606 struct base_eep_header_4k baseEepHeader; 607 u8 custData[20]; 608 struct modal_eep_4k_header modalHeader; 609 u8 calFreqPier2G[AR5416_EEP4K_NUM_2G_CAL_PIERS]; 610 struct cal_data_per_freq_4k 611 calPierData2G[AR5416_EEP4K_MAX_CHAINS][AR5416_EEP4K_NUM_2G_CAL_PIERS]; 612 struct cal_target_power_leg 613 calTargetPowerCck[AR5416_EEP4K_NUM_2G_CCK_TARGET_POWERS]; 614 struct cal_target_power_leg 615 calTargetPower2G[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 616 struct cal_target_power_ht 617 calTargetPower2GHT20[AR5416_EEP4K_NUM_2G_20_TARGET_POWERS]; 618 struct cal_target_power_ht 619 calTargetPower2GHT40[AR5416_EEP4K_NUM_2G_40_TARGET_POWERS]; 620 u8 ctlIndex[AR5416_EEP4K_NUM_CTLS]; 621 struct cal_ctl_data_4k ctlData[AR5416_EEP4K_NUM_CTLS]; 622 u8 padding; 623} __packed; 624 625struct ar9287_eeprom { 626 struct base_eep_ar9287_header baseEepHeader; 627 u8 custData[AR9287_DATA_SZ]; 628 struct modal_eep_ar9287_header modalHeader; 629 u8 calFreqPier2G[AR9287_NUM_2G_CAL_PIERS]; 630 union cal_data_per_freq_ar9287_u 631 calPierData2G[AR9287_MAX_CHAINS][AR9287_NUM_2G_CAL_PIERS]; 632 struct cal_target_power_leg 633 calTargetPowerCck[AR9287_NUM_2G_CCK_TARGET_POWERS]; 634 struct cal_target_power_leg 635 calTargetPower2G[AR9287_NUM_2G_20_TARGET_POWERS]; 636 struct cal_target_power_ht 637 calTargetPower2GHT20[AR9287_NUM_2G_20_TARGET_POWERS]; 638 struct cal_target_power_ht 639 calTargetPower2GHT40[AR9287_NUM_2G_40_TARGET_POWERS]; 640 u8 ctlIndex[AR9287_NUM_CTLS]; 641 struct cal_ctl_data_ar9287 ctlData[AR9287_NUM_CTLS]; 642 u8 padding; 643} __packed; 644 645enum reg_ext_bitmap { 646 REG_EXT_FCC_MIDBAND = 0, 647 REG_EXT_JAPAN_MIDBAND = 1, 648 REG_EXT_FCC_DFS_HT40 = 2, 649 REG_EXT_JAPAN_NONDFS_HT40 = 3, 650 REG_EXT_JAPAN_DFS_HT40 = 4 651}; 652 653struct ath9k_country_entry { 654 u16 countryCode; 655 u16 regDmnEnum; 656 u16 regDmn5G; 657 u16 regDmn2G; 658 u8 isMultidomain; 659 u8 iso[3]; 660}; 661 662struct eeprom_ops { 663 int (*check_eeprom)(struct ath_hw *hw); 664 u32 (*get_eeprom)(struct ath_hw *hw, enum eeprom_param param); 665 bool (*fill_eeprom)(struct ath_hw *hw); 666 int (*get_eeprom_ver)(struct ath_hw *hw); 667 int (*get_eeprom_rev)(struct ath_hw *hw); 668 u8 (*get_num_ant_config)(struct ath_hw *hw, enum ieee80211_band band); 669 u32 (*get_eeprom_antenna_cfg)(struct ath_hw *hw, 670 struct ath9k_channel *chan); 671 void (*set_board_values)(struct ath_hw *hw, struct ath9k_channel *chan); 672 void (*set_addac)(struct ath_hw *hw, struct ath9k_channel *chan); 673 void (*set_txpower)(struct ath_hw *hw, struct ath9k_channel *chan, 674 u16 cfgCtl, u8 twiceAntennaReduction, 675 u8 twiceMaxRegulatoryPower, u8 powerLimit); 676 u16 (*get_spur_channel)(struct ath_hw *ah, u16 i, bool is2GHz); 677}; 678 679void ath9k_hw_analog_shift_regwrite(struct ath_hw *ah, u32 reg, u32 val); 680void ath9k_hw_analog_shift_rmw(struct ath_hw *ah, u32 reg, u32 mask, 681 u32 shift, u32 val); 682int16_t ath9k_hw_interpolate(u16 target, u16 srcLeft, u16 srcRight, 683 int16_t targetLeft, 684 int16_t targetRight); 685bool ath9k_hw_get_lower_upper_index(u8 target, u8 *pList, u16 listSize, 686 u16 *indexL, u16 *indexR); 687bool ath9k_hw_nvram_read(struct ath_common *common, u32 off, u16 *data); 688void ath9k_hw_fill_vpd_table(u8 pwrMin, u8 pwrMax, u8 *pPwrList, 689 u8 *pVpdList, u16 numIntercepts, 690 u8 *pRetVpdList); 691void ath9k_hw_get_legacy_target_powers(struct ath_hw *ah, 692 struct ath9k_channel *chan, 693 struct cal_target_power_leg *powInfo, 694 u16 numChannels, 695 struct cal_target_power_leg *pNewPower, 696 u16 numRates, bool isExtTarget); 697void ath9k_hw_get_target_powers(struct ath_hw *ah, 698 struct ath9k_channel *chan, 699 struct cal_target_power_ht *powInfo, 700 u16 numChannels, 701 struct cal_target_power_ht *pNewPower, 702 u16 numRates, bool isHt40Target); 703u16 ath9k_hw_get_max_edge_power(u16 freq, struct cal_ctl_edges *pRdEdgesPower, 704 bool is2GHz, int num_band_edges); 705void ath9k_hw_update_regulatory_maxpower(struct ath_hw *ah); 706int ath9k_hw_eeprom_init(struct ath_hw *ah); 707 708#define ar5416_get_ntxchains(_txchainmask) \ 709 (((_txchainmask >> 2) & 1) + \ 710 ((_txchainmask >> 1) & 1) + (_txchainmask & 1)) 711 712extern const struct eeprom_ops eep_def_ops; 713extern const struct eeprom_ops eep_4k_ops; 714extern const struct eeprom_ops eep_ar9287_ops; 715extern const struct eeprom_ops eep_ar9287_ops; 716extern const struct eeprom_ops eep_ar9300_ops; 717 718#endif /* EEPROM_H */ 719