1/* 2 * Copyright (c) 2009 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "hw.h" 18 19enum ath_bt_mode { 20 ATH_BT_COEX_MODE_LEGACY, /* legacy rx_clear mode */ 21 ATH_BT_COEX_MODE_UNSLOTTED, /* untimed/unslotted mode */ 22 ATH_BT_COEX_MODE_SLOTTED, /* slotted mode */ 23 ATH_BT_COEX_MODE_DISALBED, /* coexistence disabled */ 24}; 25 26struct ath_btcoex_config { 27 u8 bt_time_extend; 28 bool bt_txstate_extend; 29 bool bt_txframe_extend; 30 enum ath_bt_mode bt_mode; /* coexistence mode */ 31 bool bt_quiet_collision; 32 bool bt_rxclear_polarity; /* invert rx_clear as WLAN_ACTIVE*/ 33 u8 bt_priority_time; 34 u8 bt_first_slot_time; 35 bool bt_hold_rx_clear; 36}; 37 38static const u16 ath_subsysid_tbl[] = { 39 AR9280_COEX2WIRE_SUBSYSID, 40 AT9285_COEX3WIRE_SA_SUBSYSID, 41 AT9285_COEX3WIRE_DA_SUBSYSID 42}; 43 44/* 45 * Checks the subsystem id of the device to see if it 46 * supports btcoex 47 */ 48bool ath9k_hw_btcoex_supported(struct ath_hw *ah) 49{ 50 int i; 51 52 if (!ah->hw_version.subsysid) 53 return false; 54 55 for (i = 0; i < ARRAY_SIZE(ath_subsysid_tbl); i++) 56 if (ah->hw_version.subsysid == ath_subsysid_tbl[i]) 57 return true; 58 59 return false; 60} 61 62void ath9k_hw_init_btcoex_hw(struct ath_hw *ah, int qnum) 63{ 64 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 65 const struct ath_btcoex_config ath_bt_config = { 66 .bt_time_extend = 0, 67 .bt_txstate_extend = true, 68 .bt_txframe_extend = true, 69 .bt_mode = ATH_BT_COEX_MODE_SLOTTED, 70 .bt_quiet_collision = true, 71 .bt_rxclear_polarity = true, 72 .bt_priority_time = 2, 73 .bt_first_slot_time = 5, 74 .bt_hold_rx_clear = true, 75 }; 76 u32 i; 77 78 btcoex_hw->bt_coex_mode = 79 (btcoex_hw->bt_coex_mode & AR_BT_QCU_THRESH) | 80 SM(ath_bt_config.bt_time_extend, AR_BT_TIME_EXTEND) | 81 SM(ath_bt_config.bt_txstate_extend, AR_BT_TXSTATE_EXTEND) | 82 SM(ath_bt_config.bt_txframe_extend, AR_BT_TX_FRAME_EXTEND) | 83 SM(ath_bt_config.bt_mode, AR_BT_MODE) | 84 SM(ath_bt_config.bt_quiet_collision, AR_BT_QUIET) | 85 SM(ath_bt_config.bt_rxclear_polarity, AR_BT_RX_CLEAR_POLARITY) | 86 SM(ath_bt_config.bt_priority_time, AR_BT_PRIORITY_TIME) | 87 SM(ath_bt_config.bt_first_slot_time, AR_BT_FIRST_SLOT_TIME) | 88 SM(qnum, AR_BT_QCU_THRESH); 89 90 btcoex_hw->bt_coex_mode2 = 91 SM(ath_bt_config.bt_hold_rx_clear, AR_BT_HOLD_RX_CLEAR) | 92 SM(ATH_BTCOEX_BMISS_THRESH, AR_BT_BCN_MISS_THRESH) | 93 AR_BT_DISABLE_BT_ANT; 94 95 for (i = 0; i < 32; i++) 96 ah->hw_gen_timers.gen_timer_index[(debruijn32 << i) >> 27] = i; 97} 98EXPORT_SYMBOL(ath9k_hw_init_btcoex_hw); 99 100void ath9k_hw_btcoex_init_2wire(struct ath_hw *ah) 101{ 102 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 103 104 /* connect bt_active to baseband */ 105 REG_CLR_BIT(ah, AR_GPIO_INPUT_EN_VAL, 106 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_DEF | 107 AR_GPIO_INPUT_EN_VAL_BT_FREQUENCY_DEF)); 108 109 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 110 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB); 111 112 /* Set input mux for bt_active to gpio pin */ 113 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, 114 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 115 btcoex_hw->btactive_gpio); 116 117 /* Configure the desired gpio port for input */ 118 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio); 119} 120EXPORT_SYMBOL(ath9k_hw_btcoex_init_2wire); 121 122void ath9k_hw_btcoex_init_3wire(struct ath_hw *ah) 123{ 124 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 125 126 /* btcoex 3-wire */ 127 REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL, 128 (AR_GPIO_INPUT_EN_VAL_BT_PRIORITY_BB | 129 AR_GPIO_INPUT_EN_VAL_BT_ACTIVE_BB)); 130 131 /* Set input mux for bt_prority_async and 132 * bt_active_async to GPIO pins */ 133 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, 134 AR_GPIO_INPUT_MUX1_BT_ACTIVE, 135 btcoex_hw->btactive_gpio); 136 137 REG_RMW_FIELD(ah, AR_GPIO_INPUT_MUX1, 138 AR_GPIO_INPUT_MUX1_BT_PRIORITY, 139 btcoex_hw->btpriority_gpio); 140 141 /* Configure the desired GPIO ports for input */ 142 143 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btactive_gpio); 144 ath9k_hw_cfg_gpio_input(ah, btcoex_hw->btpriority_gpio); 145} 146EXPORT_SYMBOL(ath9k_hw_btcoex_init_3wire); 147 148static void ath9k_hw_btcoex_enable_2wire(struct ath_hw *ah) 149{ 150 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 151 152 /* Configure the desired GPIO port for TX_FRAME output */ 153 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio, 154 AR_GPIO_OUTPUT_MUX_AS_TX_FRAME); 155} 156 157void ath9k_hw_btcoex_set_weight(struct ath_hw *ah, 158 u32 bt_weight, 159 u32 wlan_weight) 160{ 161 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 162 163 btcoex_hw->bt_coex_weights = SM(bt_weight, AR_BTCOEX_BT_WGHT) | 164 SM(wlan_weight, AR_BTCOEX_WL_WGHT); 165} 166EXPORT_SYMBOL(ath9k_hw_btcoex_set_weight); 167 168static void ath9k_hw_btcoex_enable_3wire(struct ath_hw *ah) 169{ 170 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 171 172 /* 173 * Program coex mode and weight registers to 174 * enable coex 3-wire 175 */ 176 REG_WRITE(ah, AR_BT_COEX_MODE, btcoex_hw->bt_coex_mode); 177 REG_WRITE(ah, AR_BT_COEX_WEIGHT, btcoex_hw->bt_coex_weights); 178 REG_WRITE(ah, AR_BT_COEX_MODE2, btcoex_hw->bt_coex_mode2); 179 180 REG_RMW_FIELD(ah, AR_QUIET1, AR_QUIET1_QUIET_ACK_CTS_ENABLE, 1); 181 REG_RMW_FIELD(ah, AR_PCU_MISC, AR_PCU_BT_ANT_PREVENT_RX, 0); 182 183 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio, 184 AR_GPIO_OUTPUT_MUX_AS_RX_CLEAR_EXTERNAL); 185} 186 187void ath9k_hw_btcoex_enable(struct ath_hw *ah) 188{ 189 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 190 191 switch (btcoex_hw->scheme) { 192 case ATH_BTCOEX_CFG_NONE: 193 break; 194 case ATH_BTCOEX_CFG_2WIRE: 195 ath9k_hw_btcoex_enable_2wire(ah); 196 break; 197 case ATH_BTCOEX_CFG_3WIRE: 198 ath9k_hw_btcoex_enable_3wire(ah); 199 break; 200 } 201 202 REG_RMW(ah, AR_GPIO_PDPU, 203 (0x2 << (btcoex_hw->btactive_gpio * 2)), 204 (0x3 << (btcoex_hw->btactive_gpio * 2))); 205 206 ah->btcoex_hw.enabled = true; 207} 208EXPORT_SYMBOL(ath9k_hw_btcoex_enable); 209 210void ath9k_hw_btcoex_disable(struct ath_hw *ah) 211{ 212 struct ath_btcoex_hw *btcoex_hw = &ah->btcoex_hw; 213 214 ath9k_hw_set_gpio(ah, btcoex_hw->wlanactive_gpio, 0); 215 216 ath9k_hw_cfg_output(ah, btcoex_hw->wlanactive_gpio, 217 AR_GPIO_OUTPUT_MUX_AS_OUTPUT); 218 219 if (btcoex_hw->scheme == ATH_BTCOEX_CFG_3WIRE) { 220 REG_WRITE(ah, AR_BT_COEX_MODE, AR_BT_QUIET | AR_BT_MODE); 221 REG_WRITE(ah, AR_BT_COEX_WEIGHT, 0); 222 REG_WRITE(ah, AR_BT_COEX_MODE2, 0); 223 } 224 225 ah->btcoex_hw.enabled = false; 226} 227EXPORT_SYMBOL(ath9k_hw_btcoex_disable); 228