1/* 2 * Copyright (c) 2010 Atheros Communications Inc. 3 * 4 * Permission to use, copy, modify, and/or distribute this software for any 5 * purpose with or without fee is hereby granted, provided that the above 6 * copyright notice and this permission notice appear in all copies. 7 * 8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 15 */ 16 17#include "hw.h" 18#include "hw-ops.h" 19#include "ar9003_phy.h" 20 21static void ar9003_hw_setup_calibration(struct ath_hw *ah, 22 struct ath9k_cal_list *currCal) 23{ 24 struct ath_common *common = ath9k_hw_common(ah); 25 26 /* Select calibration to run */ 27 switch (currCal->calData->calType) { 28 case IQ_MISMATCH_CAL: 29 /* 30 * Start calibration with 31 * 2^(INIT_IQCAL_LOG_COUNT_MAX+1) samples 32 */ 33 REG_RMW_FIELD(ah, AR_PHY_TIMING4, 34 AR_PHY_TIMING4_IQCAL_LOG_COUNT_MAX, 35 currCal->calData->calCountMax); 36 REG_WRITE(ah, AR_PHY_CALMODE, AR_PHY_CALMODE_IQ); 37 38 ath_print(common, ATH_DBG_CALIBRATE, 39 "starting IQ Mismatch Calibration\n"); 40 41 /* Kick-off cal */ 42 REG_SET_BIT(ah, AR_PHY_TIMING4, AR_PHY_TIMING4_DO_CAL); 43 break; 44 case TEMP_COMP_CAL: 45 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM, 46 AR_PHY_65NM_CH0_THERM_LOCAL, 1); 47 REG_RMW_FIELD(ah, AR_PHY_65NM_CH0_THERM, 48 AR_PHY_65NM_CH0_THERM_START, 1); 49 50 ath_print(common, ATH_DBG_CALIBRATE, 51 "starting Temperature Compensation Calibration\n"); 52 break; 53 case ADC_DC_INIT_CAL: 54 case ADC_GAIN_CAL: 55 case ADC_DC_CAL: 56 /* Not yet */ 57 break; 58 } 59} 60 61/* 62 * Generic calibration routine. 63 * Recalibrate the lower PHY chips to account for temperature/environment 64 * changes. 65 */ 66static bool ar9003_hw_per_calibration(struct ath_hw *ah, 67 struct ath9k_channel *ichan, 68 u8 rxchainmask, 69 struct ath9k_cal_list *currCal) 70{ 71 struct ath9k_hw_cal_data *caldata = ah->caldata; 72 /* Cal is assumed not done until explicitly set below */ 73 bool iscaldone = false; 74 75 /* Calibration in progress. */ 76 if (currCal->calState == CAL_RUNNING) { 77 /* Check to see if it has finished. */ 78 if (!(REG_READ(ah, AR_PHY_TIMING4) & AR_PHY_TIMING4_DO_CAL)) { 79 /* 80 * Accumulate cal measures for active chains 81 */ 82 currCal->calData->calCollect(ah); 83 ah->cal_samples++; 84 85 if (ah->cal_samples >= 86 currCal->calData->calNumSamples) { 87 unsigned int i, numChains = 0; 88 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 89 if (rxchainmask & (1 << i)) 90 numChains++; 91 } 92 93 /* 94 * Process accumulated data 95 */ 96 currCal->calData->calPostProc(ah, numChains); 97 98 /* Calibration has finished. */ 99 caldata->CalValid |= currCal->calData->calType; 100 currCal->calState = CAL_DONE; 101 iscaldone = true; 102 } else { 103 /* 104 * Set-up collection of another sub-sample until we 105 * get desired number 106 */ 107 ar9003_hw_setup_calibration(ah, currCal); 108 } 109 } 110 } else if (!(caldata->CalValid & currCal->calData->calType)) { 111 /* If current cal is marked invalid in channel, kick it off */ 112 ath9k_hw_reset_calibration(ah, currCal); 113 } 114 115 return iscaldone; 116} 117 118static bool ar9003_hw_calibrate(struct ath_hw *ah, 119 struct ath9k_channel *chan, 120 u8 rxchainmask, 121 bool longcal) 122{ 123 bool iscaldone = true; 124 struct ath9k_cal_list *currCal = ah->cal_list_curr; 125 126 /* 127 * For given calibration: 128 * 1. Call generic cal routine 129 * 2. When this cal is done (isCalDone) if we have more cals waiting 130 * (eg after reset), mask this to upper layers by not propagating 131 * isCalDone if it is set to TRUE. 132 * Instead, change isCalDone to FALSE and setup the waiting cal(s) 133 * to be run. 134 */ 135 if (currCal && 136 (currCal->calState == CAL_RUNNING || 137 currCal->calState == CAL_WAITING)) { 138 iscaldone = ar9003_hw_per_calibration(ah, chan, 139 rxchainmask, currCal); 140 if (iscaldone) { 141 ah->cal_list_curr = currCal = currCal->calNext; 142 143 if (currCal->calState == CAL_WAITING) { 144 iscaldone = false; 145 ath9k_hw_reset_calibration(ah, currCal); 146 } 147 } 148 } 149 150 /* Do NF cal only at longer intervals */ 151 if (longcal) { 152 /* 153 * Get the value from the previous NF cal and update 154 * history buffer. 155 */ 156 ath9k_hw_getnf(ah, chan); 157 158 /* 159 * Load the NF from history buffer of the current channel. 160 * NF is slow time-variant, so it is OK to use a historical 161 * value. 162 */ 163 ath9k_hw_loadnf(ah, ah->curchan); 164 165 /* start NF calibration, without updating BB NF register */ 166 ath9k_hw_start_nfcal(ah, false); 167 } 168 169 return iscaldone; 170} 171 172static void ar9003_hw_iqcal_collect(struct ath_hw *ah) 173{ 174 int i; 175 176 /* Accumulate IQ cal measures for active chains */ 177 for (i = 0; i < AR5416_MAX_CHAINS; i++) { 178 ah->totalPowerMeasI[i] += 179 REG_READ(ah, AR_PHY_CAL_MEAS_0(i)); 180 ah->totalPowerMeasQ[i] += 181 REG_READ(ah, AR_PHY_CAL_MEAS_1(i)); 182 ah->totalIqCorrMeas[i] += 183 (int32_t) REG_READ(ah, AR_PHY_CAL_MEAS_2(i)); 184 ath_print(ath9k_hw_common(ah), ATH_DBG_CALIBRATE, 185 "%d: Chn %d pmi=0x%08x;pmq=0x%08x;iqcm=0x%08x;\n", 186 ah->cal_samples, i, ah->totalPowerMeasI[i], 187 ah->totalPowerMeasQ[i], 188 ah->totalIqCorrMeas[i]); 189 } 190} 191 192static void ar9003_hw_iqcalibrate(struct ath_hw *ah, u8 numChains) 193{ 194 struct ath_common *common = ath9k_hw_common(ah); 195 u32 powerMeasQ, powerMeasI, iqCorrMeas; 196 u32 qCoffDenom, iCoffDenom; 197 int32_t qCoff, iCoff; 198 int iqCorrNeg, i; 199 const u_int32_t offset_array[3] = { 200 AR_PHY_RX_IQCAL_CORR_B0, 201 AR_PHY_RX_IQCAL_CORR_B1, 202 AR_PHY_RX_IQCAL_CORR_B2, 203 }; 204 205 for (i = 0; i < numChains; i++) { 206 powerMeasI = ah->totalPowerMeasI[i]; 207 powerMeasQ = ah->totalPowerMeasQ[i]; 208 iqCorrMeas = ah->totalIqCorrMeas[i]; 209 210 ath_print(common, ATH_DBG_CALIBRATE, 211 "Starting IQ Cal and Correction for Chain %d\n", 212 i); 213 214 ath_print(common, ATH_DBG_CALIBRATE, 215 "Orignal: Chn %diq_corr_meas = 0x%08x\n", 216 i, ah->totalIqCorrMeas[i]); 217 218 iqCorrNeg = 0; 219 220 if (iqCorrMeas > 0x80000000) { 221 iqCorrMeas = (0xffffffff - iqCorrMeas) + 1; 222 iqCorrNeg = 1; 223 } 224 225 ath_print(common, ATH_DBG_CALIBRATE, 226 "Chn %d pwr_meas_i = 0x%08x\n", i, powerMeasI); 227 ath_print(common, ATH_DBG_CALIBRATE, 228 "Chn %d pwr_meas_q = 0x%08x\n", i, powerMeasQ); 229 ath_print(common, ATH_DBG_CALIBRATE, "iqCorrNeg is 0x%08x\n", 230 iqCorrNeg); 231 232 iCoffDenom = (powerMeasI / 2 + powerMeasQ / 2) / 256; 233 qCoffDenom = powerMeasQ / 64; 234 235 if ((iCoffDenom != 0) && (qCoffDenom != 0)) { 236 iCoff = iqCorrMeas / iCoffDenom; 237 qCoff = powerMeasI / qCoffDenom - 64; 238 ath_print(common, ATH_DBG_CALIBRATE, 239 "Chn %d iCoff = 0x%08x\n", i, iCoff); 240 ath_print(common, ATH_DBG_CALIBRATE, 241 "Chn %d qCoff = 0x%08x\n", i, qCoff); 242 243 /* Force bounds on iCoff */ 244 if (iCoff >= 63) 245 iCoff = 63; 246 else if (iCoff <= -63) 247 iCoff = -63; 248 249 /* Negate iCoff if iqCorrNeg == 0 */ 250 if (iqCorrNeg == 0x0) 251 iCoff = -iCoff; 252 253 /* Force bounds on qCoff */ 254 if (qCoff >= 63) 255 qCoff = 63; 256 else if (qCoff <= -63) 257 qCoff = -63; 258 259 iCoff = iCoff & 0x7f; 260 qCoff = qCoff & 0x7f; 261 262 ath_print(common, ATH_DBG_CALIBRATE, 263 "Chn %d : iCoff = 0x%x qCoff = 0x%x\n", 264 i, iCoff, qCoff); 265 ath_print(common, ATH_DBG_CALIBRATE, 266 "Register offset (0x%04x) " 267 "before update = 0x%x\n", 268 offset_array[i], 269 REG_READ(ah, offset_array[i])); 270 271 REG_RMW_FIELD(ah, offset_array[i], 272 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, 273 iCoff); 274 REG_RMW_FIELD(ah, offset_array[i], 275 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, 276 qCoff); 277 ath_print(common, ATH_DBG_CALIBRATE, 278 "Register offset (0x%04x) QI COFF " 279 "(bitfields 0x%08x) after update = 0x%x\n", 280 offset_array[i], 281 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_I_COFF, 282 REG_READ(ah, offset_array[i])); 283 ath_print(common, ATH_DBG_CALIBRATE, 284 "Register offset (0x%04x) QQ COFF " 285 "(bitfields 0x%08x) after update = 0x%x\n", 286 offset_array[i], 287 AR_PHY_RX_IQCAL_CORR_IQCORR_Q_Q_COFF, 288 REG_READ(ah, offset_array[i])); 289 290 ath_print(common, ATH_DBG_CALIBRATE, 291 "IQ Cal and Correction done for Chain %d\n", 292 i); 293 } 294 } 295 296 REG_SET_BIT(ah, AR_PHY_RX_IQCAL_CORR_B0, 297 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE); 298 ath_print(common, ATH_DBG_CALIBRATE, 299 "IQ Cal and Correction (offset 0x%04x) enabled " 300 "(bit position 0x%08x). New Value 0x%08x\n", 301 (unsigned) (AR_PHY_RX_IQCAL_CORR_B0), 302 AR_PHY_RX_IQCAL_CORR_IQCORR_ENABLE, 303 REG_READ(ah, AR_PHY_RX_IQCAL_CORR_B0)); 304} 305 306static const struct ath9k_percal_data iq_cal_single_sample = { 307 IQ_MISMATCH_CAL, 308 MIN_CAL_SAMPLES, 309 PER_MAX_LOG_COUNT, 310 ar9003_hw_iqcal_collect, 311 ar9003_hw_iqcalibrate 312}; 313 314static void ar9003_hw_init_cal_settings(struct ath_hw *ah) 315{ 316 ah->iq_caldata.calData = &iq_cal_single_sample; 317 ah->supp_cals = IQ_MISMATCH_CAL; 318} 319 320static bool ar9003_hw_iscal_supported(struct ath_hw *ah, 321 enum ath9k_cal_types calType) 322{ 323 switch (calType & ah->supp_cals) { 324 case IQ_MISMATCH_CAL: 325 return true; 326 case ADC_GAIN_CAL: 327 case ADC_DC_CAL: 328 return false; 329 case TEMP_COMP_CAL: 330 return true; 331 } 332 333 return false; 334} 335 336/* 337 * solve 4x4 linear equation used in loopback iq cal. 338 */ 339static bool ar9003_hw_solve_iq_cal(struct ath_hw *ah, 340 s32 sin_2phi_1, 341 s32 cos_2phi_1, 342 s32 sin_2phi_2, 343 s32 cos_2phi_2, 344 s32 mag_a0_d0, 345 s32 phs_a0_d0, 346 s32 mag_a1_d0, 347 s32 phs_a1_d0, 348 s32 solved_eq[]) 349{ 350 s32 f1 = cos_2phi_1 - cos_2phi_2, 351 f3 = sin_2phi_1 - sin_2phi_2, 352 f2; 353 s32 mag_tx, phs_tx, mag_rx, phs_rx; 354 const s32 result_shift = 1 << 15; 355 struct ath_common *common = ath9k_hw_common(ah); 356 357 f2 = (f1 * f1 + f3 * f3) / result_shift; 358 359 if (!f2) { 360 ath_print(common, ATH_DBG_CALIBRATE, "Divide by 0\n"); 361 return false; 362 } 363 364 /* mag mismatch, tx */ 365 mag_tx = f1 * (mag_a0_d0 - mag_a1_d0) + f3 * (phs_a0_d0 - phs_a1_d0); 366 /* phs mismatch, tx */ 367 phs_tx = f3 * (-mag_a0_d0 + mag_a1_d0) + f1 * (phs_a0_d0 - phs_a1_d0); 368 369 mag_tx = (mag_tx / f2); 370 phs_tx = (phs_tx / f2); 371 372 /* mag mismatch, rx */ 373 mag_rx = mag_a0_d0 - (cos_2phi_1 * mag_tx + sin_2phi_1 * phs_tx) / 374 result_shift; 375 /* phs mismatch, rx */ 376 phs_rx = phs_a0_d0 + (sin_2phi_1 * mag_tx - cos_2phi_1 * phs_tx) / 377 result_shift; 378 379 solved_eq[0] = mag_tx; 380 solved_eq[1] = phs_tx; 381 solved_eq[2] = mag_rx; 382 solved_eq[3] = phs_rx; 383 384 return true; 385} 386 387static s32 ar9003_hw_find_mag_approx(struct ath_hw *ah, s32 in_re, s32 in_im) 388{ 389 s32 abs_i = abs(in_re), 390 abs_q = abs(in_im), 391 max_abs, min_abs; 392 393 if (abs_i > abs_q) { 394 max_abs = abs_i; 395 min_abs = abs_q; 396 } else { 397 max_abs = abs_q; 398 min_abs = abs_i; 399 } 400 401 return max_abs - (max_abs / 32) + (min_abs / 8) + (min_abs / 4); 402} 403 404#define DELPT 32 405 406static bool ar9003_hw_calc_iq_corr(struct ath_hw *ah, 407 s32 chain_idx, 408 const s32 iq_res[], 409 s32 iqc_coeff[]) 410{ 411 s32 i2_m_q2_a0_d0, i2_p_q2_a0_d0, iq_corr_a0_d0, 412 i2_m_q2_a0_d1, i2_p_q2_a0_d1, iq_corr_a0_d1, 413 i2_m_q2_a1_d0, i2_p_q2_a1_d0, iq_corr_a1_d0, 414 i2_m_q2_a1_d1, i2_p_q2_a1_d1, iq_corr_a1_d1; 415 s32 mag_a0_d0, mag_a1_d0, mag_a0_d1, mag_a1_d1, 416 phs_a0_d0, phs_a1_d0, phs_a0_d1, phs_a1_d1, 417 sin_2phi_1, cos_2phi_1, 418 sin_2phi_2, cos_2phi_2; 419 s32 mag_tx, phs_tx, mag_rx, phs_rx; 420 s32 solved_eq[4], mag_corr_tx, phs_corr_tx, mag_corr_rx, phs_corr_rx, 421 q_q_coff, q_i_coff; 422 const s32 res_scale = 1 << 15; 423 const s32 delpt_shift = 1 << 8; 424 s32 mag1, mag2; 425 struct ath_common *common = ath9k_hw_common(ah); 426 427 i2_m_q2_a0_d0 = iq_res[0] & 0xfff; 428 i2_p_q2_a0_d0 = (iq_res[0] >> 12) & 0xfff; 429 iq_corr_a0_d0 = ((iq_res[0] >> 24) & 0xff) + ((iq_res[1] & 0xf) << 8); 430 431 if (i2_m_q2_a0_d0 > 0x800) 432 i2_m_q2_a0_d0 = -((0xfff - i2_m_q2_a0_d0) + 1); 433 434 if (i2_p_q2_a0_d0 > 0x800) 435 i2_p_q2_a0_d0 = -((0xfff - i2_p_q2_a0_d0) + 1); 436 437 if (iq_corr_a0_d0 > 0x800) 438 iq_corr_a0_d0 = -((0xfff - iq_corr_a0_d0) + 1); 439 440 i2_m_q2_a0_d1 = (iq_res[1] >> 4) & 0xfff; 441 i2_p_q2_a0_d1 = (iq_res[2] & 0xfff); 442 iq_corr_a0_d1 = (iq_res[2] >> 12) & 0xfff; 443 444 if (i2_m_q2_a0_d1 > 0x800) 445 i2_m_q2_a0_d1 = -((0xfff - i2_m_q2_a0_d1) + 1); 446 447 if (i2_p_q2_a0_d1 > 0x800) 448 i2_p_q2_a0_d1 = -((0xfff - i2_p_q2_a0_d1) + 1); 449 450 if (iq_corr_a0_d1 > 0x800) 451 iq_corr_a0_d1 = -((0xfff - iq_corr_a0_d1) + 1); 452 453 i2_m_q2_a1_d0 = ((iq_res[2] >> 24) & 0xff) + ((iq_res[3] & 0xf) << 8); 454 i2_p_q2_a1_d0 = (iq_res[3] >> 4) & 0xfff; 455 iq_corr_a1_d0 = iq_res[4] & 0xfff; 456 457 if (i2_m_q2_a1_d0 > 0x800) 458 i2_m_q2_a1_d0 = -((0xfff - i2_m_q2_a1_d0) + 1); 459 460 if (i2_p_q2_a1_d0 > 0x800) 461 i2_p_q2_a1_d0 = -((0xfff - i2_p_q2_a1_d0) + 1); 462 463 if (iq_corr_a1_d0 > 0x800) 464 iq_corr_a1_d0 = -((0xfff - iq_corr_a1_d0) + 1); 465 466 i2_m_q2_a1_d1 = (iq_res[4] >> 12) & 0xfff; 467 i2_p_q2_a1_d1 = ((iq_res[4] >> 24) & 0xff) + ((iq_res[5] & 0xf) << 8); 468 iq_corr_a1_d1 = (iq_res[5] >> 4) & 0xfff; 469 470 if (i2_m_q2_a1_d1 > 0x800) 471 i2_m_q2_a1_d1 = -((0xfff - i2_m_q2_a1_d1) + 1); 472 473 if (i2_p_q2_a1_d1 > 0x800) 474 i2_p_q2_a1_d1 = -((0xfff - i2_p_q2_a1_d1) + 1); 475 476 if (iq_corr_a1_d1 > 0x800) 477 iq_corr_a1_d1 = -((0xfff - iq_corr_a1_d1) + 1); 478 479 if ((i2_p_q2_a0_d0 == 0) || (i2_p_q2_a0_d1 == 0) || 480 (i2_p_q2_a1_d0 == 0) || (i2_p_q2_a1_d1 == 0)) { 481 ath_print(common, ATH_DBG_CALIBRATE, 482 "Divide by 0:\na0_d0=%d\n" 483 "a0_d1=%d\na2_d0=%d\na1_d1=%d\n", 484 i2_p_q2_a0_d0, i2_p_q2_a0_d1, 485 i2_p_q2_a1_d0, i2_p_q2_a1_d1); 486 return false; 487 } 488 489 mag_a0_d0 = (i2_m_q2_a0_d0 * res_scale) / i2_p_q2_a0_d0; 490 phs_a0_d0 = (iq_corr_a0_d0 * res_scale) / i2_p_q2_a0_d0; 491 492 mag_a0_d1 = (i2_m_q2_a0_d1 * res_scale) / i2_p_q2_a0_d1; 493 phs_a0_d1 = (iq_corr_a0_d1 * res_scale) / i2_p_q2_a0_d1; 494 495 mag_a1_d0 = (i2_m_q2_a1_d0 * res_scale) / i2_p_q2_a1_d0; 496 phs_a1_d0 = (iq_corr_a1_d0 * res_scale) / i2_p_q2_a1_d0; 497 498 mag_a1_d1 = (i2_m_q2_a1_d1 * res_scale) / i2_p_q2_a1_d1; 499 phs_a1_d1 = (iq_corr_a1_d1 * res_scale) / i2_p_q2_a1_d1; 500 501 /* w/o analog phase shift */ 502 sin_2phi_1 = (((mag_a0_d0 - mag_a0_d1) * delpt_shift) / DELPT); 503 /* w/o analog phase shift */ 504 cos_2phi_1 = (((phs_a0_d1 - phs_a0_d0) * delpt_shift) / DELPT); 505 /* w/ analog phase shift */ 506 sin_2phi_2 = (((mag_a1_d0 - mag_a1_d1) * delpt_shift) / DELPT); 507 /* w/ analog phase shift */ 508 cos_2phi_2 = (((phs_a1_d1 - phs_a1_d0) * delpt_shift) / DELPT); 509 510 /* 511 * force sin^2 + cos^2 = 1; 512 * find magnitude by approximation 513 */ 514 mag1 = ar9003_hw_find_mag_approx(ah, cos_2phi_1, sin_2phi_1); 515 mag2 = ar9003_hw_find_mag_approx(ah, cos_2phi_2, sin_2phi_2); 516 517 if ((mag1 == 0) || (mag2 == 0)) { 518 ath_print(common, ATH_DBG_CALIBRATE, 519 "Divide by 0: mag1=%d, mag2=%d\n", 520 mag1, mag2); 521 return false; 522 } 523 524 /* normalization sin and cos by mag */ 525 sin_2phi_1 = (sin_2phi_1 * res_scale / mag1); 526 cos_2phi_1 = (cos_2phi_1 * res_scale / mag1); 527 sin_2phi_2 = (sin_2phi_2 * res_scale / mag2); 528 cos_2phi_2 = (cos_2phi_2 * res_scale / mag2); 529 530 /* calculate IQ mismatch */ 531 if (!ar9003_hw_solve_iq_cal(ah, 532 sin_2phi_1, cos_2phi_1, 533 sin_2phi_2, cos_2phi_2, 534 mag_a0_d0, phs_a0_d0, 535 mag_a1_d0, 536 phs_a1_d0, solved_eq)) { 537 ath_print(common, ATH_DBG_CALIBRATE, 538 "Call to ar9003_hw_solve_iq_cal() failed.\n"); 539 return false; 540 } 541 542 mag_tx = solved_eq[0]; 543 phs_tx = solved_eq[1]; 544 mag_rx = solved_eq[2]; 545 phs_rx = solved_eq[3]; 546 547 ath_print(common, ATH_DBG_CALIBRATE, 548 "chain %d: mag mismatch=%d phase mismatch=%d\n", 549 chain_idx, mag_tx/res_scale, phs_tx/res_scale); 550 551 if (res_scale == mag_tx) { 552 ath_print(common, ATH_DBG_CALIBRATE, 553 "Divide by 0: mag_tx=%d, res_scale=%d\n", 554 mag_tx, res_scale); 555 return false; 556 } 557 558 /* calculate and quantize Tx IQ correction factor */ 559 mag_corr_tx = (mag_tx * res_scale) / (res_scale - mag_tx); 560 phs_corr_tx = -phs_tx; 561 562 q_q_coff = (mag_corr_tx * 128 / res_scale); 563 q_i_coff = (phs_corr_tx * 256 / res_scale); 564 565 ath_print(common, ATH_DBG_CALIBRATE, 566 "tx chain %d: mag corr=%d phase corr=%d\n", 567 chain_idx, q_q_coff, q_i_coff); 568 569 if (q_i_coff < -63) 570 q_i_coff = -63; 571 if (q_i_coff > 63) 572 q_i_coff = 63; 573 if (q_q_coff < -63) 574 q_q_coff = -63; 575 if (q_q_coff > 63) 576 q_q_coff = 63; 577 578 iqc_coeff[0] = (q_q_coff * 128) + q_i_coff; 579 580 ath_print(common, ATH_DBG_CALIBRATE, 581 "tx chain %d: iq corr coeff=%x\n", 582 chain_idx, iqc_coeff[0]); 583 584 if (-mag_rx == res_scale) { 585 ath_print(common, ATH_DBG_CALIBRATE, 586 "Divide by 0: mag_rx=%d, res_scale=%d\n", 587 mag_rx, res_scale); 588 return false; 589 } 590 591 /* calculate and quantize Rx IQ correction factors */ 592 mag_corr_rx = (-mag_rx * res_scale) / (res_scale + mag_rx); 593 phs_corr_rx = -phs_rx; 594 595 q_q_coff = (mag_corr_rx * 128 / res_scale); 596 q_i_coff = (phs_corr_rx * 256 / res_scale); 597 598 ath_print(common, ATH_DBG_CALIBRATE, 599 "rx chain %d: mag corr=%d phase corr=%d\n", 600 chain_idx, q_q_coff, q_i_coff); 601 602 if (q_i_coff < -63) 603 q_i_coff = -63; 604 if (q_i_coff > 63) 605 q_i_coff = 63; 606 if (q_q_coff < -63) 607 q_q_coff = -63; 608 if (q_q_coff > 63) 609 q_q_coff = 63; 610 611 iqc_coeff[1] = (q_q_coff * 128) + q_i_coff; 612 613 ath_print(common, ATH_DBG_CALIBRATE, 614 "rx chain %d: iq corr coeff=%x\n", 615 chain_idx, iqc_coeff[1]); 616 617 return true; 618} 619 620static void ar9003_hw_tx_iq_cal(struct ath_hw *ah) 621{ 622 struct ath_common *common = ath9k_hw_common(ah); 623 const u32 txiqcal_status[AR9300_MAX_CHAINS] = { 624 AR_PHY_TX_IQCAL_STATUS_B0, 625 AR_PHY_TX_IQCAL_STATUS_B1, 626 AR_PHY_TX_IQCAL_STATUS_B2, 627 }; 628 const u32 tx_corr_coeff[AR9300_MAX_CHAINS] = { 629 AR_PHY_TX_IQCAL_CORR_COEFF_01_B0, 630 AR_PHY_TX_IQCAL_CORR_COEFF_01_B1, 631 AR_PHY_TX_IQCAL_CORR_COEFF_01_B2, 632 }; 633 const u32 rx_corr[AR9300_MAX_CHAINS] = { 634 AR_PHY_RX_IQCAL_CORR_B0, 635 AR_PHY_RX_IQCAL_CORR_B1, 636 AR_PHY_RX_IQCAL_CORR_B2, 637 }; 638 const u_int32_t chan_info_tab[] = { 639 AR_PHY_CHAN_INFO_TAB_0, 640 AR_PHY_CHAN_INFO_TAB_1, 641 AR_PHY_CHAN_INFO_TAB_2, 642 }; 643 s32 iq_res[6]; 644 s32 iqc_coeff[2]; 645 s32 i, j; 646 u32 num_chains = 0; 647 648 for (i = 0; i < AR9300_MAX_CHAINS; i++) { 649 if (ah->txchainmask & (1 << i)) 650 num_chains++; 651 } 652 653 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_1, 654 AR_PHY_TX_IQCAQL_CONTROL_1_IQCORR_I_Q_COFF_DELPT, 655 DELPT); 656 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_START, 657 AR_PHY_TX_IQCAL_START_DO_CAL, 658 AR_PHY_TX_IQCAL_START_DO_CAL); 659 660 if (!ath9k_hw_wait(ah, AR_PHY_TX_IQCAL_START, 661 AR_PHY_TX_IQCAL_START_DO_CAL, 662 0, AH_WAIT_TIMEOUT)) { 663 ath_print(common, ATH_DBG_CALIBRATE, 664 "Tx IQ Cal not complete.\n"); 665 goto TX_IQ_CAL_FAILED; 666 } 667 668 for (i = 0; i < num_chains; i++) { 669 ath_print(common, ATH_DBG_CALIBRATE, 670 "Doing Tx IQ Cal for chain %d.\n", i); 671 672 if (REG_READ(ah, txiqcal_status[i]) & 673 AR_PHY_TX_IQCAL_STATUS_FAILED) { 674 ath_print(common, ATH_DBG_CALIBRATE, 675 "Tx IQ Cal failed for chain %d.\n", i); 676 goto TX_IQ_CAL_FAILED; 677 } 678 679 for (j = 0; j < 3; j++) { 680 u_int8_t idx = 2 * j, 681 offset = 4 * j; 682 683 REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY, 684 AR_PHY_CHAN_INFO_TAB_S2_READ, 0); 685 686 /* 32 bits */ 687 iq_res[idx] = REG_READ(ah, chan_info_tab[i] + offset); 688 689 REG_RMW_FIELD(ah, AR_PHY_CHAN_INFO_MEMORY, 690 AR_PHY_CHAN_INFO_TAB_S2_READ, 1); 691 692 /* 16 bits */ 693 iq_res[idx+1] = 0xffff & REG_READ(ah, 694 chan_info_tab[i] + 695 offset); 696 697 ath_print(common, ATH_DBG_CALIBRATE, 698 "IQ RES[%d]=0x%x IQ_RES[%d]=0x%x\n", 699 idx, iq_res[idx], idx+1, iq_res[idx+1]); 700 } 701 702 if (!ar9003_hw_calc_iq_corr(ah, i, iq_res, iqc_coeff)) { 703 ath_print(common, ATH_DBG_CALIBRATE, 704 "Failed in calculation of IQ correction.\n"); 705 goto TX_IQ_CAL_FAILED; 706 } 707 708 ath_print(common, ATH_DBG_CALIBRATE, 709 "IQ_COEFF[0] = 0x%x IQ_COEFF[1] = 0x%x\n", 710 iqc_coeff[0], iqc_coeff[1]); 711 712 REG_RMW_FIELD(ah, tx_corr_coeff[i], 713 AR_PHY_TX_IQCAL_CORR_COEFF_01_COEFF_TABLE, 714 iqc_coeff[0]); 715 REG_RMW_FIELD(ah, rx_corr[i], 716 AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_Q_COFF, 717 iqc_coeff[1] >> 7); 718 REG_RMW_FIELD(ah, rx_corr[i], 719 AR_PHY_RX_IQCAL_CORR_LOOPBACK_IQCORR_Q_I_COFF, 720 iqc_coeff[1]); 721 } 722 723 REG_RMW_FIELD(ah, AR_PHY_TX_IQCAL_CONTROL_3, 724 AR_PHY_TX_IQCAL_CONTROL_3_IQCORR_EN, 0x1); 725 REG_RMW_FIELD(ah, AR_PHY_RX_IQCAL_CORR_B0, 726 AR_PHY_RX_IQCAL_CORR_B0_LOOPBACK_IQCORR_EN, 0x1); 727 728 return; 729 730TX_IQ_CAL_FAILED: 731 ath_print(common, ATH_DBG_CALIBRATE, "Tx IQ Cal failed\n"); 732} 733 734static bool ar9003_hw_init_cal(struct ath_hw *ah, 735 struct ath9k_channel *chan) 736{ 737 struct ath_common *common = ath9k_hw_common(ah); 738 739 /* 740 * 0x7 = 0b111 , AR9003 needs to be configured for 3-chain mode before 741 * running AGC/TxIQ cals 742 */ 743 ar9003_hw_set_chain_masks(ah, 0x7, 0x7); 744 745 /* Do Tx IQ Calibration */ 746 ar9003_hw_tx_iq_cal(ah); 747 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_DIS); 748 udelay(5); 749 REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ACTIVE_EN); 750 751 /* Calibrate the AGC */ 752 REG_WRITE(ah, AR_PHY_AGC_CONTROL, 753 REG_READ(ah, AR_PHY_AGC_CONTROL) | 754 AR_PHY_AGC_CONTROL_CAL); 755 756 /* Poll for offset calibration complete */ 757 if (!ath9k_hw_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 758 0, AH_WAIT_TIMEOUT)) { 759 ath_print(common, ATH_DBG_CALIBRATE, 760 "offset calibration failed to " 761 "complete in 1ms; noisy environment?\n"); 762 return false; 763 } 764 765 /* Revert chainmasks to their original values before NF cal */ 766 ar9003_hw_set_chain_masks(ah, ah->rxchainmask, ah->txchainmask); 767 768 ath9k_hw_start_nfcal(ah, true); 769 770 /* Initialize list pointers */ 771 ah->cal_list = ah->cal_list_last = ah->cal_list_curr = NULL; 772 773 if (ar9003_hw_iscal_supported(ah, IQ_MISMATCH_CAL)) { 774 INIT_CAL(&ah->iq_caldata); 775 INSERT_CAL(ah, &ah->iq_caldata); 776 ath_print(common, ATH_DBG_CALIBRATE, 777 "enabling IQ Calibration.\n"); 778 } 779 780 if (ar9003_hw_iscal_supported(ah, TEMP_COMP_CAL)) { 781 INIT_CAL(&ah->tempCompCalData); 782 INSERT_CAL(ah, &ah->tempCompCalData); 783 ath_print(common, ATH_DBG_CALIBRATE, 784 "enabling Temperature Compensation Calibration.\n"); 785 } 786 787 /* Initialize current pointer to first element in list */ 788 ah->cal_list_curr = ah->cal_list; 789 790 if (ah->cal_list_curr) 791 ath9k_hw_reset_calibration(ah, ah->cal_list_curr); 792 793 if (ah->caldata) 794 ah->caldata->CalValid = 0; 795 796 return true; 797} 798 799void ar9003_hw_attach_calib_ops(struct ath_hw *ah) 800{ 801 struct ath_hw_private_ops *priv_ops = ath9k_hw_private_ops(ah); 802 struct ath_hw_ops *ops = ath9k_hw_ops(ah); 803 804 priv_ops->init_cal_settings = ar9003_hw_init_cal_settings; 805 priv_ops->init_cal = ar9003_hw_init_cal; 806 priv_ops->setup_calibration = ar9003_hw_setup_calibration; 807 priv_ops->iscal_supported = ar9003_hw_iscal_supported; 808 809 ops->calibrate = ar9003_hw_calibrate; 810} 811