1/**************************************************************************** 2 * Driver for Solarflare Solarstorm network controllers and boards 3 * Copyright 2009 Solarflare Communications Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 as published 7 * by the Free Software Foundation, incorporated herein by reference. 8 */ 9 10 11#ifndef MCDI_PCOL_H 12#define MCDI_PCOL_H 13 14/* Values to be written into FMCR_CZ_RESET_STATE_REG to control boot. */ 15/* Power-on reset state */ 16#define MC_FW_STATE_POR (1) 17/* If this is set in MC_RESET_STATE_REG then it should be 18 * possible to jump into IMEM without loading code from flash. */ 19#define MC_FW_WARM_BOOT_OK (2) 20/* The MC main image has started to boot. */ 21#define MC_FW_STATE_BOOTING (4) 22/* The Scheduler has started. */ 23#define MC_FW_STATE_SCHED (8) 24 25/* Values to be written to the per-port status dword in shared 26 * memory on reboot and assert */ 27#define MC_STATUS_DWORD_REBOOT (0xb007b007) 28#define MC_STATUS_DWORD_ASSERT (0xdeaddead) 29 30/* The current version of the MCDI protocol. 31 * 32 * Note that the ROM burnt into the card only talks V0, so at the very 33 * least every driver must support version 0 and MCDI_PCOL_VERSION 34 */ 35#define MCDI_PCOL_VERSION 1 36 37/** 38 * MCDI version 1 39 * 40 * Each MCDI request starts with an MCDI_HEADER, which is a 32byte 41 * structure, filled in by the client. 42 * 43 * 0 7 8 16 20 22 23 24 31 44 * | CODE | R | LEN | SEQ | Rsvd | E | R | XFLAGS | 45 * | | | 46 * | | \--- Response 47 * | \------- Error 48 * \------------------------------ Resync (always set) 49 * 50 * The client writes it's request into MC shared memory, and rings the 51 * doorbell. Each request is completed by either by the MC writting 52 * back into shared memory, or by writting out an event. 53 * 54 * All MCDI commands support completion by shared memory response. Each 55 * request may also contain additional data (accounted for by HEADER.LEN), 56 * and some response's may also contain additional data (again, accounted 57 * for by HEADER.LEN). 58 * 59 * Some MCDI commands support completion by event, in which any associated 60 * response data is included in the event. 61 * 62 * The protocol requires one response to be delivered for every request, a 63 * request should not be sent unless the response for the previous request 64 * has been received (either by polling shared memory, or by receiving 65 * an event). 66 */ 67 68/** Request/Response structure */ 69#define MCDI_HEADER_OFST 0 70#define MCDI_HEADER_CODE_LBN 0 71#define MCDI_HEADER_CODE_WIDTH 7 72#define MCDI_HEADER_RESYNC_LBN 7 73#define MCDI_HEADER_RESYNC_WIDTH 1 74#define MCDI_HEADER_DATALEN_LBN 8 75#define MCDI_HEADER_DATALEN_WIDTH 8 76#define MCDI_HEADER_SEQ_LBN 16 77#define MCDI_HEADER_RSVD_LBN 20 78#define MCDI_HEADER_RSVD_WIDTH 2 79#define MCDI_HEADER_SEQ_WIDTH 4 80#define MCDI_HEADER_ERROR_LBN 22 81#define MCDI_HEADER_ERROR_WIDTH 1 82#define MCDI_HEADER_RESPONSE_LBN 23 83#define MCDI_HEADER_RESPONSE_WIDTH 1 84#define MCDI_HEADER_XFLAGS_LBN 24 85#define MCDI_HEADER_XFLAGS_WIDTH 8 86/* Request response using event */ 87#define MCDI_HEADER_XFLAGS_EVREQ 0x01 88 89/* Maximum number of payload bytes */ 90#define MCDI_CTL_SDU_LEN_MAX 0xfc 91 92/* The MC can generate events for two reasons: 93 * - To complete a shared memory request if XFLAGS_EVREQ was set 94 * - As a notification (link state, i2c event), controlled 95 * via MC_CMD_LOG_CTRL 96 * 97 * Both events share a common structure: 98 * 99 * 0 32 33 36 44 52 60 100 * | Data | Cont | Level | Src | Code | Rsvd | 101 * | 102 * \ There is another event pending in this notification 103 * 104 * If Code==CMDDONE, then the fields are further interpreted as: 105 * 106 * - LEVEL==INFO Command succeded 107 * - LEVEL==ERR Command failed 108 * 109 * 0 8 16 24 32 110 * | Seq | Datalen | Errno | Rsvd | 111 * 112 * These fields are taken directly out of the standard MCDI header, i.e., 113 * LEVEL==ERR, Datalen == 0 => Reboot 114 * 115 * Events can be squirted out of the UART (using LOG_CTRL) without a 116 * MCDI header. An event can be distinguished from a MCDI response by 117 * examining the first byte which is 0xc0. This corresponds to the 118 * non-existent MCDI command MC_CMD_DEBUG_LOG. 119 * 120 * 0 7 8 121 * | command | Resync | = 0xc0 122 * 123 * Since the event is written in big-endian byte order, this works 124 * providing bits 56-63 of the event are 0xc0. 125 * 126 * 56 60 63 127 * | Rsvd | Code | = 0xc0 128 * 129 * Which means for convenience the event code is 0xc for all MC 130 * generated events. 131 */ 132#define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc 133 134#define MCDI_EVENT_DATA_LBN 0 135#define MCDI_EVENT_DATA_WIDTH 32 136#define MCDI_EVENT_CONT_LBN 32 137#define MCDI_EVENT_CONT_WIDTH 1 138#define MCDI_EVENT_LEVEL_LBN 33 139#define MCDI_EVENT_LEVEL_WIDTH 3 140#define MCDI_EVENT_LEVEL_INFO (0) 141#define MCDI_EVENT_LEVEL_WARN (1) 142#define MCDI_EVENT_LEVEL_ERR (2) 143#define MCDI_EVENT_LEVEL_FATAL (3) 144#define MCDI_EVENT_SRC_LBN 36 145#define MCDI_EVENT_SRC_WIDTH 8 146#define MCDI_EVENT_CODE_LBN 44 147#define MCDI_EVENT_CODE_WIDTH 8 148#define MCDI_EVENT_CODE_BADSSERT (1) 149#define MCDI_EVENT_CODE_PMNOTICE (2) 150#define MCDI_EVENT_CODE_CMDDONE (3) 151#define MCDI_EVENT_CMDDONE_SEQ_LBN 0 152#define MCDI_EVENT_CMDDONE_SEQ_WIDTH 8 153#define MCDI_EVENT_CMDDONE_DATALEN_LBN 8 154#define MCDI_EVENT_CMDDONE_DATALEN_WIDTH 8 155#define MCDI_EVENT_CMDDONE_ERRNO_LBN 16 156#define MCDI_EVENT_CMDDONE_ERRNO_WIDTH 8 157#define MCDI_EVENT_CODE_LINKCHANGE (4) 158#define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0 159#define MCDI_EVENT_LINKCHANGE_LP_CAP_WIDTH 16 160#define MCDI_EVENT_LINKCHANGE_SPEED_LBN 16 161#define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4 162#define MCDI_EVENT_LINKCHANGE_SPEED_100M 1 163#define MCDI_EVENT_LINKCHANGE_SPEED_1G 2 164#define MCDI_EVENT_LINKCHANGE_SPEED_10G 3 165#define MCDI_EVENT_LINKCHANGE_FCNTL_LBN 20 166#define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4 167#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_LBN 24 168#define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_WIDTH 8 169#define MCDI_EVENT_CODE_SENSOREVT (5) 170#define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0 171#define MCDI_EVENT_SENSOREVT_MONITOR_WIDTH 8 172#define MCDI_EVENT_SENSOREVT_STATE_LBN 8 173#define MCDI_EVENT_SENSOREVT_STATE_WIDTH 8 174#define MCDI_EVENT_SENSOREVT_VALUE_LBN 16 175#define MCDI_EVENT_SENSOREVT_VALUE_WIDTH 16 176#define MCDI_EVENT_CODE_SCHEDERR (6) 177#define MCDI_EVENT_CODE_REBOOT (7) 178#define MCDI_EVENT_CODE_MAC_STATS_DMA (8) 179#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0 180#define MCDI_EVENT_MAC_STATS_DMA_GENERATION_WIDTH 32 181 182/* Non-existent command target */ 183#define MC_CMD_ERR_ENOENT 2 184/* assert() has killed the MC */ 185#define MC_CMD_ERR_EINTR 4 186/* Caller does not hold required locks */ 187#define MC_CMD_ERR_EACCES 13 188/* Resource is currently unavailable (e.g. lock contention) */ 189#define MC_CMD_ERR_EBUSY 16 190/* Invalid argument to target */ 191#define MC_CMD_ERR_EINVAL 22 192/* Non-recursive resource is already acquired */ 193#define MC_CMD_ERR_EDEADLK 35 194/* Operation not implemented */ 195#define MC_CMD_ERR_ENOSYS 38 196/* Operation timed out */ 197#define MC_CMD_ERR_ETIME 62 198 199#define MC_CMD_ERR_CODE_OFST 0 200 201 202/* MC_CMD_READ32: (debug, variadic out) 203 * Read multiple 32byte words from MC memory 204 */ 205#define MC_CMD_READ32 0x01 206#define MC_CMD_READ32_IN_LEN 8 207#define MC_CMD_READ32_IN_ADDR_OFST 0 208#define MC_CMD_READ32_IN_NUMWORDS_OFST 4 209#define MC_CMD_READ32_OUT_LEN(_numwords) \ 210 (4 * (_numwords)) 211#define MC_CMD_READ32_OUT_BUFFER_OFST 0 212 213/* MC_CMD_WRITE32: (debug, variadic in) 214 * Write multiple 32byte words to MC memory 215 */ 216#define MC_CMD_WRITE32 0x02 217#define MC_CMD_WRITE32_IN_LEN(_numwords) (((_numwords) * 4) + 4) 218#define MC_CMD_WRITE32_IN_ADDR_OFST 0 219#define MC_CMD_WRITE32_IN_BUFFER_OFST 4 220#define MC_CMD_WRITE32_OUT_LEN 0 221 222/* MC_CMD_COPYCODE: (debug) 223 * Copy MC code between two locations and jump 224 */ 225#define MC_CMD_COPYCODE 0x03 226#define MC_CMD_COPYCODE_IN_LEN 16 227#define MC_CMD_COPYCODE_IN_SRC_ADDR_OFST 0 228#define MC_CMD_COPYCODE_IN_DEST_ADDR_OFST 4 229#define MC_CMD_COPYCODE_IN_NUMWORDS_OFST 8 230#define MC_CMD_COPYCODE_IN_JUMP_OFST 12 231/* Control should return to the caller rather than jumping */ 232#define MC_CMD_COPYCODE_JUMP_NONE 1 233#define MC_CMD_COPYCODE_OUT_LEN 0 234 235/* MC_CMD_SET_FUNC: (debug) 236 * Select function for function-specific commands. 237 */ 238#define MC_CMD_SET_FUNC 0x04 239#define MC_CMD_SET_FUNC_IN_LEN 4 240#define MC_CMD_SET_FUNC_IN_FUNC_OFST 0 241#define MC_CMD_SET_FUNC_OUT_LEN 0 242 243/* MC_CMD_GET_BOOT_STATUS: 244 * Get the instruction address from which the MC booted. 245 */ 246#define MC_CMD_GET_BOOT_STATUS 0x05 247#define MC_CMD_GET_BOOT_STATUS_IN_LEN 0 248#define MC_CMD_GET_BOOT_STATUS_OUT_LEN 8 249#define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0 250#define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4 251/* Reboot caused by watchdog */ 252#define MC_CMD_GET_BOOT_STATUS_FLAGS_WATCHDOG_LBN (0) 253#define MC_CMD_GET_BOOT_STATUS_FLAGS_WATCHDOG_WIDTH (1) 254/* MC booted from primary flash partition */ 255#define MC_CMD_GET_BOOT_STATUS_FLAGS_PRIMARY_LBN (1) 256#define MC_CMD_GET_BOOT_STATUS_FLAGS_PRIMARY_WIDTH (1) 257/* MC booted from backup flash partition */ 258#define MC_CMD_GET_BOOT_STATUS_FLAGS_BACKUP_LBN (2) 259#define MC_CMD_GET_BOOT_STATUS_FLAGS_BACKUP_WIDTH (1) 260 261/* MC_CMD_GET_ASSERTS: (debug, variadic out) 262 * Get (and optionally clear) the current assertion status. 263 * 264 * Only OUT.GLOBAL_FLAGS is guaranteed to exist in the completion 265 * payload. The other fields will only be present if 266 * OUT.GLOBAL_FLAGS != NO_FAILS 267 */ 268#define MC_CMD_GET_ASSERTS 0x06 269#define MC_CMD_GET_ASSERTS_IN_LEN 4 270#define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0 271#define MC_CMD_GET_ASSERTS_OUT_LEN 140 272/* Assertion status flag */ 273#define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0 274/*! No assertions have failed. */ 275#define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 1 276/*! A system-level assertion has failed. */ 277#define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 2 278/*! A thread-level assertion has failed. */ 279#define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 3 280/*! The system was reset by the watchdog. */ 281#define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 4 282/* Failing PC value */ 283#define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4 284/* Saved GP regs */ 285#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_OFST 8 286#define MC_CMD_GET_ASSERTS_OUT_GP_REGS_LEN 124 287/* Failing thread address */ 288#define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_OFST 132 289 290/* MC_CMD_LOG_CTRL: 291 * Determine the output stream for various events and messages 292 */ 293#define MC_CMD_LOG_CTRL 0x07 294#define MC_CMD_LOG_CTRL_IN_LEN 8 295#define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0 296#define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART (1) 297#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ (2) 298#define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4 299#define MC_CMD_LOG_CTRL_OUT_LEN 0 300 301/* MC_CMD_GET_VERSION: 302 * Get version information about the MC firmware 303 */ 304#define MC_CMD_GET_VERSION 0x08 305#define MC_CMD_GET_VERSION_IN_LEN 0 306#define MC_CMD_GET_VERSION_V0_OUT_LEN 4 307#define MC_CMD_GET_VERSION_V1_OUT_LEN 32 308#define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 309/* Reserved version number to indicate "any" version. */ 310#define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff 311/* The version response of a boot ROM awaiting rescue */ 312#define MC_CMD_GET_VERSION_OUT_FIRMWARE_BOOTROM 0xb0070000 313#define MC_CMD_GET_VERSION_V1_OUT_PCOL_OFST 4 314/* 128bit mask of functions supported by the current firmware */ 315#define MC_CMD_GET_VERSION_V1_OUT_SUPPORTED_FUNCS_OFST 8 316/* The command set exported by the boot ROM (MCDI v0) */ 317#define MC_CMD_GET_VERSION_V0_SUPPORTED_FUNCS { \ 318 (1 << MC_CMD_READ32) | \ 319 (1 << MC_CMD_WRITE32) | \ 320 (1 << MC_CMD_COPYCODE) | \ 321 (1 << MC_CMD_GET_VERSION), \ 322 0, 0, 0 } 323#define MC_CMD_GET_VERSION_OUT_VERSION_OFST 24 324 325/* Vectors in the boot ROM */ 326/* Point to the copycode entry point. */ 327#define MC_BOOTROM_COPYCODE_VEC (0x7f4) 328/* Points to the recovery mode entry point. */ 329#define MC_BOOTROM_NOFLASH_VEC (0x7f8) 330 331/* Test execution limits */ 332#define MC_TESTEXEC_VARIANT_COUNT 16 333#define MC_TESTEXEC_RESULT_COUNT 7 334 335/* MC_CMD_SET_TESTVARS: (debug, variadic in) 336 * Write variant words for test. 337 * 338 * The user supplies a bitmap of the variants they wish to set. 339 * They must ensure that IN.LEN >= 4 + 4 * ffs(BITMAP) 340 */ 341#define MC_CMD_SET_TESTVARS 0x09 342#define MC_CMD_SET_TESTVARS_IN_LEN(_numwords) \ 343 (4 + 4*(_numwords)) 344#define MC_CMD_SET_TESTVARS_IN_ARGS_BITMAP_OFST 0 345/* Up to MC_TESTEXEC_VARIANT_COUNT of 32byte words start here */ 346#define MC_CMD_SET_TESTVARS_IN_ARGS_BUFFER_OFST 4 347#define MC_CMD_SET_TESTVARS_OUT_LEN 0 348 349/* MC_CMD_GET_TESTRCS: (debug, variadic out) 350 * Return result words from test. 351 */ 352#define MC_CMD_GET_TESTRCS 0x0a 353#define MC_CMD_GET_TESTRCS_IN_LEN 4 354#define MC_CMD_GET_TESTRCS_IN_NUMWORDS_OFST 0 355#define MC_CMD_GET_TESTRCS_OUT_LEN(_numwords) \ 356 (4 * (_numwords)) 357#define MC_CMD_GET_TESTRCS_OUT_BUFFER_OFST 0 358 359/* MC_CMD_RUN_TEST: (debug) 360 * Run the test exported by this firmware image 361 */ 362#define MC_CMD_RUN_TEST 0x0b 363#define MC_CMD_RUN_TEST_IN_LEN 0 364#define MC_CMD_RUN_TEST_OUT_LEN 0 365 366/* MC_CMD_CSR_READ32: (debug, variadic out) 367 * Read 32bit words from the indirect memory map 368 */ 369#define MC_CMD_CSR_READ32 0x0c 370#define MC_CMD_CSR_READ32_IN_LEN 12 371#define MC_CMD_CSR_READ32_IN_ADDR_OFST 0 372#define MC_CMD_CSR_READ32_IN_STEP_OFST 4 373#define MC_CMD_CSR_READ32_IN_NUMWORDS_OFST 8 374#define MC_CMD_CSR_READ32_OUT_LEN(_numwords) \ 375 (((_numwords) * 4) + 4) 376/* IN.NUMWORDS of 32bit words start here */ 377#define MC_CMD_CSR_READ32_OUT_BUFFER_OFST 0 378#define MC_CMD_CSR_READ32_OUT_IREG_STATUS_OFST(_numwords) \ 379 ((_numwords) * 4) 380 381/* MC_CMD_CSR_WRITE32: (debug, variadic in) 382 * Write 32bit dwords to the indirect memory map 383 */ 384#define MC_CMD_CSR_WRITE32 0x0d 385#define MC_CMD_CSR_WRITE32_IN_LEN(_numwords) \ 386 (((_numwords) * 4) + 8) 387#define MC_CMD_CSR_WRITE32_IN_ADDR_OFST 0 388#define MC_CMD_CSR_WRITE32_IN_STEP_OFST 4 389/* Multiple 32bit words of data to write start here */ 390#define MC_CMD_CSR_WRITE32_IN_BUFFER_OFST 8 391#define MC_CMD_CSR_WRITE32_OUT_LEN 4 392#define MC_CMD_CSR_WRITE32_OUT_STATUS_OFST 0 393 394/* MC_CMD_JTAG_WORK: (debug, fpga only) 395 * Process JTAG work buffer for RBF acceleration. 396 * 397 * Host: bit count, (up to) 32 words of data to clock out to JTAG 398 * (bits 1,0=TMS,TDO for first bit; bits 3,2=TMS,TDO for second bit, etc.) 399 * MC: bit count, (up to) 32 words of data clocked in from JTAG 400 * (bit 0=TDI for first bit, bit 1=TDI for second bit, etc.; [31:16] unused) 401 */ 402#define MC_CMD_JTAG_WORK 0x0e 403 404/* MC_CMD_STACKINFO: (debug, variadic out) 405 * Get stack information 406 * 407 * Host: nothing 408 * MC: (thread ptr, stack size, free space) for each thread in system 409 */ 410#define MC_CMD_STACKINFO 0x0f 411 412/* MC_CMD_MDIO_READ: 413 * MDIO register read 414 */ 415#define MC_CMD_MDIO_READ 0x10 416#define MC_CMD_MDIO_READ_IN_LEN 16 417#define MC_CMD_MDIO_READ_IN_BUS_OFST 0 418#define MC_CMD_MDIO_READ_IN_PRTAD_OFST 4 419#define MC_CMD_MDIO_READ_IN_DEVAD_OFST 8 420#define MC_CMD_MDIO_READ_IN_ADDR_OFST 12 421#define MC_CMD_MDIO_READ_OUT_LEN 8 422#define MC_CMD_MDIO_READ_OUT_VALUE_OFST 0 423#define MC_CMD_MDIO_READ_OUT_STATUS_OFST 4 424 425/* MC_CMD_MDIO_WRITE: 426 * MDIO register write 427 */ 428#define MC_CMD_MDIO_WRITE 0x11 429#define MC_CMD_MDIO_WRITE_IN_LEN 20 430#define MC_CMD_MDIO_WRITE_IN_BUS_OFST 0 431#define MC_CMD_MDIO_WRITE_IN_PRTAD_OFST 4 432#define MC_CMD_MDIO_WRITE_IN_DEVAD_OFST 8 433#define MC_CMD_MDIO_WRITE_IN_ADDR_OFST 12 434#define MC_CMD_MDIO_WRITE_IN_VALUE_OFST 16 435#define MC_CMD_MDIO_WRITE_OUT_LEN 4 436#define MC_CMD_MDIO_WRITE_OUT_STATUS_OFST 0 437 438/* By default all the MCDI MDIO operations perform clause45 mode. 439 * If you want to use clause22 then set DEVAD = MC_CMD_MDIO_CLAUSE22. 440 */ 441#define MC_CMD_MDIO_CLAUSE22 32 442 443/* There are two MDIO buses: one for the internal PHY, and one for external 444 * devices. 445 */ 446#define MC_CMD_MDIO_BUS_INTERNAL 0 447#define MC_CMD_MDIO_BUS_EXTERNAL 1 448 449/* The MDIO commands return the raw status bits from the MDIO block. A "good" 450 * transaction should have the DONE bit set and all other bits clear. 451 */ 452#define MC_CMD_MDIO_STATUS_GOOD 0x08 453 454 455/* MC_CMD_DBI_WRITE: (debug) 456 * Write DBI register(s) 457 * 458 * Host: address, byte-enables (and VF selection, and cs2 flag), 459 * value [,address ...] 460 * MC: nothing 461 */ 462#define MC_CMD_DBI_WRITE 0x12 463#define MC_CMD_DBI_WRITE_IN_LEN(_numwords) \ 464 (12 * (_numwords)) 465#define MC_CMD_DBI_WRITE_IN_ADDRESS_OFST(_word) \ 466 (((_word) * 12) + 0) 467#define MC_CMD_DBI_WRITE_IN_BYTE_MASK_OFST(_word) \ 468 (((_word) * 12) + 4) 469#define MC_CMD_DBI_WRITE_IN_VALUE_OFST(_word) \ 470 (((_word) * 12) + 8) 471#define MC_CMD_DBI_WRITE_OUT_LEN 0 472 473/* MC_CMD_DBI_READ: (debug) 474 * Read DBI register(s) 475 * 476 * Host: address, [,address ...] 477 * MC: value [,value ...] 478 * (note: this does not support reading from VFs, but is retained for backwards 479 * compatibility; see MC_CMD_DBI_READX below) 480 */ 481#define MC_CMD_DBI_READ 0x13 482#define MC_CMD_DBI_READ_IN_LEN(_numwords) \ 483 (4 * (_numwords)) 484#define MC_CMD_DBI_READ_OUT_LEN(_numwords) \ 485 (4 * (_numwords)) 486 487/* MC_CMD_PORT_READ32: (debug) 488 * Read a 32-bit register from the indirect port register map. 489 * 490 * The port to access is implied by the Shared memory channel used. 491 */ 492#define MC_CMD_PORT_READ32 0x14 493#define MC_CMD_PORT_READ32_IN_LEN 4 494#define MC_CMD_PORT_READ32_IN_ADDR_OFST 0 495#define MC_CMD_PORT_READ32_OUT_LEN 8 496#define MC_CMD_PORT_READ32_OUT_VALUE_OFST 0 497#define MC_CMD_PORT_READ32_OUT_STATUS_OFST 4 498 499/* MC_CMD_PORT_WRITE32: (debug) 500 * Write a 32-bit register to the indirect port register map. 501 * 502 * The port to access is implied by the Shared memory channel used. 503 */ 504#define MC_CMD_PORT_WRITE32 0x15 505#define MC_CMD_PORT_WRITE32_IN_LEN 8 506#define MC_CMD_PORT_WRITE32_IN_ADDR_OFST 0 507#define MC_CMD_PORT_WRITE32_IN_VALUE_OFST 4 508#define MC_CMD_PORT_WRITE32_OUT_LEN 4 509#define MC_CMD_PORT_WRITE32_OUT_STATUS_OFST 0 510 511/* MC_CMD_PORT_READ128: (debug) 512 * Read a 128-bit register from indirect port register map 513 * 514 * The port to access is implied by the Shared memory channel used. 515 */ 516#define MC_CMD_PORT_READ128 0x16 517#define MC_CMD_PORT_READ128_IN_LEN 4 518#define MC_CMD_PORT_READ128_IN_ADDR_OFST 0 519#define MC_CMD_PORT_READ128_OUT_LEN 20 520#define MC_CMD_PORT_READ128_OUT_VALUE_OFST 0 521#define MC_CMD_PORT_READ128_OUT_STATUS_OFST 16 522 523/* MC_CMD_PORT_WRITE128: (debug) 524 * Write a 128-bit register to indirect port register map. 525 * 526 * The port to access is implied by the Shared memory channel used. 527 */ 528#define MC_CMD_PORT_WRITE128 0x17 529#define MC_CMD_PORT_WRITE128_IN_LEN 20 530#define MC_CMD_PORT_WRITE128_IN_ADDR_OFST 0 531#define MC_CMD_PORT_WRITE128_IN_VALUE_OFST 4 532#define MC_CMD_PORT_WRITE128_OUT_LEN 4 533#define MC_CMD_PORT_WRITE128_OUT_STATUS_OFST 0 534 535#define MC_CMD_GET_BOARD_CFG 0x18 536#define MC_CMD_GET_BOARD_CFG_IN_LEN 0 537#define MC_CMD_GET_BOARD_CFG_OUT_LEN 96 538#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0 539#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4 540#define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_LEN 32 541#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_OFST 36 542#define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_OFST 40 543#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_OFST 44 544#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT0_LEN 6 545#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_OFST 50 546#define MC_CMD_GET_BOARD_CFG_OUT_MAC_ADDR_BASE_PORT1_LEN 6 547#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_OFST 56 548#define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_OFST 60 549#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_OFST 64 550#define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_OFST 68 551#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_OFST 72 552#define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_LEN 24 553 554/* MC_CMD_DBI_READX: (debug) 555 * Read DBI register(s) -- extended functionality 556 * 557 * Host: vf selection, address, [,vf selection ...] 558 * MC: value [,value ...] 559 */ 560#define MC_CMD_DBI_READX 0x19 561#define MC_CMD_DBI_READX_IN_LEN(_numwords) \ 562 (8*(_numwords)) 563#define MC_CMD_DBI_READX_OUT_LEN(_numwords) \ 564 (4*(_numwords)) 565 566/* MC_CMD_SET_RAND_SEED: 567 * Set the 16byte seed for the MC psuedo-random generator 568 */ 569#define MC_CMD_SET_RAND_SEED 0x1a 570#define MC_CMD_SET_RAND_SEED_IN_LEN 16 571#define MC_CMD_SET_RAND_SEED_IN_SEED_OFST 0 572#define MC_CMD_SET_RAND_SEED_OUT_LEN 0 573 574/* MC_CMD_LTSSM_HIST: (debug) 575 * Retrieve the history of the LTSSM, if the build supports it. 576 * 577 * Host: nothing 578 * MC: variable number of LTSSM values, as bytes 579 * The history is read-to-clear. 580 */ 581#define MC_CMD_LTSSM_HIST 0x1b 582 583/* MC_CMD_DRV_ATTACH: 584 * Inform MCPU that this port is managed on the host (i.e. driver active) 585 */ 586#define MC_CMD_DRV_ATTACH 0x1c 587#define MC_CMD_DRV_ATTACH_IN_LEN 8 588#define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0 589#define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4 590#define MC_CMD_DRV_ATTACH_OUT_LEN 4 591#define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0 592 593/* MC_CMD_NCSI_PROD: (debug) 594 * Trigger an NC-SI event (and possibly an AEN in response) 595 */ 596#define MC_CMD_NCSI_PROD 0x1d 597#define MC_CMD_NCSI_PROD_IN_LEN 4 598#define MC_CMD_NCSI_PROD_IN_EVENTS_OFST 0 599#define MC_CMD_NCSI_PROD_LINKCHANGE_LBN 0 600#define MC_CMD_NCSI_PROD_LINKCHANGE_WIDTH 1 601#define MC_CMD_NCSI_PROD_RESET_LBN 1 602#define MC_CMD_NCSI_PROD_RESET_WIDTH 1 603#define MC_CMD_NCSI_PROD_DRVATTACH_LBN 2 604#define MC_CMD_NCSI_PROD_DRVATTACH_WIDTH 1 605#define MC_CMD_NCSI_PROD_OUT_LEN 0 606 607/* Enumeration */ 608#define MC_CMD_NCSI_PROD_LINKCHANGE 0 609#define MC_CMD_NCSI_PROD_RESET 1 610#define MC_CMD_NCSI_PROD_DRVATTACH 2 611 612/* MC_CMD_DEVEL: (debug) 613 * Reserved for development 614 */ 615#define MC_CMD_DEVEL 0x1e 616 617/* MC_CMD_SHMUART: (debug) 618 * Route UART output to circular buffer in shared memory instead. 619 */ 620#define MC_CMD_SHMUART 0x1f 621#define MC_CMD_SHMUART_IN_FLAG_OFST 0 622#define MC_CMD_SHMUART_IN_LEN 4 623#define MC_CMD_SHMUART_OUT_LEN 0 624 625/* MC_CMD_PORT_RESET: 626 * Generic per-port reset. There is no equivalent for per-board reset. 627 * 628 * Locks required: None 629 * Return code: 0, ETIME 630 */ 631#define MC_CMD_PORT_RESET 0x20 632#define MC_CMD_PORT_RESET_IN_LEN 0 633#define MC_CMD_PORT_RESET_OUT_LEN 0 634 635/* MC_CMD_RESOURCE_LOCK: 636 * Generic resource lock/unlock interface. 637 * 638 * Locks required: None 639 * Return code: 0, 640 * EBUSY (if trylock is contended by other port), 641 * EDEADLK (if trylock is already acquired by this port) 642 * EINVAL (if unlock doesn't own the lock) 643 */ 644#define MC_CMD_RESOURCE_LOCK 0x21 645#define MC_CMD_RESOURCE_LOCK_IN_LEN 8 646#define MC_CMD_RESOURCE_LOCK_IN_ACTION_OFST 0 647#define MC_CMD_RESOURCE_LOCK_ACTION_TRYLOCK 1 648#define MC_CMD_RESOURCE_LOCK_ACTION_UNLOCK 0 649#define MC_CMD_RESOURCE_LOCK_IN_RESOURCE_OFST 4 650#define MC_CMD_RESOURCE_LOCK_I2C 2 651#define MC_CMD_RESOURCE_LOCK_PHY 3 652#define MC_CMD_RESOURCE_LOCK_OUT_LEN 0 653 654/* MC_CMD_SPI_COMMAND: (variadic in, variadic out) 655 * Read/Write to/from the SPI device. 656 * 657 * Locks required: SPI_LOCK 658 * Return code: 0, ETIME, EINVAL, EACCES (if SPI_LOCK is not held) 659 */ 660#define MC_CMD_SPI_COMMAND 0x22 661#define MC_CMD_SPI_COMMAND_IN_LEN(_write_bytes) (12 + (_write_bytes)) 662#define MC_CMD_SPI_COMMAND_IN_ARGS_OFST 0 663#define MC_CMD_SPI_COMMAND_IN_ARGS_ADDRESS_OFST 0 664#define MC_CMD_SPI_COMMAND_IN_ARGS_READ_BYTES_OFST 4 665#define MC_CMD_SPI_COMMAND_IN_ARGS_CHIP_SELECT_OFST 8 666/* Data to write here */ 667#define MC_CMD_SPI_COMMAND_IN_WRITE_BUFFER_OFST 12 668#define MC_CMD_SPI_COMMAND_OUT_LEN(_read_bytes) (_read_bytes) 669/* Data read here */ 670#define MC_CMD_SPI_COMMAND_OUT_READ_BUFFER_OFST 0 671 672/* MC_CMD_I2C_READ_WRITE: (variadic in, variadic out) 673 * Read/Write to/from the I2C bus. 674 * 675 * Locks required: I2C_LOCK 676 * Return code: 0, ETIME, EINVAL, EACCES (if I2C_LOCK is not held) 677 */ 678#define MC_CMD_I2C_RW 0x23 679#define MC_CMD_I2C_RW_IN_LEN(_write_bytes) (8 + (_write_bytes)) 680#define MC_CMD_I2C_RW_IN_ARGS_OFST 0 681#define MC_CMD_I2C_RW_IN_ARGS_ADDR_OFST 0 682#define MC_CMD_I2C_RW_IN_ARGS_READ_BYTES_OFST 4 683/* Data to write here */ 684#define MC_CMD_I2C_RW_IN_WRITE_BUFFER_OFSET 8 685#define MC_CMD_I2C_RW_OUT_LEN(_read_bytes) (_read_bytes) 686/* Data read here */ 687#define MC_CMD_I2C_RW_OUT_READ_BUFFER_OFST 0 688 689/* Generic phy capability bitmask */ 690#define MC_CMD_PHY_CAP_10HDX_LBN 1 691#define MC_CMD_PHY_CAP_10HDX_WIDTH 1 692#define MC_CMD_PHY_CAP_10FDX_LBN 2 693#define MC_CMD_PHY_CAP_10FDX_WIDTH 1 694#define MC_CMD_PHY_CAP_100HDX_LBN 3 695#define MC_CMD_PHY_CAP_100HDX_WIDTH 1 696#define MC_CMD_PHY_CAP_100FDX_LBN 4 697#define MC_CMD_PHY_CAP_100FDX_WIDTH 1 698#define MC_CMD_PHY_CAP_1000HDX_LBN 5 699#define MC_CMD_PHY_CAP_1000HDX_WIDTH 1 700#define MC_CMD_PHY_CAP_1000FDX_LBN 6 701#define MC_CMD_PHY_CAP_1000FDX_WIDTH 1 702#define MC_CMD_PHY_CAP_10000FDX_LBN 7 703#define MC_CMD_PHY_CAP_10000FDX_WIDTH 1 704#define MC_CMD_PHY_CAP_PAUSE_LBN 8 705#define MC_CMD_PHY_CAP_PAUSE_WIDTH 1 706#define MC_CMD_PHY_CAP_ASYM_LBN 9 707#define MC_CMD_PHY_CAP_ASYM_WIDTH 1 708#define MC_CMD_PHY_CAP_AN_LBN 10 709#define MC_CMD_PHY_CAP_AN_WIDTH 1 710 711/* Generic loopback enumeration */ 712#define MC_CMD_LOOPBACK_NONE 0 713#define MC_CMD_LOOPBACK_DATA 1 714#define MC_CMD_LOOPBACK_GMAC 2 715#define MC_CMD_LOOPBACK_XGMII 3 716#define MC_CMD_LOOPBACK_XGXS 4 717#define MC_CMD_LOOPBACK_XAUI 5 718#define MC_CMD_LOOPBACK_GMII 6 719#define MC_CMD_LOOPBACK_SGMII 7 720#define MC_CMD_LOOPBACK_XGBR 8 721#define MC_CMD_LOOPBACK_XFI 9 722#define MC_CMD_LOOPBACK_XAUI_FAR 10 723#define MC_CMD_LOOPBACK_GMII_FAR 11 724#define MC_CMD_LOOPBACK_SGMII_FAR 12 725#define MC_CMD_LOOPBACK_XFI_FAR 13 726#define MC_CMD_LOOPBACK_GPHY 14 727#define MC_CMD_LOOPBACK_PHYXS 15 728#define MC_CMD_LOOPBACK_PCS 16 729#define MC_CMD_LOOPBACK_PMAPMD 17 730#define MC_CMD_LOOPBACK_XPORT 18 731#define MC_CMD_LOOPBACK_XGMII_WS 19 732#define MC_CMD_LOOPBACK_XAUI_WS 20 733#define MC_CMD_LOOPBACK_XAUI_WS_FAR 21 734#define MC_CMD_LOOPBACK_XAUI_WS_NEAR 22 735#define MC_CMD_LOOPBACK_GMII_WS 23 736#define MC_CMD_LOOPBACK_XFI_WS 24 737#define MC_CMD_LOOPBACK_XFI_WS_FAR 25 738#define MC_CMD_LOOPBACK_PHYXS_WS 26 739 740/* Generic PHY statistics enumeration */ 741#define MC_CMD_OUI 0 742#define MC_CMD_PMA_PMD_LINK_UP 1 743#define MC_CMD_PMA_PMD_RX_FAULT 2 744#define MC_CMD_PMA_PMD_TX_FAULT 3 745#define MC_CMD_PMA_PMD_SIGNAL 4 746#define MC_CMD_PMA_PMD_SNR_A 5 747#define MC_CMD_PMA_PMD_SNR_B 6 748#define MC_CMD_PMA_PMD_SNR_C 7 749#define MC_CMD_PMA_PMD_SNR_D 8 750#define MC_CMD_PCS_LINK_UP 9 751#define MC_CMD_PCS_RX_FAULT 10 752#define MC_CMD_PCS_TX_FAULT 11 753#define MC_CMD_PCS_BER 12 754#define MC_CMD_PCS_BLOCK_ERRORS 13 755#define MC_CMD_PHYXS_LINK_UP 14 756#define MC_CMD_PHYXS_RX_FAULT 15 757#define MC_CMD_PHYXS_TX_FAULT 16 758#define MC_CMD_PHYXS_ALIGN 17 759#define MC_CMD_PHYXS_SYNC 18 760#define MC_CMD_AN_LINK_UP 19 761#define MC_CMD_AN_COMPLETE 20 762#define MC_CMD_AN_10GBT_STATUS 21 763#define MC_CMD_CL22_LINK_UP 22 764#define MC_CMD_PHY_NSTATS 23 765 766/* MC_CMD_GET_PHY_CFG: 767 * Report PHY configuration. This guarantees to succeed even if the PHY is in 768 * a "zombie" state. 769 * 770 * Locks required: None 771 * Return code: 0 772 */ 773#define MC_CMD_GET_PHY_CFG 0x24 774 775#define MC_CMD_GET_PHY_CFG_IN_LEN 0 776#define MC_CMD_GET_PHY_CFG_OUT_LEN 72 777 778#define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0 779#define MC_CMD_GET_PHY_CFG_PRESENT_LBN 0 780#define MC_CMD_GET_PHY_CFG_PRESENT_WIDTH 1 781#define MC_CMD_GET_PHY_CFG_BIST_CABLE_SHORT_LBN 1 782#define MC_CMD_GET_PHY_CFG_BIST_CABLE_SHORT_WIDTH 1 783#define MC_CMD_GET_PHY_CFG_BIST_CABLE_LONG_LBN 2 784#define MC_CMD_GET_PHY_CFG_BIST_CABLE_LONG_WIDTH 1 785#define MC_CMD_GET_PHY_CFG_LOWPOWER_LBN 3 786#define MC_CMD_GET_PHY_CFG_LOWPOWER_WIDTH 1 787#define MC_CMD_GET_PHY_CFG_POWEROFF_LBN 4 788#define MC_CMD_GET_PHY_CFG_POWEROFF_WIDTH 1 789#define MC_CMD_GET_PHY_CFG_TXDIS_LBN 5 790#define MC_CMD_GET_PHY_CFG_TXDIS_WIDTH 1 791#define MC_CMD_GET_PHY_CFG_BIST_LBN 6 792#define MC_CMD_GET_PHY_CFG_BIST_WIDTH 1 793#define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4 794/* Bitmask of supported capabilities */ 795#define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_OFST 8 796#define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_OFST 12 797#define MC_CMD_GET_PHY_CFG_OUT_PRT_OFST 16 798/* PHY statistics bitmap */ 799#define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_OFST 20 800/* PHY type/name string */ 801#define MC_CMD_GET_PHY_CFG_OUT_NAME_OFST 24 802#define MC_CMD_GET_PHY_CFG_OUT_NAME_LEN 20 803#define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_OFST 44 804#define MC_CMD_MEDIA_XAUI 1 805#define MC_CMD_MEDIA_CX4 2 806#define MC_CMD_MEDIA_KX4 3 807#define MC_CMD_MEDIA_XFP 4 808#define MC_CMD_MEDIA_SFP_PLUS 5 809#define MC_CMD_MEDIA_BASE_T 6 810/* MDIO "MMDS" supported */ 811#define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_OFST 48 812/* Native clause 22 */ 813#define MC_CMD_MMD_CLAUSE22 0 814#define MC_CMD_MMD_CLAUSE45_PMAPMD 1 815#define MC_CMD_MMD_CLAUSE45_WIS 2 816#define MC_CMD_MMD_CLAUSE45_PCS 3 817#define MC_CMD_MMD_CLAUSE45_PHYXS 4 818#define MC_CMD_MMD_CLAUSE45_DTEXS 5 819#define MC_CMD_MMD_CLAUSE45_TC 6 820#define MC_CMD_MMD_CLAUSE45_AN 7 821/* Clause22 proxied over clause45 by PHY */ 822#define MC_CMD_MMD_CLAUSE45_C22EXT 29 823#define MC_CMD_MMD_CLAUSE45_VEND1 30 824#define MC_CMD_MMD_CLAUSE45_VEND2 31 825/* PHY stepping version */ 826#define MC_CMD_GET_PHY_CFG_OUT_REVISION_OFST 52 827#define MC_CMD_GET_PHY_CFG_OUT_REVISION_LEN 20 828 829/* MC_CMD_START_BIST: 830 * Start a BIST test on the PHY. 831 * 832 * Locks required: PHY_LOCK if doing a PHY BIST 833 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held) 834 */ 835#define MC_CMD_START_BIST 0x25 836#define MC_CMD_START_BIST_IN_LEN 4 837#define MC_CMD_START_BIST_IN_TYPE_OFST 0 838#define MC_CMD_START_BIST_OUT_LEN 0 839 840/* Run the PHY's short cable BIST */ 841#define MC_CMD_PHY_BIST_CABLE_SHORT 1 842/* Run the PHY's long cable BIST */ 843#define MC_CMD_PHY_BIST_CABLE_LONG 2 844/* Run BIST on the currently selected BPX Serdes (XAUI or XFI) */ 845#define MC_CMD_BPX_SERDES_BIST 3 846/* Run the MC loopback tests */ 847#define MC_CMD_MC_LOOPBACK_BIST 4 848/* Run the PHY's standard BIST */ 849#define MC_CMD_PHY_BIST 5 850 851/* MC_CMD_POLL_PHY_BIST: (variadic output) 852 * Poll for BIST completion 853 * 854 * Returns a single status code, and optionally some PHY specific 855 * bist output. The driver should only consume the BIST output 856 * after validating OUTLEN and PHY_CFG.PHY_TYPE. 857 * 858 * If a driver can't successfully parse the BIST output, it should 859 * still respect the pass/Fail in OUT.RESULT 860 * 861 * Locks required: PHY_LOCK if doing a PHY BIST 862 * Return code: 0, EACCES (if PHY_LOCK is not held) 863 */ 864#define MC_CMD_POLL_BIST 0x26 865#define MC_CMD_POLL_BIST_IN_LEN 0 866#define MC_CMD_POLL_BIST_OUT_LEN UNKNOWN 867#define MC_CMD_POLL_BIST_OUT_SFT9001_LEN 36 868#define MC_CMD_POLL_BIST_OUT_MRSFP_LEN 8 869#define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 870#define MC_CMD_POLL_BIST_RUNNING 1 871#define MC_CMD_POLL_BIST_PASSED 2 872#define MC_CMD_POLL_BIST_FAILED 3 873#define MC_CMD_POLL_BIST_TIMEOUT 4 874/* Generic: */ 875#define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4 876/* SFT9001-specific: */ 877#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4 878#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_OFST 8 879#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_OFST 12 880#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_OFST 16 881#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_OFST 20 882#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_OFST 24 883#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_OFST 28 884#define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_OFST 32 885#define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 1 886#define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 2 887#define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 3 888#define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 4 889#define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 9 890/* mrsfp "PHY" driver: */ 891#define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4 892#define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0 893#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 1 894#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 2 895#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 3 896#define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 4 897#define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 5 898#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 6 899#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 7 900#define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 8 901 902/* MC_CMD_PHY_SPI: (variadic in, variadic out) 903 * Read/Write/Erase the PHY SPI device 904 * 905 * Locks required: PHY_LOCK 906 * Return code: 0, ETIME, EINVAL, EACCES (if PHY_LOCK is not held) 907 */ 908#define MC_CMD_PHY_SPI 0x27 909#define MC_CMD_PHY_SPI_IN_LEN(_write_bytes) (12 + (_write_bytes)) 910#define MC_CMD_PHY_SPI_IN_ARGS_OFST 0 911#define MC_CMD_PHY_SPI_IN_ARGS_ADDR_OFST 0 912#define MC_CMD_PHY_SPI_IN_ARGS_READ_BYTES_OFST 4 913#define MC_CMD_PHY_SPI_IN_ARGS_ERASE_ALL_OFST 8 914/* Data to write here */ 915#define MC_CMD_PHY_SPI_IN_WRITE_BUFFER_OFSET 12 916#define MC_CMD_PHY_SPI_OUT_LEN(_read_bytes) (_read_bytes) 917/* Data read here */ 918#define MC_CMD_PHY_SPI_OUT_READ_BUFFER_OFST 0 919 920 921/* MC_CMD_GET_LOOPBACK_MODES: 922 * Returns a bitmask of loopback modes evailable at each speed. 923 * 924 * Locks required: None 925 * Return code: 0 926 */ 927#define MC_CMD_GET_LOOPBACK_MODES 0x28 928#define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0 929#define MC_CMD_GET_LOOPBACK_MODES_OUT_LEN 32 930#define MC_CMD_GET_LOOPBACK_MODES_100M_OFST 0 931#define MC_CMD_GET_LOOPBACK_MODES_1G_OFST 8 932#define MC_CMD_GET_LOOPBACK_MODES_10G_OFST 16 933#define MC_CMD_GET_LOOPBACK_MODES_SUGGESTED_OFST 24 934 935/* Flow control enumeration */ 936#define MC_CMD_FCNTL_OFF 0 937#define MC_CMD_FCNTL_RESPOND 1 938#define MC_CMD_FCNTL_BIDIR 2 939/* Auto - Use what the link has autonegotiated 940 * - The driver should modify the advertised capabilities via SET_LINK.CAP 941 * to control the negotiated flow control mode. 942 * - Can only be set if the PHY supports PAUSE+ASYM capabilities 943 * - Never returned by GET_LINK as the value programmed into the MAC 944 */ 945#define MC_CMD_FCNTL_AUTO 3 946 947/* Generic mac fault bitmask */ 948#define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 949#define MC_CMD_MAC_FAULT_XGMII_LOCAL_WIDTH 1 950#define MC_CMD_MAC_FAULT_XGMII_REMOTE_LBN 1 951#define MC_CMD_MAC_FAULT_XGMII_REMOTE_WIDTH 1 952#define MC_CMD_MAC_FAULT_SGMII_REMOTE_LBN 2 953#define MC_CMD_MAC_FAULT_SGMII_REMOTE_WIDTH 1 954 955/* MC_CMD_GET_LINK: 956 * Read the unified MAC/PHY link state 957 * 958 * Locks required: None 959 * Return code: 0, ETIME 960 */ 961#define MC_CMD_GET_LINK 0x29 962#define MC_CMD_GET_LINK_IN_LEN 0 963#define MC_CMD_GET_LINK_OUT_LEN 28 964/* near-side and link-partner advertised capabilities */ 965#define MC_CMD_GET_LINK_OUT_CAP_OFST 0 966#define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4 967/* Autonegotiated speed in mbit/s. The link may still be down 968 * even if this reads non-zero */ 969#define MC_CMD_GET_LINK_OUT_LINK_SPEED_OFST 8 970#define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_OFST 12 971#define MC_CMD_GET_LINK_OUT_FLAGS_OFST 16 972/* Whether we have overall link up */ 973#define MC_CMD_GET_LINK_LINK_UP_LBN 0 974#define MC_CMD_GET_LINK_LINK_UP_WIDTH 1 975#define MC_CMD_GET_LINK_FULL_DUPLEX_LBN 1 976#define MC_CMD_GET_LINK_FULL_DUPLEX_WIDTH 1 977/* Whether we have link at the layers provided by the BPX */ 978#define MC_CMD_GET_LINK_BPX_LINK_LBN 2 979#define MC_CMD_GET_LINK_BPX_LINK_WIDTH 1 980/* Whether the PHY has external link */ 981#define MC_CMD_GET_LINK_PHY_LINK_LBN 3 982#define MC_CMD_GET_LINK_PHY_LINK_WIDTH 1 983#define MC_CMD_GET_LINK_OUT_FCNTL_OFST 20 984#define MC_CMD_GET_LINK_OUT_MAC_FAULT_OFST 24 985 986/* MC_CMD_SET_LINK: 987 * Write the unified MAC/PHY link configuration 988 * 989 * A loopback speed of "0" is supported, and means 990 * (choose any available speed) 991 * 992 * Locks required: None 993 * Return code: 0, EINVAL, ETIME 994 */ 995#define MC_CMD_SET_LINK 0x2a 996#define MC_CMD_SET_LINK_IN_LEN 16 997#define MC_CMD_SET_LINK_IN_CAP_OFST 0 998#define MC_CMD_SET_LINK_IN_FLAGS_OFST 4 999#define MC_CMD_SET_LINK_LOWPOWER_LBN 0 1000#define MC_CMD_SET_LINK_LOWPOWER_WIDTH 1 1001#define MC_CMD_SET_LINK_POWEROFF_LBN 1 1002#define MC_CMD_SET_LINK_POWEROFF_WIDTH 1 1003#define MC_CMD_SET_LINK_TXDIS_LBN 2 1004#define MC_CMD_SET_LINK_TXDIS_WIDTH 1 1005#define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_OFST 8 1006#define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_OFST 12 1007#define MC_CMD_SET_LINK_OUT_LEN 0 1008 1009/* MC_CMD_SET_ID_LED: 1010 * Set indentification LED state 1011 * 1012 * Locks required: None 1013 * Return code: 0, EINVAL 1014 */ 1015#define MC_CMD_SET_ID_LED 0x2b 1016#define MC_CMD_SET_ID_LED_IN_LEN 4 1017#define MC_CMD_SET_ID_LED_IN_STATE_OFST 0 1018#define MC_CMD_LED_OFF 0 1019#define MC_CMD_LED_ON 1 1020#define MC_CMD_LED_DEFAULT 2 1021#define MC_CMD_SET_ID_LED_OUT_LEN 0 1022 1023/* MC_CMD_SET_MAC: 1024 * Set MAC configuration 1025 * 1026 * The MTU is the MTU programmed directly into the XMAC/GMAC 1027 * (inclusive of EtherII, VLAN, bug16011 padding) 1028 * 1029 * Locks required: None 1030 * Return code: 0, EINVAL 1031 */ 1032#define MC_CMD_SET_MAC 0x2c 1033#define MC_CMD_SET_MAC_IN_LEN 24 1034#define MC_CMD_SET_MAC_IN_MTU_OFST 0 1035#define MC_CMD_SET_MAC_IN_DRAIN_OFST 4 1036#define MC_CMD_SET_MAC_IN_ADDR_OFST 8 1037#define MC_CMD_SET_MAC_IN_REJECT_OFST 16 1038#define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0 1039#define MC_CMD_SET_MAC_IN_REJECT_UNCST_WIDTH 1 1040#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_LBN 1 1041#define MC_CMD_SET_MAC_IN_REJECT_BRDCST_WIDTH 1 1042#define MC_CMD_SET_MAC_IN_FCNTL_OFST 20 1043#define MC_CMD_SET_MAC_OUT_LEN 0 1044 1045/* MC_CMD_PHY_STATS: 1046 * Get generic PHY statistics 1047 * 1048 * This call returns the statistics for a generic PHY in a sparse 1049 * array (indexed by the enumerate). Each value is represented by 1050 * a 32bit number. 1051 * 1052 * If the DMA_ADDR is 0, then no DMA is performed, and the statistics 1053 * may be read directly out of shared memory. If DMA_ADDR != 0, then 1054 * the statistics are dmad to that (page-aligned location) 1055 * 1056 * Locks required: None 1057 * Returns: 0, ETIME 1058 * Response methods: shared memory, event 1059 */ 1060#define MC_CMD_PHY_STATS 0x2d 1061#define MC_CMD_PHY_STATS_IN_LEN 8 1062#define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0 1063#define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4 1064#define MC_CMD_PHY_STATS_OUT_DMA_LEN 0 1065#define MC_CMD_PHY_STATS_OUT_NO_DMA_LEN (MC_CMD_PHY_NSTATS * 4) 1066 1067/* Unified MAC statistics enumeration */ 1068#define MC_CMD_MAC_GENERATION_START 0 1069#define MC_CMD_MAC_TX_PKTS 1 1070#define MC_CMD_MAC_TX_PAUSE_PKTS 2 1071#define MC_CMD_MAC_TX_CONTROL_PKTS 3 1072#define MC_CMD_MAC_TX_UNICAST_PKTS 4 1073#define MC_CMD_MAC_TX_MULTICAST_PKTS 5 1074#define MC_CMD_MAC_TX_BROADCAST_PKTS 6 1075#define MC_CMD_MAC_TX_BYTES 7 1076#define MC_CMD_MAC_TX_BAD_BYTES 8 1077#define MC_CMD_MAC_TX_LT64_PKTS 9 1078#define MC_CMD_MAC_TX_64_PKTS 10 1079#define MC_CMD_MAC_TX_65_TO_127_PKTS 11 1080#define MC_CMD_MAC_TX_128_TO_255_PKTS 12 1081#define MC_CMD_MAC_TX_256_TO_511_PKTS 13 1082#define MC_CMD_MAC_TX_512_TO_1023_PKTS 14 1083#define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 15 1084#define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 16 1085#define MC_CMD_MAC_TX_GTJUMBO_PKTS 17 1086#define MC_CMD_MAC_TX_BAD_FCS_PKTS 18 1087#define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 19 1088#define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 20 1089#define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 21 1090#define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 22 1091#define MC_CMD_MAC_TX_DEFERRED_PKTS 23 1092#define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 24 1093#define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 25 1094#define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 26 1095#define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 27 1096#define MC_CMD_MAC_RX_PKTS 28 1097#define MC_CMD_MAC_RX_PAUSE_PKTS 29 1098#define MC_CMD_MAC_RX_GOOD_PKTS 30 1099#define MC_CMD_MAC_RX_CONTROL_PKTS 31 1100#define MC_CMD_MAC_RX_UNICAST_PKTS 32 1101#define MC_CMD_MAC_RX_MULTICAST_PKTS 33 1102#define MC_CMD_MAC_RX_BROADCAST_PKTS 34 1103#define MC_CMD_MAC_RX_BYTES 35 1104#define MC_CMD_MAC_RX_BAD_BYTES 36 1105#define MC_CMD_MAC_RX_64_PKTS 37 1106#define MC_CMD_MAC_RX_65_TO_127_PKTS 38 1107#define MC_CMD_MAC_RX_128_TO_255_PKTS 39 1108#define MC_CMD_MAC_RX_256_TO_511_PKTS 40 1109#define MC_CMD_MAC_RX_512_TO_1023_PKTS 41 1110#define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 42 1111#define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 43 1112#define MC_CMD_MAC_RX_GTJUMBO_PKTS 44 1113#define MC_CMD_MAC_RX_UNDERSIZE_PKTS 45 1114#define MC_CMD_MAC_RX_BAD_FCS_PKTS 46 1115#define MC_CMD_MAC_RX_OVERFLOW_PKTS 47 1116#define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 48 1117#define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 49 1118#define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 50 1119#define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 51 1120#define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 52 1121#define MC_CMD_MAC_RX_JABBER_PKTS 53 1122#define MC_CMD_MAC_RX_NODESC_DROPS 54 1123#define MC_CMD_MAC_RX_LANES01_CHAR_ERR 55 1124#define MC_CMD_MAC_RX_LANES23_CHAR_ERR 56 1125#define MC_CMD_MAC_RX_LANES01_DISP_ERR 57 1126#define MC_CMD_MAC_RX_LANES23_DISP_ERR 58 1127#define MC_CMD_MAC_RX_MATCH_FAULT 59 1128#define MC_CMD_GMAC_DMABUF_START 64 1129#define MC_CMD_GMAC_DMABUF_END 95 1130/* Insert new members here. */ 1131#define MC_CMD_MAC_GENERATION_END 96 1132#define MC_CMD_MAC_NSTATS (MC_CMD_MAC_GENERATION_END+1) 1133 1134/* MC_CMD_MAC_STATS: 1135 * Get unified GMAC/XMAC statistics 1136 * 1137 * This call returns unified statistics maintained by the MC as it 1138 * switches between the GMAC and XMAC. The MC will write out all 1139 * supported stats. The driver should zero initialise the buffer to 1140 * guarantee consistent results. 1141 * 1142 * Locks required: None 1143 * Returns: 0 1144 * Response methods: shared memory, event 1145 */ 1146#define MC_CMD_MAC_STATS 0x2e 1147#define MC_CMD_MAC_STATS_IN_LEN 16 1148#define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0 1149#define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4 1150#define MC_CMD_MAC_STATS_IN_CMD_OFST 8 1151#define MC_CMD_MAC_STATS_CMD_DMA_LBN 0 1152#define MC_CMD_MAC_STATS_CMD_DMA_WIDTH 1 1153#define MC_CMD_MAC_STATS_CMD_CLEAR_LBN 1 1154#define MC_CMD_MAC_STATS_CMD_CLEAR_WIDTH 1 1155#define MC_CMD_MAC_STATS_CMD_PERIODIC_CHANGE_LBN 2 1156#define MC_CMD_MAC_STATS_CMD_PERIODIC_CHANGE_WIDTH 1 1157/* Remaining PERIOD* fields only relevent when PERIODIC_CHANGE is set */ 1158#define MC_CMD_MAC_STATS_CMD_PERIODIC_ENABLE_LBN 3 1159#define MC_CMD_MAC_STATS_CMD_PERIODIC_ENABLE_WIDTH 1 1160#define MC_CMD_MAC_STATS_CMD_PERIODIC_CLEAR_LBN 4 1161#define MC_CMD_MAC_STATS_CMD_PERIODIC_CLEAR_WIDTH 1 1162#define MC_CMD_MAC_STATS_CMD_PERIODIC_NOEVENT_LBN 5 1163#define MC_CMD_MAC_STATS_CMD_PERIODIC_NOEVENT_WIDTH 1 1164#define MC_CMD_MAC_STATS_CMD_PERIOD_MS_LBN 16 1165#define MC_CMD_MAC_STATS_CMD_PERIOD_MS_WIDTH 16 1166#define MC_CMD_MAC_STATS_IN_DMA_LEN_OFST 12 1167 1168#define MC_CMD_MAC_STATS_OUT_LEN 0 1169 1170/* Callisto flags */ 1171#define MC_CMD_SFT9001_ROBUST_LBN 0 1172#define MC_CMD_SFT9001_ROBUST_WIDTH 1 1173#define MC_CMD_SFT9001_SHORT_REACH_LBN 1 1174#define MC_CMD_SFT9001_SHORT_REACH_WIDTH 1 1175 1176/* MC_CMD_SFT9001_GET: 1177 * Read current callisto specific setting 1178 * 1179 * Locks required: None 1180 * Returns: 0, ETIME 1181 */ 1182#define MC_CMD_SFT9001_GET 0x30 1183#define MC_CMD_SFT9001_GET_IN_LEN 0 1184#define MC_CMD_SFT9001_GET_OUT_LEN 4 1185#define MC_CMD_SFT9001_GET_OUT_FLAGS_OFST 0 1186 1187/* MC_CMD_SFT9001_SET: 1188 * Write current callisto specific setting 1189 * 1190 * Locks required: None 1191 * Returns: 0, ETIME, EINVAL 1192 */ 1193#define MC_CMD_SFT9001_SET 0x31 1194#define MC_CMD_SFT9001_SET_IN_LEN 4 1195#define MC_CMD_SFT9001_SET_IN_FLAGS_OFST 0 1196#define MC_CMD_SFT9001_SET_OUT_LEN 0 1197 1198 1199/* MC_CMD_WOL_FILTER_SET: 1200 * Set a WoL filter 1201 * 1202 * Locks required: None 1203 * Returns: 0, EBUSY, EINVAL, ENOSYS 1204 */ 1205#define MC_CMD_WOL_FILTER_SET 0x32 1206#define MC_CMD_WOL_FILTER_SET_IN_LEN 192 /* 190 rounded up to a word */ 1207#define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 1208#define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 1209 1210/* There is a union at offset 8, following defines overlap due to 1211 * this */ 1212#define MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 8 1213 1214#define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_OFST \ 1215 MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 1216 1217#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_OFST \ 1218 MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 1219#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_OFST \ 1220 (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 4) 1221#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_PORT_OFST \ 1222 (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 8) 1223#define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_PORT_OFST \ 1224 (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 10) 1225 1226#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_IP_OFST \ 1227 MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 1228#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_IP_OFST \ 1229 (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 16) 1230#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_SRC_PORT_OFST \ 1231 (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 32) 1232#define MC_CMD_WOL_FILTER_SET_IN_IPV6_SYN_DST_PORT_OFST \ 1233 (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 34) 1234 1235#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_MASK_OFST \ 1236 MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 1237#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_OFST \ 1238 (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 48) 1239#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LEN_OFST \ 1240 (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 176) 1241#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER3_OFST \ 1242 (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 177) 1243#define MC_CMD_WOL_FILTER_SET_IN_BITMAP_LAYER4_OFST \ 1244 (MC_CMD_WOL_FILTER_SET_IN_DATA_OFST + 178) 1245 1246#define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_OFST \ 1247 MC_CMD_WOL_FILTER_SET_IN_DATA_OFST 1248#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0 1249#define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_WIDTH 1 1250#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_LBN 1 1251#define MC_CMD_WOL_FILTER_SET_IN_LINK_DOWN_WIDTH 1 1252 1253#define MC_CMD_WOL_FILTER_SET_OUT_LEN 4 1254#define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0 1255 1256/* WOL Filter types enumeration */ 1257#define MC_CMD_WOL_TYPE_MAGIC 0x0 1258 /* unused 0x1 */ 1259#define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2 1260#define MC_CMD_WOL_TYPE_IPV4_SYN 0x3 1261#define MC_CMD_WOL_TYPE_IPV6_SYN 0x4 1262#define MC_CMD_WOL_TYPE_BITMAP 0x5 1263#define MC_CMD_WOL_TYPE_LINK 0x6 1264#define MC_CMD_WOL_TYPE_MAX 0x7 1265 1266#define MC_CMD_FILTER_MODE_SIMPLE 0x0 1267#define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff 1268 1269/* MC_CMD_WOL_FILTER_REMOVE: 1270 * Remove a WoL filter 1271 * 1272 * Locks required: None 1273 * Returns: 0, EINVAL, ENOSYS 1274 */ 1275#define MC_CMD_WOL_FILTER_REMOVE 0x33 1276#define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4 1277#define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0 1278#define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0 1279 1280 1281/* MC_CMD_WOL_FILTER_RESET: 1282 * Reset (i.e. remove all) WoL filters 1283 * 1284 * Locks required: None 1285 * Returns: 0, ENOSYS 1286 */ 1287#define MC_CMD_WOL_FILTER_RESET 0x34 1288#define MC_CMD_WOL_FILTER_RESET_IN_LEN 0 1289#define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0 1290 1291/* MC_CMD_SET_MCAST_HASH: 1292 * Set the MCASH hash value without otherwise 1293 * reconfiguring the MAC 1294 */ 1295#define MC_CMD_SET_MCAST_HASH 0x35 1296#define MC_CMD_SET_MCAST_HASH_IN_LEN 32 1297#define MC_CMD_SET_MCAST_HASH_IN_HASH0_OFST 0 1298#define MC_CMD_SET_MCAST_HASH_IN_HASH1_OFST 16 1299#define MC_CMD_SET_MCAST_HASH_OUT_LEN 0 1300 1301/* MC_CMD_NVRAM_TYPES: 1302 * Return bitfield indicating available types of virtual NVRAM partitions 1303 * 1304 * Locks required: none 1305 * Returns: 0 1306 */ 1307#define MC_CMD_NVRAM_TYPES 0x36 1308#define MC_CMD_NVRAM_TYPES_IN_LEN 0 1309#define MC_CMD_NVRAM_TYPES_OUT_LEN 4 1310#define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0 1311 1312/* Supported NVRAM types */ 1313#define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0 1314#define MC_CMD_NVRAM_TYPE_MC_FW 1 1315#define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 2 1316#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 3 1317#define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 4 1318#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 5 1319#define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 6 1320#define MC_CMD_NVRAM_TYPE_EXP_ROM 7 1321#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 8 1322#define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 9 1323#define MC_CMD_NVRAM_TYPE_PHY_PORT0 10 1324#define MC_CMD_NVRAM_TYPE_PHY_PORT1 11 1325#define MC_CMD_NVRAM_TYPE_LOG 12 1326 1327/* MC_CMD_NVRAM_INFO: 1328 * Read info about a virtual NVRAM partition 1329 * 1330 * Locks required: none 1331 * Returns: 0, EINVAL (bad type) 1332 */ 1333#define MC_CMD_NVRAM_INFO 0x37 1334#define MC_CMD_NVRAM_INFO_IN_LEN 4 1335#define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0 1336#define MC_CMD_NVRAM_INFO_OUT_LEN 24 1337#define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0 1338#define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4 1339#define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_OFST 8 1340#define MC_CMD_NVRAM_INFO_OUT_FLAGS_OFST 12 1341#define MC_CMD_NVRAM_PROTECTED_LBN 0 1342#define MC_CMD_NVRAM_PROTECTED_WIDTH 1 1343#define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_OFST 16 1344#define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_OFST 20 1345 1346/* MC_CMD_NVRAM_UPDATE_START: 1347 * Start a group of update operations on a virtual NVRAM partition 1348 * 1349 * Locks required: PHY_LOCK if type==*PHY* 1350 * Returns: 0, EINVAL (bad type), EACCES (if PHY_LOCK required and not held) 1351 */ 1352#define MC_CMD_NVRAM_UPDATE_START 0x38 1353#define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4 1354#define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0 1355#define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0 1356 1357/* MC_CMD_NVRAM_READ: 1358 * Read data from a virtual NVRAM partition 1359 * 1360 * Locks required: PHY_LOCK if type==*PHY* 1361 * Returns: 0, EINVAL (bad type/offset/length), EACCES (if PHY_LOCK required and not held) 1362 */ 1363#define MC_CMD_NVRAM_READ 0x39 1364#define MC_CMD_NVRAM_READ_IN_LEN 12 1365#define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0 1366#define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4 1367#define MC_CMD_NVRAM_READ_IN_LENGTH_OFST 8 1368#define MC_CMD_NVRAM_READ_OUT_LEN(_read_bytes) (_read_bytes) 1369#define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0 1370 1371/* MC_CMD_NVRAM_WRITE: 1372 * Write data to a virtual NVRAM partition 1373 * 1374 * Locks required: PHY_LOCK if type==*PHY* 1375 * Returns: 0, EINVAL (bad type/offset/length), EACCES (if PHY_LOCK required and not held) 1376 */ 1377#define MC_CMD_NVRAM_WRITE 0x3a 1378#define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0 1379#define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4 1380#define MC_CMD_NVRAM_WRITE_IN_LENGTH_OFST 8 1381#define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_OFST 12 1382#define MC_CMD_NVRAM_WRITE_IN_LEN(_write_bytes) (12 + _write_bytes) 1383#define MC_CMD_NVRAM_WRITE_OUT_LEN 0 1384 1385/* MC_CMD_NVRAM_ERASE: 1386 * Erase sector(s) from a virtual NVRAM partition 1387 * 1388 * Locks required: PHY_LOCK if type==*PHY* 1389 * Returns: 0, EINVAL (bad type/offset/length), EACCES (if PHY_LOCK required and not held) 1390 */ 1391#define MC_CMD_NVRAM_ERASE 0x3b 1392#define MC_CMD_NVRAM_ERASE_IN_LEN 12 1393#define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0 1394#define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4 1395#define MC_CMD_NVRAM_ERASE_IN_LENGTH_OFST 8 1396#define MC_CMD_NVRAM_ERASE_OUT_LEN 0 1397 1398/* MC_CMD_NVRAM_UPDATE_FINISH: 1399 * Finish a group of update operations on a virtual NVRAM partition 1400 * 1401 * Locks required: PHY_LOCK if type==*PHY* 1402 * Returns: 0, EINVAL (bad type/offset/length), EACCES (if PHY_LOCK required and not held) 1403 */ 1404#define MC_CMD_NVRAM_UPDATE_FINISH 0x3c 1405#define MC_CMD_NVRAM_UPDATE_FINISH_IN_LEN 8 1406#define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0 1407#define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4 1408#define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0 1409 1410/* MC_CMD_REBOOT: 1411 * Reboot the MC. 1412 * 1413 * The AFTER_ASSERTION flag is intended to be used when the driver notices 1414 * an assertion failure (at which point it is expected to perform a complete 1415 * tear down and reinitialise), to allow both ports to reset the MC once 1416 * in an atomic fashion. 1417 * 1418 * Production mc firmwares are generally compiled with REBOOT_ON_ASSERT=1, 1419 * which means that they will automatically reboot out of the assertion 1420 * handler, so this is in practise an optional operation. It is still 1421 * recommended that drivers execute this to support custom firmwares 1422 * with REBOOT_ON_ASSERT=0. 1423 * 1424 * Locks required: NONE 1425 * Returns: Nothing. You get back a response with ERR=1, DATALEN=0 1426 */ 1427#define MC_CMD_REBOOT 0x3d 1428#define MC_CMD_REBOOT_IN_LEN 4 1429#define MC_CMD_REBOOT_IN_FLAGS_OFST 0 1430#define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 1 1431#define MC_CMD_REBOOT_OUT_LEN 0 1432 1433/* MC_CMD_SCHEDINFO: 1434 * Request scheduler info. from the MC. 1435 * 1436 * Locks required: NONE 1437 * Returns: An array of (timeslice,maximum overrun), one for each thread, 1438 * in ascending order of thread address.s 1439 */ 1440#define MC_CMD_SCHEDINFO 0x3e 1441#define MC_CMD_SCHEDINFO_IN_LEN 0 1442 1443 1444/* MC_CMD_SET_REBOOT_MODE: (debug) 1445 * Set the mode for the next MC reboot. 1446 * 1447 * Locks required: NONE 1448 * 1449 * Sets the reboot mode to the specified value. Returns the old mode. 1450 */ 1451#define MC_CMD_REBOOT_MODE 0x3f 1452#define MC_CMD_REBOOT_MODE_IN_LEN 4 1453#define MC_CMD_REBOOT_MODE_IN_VALUE_OFST 0 1454#define MC_CMD_REBOOT_MODE_OUT_LEN 4 1455#define MC_CMD_REBOOT_MODE_OUT_VALUE_OFST 0 1456#define MC_CMD_REBOOT_MODE_NORMAL 0 1457#define MC_CMD_REBOOT_MODE_SNAPPER 3 1458 1459/* MC_CMD_DEBUG_LOG: 1460 * Null request/response command (debug) 1461 * - sequence number is always zero 1462 * - only supported on the UART interface 1463 * (the same set of bytes is delivered as an 1464 * event over PCI) 1465 */ 1466#define MC_CMD_DEBUG_LOG 0x40 1467#define MC_CMD_DEBUG_LOG_IN_LEN 0 1468#define MC_CMD_DEBUG_LOG_OUT_LEN 0 1469 1470/* Generic sensor enumeration. Note that a dual port NIC 1471 * will EITHER expose PHY_COMMON_TEMP OR PHY0_TEMP and 1472 * PHY1_TEMP depending on whether there is a single sensor 1473 * in the vicinity of the two port, or one per port. 1474 */ 1475#define MC_CMD_SENSOR_CONTROLLER_TEMP 0 /* degC */ 1476#define MC_CMD_SENSOR_PHY_COMMON_TEMP 1 /* degC */ 1477#define MC_CMD_SENSOR_CONTROLLER_COOLING 2 /* bool */ 1478#define MC_CMD_SENSOR_PHY0_TEMP 3 /* degC */ 1479#define MC_CMD_SENSOR_PHY0_COOLING 4 /* bool */ 1480#define MC_CMD_SENSOR_PHY1_TEMP 5 /* degC */ 1481#define MC_CMD_SENSOR_PHY1_COOLING 6 /* bool */ 1482#define MC_CMD_SENSOR_IN_1V0 7 /* mV */ 1483#define MC_CMD_SENSOR_IN_1V2 8 /* mV */ 1484#define MC_CMD_SENSOR_IN_1V8 9 /* mV */ 1485#define MC_CMD_SENSOR_IN_2V5 10 /* mV */ 1486#define MC_CMD_SENSOR_IN_3V3 11 /* mV */ 1487#define MC_CMD_SENSOR_IN_12V0 12 /* mV */ 1488 1489 1490/* Sensor state */ 1491#define MC_CMD_SENSOR_STATE_OK 0 1492#define MC_CMD_SENSOR_STATE_WARNING 1 1493#define MC_CMD_SENSOR_STATE_FATAL 2 1494#define MC_CMD_SENSOR_STATE_BROKEN 3 1495 1496/* MC_CMD_SENSOR_INFO: 1497 * Returns information about every available sensor. 1498 * 1499 * Each sensor has a single (16bit) value, and a corresponding state. 1500 * The mapping between value and sensor is nominally determined by the 1501 * MC, but in practise is implemented as zero (BROKEN), one (TEMPERATURE), 1502 * or two (VOLTAGE) ranges per sensor per state. 1503 * 1504 * This call returns a mask (32bit) of the sensors that are supported 1505 * by this platform, then an array (indexed by MC_CMD_SENSOR) of byte 1506 * offsets to the per-sensor arrays. Each sensor array has four 16bit 1507 * numbers, min1, max1, min2, max2. 1508 * 1509 * Locks required: None 1510 * Returns: 0 1511 */ 1512#define MC_CMD_SENSOR_INFO 0x41 1513#define MC_CMD_SENSOR_INFO_IN_LEN 0 1514#define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0 1515#define MC_CMD_SENSOR_INFO_OUT_OFFSET_OFST(_x) \ 1516 (4 + (_x)) 1517#define MC_CMD_SENSOR_INFO_OUT_MIN1_OFST(_ofst) \ 1518 ((_ofst) + 0) 1519#define MC_CMD_SENSOR_INFO_OUT_MAX1_OFST(_ofst) \ 1520 ((_ofst) + 2) 1521#define MC_CMD_SENSOR_INFO_OUT_MIN2_OFST(_ofst) \ 1522 ((_ofst) + 4) 1523#define MC_CMD_SENSOR_INFO_OUT_MAX2_OFST(_ofst) \ 1524 ((_ofst) + 6) 1525 1526/* MC_CMD_READ_SENSORS 1527 * Returns the current reading from each sensor 1528 * 1529 * Returns a sparse array of sensor readings (indexed by the sensor 1530 * type) into host memory. Each array element is a dword. 1531 * 1532 * The MC will send a SENSOREVT event every time any sensor changes state. The 1533 * driver is responsible for ensuring that it doesn't miss any events. The board 1534 * will function normally if all sensors are in STATE_OK or state_WARNING. 1535 * Otherwise the board should not be expected to function. 1536 */ 1537#define MC_CMD_READ_SENSORS 0x42 1538#define MC_CMD_READ_SENSORS_IN_LEN 8 1539#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0 1540#define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4 1541#define MC_CMD_READ_SENSORS_OUT_LEN 0 1542 1543/* Sensor reading fields */ 1544#define MC_CMD_READ_SENSOR_VALUE_LBN 0 1545#define MC_CMD_READ_SENSOR_VALUE_WIDTH 16 1546#define MC_CMD_READ_SENSOR_STATE_LBN 16 1547#define MC_CMD_READ_SENSOR_STATE_WIDTH 8 1548 1549 1550/* MC_CMD_GET_PHY_STATE: 1551 * Report current state of PHY. A "zombie" PHY is a PHY that has failed to 1552 * boot (e.g. due to missing or corrupted firmware). 1553 * 1554 * Locks required: None 1555 * Return code: 0 1556 */ 1557#define MC_CMD_GET_PHY_STATE 0x43 1558 1559#define MC_CMD_GET_PHY_STATE_IN_LEN 0 1560#define MC_CMD_GET_PHY_STATE_OUT_LEN 4 1561#define MC_CMD_GET_PHY_STATE_STATE_OFST 0 1562/* PHY state enumeration: */ 1563#define MC_CMD_PHY_STATE_OK 1 1564#define MC_CMD_PHY_STATE_ZOMBIE 2 1565 1566 1567/* 802.1Qbb control. 8 Tx queues that map to priorities 0 - 7. Use all 1s to 1568 * disable 802.Qbb for a given priority. */ 1569#define MC_CMD_SETUP_8021QBB 0x44 1570#define MC_CMD_SETUP_8021QBB_IN_LEN 32 1571#define MC_CMD_SETUP_8021QBB_OUT_LEN 0 1572#define MC_CMD_SETUP_8021QBB_IN_TXQS_OFFST 0 1573 1574 1575/* MC_CMD_WOL_FILTER_GET: 1576 * Retrieve ID of any WoL filters 1577 * 1578 * Locks required: None 1579 * Returns: 0, ENOSYS 1580 */ 1581#define MC_CMD_WOL_FILTER_GET 0x45 1582#define MC_CMD_WOL_FILTER_GET_IN_LEN 0 1583#define MC_CMD_WOL_FILTER_GET_OUT_LEN 4 1584#define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0 1585 1586 1587/* MC_CMD_ADD_LIGHTSOUT_OFFLOAD: 1588 * Offload a protocol to NIC for lights-out state 1589 * 1590 * Locks required: None 1591 * Returns: 0, ENOSYS 1592 */ 1593#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD 0x46 1594 1595#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_LEN 16 1596#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 1597 1598/* There is a union at offset 4, following defines overlap due to 1599 * this */ 1600#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_DATA_OFST 4 1601#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARPMAC_OFST 4 1602#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_ARPIP_OFST 10 1603#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NSMAC_OFST 4 1604#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NSSNIPV6_OFST 10 1605#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_IN_NSIPV6_OFST 26 1606 1607#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_LEN 4 1608#define MC_CMD_ADD_LIGHTSOUT_OFFLOAD_OUT_FILTER_ID_OFST 0 1609 1610 1611/* MC_CMD_REMOVE_LIGHTSOUT_PROTOCOL_OFFLOAD: 1612 * Offload a protocol to NIC for lights-out state 1613 * 1614 * Locks required: None 1615 * Returns: 0, ENOSYS 1616 */ 1617#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD 0x47 1618#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_LEN 8 1619#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_OUT_LEN 0 1620 1621#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_PROTOCOL_OFST 0 1622#define MC_CMD_REMOVE_LIGHTSOUT_OFFLOAD_IN_FILTER_ID_OFST 4 1623 1624/* Lights-out offload protocols enumeration */ 1625#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_ARP 0x1 1626#define MC_CMD_LIGHTSOUT_OFFLOAD_PROTOCOL_NS 0x2 1627 1628 1629/* MC_CMD_MAC_RESET_RESTORE: 1630 * Restore MAC after block reset 1631 * 1632 * Locks required: None 1633 * Returns: 0 1634 */ 1635 1636#define MC_CMD_MAC_RESET_RESTORE 0x48 1637#define MC_CMD_MAC_RESET_RESTORE_IN_LEN 0 1638#define MC_CMD_MAC_RESET_RESTORE_OUT_LEN 0 1639 1640 1641/* MC_CMD_TEST_ASSERT: 1642 * Deliberately trigger an assert-detonation in the firmware for testing 1643 * purposes (i.e. to allow tests that the driver copes gracefully). 1644 * 1645 * Locks required: None 1646 * Returns: 0 1647 */ 1648 1649#define MC_CMD_TESTASSERT 0x49 1650#define MC_CMD_TESTASSERT_IN_LEN 0 1651#define MC_CMD_TESTASSERT_OUT_LEN 0 1652 1653#define MC_CMD_WORKAROUND 0x4a 1654#define MC_CMD_WORKAROUND_IN_LEN 8 1655#define MC_CMD_WORKAROUND_IN_TYPE_OFST 0 1656#define MC_CMD_WORKAROUND_BUG17230 1 1657#define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4 1658#define MC_CMD_WORKAROUND_OUT_LEN 0 1659 1660/* MC_CMD_GET_PHY_MEDIA_INFO: 1661 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for 1662 * SFP+ PHYs). 1663 * 1664 * The "media type" can be found via GET_PHY_CFG (GET_PHY_CFG_OUT_MEDIA_TYPE); 1665 * the valid "page number" input values, and the output data, are interpreted 1666 * on a per-type basis. 1667 * 1668 * For SFP+: PAGE=0 or 1 returns a 128-byte block read from module I2C address 1669 * 0xA0 offset 0 or 0x80. 1670 * Anything else: currently undefined. 1671 * 1672 * Locks required: None 1673 * Return code: 0 1674 */ 1675#define MC_CMD_GET_PHY_MEDIA_INFO 0x4b 1676#define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4 1677#define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0 1678#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(_num_bytes) (4 + (_num_bytes)) 1679#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0 1680#define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4 1681 1682/* MC_CMD_NVRAM_TEST: 1683 * Test a particular NVRAM partition for valid contents (where "valid" 1684 * depends on the type of partition). 1685 * 1686 * Locks required: None 1687 * Return code: 0 1688 */ 1689#define MC_CMD_NVRAM_TEST 0x4c 1690#define MC_CMD_NVRAM_TEST_IN_LEN 4 1691#define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0 1692#define MC_CMD_NVRAM_TEST_OUT_LEN 4 1693#define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0 1694#define MC_CMD_NVRAM_TEST_PASS 0 1695#define MC_CMD_NVRAM_TEST_FAIL 1 1696#define MC_CMD_NVRAM_TEST_NOTSUPP 2 1697 1698/* MC_CMD_MRSFP_TWEAK: (debug) 1699 * Read status and/or set parameters for the "mrsfp" driver in mr_rusty builds. 1700 * I2C I/O expander bits are always read; if equaliser parameters are supplied, 1701 * they are configured first. 1702 * 1703 * Locks required: None 1704 * Return code: 0, EINVAL 1705 */ 1706#define MC_CMD_MRSFP_TWEAK 0x4d 1707#define MC_CMD_MRSFP_TWEAK_IN_LEN_READ_ONLY 0 1708#define MC_CMD_MRSFP_TWEAK_IN_LEN_EQ_CONFIG 16 1709#define MC_CMD_MRSFP_TWEAK_IN_TXEQ_LEVEL_OFST 0 /* 0-6 low->high de-emph. */ 1710#define MC_CMD_MRSFP_TWEAK_IN_TXEQ_DT_CFG_OFST 4 /* 0-8 low->high ref.V */ 1711#define MC_CMD_MRSFP_TWEAK_IN_RXEQ_BOOST_OFST 8 /* 0-8 low->high boost */ 1712#define MC_CMD_MRSFP_TWEAK_IN_RXEQ_DT_CFG_OFST 12 /* 0-8 low->high ref.V */ 1713#define MC_CMD_MRSFP_TWEAK_OUT_LEN 12 1714#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_INPUTS_OFST 0 /* input bits */ 1715#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_OUTPUTS_OFST 4 /* output bits */ 1716#define MC_CMD_MRSFP_TWEAK_OUT_IOEXP_DIRECTION_OFST 8 /* dirs: 0=out, 1=in */ 1717 1718/* MC_CMD_TEST_HACK: (debug (unsurprisingly)) 1719 * Change bits of network port state for test purposes in ways that would never be 1720 * useful in normal operation and so need a special command to change. */ 1721#define MC_CMD_TEST_HACK 0x2f 1722#define MC_CMD_TEST_HACK_IN_LEN 8 1723#define MC_CMD_TEST_HACK_IN_TXPAD_OFST 0 1724#define MC_CMD_TEST_HACK_IN_TXPAD_AUTO 0 /* Let the MC manage things */ 1725#define MC_CMD_TEST_HACK_IN_TXPAD_ON 1 /* Force on */ 1726#define MC_CMD_TEST_HACK_IN_TXPAD_OFF 2 /* Force on */ 1727#define MC_CMD_TEST_HACK_IN_IPG_OFST 4 /* Takes a value in bits */ 1728#define MC_CMD_TEST_HACK_IN_IPG_AUTO 0 /* The MC picks the value */ 1729#define MC_CMD_TEST_HACK_OUT_LEN 0 1730 1731/* MC_CMD_SENSOR_SET_LIMS: (debug) (mostly) adjust the sensor limits. This 1732 * is a warranty-voiding operation. 1733 * 1734 * IN: sensor identifier (one of the enumeration starting with MC_CMD_SENSOR_CONTROLLER_TEMP 1735 * followed by 4 32-bit values: min(warning) max(warning), min(fatal), max(fatal). Which 1736 * of these limits are meaningful and what their interpretation is is sensor-specific. 1737 * 1738 * OUT: nothing 1739 * 1740 * Returns: ENOENT if the sensor specified does not exist, EINVAL if the limits are 1741 * out of range. 1742 */ 1743#define MC_CMD_SENSOR_SET_LIMS 0x4e 1744#define MC_CMD_SENSOR_SET_LIMS_IN_LEN 20 1745#define MC_CMD_SENSOR_SET_LIMS_IN_SENSOR_OFST 0 1746#define MC_CMD_SENSOR_SET_LIMS_IN_LOW0_OFST 4 1747#define MC_CMD_SENSOR_SET_LIMS_IN_HI0_OFST 8 1748#define MC_CMD_SENSOR_SET_LIMS_IN_LOW1_OFST 12 1749#define MC_CMD_SENSOR_SET_LIMS_IN_HI1_OFST 16 1750 1751/* Do NOT add new commands beyond 0x4f as part of 3.0 : 0x50 - 0x7f will be 1752 * used for post-3.0 extensions. If you run out of space, look for gaps or 1753 * commands that are unused in the existing range. */ 1754 1755#endif /* MCDI_PCOL_H */ 1756