1/******************************************************************************* 2 3 Intel(R) Gigabit Ethernet Linux driver 4 Copyright(c) 2007-2009 Intel Corporation. 5 6 This program is free software; you can redistribute it and/or modify it 7 under the terms and conditions of the GNU General Public License, 8 version 2, as published by the Free Software Foundation. 9 10 This program is distributed in the hope it will be useful, but WITHOUT 11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 more details. 14 15 You should have received a copy of the GNU General Public License along with 16 this program; if not, write to the Free Software Foundation, Inc., 17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA. 18 19 The full GNU General Public License is included in this distribution in 20 the file called "COPYING". 21 22 Contact Information: 23 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net> 24 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 25 26*******************************************************************************/ 27 28#include <linux/if_ether.h> 29#include <linux/delay.h> 30 31#include "e1000_mac.h" 32#include "e1000_nvm.h" 33 34/** 35 * igb_raise_eec_clk - Raise EEPROM clock 36 * @hw: pointer to the HW structure 37 * @eecd: pointer to the EEPROM 38 * 39 * Enable/Raise the EEPROM clock bit. 40 **/ 41static void igb_raise_eec_clk(struct e1000_hw *hw, u32 *eecd) 42{ 43 *eecd = *eecd | E1000_EECD_SK; 44 wr32(E1000_EECD, *eecd); 45 wrfl(); 46 udelay(hw->nvm.delay_usec); 47} 48 49/** 50 * igb_lower_eec_clk - Lower EEPROM clock 51 * @hw: pointer to the HW structure 52 * @eecd: pointer to the EEPROM 53 * 54 * Clear/Lower the EEPROM clock bit. 55 **/ 56static void igb_lower_eec_clk(struct e1000_hw *hw, u32 *eecd) 57{ 58 *eecd = *eecd & ~E1000_EECD_SK; 59 wr32(E1000_EECD, *eecd); 60 wrfl(); 61 udelay(hw->nvm.delay_usec); 62} 63 64/** 65 * igb_shift_out_eec_bits - Shift data bits our to the EEPROM 66 * @hw: pointer to the HW structure 67 * @data: data to send to the EEPROM 68 * @count: number of bits to shift out 69 * 70 * We need to shift 'count' bits out to the EEPROM. So, the value in the 71 * "data" parameter will be shifted out to the EEPROM one bit at a time. 72 * In order to do this, "data" must be broken down into bits. 73 **/ 74static void igb_shift_out_eec_bits(struct e1000_hw *hw, u16 data, u16 count) 75{ 76 struct e1000_nvm_info *nvm = &hw->nvm; 77 u32 eecd = rd32(E1000_EECD); 78 u32 mask; 79 80 mask = 0x01 << (count - 1); 81 if (nvm->type == e1000_nvm_eeprom_spi) 82 eecd |= E1000_EECD_DO; 83 84 do { 85 eecd &= ~E1000_EECD_DI; 86 87 if (data & mask) 88 eecd |= E1000_EECD_DI; 89 90 wr32(E1000_EECD, eecd); 91 wrfl(); 92 93 udelay(nvm->delay_usec); 94 95 igb_raise_eec_clk(hw, &eecd); 96 igb_lower_eec_clk(hw, &eecd); 97 98 mask >>= 1; 99 } while (mask); 100 101 eecd &= ~E1000_EECD_DI; 102 wr32(E1000_EECD, eecd); 103} 104 105/** 106 * igb_shift_in_eec_bits - Shift data bits in from the EEPROM 107 * @hw: pointer to the HW structure 108 * @count: number of bits to shift in 109 * 110 * In order to read a register from the EEPROM, we need to shift 'count' bits 111 * in from the EEPROM. Bits are "shifted in" by raising the clock input to 112 * the EEPROM (setting the SK bit), and then reading the value of the data out 113 * "DO" bit. During this "shifting in" process the data in "DI" bit should 114 * always be clear. 115 **/ 116static u16 igb_shift_in_eec_bits(struct e1000_hw *hw, u16 count) 117{ 118 u32 eecd; 119 u32 i; 120 u16 data; 121 122 eecd = rd32(E1000_EECD); 123 124 eecd &= ~(E1000_EECD_DO | E1000_EECD_DI); 125 data = 0; 126 127 for (i = 0; i < count; i++) { 128 data <<= 1; 129 igb_raise_eec_clk(hw, &eecd); 130 131 eecd = rd32(E1000_EECD); 132 133 eecd &= ~E1000_EECD_DI; 134 if (eecd & E1000_EECD_DO) 135 data |= 1; 136 137 igb_lower_eec_clk(hw, &eecd); 138 } 139 140 return data; 141} 142 143/** 144 * igb_poll_eerd_eewr_done - Poll for EEPROM read/write completion 145 * @hw: pointer to the HW structure 146 * @ee_reg: EEPROM flag for polling 147 * 148 * Polls the EEPROM status bit for either read or write completion based 149 * upon the value of 'ee_reg'. 150 **/ 151static s32 igb_poll_eerd_eewr_done(struct e1000_hw *hw, int ee_reg) 152{ 153 u32 attempts = 100000; 154 u32 i, reg = 0; 155 s32 ret_val = -E1000_ERR_NVM; 156 157 for (i = 0; i < attempts; i++) { 158 if (ee_reg == E1000_NVM_POLL_READ) 159 reg = rd32(E1000_EERD); 160 else 161 reg = rd32(E1000_EEWR); 162 163 if (reg & E1000_NVM_RW_REG_DONE) { 164 ret_val = 0; 165 break; 166 } 167 168 udelay(5); 169 } 170 171 return ret_val; 172} 173 174/** 175 * igb_acquire_nvm - Generic request for access to EEPROM 176 * @hw: pointer to the HW structure 177 * 178 * Set the EEPROM access request bit and wait for EEPROM access grant bit. 179 * Return successful if access grant bit set, else clear the request for 180 * EEPROM access and return -E1000_ERR_NVM (-1). 181 **/ 182s32 igb_acquire_nvm(struct e1000_hw *hw) 183{ 184 u32 eecd = rd32(E1000_EECD); 185 s32 timeout = E1000_NVM_GRANT_ATTEMPTS; 186 s32 ret_val = 0; 187 188 189 wr32(E1000_EECD, eecd | E1000_EECD_REQ); 190 eecd = rd32(E1000_EECD); 191 192 while (timeout) { 193 if (eecd & E1000_EECD_GNT) 194 break; 195 udelay(5); 196 eecd = rd32(E1000_EECD); 197 timeout--; 198 } 199 200 if (!timeout) { 201 eecd &= ~E1000_EECD_REQ; 202 wr32(E1000_EECD, eecd); 203 hw_dbg("Could not acquire NVM grant\n"); 204 ret_val = -E1000_ERR_NVM; 205 } 206 207 return ret_val; 208} 209 210/** 211 * igb_standby_nvm - Return EEPROM to standby state 212 * @hw: pointer to the HW structure 213 * 214 * Return the EEPROM to a standby state. 215 **/ 216static void igb_standby_nvm(struct e1000_hw *hw) 217{ 218 struct e1000_nvm_info *nvm = &hw->nvm; 219 u32 eecd = rd32(E1000_EECD); 220 221 if (nvm->type == e1000_nvm_eeprom_spi) { 222 /* Toggle CS to flush commands */ 223 eecd |= E1000_EECD_CS; 224 wr32(E1000_EECD, eecd); 225 wrfl(); 226 udelay(nvm->delay_usec); 227 eecd &= ~E1000_EECD_CS; 228 wr32(E1000_EECD, eecd); 229 wrfl(); 230 udelay(nvm->delay_usec); 231 } 232} 233 234/** 235 * e1000_stop_nvm - Terminate EEPROM command 236 * @hw: pointer to the HW structure 237 * 238 * Terminates the current command by inverting the EEPROM's chip select pin. 239 **/ 240static void e1000_stop_nvm(struct e1000_hw *hw) 241{ 242 u32 eecd; 243 244 eecd = rd32(E1000_EECD); 245 if (hw->nvm.type == e1000_nvm_eeprom_spi) { 246 /* Pull CS high */ 247 eecd |= E1000_EECD_CS; 248 igb_lower_eec_clk(hw, &eecd); 249 } 250} 251 252/** 253 * igb_release_nvm - Release exclusive access to EEPROM 254 * @hw: pointer to the HW structure 255 * 256 * Stop any current commands to the EEPROM and clear the EEPROM request bit. 257 **/ 258void igb_release_nvm(struct e1000_hw *hw) 259{ 260 u32 eecd; 261 262 e1000_stop_nvm(hw); 263 264 eecd = rd32(E1000_EECD); 265 eecd &= ~E1000_EECD_REQ; 266 wr32(E1000_EECD, eecd); 267} 268 269/** 270 * igb_ready_nvm_eeprom - Prepares EEPROM for read/write 271 * @hw: pointer to the HW structure 272 * 273 * Setups the EEPROM for reading and writing. 274 **/ 275static s32 igb_ready_nvm_eeprom(struct e1000_hw *hw) 276{ 277 struct e1000_nvm_info *nvm = &hw->nvm; 278 u32 eecd = rd32(E1000_EECD); 279 s32 ret_val = 0; 280 u16 timeout = 0; 281 u8 spi_stat_reg; 282 283 284 if (nvm->type == e1000_nvm_eeprom_spi) { 285 /* Clear SK and CS */ 286 eecd &= ~(E1000_EECD_CS | E1000_EECD_SK); 287 wr32(E1000_EECD, eecd); 288 udelay(1); 289 timeout = NVM_MAX_RETRY_SPI; 290 291 /* 292 * Read "Status Register" repeatedly until the LSB is cleared. 293 * The EEPROM will signal that the command has been completed 294 * by clearing bit 0 of the internal status register. If it's 295 * not cleared within 'timeout', then error out. 296 */ 297 while (timeout) { 298 igb_shift_out_eec_bits(hw, NVM_RDSR_OPCODE_SPI, 299 hw->nvm.opcode_bits); 300 spi_stat_reg = (u8)igb_shift_in_eec_bits(hw, 8); 301 if (!(spi_stat_reg & NVM_STATUS_RDY_SPI)) 302 break; 303 304 udelay(5); 305 igb_standby_nvm(hw); 306 timeout--; 307 } 308 309 if (!timeout) { 310 hw_dbg("SPI NVM Status error\n"); 311 ret_val = -E1000_ERR_NVM; 312 goto out; 313 } 314 } 315 316out: 317 return ret_val; 318} 319 320/** 321 * igb_read_nvm_eerd - Reads EEPROM using EERD register 322 * @hw: pointer to the HW structure 323 * @offset: offset of word in the EEPROM to read 324 * @words: number of words to read 325 * @data: word read from the EEPROM 326 * 327 * Reads a 16 bit word from the EEPROM using the EERD register. 328 **/ 329s32 igb_read_nvm_eerd(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 330{ 331 struct e1000_nvm_info *nvm = &hw->nvm; 332 u32 i, eerd = 0; 333 s32 ret_val = 0; 334 335 /* 336 * A check for invalid values: offset too large, too many words, 337 * and not enough words. 338 */ 339 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 340 (words == 0)) { 341 hw_dbg("nvm parameter(s) out of bounds\n"); 342 ret_val = -E1000_ERR_NVM; 343 goto out; 344 } 345 346 for (i = 0; i < words; i++) { 347 eerd = ((offset+i) << E1000_NVM_RW_ADDR_SHIFT) + 348 E1000_NVM_RW_REG_START; 349 350 wr32(E1000_EERD, eerd); 351 ret_val = igb_poll_eerd_eewr_done(hw, E1000_NVM_POLL_READ); 352 if (ret_val) 353 break; 354 355 data[i] = (rd32(E1000_EERD) >> 356 E1000_NVM_RW_REG_DATA); 357 } 358 359out: 360 return ret_val; 361} 362 363/** 364 * igb_write_nvm_spi - Write to EEPROM using SPI 365 * @hw: pointer to the HW structure 366 * @offset: offset within the EEPROM to be written to 367 * @words: number of words to write 368 * @data: 16 bit word(s) to be written to the EEPROM 369 * 370 * Writes data to EEPROM at offset using SPI interface. 371 * 372 * If e1000_update_nvm_checksum is not called after this function , the 373 * EEPROM will most likley contain an invalid checksum. 374 **/ 375s32 igb_write_nvm_spi(struct e1000_hw *hw, u16 offset, u16 words, u16 *data) 376{ 377 struct e1000_nvm_info *nvm = &hw->nvm; 378 s32 ret_val; 379 u16 widx = 0; 380 381 /* 382 * A check for invalid values: offset too large, too many words, 383 * and not enough words. 384 */ 385 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) || 386 (words == 0)) { 387 hw_dbg("nvm parameter(s) out of bounds\n"); 388 ret_val = -E1000_ERR_NVM; 389 goto out; 390 } 391 392 ret_val = hw->nvm.ops.acquire(hw); 393 if (ret_val) 394 goto out; 395 396 msleep(10); 397 398 while (widx < words) { 399 u8 write_opcode = NVM_WRITE_OPCODE_SPI; 400 401 ret_val = igb_ready_nvm_eeprom(hw); 402 if (ret_val) 403 goto release; 404 405 igb_standby_nvm(hw); 406 407 /* Send the WRITE ENABLE command (8 bit opcode) */ 408 igb_shift_out_eec_bits(hw, NVM_WREN_OPCODE_SPI, 409 nvm->opcode_bits); 410 411 igb_standby_nvm(hw); 412 413 /* 414 * Some SPI eeproms use the 8th address bit embedded in the 415 * opcode 416 */ 417 if ((nvm->address_bits == 8) && (offset >= 128)) 418 write_opcode |= NVM_A8_OPCODE_SPI; 419 420 /* Send the Write command (8-bit opcode + addr) */ 421 igb_shift_out_eec_bits(hw, write_opcode, nvm->opcode_bits); 422 igb_shift_out_eec_bits(hw, (u16)((offset + widx) * 2), 423 nvm->address_bits); 424 425 /* Loop to allow for up to whole page write of eeprom */ 426 while (widx < words) { 427 u16 word_out = data[widx]; 428 word_out = (word_out >> 8) | (word_out << 8); 429 igb_shift_out_eec_bits(hw, word_out, 16); 430 widx++; 431 432 if ((((offset + widx) * 2) % nvm->page_size) == 0) { 433 igb_standby_nvm(hw); 434 break; 435 } 436 } 437 } 438 439 msleep(10); 440release: 441 hw->nvm.ops.release(hw); 442 443out: 444 return ret_val; 445} 446 447/** 448 * igb_read_part_num - Read device part number 449 * @hw: pointer to the HW structure 450 * @part_num: pointer to device part number 451 * 452 * Reads the product board assembly (PBA) number from the EEPROM and stores 453 * the value in part_num. 454 **/ 455s32 igb_read_part_num(struct e1000_hw *hw, u32 *part_num) 456{ 457 s32 ret_val; 458 u16 nvm_data; 459 460 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_0, 1, &nvm_data); 461 if (ret_val) { 462 hw_dbg("NVM Read Error\n"); 463 goto out; 464 } 465 *part_num = (u32)(nvm_data << 16); 466 467 ret_val = hw->nvm.ops.read(hw, NVM_PBA_OFFSET_1, 1, &nvm_data); 468 if (ret_val) { 469 hw_dbg("NVM Read Error\n"); 470 goto out; 471 } 472 *part_num |= nvm_data; 473 474out: 475 return ret_val; 476} 477 478/** 479 * igb_read_mac_addr - Read device MAC address 480 * @hw: pointer to the HW structure 481 * 482 * Reads the device MAC address from the EEPROM and stores the value. 483 * Since devices with two ports use the same EEPROM, we increment the 484 * last bit in the MAC address for the second port. 485 **/ 486s32 igb_read_mac_addr(struct e1000_hw *hw) 487{ 488 u32 rar_high; 489 u32 rar_low; 490 u16 i; 491 492 rar_high = rd32(E1000_RAH(0)); 493 rar_low = rd32(E1000_RAL(0)); 494 495 for (i = 0; i < E1000_RAL_MAC_ADDR_LEN; i++) 496 hw->mac.perm_addr[i] = (u8)(rar_low >> (i*8)); 497 498 for (i = 0; i < E1000_RAH_MAC_ADDR_LEN; i++) 499 hw->mac.perm_addr[i+4] = (u8)(rar_high >> (i*8)); 500 501 for (i = 0; i < ETH_ALEN; i++) 502 hw->mac.addr[i] = hw->mac.perm_addr[i]; 503 504 return 0; 505} 506 507/** 508 * igb_validate_nvm_checksum - Validate EEPROM checksum 509 * @hw: pointer to the HW structure 510 * 511 * Calculates the EEPROM checksum by reading/adding each word of the EEPROM 512 * and then verifies that the sum of the EEPROM is equal to 0xBABA. 513 **/ 514s32 igb_validate_nvm_checksum(struct e1000_hw *hw) 515{ 516 s32 ret_val = 0; 517 u16 checksum = 0; 518 u16 i, nvm_data; 519 520 for (i = 0; i < (NVM_CHECKSUM_REG + 1); i++) { 521 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 522 if (ret_val) { 523 hw_dbg("NVM Read Error\n"); 524 goto out; 525 } 526 checksum += nvm_data; 527 } 528 529 if (checksum != (u16) NVM_SUM) { 530 hw_dbg("NVM Checksum Invalid\n"); 531 ret_val = -E1000_ERR_NVM; 532 goto out; 533 } 534 535out: 536 return ret_val; 537} 538 539/** 540 * igb_update_nvm_checksum - Update EEPROM checksum 541 * @hw: pointer to the HW structure 542 * 543 * Updates the EEPROM checksum by reading/adding each word of the EEPROM 544 * up to the checksum. Then calculates the EEPROM checksum and writes the 545 * value to the EEPROM. 546 **/ 547s32 igb_update_nvm_checksum(struct e1000_hw *hw) 548{ 549 s32 ret_val; 550 u16 checksum = 0; 551 u16 i, nvm_data; 552 553 for (i = 0; i < NVM_CHECKSUM_REG; i++) { 554 ret_val = hw->nvm.ops.read(hw, i, 1, &nvm_data); 555 if (ret_val) { 556 hw_dbg("NVM Read Error while updating checksum.\n"); 557 goto out; 558 } 559 checksum += nvm_data; 560 } 561 checksum = (u16) NVM_SUM - checksum; 562 ret_val = hw->nvm.ops.write(hw, NVM_CHECKSUM_REG, 1, &checksum); 563 if (ret_val) 564 hw_dbg("NVM Write Error while updating checksum.\n"); 565 566out: 567 return ret_val; 568} 569