1/* 2 * Fast Ethernet Controller (FEC) driver for Motorola MPC8xx. 3 * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) 4 * 5 * Right now, I am very wasteful with the buffers. I allocate memory 6 * pages and then divide them into 2K frame buffers. This way I know I 7 * have buffers large enough to hold one frame within one buffer descriptor. 8 * Once I get this working, I will use 64 or 128 byte CPM buffers, which 9 * will be much more memory efficient and will easily handle lots of 10 * small packets. 11 * 12 * Much better multiple PHY support by Magnus Damm. 13 * Copyright (c) 2000 Ericsson Radio Systems AB. 14 * 15 * Support for FEC controller of ColdFire processors. 16 * Copyright (c) 2001-2005 Greg Ungerer (gerg@snapgear.com) 17 * 18 * Bug fixes and cleanup by Philippe De Muyter (phdm@macqel.be) 19 * Copyright (c) 2004-2006 Macq Electronique SA. 20 */ 21 22#include <linux/module.h> 23#include <linux/kernel.h> 24#include <linux/string.h> 25#include <linux/ptrace.h> 26#include <linux/errno.h> 27#include <linux/ioport.h> 28#include <linux/slab.h> 29#include <linux/interrupt.h> 30#include <linux/pci.h> 31#include <linux/init.h> 32#include <linux/delay.h> 33#include <linux/netdevice.h> 34#include <linux/etherdevice.h> 35#include <linux/skbuff.h> 36#include <linux/spinlock.h> 37#include <linux/workqueue.h> 38#include <linux/bitops.h> 39#include <linux/io.h> 40#include <linux/irq.h> 41#include <linux/clk.h> 42#include <linux/platform_device.h> 43#include <linux/phy.h> 44#include <linux/fec.h> 45 46#include <asm/cacheflush.h> 47 48#ifndef CONFIG_ARCH_MXC 49#include <asm/coldfire.h> 50#include <asm/mcfsim.h> 51#endif 52 53#include "fec.h" 54 55#ifdef CONFIG_ARCH_MXC 56#include <mach/hardware.h> 57#define FEC_ALIGNMENT 0xf 58#else 59#define FEC_ALIGNMENT 0x3 60#endif 61 62/* 63 * Define the fixed address of the FEC hardware. 64 */ 65#if defined(CONFIG_M5272) 66 67static unsigned char fec_mac_default[] = { 68 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 69}; 70 71/* 72 * Some hardware gets it MAC address out of local flash memory. 73 * if this is non-zero then assume it is the address to get MAC from. 74 */ 75#if defined(CONFIG_NETtel) 76#define FEC_FLASHMAC 0xf0006006 77#elif defined(CONFIG_GILBARCONAP) || defined(CONFIG_SCALES) 78#define FEC_FLASHMAC 0xf0006000 79#elif defined(CONFIG_CANCam) 80#define FEC_FLASHMAC 0xf0020000 81#elif defined(CONFIG_M5272C3) 82#define FEC_FLASHMAC (0xffe04000 + 4) 83#elif defined(CONFIG_MOD5272) 84#define FEC_FLASHMAC 0xffc0406b 85#else 86#define FEC_FLASHMAC 0 87#endif 88#endif /* CONFIG_M5272 */ 89 90/* The number of Tx and Rx buffers. These are allocated from the page 91 * pool. The code may assume these are power of two, so it it best 92 * to keep them that size. 93 * We don't need to allocate pages for the transmitter. We just use 94 * the skbuffer directly. 95 */ 96#define FEC_ENET_RX_PAGES 8 97#define FEC_ENET_RX_FRSIZE 2048 98#define FEC_ENET_RX_FRPPG (PAGE_SIZE / FEC_ENET_RX_FRSIZE) 99#define RX_RING_SIZE (FEC_ENET_RX_FRPPG * FEC_ENET_RX_PAGES) 100#define FEC_ENET_TX_FRSIZE 2048 101#define FEC_ENET_TX_FRPPG (PAGE_SIZE / FEC_ENET_TX_FRSIZE) 102#define TX_RING_SIZE 16 /* Must be power of two */ 103#define TX_RING_MOD_MASK 15 /* for this to work */ 104 105#if (((RX_RING_SIZE + TX_RING_SIZE) * 8) > PAGE_SIZE) 106#error "FEC: descriptor ring size constants too large" 107#endif 108 109/* Interrupt events/masks. */ 110#define FEC_ENET_HBERR ((uint)0x80000000) /* Heartbeat error */ 111#define FEC_ENET_BABR ((uint)0x40000000) /* Babbling receiver */ 112#define FEC_ENET_BABT ((uint)0x20000000) /* Babbling transmitter */ 113#define FEC_ENET_GRA ((uint)0x10000000) /* Graceful stop complete */ 114#define FEC_ENET_TXF ((uint)0x08000000) /* Full frame transmitted */ 115#define FEC_ENET_TXB ((uint)0x04000000) /* A buffer was transmitted */ 116#define FEC_ENET_RXF ((uint)0x02000000) /* Full frame received */ 117#define FEC_ENET_RXB ((uint)0x01000000) /* A buffer was received */ 118#define FEC_ENET_MII ((uint)0x00800000) /* MII interrupt */ 119#define FEC_ENET_EBERR ((uint)0x00400000) /* SDMA bus error */ 120 121#define FEC_DEFAULT_IMASK (FEC_ENET_TXF | FEC_ENET_RXF | FEC_ENET_MII) 122 123/* The FEC stores dest/src/type, data, and checksum for receive packets. 124 */ 125#define PKT_MAXBUF_SIZE 1518 126#define PKT_MINBUF_SIZE 64 127#define PKT_MAXBLR_SIZE 1520 128 129 130/* 131 * The 5270/5271/5280/5282/532x RX control register also contains maximum frame 132 * size bits. Other FEC hardware does not, so we need to take that into 133 * account when setting it. 134 */ 135#if defined(CONFIG_M523x) || defined(CONFIG_M527x) || defined(CONFIG_M528x) || \ 136 defined(CONFIG_M520x) || defined(CONFIG_M532x) || defined(CONFIG_ARCH_MXC) 137#define OPT_FRAME_SIZE (PKT_MAXBUF_SIZE << 16) 138#else 139#define OPT_FRAME_SIZE 0 140#endif 141 142/* The FEC buffer descriptors track the ring buffers. The rx_bd_base and 143 * tx_bd_base always point to the base of the buffer descriptors. The 144 * cur_rx and cur_tx point to the currently available buffer. 145 * The dirty_tx tracks the current buffer that is being sent by the 146 * controller. The cur_tx and dirty_tx are equal under both completely 147 * empty and completely full conditions. The empty/ready indicator in 148 * the buffer descriptor determines the actual condition. 149 */ 150struct fec_enet_private { 151 /* Hardware registers of the FEC device */ 152 void __iomem *hwp; 153 154 struct net_device *netdev; 155 156 struct clk *clk; 157 158 /* The saved address of a sent-in-place packet/buffer, for skfree(). */ 159 unsigned char *tx_bounce[TX_RING_SIZE]; 160 struct sk_buff* tx_skbuff[TX_RING_SIZE]; 161 struct sk_buff* rx_skbuff[RX_RING_SIZE]; 162 ushort skb_cur; 163 ushort skb_dirty; 164 165 /* CPM dual port RAM relative addresses */ 166 dma_addr_t bd_dma; 167 /* Address of Rx and Tx buffers */ 168 struct bufdesc *rx_bd_base; 169 struct bufdesc *tx_bd_base; 170 /* The next free ring entry */ 171 struct bufdesc *cur_rx, *cur_tx; 172 /* The ring entries to be free()ed */ 173 struct bufdesc *dirty_tx; 174 175 uint tx_full; 176 /* hold while accessing the HW like ringbuffer for tx/rx but not MAC */ 177 spinlock_t hw_lock; 178 179 struct platform_device *pdev; 180 181 int opened; 182 183 /* Phylib and MDIO interface */ 184 struct mii_bus *mii_bus; 185 struct phy_device *phy_dev; 186 int mii_timeout; 187 uint phy_speed; 188 phy_interface_t phy_interface; 189 int index; 190 int link; 191 int full_duplex; 192 struct completion mdio_done; 193}; 194 195static irqreturn_t fec_enet_interrupt(int irq, void * dev_id); 196static void fec_enet_tx(struct net_device *dev); 197static void fec_enet_rx(struct net_device *dev); 198static int fec_enet_close(struct net_device *dev); 199static void fec_restart(struct net_device *dev, int duplex); 200static void fec_stop(struct net_device *dev); 201 202/* FEC MII MMFR bits definition */ 203#define FEC_MMFR_ST (1 << 30) 204#define FEC_MMFR_OP_READ (2 << 28) 205#define FEC_MMFR_OP_WRITE (1 << 28) 206#define FEC_MMFR_PA(v) ((v & 0x1f) << 23) 207#define FEC_MMFR_RA(v) ((v & 0x1f) << 18) 208#define FEC_MMFR_TA (2 << 16) 209#define FEC_MMFR_DATA(v) (v & 0xffff) 210 211#define FEC_MII_TIMEOUT 1000 /* us */ 212 213/* Transmitter timeout */ 214#define TX_TIMEOUT (2 * HZ) 215 216static netdev_tx_t 217fec_enet_start_xmit(struct sk_buff *skb, struct net_device *dev) 218{ 219 struct fec_enet_private *fep = netdev_priv(dev); 220 struct bufdesc *bdp; 221 void *bufaddr; 222 unsigned short status; 223 unsigned long flags; 224 225 if (!fep->link) { 226 /* Link is down or autonegotiation is in progress. */ 227 return NETDEV_TX_BUSY; 228 } 229 230 spin_lock_irqsave(&fep->hw_lock, flags); 231 /* Fill in a Tx ring entry */ 232 bdp = fep->cur_tx; 233 234 status = bdp->cbd_sc; 235 236 if (status & BD_ENET_TX_READY) { 237 /* Ooops. All transmit buffers are full. Bail out. 238 * This should not happen, since dev->tbusy should be set. 239 */ 240 printk("%s: tx queue full!.\n", dev->name); 241 spin_unlock_irqrestore(&fep->hw_lock, flags); 242 return NETDEV_TX_BUSY; 243 } 244 245 /* Clear all of the status flags */ 246 status &= ~BD_ENET_TX_STATS; 247 248 /* Set buffer length and buffer pointer */ 249 bufaddr = skb->data; 250 bdp->cbd_datlen = skb->len; 251 252 /* 253 * On some FEC implementations data must be aligned on 254 * 4-byte boundaries. Use bounce buffers to copy data 255 * and get it aligned. Ugh. 256 */ 257 if (((unsigned long) bufaddr) & FEC_ALIGNMENT) { 258 unsigned int index; 259 index = bdp - fep->tx_bd_base; 260 memcpy(fep->tx_bounce[index], (void *)skb->data, skb->len); 261 bufaddr = fep->tx_bounce[index]; 262 } 263 264 /* Save skb pointer */ 265 fep->tx_skbuff[fep->skb_cur] = skb; 266 267 dev->stats.tx_bytes += skb->len; 268 fep->skb_cur = (fep->skb_cur+1) & TX_RING_MOD_MASK; 269 270 /* Push the data cache so the CPM does not get stale memory 271 * data. 272 */ 273 bdp->cbd_bufaddr = dma_map_single(&dev->dev, bufaddr, 274 FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 275 276 /* Send it on its way. Tell FEC it's ready, interrupt when done, 277 * it's the last BD of the frame, and to put the CRC on the end. 278 */ 279 status |= (BD_ENET_TX_READY | BD_ENET_TX_INTR 280 | BD_ENET_TX_LAST | BD_ENET_TX_TC); 281 bdp->cbd_sc = status; 282 283 /* Trigger transmission start */ 284 writel(0, fep->hwp + FEC_X_DES_ACTIVE); 285 286 /* If this was the last BD in the ring, start at the beginning again. */ 287 if (status & BD_ENET_TX_WRAP) 288 bdp = fep->tx_bd_base; 289 else 290 bdp++; 291 292 if (bdp == fep->dirty_tx) { 293 fep->tx_full = 1; 294 netif_stop_queue(dev); 295 } 296 297 fep->cur_tx = bdp; 298 299 spin_unlock_irqrestore(&fep->hw_lock, flags); 300 301 return NETDEV_TX_OK; 302} 303 304static void 305fec_timeout(struct net_device *dev) 306{ 307 struct fec_enet_private *fep = netdev_priv(dev); 308 309 dev->stats.tx_errors++; 310 311 fec_restart(dev, fep->full_duplex); 312 netif_wake_queue(dev); 313} 314 315static irqreturn_t 316fec_enet_interrupt(int irq, void * dev_id) 317{ 318 struct net_device *dev = dev_id; 319 struct fec_enet_private *fep = netdev_priv(dev); 320 uint int_events; 321 irqreturn_t ret = IRQ_NONE; 322 323 do { 324 int_events = readl(fep->hwp + FEC_IEVENT); 325 writel(int_events, fep->hwp + FEC_IEVENT); 326 327 if (int_events & FEC_ENET_RXF) { 328 ret = IRQ_HANDLED; 329 fec_enet_rx(dev); 330 } 331 332 /* Transmit OK, or non-fatal error. Update the buffer 333 * descriptors. FEC handles all errors, we just discover 334 * them as part of the transmit process. 335 */ 336 if (int_events & FEC_ENET_TXF) { 337 ret = IRQ_HANDLED; 338 fec_enet_tx(dev); 339 } 340 341 if (int_events & FEC_ENET_MII) { 342 ret = IRQ_HANDLED; 343 complete(&fep->mdio_done); 344 } 345 } while (int_events); 346 347 return ret; 348} 349 350 351static void 352fec_enet_tx(struct net_device *dev) 353{ 354 struct fec_enet_private *fep; 355 struct bufdesc *bdp; 356 unsigned short status; 357 struct sk_buff *skb; 358 359 fep = netdev_priv(dev); 360 spin_lock(&fep->hw_lock); 361 bdp = fep->dirty_tx; 362 363 while (((status = bdp->cbd_sc) & BD_ENET_TX_READY) == 0) { 364 if (bdp == fep->cur_tx && fep->tx_full == 0) 365 break; 366 367 dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, FEC_ENET_TX_FRSIZE, DMA_TO_DEVICE); 368 bdp->cbd_bufaddr = 0; 369 370 skb = fep->tx_skbuff[fep->skb_dirty]; 371 /* Check for errors. */ 372 if (status & (BD_ENET_TX_HB | BD_ENET_TX_LC | 373 BD_ENET_TX_RL | BD_ENET_TX_UN | 374 BD_ENET_TX_CSL)) { 375 dev->stats.tx_errors++; 376 if (status & BD_ENET_TX_HB) /* No heartbeat */ 377 dev->stats.tx_heartbeat_errors++; 378 if (status & BD_ENET_TX_LC) /* Late collision */ 379 dev->stats.tx_window_errors++; 380 if (status & BD_ENET_TX_RL) /* Retrans limit */ 381 dev->stats.tx_aborted_errors++; 382 if (status & BD_ENET_TX_UN) /* Underrun */ 383 dev->stats.tx_fifo_errors++; 384 if (status & BD_ENET_TX_CSL) /* Carrier lost */ 385 dev->stats.tx_carrier_errors++; 386 } else { 387 dev->stats.tx_packets++; 388 } 389 390 if (status & BD_ENET_TX_READY) 391 printk("HEY! Enet xmit interrupt and TX_READY.\n"); 392 393 /* Deferred means some collisions occurred during transmit, 394 * but we eventually sent the packet OK. 395 */ 396 if (status & BD_ENET_TX_DEF) 397 dev->stats.collisions++; 398 399 /* Free the sk buffer associated with this last transmit */ 400 dev_kfree_skb_any(skb); 401 fep->tx_skbuff[fep->skb_dirty] = NULL; 402 fep->skb_dirty = (fep->skb_dirty + 1) & TX_RING_MOD_MASK; 403 404 /* Update pointer to next buffer descriptor to be transmitted */ 405 if (status & BD_ENET_TX_WRAP) 406 bdp = fep->tx_bd_base; 407 else 408 bdp++; 409 410 /* Since we have freed up a buffer, the ring is no longer full 411 */ 412 if (fep->tx_full) { 413 fep->tx_full = 0; 414 if (netif_queue_stopped(dev)) 415 netif_wake_queue(dev); 416 } 417 } 418 fep->dirty_tx = bdp; 419 spin_unlock(&fep->hw_lock); 420} 421 422 423/* During a receive, the cur_rx points to the current incoming buffer. 424 * When we update through the ring, if the next incoming buffer has 425 * not been given to the system, we just set the empty indicator, 426 * effectively tossing the packet. 427 */ 428static void 429fec_enet_rx(struct net_device *dev) 430{ 431 struct fec_enet_private *fep = netdev_priv(dev); 432 struct bufdesc *bdp; 433 unsigned short status; 434 struct sk_buff *skb; 435 ushort pkt_len; 436 __u8 *data; 437 438#ifdef CONFIG_M532x 439 flush_cache_all(); 440#endif 441 442 spin_lock(&fep->hw_lock); 443 444 /* First, grab all of the stats for the incoming packet. 445 * These get messed up if we get called due to a busy condition. 446 */ 447 bdp = fep->cur_rx; 448 449 while (!((status = bdp->cbd_sc) & BD_ENET_RX_EMPTY)) { 450 451 /* Since we have allocated space to hold a complete frame, 452 * the last indicator should be set. 453 */ 454 if ((status & BD_ENET_RX_LAST) == 0) 455 printk("FEC ENET: rcv is not +last\n"); 456 457 if (!fep->opened) 458 goto rx_processing_done; 459 460 /* Check for errors. */ 461 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH | BD_ENET_RX_NO | 462 BD_ENET_RX_CR | BD_ENET_RX_OV)) { 463 dev->stats.rx_errors++; 464 if (status & (BD_ENET_RX_LG | BD_ENET_RX_SH)) { 465 /* Frame too long or too short. */ 466 dev->stats.rx_length_errors++; 467 } 468 if (status & BD_ENET_RX_NO) /* Frame alignment */ 469 dev->stats.rx_frame_errors++; 470 if (status & BD_ENET_RX_CR) /* CRC Error */ 471 dev->stats.rx_crc_errors++; 472 if (status & BD_ENET_RX_OV) /* FIFO overrun */ 473 dev->stats.rx_fifo_errors++; 474 } 475 476 /* Report late collisions as a frame error. 477 * On this error, the BD is closed, but we don't know what we 478 * have in the buffer. So, just drop this frame on the floor. 479 */ 480 if (status & BD_ENET_RX_CL) { 481 dev->stats.rx_errors++; 482 dev->stats.rx_frame_errors++; 483 goto rx_processing_done; 484 } 485 486 /* Process the incoming frame. */ 487 dev->stats.rx_packets++; 488 pkt_len = bdp->cbd_datlen; 489 dev->stats.rx_bytes += pkt_len; 490 data = (__u8*)__va(bdp->cbd_bufaddr); 491 492 dma_unmap_single(NULL, bdp->cbd_bufaddr, bdp->cbd_datlen, 493 DMA_FROM_DEVICE); 494 495 /* This does 16 byte alignment, exactly what we need. 496 * The packet length includes FCS, but we don't want to 497 * include that when passing upstream as it messes up 498 * bridging applications. 499 */ 500 skb = dev_alloc_skb(pkt_len - 4 + NET_IP_ALIGN); 501 502 if (unlikely(!skb)) { 503 printk("%s: Memory squeeze, dropping packet.\n", 504 dev->name); 505 dev->stats.rx_dropped++; 506 } else { 507 skb_reserve(skb, NET_IP_ALIGN); 508 skb_put(skb, pkt_len - 4); /* Make room */ 509 skb_copy_to_linear_data(skb, data, pkt_len - 4); 510 skb->protocol = eth_type_trans(skb, dev); 511 netif_rx(skb); 512 } 513 514 bdp->cbd_bufaddr = dma_map_single(NULL, data, bdp->cbd_datlen, 515 DMA_FROM_DEVICE); 516rx_processing_done: 517 /* Clear the status flags for this buffer */ 518 status &= ~BD_ENET_RX_STATS; 519 520 /* Mark the buffer empty */ 521 status |= BD_ENET_RX_EMPTY; 522 bdp->cbd_sc = status; 523 524 /* Update BD pointer to next entry */ 525 if (status & BD_ENET_RX_WRAP) 526 bdp = fep->rx_bd_base; 527 else 528 bdp++; 529 /* Doing this here will keep the FEC running while we process 530 * incoming frames. On a heavily loaded network, we should be 531 * able to keep up at the expense of system resources. 532 */ 533 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 534 } 535 fep->cur_rx = bdp; 536 537 spin_unlock(&fep->hw_lock); 538} 539 540/* ------------------------------------------------------------------------- */ 541#ifdef CONFIG_M5272 542static void __inline__ fec_get_mac(struct net_device *dev) 543{ 544 struct fec_enet_private *fep = netdev_priv(dev); 545 unsigned char *iap, tmpaddr[ETH_ALEN]; 546 547 if (FEC_FLASHMAC) { 548 /* 549 * Get MAC address from FLASH. 550 * If it is all 1's or 0's, use the default. 551 */ 552 iap = (unsigned char *)FEC_FLASHMAC; 553 if ((iap[0] == 0) && (iap[1] == 0) && (iap[2] == 0) && 554 (iap[3] == 0) && (iap[4] == 0) && (iap[5] == 0)) 555 iap = fec_mac_default; 556 if ((iap[0] == 0xff) && (iap[1] == 0xff) && (iap[2] == 0xff) && 557 (iap[3] == 0xff) && (iap[4] == 0xff) && (iap[5] == 0xff)) 558 iap = fec_mac_default; 559 } else { 560 *((unsigned long *) &tmpaddr[0]) = readl(fep->hwp + FEC_ADDR_LOW); 561 *((unsigned short *) &tmpaddr[4]) = (readl(fep->hwp + FEC_ADDR_HIGH) >> 16); 562 iap = &tmpaddr[0]; 563 } 564 565 memcpy(dev->dev_addr, iap, ETH_ALEN); 566 567 /* Adjust MAC if using default MAC address */ 568 if (iap == fec_mac_default) 569 dev->dev_addr[ETH_ALEN-1] = fec_mac_default[ETH_ALEN-1] + fep->index; 570} 571#endif 572 573/* ------------------------------------------------------------------------- */ 574 575/* 576 * Phy section 577 */ 578static void fec_enet_adjust_link(struct net_device *dev) 579{ 580 struct fec_enet_private *fep = netdev_priv(dev); 581 struct phy_device *phy_dev = fep->phy_dev; 582 unsigned long flags; 583 584 int status_change = 0; 585 586 spin_lock_irqsave(&fep->hw_lock, flags); 587 588 /* Prevent a state halted on mii error */ 589 if (fep->mii_timeout && phy_dev->state == PHY_HALTED) { 590 phy_dev->state = PHY_RESUMING; 591 goto spin_unlock; 592 } 593 594 /* Duplex link change */ 595 if (phy_dev->link) { 596 if (fep->full_duplex != phy_dev->duplex) { 597 fec_restart(dev, phy_dev->duplex); 598 status_change = 1; 599 } 600 } 601 602 /* Link on or off change */ 603 if (phy_dev->link != fep->link) { 604 fep->link = phy_dev->link; 605 if (phy_dev->link) 606 fec_restart(dev, phy_dev->duplex); 607 else 608 fec_stop(dev); 609 status_change = 1; 610 } 611 612spin_unlock: 613 spin_unlock_irqrestore(&fep->hw_lock, flags); 614 615 if (status_change) 616 phy_print_status(phy_dev); 617} 618 619static int fec_enet_mdio_read(struct mii_bus *bus, int mii_id, int regnum) 620{ 621 struct fec_enet_private *fep = bus->priv; 622 unsigned long time_left; 623 624 fep->mii_timeout = 0; 625 init_completion(&fep->mdio_done); 626 627 /* start a read op */ 628 writel(FEC_MMFR_ST | FEC_MMFR_OP_READ | 629 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 630 FEC_MMFR_TA, fep->hwp + FEC_MII_DATA); 631 632 /* wait for end of transfer */ 633 time_left = wait_for_completion_timeout(&fep->mdio_done, 634 usecs_to_jiffies(FEC_MII_TIMEOUT)); 635 if (time_left == 0) { 636 fep->mii_timeout = 1; 637 printk(KERN_ERR "FEC: MDIO read timeout\n"); 638 return -ETIMEDOUT; 639 } 640 641 /* return value */ 642 return FEC_MMFR_DATA(readl(fep->hwp + FEC_MII_DATA)); 643} 644 645static int fec_enet_mdio_write(struct mii_bus *bus, int mii_id, int regnum, 646 u16 value) 647{ 648 struct fec_enet_private *fep = bus->priv; 649 unsigned long time_left; 650 651 fep->mii_timeout = 0; 652 init_completion(&fep->mdio_done); 653 654 /* start a write op */ 655 writel(FEC_MMFR_ST | FEC_MMFR_OP_WRITE | 656 FEC_MMFR_PA(mii_id) | FEC_MMFR_RA(regnum) | 657 FEC_MMFR_TA | FEC_MMFR_DATA(value), 658 fep->hwp + FEC_MII_DATA); 659 660 /* wait for end of transfer */ 661 time_left = wait_for_completion_timeout(&fep->mdio_done, 662 usecs_to_jiffies(FEC_MII_TIMEOUT)); 663 if (time_left == 0) { 664 fep->mii_timeout = 1; 665 printk(KERN_ERR "FEC: MDIO write timeout\n"); 666 return -ETIMEDOUT; 667 } 668 669 return 0; 670} 671 672static int fec_enet_mdio_reset(struct mii_bus *bus) 673{ 674 return 0; 675} 676 677static int fec_enet_mii_probe(struct net_device *dev) 678{ 679 struct fec_enet_private *fep = netdev_priv(dev); 680 struct phy_device *phy_dev = NULL; 681 char mdio_bus_id[MII_BUS_ID_SIZE]; 682 char phy_name[MII_BUS_ID_SIZE + 3]; 683 int phy_id; 684 685 fep->phy_dev = NULL; 686 687 /* check for attached phy */ 688 for (phy_id = 0; (phy_id < PHY_MAX_ADDR); phy_id++) { 689 if ((fep->mii_bus->phy_mask & (1 << phy_id))) 690 continue; 691 if (fep->mii_bus->phy_map[phy_id] == NULL) 692 continue; 693 if (fep->mii_bus->phy_map[phy_id]->phy_id == 0) 694 continue; 695 strncpy(mdio_bus_id, fep->mii_bus->id, MII_BUS_ID_SIZE); 696 break; 697 } 698 699 if (phy_id >= PHY_MAX_ADDR) { 700 printk(KERN_INFO "%s: no PHY, assuming direct connection " 701 "to switch\n", dev->name); 702 strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); 703 phy_id = 0; 704 } 705 706 snprintf(phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id); 707 phy_dev = phy_connect(dev, phy_name, &fec_enet_adjust_link, 0, 708 PHY_INTERFACE_MODE_MII); 709 if (IS_ERR(phy_dev)) { 710 printk(KERN_ERR "%s: could not attach to PHY\n", dev->name); 711 return PTR_ERR(phy_dev); 712 } 713 714 /* mask with MAC supported features */ 715 phy_dev->supported &= PHY_BASIC_FEATURES; 716 phy_dev->advertising = phy_dev->supported; 717 718 fep->phy_dev = phy_dev; 719 fep->link = 0; 720 fep->full_duplex = 0; 721 722 printk(KERN_INFO "%s: Freescale FEC PHY driver [%s] " 723 "(mii_bus:phy_addr=%s, irq=%d)\n", dev->name, 724 fep->phy_dev->drv->name, dev_name(&fep->phy_dev->dev), 725 fep->phy_dev->irq); 726 727 return 0; 728} 729 730static int fec_enet_mii_init(struct platform_device *pdev) 731{ 732 struct net_device *dev = platform_get_drvdata(pdev); 733 struct fec_enet_private *fep = netdev_priv(dev); 734 int err = -ENXIO, i; 735 736 fep->mii_timeout = 0; 737 738 /* 739 * Set MII speed to 2.5 MHz (= clk_get_rate() / 2 * phy_speed) 740 */ 741 fep->phy_speed = DIV_ROUND_UP(clk_get_rate(fep->clk), 5000000) << 1; 742 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 743 744 fep->mii_bus = mdiobus_alloc(); 745 if (fep->mii_bus == NULL) { 746 err = -ENOMEM; 747 goto err_out; 748 } 749 750 fep->mii_bus->name = "fec_enet_mii_bus"; 751 fep->mii_bus->read = fec_enet_mdio_read; 752 fep->mii_bus->write = fec_enet_mdio_write; 753 fep->mii_bus->reset = fec_enet_mdio_reset; 754 snprintf(fep->mii_bus->id, MII_BUS_ID_SIZE, "%x", pdev->id + 1); 755 fep->mii_bus->priv = fep; 756 fep->mii_bus->parent = &pdev->dev; 757 758 fep->mii_bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL); 759 if (!fep->mii_bus->irq) { 760 err = -ENOMEM; 761 goto err_out_free_mdiobus; 762 } 763 764 for (i = 0; i < PHY_MAX_ADDR; i++) 765 fep->mii_bus->irq[i] = PHY_POLL; 766 767 platform_set_drvdata(dev, fep->mii_bus); 768 769 if (mdiobus_register(fep->mii_bus)) 770 goto err_out_free_mdio_irq; 771 772 return 0; 773 774err_out_free_mdio_irq: 775 kfree(fep->mii_bus->irq); 776err_out_free_mdiobus: 777 mdiobus_free(fep->mii_bus); 778err_out: 779 return err; 780} 781 782static void fec_enet_mii_remove(struct fec_enet_private *fep) 783{ 784 if (fep->phy_dev) 785 phy_disconnect(fep->phy_dev); 786 mdiobus_unregister(fep->mii_bus); 787 kfree(fep->mii_bus->irq); 788 mdiobus_free(fep->mii_bus); 789} 790 791static int fec_enet_get_settings(struct net_device *dev, 792 struct ethtool_cmd *cmd) 793{ 794 struct fec_enet_private *fep = netdev_priv(dev); 795 struct phy_device *phydev = fep->phy_dev; 796 797 if (!phydev) 798 return -ENODEV; 799 800 return phy_ethtool_gset(phydev, cmd); 801} 802 803static int fec_enet_set_settings(struct net_device *dev, 804 struct ethtool_cmd *cmd) 805{ 806 struct fec_enet_private *fep = netdev_priv(dev); 807 struct phy_device *phydev = fep->phy_dev; 808 809 if (!phydev) 810 return -ENODEV; 811 812 return phy_ethtool_sset(phydev, cmd); 813} 814 815static void fec_enet_get_drvinfo(struct net_device *dev, 816 struct ethtool_drvinfo *info) 817{ 818 struct fec_enet_private *fep = netdev_priv(dev); 819 820 strcpy(info->driver, fep->pdev->dev.driver->name); 821 strcpy(info->version, "Revision: 1.0"); 822 strcpy(info->bus_info, dev_name(&dev->dev)); 823} 824 825static struct ethtool_ops fec_enet_ethtool_ops = { 826 .get_settings = fec_enet_get_settings, 827 .set_settings = fec_enet_set_settings, 828 .get_drvinfo = fec_enet_get_drvinfo, 829 .get_link = ethtool_op_get_link, 830}; 831 832static int fec_enet_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 833{ 834 struct fec_enet_private *fep = netdev_priv(dev); 835 struct phy_device *phydev = fep->phy_dev; 836 837 if (!netif_running(dev)) 838 return -EINVAL; 839 840 if (!phydev) 841 return -ENODEV; 842 843 return phy_mii_ioctl(phydev, rq, cmd); 844} 845 846static void fec_enet_free_buffers(struct net_device *dev) 847{ 848 struct fec_enet_private *fep = netdev_priv(dev); 849 int i; 850 struct sk_buff *skb; 851 struct bufdesc *bdp; 852 853 bdp = fep->rx_bd_base; 854 for (i = 0; i < RX_RING_SIZE; i++) { 855 skb = fep->rx_skbuff[i]; 856 857 if (bdp->cbd_bufaddr) 858 dma_unmap_single(&dev->dev, bdp->cbd_bufaddr, 859 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 860 if (skb) 861 dev_kfree_skb(skb); 862 bdp++; 863 } 864 865 bdp = fep->tx_bd_base; 866 for (i = 0; i < TX_RING_SIZE; i++) 867 kfree(fep->tx_bounce[i]); 868} 869 870static int fec_enet_alloc_buffers(struct net_device *dev) 871{ 872 struct fec_enet_private *fep = netdev_priv(dev); 873 int i; 874 struct sk_buff *skb; 875 struct bufdesc *bdp; 876 877 bdp = fep->rx_bd_base; 878 for (i = 0; i < RX_RING_SIZE; i++) { 879 skb = dev_alloc_skb(FEC_ENET_RX_FRSIZE); 880 if (!skb) { 881 fec_enet_free_buffers(dev); 882 return -ENOMEM; 883 } 884 fep->rx_skbuff[i] = skb; 885 886 bdp->cbd_bufaddr = dma_map_single(&dev->dev, skb->data, 887 FEC_ENET_RX_FRSIZE, DMA_FROM_DEVICE); 888 bdp->cbd_sc = BD_ENET_RX_EMPTY; 889 bdp++; 890 } 891 892 /* Set the last buffer to wrap. */ 893 bdp--; 894 bdp->cbd_sc |= BD_SC_WRAP; 895 896 bdp = fep->tx_bd_base; 897 for (i = 0; i < TX_RING_SIZE; i++) { 898 fep->tx_bounce[i] = kmalloc(FEC_ENET_TX_FRSIZE, GFP_KERNEL); 899 900 bdp->cbd_sc = 0; 901 bdp->cbd_bufaddr = 0; 902 bdp++; 903 } 904 905 /* Set the last buffer to wrap. */ 906 bdp--; 907 bdp->cbd_sc |= BD_SC_WRAP; 908 909 return 0; 910} 911 912static int 913fec_enet_open(struct net_device *dev) 914{ 915 struct fec_enet_private *fep = netdev_priv(dev); 916 int ret; 917 918 /* I should reset the ring buffers here, but I don't yet know 919 * a simple way to do that. 920 */ 921 922 ret = fec_enet_alloc_buffers(dev); 923 if (ret) 924 return ret; 925 926 /* Probe and connect to PHY when open the interface */ 927 ret = fec_enet_mii_probe(dev); 928 if (ret) { 929 fec_enet_free_buffers(dev); 930 return ret; 931 } 932 phy_start(fep->phy_dev); 933 netif_start_queue(dev); 934 fep->opened = 1; 935 return 0; 936} 937 938static int 939fec_enet_close(struct net_device *dev) 940{ 941 struct fec_enet_private *fep = netdev_priv(dev); 942 943 /* Don't know what to do yet. */ 944 fep->opened = 0; 945 netif_stop_queue(dev); 946 fec_stop(dev); 947 948 if (fep->phy_dev) 949 phy_disconnect(fep->phy_dev); 950 951 fec_enet_free_buffers(dev); 952 953 return 0; 954} 955 956/* Set or clear the multicast filter for this adaptor. 957 * Skeleton taken from sunlance driver. 958 * The CPM Ethernet implementation allows Multicast as well as individual 959 * MAC address filtering. Some of the drivers check to make sure it is 960 * a group multicast address, and discard those that are not. I guess I 961 * will do the same for now, but just remove the test if you want 962 * individual filtering as well (do the upper net layers want or support 963 * this kind of feature?). 964 */ 965 966#define HASH_BITS 6 /* #bits in hash */ 967#define CRC32_POLY 0xEDB88320 968 969static void set_multicast_list(struct net_device *dev) 970{ 971 struct fec_enet_private *fep = netdev_priv(dev); 972 struct netdev_hw_addr *ha; 973 unsigned int i, bit, data, crc, tmp; 974 unsigned char hash; 975 976 if (dev->flags & IFF_PROMISC) { 977 tmp = readl(fep->hwp + FEC_R_CNTRL); 978 tmp |= 0x8; 979 writel(tmp, fep->hwp + FEC_R_CNTRL); 980 return; 981 } 982 983 tmp = readl(fep->hwp + FEC_R_CNTRL); 984 tmp &= ~0x8; 985 writel(tmp, fep->hwp + FEC_R_CNTRL); 986 987 if (dev->flags & IFF_ALLMULTI) { 988 /* Catch all multicast addresses, so set the 989 * filter to all 1's 990 */ 991 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 992 writel(0xffffffff, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 993 994 return; 995 } 996 997 /* Clear filter and add the addresses in hash register 998 */ 999 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1000 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1001 1002 netdev_for_each_mc_addr(ha, dev) { 1003 /* Only support group multicast for now */ 1004 if (!(ha->addr[0] & 1)) 1005 continue; 1006 1007 /* calculate crc32 value of mac address */ 1008 crc = 0xffffffff; 1009 1010 for (i = 0; i < dev->addr_len; i++) { 1011 data = ha->addr[i]; 1012 for (bit = 0; bit < 8; bit++, data >>= 1) { 1013 crc = (crc >> 1) ^ 1014 (((crc ^ data) & 1) ? CRC32_POLY : 0); 1015 } 1016 } 1017 1018 /* only upper 6 bits (HASH_BITS) are used 1019 * which point to specific bit in he hash registers 1020 */ 1021 hash = (crc >> (32 - HASH_BITS)) & 0x3f; 1022 1023 if (hash > 31) { 1024 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1025 tmp |= 1 << (hash - 32); 1026 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1027 } else { 1028 tmp = readl(fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1029 tmp |= 1 << hash; 1030 writel(tmp, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1031 } 1032 } 1033} 1034 1035/* Set a MAC change in hardware. */ 1036static int 1037fec_set_mac_address(struct net_device *dev, void *p) 1038{ 1039 struct fec_enet_private *fep = netdev_priv(dev); 1040 struct sockaddr *addr = p; 1041 1042 if (!is_valid_ether_addr(addr->sa_data)) 1043 return -EADDRNOTAVAIL; 1044 1045 memcpy(dev->dev_addr, addr->sa_data, dev->addr_len); 1046 1047 writel(dev->dev_addr[3] | (dev->dev_addr[2] << 8) | 1048 (dev->dev_addr[1] << 16) | (dev->dev_addr[0] << 24), 1049 fep->hwp + FEC_ADDR_LOW); 1050 writel((dev->dev_addr[5] << 16) | (dev->dev_addr[4] << 24), 1051 fep->hwp + FEC_ADDR_HIGH); 1052 return 0; 1053} 1054 1055static const struct net_device_ops fec_netdev_ops = { 1056 .ndo_open = fec_enet_open, 1057 .ndo_stop = fec_enet_close, 1058 .ndo_start_xmit = fec_enet_start_xmit, 1059 .ndo_set_multicast_list = set_multicast_list, 1060 .ndo_change_mtu = eth_change_mtu, 1061 .ndo_validate_addr = eth_validate_addr, 1062 .ndo_tx_timeout = fec_timeout, 1063 .ndo_set_mac_address = fec_set_mac_address, 1064 .ndo_do_ioctl = fec_enet_ioctl, 1065}; 1066 1067static int fec_enet_init(struct net_device *dev, int index) 1068{ 1069 struct fec_enet_private *fep = netdev_priv(dev); 1070 struct bufdesc *cbd_base; 1071 struct bufdesc *bdp; 1072 int i; 1073 1074 /* Allocate memory for buffer descriptors. */ 1075 cbd_base = dma_alloc_coherent(NULL, PAGE_SIZE, &fep->bd_dma, 1076 GFP_KERNEL); 1077 if (!cbd_base) { 1078 printk("FEC: allocate descriptor memory failed?\n"); 1079 return -ENOMEM; 1080 } 1081 1082 spin_lock_init(&fep->hw_lock); 1083 1084 fep->index = index; 1085 fep->hwp = (void __iomem *)dev->base_addr; 1086 fep->netdev = dev; 1087 1088 /* Set the Ethernet address */ 1089#ifdef CONFIG_M5272 1090 fec_get_mac(dev); 1091#else 1092 { 1093 unsigned long l; 1094 l = readl(fep->hwp + FEC_ADDR_LOW); 1095 dev->dev_addr[0] = (unsigned char)((l & 0xFF000000) >> 24); 1096 dev->dev_addr[1] = (unsigned char)((l & 0x00FF0000) >> 16); 1097 dev->dev_addr[2] = (unsigned char)((l & 0x0000FF00) >> 8); 1098 dev->dev_addr[3] = (unsigned char)((l & 0x000000FF) >> 0); 1099 l = readl(fep->hwp + FEC_ADDR_HIGH); 1100 dev->dev_addr[4] = (unsigned char)((l & 0xFF000000) >> 24); 1101 dev->dev_addr[5] = (unsigned char)((l & 0x00FF0000) >> 16); 1102 } 1103#endif 1104 1105 /* Set receive and transmit descriptor base. */ 1106 fep->rx_bd_base = cbd_base; 1107 fep->tx_bd_base = cbd_base + RX_RING_SIZE; 1108 1109 /* The FEC Ethernet specific entries in the device structure */ 1110 dev->watchdog_timeo = TX_TIMEOUT; 1111 dev->netdev_ops = &fec_netdev_ops; 1112 dev->ethtool_ops = &fec_enet_ethtool_ops; 1113 1114 /* Initialize the receive buffer descriptors. */ 1115 bdp = fep->rx_bd_base; 1116 for (i = 0; i < RX_RING_SIZE; i++) { 1117 1118 /* Initialize the BD for every fragment in the page. */ 1119 bdp->cbd_sc = 0; 1120 bdp++; 1121 } 1122 1123 /* Set the last buffer to wrap */ 1124 bdp--; 1125 bdp->cbd_sc |= BD_SC_WRAP; 1126 1127 /* ...and the same for transmit */ 1128 bdp = fep->tx_bd_base; 1129 for (i = 0; i < TX_RING_SIZE; i++) { 1130 1131 /* Initialize the BD for every fragment in the page. */ 1132 bdp->cbd_sc = 0; 1133 bdp->cbd_bufaddr = 0; 1134 bdp++; 1135 } 1136 1137 /* Set the last buffer to wrap */ 1138 bdp--; 1139 bdp->cbd_sc |= BD_SC_WRAP; 1140 1141 fec_restart(dev, 0); 1142 1143 return 0; 1144} 1145 1146/* This function is called to start or restart the FEC during a link 1147 * change. This only happens when switching between half and full 1148 * duplex. 1149 */ 1150static void 1151fec_restart(struct net_device *dev, int duplex) 1152{ 1153 struct fec_enet_private *fep = netdev_priv(dev); 1154 int i; 1155 1156 /* Whack a reset. We should wait for this. */ 1157 writel(1, fep->hwp + FEC_ECNTRL); 1158 udelay(10); 1159 1160 /* Clear any outstanding interrupt. */ 1161 writel(0xffc00000, fep->hwp + FEC_IEVENT); 1162 1163 /* Reset all multicast. */ 1164 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_HIGH); 1165 writel(0, fep->hwp + FEC_GRP_HASH_TABLE_LOW); 1166#ifndef CONFIG_M5272 1167 writel(0, fep->hwp + FEC_HASH_TABLE_HIGH); 1168 writel(0, fep->hwp + FEC_HASH_TABLE_LOW); 1169#endif 1170 1171 /* Set maximum receive buffer size. */ 1172 writel(PKT_MAXBLR_SIZE, fep->hwp + FEC_R_BUFF_SIZE); 1173 1174 /* Set receive and transmit descriptor base. */ 1175 writel(fep->bd_dma, fep->hwp + FEC_R_DES_START); 1176 writel((unsigned long)fep->bd_dma + sizeof(struct bufdesc) * RX_RING_SIZE, 1177 fep->hwp + FEC_X_DES_START); 1178 1179 fep->dirty_tx = fep->cur_tx = fep->tx_bd_base; 1180 fep->cur_rx = fep->rx_bd_base; 1181 1182 /* Reset SKB transmit buffers. */ 1183 fep->skb_cur = fep->skb_dirty = 0; 1184 for (i = 0; i <= TX_RING_MOD_MASK; i++) { 1185 if (fep->tx_skbuff[i]) { 1186 dev_kfree_skb_any(fep->tx_skbuff[i]); 1187 fep->tx_skbuff[i] = NULL; 1188 } 1189 } 1190 1191 /* Enable MII mode */ 1192 if (duplex) { 1193 /* MII enable / FD enable */ 1194 writel(OPT_FRAME_SIZE | 0x04, fep->hwp + FEC_R_CNTRL); 1195 writel(0x04, fep->hwp + FEC_X_CNTRL); 1196 } else { 1197 /* MII enable / No Rcv on Xmit */ 1198 writel(OPT_FRAME_SIZE | 0x06, fep->hwp + FEC_R_CNTRL); 1199 writel(0x0, fep->hwp + FEC_X_CNTRL); 1200 } 1201 fep->full_duplex = duplex; 1202 1203 /* Set MII speed */ 1204 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1205 1206#ifdef FEC_MIIGSK_ENR 1207 if (fep->phy_interface == PHY_INTERFACE_MODE_RMII) { 1208 /* disable the gasket and wait */ 1209 writel(0, fep->hwp + FEC_MIIGSK_ENR); 1210 while (readl(fep->hwp + FEC_MIIGSK_ENR) & 4) 1211 udelay(1); 1212 1213 /* configure the gasket: RMII, 50 MHz, no loopback, no echo */ 1214 writel(1, fep->hwp + FEC_MIIGSK_CFGR); 1215 1216 /* re-enable the gasket */ 1217 writel(2, fep->hwp + FEC_MIIGSK_ENR); 1218 } 1219#endif 1220 1221 /* And last, enable the transmit and receive processing */ 1222 writel(2, fep->hwp + FEC_ECNTRL); 1223 writel(0, fep->hwp + FEC_R_DES_ACTIVE); 1224 1225 /* Enable interrupts we wish to service */ 1226 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1227} 1228 1229static void 1230fec_stop(struct net_device *dev) 1231{ 1232 struct fec_enet_private *fep = netdev_priv(dev); 1233 1234 /* We cannot expect a graceful transmit stop without link !!! */ 1235 if (fep->link) { 1236 writel(1, fep->hwp + FEC_X_CNTRL); /* Graceful transmit stop */ 1237 udelay(10); 1238 if (!(readl(fep->hwp + FEC_IEVENT) & FEC_ENET_GRA)) 1239 printk("fec_stop : Graceful transmit stop did not complete !\n"); 1240 } 1241 1242 /* Whack a reset. We should wait for this. */ 1243 writel(1, fep->hwp + FEC_ECNTRL); 1244 udelay(10); 1245 writel(fep->phy_speed, fep->hwp + FEC_MII_SPEED); 1246 writel(FEC_DEFAULT_IMASK, fep->hwp + FEC_IMASK); 1247} 1248 1249static int __devinit 1250fec_probe(struct platform_device *pdev) 1251{ 1252 struct fec_enet_private *fep; 1253 struct fec_platform_data *pdata; 1254 struct net_device *ndev; 1255 int i, irq, ret = 0; 1256 struct resource *r; 1257 1258 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1259 if (!r) 1260 return -ENXIO; 1261 1262 r = request_mem_region(r->start, resource_size(r), pdev->name); 1263 if (!r) 1264 return -EBUSY; 1265 1266 /* Init network device */ 1267 ndev = alloc_etherdev(sizeof(struct fec_enet_private)); 1268 if (!ndev) 1269 return -ENOMEM; 1270 1271 SET_NETDEV_DEV(ndev, &pdev->dev); 1272 1273 /* setup board info structure */ 1274 fep = netdev_priv(ndev); 1275 memset(fep, 0, sizeof(*fep)); 1276 1277 ndev->base_addr = (unsigned long)ioremap(r->start, resource_size(r)); 1278 fep->pdev = pdev; 1279 1280 if (!ndev->base_addr) { 1281 ret = -ENOMEM; 1282 goto failed_ioremap; 1283 } 1284 1285 platform_set_drvdata(pdev, ndev); 1286 1287 pdata = pdev->dev.platform_data; 1288 if (pdata) 1289 fep->phy_interface = pdata->phy; 1290 1291 /* This device has up to three irqs on some platforms */ 1292 for (i = 0; i < 3; i++) { 1293 irq = platform_get_irq(pdev, i); 1294 if (i && irq < 0) 1295 break; 1296 ret = request_irq(irq, fec_enet_interrupt, IRQF_DISABLED, pdev->name, ndev); 1297 if (ret) { 1298 while (i >= 0) { 1299 irq = platform_get_irq(pdev, i); 1300 free_irq(irq, ndev); 1301 i--; 1302 } 1303 goto failed_irq; 1304 } 1305 } 1306 1307 fep->clk = clk_get(&pdev->dev, "fec_clk"); 1308 if (IS_ERR(fep->clk)) { 1309 ret = PTR_ERR(fep->clk); 1310 goto failed_clk; 1311 } 1312 clk_enable(fep->clk); 1313 1314 ret = fec_enet_init(ndev, 0); 1315 if (ret) 1316 goto failed_init; 1317 1318 ret = fec_enet_mii_init(pdev); 1319 if (ret) 1320 goto failed_mii_init; 1321 1322 /* Carrier starts down, phylib will bring it up */ 1323 netif_carrier_off(ndev); 1324 1325 ret = register_netdev(ndev); 1326 if (ret) 1327 goto failed_register; 1328 1329 return 0; 1330 1331failed_register: 1332 fec_enet_mii_remove(fep); 1333failed_mii_init: 1334failed_init: 1335 clk_disable(fep->clk); 1336 clk_put(fep->clk); 1337failed_clk: 1338 for (i = 0; i < 3; i++) { 1339 irq = platform_get_irq(pdev, i); 1340 if (irq > 0) 1341 free_irq(irq, ndev); 1342 } 1343failed_irq: 1344 iounmap((void __iomem *)ndev->base_addr); 1345failed_ioremap: 1346 free_netdev(ndev); 1347 1348 return ret; 1349} 1350 1351static int __devexit 1352fec_drv_remove(struct platform_device *pdev) 1353{ 1354 struct net_device *ndev = platform_get_drvdata(pdev); 1355 struct fec_enet_private *fep = netdev_priv(ndev); 1356 1357 platform_set_drvdata(pdev, NULL); 1358 1359 fec_stop(ndev); 1360 fec_enet_mii_remove(fep); 1361 clk_disable(fep->clk); 1362 clk_put(fep->clk); 1363 iounmap((void __iomem *)ndev->base_addr); 1364 unregister_netdev(ndev); 1365 free_netdev(ndev); 1366 return 0; 1367} 1368 1369#ifdef CONFIG_PM 1370static int 1371fec_suspend(struct device *dev) 1372{ 1373 struct net_device *ndev = dev_get_drvdata(dev); 1374 struct fec_enet_private *fep; 1375 1376 if (ndev) { 1377 fep = netdev_priv(ndev); 1378 if (netif_running(ndev)) 1379 fec_enet_close(ndev); 1380 clk_disable(fep->clk); 1381 } 1382 return 0; 1383} 1384 1385static int 1386fec_resume(struct device *dev) 1387{ 1388 struct net_device *ndev = dev_get_drvdata(dev); 1389 struct fec_enet_private *fep; 1390 1391 if (ndev) { 1392 fep = netdev_priv(ndev); 1393 clk_enable(fep->clk); 1394 if (netif_running(ndev)) 1395 fec_enet_open(ndev); 1396 } 1397 return 0; 1398} 1399 1400static const struct dev_pm_ops fec_pm_ops = { 1401 .suspend = fec_suspend, 1402 .resume = fec_resume, 1403 .freeze = fec_suspend, 1404 .thaw = fec_resume, 1405 .poweroff = fec_suspend, 1406 .restore = fec_resume, 1407}; 1408#endif 1409 1410static struct platform_driver fec_driver = { 1411 .driver = { 1412 .name = "fec", 1413 .owner = THIS_MODULE, 1414#ifdef CONFIG_PM 1415 .pm = &fec_pm_ops, 1416#endif 1417 }, 1418 .probe = fec_probe, 1419 .remove = __devexit_p(fec_drv_remove), 1420}; 1421 1422static int __init 1423fec_enet_module_init(void) 1424{ 1425 printk(KERN_INFO "FEC Ethernet Driver\n"); 1426 1427 return platform_driver_register(&fec_driver); 1428} 1429 1430static void __exit 1431fec_enet_cleanup(void) 1432{ 1433 platform_driver_unregister(&fec_driver); 1434} 1435 1436module_exit(fec_enet_cleanup); 1437module_init(fec_enet_module_init); 1438 1439MODULE_LICENSE("GPL"); 1440